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Document Revision: 1.01 Date: 3rd April, 2005
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cost. weight. displays.Overview Micro-controllers are useful to the extent that they communicate with other devices. availability. reliability. size. manufacturability. Many microcontroller designs typically mix multiple interfacing methods. Microwire) Page 2 . keypads. such as sensors. In a very simplistic form. memory and even other micro-controllers. motors. performs processing and writes to ( controls ) outputs. Many interface methods have been developed over the years to solve the complex problem of balancing circuit design criteria such as features. Input Devices Microcontroller Output Devices Microcontroller Interfaces Digital Analog On/Off Parallel Serial Voltage Current Asynchronous 1-wire RS232/RS485 Ethernet Synchronous 2-wire (I2C) 4-wire (SPI. power consumption. switches. a micro-controller system can be viewed as a system that reads from (monitors) inputs.
1 P2. few feet maximum.1 P2. Single device control/monitoring Digital Input Example: Reading the status of buttons or switches Single-ended (non-matrix) switches P2.4 P2.6 Columns Columns P2.5 8051 Microcontroller (AT89C51ED2) P2.2 P2.6 P2.2 P2.0 Digital Input Example: Keypad Interface 4X4 Matrix Keypad Interface P2.4 P2.5 8051 Microcontroller (AT89C51ED2) Rows 1 P2.Digital Inputs/Outputs On/OFF control and monitoring.0 2 5 8 0 3 6 9 # A B C D 4 7 * Rows Page 3 .3 P2.7 P2.7 P2.3 P2. Advantages • • • • Simplest interface Lowest-cost to implement (built into the microcontroller) High speed Low programming overhead • • • Disadvantages Only on/off control/monitoring Short distance.
1 P0.2 P0.Digital Output Example: LED control VCC LED Interface Current Limiting Resistors 8051 Microcontroller (AT89C51ED2) LED's P0.4 Page 4 .3 P0.0 Digital Output Example: Relay control VCC Relay Interface 8051 Microcontroller (AT89C51ED2) 7407 P1.
Voltage type: Typical ranges • • • • • • 0 to 2.Analog Inputs/Outputs Voltage-based control and monitoring. Short distance.5V +/. Disadvantages • • • • Advantages Simple interface Low cost for low-resolutions High speed Low programming overhead • • • • High cost for higher resolutions Not all microcontrollers have analog inputs/outputs built-in Complicates the circuit design when external ADC or DAC are needed.4V +/.2.5V 0 to 4V 0 to 5V +/.5V Current type: Typical ranges • • 0-20mA 4-20mA Analog Interface Vcc Amplifier Potentiometer LM35 Temperature Sensor Vcc Vcc Analog/ Digital Converter (ADC) 8051 Microcontroller (AT89C51ED2) Digital/ Analog Converter (DAC) Strain-gage 4-20mA Output Page 5 . few feet maximum.
g.0 D7 D6 D5 D4 D3 D2 D1 D0 E R/W RS Hello World 8-bit LCD Interface Alphanumeric LCD 8051 Microcontroller (AT89C51ED2) P0.g.5 P0.2 P2.4 P0. Most common types: • • • • 4-bit 8-bit ( e.2 P0.1 P0. Centronics ) 16-bit ( e.0 P2.g.3 P0.5 P0.6 P0.2 P0. ISA ) 32-bit ( e.0 D7 D6 D5 D4 D3 D2 D1 D0 E R/W RS Hello World Page 6 .1 P0.7 P0.7 P0.6 P0.4 P0. PCI ) Disadvantages • Large number of microcontroller pins that needed for implementing the parallel bus • • • Advantages High speed High throughput: Several bits are transmitted on one clock transition Low cost Example: LCD Interface 4-bit LCD Interface Alphanumeric LCD 8051 Microcontroller (AT89C51ED2) P0.Parallel Bus Consists of multiple digital inputs/outputs.1 P2.
SDA is always bi-directional. Typical device capacitance is 10 pF. SCL is bidirectional only in multi-master mode. the bus master (typically a microcontroller) places the address of the device with which it intends to communicate (the slave) on the bus. Advantages Multiple slave devices can be accessed with only 3 wires Low-cost to implement Implemented in hardware or software Ease to implement. Originated by Philips Semiconductor in the early 80’s to connect a microcontroller to peripheral devices in TV sets.Serial Buses I2C ( Inter Integrated Circuit bus ) 2-wire interface with one master and multiple slaves ( multi-master configurations possible ). Maximum allowable capacitance on the lines is 400 pF. Only the device with the correct address communicates with the master.2K 2.7) SCL (P1. To start the communications. I2C is 5V. CLOCK (SCL) and Ground. many examples Supports multi-master configuration Disadvantages • • • Short distance Slow speed: 100 KHz although 400 KHz and 1 MHz slave devise exist. By definition. All slave devices monitor the bus to determine if the master device is sending their address.6) SDA AT24C04 SCL EEPROM 8051 Microcontroller (AT89C51ED2) SCL SDA A0 A1 A2 Lithium Battery DS1307 Real-Time Clock Crystal Page 7 .2K SDA (P1. These can not coexist with slower devices. Signals: DATA (SDA). Limited device addresses • • • • • 2-wire (I2C) interface VCC 2.
Start and Stop An I2C master prepares to communicate with a slave device first by generating a Start condition on the bus. Data should remain stable while the clock is going high. Start condition is defined as SDA signal going low while SCL signal is high. Data Validity Data can change while the clock is low. Stop condition is defined as SDA going high while SCL is high. Acknowledge (ACK) Page 8 .
Writing a byte to a serial EEPROM (24C04 ) on the I2C bus: where Device Address is defined as P0. P2 indicate the page number ( 2Kbit pages ). A2 indicate the device number on the bus. P1. A0. A1. Reading a byte from a serial EEPROM (24C04 ) on the I2C bus ( starting from the current address ) Example: Page 9 .
SPI is full duplex: Data is simultaneously transmitted and received. many examples Can be high speed ( e.3 P3. Advantages • • • • • Multiple slave devices can be accessed with only few wires Low-cost Implemented in hardware or software Ease to implement. one is referred to as the "master" and the other as the "slave" device.4 CLK 8051 Microcontroller (AT89C51ED2) Multimedia Card MMC Page 10 .5 P3. 4MHz or higher if implemented in hardware ) • • Disadvantages Short distance Data and clock lines can be shared but each device requires a separate Chip Select signal.7 CS DIN DOUT P3. CS ( Chip Select ) Originated by Motorola.g.SPI ( Serial Peripheral Interface ) 4-wire interface with one master and multiple slaves. Signals: DATA IN. limiting the number of devices in limited I/O systems Example: Multimedia Card ( MMC ) Interface using SPI MMC Interface P3. DATA OUT. SPI bus is a master/slave interface. A synchronous clock shifts serial data into and out of the microcontrollers in blocks of 8 bits. SPI bus is a relatively simple synchronous serial interface for connecting low speed external devices using minimal number of wires. The master drives the serial clock. Whenever two devices communicate. CLOCK.
and memory chips from a single wire interface ( DATA and Ground ).com/applications/ds18xx_app. The system is sensitive to the right timing to operate well. Usually the network is built using a wire pair where one wire carries the signal and power and the other wire is ground. Advantages Multiple slave devices can be accessed with only 2 wires Low-cost Implemented in hardware or software Ease to implement. many examples Relatively long distance.bipom.pdf Page 11 .1-wire Originated by Dallas Semiconductor ( now part of MAXIM ) to address a variety of peripherals. Theoretically 300 meters but this is limited in practice due to noise and cable capacitance Disadvantages • • Slow speed 1-wire slave devices typically has to come from one source: Dallas Semiconductor For more information on the 1-wire bus. sensors. One signal wire carries both operating power and signal. please refer to BiPOM Application Note: Temperature Measurements with 1-Wire Bus Sensors http://www.
many examples • • • • Disadvantages More suitable for system to system communications. 115200 baud can be achieved with small microcontrollers using short distances Requires transceiver chips which add to system cost ( TTL/CMOS level RS232 can be used without transceiver chips ). not so much for chip to chip or chip to sensor Low speed for long distance. 50 feet maximum for low baud rates although longer distances work in practice. Single master/single slave Page 12 . with low baud rates and error correction Immune to noise due to +/-5 Volts or higher voltage levels for logic “0” and “1” Implemented in hardware or software Ease to implement.RS232 Asynchronous communications Advantages • • • • • • Popular interface with many examples Many compatible legacy devices Relatively long distance.
but not at the same time. thousands of feet Immune to noise due to differential voltage Implemented in hardware or software Ease to implement. Page 13 . Otherwise. many examples Widely used in industrial automation Higher speeds beyond 115200 baud • • Disadvantages More suitable for system to system communications. Correct termination resistor that matches the characteristic impedance of the cable is very important in RS485. RS485 Network Topology: Any station can communicate with any other station. not so much for chip to chip or chip to sensor Requires transceiver chips and twisted pair cable with terminating resistors which add to system cost. reflected waves will result in distortions of the original waveform to the point where data errors occur.RS485 Asynchronous communications Advantages • • • • • • • Popular interface with many examples Very long distance.
jack and special cabling that add to system cost. hundreds of feet can be achieved. Complicated to implement High code footprint Page 14 . transformer. more with hubs and switches Immune to noise Widely used in industrial automation due to noise immunity Disadvantages • • • • • Cost More suitable for system to system communications. not so much for chip to chip/sensor Requires Ethernet chipset.Ethernet Advantages • • • • Very high speed ( 10Mbit to 100Mbit/s ) Very long distance.
1.5V.maxim-ic.1V Transmission LS bit first.5V. driver specification MS bit first. resistive open drain. 27. HighSpeed: ~0 to 3. including 2 parity 29 bits (extended bits format) N/A. check sum.8 to 6. Power. CAN_L. multiple slaves 4. 2. bits.8V. DO. frames Yes. VDD (exception) N/A. 2. halfduplex. 180nF M to S: voltage drive S to M: current load ~40V Master to slave: 24V. multiple slaves 1 (LIN) N/A Up to 40m. (SCL. >2. DI.7V to 5.com ) 1-Wire Network Concept Number of Signal Lines Optional signals Network Size single master. 400pF bus capacitance requirement 4. message-based protocol. resistive or active master pull-up From 2.5V (dominant). ~4.7ms (standard) or 39µs from start of frame to (extended) from start 1st data bit of frame to 1st data bit 15-bit CRC. >11mA LS bit first.5ms (long frame) Even parity.4ms Overdrive: ~0. slave addresses hardcoded in firmware Standard: ~0 to 100k bps. device specific I C* multiple masters. 36V nominalSlave to master: <1. half-duplex 7 bits. single master. max.1. fullAcknowledge bit. SO. multiple slaves 2. device specific Fixed level: >1. SMBDAT) SMBSUS#.8V.8 to 5.0 V.Appendix A: Comparison of Serial Digital Data Networks ( from MAXIM website: www. not address based Network Inventory Automatic. half-duplex N/A (circuit board N/A (circuit board level) level) Network Interface Network Voltage open drain. device specific VDD-related level: <20% (30%).) LS bit first. 10nF total load open drain.0 only) N/A Address Format 56 bits N/A Message identifier 11 Message identifier 8 bits (standard format). 2. frames. (CS\. (CS\.3k bps Overdrive: ~0 to 142k bps) Standard: ~ 5. slaves multiple slaves 2 (lines can be swapped) N/A Max. frame acknowledge Yes: CSMA/CD VDD only. slave select (CS\) (CS\) hard-coded hard-coded in firmware in firmware Automatic Gross Data Rate 10k to 100k bps ~0 to ~10 M bps (device specific) ~0 to ~5 M bps (device specific) 300. 9600 bps ~0 to 1M bps ~1k to ~20k bps Access Time Standard: ~95µsFast: ~95µs @ 100k ~23µs(at maximum bps speed) N/A Yes (multi-master operation only) VDD only PEC Packet Error Code (Rev. terminated) 2nd GND. duplex half-duplex 7 bits. 250 slaves. through check sum Parasitic only Data Protection Collision Detection Slave supply N/A N/A VDD only N/A N/A VDD only .4M bps 2. SK) N/A M-Bus (EN1434) CAN (ISO11898) LIN Bus single master. (10 bits defined but not implemented) N/A. slave select N/A. (10 bits defined but not implemented) ARP. device specific Fixed level: <0./emitter VDD-VD (diode drop). multiple multiple masters.8V to 5. through nonmatching CRC Parasitic (typical). Shield 40m @1M bps1000m @ 50k bps (example) Differential open drain/source or open coll. SMBALERT# Limited by max. multiple slaves multiple slaves 2.5V From 1.0 V VDD-related level: <30%. acknowledge response 8 bits (primary address).0) Yes (Rev. >70% of VDD MS bit first plus Acknowledge bit. supports dynamic topology change Standard: ~0 to 16. halfduplex multiple masters.5V max. >3. Push-pull with or active master resistive or active tristate pull-up master pull-up From 1. Fast: ~0 to 400k bps. local or remote source Check sum. Differential: <50mV (recessive). message-based protocol. (SMBCLK. 2400. 350m per segment of max. max. multiple slaves 1 (IO) N/A Up to 300 m (with suitable master circuit) open drain. >2.8V to 5. >70% of VDD (inconsistent) Push-pull with tristate From 1. >70% (80%) of VDD (inconsistent) MS bit first.0V.75ms (short frame). SI.0 only) VDD only N/A N/A Primary address.5V. 2400 bps: 13. SCK) N/A single master. resistive master pull-up 8 to 18V VDD-related level: <20%. VDD-related level: <20% (30%). halfduplex MS bit first plus MS bit first.6ms (at maximum speed) 8-bit and 16-bit CRC Yes. full-duplex Logic Thresholds Vary with network voltage <0.5mA. 400pF bus capacitance requirement 2 SMBUS™ SPI™ MicroWire/PLUS™ single master. >80% of VDD (driver spec. >60% of VDD (receiver spec. not address based N/A. 64 bits (secondary address) 2 (CAN_H. >1. Address Resolution Protocol (Rev. frames Yes ("medium" and "strong" collisions) Parasitic and/or local supply At 1M bps 19µs At 20k bps 1.)<40%.5V. SDA) N/A Limited by max.