This action might not be possible to undo. Are you sure you want to continue?
The bottom-up design flow for a transistor-level circuit layout always starts with a set of design specifications. The "specs" typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. Note that the limitations spelled out in the initial design specs typically require certain design trade-offs, such as increasing the dimensions of the transistors in order to reduce the delay times. In a large-scale design, the initial design specifications may also evolve during the design process to accomodate other specs or limitations. This implies that the designer(s) of individual blocks or modules must communicate clearly and frequently about the spec updates, in order to avoid later inconsistencies. As an example, the initial design specs of a one-bit binary full adder circuit are listed below:
y y y y y
Technology: 0.8 um twin-well CMOS Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case) Transition times of "sum" and "carry_out" signals <1.2 ns (worst case) Circuit area < 1500 um^2 Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1 mW
It can be seen that one can design a number of different adders (with different topologies, different maximum delays, different total silicon areas, etc.), all of which essentially conform to the specs listed above. This indicates that the starting point of a typical bottom-up design process usually leaves the designer a considerable amount of design freedom.
Please follow the example link (button) for a detailed description of "Schematic Capture". The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design. The resulting schematic drawing must accurately describe the main electrical properties of all components and their interconnections. Also included in the schematic are the power supply and ground connections, as well as all "pins" for the input and output signals of your circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the transistorlevel design flow. Usually, some properties of the components (e.g. transistor dimensions) and/or the interconnections between the devices are subsequently modified as a result of iterative optimization steps. These later modifications and improvements on the circuit structure must also be accurately reflected in the most current version of the corresponding schematic.
Click File on the menu banner in the Library Manager and hold the left mouse button until you choose New and then Cellview. so we type "inverter" in the Cell Name field. There are four main fields in the Create New File window : y Library Name You have to choose your working directory by clicking and holding the left mouse button on the Library field. In our example. "tutorial". A small new window called "Create New File" appears.Example : Schematic Capture (CMOS Inverter) Step 1 : Open a new schematic window Note : Before you begin with going through this example. Since our library name is "tutorial" in this example. . 2. we will draw the schematic of an inverter. be sure that you have the Library Manager open. y Cell Name Enter the name of your cell for which you will draw the schematic. 1. we choose the corresponding label.
you will see the available tools. Composer Schematic : Schematic editor Composer Symbol Virtuoso Layout : Symbol editor : Layout editor Since we will draw a schematic. we choose "Composer Schematic". you have to select the design editing tool that you will use to enter your design. the correct view name choice is "schematic" for our example. Since we will draw the schematic of an inverter. You can determine that you are going to draw either a symbol or a schematic or a layout in this field just by typing the corresponding view name. . y Tool Here. Choosing Composer Schematic automatically converts the View Name to schematic. If you click and hold the left mouse button on the tool field. Actually. The tool depends on the hierarchy level of your design.y View Name The View Name indicates the level of the design hierarchy. Only three of these tools will be used for all the examples. the selected tool converts the View Name to the corresponding one.
3. Now. click on "OK" to close this window and open the new schematic editor window chosen in the "Create New File" window. .
which enables the designer to browse easily through the available libraries and select the desired components. Cell Name and the View Name of the component to be added to the schematic. you should have an empty schematic editor window open. . 1. click on Add in the menu banner of the schematic entry window and choose Component. ( Add --> Component ) 2. The components we need for a schematic of an inverter are the following : y y y y PMOS : p-type MOSFET NMOS : n-type MOSFET VDD : Power supply voltage GND : Ground line To add components. The first thing to do is to add and place components which will be used in the schematic. where you can enter the Library Name.Example : Schematic Capture (CMOS Inverter) Step 2 : Add components Note : At this point. One of them is "Add Component Window". Two new pop-up windows appear. as shown below. The other window is the "Component Browser".
The correct library is "NCSU_Analog_Parts". If you move the mouse cursor on the schematic window. you decide where to put this transistor. Each of them is named depending on the components they include. to pick up an n-type MOSFET. 3. Click on a location in the schematic window. where you want to put the transistor. You must be careful to pick up the components from the correct library. you will see a bright NMOS transistor symbol moving with the mouse pointer showing the gate terminal of the transistor. you have open the "N_Transistors" folder by clicking once on it. so. Please refer to the images below to see the difference between a "to be placed" transistor (left image) and "a placed transistor" (right image). At this point. which is a model for a three terminal n-type MOSFET. So.Component Browser pops up every time the Browse button on the Add Component window is clicked. The new folder contains many symbols which are also shown in the picture below. select this library if it is not selected when you opened the Component Browser. We begin picking up the components by selecting the MOS transistors from the Component Browser window. There are many folders under this library. . Pick up the NMOS transistor by clicking once on "nmos". After all. You can change the component library simply by clicking and holding the left mouse button on the library field. the window should appear like shown above.
. The only difference is to pick "pmos" from the "P-Transistors" folder in the Component Browser. The differences between the PMOS symbol and the NMOS symbol are: y There is a tiny circle at the gate terminal of PMOS transistors. Note : Always make sure that you are not confusing a PMOS transistor with an NMOS transistor.The same procedure can be applied to select and to place the PMOS transistor. The "select-and-place" procedure for PMOS is summarized below.
.y The direction of the arrow which always marks the source terminal of the transistor is different. The arrow points from the source terminal towards the transistor in the PMOS symbol. while it points out towards the source terminal in the NMOS symbol.
move the mouse on the schematic window and place the component by clicking a location in that window. Let's assume that we take "vdd" first. Click on the folder "Supply_Nets". The individual steps of this procedure are described in the images below. y y Choose Add and then Component on the menu banner if you somehow closed the Component Browser window.Example : Schematic Capture (CMOS Inverter) Step 3 : Placing supply voltage components 1. so. click on "vdd". so that you will access the components in this folder. y We will put the components "vdd" and "gnd" in our schematic. Picking up the supply voltage components involves the same steps as in adding transistors to the schematic. . You can pick up one of them simply by clicking on the corresponding one.
. Press "ESCAPE" (ESC) key on the keyboard to close the Component Browser and Add Component windows. At this point. 3. we are finished with selecting and placing the necessary components.2. You can follow similar steps for placing the "gnd" component.
We begin to wire the components by connecting VDD and the source terminal of the PMOS transistor. we use wires by choosing Add and then Wire (narrow) on the menu banner.Example : Schematic Capture (CMOS Inverter) Step 4 : Wire components (making connections) 1. 2. . Every component has tiny red squares on its terminals where you can do the wiring. ( Add --> Wire (narrow) ) This command initiates the wiring mode. A new window called Add Wire will pop-up. In this window you can change the routing method and the draw mode. they should be connected according to the function they realize. Connecting any two nets in the schematic is done by first clicking at one of the nets and then at the other one. After all the components are placed. To connect the components in a schematic. 3.
During these steps. One end of the wire is now fixed. The new prompt is the following : Point at ending point for the router 3. you will always be prompted by the schematic window. Click on the target net which is the source terminal of the PMOS transistor . The message appears in the bottom most field of the schematic window. you can easily complete your job. If you follow the instructions prompted in that field. we click first at the center of the red square which corresponds to the VDD net. In this step. . and you will realize that the other end floats and moves according to the mouse pointer. You will also see that the nearest net to the floating end of the wire is automatically highlighted. the following phrase will be prompted : Point at the starting point for the router Since we begin with wiring the VDD and the source of PMOS.
As long as you are in the wiring mode. Click on the drain terminal of NMOS. The remaining steps are summarized below. You will be in this mode. as described above. Click on the gate terminal of NMOS. you will be prompted about the next step you have to do. y Click on the drain terminal of PMOS. wire them together just by clicking first one of them and then the other. 4. In the wiring mode. The same procedure can be applied for the rest of the nodes.This was the final step of connecting the two nodes. y Click on the gate terminal of PMOS. first choose any two nodes which should be connected. Then. to leave the wiring mode. as long as you don't press ESC or choose another command from the menu. . Press ESC on the keyboard.
y Click on the GND node. Your schematic should look like the schematic shown in the image below. Press ESC key to leave the wiring mode. Click on the source terminal of NMOS. 5. .
2. The selected component should be highlighted by a bright rectangle (box) around it. You can (and usually should) modify component properties according to your design specifications. Select the PMOS transistor by clicking on it . Edit the properties by clicking on the corresponding field. you will change only the Width value.Example : Schematic Capture (CMOS Inverter) Step 5 : Edit properties of components The components you select and place from the library always come with a set of default parameters or properties. which stands for the channel width. You may change the values for Width or Length depending on your design specifications. Here are the steps to edit component properties in the schematic window. 3. A larger window with many editable fields appears which is called the Edit Object Properties window. Usually. The . Choose Properties and then Object from the Edit menu. W. 1.
Then enter a new value which is either a result of your calculations or just an initial value to see how the performance changes depending on this variable. click on the Width field.default values for these properties are the smallest available values which are determined by the current technology. To edit the channel width of the transistor.2 um (micrometers). 4. Click OK after editing the properties in the Edit Object Properties Window. The channel width is changed to 1200 nm (nanometers) which is equal to 1. you have pay attention to the unit you use (click here for the list of units). While changing a parameter. .
You can easily observe the changes of these properties that are listed near the corresponding transistor in the schematic. . dimensions) always appear in the schematic window.The most important parameters (type.
Enter the name of your input pin in the Pin Names field. only putting space between them. 1. In this case. We will only use an input pin and an output pin in our inverter schematic. The input name in this example is "Inp" (note that the pin names can be completely arbitrary). Since the input is the gate terminals of both transistors. you have your input pin with the name "Inp" floating in the schematic window. As long as you enter pins of the same direction. The Add Pins window appears. Move the mouse cursor on the schematic window to place pin. . Also. A pin can be an input or an output or an input-output (bi-directional) or a switch pin. note that the Direction option is set to Input indicating that the current pin is an input pin. Now. each time you place a pin. 4.Example : Schematic Capture (CMOS Inverter) Step 6 : Placing the pins You must place I/O pins in your schematic to identify the inputs and the outputs. it is more convenient to put this pin in front of the common node of these terminals. Click Add on the menu and then select Pin on the pull-down menu. 3. you can enter pin names one after the other in the Pin Names field. 2. the next one will appear until all your pins are placed in the schematic. Point to a location to place the input pin.
Place the output pin by clicking on a lcoation in the schematic window. Press ESC on the keyboard to close the Add Pin window. click the left mouse button on the Direction field and select Output in the pop-up menu. Go back to the Add Pin window to pick up an output pin. At this point.4. Enter the output pin name. Now it is better to put the output pin near the common drain node which is the output of the inverter circuit. you have to change the pin direction to Output. which is "Outp" in our example. To do this. First. 5. The procedure is completely analogous to the placement of input pins. you are finished placing the pins. .
Click on a point on the common wire which connects the drain terminals of both transistors. Connect the pins to the corresponding nodes using wires. => The other end of the wire is floating. The wiring procedure is the same as described in the previous steps. PMOS and NMOS. y Press ESC to close the wiring mode. PMOS and NMOS. y Click on the input pin. At the end of this step. You are now in the wiring mode again. your schematic should look like the following: .6. y Click on the output pin. Click on a point on the common wire which connects the gate terminals of both transistors. => The other end of the wire is floating. Wiring the pins is summarized below : Click on Add on the menu and then select Wire (narrow).
Check the message field every time you save a design. It is also strongly advised that you save your designs frequently. 2. you may save your design selecting Save on the Design menu. Click Design on the menu banner and then select Check and Save. the errors would have been listed in this window. . Check the message field in the CIW window to see the error and the warning messages. During this tutorial. so that you don't loose your data because of a computer crash or because of a mistake that can happen in a complicated design environment such as this one. every time after you make significant changes. If this wasn't the case.Example : Schematic Capture (CMOS Inverter) Step 7 : Check and Save 1. You can see the message in the screen-shot above indicating that there is no error in our schematic.
If a certain circuit design consists of smaller hierarchical components (or modules). A symbol view of the circuit is also required for some of the subsequent simulation steps. but the default symbol icon is a simple rectangular box with input and output pins. the schematic capture of the circuit topology is usually followed by the creation of a symbol to represent the entire circuit.AND. This step largely simplifies the schematic representation of the overall system. . The "symbol" view of a circuit module is an icon that stands for the collection of all components within the module. OR. it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. and so on. NAND. NOR). allowing the circuit designer to create a systemlevel design consisting of multiple hierarchy levels. The shape of the icon to be used for the symbol may suggest the function of the module (e.g. Note that this icon can now be used as the building block of another module.Symbol Creation Please follow the example link (button) for a detailed description of "Symbol Creation". logic gates . thus.
The cells in the library will appear in the cell column. . 2. 1. Select your library by clicking on it in the library column of the Library Manager. Select your cell by clicking on it in the cell column of the Library Manager. The name of the selected view will appear in the small cell window.Example : Creating a Symbol Step 1: Opening an existing schematic Note : You can skip this step if you have your schematic window open. there should be only the "schematic" view appearing in the "view" column. 4. 3. At this point. In the Library Manager Window. The existing cellviews of your cell will appear in the view section. Select your cellview by clicking on it in the view column of the Library Manager. select Open from the File menu: ( File --> Open ) The schematic of the design will pop-up.
which is indicated with "To View Name" in the bottom-right corner of the pop-up window. Check the view names and click OK Before clicking OK. 2. From the Design menu. . you have to ensure that the target view name is symbol.Example : Creating a Symbol Step 2 : Creating cellview 1. If not. then you can change the target view name to "symbol" by clicking and holding the left mouse button on the corresponding box. select Create Cellview and then From Cellview : ( Design --> Create Cellview --> From Cellview ) The following window will pop up.
In the default case. This is the "black box" or symbol representation of your schematic.Example : Creating a Symbol Step 3 : Locating the pins 1. 2. window the following window pops up : In this window (Symbol Generation Options) you can edit your pin attributes and locations. If you don't want to change anything or you are finished with editing the pin specifications. After clicking OK in the Cellview From Cellview. showing your new symbol. You can change your pin locations simply by putting the pin name in the corresponding pin location field. then press OK to continue. A new window will appear. you will have your input(s) on the left and your output(s) on the right of the symbol. .
then you can create a new symbol simply by editing the existing one. You can do the following operations on your symbol : y y y y Deleting/replacing some existing parts Adding new geometric shapes Changing the locations for pins and instance name Adding new labels The following is an example for a manually created inverter symbol. the default shape of the symbol icon is a rectangle. As seen in the window. with the pins located as defined during the previous step in Symbol Generation Options pop-up window. which was obtained by editing the symbol above. If you are not satisfied with the symbol properties.Example : Creating a Symbol Step 4 : Editing the shape of the symbol icon 1. 2. . The red rectangle surrounding the whole symbol determines the clickable area to select the symbol when used in a schematic. the automatically generated symbol is shown. The small red squares indicate the connection points for each corresponding pin. In the new window.
Example : Creating a Symbol Step 5 : Check and Save 1. you can use only Save. At this point. by matching all of the pin names. which does not check anything. To check and save the symbol. . choose Check and Save from the Design menu : ( Design --> Check and Save ) While editing the symbol. This occurs only when you click on Check and Save. checking a symbol means comparing the symbol view with the corresponding schematic view.
It is quite common to discover errors such as a missing connection or an unintended crossing of two signals in the schematic. The initial simulation phase also serves to detect some of the design errors that may have been created during the schematic entry step. to accurately assess the electrical performance of the completed design. The second simulation phase follows the "extraction" of a mask layout (post-layout simulation). After the transistor-level description of a circuit is completed using the Schematic Editor. Based on simulation results. . hence. the designer usually modifies some of the device properties (such as transistor width-to-length ratio) in order to optimize the performance. The detailed transistor-level simulation of your design will be the first in-depth validation of its operation. the electrical performance and the functionality of the circuit must be verified using a Simulation tool. it is extremely important to complete this step before proceeding with the subsequent design optimization steps.Simulation Please follow the example link (button) for a detailed description of "Simulation".
Example : Simulation Step 2 : Select and place components Note : At this point. 1. you should have an empty schematic editor window open. 1. Give a name to your new schematic which makes it clear that the new schematic is to simulate the inverter. The components we need for the simulation of the inverter are the following : * inverter Symbol created for the inverter Power supply voltage Ground line DC voltage source Pulse waveform generator Capacitor * VDD * * GND vdc * vpulse * C . refer to the "Create Symbol" example. Follow the same procedure described in "Open a New Schematic" to create a new schematic where you will put your simulation schematic for the inverter.Example : Simulation Step 1 : Open a new schematic design Note : You should first create the symbol of the circuit schematic which you want to simulate. If you did not have the symbol for the schematic. The new schematic is called "invTest" in this example. The first step is to add and to place the components which will be used to simulate the inverter. Open a new schematic.
This means. Here you will see how to pick up a symbol you created from your library. "tutorial". and to place it in your schematic. to pick up the inverter symbol. This can be done. You can change the component library simply by clicking and holding the left mouse button on the library field. Click Browse in the Add Component window to activate the Component Browser. we have two source libraries. This library's name in our example is "tutorial". as explained in previous steps [click here for the . 2. Two new pop-up windows appear. Component Browser and Add Component.Adding and placing components in a schematic was explained previously [click here for the corresponding example]. 3. You should pay attention to the library from which you take the components. and the other is our design library which contains the components that we designed stored previously. The point where you have to take care of is picking up the components from the correct library. In this step. Click Add and select Component. we have to change the library of the Component Browser to our library. one is the given component library "NCSU_Analog_Parts".
Every symbol that you created within this library will show up here. there will be a new list of components which are included in this library. you can pick up the symbol you created for the inverter. So. by clicking on "inverter" in the component list in the Component Browser. After the library "tutorial" is selected. These two images below show the symbol before placement and after placement. This can be easily seen in the image below. You can go to the schematic window and place the symbol of the inverter to a point by clicking on it.corresponding example]. You can always check the corresponding fields in the Add Component window to make sure that you selected the desired component. . by clicking and holding the left mouse button until you select the corresponding library in the pop-up library list.
. Placement of the other components will be explained in the next step.We are now finished placing the symbol of the inverter.
"vdd" and "gnd". The remaining components are in the "NCSU_Analog_Parts" library. Your original circuit schematic already does have these supply nets attached to its appropriate nodes. you can always move a component to some other location in the same schematic. select "vdd" and "gnd" and place them anywhere in the schematic window. y Place the supply nets. "vdc" and "vpulse". Go up one folder to the main content folder.Example : Simulation Step 3 : Select and place components Note : You do not have to place the components exactly the same way as seen in the example images. but now you have to define the voltages in the new schematic window. Refer to the previous example (step 3 :"Changing the library in the Component Browser window") to see how you can change the source library. 1. Open the folder "Voltage Sources". Change your library from "tutorial" to "NCSU_Analog_Parts". Open the folder "Supply_Nets". y Place the voltage sources. select "vdc" and "vpulse" and place them in the schematic window. Pick up and place the rest of the components required for the simulation. As long as you connect them correctly. .
Open the folder "R_L_C". Go up one folder to the main content folder. We placed all the necessary components for this schematic. Why did we put these components into this schematic ? . select "cap" and place it in the schematic window.y Place the capacitance which will be the output load. "cap". 2.
The value of this voltage usually depends on the technology used. If you make a mistake. How to configure the voltage value of the source will be explained in the next steps. you can use the undo command under the edit menu. 1. A DC-voltage source called "vdd" is required as the power supply voltage in all digital circuits. To supply the VDD voltage to the circuit. load devices. Connect the DC-voltage source "vdc" to "vdd" and "gnd". you must build a simple test set-up (consisting of voltage sources.) around your original circuit to measure its operation and its characteristics. which is low-voltage process meaning that the typical VDD voltage value is 3.3 V. we will use a DC-voltage source with a constant voltage value of 3. .6u AMOS14TB [click here for further information]. The connections of the voltage source are shown in the image below. etc. The technology we use for this example is HP 0. Example : Simulation Step 4 : Wire components Note : Always save your designs if you make any changes on it. As in the real test-bench case.You can think of this procedure (creating a new schematic and placing these components into the new schematic) as being analogous to building a "test-bench" for the circuit you designed.3 V. Simply wire the "vdd" with the positive terminal of the DC-voltage source and the "gnd" with the negative terminal of the voltage source.
This source will be used to generate the input data (stimuli).2. period and voltage levels. so that we can observe the output of the inverter and see if the inverter operates correctly. Connect the pulse wavefrom generator "vpulse" to the input of the inverter "Inp". Wire the positive terminal of the pulse generator to the input pin of the inverter "Inp" and then the negative terminal of the pulse generator to "gnd". The pulse generator is a voltage source which can produce pulses of any duration. .
you may prefer to copy the existing "gnd" instance which is the one we connected with the DC-voltage source. Wire the positive node of the capacitance to the output pin of the inverter "Outp" and then the negative node of the capacitance to "gnd". 3. For example. All nodes connected to the "gnd" symbol will be short circuited throughout the schematic. In CMOS digital circuits.e. i. Connect the load capacitance "cap" to the output of the inverter "Outp". the output nodes are typically loaded by purely capacitive loads. The connections in the schematic below describe the same circuit as in the schematic shown above. all of them will stay at the reference voltage level which is O V (zero volts). To add a new component. you can either use the Add Component and the Component Browser window. the larger the delays to drive this load. or copy the component if it exists in the current schematic.For the sake of simplicity. The larger the capacitive load at the output. rather than browsing through the libraries and the components. you can also pick up more "gnd" components and put them into your schematic where it is needed. One of the important specifications of a circuit would usually be its driving capability for a given capacitive load. The following is an example to describe the case explained in the last paragraph.. .
Click Edit on the menu bar and select Properties and Object. Select the DC-voltage source by clicking on it. respectively. . The selected component is highlighted by a bright box (rectangle) around it.Example : Simulation Step 5 : Define the voltage sources In this step. The Edit Object Properties window appears. we will enter the necessary parameters for the voltage source components. Edit the properties of the DC-voltage source. 1.
Edit the DC voltage field in the Edit Object Properties window and type the VDD value which is 3.3V in our examples.
Click the "OK" button on the Edit Object Properties window. You can observe the new value entered for the DC-voltage near the DC-voltage source.
2. Edit the properties of the pulse generator Select the pulse generator instance in the schematic.
The Edit Object Properties window for the pulse generator appears.
The parameters which are listed in the image above are used to define a pulse which will be repeated periodically. How to use these parameters to define the input pulse waveform is explained in the figure below.
The following image shows the values for the pulse generator parameters which are used to define the input waveform. Click on OK to apply these changes and close the Edit Object Properties window.
Finally. . the new values for the important parameters of the pulse generator appear near the its instance.
The Edit Object Properties window appears. . Select the capacitor by clicking on it. This time. respectively. Click edit on the menu and select Properties and Object.Step 6 : Determine the output load 1. the listed parameters are valid for the selected capacitor. Edit the properties of the capacitor which is the output load of the inverter.
By editing the corresponding field in the Edit Object Properties window. Add labels to the nodes you want to observe after the simulation. the default value for the capacitance is 1 pF (picofarads). This value may be too high for a typical inverter load in this technology. These . In our example. Refer to the "Commonly Used Prefixes for Units in Cadence". In Cadence. there are two important nodes (or wires) which we want to observe during our simulations.The only parameter we change is the capacitance. As shown in the previous image above. 2. Click on OK in the Edit Object Properties window. labeling a node corresponds to adding certain names to the wires. The capacitance will be updated to the new value which is 25 fF. we change the capacitor value to 25 fF (femtofarads).
Click on the corresponding net to name the net with this label. we will label the two wires as "in" and "out". Select Wire Name in the Add command list. those labels are only valid in that schematic which is now in the lower level of hierarchy. You will see that there isn't any information related to the direction of the nodes. move the mouse cursor on the schematic. every time you create a symbol and use this symbol in a new schematic. But. The Add Wire Name window appears. the second label will appear on the mouse cursor. because only the pins are defined with a direction. You may think that you labeled these nets before while you were drawing the schematic for the inverter by adding the pins. This procedure is repeated until you are finished putting all label names you entered in the Add Label window. as shown below. Now. Now you will see the first label floating with the mouse cursor. you can type all the label names one after the other in the Names field. . As soon as you put the first label.are the input and the output nodes of the inverter. So. After all the labels are typed. you have give new labels to the nodes you want to specify. In the example.
. Be sure that the CIW doesn't report any errors or any warnings.The schematic with the wires ("in" and "out") labeled is shown in the image below. Close the Add Label window either by clicking on OK in the window or pressing ESC on keyboard. Save your design by using Check and Save in the Design command list.
y y y y Design Analyses Design Variables Outputs Note that the library.Example : Simulation Step 7 : Open the simulator window Now. Click on Tools in the menu banner of the schematic entry window and choose Analog Artist. 1. . The Analog Artist main window will appears. We will use Analog Artist as the simulator. Open the Analog Artist window. the cell and the view names are listed in the Design field. As you can see. there are four main fields in this window. we are ready to simulate our design. as shown below. so that you can check that you are simulating the desired cell using the correct view.
The Choosing Analyses window appears where you can choose the simulation type. we choose the transient simulation type. Note : Do not leave any space between the numeric value and the unit. Do not type "s" after the unit where "s" stands for "seconds".Example : Simulation Step 8 : Edit the Simulation Parameters 1. Do not forget to type a unit after the numeric value. type a value in the Stop Time field to determine how long the simulation will take place. Each of these options provides a specific sub-region within the Choosing Analysis window. 2. There are many available analysis options you can choose. the stop time for the simulation will be something in seconds which means your simulation will last forever ! . Click on Analyses in the menu banner and select Choose. so that the output can be traced in time domain. The Stop Time is chosen 30ns (nanoseconds). In the Transient Analysis region. Since we want to obtain the delay information for the inverter. Click on tran in the Analysis field. otherwise.
. select To Be Plotted and then Select on Schematic.3. so that you can select the nodes to be observed in that window. The schematic window becomes active. we have to select the nodes that we want to observe as simulation results. Click on the nets which you want to observe in the schematic window. Example : Simulation Step 9 : Run the Simulation Now. Click on OK in the Choosing Analyses window to close it and to go back to the Analog Artist window. Click on Outputs in the menu banner. 1. 2.
It includes the waveforms of the selected nodes plotted between t=0 and the determined Stop Time which is 30 ns in our example. Press ESC to finish your selections. the corresponding wire name appears in the Outputs list. "in". 4. Start the simulation by clicking Simulation and then selecting Run. Each time you select a node. 3.The selected nodes are the input of the inverter. . The waveform window appears after the simulation is completed. and the output of the inverter "out" which drives the capacitive load.
Notice that this option has replaced the former To Strip option. To separate the waveforms. Once seperated you can select the waveforms by clicking on them and draging them on top of each other to group. plotted on the same time axis.You will see the two waveforms together. . from the menu Axes select option To Composite. from the menu Axes select option To Strip. To return to the initial composite waveforms.
there are two different aspects that can be modified : y The simulation environment is not satisfactory. Refer to the step "Define the voltage sources" to setup your input sources. Also. The symbol for the inverter should be selected in this example. the properties of the input signal you feed to the circuit and the amount of output load which is capacitive. Refer to the step "Define the voltage sources" to check the connections of your power supply voltages. These changes are made without descending to a lower level of hierarchy in the design. y You have to modify your circuit design. This means that the setup to simulate your design should be modified. . you will need to change the W/L ratios (the ratio between the channel width and channel length) of the transistors to meet your design specifications. Go back to the schematic window and select the symbol of your design. you have to edit your design which consists only of a CMOS inverter in our example. Refer to the step "Determine the output load" to change the capacitance value of the capacitor. make sure that the power supply voltages are connected properly. You can basically change two things. The procedure describing how to re-run the simulation after editing the design is summarized below. 1.Example : Simulation Step 10 : Re-run the Simulation If you are not satisfied with the simulation results. Usually. Therefore.
. The existing schematic window now displays the schematic view for the inverter. Make the appropriate changes in the editable schematic of the design. Click on Design in the menu banner. select Hierarchy and then Descend Edit. 4.2. you have to edit its object properties. Click on OK in the Descend window which asks the designer which view of the design is to be edited. 5. Check and save your new schematic. To change the existing W/L ratio for a specific transistor. by going one level down through the design hierarchy. 3. Refer to the "Edit Object Properties" step in the schematic example.
quit the Analog Artist simulator. 7.you always must return to the original level from which you have descended. Note: Quitting a tool does not mean closing the corresponding window.6. Go to the Analog Artist window and run the simulation again. as described in "Run the Simulation" step. . You can iterate on your design as described in this section of the tutorial. Click on Design in the menu banner. because the waveforms will be updated after the simulation is finished. Never forget that you are editing the design at a lower level of the hierarchy . This will automatically close the Waveform window. too. As the simulation runs. When you want to end the simulation. Please always use the "close" or "quit" commands located in the menu bar of the tool. you can switch to the waveform window. select Hierarchy and then Return.
and obviously.Mask Layout y y Manual Layout Example Automatic Layout Example (Device Level Placer) The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow. The physical (mask layout) design of CMOS logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors. the detailed mask layout of logic gates requires a very intensive and time-consuming design effort. Physical layout design is very tightly linked to overall circuit performance (area. It is extremely imporant that the layout design must not violate any of the Layout Design Rules. On the other hand. using a Layout Editor. the parasitic capacitances and resistances. . where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication. the silicon area which is used to realize a certain function. in order to ensure a high probability of defect-free fabrication of all features described in the mask layout. speed and power dissipation) since the physical structure determines the transconductances of the transistors.
Please follow this example link for a detailed description of the main procedures in "Mask Layout Design". . Another alternative of generating the mask layout is to make use of automated tools. Please follow this example link for a detailed description of generating a layout from a schematic using the device level placer.
We will start with a simple design idea and will complete the mask layout using different techniques. Steps of Layout Design y y y y Starting up o Design Idea o Create Layout Cellview o Virtuoso and LSW NMOS o Drawing the N-Diffusion (Active) o The Gate Poly o Making Active Contacts o Covering Contacts with Metal-1 o The N-Select Layer PMOS o Drawing the P-Diffusion (Active) o Transistor Features o The P-Select Layer o Drawing the N-Well Connecting both transistors o Placing the PMOS and NMOS o Connecting the Output . a simple CMOS inverter layout will be drawn step by step.Example: CMOS Inverter Layout In this tutorial.
The schematic will the contain exact connection diagram and individual device properties. two main items are necessary at the beginning: 1. A circuit schematic 2.y Connecting the Input Making a Metal-1 connection for the Input Power Rails P Substrate contact N Substrate contact Enclosing the Substrate Contact DRC and Finalizing o Design Rule Checking o Final Layout o o o o o o Example: CMOS Inverter Layout Design Idea To draw the mask layout of a circuit. the one on the right is drawn in a way to resemble the final layout. It is important that the schematic of a functionally correct circuit is present and the layout is drawn according to the schematic (and not the other way around). Circuit schematic Any physical layout will actually correspond to a circuit schematic. Two example inverter schematics can be seen below. . While both schematics are identical. A signal flow diagram 1.
. Metal-1. The most important factor determining the actual layout is the signal flow. Metal-2. more than one physical layer can be used to transfer signals. In modern fabrication technologies. The actual mask layout will roughly follow this concept. Metal-3) can be used.2u and L=0. The general flow of the signal connections as well as their layers need to be pre-determined. it has been decided that all signals are on the same layer (blue. Metal-1) and that all signals will travel horizontally.In this example the NMOS transistor and the PMOS transistor have identical dimensions W=1. Note that the signal flow diagram is just a concept that you can visualize for a particular circuit. The layout will almost in all cases be a part of a larger structure or the basic building element of an array of identical blocks. The following is an sample flow diagram used for the example layout: In this flow diagram. or a simple scetch that you can scribble on the back of an envelope. For example with the fabrication technology used throughout this manual.6u 2. Signal flow diagram A layout can be drawn in a number of different ways. a total of 4 layers (poly.
cellname and cellview. Example: CMOS Inverter Layout . Please refer to Starting Cadence Section if you have not done so. Make sure that the library name corresponds to your design library. that you have logged on and started Cadence Design Tools. Enter cellname and choose layout cellview A dialog box will appear prompting you for the design library.Example: CMOS Inverter Layout Create Layout Cellview We will assume. choose a name for your cell and choose Virtuoso as the design tool. From the Library Manager. The cellview will be selected as layout. and that you already have created a design library for yourself. 1. choose File then New and then Cellview ( File --> New --> Cellview ) 2.
the default mode is selection. There is a small button bar on the left side of the editor. Note that these functions will change according tto the command you are currently executing. This information can be very handy while editing. . To select a layer. LSW The Layer Selection Window (LSW). To quit from any mode and return to the default selection mode. (from left to right) contains the X and Y coordinates of the cursor. Most of the commands in Virtuoso will start a mode. simply click on the desired layer within the LSW. number of selected objects. Commonly used functions can be accessed by pressing these buttons. Virtuoso Virtuoso is the main layout editor of Cadence design tools. Virtuoso will always use the layer selected in the LSW for editing. another line shows what function the mouse buttons have at any given moment. The LSW can also be used to determine which layers will be visible and which layers will be selectable. as long as you do not choose a new mode you will remain in that mode. the total distance and the command currently in use.Virtuoso and LSW Two design windows will pop-up after you have entered the design name. At the bottom of the window. lets the user select different layers of the mask layout. This information line. There is an information line at the top of the window. the "ESC" key can be used. the travelled distance in X and Y.
Draw the box You are now in rectangle mode. We will select the n-diffusion layer and draw a rectangular active area to define the transistor. From the Create menu in Virtuoso select Rectangle ( Create --> Rectangle ) 3.15u increments only. . click once. that is the cursor moves in 0. which will be the NMOS transistor of the CMOS inverter. Select nactive layer from the LSW 2. From the schematic. The width of the transistor will correspond to the width of the active area. All units are in micrometers by default. we know that this transistor has a channel width of 1.2u. Using the information bar. 1. and then move the mouse cursor to the opposite corner. Select the first corner of rectangle in the layout window (you may select any point within the window but try to select a point close to the origin). To simplify the drawing. a grid of half a lambda is used.Example: CMOS Inverter Layout Drawing the N-Diffusion (Active) Now we will start drawing our first transistor. draw a box that is 3.6u horizontal and 1.2u vertical.
Example: CMOS Inverter Layout The Gate Poly The second step is to draw the gate. Note that the length of the transistor channel will be determined by the width of this poly rectangle. We will use a vertical polysilicon rectangle to create the channel. 1. From the menu Misc choose Ruler ( Misc --> Ruler ) . Select poly layer from the LSW 2.
Draw poly rectangle The starting point is pinpointed by two rulers. .The ruler is a very handy function. design rules tell us that poly must extend at least by 0. The rectangle function is used to draw a poly rectangle that is 0.6u horizontal and 2. To pinpoint the location of the poly gate we can use two rulers. Select the ca (Active Contact) layer from the LSW. In our case we need to draw the poly rectangle in the middle of the diffusion region. 1. while a second ruler will show the minimum amount of poly extension outside the diffusion according to the design rules 3. Example: CMOS Inverter Layout Making Active Contacts The next step is to make the active contacts. One ruler will be used to determine the horizontal distance of the poly gate from the diffusion edge.6u (2 Lambda) from edge of the diffusion .4u vertical. These contacts will provide access to the drain and source regions of the NMOS transistor. Furthermore.
From the Edit menu choose Copy ( Edit --> Copy ) You could choose to draw the second contact the same way as you have drawn the first one. 3. .30u from the edges of diffusion. For this operation the default values are appropriate. copying existing features is also a viable alternative.6u within the active area. The Snap Mode is an interesting option. 4. However. Use the ruler to pinpoint a location 0.2. The copy dialog box will pop-up as soon as you select the copying mode. When this is in orthogonal setting the copied objects will move only along one axis. This is a good feature to help you avoid alignment problems. Create a square with a width and height of 0.
After you are finished (by hitting "ESC" key) you'll return to the mode you were in. Now move the object. Click in the contact. You can use a ruler to pinpoint the location. and click when you are satisfied with the location. Copy the contact After you enter the copy mode. you'll notice that the outline of contact will attach to your cursor.5. an object must be selected. . Design rules state that the minimum contact to poly spacing must be 0.6u (2 lambda). Please note that you can interrupt any mode for placing a ruler (and zooming in and out).
Example: CMOS Inverter Layout Covering Contacts with Metal-1 Active contacts in fact only define holes in the oxide (connection terminals).2u wide to cover the contacts Note that Metal-1 has to extend over the contact in all directions by at least 0.3u (1 lambda).Now you have placed an active contact each into the source and drain diffusion regions of the transistor. Draw two rectangles 1. Select layer Metal-1 from the LSW 2. 1. The actual connection to the corresponding diffusion region is made by the Metal layer. .
now let us make a few million more of the same :-) Example: CMOS Inverter Layout .6u (2 lambda) in all directions. 2. Select nselect layer from the LSW.Example: CMOS Inverter Layout The N-Select Layer Each diffusion area of each transistor must be selected as being of n-type or p-type. 1. This is accomplished by a defining the "window: of n-type (or p-type) doping (implantation). Draw a rectangle extending over the active area by 0. This is it ! Our first transistor is finished. through a special mask layer called n-select (p-select).
Example: CMOS Inverter Layout Transistor Features . Make sure you leave enough separation between the NMOS and the PMOS. the next step is to draw the PMOS transistor.6u by 1.Drawing the P-Diffusion (Active) Now that we have drawn the NMOS transistor. The basic steps invloved in drawing the PMOS are the same. 1.2u You can use the cursor keys and the zoom function to find yourself a place to build the transistor. Note that the PMOS transistor will also be sorrounded by the N-well region. Draw a rectangle 3. Select pactive layer from the LSW 2.
Place the contacts 3. Draw the gate poly 2.These three steps are identical to the ones done for the NMOS. 1. Cover contacts with Metal-1 .
Example: CMOS Inverter Layout The P-Select Layer As with the NMOS transistor. Draw a rectangle that extends over the active area by 0. Select pselect layer from the LSW 2.6u (2 lambda) in all directions. . the p-type doping (implantation) window over the active area must be defined using the n-pelect layer. 1.
the n-well is one of the first structures to be formed on the surface during fabrication. From the process point of view. which acts like a substrate for the PMOS transistors. NMOS transistors can be realized on this p-type substrate simply by creating n-type diffusion areas. For the PMOS transistors however a different approach must be taken: A larger n-type region (n-well) must be created.Example: CMOS Inverter Layout Drawing the N-Well In this process. 1. Draw a large n-well rectangle extending over the P-Diffusion . it does not have to follow the actual fabrication sequence. Note that the drawing sequence of different layers in a mask layout is completely arbitrary. Here we chose to draw the n-well after almost everything else is finished. the silicon substrate is originally doped with p-type impurities. Select the nwell layer from the LSW 2.
we did not pay much attention to the location of the transistors while building them. If you are in any other mode (like rectangle drawing mode) exit the mode by pressing "ESC". As long as the design rules are not violated. it is more desirable to place the PMOS transistor directly on top of the NMOS transitor.for a more compact layout.8u (6 lambda) Example: CMOS Inverter Layout Placing the PMOS and NMOS transistors In this example.The n-well must extend over the PMOS active area by a large margin. Select the PMOS transistor First make sure that you are in selection mode. the transistors can be placed in any arbitrary arrangement. all the objects within the PMOS would be highlighted as in the figure below: . click and drag a box that covers your PMOS. Yet based on our original signal flow diagram. 1. If you were successful. at least 1. Now using the mouse.
Since the minimum distance from diffusion to the n-well edge is 1. After we have picked the reference point.2. the PMOS and NMOS have to be at least 3. The corner between the diffusion and the poly is a good place to grab the PMOS. Since we want an accurate placement. the outline of the shape will appear attached to the cursor and we will be able to move the shape around. 3. This time we will have to change the Snap Mode option to Anyangle so that we can move the transistor freely. We can place a ruler to help us aligning the two shapes and to measure the distance.6u apart. . it is advisable to select a point for which alignment is simpler. The cursor will practically grab the object from that reference point. Pick the reference point We will be asked to find a reference point for the object to be moved.8u. From the menu Edit select the option Move ( Edit --> Move ) A window will pop-up similar to the copy window.
Example: CMOS Inverter Layout .4. poly and contacts) into its final location by clicking once on the left mouse button. Place the transistor You can drop the selected object (in this case consisting of the n-well. the p-active.
Please become familiar with as many of such options as possible. . you will see that you typically have multiple options. the path command. which will form the input. Example: CMOS Inverter Layout Connecting the Input The next step will be to connect the gates of both transistors. thus narrower than the Metal-1 covering the contacts. we could use the rectangle command again. but this time we will use a different command.Connecting the Output 1. the source and drain regions are interchangeable.9u (3 lambda). Draw a Metal-1 rectangle between NMOS and PMOS drain region contacts Note that the minimum Metal-1 width is 0. commands or procedures available to create the same features in the layout. Throughout this tutorial. Also note that the transistors are completely symmetric. To do this.
You'll see a ghost line appear.1. Select poly layer from the LSW 2. Start path To start the path. The width of the drawn line can be adjusted. click on the middle of the PMOS poly extension. Move this ghost line to the NMOS poly extension. 3. . From the Create menu select Path ( Create --> Path ) The path options box will pop up: In the path mode you can draw lines (or paths) with the selected layer. the default is the minimum width of the selected layer.
4. Double click to finish path A single click will finish a line segment and let you continue drawing. a double click will finish the path. Example: CMOS Inverter Layout .
You can place the contact at a certain location by clicking once. Starting from the poly line connecting the gates. click on Change To Layer and switch to Metal1 This will automatically add a contact to the end of the current path. Finish the path . Therefore we have to make a connection from the poly layer to the Metal-1 layer.Making a Metal-1 connection for the Input We have already decided in our signal flow graph that we want the input in Metal-1. This connection can be done manually by drawing a poly contact layer between Metal-1 and poly. but we will use the path command to automatically add the contacts. thereafter the path will continue using the new layer. 1. On the Path Options dialog box. 3. start drawing a horizontal poly path 2. note that this will still be a ghost line.
Our Signal Flow Graph suggests horizontal power and ground lines in Metal-1. Therefore it is common to design cells such that they will have one continous.You can finish the path by double clicking. there will be a red square instead. it is not possible to edit that layout from within your cell. You can press SHIFT-F to see all levels of hierarchy. Objects that you include as instances will be shown as boxes corresponding to their size. CTRL-F will return you to viewing only a single layer of hierarchy. Draw the Power Rail in Metal-1 above the PMOS . only the current layer of hierarchy is visible. An instance is practically a finished layout that is included completely in your circuit. Example: CMOS Inverter Layout Power Rails Now that our transistors are placed and connected. Since it is a complete layout. all of which need power and ground connections. Usually a layout consists of a large number of cells. This is called an instance. wide power and ground connection when placed side by side. By default. it is said to be on a lower level of hierarchy. we will have to add Power and Ground rails. Note that you will not be able to see the contact between the metal and poly layers. 1.
respectively. Draw the Ground Rail in Metal-1 below the NMOS Make sure to connect the Power Rail and the Ground rail to the source contact of the PMOS and to that of NMOS.2. Example: CMOS Inverter Layout .
1. Since the contact will be made to p-substrate. . Draw a P-select square next to the NMOS transistor. Draw a P-active square inside the P-select area. 2.P-Substrate Contact The substrate on which the transistors are built must be properly biased. This will define the active area of the substrate contact. The way to do this is to add substrate contacts. we will have to create a p-type substrate contact. make sure that you are not violating any design rules associated with active area spacing. The NMOS transistors are build on a p-type substrate. the contact area will have to be p-type.
4. covering the entire substrate contact. Draw the active contact square inside the p-type active area. Make a metal connection to ground.3. .
this alternative approach will be demonstrated in the next step. Similar instances also exist for the substrate connections. Example: CMOS Inverter Layout N-Substrate Contact The PMOS transistor was placed within the n-well. this well also has to be biased with the VDD potential. Almost all of the interlayer connections are already available as instances in your design library. instead of drawing every item seperately. We used the metal-poly contact instance while connecting the input. We can follow the same steps that we did for the p substrate contact. 1. but we will try to introduce another method.Note that the susbtrate contact can also be created and placed as an instance. for the nwell contact. From the menu Create select option Instance ( Create --> Instance ) . THis will be done with an n-type substrate contact.
but in this case it is better to Browse in your library to find the appropriate cell. The N-substrate contact is named NTAP. cell and cell view. You'll have to provide a cell name and library here. and you'll be able to move the instance to the desired location: . 2. Move the instance to the desired location. Once you have selected the instance.This will pop-up the instance options menu. the cursor will show a ghost image representing the instance. It may be the case that you already know the cell name and cell view. and only has a symbolic view. It lets you choose the library. your selection will be transferred to the Instance options menu. This is essentially the same library browser that you access when you start Cadence Design Tools.
. which will obviously generate a rul eviolation. press "ESC" to go back to selection mode again. Make the power connection. You'll remain in the instance mode after you have placed the instance. This will have to be dealt with in the next step. the n-well contact has been placed right on top of the n-well boundary. Once satisfied.3. Note that in this example. The instance will not automatically connect itself to the power supply rail. Place the instance. This connection has to be made by either a Metal-1 rectangle or path. you can click to place the instance. the n-well is simply not wide enough to accomodate both the PMOS transistor and rge contact. 4.
Move cursor over the left edge of the n-well. Pressing "F4" will change this default to partial selection. Press F4 on the keyboard to toggle selection mode. so that it also covers the substrate contact. . By default. The information bar will start displaying "(P) Select" (P for partial) instead of "(F) Select" (F for Full). 2. the well is not wide enough to accomodate the additional contact. We must enlarge the n-well. Since we had drawn the n-well to cover the P-diffusion at minimum length.Example: CMOS Inverter Layout Enclosing the substrate contact In the previous step we tried to place the n-type substrate contact in the n-well. we will try to modify the existing rectangle. so that it covers the contact. One way to do this would be to simply draw an adjoining rectangle using the n-well layer. 1. the selection mode will only select whole objects. Instead.
Move the edge of the n-well so that all the of the substrate contact is covered by n-well. You'll notice that the cursor changes shape when you are close to the edge. only the edge line will be highlighted as a pale dashed line. You have grabbed the edge. Press and hold left mouse button when cursor changes above the selected edge. and as long as you do not release the mouse button you can "stretch" the edge. Move mouse over the selected edge (without pressing any mouse buttons). .You'll notice that as soon as the cursor is close to the edge. Click once to select the edge. 3. 3. 4.
an automatic program will check each and every feature in your design against these design rules and report violations. After you have finished your design. This process is called Design Rule Checking. From the menu Verify select option DRC ( Check --> DRC ) This will pop-up the DRC options dialog box. 1. .Example: CMOS Inverter Layout Design Rule Checking The layout must be drawn according to strict design rules. we must now perform a Design rule Check to see if we have any errors. Our design is finished.
. Start DRC The default options for the DRC are adequate for most situations. and the spacing is supposed to be at least 1.5.5um The errors are also highlighted on the layout. In this example we have two poly-to-poly contact spacing errors. DRC results and progress will be displayed in the CIW. You can also see that the rule number for this is 5.2. You'll have to check the results from the CIW.
. one misplacement will cause multiple DRC errors.As it is mostly the case. The error can be corrected by moving the contact further to the left.
This is a successful DRC. we will have to perform another DRC. .After moving the contact to the left.
. Congratulations.Example: CMOS Inverter Layout Final Layout This is the completed layout of the CMOS inverter.
Example: Automatic Layout Generation Tools (Device Level Placer)
In this tutorial an alternative way of drawing layouts will be introduced. This tutorial assumes that the reader is familiar with the Virtuoso layout tool and has followed the layout manual.
Since the manual creation of the physical layout is labour intensive, significant amount of work has been put into the automation of the physical layout design process. The device level placer is one of the lower-level answers. The device level placer, will read in a schematic and place all the transistors and I/O pins in the layout window. This tool will use parametric instances that will generate appropriately sized transistors. Although the device level placer and similar contemporary tools provide some nice features, the quality of the layouts they produce are still far from hand optimized layouts. Steps of Automatic Layout Generation
y y y y
Starting the Automatic Layout Tool Placing the Components Making Connections Finishing Touches
Example : Automatic Layout Generation (CMOS Inverter)
Step 1 : Starting the Automatic Layout Tool
To start the automatic layout generation, you must have finished your circuit schematic first. Please follow the Schematic Tutorial Example first if you have not done so. 1. Open the schematic view of your design.
In this example, the PMOS transistor has a channel width of W=4.5u and a channel length of L=0.6u, while the NMOS transistor has a channel width of W=3u and a channel length of L=0.6u. 2. From the menu select Tools --> Design Synthesis --> Device-Level Editor.
Selecting this option will first open up a small dialog box that will let the user select the cell name for the layout. It is a good idea to use the same cell name and specify layout as the cell view name.
Upon the selection of the view name, the user will be prompted another small dialog box. This box will ask for a pin layer, pins in the layout will be placed as connections in the given layer. Choose Metal-1 as the I/O Pin Layer, and all of the pins that you have specified in your schematic will be placed as connections in Metal-1.
In addition to the already open schematic window, a new layout window and the layer selection window will pop up. These three windows define the working environment for the automatic layout generation flow.
After the I/O pin layer is selected, two rectangles representing the transistors (the nmos and the pmos) and two Metal-1 squares will show up in the bottom half of the layout window. Notice the cyan colored square on the upper half of the layout window: This is the estimated size of the layout, this size is not mandatory, it is calculated roughly from the sizes of the active elements. With the next step, you'll start forming the layout within the box above.
Example : Automatic Layout Generation (CMOS Inverter) Step 2 : Placing the Components The default behavior of the layout editor is to show only the current hierarchy. . this way you'll be able to see actual transistors instead of the red instance rectangles. 2. 1. Move the selected transistor by dragging it with the mouse. The first step is to place all the components within the design area. You can press shift-f to display all the hierarchy levels. Select the PMOS transistor by clicking once.
Release the mouse button to place the selected transistor. Move the remaining objects the same way . 3. lines to other objects will show up. These lines represent the connections of the selected (and dragged) object to other objects of the design. 4. In this example the poly of the PMOS transistor will be shown connected to the poly of the NMOS transistor and the input.Note that in addition to the ghost image of the selected object. and the drain region of the transistor will be shown connected to the output and the drain region of the NMOS.
All of the commands that were available in the manual layout tool are available in this tool too. You can use rulers to pinpoint the exact location of the devices.Note that the automatic layout tool looks almost identical to the Virtuoso layout editor. .
move and place the output pin too.The I/O pins correspond to the pins drawn in the schematic. type and direction of the connection. As the last step. 5. Although they just look like an ordinary Metal-1 patch they contain information about the name. Final placement .
From the menu DLE select option Probe.Your final working environment should look more or less like this. 1. you can choose to place the transistors and the I/O pins any way you desire. Note that this placement is not obligatory. the next step is to make the connections between individual objects. The probe option will display a small dialog box: . We will be using the same methods that we used during manually drawing a layout here. Example : Automatic Layout Generation (CMOS Inverter) Step 3 : Making Connections In the previous step we have placed the components. The automatic layout tool has an additional menu which provides some useful options to faciliate signal connections.
Now you can go and select connections (nets) devices, and terminals in either layout or the schematic window and the corresponding object will be highlighted in the other window. This is called cross-probing.
As an example try clicking and selecting the wire connecting the drains of both transistors to the output pin, notice that two drain regions as well as the output I/O pin in the layout window will be highlighted. 2. Connect the drain regions with Metal-1 using the path command.
Notice that the new connection will also be highlighted as it is drawn.
Connect the gates of both transistors using a poly path and connect this path to the input.
Example : Automatic Layout Generation (CMOS Inverter)
Step 4 : Finishing Touches
At this point the design is almost finished. Unfortunately the automatic design creation process for this fabrication technology is unable to add substrate connections. So these will have to be added by the user. 1. Using the Create --> Instance command select a PTAP substrate contact.
Place the instance close to the bottom of the NMOS transistor, close to the source region (which has not been connected to a ground rail yet).
2. Using the Create --> Instance command select a NTAP substrate contact.
This contact will be used as the n-well contact.
As in the previous manuallayout example, the N-Substrate contact will not fit in a n-well that is drawn according to the minimum distance rules from the transistor. Since the transistor is an instance, it is not possible to stretch the n-well edge as it has been done in the layout example.
Draw the power rail with Metal-1. 3.To address this problem. . 4. we can easily draw an extension to the already existing n-well using the rectangle command. The next step is to draw the ground rail and the power rail. Make sure to connect the NMOS source and the substrate contact to the ground rail you have just drawn. So instead of redrawing the power rail you can copy the ground rail. Notice that the power rail and the ground rail are symmetric. Using the Rectangle command draw the ground rail with Metal-1.
first select the Metal-1 layer from the layer selection window and then use the Create --> Pin command. You can flip the selected image upsidedown by clicking the "upsidedown" button on the copy dialog box. Place the pins. This will pop-up a dialog box to allow you enter various parameters of the pin. When you are done. .To select multiple objects press "SHIFT" key while selecting objects. To do this. 5. use Edit --> Copy command to copy the selected image. The next step is to give connection information to the power rails and ground rails.
For the power rail enter the name: "vdd!" (without quotes. Define a rectangle with the Metal-1 layer on the power rail. Use the name "gnd!" (without the quotes. as the pin location.9u) and make sure it is on the power rail. Place the pin: . Place a pin on the ground rail in a similar way. as a good practice try to make it a minimum sized box (0. that is a signal name that is unique accross your entire design. watch case and the exclamation mark). The location of the pin and the size are not relevant (at least not in this context).9u x 0. it defines a global signal. The exclamation mark is important. watch for the case and exclamation mark) for the pin name.
1. So these will have to be added by the user. .This is the final layout. Using the Create --> Instance command select a PTAP substrate contact. Example : Automatic Layout Generation (CMOS Inverter) Step 4 : Finishing Touches At this point the design is almost finished. Unfortunately the automatic design creation process for this fabrication technology is unable to add substrate connections. created by the automatic device level editor.
As in the previous manuallayout example. close to the source region (which has not been connected to a ground rail yet).Place the instance close to the bottom of the NMOS transistor. Using the Create --> Instance command select a NTAP substrate contact. the N-Substrate contact will not fit in a n-well that is drawn according to the minimum distance rules from the transistor. it is not possible to stretch the n-well edge as it has been done in the layout example. . 2. This contact will be used as the n-well contact. Since the transistor is an instance.
To address this problem. The next step is to draw the ground rail and the power rail. 3. we can easily draw an extension to the already existing n-well using the rectangle command. . Using the Rectangle command draw the ground rail with Metal-1. Draw the power rail with Metal-1. 4. Make sure to connect the NMOS source and the substrate contact to the ground rail you have just drawn. Notice that the power rail and the ground rail are symmetric. So instead of redrawing the power rail you can copy the ground rail.
The next step is to give connection information to the power rails and ground rails.To select multiple objects press "SHIFT" key while selecting objects. Place the pins. You can flip the selected image upsidedown by clicking the "upsidedown" button on the copy dialog box. . use Edit --> Copy command to copy the selected image. To do this. This will pop-up a dialog box to allow you enter various parameters of the pin. 5. first select the Metal-1 layer from the layer selection window and then use the Create --> Pin command. When you are done.
watch case and the exclamation mark). The exclamation mark is important.9u) and make sure it is on the power rail. watch for the case and exclamation mark) for the pin name. as a good practice try to make it a minimum sized box (0.9u x 0. Place a pin on the ground rail in a similar way. The location of the pin and the size are not relevant (at least not in this context). Use the name "gnd!" (without the quotes. it defines a global signal.For the power rail enter the name: "vdd!" (without quotes. that is a signal name that is unique accross your entire design. as the pin location. Define a rectangle with the Metal-1 layer on the power rail. Place the pin: .
1. Using the Create --> Instance command select a PTAP substrate contact. Unfortunately the automatic design creation process for this fabrication technology is unable to add substrate connections. So these will have to be added by the user.This is the final layout. created by the automatic device level editor. . Example : Automatic Layout Generation (CMOS Inverter) Step 4 : Finishing Touches At this point the design is almost finished.
Place the instance close to the bottom of the NMOS transistor. As in the previous manuallayout example. Since the transistor is an instance. it is not possible to stretch the n-well edge as it has been done in the layout example. the N-Substrate contact will not fit in a n-well that is drawn according to the minimum distance rules from the transistor. This contact will be used as the n-well contact. . close to the source region (which has not been connected to a ground rail yet). Using the Create --> Instance command select a NTAP substrate contact. 2.
we can easily draw an extension to the already existing n-well using the rectangle command. So instead of redrawing the power rail you can copy the ground rail. 3. Draw the power rail with Metal-1. Notice that the power rail and the ground rail are symmetric.To address this problem. . 4. Using the Rectangle command draw the ground rail with Metal-1. The next step is to draw the ground rail and the power rail. Make sure to connect the NMOS source and the substrate contact to the ground rail you have just drawn.
This will pop-up a dialog box to allow you enter various parameters of the pin. . first select the Metal-1 layer from the layer selection window and then use the Create --> Pin command. The next step is to give connection information to the power rails and ground rails. When you are done. use Edit --> Copy command to copy the selected image. You can flip the selected image upsidedown by clicking the "upsidedown" button on the copy dialog box. 5. Place the pins.To select multiple objects press "SHIFT" key while selecting objects. To do this.
as a good practice try to make it a minimum sized box (0. The exclamation mark is important. Place a pin on the ground rail in a similar way. as the pin location. Define a rectangle with the Metal-1 layer on the power rail. Use the name "gnd!" (without the quotes. it defines a global signal. The location of the pin and the size are not relevant (at least not in this context). that is a signal name that is unique accross your entire design. watch for the case and exclamation mark) for the pin name. Place the pin: .For the power rail enter the name: "vdd!" (without quotes.9u x 0.9u) and make sure it is on the power rail. watch case and the exclamation mark).
Using the Create --> Instance command select a PTAP substrate contact. Unfortunately the automatic design creation process for this fabrication technology is unable to add substrate connections. Example : Automatic Layout Generation (CMOS Inverter) Step 4 : Finishing Touches At this point the design is almost finished. So these will have to be added by the user.This is the final layout. . 1. created by the automatic device level editor.
it is not possible to stretch the n-well edge as it has been done in the layout example. 2. the N-Substrate contact will not fit in a n-well that is drawn according to the minimum distance rules from the transistor. Using the Create --> Instance command select a NTAP substrate contact. Since the transistor is an instance. close to the source region (which has not been connected to a ground rail yet). . As in the previous manuallayout example. This contact will be used as the n-well contact.Place the instance close to the bottom of the NMOS transistor.
The next step is to draw the ground rail and the power rail. we can easily draw an extension to the already existing n-well using the rectangle command.To address this problem. 3. Draw the power rail with Metal-1. So instead of redrawing the power rail you can copy the ground rail. Using the Rectangle command draw the ground rail with Metal-1. 4. . Make sure to connect the NMOS source and the substrate contact to the ground rail you have just drawn. Notice that the power rail and the ground rail are symmetric.
You can flip the selected image upsidedown by clicking the "upsidedown" button on the copy dialog box. The next step is to give connection information to the power rails and ground rails. To do this. 5.To select multiple objects press "SHIFT" key while selecting objects. Place the pins. When you are done. use Edit --> Copy command to copy the selected image. first select the Metal-1 layer from the layer selection window and then use the Create --> Pin command. This will pop-up a dialog box to allow you enter various parameters of the pin. .
9u x 0. Place the pin: . as the pin location. as a good practice try to make it a minimum sized box (0. it defines a global signal.9u) and make sure it is on the power rail. Place a pin on the ground rail in a similar way. The location of the pin and the size are not relevant (at least not in this context). Define a rectangle with the Metal-1 layer on the power rail. Use the name "gnd!" (without the quotes.For the power rail enter the name: "vdd!" (without quotes. The exclamation mark is important. that is a signal name that is unique accross your entire design. watch for the case and exclamation mark) for the pin name. watch case and the exclamation mark).
and the corresponding rule is also displayed in a separate window. created by the automatic device level editor.This is the final layout. The created mask layout must conform to a complex set of design rules. is used to detect any design rule violations during and after the mask layout design. in order to ensure a lower probability of fabrication defects. called Design Rule Checker. A tool built into the Layout Editor. Design Rule Check (DRC) Please follow this example link for a description of how to run DRC on a layout. The detected errors are displayed on the layout editor window as error markers. The designer must perform DRC (in a .
and make sure that all layout errors are eventually removed from the mask layout. . DRC is usually performed frequently .before the entire design is completed). before the final design is saved.large design.
This action might not be possible to undo. Are you sure you want to continue?
We've moved you to where you read on your other device.
Get the full title to continue listening from where you left off, or restart the preview.