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Digital Principles & Systems Design
3rd SEM CSE & IT
PANIMALAR INSTITUTE OF TECHNOLOGY
(JAI SAKTHI EDUCATIONAL TRUST) CHENNAI- 600 123
CHAPTER 1 BOOLEAN ALGEBRA AND LOGIC GATES
Number Base Conversions :
1. List the different number systems? i) Binary Number system ii) Octal Number system iii) Decimal Number system iv) Hexadecimal Number system 2. Express the following in decimal: a) (10110.0101)2, b) (16.5)16, c) (26.24)8, d) (FAFA.B)16, e) (1010.1010)2 (a) (10110.0101)2 = (1x24) + (0x23) + (1x22) + (1x21) + (0x20) + (0x2-1) + (1x2-2) + (0x2-3) + (1x2-4) = 16 + 4 + 2 + 0.25 +0.0625 = (22.3125)10 (b) (16.5)16 = (1x161) + (6x160) + (5x16-1) = 16 + 6 + (5 (0.0615)) = (22.3125)10 (c) (26.24)8 = (2x81) + (6x80) + (2x8-1) + (4x8-2) = 16 + 6 + 2/8 + 4/64 = (22.3125)10 (d) (FAFA.B)16 = (Fx163) + (Ax162) + (Fx161) + (Ax160) + (Bx16-1) = (15x163) + (10x162) + (15x161) + (10x160) + (11x16-1) = (64,250.6875)10
(e) (1010.1010)2 = (1x23) + (0x22) + (1x21) + (0x20) + (1x2-1) + (0x2-2) + (1x2-3) + (0x2-4) = 8 + 2 + 0.5 +0.125 = (10.625)10 3. Convert the following binary numbers to hexadecimal and to decimal: a) 1.11010, b) 1110.10 Explain why the decimal answer in (b) is 8 times that of (a). To convert from binary to hexadecimal: Each 4 binary digits are equal to 1 hexadecimal digit: a) (0001.11010)2 = (1.D0)16 b) (1110.1000)2 = (E.8) 16 To convert from binary to decimal: a) (1.11010)2 = (1x20) + (1x2-1) + (1x2-2) + (0x2-3) + (1x2-4) + (0x2-5) = (1) + (0.5+0.25+0.0625) = (1.8125)10 b) (1110.10) 2 = (1x23) + (1x22) + (1x21) + (0x20) + (1x2-1) + (0x2-2) = (8+4+2) + (0.5) = (14.5) 10 The decimal answer in (b) is 8 times that of (a) because the binary number in (b) is the same as that in (a) except that the point is shifted to the right 3 digits and this means that it is multiplied by 23. 4. Convert (9B2.1A) H to its decimal equivalent. N = (9 x 16 2) + (B x 16 1) + (2 x 16 0) + (1 x 16 -1) + (A (10) x 16 -2) = 2304 + 176 + 2 + 0.0625 + 0.039 = (2482.1)10
0625 0.984 0.513)10 to octal. Convert 0.513)10 = (231.125 0.656 0. 2010) 8. 2004) (346)7. (May.0 (0.104 0.248 0.406517)8 --1 3 5 1 (May.640 625)10 = (0.125 x 8 = 1.656 x 8 = 5.0 Ans = (0.640625 decimal number to its octal equivalent.0625 x 16 = 1. 6. = (3x72) + (4x71) + (6x70) = (181)10.248 x 8 = 1.21)16 2 1 .51) 8 7. Convert 0.5.832 0. 0.1289062 decimal number to its hex equivalent 0.984 x 8 = 7.513 x 8 = 4.104 x 8 = 0.1289062 x 16 = 2.832 x 8 = 6. 406517)8 4 0 6 5 1 7 = (0.640625 x 8 = 5. Integer part: 8 153 8 19 2 = (231)8 Fractional part: 0. Convert the (153.872 (approximate) • (153. Find the decimal equivalent of (346)7.
44 x 16 = 7. 2008) 10.24 0.3042) 7 3 0 4 2 = (0.84 0. Integer part: 16 1 = (16)16 Fractional Part: 0.64 to hexadecimal number.4414062)10 Now.342)8 = (104.84 x 16 = 13. convert this number to base 7.342)8 = ( ) 7.64 x 16 = 10. A3D7) 16 A 3 D 7 22 -6 .9.4414062x 7 = 3.4023266x 7 = 2.3042)7 --4 0 (May.0898434 0. (65.44 0.04 Ans = (16. Convert the following number from one base to other (65.4023266 0.342)8= (6x81) + (5x80) + (3x8-1) + (4x8-2) + (2x8-3) = (53.6289038 0.24 x 16 = 3. Convert 22.6289038 x 7 = 4.0898434x 7 = 0. Integer part: 7 53 7 7 1 = (104)7 Fractional part 0.8162862 • (65.
(a) (354. Convert (634)8 to binary 6 110 3 011 4 100 Ans = (110011100)2 13.11.0555 = (142.25 0.8333+ 0.75 0. (231.3)4 = (2x42) + (3x41) + (1x40) + (3x4-1) = 32+ 12+ 1+ 0.25x 7 = 1. Convert the following number from one base to other (a) (354. 2005) (231.52) 6 = (142.3)4 = (63.888) 10 • (354.75x 7 = 5.3)4 to base 7.52) 6 = ( )10 (b) (100)10 = ( ) 16.25x 7 = 1. Convert the given number to decimal.5151)7 -3 = (45. convert this number to base 7.5151)7 12.75 • 5 1 5 1 = (0.75)10 Now. 2006) .25 0.52) 6 = (3x62) + (5x61) + (4x60) + (5x6-1) + (2x6-2) = 108+ 30+ 4 + 0. Convert (231.75x 7 = 5. (May.888) 10 (Nov.75 Integer part: 7 45 6 = (63)7 Fractional part: 0.
What are the different types of number complements? i) r’s Complement ii) (r-1)’s Complement. What is the minimum number of hexadecimal digits that the counter must have? Soln: (May. 2004) -4 • (10.000)10 = (2710)16 Complements : 15.(b) (100)10 16 100 6 = (64)7 • (100)10 = (64)16.000)10 is to be constructed. 14. . A hexadecimal counter capable of counting upto atleast (10.
1) to – (2n-1-1) Where.16. N= given number or digit 17. The 2’s complement of N is a) 11101010 b) 01111110 c) 00000001 d) 10000000 e) 00000000 . Why complementing a number representation is needed? Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used. Obtain the 1’s and 2’s complement of the following binary numbers: (May. 1’s complement of N= + (2n-1. The given number N in the base r= 2 having n digits.1) to – (2n-1). Where. 2’s complement of N= + (2n-1. n is number of digits. The (r-1)’s complement of N is defined as follows. Substract (0 1 0 1)2 from (1 0 1 1)2 1010 (-) 0 1 0 1 -------0110 -------Answer = (1 1 0)2 19. 2006) The given number N in the base 2 having n digits. 20. What is the range of values that can be represented using n-bit 2’s complement form of representation? What is the corresponding range with n-bit 1’s complement form? defined as follows. Add (1 0 1 0)2 and (0 0 1 1)2 1010 (+) 0 0 1 1 --------1101 --------Answer = (1 1 0 1)2 18.
a) 11101010 1’s complement: (00010101)2 2’s complement : 0 0 0 1 0 1 0 1 (+) 1 -------------------(0 0 0 1 0 1 1 0)2 --------------------b) 01111110 1’s complement: (10000001)2 2’s complement : 1 0 0 0 0 0 0 1 (+) 1 --------------------(1 0 0 0 0 0 1 0)2 --------------------c) 00000001 1’s complement: (01111110)2 2’s complement : 0 1 1 1 1 1 1 0 (+) 1 ---------------------(1 1 1 1 1 1 1 1)2 ----------------------d) 10000000 1’s complement: (01111111)2 2’s complement : 0 1 1 1 1 1 1 1 (+) 1 ----------------------(1 0 0 0 0 0 0 0)2 ----------------------e) 00000000 1’s complement: (11111111)2 . then add (1) to the LSB. 2’s complement: change every 1 to 0 and vice versa.Soln: 1’s complement : change every 1 to 0 and vice versa.
Soln: 000110 . Soln: Substract (1 1 1 0 0 1)2 from (1 0 1 0 1 1)2 using 2’s complement method.1’s Complement . Perform subtraction using 1’s complement (11010)2 – (10000)2. of (1 1 1 0 0 1)2 --------------1 1 0 0 1 0 in 2’s complement form --------------To get the answer in true form .( 0 0 1 1 1 0 )2 23.2’s complement : 0 1 1 1 1 1 1 1 (+) 1 ----------------------(1 0 0 0 0 0 0 0 0)2 ----------------------Find 2’s complement of (1 0 1 0 0 0 1 1) 2 010111001 (+) 0 0 0 0 0 0 1 ---------------------(0 1 0 1 1 1 0 1 0)2 ---------------------22. 21. Answer in true form . -------------101011 +000111 . take the 2’s complement and assign negative number to the answer.2’s complement. 1111 11010 (+) 01111 (+) 1 (0 1 0 1 0)2 1’s complement of (10000)2 (Add carry to LSB) 1 01001 .1’s Complement of (1 1 1 0 0 1)2 +00001 -------------000111 . .2’s comp.2’s complement.
(a) X -Y and (b) Y . Given two binary numbers X = 1010100 and Y = 1000011. a) X = 1 0 1 0 1 0 0 0111101 ---------------10010001 Discard end carry Answer: X .(0010001)2 25. Given two binary numbers X = 1010100 and Y = 1000011.Y = (0010001)2 b) Y .1010100 Y=1000011 0101011 ----------------(1's complement of X) (1's complement of Y) . So. Answer is Y-X = .X using 1's complements.X using 2's complements.(2's complement of 1101111) = .Y = 1010100 . perform subtraction.• Y.Y = (0010001)2 b) Y = 1 0 0 0 0 1 1 0101100 ----------------1101111 (2's complement of Y) (2's complement of X) There is no end carry. take 2’s complement again for the above answer.X = (01010)2 24. a) X . perform subtraction.X = 1000011 .1000011 X=1010100 0111100 ----------------10010000 Discard end carry = + 1 Answer: X . (a) X -Y and (b) Y .
The ASCII code. What are the different ways to represent a negative number? The different ways of representing a negative number areIn ordinary arithmetic. In signed 2’s complement representation. 2006) Binary Codes : 27. ii. . iv. Binary weighted code. iii. ix. 28. the negative sign is indicated by a minus sign. i. Answer is Y . Extended binary-coded decimal interchange code (EBCDIC). in which MSB is indicated as ‘0’ to represent negative number.1101110 There is no end carry.(0010001)2 26.X = . (Nov. Mention the different type of binary codes? BCD code (Binary Coded decimal). v. vii. iv. viii. i. The excess-3 (X’s-3) code. ii. vi. Alphanumeric code. Error-detecting and error-correcting code. iii. Gray code. i. in which the negative number is indicated by its 1’s complement.(1's complement of 1101110) = . Self-complementing code. State the different classification of binary codes? Weighted codes The various types of binary codes are. In signed 1’s complement representation. in which the negative number is indicated by its 2’s complement. In signed magnitude representation. Hamming code. x.
v. What are error detecting codes? (Nov. vi. 31. 2007) . What is meant by bit? A binary digit is called bit 30. What is advantage of gray codes over binary number sequence? (May. 32. To maintain the data integrity between transmitter and receiver. 35. Write down the result. Gray Code : 1 0 1 0 1 1 Binary Code: 1 1 0 0 1 0 34.Extended Binary Coded Decimal Information Code. EBCDIC .ii. iii. To obtain the next binary digit. iv. Define byte? Group of 8 bits. perform an exclusive OR operation between the bit just written down and the next gray code bit. extra bit or more than one bit is added in the data. Code which allow only error detection are called error detecting codes. State the steps involved in Gray to binary conversion? The MSB of the binary number is the same as the MSB of the gray code number. The data along with the extra bit/bits forms the code. Non .American Standard Code for Information Interchange. State the abbreviations of ASCII and EBCDIC code? ASCII . Convert gray code 101011 into its binary equivalent. 2007) When the digital information in the binary form is transmitted from one circuit or system to another circuit or system an error may occur.weighted codes Reflective codes Sequential codes Alphanumeric codes Error Detecting and correcting codes. So write it down. 33. 29.
The associative property is stated as follows: A+ (B+C) = (A+B) +C 38. The commutative property is: (A+B) = (B+A) 39. The distributive property states that ANDing several variables and ORing the result with a single variable is equivalent to ORing the single variable with each of the several variables and then ANDing the sums. associative property and distributive property. The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. State the commutative property of Boolean algebra. The distributive property is: A+BC= (A+B) (A+C) 40.The advantage of gray codes over the binary number is that only one bit in the code group changes when going from one number to the next. What are basic properties of Boolean algebra? The basic properties of Boolean algebra are commutative property. 37. State De Morgan's theorem. The commutative property states that the order in which the variables are ORed makes no difference. . State the associative property of Boolean algebra. The gray code is used in applications where the normal sequence of binary number may produce an error or ambiguity during the transition from one number to next. State the distributive property of Boolean algebra. Boolean Algebra & Theorems : 36. De Morgan suggested two theorems that form important part of Boolean algebra.
starting with a Boolean relation. What are minterms? Each individual term in standard SOP form is called minterms 45. (Nov. (A. State the absorption law of Boolean algebra.B' 41. A (A+B) =A. you can derive another Boolean relation by 1. • • 42.B = A+ AB + A’B = A+ B (A+ A’) = A+ B (1) = A+ B [A+ A’= 1] [ A+AB = A] Canonical Form : 44. 1) The complement of a product is equal to the sum of the complements. Changing each AND sign to an OR sign 3. The absorption law of Boolean algebra is given by. 2005) LHS= A+A’. (A+B)' = A'. What are maxterms? (May. A+AB=A. Show that A+A’. Define duality property.B)' = A'+B' 2) The complement of a sum term is equal to the product of the complements. Changing each OR sign to an AND sign 2. Duality property states that.They are. Complementing any 0 or 1 appearing in the expression For Example: A+ A’= 1 is A. 2008) . A’= 0 43.B = A+B using the theorems of Boolean algebra.
Convert the following function into sum of product form (AB+C)(B+C’D).M6 = ПM (1.15) Write the maxterms corresponding to the logical expression = (A + B + C’) (A + B' + C') (A' + B' + C) =M1.C’D+ C. = (AB. 2008) [A + A =1] Y = (A + B + C’) (A + B' + C') (A' + B' + C) . 6) 47. B= 1] [C. Find the minterms of the logical expression Y= A'B'C' +A'B'C +A'BC +ABC' Y = A'B'C' + A'B'C + A'BC + ABC' = m0 + m1 +m3 +m6 = ∑m (0.B+ B. 6. 46. 5.Each individual term in standard POS form is called maxterms. Convert the given expression in canonical SOP form Y = AC + AB + BC Y = AC + AB + BC = AC (B + B’) + AB (C + C’) + (A + A') BC = ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC = ABC + ABC' +AB'C + AB'C' = m7 + m6 +m5 +m4 = ∑m (4.M3.D)= ∑m( 6.C’= 0] AND each product term having missing literals.C. = m15+ m14+ m13+ m12+ m7+ m6 • 49. by ORing the literals and its complement = AB (C+ C’) (D+ D’) + BC (A+ A’) (D+ D’) + ABC’D = (ABC+ ABC’) (D+ D’) + (ABC+ A’BC) (D+ D’) + ABC’D = ABCD+ ABCD’+ ABC’D+ ABC’D’+ ABCD+ ABCD’+ A’BCD+ A’BCD’ + ABC’D = ABCD+ ABCD’+ ABC’D+ ABC’D’+ A’BCD+ A’BCD’.7.B.C’D) = AB+ BC+ ABC’D [B.C+ AB. 12. 6) (May. 1.13. 3. 7) 48. F(A. 3.14.
(a) F1= xy’+ x’y F1’= (xy’+ x’y)’ = (xy’)’. F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z) (x + y +z') F2' = [x (y'z' + yz)]' = x' + (y'z' + yz)' = x' + (y'z')'(yz)' = x' + (y + z) (y' + z') 51. (b) F2= (xy + y’z + xz) x. F2’ = ((xy + y’z + xz) x)’ = (xy + y’z + xz)’ + x’ = [(xy)’ (y’z)’ (xz)’] + x’ = [(x’+y’) (y+z’) (x’+z’)] + x’ = [(x’y+ x’z’+ 0+ y’z’) ( x’+z’)] + x’ = x’x’y+ x’x’z’+ x’y’z’+ x’yz’+ x’z’z’+ y’z’z’+ x’ = x’y+ x’z’+ x’y’z’+ x’yz’+ x’z’+ y’z’+ x’ = x’y+ x’z’+ x’z’ (y’+ y) + y’z’+ x’ = x’y+ x’z’+ x’z’ (1) + y’z’+ x’ = x’y+ x’z’+ y’z’+ x’ [x+ x = x]. Find the complements for the following functions (a) F1= xy’+ x’y. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz). By applying De-Morgan's theorem.50. (b) F2= (xy + y’z + xz) x. (x’y)’ = (x’+y) (x+y’) = x’x+ x’y’+ yx+ yy’ = x’y’+ xy. [x. x = x] [x+ x’= 1] (Nov. 2007) .
x’+ xy. w’+ w’y. w’+ w’x’. w’+ xy. z’+ w’y.z’ = w’x’+ w’y+ w’xy+ w’x’y’+ w’x’+ w’x’y+ 0 + x’y’+ w’x’z’+ w’yz’+ xyz’+ x’y’z’ = w’x’+ w’y+ w’xy+ w’x’y’+ w’x’y+ x’y’+ w’x’z’+ w’yz’+ xyz’+ x’y’z’ = w’x’( 1+ y’+ y+ z’)+ w’y( 1+ x+ z’)+ x’y’(1+ z’)+ xyz’ = w’x’(1)+ w’y(1)+ x’y’(1)+ xyz’ = w’x’+ w’y+ x’y’+ xyz’ Minimization of Boolean Expressions : 53.= x’y+ x’+ x’z’+ y’z’ = x’(y+1) + x’z+ y’z’ = x’ (1+z) + y’z’ = x’+ y’z’ [y+1= 1] [y+1= 1] 52. x’+w’y. = [((AB)'C)'' D]' . x’+ x’y’. x’+ w’x’. w’+ x’y’. Obtain the complement of f = wx’y + xy’+ wxz using De Morgan’s theorem. 2006) f’ = (wx’y + xy’+ wxz)’ = (wx’y)’ (xy’)’ (wxz)’ = (w’+x+ y’) (x’+ y) (w’+ x’+ z’) = (w’x’+ w’y+ xx’+ xy+ x’y’+ yy’) (w’+ x’+ z’) = (w’x’+ w’y+ xy+ x’y’) (w’+ x’+ z’) = w’x’.H. z’+ x’y’.S. Simplify the following using De Morgan's theorem [((AB)'C)'' D]' = ((AB)'C)'' + D' = (AB)' C + D' = (A' + B’) C + D' [(AB)' = A' + B'] L. z’+ xy. (May.
Reduce A'B'C' + A'BC' + A'BC A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C = A'C' + A'BC = A'(C' + BC) = A'(C' + B) 55.A = 1] [(AB)' = A' + B'] [A + AB' = A + B] [A + A'B = A + B] Y = (A + B) (A + C’) (B' + C’) = (AA' + AC +A'B +BC) (B' + C') = (AC + A'B + BC) (B' + C’) = AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC' = AB'C + A'BC' .A'C [A + A'B = A + B] [A + A' = 1] AB + (AC)' + AB’C (AB + C) = AB + (AC)' + AAB'BC + AB'CC = AB + (AC)' + AB'CC = AB + (AC)' + AB'C = AB + A' + C' =AB'C = A' + B + C' + AB'C = A' + B'C + B + C' = A' + B + C' + B'C = A' + B + C' + B' = A' + C' + 1 =1 57.54.A' = 0] A.A'C [A. Reduce AB + (AC)' + AB’C (AB + C) Reduce A. = 0.A' = 0] [A. [A + 1 =1] Simplify the following expression Y = (A + B) (A + C’) (B' + C’) [A.C =0 56.A' = 0] [A.
x’= 0] (May. 2007) [1 + B = 1] .A' = 0] Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC (X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y’) (X' + Y) = (X + Y’) (X + Y’) (X'Y) = (X + Y’) (X'Y) = X.B = A (1 + B) = A.Proved 60.Y =0 59.X' + Y'.B = A + A. ABC + ABC' + AB'C + A'BC = AB(C + C') + AB'C + A'BC = AB + AB'C + A'BC = A (B + B'C) + A'BC = A (B + C) + A'BC = AB + AC + A'BC = B (A + C) + AC = AB + BC + AC = AB + AC +BC . Show that (X + Y' + XY)( X + Y')(X'Y) = 0 [A + A'B = A + B] [A + A = 1] [A.. 61. Simplify the following Boolean function: (a) x (x’+y) (b) xy + x’z + yz..X'. [x. (a) x (x’+y) = xx’+ xy = xy.A + A. Reduce A (A + B) A (A + B) = A.58.A = 1] [A.
63. y’= 0] . 62.x+ xy’+ yx+ yy’ = x+ xy’+ xy+ 0 = x (1+ y’+ y) = x (1) = x. = xy + x’z + yz( x+ x’) = xy + x’z + xyz + x’yz = xy + xyz + x’z +x’yz = xy (1+ z) + x’z (1+y) = xy+ x’z. = xy + x’z + yz (1) = xy + x’z + yz (x+ x’) = xy + x’z + xyz + x’yz Re-arranging. b) xy + x’z + yz. [1+z= 1] [x+ x’= 1] [ 1+y= 1 ] [ x.(b) xy + x’z + yz. = xy + xyz + x’z +x’yz = xy (1+ z) + x’z (1+y) = xy (1) + x’z (1) = xy+ x’z. x= x]. [ y. Simplify the following expression Y = (A + B) (A + C) (B + C) = (A A + A C + A B + B C) (B + C) = (A C + A B + B C) (B + C) =ABC+ACC+ABB+ABC+BBC+BCC [1+y= 1]. 2010) [1+y= 1] a) (x+ y) (x+ y’) = x. Simplify the following Boolean functions to a minimum number of literals a) b) (x + y) (x + y’) xy + x’z + yz (May.
67. with each squares representing one minterm of the function. What are the methods adopted to reduce Boolean function? i) Karnaugh map ii) Tabular method or Quine Mc-Cluskey method iii) Variable entered map technique. 2008) Simplification Of Boolean functions using K-map & Tabulation Methods : 66. Find the minterm of xy+yz+xy'z = xy+ yz+ xy’z = xy+ z (y+ xy’) = xy+ z (y+ x) 65. 68. 2009) Simplify the following Boolean expression to a minimum number of literals: (Nov. What is meant by three variable map? . What is a Karnaugh map? A Karnaugh map or k map is a pictorial form of truth table. A’B’+ A’C’D’+ A’B’D+ A’B’CD’ = A’B’ (1+D) + A’C’D’+ A’B’CD’ = A’B’ (1) + A’C’D’+ A’B’CD’ = A’B’+ A’C’D’+ A’B’CD’ = A’B’+ A’B’CD’+ A’C’D’ = A’B’ (1+CD’) + A’C’D’ = A’B’ (1) + A’C’D’ = A’B’+ A’C’D’ = A’ (B’+C’D’) [1+ x = 1] [1+ x = 1] [x+ x’y = x+ y] (May. in which the map diagram is made up of squares.=ABC 64.
72. What are called don’t care conditions? In some logic circuits certain input conditions never occur. 2009) Therefore. What is an essential implicant? If a min term is covered by only one prime implicant. 71. Simplify the following Boolean function by Karnaugh map method: F (A. it can be either high or low. 69.) more than six variable involving expressions are not reduced. D) = ∑m (1.e. the prime implicant is said to be essential. hence the map consists of 8 squares. What is a prime implicant? A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.Three variable map have 8 minterms for three variables. therefore the corresponding output never appears. one for each minterm. . C. 70. 13. These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care conditions or incompletely specified functions. In such cases the output level is not defined. 15) (May. B. 5. What are the drawbacks of Karnaugh map? (Nov. 9. F= ABD+ C’D+ ABC’ 73. 2007) The drawbacks of the K-map method are Generally it is limited to six variable map (i. 12. i.
iv. iii. 76. iii. It is not suitable for computer reduction. iii. ii. It is more suitable for class room teachings on logic simplification. The disadvantages are. Digital computers can be used to obtain the solution fast. Explain or list out the advantages and disadvantages of K-map method? It is a fast method for simplifying expression up to four variables. ii. Why we go in for tabulation method? This method can be applied to problems with many variables and has the advantage of being suitable for machine computation. It is not suitable for computer reduction. The advantages of the K-map method are The disadvantages of the K-map method are i. iii. It gives a visual method of logic simplification. i. Essential prime implicants. 1 (or) don’t care terms. K-maps are not suitable when the number of variables involved exceed four. The advantages are. 75. v. i. The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form. List out the advantages and disadvantages of Quine Mc-Cluskey method? This is suitable when the number of variables exceed four. Care must be taken to fill in every cell with the relevant entry. . Care must be taken to fill in every cell with the relevant entry. Prime implicants and essential prime implicants are identified fast. 1 (or) don’t care terms. ii.such as a 0. iv. 74. Suitable for both SOP and POS forms of reduction.ii. such as a 0. which are not evident in K-map. can be clearly seen in the final results.
i. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. AND gate OR gate NOT gate The three basic logic gates are Which gates are called as the universal gates? What are its advantages? The NAND and NOR gates are called as the universal gates. 78. then it is a negative logic system. ii. Logic Gates : 77. (Nov. 1 and 0. The Quine Mc-Cluskey method is essentially a computer reduction method. On the other hand. What is a Logic gate? Logic gates are the basic elements that make up a digital system. v. iii. It is much slower. 81. the system is called positive logic system. if the lower voltage represents a 1 and the higher voltage represents a 0. 79. 2003) In binary logic. Bubbled OR gate is equal to-------------NAND gate . If the higher of the two voltages represents a 1 and the lower voltage represents a 0. What are the basic digital logic gates? • • • 80. two voltage levels represent the two binary digits. iv. Distinguish between positive logic and negative logic. These gates are used to perform any type of logic application. Requires several grouping and steps as compared to K-map. Lengthy procedure than K-map. No visual identification of reduction process.
Y= (A . Bubbled AND gate is equal to-------------NOR gate 83.82. We will get complemented output when all applied inputs . 88. How will you use a 4 input NAND gate as a 2 input NAND gate? (Nov. Show that a positive logic NAND gate is the same as a negative logic NOR gate. 2005) (May. 2003. How will you use a 4 input NOR gate as a 2 input NOR gate? (May. 2004. What happens when all the gates is a two level AND-OR gate network are replaced by NOR gate are complemented. we can use 4-input NAND gate as a 2 input NAND gate. 84. Nov. 2004.B)’ = A’ +B’ Y= A’ + B’ is the logic expression for negative logic NOR gate. 85. Realize OR gate using NAND gate. 86. we can use 4-input NOR gate as a 2 input NOR gate. (May. 2003) By connecting unused inputs to logic 0.B)’ Y= (A . 87. Nov. What is meant by a functionally complete set of logic gates? (May. IT) The output will change. 2002) By connecting unused inputs to logic 1. (Nov. 2005) A set of logic gates by which we can implement any logic function is called functionally complete set of logic gates. 2004) Logic expression for NAND gate is.
2. Inputs A B Outputs Sum Carry (S) (C) . It has two inputs that represent the two bits to be added and two outputs. Define Combinational circuit. with one producing the SUM output and the other producing the CARRY. (May 2009) A combinational circuit consists of logic gates whose outputs at anytime are determined directly from the present combination of inputs. 3. without regard to previous inputs.OR gate using AND gate CHAPTER 2 COMBINATIONAL LOGIC 1. What is a half-adder? A half-adder is a combinational circuit that can be used to add two bits. Give the truth table for a half adder.
represent the significant bits to be added. (Nov. What is a full adder? (May. 05. . The block diagram of full adder is given by. Two of the input variables. It consists of 3 inputs and 2 outputs. Draw the logic diagram of a half-adder. Nov 09) 6. The third input represents the carry from previous lower significant position. 2007) A full adder is a combinational circuit that forms the arithmetic sum of three input bits. 0 1 0 1 0 1 1 0 0 0 0 1 From the truth table of a half adder derive the logic equation 5.0 0 1 1 4.
. Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Sum (S) 0 1 1 0 1 0 0 1 Outputs Carry (Cout) 0 0 0 1 0 1 1 1 8. From the truth table of a full adder derive the logic equation 9. The BORROW output here specifies whether a ‘1’ has been borrowed to perform the subtraction. 10.7. Draw the circuit of a full-adder. Give the truth table for a full adder. What is half-Subtractor? A half-subtractor is a combinational circuit that can be used to subtract one binary digit from another to produce a DIFFERENCE output and a BORROW output.
What is a full-subtractor? A full subtractor performs subtraction operation on two bits. 2005) 12. a minuend and a subtrahend.11. Outputs Difference Borrow A B (D) (Bout) 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 From the truth table of a half-Subtractor derive the logic equation 13. . Draw the circuit of a half-subtractor. and also takes into consideration whether a ‘1’ has already been borrowed by the previous adjacent lower minuend bit or not. Give the truth table for a half Subtractor. 14. Inputs (Nov.
There are two outputs. there are three bits to be handled at the input of a full subtractor. namely the DIFFERENCE output D and the BORROW output Bo. From the truth table of a full-Subtractor derive the logic equation 17. namely the two bits to be subtracted and a borrow bit designated as B in. Draw the circuit of a full-subtractor.As a result. 2004) Outputs Difference( Borrow(Bo D) ut) 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 1 16. . 15. The BORROW output bit tells whether the minuend bit needs to borrow a ‘1’ from the next possible higher minuend bit. Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1 (Nov. Give the truth table for a full-subtractor.
An error is detected if the checked parity does not correspond with the one transmitted. Draw the circuit diagram for 3-bit parity generator. 20. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. The message. 21. 2007) .18. including the parity bit is transmitted and then checked at the receiving end for errors. What is BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. A parity bit is an extra bit included in a binary message to make the number of 1’s either odd or even. What is Binary parallel adder? A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel. 19. (Nov. What are Parity Generator/ Checker? A parity bit is used for the purpose of detecting errors during transmission of binary information.
What is the need for code conversion? If two systems working with different binary codes are to be synchronized in operation. 24. (May. Depending upon the relative magnitudes of the two numbers. What is code converter? It is a circuit that makes the two systems compatible even though each uses a different binary code. It receives two n-bit numbers A and B as inputs and the outputs are A>B.22. then we need digital circuit which converts one system of codes to the other. A=B and A<B. (Nov. What is Magnitude Comparator? A Magnitude Comparator is a combinational circuit designed primarily to compare the relative magnitude of two binary numbers. the reference value. One example is a BCD to Xs3 converter. It is a device that converts binary signals from a source code to its output code. List out the applications of comparators? • • • 25. The process of conversion is referred to as code conversion. 2008) 23. Comparators are used as a part of the address decoding circuitry in They are used to actuate circuitry to drive the physical variable towards They are used in control applications. 2009) The following are the applications of comparator computers to select a specific input/output device for the storage of data. Draw the logic diagram of 4 bit even parity checker. one of the outputs will be high. . 26.
. 3. 2006) 1. 2. (May. 30. 2. 2006.27. It is used to represent and document digital systems in a form that can be read by both humans and computers. (May. 2007) Logic Synthesis is the automatic process of transforming a high level language description such as HDL into an optimized netlist of gates that perform the operations specified by the source code. What is logic synthesis in HDL? (Nov. It can be used to represent logic diagrams. It can be used to represent logic diagrams. Mention any two uses of HDL. It is specifically oriented to describe hardware structures and behaviors. 2006) The gray code is often used in digital systems because it has the advantage that only bit in the numerical representation changes between successive. 2006. It is the process of deriving a list of components and their interconnections from the model of a digital system described in HDL. 29. Nov. List the important features of HDL. (Nov. HDL is a language that describes the hardware of digital systems in textural form. Construct a 4-bit binary to gray code converter circuit and discuss its operation. Boolean expressions and other more complex digital circuits. Boolean expressions and other complex digital circuits. 28. May 2010) 1.
The general structure of decoder circuit is – (May. . (ie) the available logic diagram is analyzed step by step and finding the Boolean function. CHAPTER 3 DESIGN WITH MSI DEVICES Decoders & Encoders 1. What do you mean by analyzing a combinational circuit? The reverse process for implementing a Boolean expression is called as analyzing a combinational circuit.3. The language content can be stored and retrieved easily and processed by computer software in an efficient manner. 2. What is decoder? 09) A decoder is a combinational circuit that decodes the binary information on ‘n’ input lines to a maximum of 2n unique output lines. 4. It is used to represent and document digital systems in a form that can be read by both humans and computers.
. Decoder outputs can be used to drive a display system. The general structure of encoder circuit is – 4. An encoder is a combinational circuit that converts binary information from 2n input lines to a maximum of ‘n’ unique output lines.3. A decoder is a combinational circuit that decodes the binary information on ‘n’ input lines to a maximum of 2n unique output lines. 5. What are the functions of encoders and decoders? 2006) An encoder is a combinational circuit that converts binary information from 2n input lines to a maximum of ‘n’ unique output lines. Decoders are used in counter system. What is encoder? 10) (May. 2. They are used in analog to digital converter. 6. List out the applications of decoder? 1. 3. Distinguish between decoder and encoder (Nov.
2. The input code generally has a fewer bits than the output code. . May. Encoder The input lines generate the binary code. Implement the logic function f= ∑m (0. A priority encoder is an encoder that includes the priority function. 2008. 7. the input having the highest priority will take precedence.No Decoder 1 One of the input lines is activated corresponding 2 to the binary input Input of the decoder is an encoded information presented as ‘n’ input producing 2n possible 3 4 outputs. The input code generally has more bits than the output code. 2006) 8. corresponding to the input value Input of the encoder is a decoded information presented as ‘2n’ inputs producing ‘n’ outputs. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time. 3. What is priority encoder? 2007) (May.S. 6) using a decoder (May.
What is the function of the enable input in a Multiplexer? The function of the enable input in a MUX is to control the operation of the unit.B’ using a suitable multiplexer. The selection of a particular input line is controlled by a set of selection lines. 11. (Nov. 06. 10. Implement the logic function f= AB + A’.D0 0 1 x x x Inputs D1 D2 0 0 0 0 1 0 x 1 x x D3 0 0 0 0 1 Y1 x 0 0 1 1 Outputs Y0 x 0 1 0 1 V 0 1 1 1 1 Multiplexers & Demultiplexers 9. The basic multiplexer has several data-input lines and a single output line. (Nov. 2005) f= AB + A’B’ = ∑m (3. Normally there are 2n input lines and n selection lines. What is a multiplexer? May 10) A multiplexer is a digital switch which allows digital information from several sources to be routed into a single output line. 0) .
14. 13. It can be used in communication systems e. 09) . Data routing (May. 07. How can a multiplexer be used to convert 8-bit parallel data into serial form? Draw the circuit and briefly explain. therefore D0 through D7 bits are available at the output of the multiplexer as serial output. Mention any two applications of multiplexers. binary counter is used to derive the select inputs of the multiplexer so that as the binary counter increments its count. It can be used to realize a Boolean function 2. the next bit is available at the output of the multiplexer. The binary counter counts from 000 to 111.g. time division multiplexing.12. 1. Mention the uses of multiplexer. 1. May.. 2006) Here. (May.
The output line that gets the information present on the input line is decided by the bit status of the selection lines. What is a demultiplexer? (May 2008) A demultiplexer is a combinational logic circuit with an input line. (Nov. 2008) 16. 3. 15. . Construct a 16×1 multiplexer with two 8×1 multiplexer and 2×1 multiplexer.2. Logic function generator Control sequencer Parallel-to-serial converter. 4. It routes the information present on the input line to any of the output lines. 2n output lines and n select lines.
Demultiplexer is a circuit which converts one input to many outputs. Demultiplexer is otherwise called as Data distributor. 18. . A decoder with enable can function as a Demultiplexer if the enable line E is taken as a data input line A and B are taken as selection lines. 1. If the enable line E is taken as a data input line A and B are taken as selection lines. 21. One simple application is binary to Decimal decoder.17. then it is a demultiplexer. Can a decoder function as a Demultiplexer? Yes. 19. 20. How can a decoder be converted into a demultiplexer? (Nov. Not only in computers. Give other name for Multiplexer and Demultiplexer. Demultiplexer is used in computers when a same message has to be sent to different receivers. Give the applications of Demultiplexer. but any time information from one source can be fed to several places. 2005) Decoder is a circuit which converts one form of code into another. Mention the uses of Demultiplexer. It finds its application in Data transmission system with error detection. Multiplexer is otherwise called as Data selector. 2.
(May. 24. Memory & Programmable logic . Distinguish between decoder and demultiplexer. 09) S. The selection of specific output line is controlled by the value of selection lines. There are no selection lines. 23. Design 8: 1 multiplexer using two 4:1 multiplexers. Decoder Decoder is a many input to many output device.No 1 2 Demultiplexer Demultiplexer is a one input to many output devices. Nov. Design 1: 8 demultiplexer using two 1: 4 demultiplexers. 04.22.
25. 29. What is RAM? A memory unit is a collection of storage cells together with associated circuits needed to transfer information in and out of the device. SRAM is easier to use and has shorter read and write cycle. 2. The dynamic RAM (DRAM) stores the binary information in the form of electric charges on capacitors. Hence. Define address and word Each bit combination of the input variable is called on address. The capacitors are provided inside the chip by MOS transistors. Explain SRAM? 1. 1. Dynamic RAM . Static RAM (SRAM) consists of internal latches that store the binary information. Static RAM 2. 26. List the types of RAM. The memory capacity of a static RAM varies from 64 bit to 1 mega bit. The time it takes to transfer information to or from any desired random location is always the same. The stored information remains valid as long as the power is applied to the unit. Each bit combination that comes out of the output lines is called a word. 27. 3. Dynamic RAM 28. the name random-access memory (RAM). Explain DRAM? 1.
3 Differentiate volatile and non-volatile memory? Volatile memory They are memory units which loses stored information when power is turned off. SRAM and DRAM Non-volatile memory It retains stored information when power is turned off. Cost is more This makes system design complicated.g. 1 2 32.No 1 2 Differentiate static RAM and dynamic RAM. hence faster memories. Extra hardware is required to control refreshing. What are the advantages of RAM? The advantages of RAM are . S. Dyanamic RAM It contains more memory cells per unit area. 5 31.g. Cost is less. The stored charges on the capacitors tend to discharge with time and the capacitors must be tending to discharge with time and the capacitors must be periodically recharged by refreshing the dynamic memory. It consists of number of flip-flops. It consists of MOSFET and capacitor for each cell. after every few milliseconds. 3. Its access time is less. E. No.2. Its access time is greater than static RAM It stores the data as a charge on the capacitor. Refreshing circuitry is required to maintain the charge on the capacitors every time 4 Refreshing circuitry is not required. E. Static RAM It contains less memory cells per unit area. DRAM offers reduced power consumption and larger storage capacity in a single memory chip. 30. Each flip-flop stores one bit. Magnetic disc and ROM S.
What is ROM? A Read-only memory (ROM) is essentially a memory device in which permanent binary information is stored. 2.1. the address. Compatibility 5. 36. Both memory IC’s are selected simultaneously by common chip select signal to access entire expanded word at time. The binary information must be specified by the designer and is then embedded in the unit to form the required interconnection pattern. The memory expansion can be achieved in two ways: . Economy. it stays within the unit even when power is turned OFF and ON again. In what ways memory expansion can be achieved? 1. Fast operating speed 3. How memory expansion can be achieved by expanding memory capacity? The memory capacity can be increased by connecting two or more memory IC’s in parallel ie. Once the pattern is established. By expanding memory capacity. Low power dissipation 4. Masked ROM. Each IC is selected by the separate chip select signal generated by the address decoder. How memory expansion can be achieved by expanding word size? The word size of the memory IC can be increased by connecting two memory IC’s in such a way that their data bus is in series and address bus in parallel. Non-destructive read out 2.. 34. List the types of ROM. data and control lines are connected in parallel to all memory IC’s. By expanding word size. 1. 33. 35. 37.
It uses the fuses with material like nichrome and polycrystalline. It can be programmed by the user by a special EPROM programmer. The chip can be reprogrammed. It is ideally suited for product development. Explain masked ROM. The EPROM (Erasable PROM). 39. The PROM’s are one-time programmable. The PROM programmer selectively burns the fuses according to the bit pattern to be stored. the information stored is permanent. it is not possible to erase selective information. Electrically Erasable ROM (EEROM) 38. In masked ROM. when erased the entire information is lost. They store 1’s and 0’s as packets of charge in a buried layer of IC chip. The information stored can be erased by exposing the chip to Ultraviolet through its quartz window for 15 to 20 minutes.2. the ROM is to satisfy. The procedure for fabricating a ROM requires that the customer fill out the truth table. Explain EEPROM. 41. Erasable ROM (EPROM) 4. In EPROM’s. once programmed. Explain EPROM. The blowing of fuses according to the truth table is called programming of ROM. college laboratories. mask programming is done by the manufacturer during the last fabrication process of the unit. . Programmable ROM (PROM) 3. 40. The PROM (Programmable Read-only memory). The user can blow the fuses by passing around 20 – 50 mA of current for a period of 5 – 20 µsec. uses MOS circuitry. Explain PROM. etc. allows user to store data/ program.
Explain PROM? The Programmable read-only memory has a fixed AND array constructed as a decoder and programmable OR array. 5. Therefore a voltage as low as 20. Explain PAL? . FPGAs: Field programmable Gate Arrays. List basic types of programmable logic devices. PLA: Programmable logic Array. PROM: Programmable Read only memory. 1. 3. What is a Programmable logic device (PLD)? A Programmable logic device (PLD) is an integrated circuit with internal logic gates that are connected through electronic fuses. which is made very thin (< 200Å). 4. The programmable OR gates implement the Boolean function in sum of minterms. also uses MOS circuitry. Data is stored as charge or no charge on an insulating layer.The EEPROM (Electrically Erasable PROM). It is divided into an AND array and an OR array to provide an AND-OR sum of product implementation. 43. 2.25V can be used to move charges across the thin barrier in either direction for programming or erasing ROM. 45. It has chip erase mode by which the entire chip can be erased in 10 msec. 42. CPLDs: Complex programmable Logic Devices. since the information can be changed by using electrical signals. PAL: Programmable Array Logic. Hence EEPROM’s are most expensive. It allows selective erasing at the register level rather than erasing all the information. Programming the device involves blowing the fuses along the paths that must be disconnected so as to obtain a particular configuration. 44.
46. PLD’s (Programmable Logic Array) It is a device that includes both AND and OR gates with in a single IC package PLD’s does not provide full decoding of the variable and does not generate all the minterms. S. which are logically summed in each OR gate.No What are the difference between PLA and PAL? PLA PAL (Nov. Differentiate ROM & PLD’s. where both the AND and OR arrays can be programmed. The product term in the AND array may be shared by any OR gate to provide the required sum of product implementation.No ROM (Read Only Memory) 1. Explain PLA The most flexible PLD is the programmable logic array (PLA).It has a programmable AND array and a fixed OR array. 47. The AND gates are programmed to provide the product terms for the Boolean functions.It is a device that includes both 1 the decoder and the OR gates with in a single IC package ROM does full decoding of the 2 variables and generates all the minterms 48. 2006) . S.
Number of inputs b. It is less flexible than PLA. 52. PLA. 09) PAL OR array is fixed and AND array is programmable Cheaper and simpler AND array can be programmed to get desired minterms Any Boolean functions in SOP form can be implemented using PLA Give differences between PROM.No 1 program. PROM AND array is fixed and OR array is programmable Cheaper and simpler to use All minterms are decoded Only Boolean functions PLA Both AND and OR arrays are programmable Costliest and complex AND array can be programmed to get desired minterms Any Boolean functions in SOP form can be implemented using PLA 2 3 4 in standard SOP form can be implemented using PROM 50. and PAL. Number of products terms c. Number of outputs The size of a PAL is specified by the 51. What is meant by memory decoding? The memory IC used in a digital system is selected or enabled only for the range of addresses assigned to it. PAL is a programmable logic device with a fixed OR array and programmable AND array. PAL is easier to program as only AND gates are programmable. as both AND and OR array are programmable.PLA is a device with a 1 programmable AND array and programmable OR array PLA is comparatively difficult to 2 3 49. What are the terms that determine the size of a PAL? a. S. It is flexible. (Nov. What is access and cycle time? .
. = 210 = 1024 bytes. 2008) HDL for Combinational Circuits 55. The language is not case sensitive. What are the features of VHDL? The features of VHDL are 1. 54. Sequential language 2. 2. 56. The VHDL language has a combination of the following language. What is VHDL? VHDL is a hardware description language that can be used to model a digital system at many level of abstraction. 53. VHDL supports design library. Timing specification 5.The access time of the memory is the time to select word and read it. 2007) When the output exceeds the capacity of accumulator. The cycle time of a memory is a time required to complete a write operation. Concurrent language 3. What is the maximum range of a memory that can be accessed using 10 address lines? Maximum range of memory = 2 address lines. 3. Waveform generation language. When an overflow condition will encounter in an accumulator register? (Nov. (May. ranging from the algorithmic level to the gate level. Net-list language 4. 1. VHDL has powerful constructs.
What is gate level modelling?
This technique uses primitive gates and user-defined modules. It describes a schematic diagram in a textural form. 58. What are the modelling techniques available to build HDL module? (May, 2007) 1. Gate level modeling using instantiation of primitive gates and user-defined modules. 2. Data flow modeling, using continuous assignment statements with keyword ‘assign’. 3. Behavioral modeling using procedural assignment with keyword ‘always’. 59. Define entity? Entity gives the specification of input/output signals to external circuitry. An entity is modeled using an entity declaration and at least one architecture body. Entity gives interfacing between device and others peripherals. 60. List out the different elements of entity declaration? 1. entity_name 2. signal_name 3. mode 4. in: 5. out: 6. input 7. buffer 8. signal_type 61. What do you meant by concurrent statement?
The different elements of entity declaration are:
Architecture contains only concurrent statements. It specifies behavior, functionality, interconnections or relationship between inputs and outputs. 62. What are operators used in VDHL language? Logical operators Relational operator Shift operators : AND, OR, NOT, XOR, etc., : equal to, <less than etc., : SLL- Shift Left Logical, ROR- Rotate Right Logical etc.,
There are different types of operators used in VHDL language
Arithmetic operators : Addition, subtraction etc., Miscellaneous operators: <= assign to etc., 63. Define VHDL package? A VHDL, package is a file containing definitions of objects which can be used in other programs. A package may include objects such as signals, type, constant, function, procedure and component declarations.
SYNCHRONOUS SEQUENTIAL CIRCUITS
What is sequential circuit? The circuits in which the output variables depend not only on the present input but
they also depend upon the past history of these input variables are known as sequential circuits.
Block diagram of sequential circuit
The memory elements are connected to the combinational circuit as a feedback path. The present state and the external inputs determine the outputs and the next state of the sequential circuit. 2. What are the differences between sequential and combinational logic circuits? (Nov, 2004; Nov, 2007; May 2010) S.No 1 2 3 4 5 3. Combinational logic Output depends on present input Memory unit is not required Faster in speed Easy to design Ex: Adders, Subtractor, MUX, DEMUX, Encoder, Decoder etc.., List the classifications of sequential circuit. 1. Synchronous sequential circuit. 2. Asynchronous sequential circuit. 4. What is Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time. 5. Mention one advantage and disadvantage of Asynchronous sequential circuit. Sequential logic Output depends not only on present input but also depend upon the past inputs. Memory unit is required to store past input variables Slower Hard Ex: Shift Registers, Counters
(Nov, 2005) Advantage: Because of the absence of clock it can operate faster than synchronous sequential circuits. Disadvantage: The charge in input signal can affect memory elements at any instant of time and it is more difficult to design. 6. Distinguish between synchronous and asynchronous sequential logic circuits. (Nov, 2002; Nov, 2003; May, 2005) S.No 1 Synchronous sequential circuits Memory elements are clocked flipflops The change in input signals can affect memory element upon activation of clock signal. The maximum operating speed of 3 4 7. clock depends on time delays involved. Easier to design What is a clocked sequential circuit? Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they don’t cause instability problems. Asynchronous sequential circuits Memory elements are either unclocked flip-flops or time delay elements. The change in input signals can affect memory element at any instant of time. Because of the absence of clock, it can operate faster than synchronous circuits. More difficult to design
8. What is called latch? Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored.
Enable signal is provided with the latch. 9. Draw the internal circuit of a NOR gate latch and derive the truth table. When enable signal is not activated. Draw the logic diagram of D-type latch. 2007) 10. When enable signal is active. 2006) The SR latch is a digital circuit with two inputs S and R and two cross-coupled NOR gates. (May. . Truth table: S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 0 1 1 x x State No Change (NC) Reset Set Indeterminat e * (Nov. output changes with output. input changes does not affect output.
What do you mean by triggering of flip-flop? The state of a flip-flop is switched by a momentary change in the input signal. List different types of flip-flops. 2010) Latch is a sequential device that checks all of its inputs continuously and changes its outputs according to any time. An edge-triggered Flip-Flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock. (May.11. 13. Differentiate Flip-flops from Latches. . 12. i) SR flip-flop ii) JK flip-flop iii) D flip-flop iv) T flip-flop 14. This momentary change is called a trigger and the transition it causes is said to trigger the flip-flop. What is flip-flop? Flip-Flops are synchronous bistable devices (has two outputs Q and Q’). independent of a clocking signal. Flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by clocking signal.
(Nov. 18. 17. . 2004) 16. Draw the logic diagram for clocked D Flip-Flop. Draw the logic diagram for clocked JK Flip-Flop. What is a characteristic table? A characteristic table defines the logical property of the flip-flop by describing its operation in tabular form.15. Draw the diagram of a clocked SR flip-flop using four NAND gates.
09. . 21. 2008) 20. Draw the logic diagram for T Flip-Flop. (May. Nov. then the output toggles continuously. This condition is called a race around condition. What is race around condition? How can it be avoided? (May. 09) In a JK latch.19. Draw the logic diagram for Master-slave SR Flip-Flop. when J and k are both high.
Inputs S 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 Next State Qn+1 0 0 1 x 1 0 1 x (Nov. Present State Qn 0 0 0 0 1 1 1 1 Inputs J 0 0 1 1 0 0 1 1 K 0 1 0 1 0 1 0 1 Next State Qn+1 0 0 1 1 1 0 1 0 24.Due to this. Present State Qn 0 0 0 0 1 1 1 1 23. Present State Qn Input D Next State Qn+1 . the output changes only at the positive edge or a negative edge of the clock. To avoid this condition. 2008) Write down the characteristic table of JK flip flop. in the positive half cycle of the clock pulse (Enable). if J and K both are HIGH. an edge triggered or pulse triggered JK flip-flop is created. Write down the characteristic table of SR flip flop. In this flip-flop. 22. Write down the characteristic table of D flip flop. then the output toggles continuously.
Give the excitation table of a T flip-flop. A table which lists the required inputs for a given chance of state is called an excitation table. Present State Qn 0 0 1 1 Input T 0 1 0 1 0 1 0 1 Next State Qn+1 0 1 1 0 26. What is an excitation table? During the design process we usually know the transition from present state to next state and wish to find the flip-flop input conditions that will cause the required transition.25. Give the excitation table of a SR flip-flop. Present State Qn 0 0 1 1 28. 27. Next State Qn+1 0 1 0 1 Inputs S 0 1 0 x R x 0 1 0 Give the excitation table of a JK flip-flop. 0 0 0 1 1 0 1 1 Write down the characteristic table of T flip flop. Present Next Input . Present State Qn 0 0 1 1 Next State Qn+1 0 1 0 1 Inputs J 0 1 x x K x x 1 0 29.
IT) . 2002. Characteristic Equation: Qn+1= JQ’+ K’Q. 2003) 31. Derive the characteristic equation of a JK flip-flop.30. Present State Qn 0 0 1 1 Next State Qn+1 0 1 0 1 T 0 1 1 0 Input D 0 1 0 1 (May. State State Qn Qn+1 0 0 0 1 1 0 1 1 Give the excitation table of a D flip-flop. 32. (Nov. Derive the characteristic equation of a D flip-flop.
33. IT) Characteristic equation: Qn+1= TQn’+ T’Qn 34.Characteristic Equation: Qn+1= D. Derive the characteristic equation of a T flip-flop. 35. 2004. state. How will you convert a SR flip-flop into D flip-flop? Input D 0 Present state Qn 0 Next state Qn+1 0 Flip-Flop Inputs S 0 R x What is the difference between truth table and excitation table? i) An excitation table is a table that lists the required inputs for a given change of . ii) A truth table is a table indicating the output of a logic circuit for various input states. (May.
0 1 1 1 0 1 0 1 1 0 1 x 1 0 0 SR to D Flip-Flop 36. How will you convert a SR flip-flop into JK flip-flop? Inputs J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Present state Qn 0 1 0 1 0 1 0 1 Next state Qn+1 0 1 0 0 1 1 1 0 Flip-Flop Inputs S R 0 x x 0 0 x 0 1 1 0 x 0 1 0 0 1 .
How will you convert a JK flip-flop into T flip-flop? Input T 0 0 1 1 Present state Qn 0 1 0 1 Next state Qn+1 0 1 1 0 Flip-Flop Inputs J K 0 x x 0 1 x x 1 .SR to JK Flip-Flop 37. How will you convert a SR flip-flop into T flip-flop? Input T 0 0 1 1 Present state Qn 0 1 0 1 Next state Qn+1 0 1 1 0 Flip-Flop Inputs S 0 x 1 0 R x 0 0 1 SR to T Flip-Flop 38.
How will you convert a JK flip-flop into D flip-flop? Input D 0 0 1 1 Present state Qn 0 1 0 1 Next state Qn+1 0 0 1 1 Flip-Flop Inputs J 0 x 1 x K x 1 x 0 JK to D Flip-Flop 40.JK to T Flip-Flop 39. How will you convert a D flip-flop into T flip-flop? Input T 0 0 1 Present state Qn 0 1 0 Next state Qn+1 0 1 1 Flip-Flop Input D 0 1 1 .
43. What is the difference between a Mealy machine and Moore machine? . 2006) The clocked sequential circuits are represented by two models as 1. How will you convert a T flip-flop into D flip-flop? Input D 0 0 1 1 Present state Qn 0 1 0 1 Next state Qn+1 0 0 1 1 Flip-Flop Input T 0 1 1 0 T to D Flip-Flop 42. What are the models used to represent clocked sequential circuits? (Nov.1 1 0 0 D to T Flip-Flop 41. Mealy circuit. 2. Moore circuit.
2005) S. 46. Generally it consists of three section present state. An input change may affect the output of the circuit It requires less number of states for implementing same function. A reduced state table has 14 rows. is called state table. which consists time sequence of inputs. What is the use of state diagram? i) Behavior of a state machine can be analyzed rapidly. 2004) Mealy model Its output is a function of present state as well as present input. What is state table? A table. What is the minimum number of flip-flops needed to build the sequential circuit? 24 ≥ 14. ii) It can be used to design a machine from a set of specification. Define state of sequential circuit? The binary information stored in the memory elements at any given time defines the “state” of sequential circuits. A graphical representation of a state table is called a state diagram. 47. outputs and flip-flop states. next state and output. What is a state equation? (Nov. 48. Define state diagram. 44. . An input change does not affect the output. 49. It requires more number of states for implementing same function.(Nov. May. 45. 4 flip-flops.No Moore model 1 Its output is a function of present 2 3 state only. 2008. Therefore.
the clock pulse is applied simultaneously to all flipflops. a Boolean function specifies the present state. 52. 51. the change of output is given as clock to next flip-flop. The left side of the equation denotes the next state of the flip-flop and the right side. The output of the flip-flops changes state at the same instant. Counters 50. Speed of operation is high Speed of operation is low. What is the difference between synchronous and asynchronous counter? Synchronous counter Clock pulse is applied 1 simultaneously All the flip-flops are clocked simultaneously. What is counter? A counter is used to count pulse and give the output in binary form.No 2 3 4 circuit as number of state increases number of states. 53. The speed of operation is high compared to an asynchronous counter. The change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on. Logic circuit is very simple even for more S. . Here all the flip-flops do not change state at the same instant and hence speed is less. What is an Asynchronous/ ripple counter? In an Asynchronous counter. What is synchronous counter? In a synchronous counter. Design involves complex logic Asynchronous counter Clock pulse is applied to the first flip-flop. the clock pulse is applied to the first flip-flops. as an application equation is an algebraic expression that specifies the condition for a flip-flop state transition. All the flip-flops are not clocked simultaneously.A state equation also called.
56. What is up counter? A counter that increments the output by one binary number each time a clock pulse is applied. What is up/down counter? A counter. What is down counter? A counter that decrements the output by one binary number each time a clock pulse is applied. What is meant by natural count of a counter? By the term natural count of a counter we say that the maximum number of states through which a counter can progress. What is modulo-N counter? (May. depending on a control lead (Up/ down). Parallel to serial data conversion. 58. What is a ripple counter? A ripple counter is nothing but an asynchronous counter. What is meant by modulus of a counter? By the term modulus of a counter we say it is the number of states through which a counter can progress. 60. Auto parking control 3. 55. The digital clock 2. What are the uses of a counter? 1. 57. 2008) . 61. 62. which is capable of operating as an up counter or down counter. A ripple counter is a -----------.54. 59. Ans: Asynchronous. in which the output of the flip-flop changes state like a ripple in water.sequential counter.
66. 65. Clk 1 1 1 1 1 1 1 1 1 Q2 1 1 1 1 0 0 0 0 1 Q1 1 1 0 0 1 1 0 0 1 Q0 1 0 1 0 1 0 1 0 1 (May. six flip-flops are required. 64. Form the truth table for 3-bit binary down counter.A modulo-N counter is a counter of that goes through a repeated sequence of N counts. How many flip-flops are required for designing synchronous MOD50 counter? (May.8? 2n ≥ N 23 ≥ 8 Therefore. five flip-flops are required. What is the minimum number of flip-flops needed to build a counter of modulus. 2004) . 2009) 2n ≥ N 26 ≥ 8 Therefore. three flip-flops are required. 63. The number of flip-flops required for modulo-18 counter is ------2n ≥ N 25 ≥ 18 Therefore.
What is a ring counter? A counter formed by circulating a ‘bit’ in a shift register whose serial output has been connected to its serial input. however. 71. What is Johnson counter? It is a ring counter in which the inverted output is fed into the input. What is a binary counter? (Nov. 68. What are the uses of a ring counter? i) Control section of a digital system. ii) Controlling events. State the relative merits of series and parallel counters. Because of the return to 0000 after a count of 1001. What is BCD counter? A BCD counter counts in binary coded decimal from 0000 to 1001 and back to 0000. 70. 2003) In comparison with parallel counters the serial counters have simple logic circuits.67. serial counters are low speed counters as the clock is propagated through number is flip-flops before it reaches the last flip-flop. 69. An n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2n-1. a BCD counter does not have a regular pattern as in a straight binary counter. 2006) A counter that follows the binary sequence is called binary counter. 73. which occur in strict time sequence. What is a cycle counter? A cycle counter is a counter that outputs a stated number of counts and then stops. (May. . It is also know as a twisted ring counter. 72.
Shift Register 74. 79. What is parallel shifting? In a shift register all the data are moved simultaneously and then the technique is called parallel shifting. 2003) A register capable of shifting its binary information in one or both directions is called shift register. What are the applications of shift registers? (May. i) Temporary data storage ii) Bit manipulations. with the output of one flip-flop connected to the input of the next flip-flop. which activate the shift from one stage to the next. It consists of a group of flip-flops. 80. 78. 77. What is a shift register? (Nov. 75. . How many flip-flops are needed to build an 8-bit register? 2002) 8 -flops are needed to build an 8-bit register. if the data is moved 1 bit at a time in a serial fashion. What is a register? Memory elements capable of storing one binary word. What is serial shifting? In a shift register. which store the binary information. 2005) (Nov. All flip-flops receive common clock pulses. The logical configuration of a shift register consists of a chain of flip-flops in cascade. Write the uses of a shift register. 76. then the technique is called serial shifting.
A serial-in-serial-out shift register can be used to introduce time delay in digital signals.001. 2003) In shift register outputs J and K of previous flip-flop is connected to the inputs of the next flip-flop. How many states are there in a 3-bit ring counter? What are they? (May. A serial-in-parallel-out shift register can be used to convert data in the serial form to the parallel form. 010. we can complement the contents of flip-flop. A parallel-in-serial-out shift register can be used to convert data in the parallel form to the serial form. 82. When complement line is high all J and K inputs will be high and flip-flops will complement the output. 4. A shift register comprises of JK flip-flops. 3. 2007) The number of states in a 3-bit counter is three. 81. 2. 100. How will you complement the contents of the register? (May.1. A shift register can also be used as a counter. . If these lines are connected through OR gate.
Cycles b. Races c. Nov. (May. What are the problems involved in asynchronous circuits? The asynchronous sequential circuits have three problems namely. race condition occurs in asynchronous sequential circuits. a. Hazards 2. Define cycles. 3. What is meant by race? 2003) When two or more binary state variables change their value in response to a change in an input variable. 2004. .CHAPTER 5 ASYNCHRONOUS SEQUENTIAL CIRCUITS 1. If an input change includes a feedback transition through more than unstable state then such a situation is called a cycle.
. For the proper operation of the circuits. 8. The final stable state that the circuit reaches depends on the order in which the state variables change. 04. a race condition may cause the state variables to change in an unpredictable manner.In case of unequal delays. 6. 9. How can a race be avoided? Races can be avoided by directing the circuit through intermediate unstable states with a unique state – variable change. May. What is critical race? Why should it be avoided? variables charge during a state transition. the race is called non-critical race. The final stable state that the circuit reaches does not depend on the order in which the state variables change. 5. 4. 09) (Nov. 2007. 2005) Race exists in synchronous sequential circuits when two or more binary state Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays. 7. May. the critical races must be avoided. What is a hazard? (May. What is meant by a non-critical race? What is its cause? (May. the race is called critical race. the race is called a non-critical race. 2006) A race condition is said to exist in an asynchronous sequential circuit when two or more binary state variables changes value in response to a change in an input variable. Define critical & non-critical race. The order by which the state variables change may not be known in advance if the final stable state that the circuit reaches does not depend on the order in which the state variable change. A race becomes critical if the correct next value in not reached during a state transition. What is a hazard in combinational circuits? 2008) (May.
Does Hazard occur in sequential circuit? If so what is the problem caused? Yes. 11. 2005) In a combinational circuit. The main cause of hazards is the different propagation delays at different paths. The hazards cause the circuit to malfunction. 13. the hazard is known as static-1 hazard. What are the types of hazards? The 3 types of hazards are 1. they may result in a transition to a wrong stable state. if output goes momentarily 0 when it should remain a 1. If the output goes momentarily 1 when it should remain a 0. 2005) Hazards can be eliminated by enclosing two minterms or maxterms. Hazards occur in the combinational circuits. (May.The unwanted switching transients that may appear at the output of a circuit are called hazards. (May. where they may cause a temporary false output value. Define static 0-hazard. Describe how to detect and eliminate hazards from an asynchronous network. Static – 0 hazards 2. 12. . When the output changes three or more times when it should change from 1 to 0 or from 0 to 1 is known as dynamic hazard. Dynamic hazards. Hazards occur in sequential circuit that is Asynchronous sequential circuit. It may result in a transition to a wrong state. the hazard is known as static-0 hazard. Static – 1 hazard 3. static 1-hazard and dynamic hazard. When such combinational circuits are used in the asynchronous sequential circuits. 10.
What are the two types of asynchronous circuits? How do they differ? (May. What are the assumptions that must be made for fundamental mode circuit? (May 2008) 1. An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path causes essential hazard. 3. 17. Only one input variable can change at a given time. Fundamental mode circuit. The input variables change only when the circuit is stable. Here the inputs are levels and not pulses. According to the characteristics of the input. Fundamental mode circuit: The input is allowed to charge after the steady state condition. Pulse mode circuit. Generally Fundamental mode circuit is preferred over pulse mode circuits because it is very difficult to fix the pulse width.14. Pulse mode circuit: Here the inputs are pulses. . 2006) Two types of asynchronous circuits are – 1. 2. The pulses width must not be so long that it is still present after the new state is reached. 2. How can the hazards in combinational circuit be removed? Hazards in the combinational circuits can be removed by covering any two min terms that may produce a hazard with a product term common to both. The removal of hazards requires the addition of redundant gates to the circuit 15. Inputs are levels and not pulses. 16. How does an essential hazard occur? An essential hazard occurs due to unequal delays along two or more paths that originate from the same input.
18. What are the steps for the design of asynchronous sequential circuit? (Nov. Such a table is called a flow table. Define merging? The primitive flow table has only one stable state in each row. i. What is meant by flow table? During the design of asynchronous sequential circuits. Find the maximal compatibles using a Merger diagram Find a minimal collection of compatibles that covers all the states and is closed. The width of the pulses is long enough for the circuit to respond to the input. 20. May. Determine all compatible pairs by using the implication table. 2007. Give the procedural steps for determining the compatibles used for the purpose of merging a flow table. 2007) 1. 19. The purpose that must be applied in order to find a suitable group of compatibles for the purpose of merging a flow table can be divided into 3 procedural steps. ii. iii. The pulse width must not be so long that it is still present after the new state is reached. Remember that a total state consists of the internal state combined with the input. 09) . The table can be reduced to a smaller numbers of rows if two or more stable states are placed in the same row of the flow table. 23. The grouping of stable states from separate rows into one common row is called merging. What are the assumptions made for pulse mode circuit? (Nov 2006. Nov. The input variables are pulses instead of levels. it is more convenient to name the states by letter symbols without making specific reference to their binary values. 21. 3. Define primitive flow table? A primitive flow table is a flow table with only one stable total state in each row. 2. 22.
1. What is the advantage of debounce circuit? (Nov. 2008) A debounce circuit is a circuit which removes the series of pulses that result from a contact bounce and produces a single smooth transition of the binary signal from 0 to 1 or from 1 to 0. . 4. Primitive flow table is reduced by eliminating redundant states using the state reduction. 24. 3. 2. Construction of a primitive flow table from the problem statement. The primitive flow table is realized using appropriate logic elements. State assignment is made.
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