I YEAR Code
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech. Degree COURSE STRUCTURE in EMBEDDED SYSTEMS - I Semester Group Subject L P Credits Microcontrollers for Embedded System 3 0 3 Design Embedded Real Time Operating Systems 3 0 3 VLSI Technology & Design 3 0 3 Advanced Computer Networks 3 0 3 Elective -I Advanced Computer Architecture 3 0 3 Wireless LANs & PANs Advanced Digital Signal processing Elective -II Digital System Design 3 0 3 Neural Networks & Applications Advanced Operating Systems Lab Embedded Systems Lab - I 0 3 2 Seminar 2 Total Credits (6 Theory + 1 Lab.) 22
SDMA. Unit – II: Microcontrollers and Processor Architecture & Interfacing 8051 Architecture. Embedded Hardware Units and Devices in system. Digital blocks.I Year – I Sem. Modes of operation and overview of Instructions Unit – IV: Interrupts & Device Drivers Exceptions and Interrupt handling Schemes – Context & Periods for Context Switching. Formalization of System Design. Input/Output Ports and Circuits. Sloss. Peatman. Switched Capacitor blocks. 2008. PIC Microcontroller and Embedded Systems – Muhammad Ali Mazidi. Serial port Device Driver.
. PH Inc. External Bus Interface TEXT BOOKS: 1. ARM Systems Developers Guides.
REFERENCES: 1.Mckinaly. Elsevier. M. Interfacing Processor (8051. PIC Controllers. 2. PIC). Processor Embedded into a system. Device drivers for Internal Programmable timing devices Unit – V: Network Protocols Serial communication protocols. 2005. Designing with PIC Microcontrollers. Danny Causy – PE. Unit – III: Embedded RISC Processors & Embedded System-on Chip Processor PSOC (Programmable System-on-Chip) architectures. Elsevier. 3. Embedded Systems . 3. Deadline & interrupt latency. Valvano – Brookes / Cole. External Memory. Embedded RISC Processor architecture – ARM Processor architecture. Register Set.Design & Optimizing System Software . I/O blocks. Ethernet Protocol. 2. 1998. 2004. I/O Devices.Tech (Embedded Systems) MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN
Unit – I: Introduction to Embedded Systems Overview of Embedded Systems.Andrew N. Dominic Symes. Continuous Timer blocks.TMH. Device driver using Interrupt Service Routine. Channel & IDMA. 2nd ed.Architecture Programming and Design – Raj Kamal. Real Time Interfacing – Jonathan W.John B. Classification of Embedded Systems. Memory Controller and Memory arbitration Schemes. Embedded Software. Embedded Microcomputer Systems. Memory Interfacing. Complex System Design. Counters and Timers. 1999. Thomas Learning. Programming of PSOC. Rolin D.. Designers Guide to the Cypress PSOC – Robert Ashpy. Chris Wright. Design Process in Embedded System.
C. exec). Use of µCOS-II Unit V: VX Works & Case Studies Memory managements task state transition diagram. Richard Stevens VX Works Programmers Guide
. Shin. TEXT BOOKS: 1. Liu. read. Overview of Commands. RT & Embedded Systems OS. Effective release time and Dead lines.M. waitpid. counting watch dugs. shared memory) Unit II: Real Time Systems: Typical real time applications. Inter-process communication Unit IV: Real Time Operating Systems & Programming Tools Operating Systems Services.Multiple Process in an Application. Case Study of an Embedded System for a smart card. Advanced UNIX Programming. create. lseek. wait. Periodic task model precedence constraints and data dependency. A reference model of Real Time Systems: Processors and Resources. functional parameters. close.TMH.Case Study of Automatic Chocolate Vending m/c using µCOS RTOS. File I/O. Signals. KANG G. Offline Vs Online Scheduling.Jane W.( pipes. I/O system Case Studies of programming with RTOS. S. semaphores. Programming and Design by Rajkamal. Resource Parameters of jobs and parameters of resources. Real Time Systems. 2. 2. 1996.( open. exit.Binary mutex. fifos. Process Control ( fork. Unit III: Scheduling & Inter-process Communication Commonly used Approaches to Real Time Scheduling Clock Driven. Temporal Parameters of real Time Work load. Scheduling context switchessemaphore. Embedded Systems.Need of a well Tested & Debugged RTOs. Tasks and Threads. M. pre-emptive priority. TMH
REFERENCES: 1. Real Time Systems. Problem of Sharing data by multiple tasks & routines. Weighted Round Robin. I/O Subsystems. case study of sending application Layer byte Streams on a TCP/IP network.Architecture. Dynamic Vs State Systems. message queues. 2008. Priority Driven. 3.. vfork. Inter-process Communication and Synchronization of Processes. Interprocess communication. write).Tech (Embedded Systems) EMBEDDED REAL TIME OPERATING SYSTEMS
Unit – I: Introduction Introduction to UNIX.Krishna. Hard Vs Soft real-time systems.I Year – I Sem.PHI. Interrupt Routine in RTOS Environment Micro C/OS-II. 2nd ed.
A. Scalable Design rules. Resistive and Inductive interconnect delays. Gds and ωo. PHI. M. Simulation.. Power optimization. Alternative Gate circuits. REFERENCES: 1. Design validation and testing. Switch Logic..Pucknell. Highlevel synthesis. Power optimization.I Year – I Sem. 2005. K. Essentials of VLSI Circuits and Systems. Interconnect design. K. Design. Trends And Projections. 2nd ed.Eshraghian.
.Wayne Wolf. Basic Electrical Properties of MOS. Clocking disciplines. UNIT – II: LAYOUT DESIGN AND TOOLS: Transistor structures. D. CMOS & Bi CMOS Inverters. 1997. LOGIC GATES & LAYOUTS: Static Complementary Gates. Low power gates. Threshold Voltage Vt. Gate and Network testing. 2. Adisson Wesley. Eshraghian Eshraghian. Architecture testing. Principals of CMOS VLSI Design – N. TEXT BOOKS: 1. Gm. Pearson Education. UNIT – III: COMBINATIONAL LOGIC NETWORKS: Layouts. Network delay. Zpu/Zpd. Pass Transistor. CMOS. Switch logic networks. Latch-up in CMOS circuits.E Weste. Architecture for low power. MOS Transistor circuit model. SOCs and Embedded CPUs.H. UNIT – V: FLOOR PLANNING & ARCHITECTURE DESIGN: Floor planning methods. Wires and Vias. CMOS & BiCMOS Circuits: I ds-Vds relationships. UNIT –IV: SEQUENTIAL SYSTEMS: Memory cells and Arrays. off-chip connections. MOS. Modern VLSI Design .Tech (Embedded Systems) VLSI TECHNOLOGY & DESIGN
UNIT – I: Review of Microelectronics and Introduction to MOS Technologies: MOS. 3rd ed. BiCMOS Technology. Layout Design tools.
High Performance TCP / IP Networking – Mahaboob Hassan. Wireless Communications . Introduction to Broadband Communication Systems. Open loop and Closed Loop Congestion Control in TCP and Frame Relay. Dynamic Resource Allocation. QoS and QoS Classes. Wireless LAN Requirements.P.I Year – I Sem.Manoj. G.Properties.Andrea Goldsmith. Best Effort Service Features. ATM Layer: ATM Cell Header Structure at UNI. S. Ad Hoc Wireless Networks: Architectures and Protocols .TMH REFERENCES: 1. Freeman. ATM Service Categories. Wireless LAN Topologies. Latest Developments. Cambridge University Press.S. 2nd updating. PHI 2. ATM Adaptation Layer 2 (AAL2). PHI. Physical Layer Standards for ATM. Telecommunication System Engineering – Roger L. 2004. 4. The Second. IEEE 802. 4/ed. Siva Ram Murthy and B. Scheduling. Congestion Control.Tech (Embedded Systems) ADVANCED COMPUTER NETWORKS
Unit -I: Congestion and Quality of Service (QoS) Data traffic. Interference Reduction Techniques. Need For QoS. John Wiley & Sons.Generation Cellular Systems. A. ATM Adaptation Layer 1 (AAL1). Queue Management: Passive. SONET/SDH: SONET/SDH Architecture. Mathew N. 2. Choke) Queue Management Schemes. Unit-III: Cellular Systems and Infrastructure. Akujuobi. the Medium Access Control (MAC) Layer. 2005. SONET Layers. Channel Reuse. Transmission Convergence (TC) Sub-layer. TEXT BOOKS: 1. Looping Algorithm.16 Standard. Resource Allocation. A. Papadimitriou. and Fair (BRED. Virtual Private Network (VPN): Types of VPN. JohnWiley & Sons 3. The FirstGeneration Cellular Systems.Based Wireless Networks: Cellular Systems Fundamentals. Unit-IV: ATM Protocol Reference Model: Introduction. Nicopolitidis. VPN Security Issues. Quality of Service. Wireless Wide Area Networks and MANS: The Cellular Concept. M. Wireless Networks. Wiley-Interscience. Integrated and Differential Services. Home RF. ATM Adaptation Layer: Service Classes and ATM Adaptation Layer. the Physical Layer. Benes Networks. Flow Characterization. Fundamental Rate Limits. Wireless ATM. ATM Adaptation Layer 5 (AAL5).Forouzan. Active (RED).Sadiku. M. ATM Traffic and Service Parameterization: ATM Traffic Parameters. Cajetan. SONET Frames. Rearrangeable Networks. 3. Physical Medium Dependent (PMD) Sub-layer. VPN Standards. STS Multiplexing.B.. Unit-II: Wireless Local Area Networks: Introduction. Three Stage Class Networks. PHI. 2004. Current VPN Advantages and Disadvantages. The Third. Techniques to Improve QoS. Wireless in Local Loop. Crossbar Switch. Congestion. Resource Reservation and Admission Control Scheduling. Pomportsis. ATM Service Parameters.M. Cellular Architecture. Factors Affecting QoS Parameters. Flow Classes..O. Traffic Shaping. Wireless Personal Area Networks (WPANs): Introduction to PAN Technology and Applications. Jain Raj. ATM Cell Header Structure at NNI. BitAllocation Algorithm. Commercial Alternatives.C. I. Unit-V: Interconnection Networks: Introduction. SONET Networks. ATM Adaptation Layer 3/4 (AAL3/4). Banyan Networks.
. VPN General Architecture. 2003. Obaidat.Generation Cellular Systems. ATM Layer Functions. Data Communication and Networking . S. 2004.Bluetooth. SIR and User Capacity. Folding Algorithm.
control hazard. main memory. 2. 2. problems in parallel processing. IO Processor. IO channel. memory organization and mapping. “Computer Architecture and parallel Processing” Kai Hwang and A. Carl Hamachar. Zvonko Vranesic and Safwat Zaky. UNIT IV ILP software approach-complier techniques-static branch protection-VLIW approach-H. Patteson Morgan Kufmann (An Imprint of Elsevier) Reference Books: 1.I Year – I Sem. Hannessy & David A. register organization and stack organization. PHI of India.Tech (Embedded Systems) ADVANCED COMPUTER ARCHITECTURE (ELECTIVE – I)
UNIT I Concept of instruction format and instruction set of a computer.W support for more ILP at compile time-H. Programmed IO. Computer Architecture & Organization. laser printer. Horizontal and vertical instruction format. parallel processing. instruction pipeline.
. Computer organization. Williams Stallings. UNIT II Memory devices. instruction cycle. partitioning. processor organization. Dezso Sima. UNIT V Storage System-Types-Buses-RAID-errors and failures-bench marking a storage device designing a I/O system. basic details of Pentium processor and power PC processor. Terence Fountain.W verses S. Inter connection networks and clusters-interconnection network media – practical issues in interconnecting networks-examples-clusters-designing a cluster Text Books:
1. Pearson. cache memory. segmentation. associative memory organization. data hazard.
3. John P. IO addressing. DOT matrix printer. microprogramming. introduction to magnetic tape and CDROM. ink jet printer. concept of virtual memory. Peter Kacsuk. microinstruction sequencing and control. Hayes. demand paging.W solutions Multiprocessors and thread level parallelism-symmetric shared memory architectures-distributed shared memory-Synchronization-multi threading. UNIT III IO Devices. types of operands and operations. TMH III Edition. 4. Advanced concepts. “Computer organization and architecture”. addressing modes. McGraw Hill International Edition. Advanced Computer Architecture. 1998. interrupt driver IO. DMA IO modules. Briggs International edition McGraw-Hill. magnetic disk organization. RISC and CISC instruction set. M. Semiconductor and ferrite core memory. Computer Architecture A quantitative approach 3rd edition John L.
Tech (Embedded Systems) WIRELESS LANS AND PANS
(ELECTIVE – I) UNIT 1: Overview of Wireless Communication History of wireless communication. Wireless Networks. High rate WPANs. Cengage Learning. Wireless Wide Area Networks: Cellular Telephone Applications. Jeorge Olenewa. Prashant Krishnamurthy. Evolution of The WLAN Industry. 2007. High rate WPAN Standards.Wireless Networks Application. Ultra Wideband. Multicasting. Surrent Wireless Systems. RFWPANs. Network Capacity Limits.Andrea Goldsmith. Wireless Home Networking.Marks Ciampor. Cellular and Adhoc wireless networks. Digital Cellular Technology.16 (WiMAX). quality of service browsining. Unit 4: Low Rate Wireless Personal Area Networks Infrared WPANs.I Year – I Sem. Transport layer Protocols. Wireless Metropolitan Area Networks: What is WMAN?. Digital Cellular Challenges and Outlook. Protocol Layers. 3. TEXT BOOKS: 1. Adhoc wireless Internet. WLAN Application. Technical Issues. WLAN Components.Based Fixed Broadband Wireless. WMAN Security. WLAN Security. Client Software. Unit 2: Introduction to Wireless LANS Historical Overview of LAN Industry. Design Principles and Challenges. applications. WLAN Standards and operation. 2. Cambridge University Press. Unit 5: Ad-Hoc.
.15. Cross Layer Design. Energy Constrained Networks. The Wireless Spectrum. M. 2002.11b and other WLAN Standards. WLAN Modes. IEEE 802. MAC protocols. Wireless Vision. Routing. PHI. Satellite Broadband Wireless. WPAN Challenges. Wireless Communication.11a and IEEE 802. Low rate WPAN Security.Kaveh Pahlaram.3. Wireless Communication. Land. deployment considerations. Unit 3: High-speed Wireless LANs and WLAN Security IEEE 802. 802.
Decimation by a factor D. Algorithms & Applications . 4th ed. Interpolation by a factor I. 3.Manolokis.Salivahanan.Proakis & D. Non-parametric Methods: Bartlett. Jervis. FIR Filters.Gnanapriya.Tech (Embedded Systems) ADVANCED DIGITAL SIGNAL PROCESSING
(ELECTIVE – I) UNIT I Review of DFT.TMH
. Multirate Systems and Filter Banks – P.Ifeacher. M .. IIR Filters. Barrie. Properties of Linear Prediction Filters UNIT V Finite Word Length Effects: Analysis of finite word length effects in Fixed-point DSP systems – Fixed. W.Vallavaraj.Kay. 2 ed. MA & ARMA models for power spectrum estimation.J. TEXTBOOKS: 1. Multistage Implementation of Sampling Rate Conversion. Welch & Blackman & Tukey methods. A. Modern spectral Estimation : Theory & Application – S. Sampling rate conversion by a rational factor I/D. Applications of Multirate Signal Processing UNIT II Non-Parametric methods of Power Spectral Estimation: Estimation of spectra from finite duration observation of signals. FFT. Floating Point Arithmetic – ADC quantization noise & signal quality – Finite word length effect in IIR digital Filters – Finite word-length effects in FFT algorithms. Backward Linear Prediction. 2. Comparison of all Non-Parametric methods UNIT III Parametric Methods of Power Spectrum Estimation: Autocorrelation & Its Properties.Vaidyanathan – Pearson Education Digital Signal Processing – S.. Relation between auto correlation & model parameters.Yule-Waker & Burg Methods. AR Models . UNIT –IV Linear Prediction : Forward and Backward Linear Prediction – Forward Linear Prediction. Schur Algorithm. Solution of the Normal Equations: Levinson Durbin Algorithm. PHI. Filter design & Implementation for sampling rate conversion. 2.
REFERENCES: 1.Alan V Oppenheim & Ronald W Schaffer.I Year – I Sem. Optimum reflection coefficients for the Lattice Forward and Backward Predictors. M. PHI. Discrete Time signal processing . 1988.G. Digital Signal Processing: Principles. C.G. PHI. 3. Multirate Signal Processing: Introduction. 2000. DSP – A Pratical Approach – Emmanuel C. Pearson Education.P.
Cycles and Hazards.D. 3. Unit-II: Fault Modeling & Test Pattern Generation Logic Fault model – Fault detection & Redundancy. Switching and Finite Automata Theory – Z. Signature analysis and test bridging faults. Fundamentals of Logic Design – Charles H.Problem of Initial state assignment for One –Hot encoding . N. Transition Check Approach . Roth. Boolean Difference method – Kohavi algorithm – Test algorithms – D algorithm...Binary Multiplier – Signed Binary number multiplier (2’s Complement multiplier) – Binary Divider – Control logic for Sequence detector – Realization with Multiplexer – PLA – PAL. PHI REFERENCES: 1. Random testing. Friedman. TEXT BOOKS: 1.John Wiley & Sons Inc. M. Lee . 3. Melvin A.State identification and fault detection experiment. Unit-III: Fault Diagnosis in Sequential Circuits Circuit Test Approach. Fault model in PLA. 5th ed. Test generation and Testable PLA Design. Unit-V: Minimization and Transformation of Sequential Machines The Finite state Model – Capabilities and limitations of FSM – State equivalence and machine minimization – Simplification of incompletely specified machines. PODEM. Digital Systems Testing and Testable Design – Miron Abramovici. Fundamental mode model – Flow table – State reduction – Minimal closed covers – Races. PHI
. Kohavi . 2001. Logic Design Theory – N. Biswas. Breuer and Arthur D.Ciletti. 4th Edition. Design of fault detection experiment. Digital Circuits and Logic Design – Samuel C.I Year – I Sem. 2. Machine identification. State transition table.State assignment for FPGA’s . Cengage Learning. Transition count testing.Tech (Embedded Systems) DIGITAL SYSTEM DESIGN
(ELECTIVE – II) Unit-I: Designing with Programmable Logic Devices Designing with Read only memories – Programmable Logic Arrays – Programmable Array logic – Sequential Programmable Logic Devices – Design with FPGA’s– Using a One-hot state assignment. M. 2nd ed.Fault equivalence and fault location –Fault dominance – Single stuck at fault model – Multiple stuck at fault models –Bridging fault model Fault diagnosis of combinational circuits by conventional methods – Path sensitization techniques. Unit-IV: PLA Minimization and Testing PLA Minimization – PLA folding.State Machine charts – Derivation of SM Charts – Realization of SM charts – Design Examples – Serial adder with Accumulator . Digital Design – Morris Mano. PHI. TMH 2.
UNIT – II Single Layer Feed Forward Networks Classification Model. Generalized Delta Learning Rule.. Necessary number of Hidden Neurons. Elements of Artificial Neural Networks . Out Star Learning Rule.Tech (Embedded Systems) NEURAL NETWORKS AND APPLICATIONS
(ELECTIVE – II) UNIT – I Fundamental Concepts. feature mapping: Self organizing feature maps.
REFERENCES: 1. Steepness of activation function. Chelkuri K. 2nd ed. Supervised and Unsupervised Learning Neural Network Learning rules: Hebbian Learning Rule. Feed Forward Network and Feed Backward Network.I Year – I Sem. Features and Decision Regions. Minimization of the Traveling salesman tour length. Discriminant Functions.Zurada. Models & Learning Rules of Artificial Neural Systems Biological Neuron Models and their Artificial Models Biological Neuron. Feed Forward Recall and Error Back Propagation Training. Multicategory Single Layer Perceptron Networks. Summary of Learning Rules. Yagananarayana.Dr. New Delhi. Mathematical Foundation of Gradient-Type Hopfield Networks. Boltzman machines. Mathematical Foundation of Discrete-Time Hop field Networks. Learning Factors. separability limitations. Mohan.Basic concepts of Dynamical systems. Introduction Neural Networks Using MATLAB 6. Application of Back propagation Networks in pattern recognition & Image processing UNIT – IV Associative Memories Basic concepts Linear associator . Sumati. Initial weights Cumulative Weight Adjustment versus Incremental Updating. McCulloch-Pitts Neuron Model.0 . Delta Learning Rule for Multiperception layer. Neural Processing. M. Nonparametric Training Concept. S. N. Fundamental of Neural Networks –Laurene Fausett
. Solving Simultaneous Linear Equations. Example Solution of Optimization Problems. Shivanandam. Delta Learning Rule Widrow-Hoff Rule. Training and Classification using the Discrete Perceptron: Algorithm and Examples. Cluster discovery networks (ART1). Single Layer Continuous Perceptron Networks for Linearly Separable Classifications. Examples of Error BackPropagation. Sanjay Ranka. Transient response of Continuous Time Networks. Counter propagation networks. Perceptron Convergence Theorem. Winner –Take-All Learning Rule.S. B. Linear Machine and Minimum Distance Classification. Neuron Modeling for Artificial Neuron Models. Jaico Publishers Artificial Neural Networks . Introduction to Artificial Neural Systems .J. New Delhi. TMH. Training Errors.Bidirectional Associative Memory. UNIT – III Multilayer Feed Forward Networks Linearly Nonseparable Pattern Classification. Associative Memory of Spatio-temporal Patterns UNIT – V Matching And Self-Organizing Networks Hamming net and MAXNET Unsupervised learning of clusters. momentum method. Summing networks with digital outputs. Multidirectional Associative Memory. Penram International 2. Models of Artificial Neural Networks.N. Deepa. initialization of weights. Correlation Learning Rule. Clustering and similarity measures Winner take all learning . S. Artificial Neural Network –Simon Haykin.Kishan Mehrotra. Network architecture Versus Data Representation. Perception Learning Rule.1/e. TEXT BOOKS: 1. 2. 4. Pearson Education 3. learning constant. PHI. 1999.recall mode.M.
pipes..1998. Operating System Principles. 2.1986. 4th ed.W. 4.Tech (Embedded Systems) ADVANCED OPERATING SYSTEMS
(ELECTIVE – II) Unit – I: Introduction to Operating Systems: Overview of computer system hardware. Evaluation of operating System Unit – II: Introduction to UNIX and LINUX: Basic commands & command arguments. Interrupts. Distributed Operating System . Greg Gagne. Operating Systems : Internal and Design Principles . Memory hierarchy.Stallings. PHI.. E-tech algorithms. file and record locking. Streams & Messages. Unit – IV: Introduction to Distributed systems: Goals of distributed system. Inter process Communication: Introduction. 6th ed. Tanenbaum. 3.Andrew.. Process creation & termination.Bach.
REFERENCES: 1. Name Spaces. PE. Atomic transactions Deadlocks: Dead lock in distributed systems. Communication in Distributed systems: Layered protocols. 2. Design issues. I/O function. Shared Memory. Client . FIFOs. PE.. Peter B. Shells and operations Unit – III: System Calls: System calls and related file structures. Modern Operating Systems. Instruction execution. PHI. Hardware and software concepts. UNIX Network Programming . 7th ed. output. The Complete reference LINUX – Richard Peterson. 5. 6. The design of the UNIX Operating Systems – Maurice J. Remote procedure call and Group communication. S. Standard input. Distributed dead lock prevention and distributed dead lock detection. Sockets & TLI. TEXT BOOKS: 1. ATM networks. Bully algorithm.. John Wiley UNIX User Guide – Ritchie & Yates.
. Input / output redirection. Ring algorithm.Abraham Silberchatz. 3. Andrew S Tanenbaum 3rd ed. Mutual exclusion. 1994. Message queues. Semaphores. Galvin. I/O Communication techniques. PHI. Systems V IPC. M. Operating system objectives and functions. The UNIX Programming Environment – Kernighan & Pike. Client – Server example.I Year – I Sem. McGraw – Hill. Unit – V: Synchronization in Distributed systems : Clock synchronization. Input / Output.Server model. PE.Richard Stevens . filters and editors.
ADC. c. Cross Compiler/ Assembler. Case Studies. LCD interface to 8051. DAC interface to 8051.Any two a. Look up tables for 8051.Real time times and Applications. 3. Keyboard interface to 8051. Serial Communication Drivers for ARM Processors. b. 4.
. 3. 6. Serial Data Transmission using 8051 microcontroller in different modes.Tech (Embedded Systems)
EMBEDDED SYSTEMS LAB-1 CYCLE 1: 8051 Microcontrollers 1.I Year – I Sem. 5. Software Development for DSP Applications. 5. 2.
CYCLE 2: 1. 4. Vx Works. M. Design of RTOS Kernel. 2. Development of Devices Drivers for RT Linux. Timing subroutines for 8051. Study of Real Time Operating Systems.