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Compal Confidential 2

ICW50 Schematics Document


AMD Turion/Sempron + Nvidia MCP67-MV
2007 / 04 / 20 Rev:1.0 FOR Pre-MP
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title


Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 1 of 42
A B C D E
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Compal confidential
Project Code: ICW50 DDRII 533/667/800 DDRII-SO-DIMM X2
Thermal Sensor AMD Turion/Sempron CPU
page 08,09
File Name : LA-3581P ADM1032ARM Socket S1 638P
page 4,5,6,7 Dual Channel
page 6
D HT LINK D

200-800MHz

DVI-D Conn. LCD Conn. CRT & TV-out


page 20 page 20 page 19
Nvidia USB conn x4 Bluetooth CMOS
LVDS Conn page Camera
MCP67-MV page 25,26 29 page 20

DVI LVDS 836 BGA USB 2.0 BUS

HD Audio 3.3V 24.576MHz/48Mhz


PCI-Express
IDE BUS 3.3V ATA-100

MXM II VGA/B SATA BUS


page 18 CDROM MDC 1.5 HDA Codec
Conn. Conn ALC268
C
page 21 page 29 page 31 C
PCI-Express port 1

PCI BUS S-ATA HDD


IDSEL:AD20
3.3V 33 MHz Conn. page 21
New Card MINI Card x2 PHY(GbE) (PIRQE#, Audio AMP
page 10,11,12,13,14,15,16,17
Socket WLAN, TV-Tuner RTL8211B GNT#0,
REQ#0) page 32
page 22

Card Reader
RICOH R5C833 Phone Jack x3
RJ45 page 23 LPC BUS page 32

page 22

1394 6 in 1
B Conn. socket B

page 23 page 24 ENE KB926


page 27,28

Power On/Off CKT / LID switch / Power OK CKT


page 30
Touch Pad Int.KBD
page 29 page 29
DC/DC Interface CKT. CIR/LED RTC CKT.
page 33 page 29 page 16
EC I/O Buffer BIOS
page 29 page 29
Power Circuit DC/DC
page 35~41

CIR
page 30
A A

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH ON ON ON LOW


Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH ON ON OFF OFF
D D
B+ AC or battery power rail for power circuit. N/A N/A N/A
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.2VALW 1.2V always on power rail ON ON ON*
+1.2VS 1.2V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.2V_HT 1.2V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+2.5VS 2.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW/+3V/+3VAUX 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+VSB VSB always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
C
+RTCVCC RTC power ON ON ON 6 200K +/- 5% 1.935 V 2.200 V 2.341 V C

7 NC 2.500 V 3.300 V 3.300 V

BOARD ID Table BTO Option Table


Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 UMA (0V) DIP CAP & RTC 45@
1394 AD20 0 PIRQE
1 DISCRETE (3.3V) UMA UMA@
2 VGA VGA@
3 UMA & TV-OUT UMA&TV@
4 2 SATA HDD SATA2@
5 CAMERA CMOS@
6 BLUETOOTH BT@
7 MINI CARD 1(TV) MINI1@
B MINI CARD 2(WLAN) MINI2@ B

NEW CARD EXPRESS@


EC SM Bus1 address EC SM Bus2 address SKU ID Table TV-OUT TV@
DVI DVI@
Device Address Device Address SKU ID SKU
1394 1394@
Smart Battery 0001 011X b ADM1032 1001 100X b 0 B - PHASE
CARD READER 5IN1@
1 C - PHASE
HT Debug Port HT@
2
3
4
5
MCP67 SM Bus address 6
7
Device Address
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 001Xb
A A

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
TABLE OF CONTENTS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 3 of 42
5 4 3 2 1
5 4 3 2 1

PROCESSOR HYPERTRANSPORT INTERFACE


VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
D D
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.2V_HT
FAN Conn
JP22A
D4 VLDT_A3 VLDT_B3 AE5 1 2 C533
D3 AE4 4.7U_0805_10V4Z
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 AE2 +5VS
VLDT_A0 VLDT_B0

1
H_CADIP15 N5 T4 H_CADOP15 D20
(10) H_CADIP15 L0_CADIN_H15 L0_CADOUT_H15 H_CADOP15 (10)
H_CADIN15 P5 T3 H_CADON15 1SS355_SOD323-2
(10) H_CADIN15 L0_CADIN_L15 L0_CADOUT_L15 H_CADON15 (10)
H_CADIP14 M3 V5 H_CADOP14 W=40mils
(10) H_CADIP14 L0_CADIN_H14 L0_CADOUT_H14 H_CADOP14 (10)
H_CADIN14 M4 U5 H_CADON14
(10) H_CADIN14 L0_CADIN_L14 L0_CADOUT_L14 H_CADON14 (10) +VCC_FAN1
H_CADIP13 L5 V4 H_CADOP13
(10) H_CADIP13 H_CADOP13 (10)

2
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
(10) H_CADIN13 M5 L0_CADIN_L13 L0_CADOUT_L13 V3 H_CADON13 (10)
H_CADIP12 K3 Y5 H_CADOP12 FAN1 1 2
(10) H_CADIP12 L0_CADIN_H12 L0_CADOUT_H12 H_CADOP12 (10) +3VS
H_CADIN12 K4 W5 H_CADON12 C510 10U_0805_10V4Z
(10) H_CADIN12 L0_CADIN_L12 L0_CADOUT_L12 H_CADON12 (10)

1
H_CADIP11 H3 AB5 H_CADOP11 D21
(10) H_CADIP11 L0_CADIN_H11 L0_CADOUT_H11 H_CADOP11 (10)
H_CADIN11 H4 AA5 H_CADON11 BAS16_SOT23-3
(10) H_CADIN11 L0_CADIN_L11 L0_CADOUT_L11 H_CADON11 (10)

1
H_CADIP10 G5 AB4 H_CADOP10 1 2
(10) H_CADIP10 L0_CADIN_H10 L0_CADOUT_H10 H_CADOP10 (10)
H_CADIN10 H5 AB3 H_CADON10 R88 C509 1000P_0402_50V7K
(10) H_CADIN10 L0_CADIN_L10 L0_CADOUT_L10 H_CADON10 (10)
H_CADIP9 F3 AD5 H_CADOP9 10K_0402_5% Update Footprint
(10) H_CADIP9 H_CADOP9 (10)

2
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9 JP16
(10) H_CADIN9 F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 H_CADON9 (10)
H_CADIP8 E5 AD4 H_CADOP8
(10) H_CADIP8 H_CADOP8 (10)

2
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8 1
(10) H_CADIN8 F5 L0_CADIN_L8 L0_CADOUT_L8 AD3 H_CADON8 (10) (27,28) FAN_SPEED1 2
C H_CADIP7 N3 T1 H_CADOP7 C
(10) H_CADIP7 L0_CADIN_H7 L0_CADOUT_H7 H_CADOP7 (10) 3
H_CADIN7 N2 R1 H_CADON7
(10) H_CADIN7 L0_CADIN_L7 L0_CADOUT_L7 H_CADON7 (10)
H_CADIP6 L1 U2 H_CADOP6 1 ACES_85205-03001
HTT Interface

(10) H_CADIP6 L0_CADIN_H6 L0_CADOUT_H6 H_CADOP6 (10)


H_CADIN6 M1 U3 H_CADON6
(10) H_CADIN6 L0_CADIN_L6 L0_CADOUT_L6 H_CADON6 (10)
H_CADIP5 L3 V1 H_CADOP5 C52
(10) H_CADIP5 L0_CADIN_H5 L0_CADOUT_H5 H_CADOP5 (10)
H_CADIN5 L2 U1 H_CADON5 1000P_0402_50V7K
(10) H_CADIN5 L0_CADIN_L5 L0_CADOUT_L5 H_CADON5 (10) 2
H_CADIP4 J1 W2 H_CADOP4
(10) H_CADIP4 L0_CADIN_H4 L0_CADOUT_H4 H_CADOP4 (10)
H_CADIN4 K1 W3 H_CADON4
(10) H_CADIN4 L0_CADIN_L4 L0_CADOUT_L4 H_CADON4 (10)
H_CADIP3 G1 AA2 H_CADOP3
(10) H_CADIP3 L0_CADIN_H3 L0_CADOUT_H3 H_CADOP3 (10)
H_CADIN3 H1 AA3 H_CADON3
(10) H_CADIN3 L0_CADIN_L3 L0_CADOUT_L3 H_CADON3 (10)
H_CADIP2 G3 AB1 H_CADOP2
(10) H_CADIP2 L0_CADIN_H2 L0_CADOUT_H2 H_CADOP2 (10)
H_CADIN2 G2 AA1 H_CADON2
(10) H_CADIN2 L0_CADIN_L2 L0_CADOUT_L2 H_CADON2 (10)
H_CADIP1 E1 AC2 H_CADOP1
(10) H_CADIP1 L0_CADIN_H1 L0_CADOUT_H1 H_CADOP1 (10)
H_CADIN1 F1 AC3 H_CADON1 U11
(10) H_CADIN1 L0_CADIN_L1 L0_CADOUT_L1 H_CADON1 (10)
H_CADIP0 E3 AD1 H_CADOP0 1 8
(10) H_CADIP0 L0_CADIN_H0 L0_CADOUT_H0 H_CADOP0 (10) VEN GND
H_CADIN0 E2 AC1 H_CADON0 +5VS 2 7
(10) H_CADIN0 L0_CADIN_L0 L0_CADOUT_L0 H_CADON0 (10) VIN GND
+VCC_FAN1 3 VO GND 6
H_CLKIP1 J5 Y4 H_CLKOP1 EN_DFAN1 4 5
(10) H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 (10) (27,28) EN_DFAN1 VSET GND
H_CLKIN1 K5 Y3 H_CLKON1 1
(10) H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 (10)
H_CLKIP0 J3 Y1 H_CLKOP0 G993P1UF_SOP8
(10) H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 (10)
+1.2V_HT H_CLKIN0 J2 W1 H_CLKON0 C310
(10) H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 (10)
10U_0805_10V4Z
2
R1431 2 51_0402_1% H_CTLIP1 P3 T5
R1421 H_CTLIN1 L0_CTLIN_H1 L0_CTLOUT_H1
2 51_0402_1% P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5

H_CTLIP0 N1 R2 H_CTLOP0
(10) H_CTLIP0
(10) H_CTLIN0
H_CTLIN0 P1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLOUT_H0
L0_CTLOUT_L0 R3 H_CTLON0
H_CTLOP0 (10)
H_CTLON0 (10) FAN1 Conn
FOX_PZ63823-284S-41F
B Athlon 64 S1 B
Processor Socket

+1.2V_HT C541 C536 C539


4.7U_0805_10V4Z 0.22U_0402_10V4Z 180P_0402_50V8J

1 1 1 1 1 1

2 2 2 2 2 2
C542 C540 C538
4.7U_0805_10V4Z 0.22U_0402_10V4Z 180P_0402_50V8J

LAYOUT: Place bypass cap on topside of board


NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
A A

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
AMD CPU HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 4 of 42
5 4 3 2 1
A B C D E

Processor DDR2 Memory Interface


VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED JP22C
(9) DDR_B_D[63..0]
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE DDR_A_D[63..0] (8)
DDR_B_D63 AD11 AA12 DDR_A_D63
DDR_B_D62 MB_DATA63 MA_DATA63 DDR_A_D62
AF11 MB_DATA62 MA_DATA62 AB12
DDR_B_D61 AF14 AA14 DDR_A_D61
DDR_B_D60 MB_DATA61 MA_DATA61 DDR_A_D60
AE14 MB_DATA60 MA_DATA60 AB14
DDR_B_D59 Y11 W11 DDR_A_D59
DDR_B_D58 MB_DATA59 MA_DATA59 DDR_A_D58
AB11 MB_DATA58 MA_DATA58 Y12
DDR_B_D57 AC12 AD13 DDR_A_D57
+1.8V DDR_B_D56 MB_DATA57 MA_DATA57 DDR_A_D56
AF13 MB_DATA56 MA_DATA56 AB13
+0.9VREF_CPU DDR_B_D55 AF15 AD15 DDR_A_D55
4 JP22B +0.9V DDR_B_D54 MB_DATA55 MA_DATA55 DDR_A_D54 4
AF16 MB_DATA54 MA_DATA54 AB15
DDR_B_D53 AC18 AB17 DDR_A_D53
MB_DATA53 MA_DATA53
1

W17 D10 DDR_B_D52 AF19 Y17 DDR_A_D52


R386 M_VREF VTT1 DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51
VTT2 C10 AD14 MB_DATA51 MA_DATA51 Y14
39.2_0402_1%~D PAD TP2 VTT_SENSE Y10 B10 DDR_B_D50 AC14 W14 DDR_A_D50
VTT_SENSE VTT3 DDR_B_D49 MB_DATA50 MA_DATA50 DDR_A_D49
VTT4 AD10 AE18 MB_DATA49 MA_DATA49 W16
W10 DDR_B_D48 AD18 AD17 DDR_A_D48
2

M_ZN VTT5 DDR_B_D47 MB_DATA48 MA_DATA48 DDR_A_D47


AE10 M_ZN VTT6 AC10 AD20 MB_DATA47 MA_DATA47 Y18
M_ZP AF10 AB10 DDR_B_D46 AC20 AD19 DDR_A_D46
M_ZP VTT7 DDR_B_D45 MB_DATA46 MA_DATA46 DDR_A_D45
AA10 AF23 AD21
R388 10:8:10:8:10 VTT8
A10 DDR_B_D44 AF24
MB_DATA45 MA_DATA45
AB21 DDR_A_D44
VTT9 MB_DATA44 MA_DATA44
1

39.2_0402_1%~D DDR_B_D43 AF20 AB18 DDR_A_D43


DDR_CS3_DIMMA# DDR_A_CLK2 DDR_B_D42 MB_DATA43 MA_DATA43 DDR_A_D42
(8) DDR_CS3_DIMMA# V19 MA0_CS_L3 MA0_CLK_H2 Y16 DDR_A_CLK2 (8) AE20 MB_DATA42 MA_DATA42 AA18

DDRII Cmd/Ctrl//Clk
DDR_CS2_DIMMA# J22 AA16 DDR_A_CLK#2 DDR_B_D41 AD22 AA20 DDR_A_D41
(8) DDR_CS2_DIMMA# MA0_CS_L2 MA0_CLK_L2 DDR_A_CLK#2 (8) MB_DATA41 MA_DATA41
DDR_CS1_DIMMA# V22 E16 DDR_A_CLK1 DDR_B_D40 AC22 Y20 DDR_A_D40
(8) DDR_CS1_DIMMA# MA0_CS_L1 MA0_CLK_H1 DDR_A_CLK1 (8) MB_DATA40 MA_DATA40
DDR_CS0_DIMMA# T19 F16 DDR_A_CLK#1 DDR_B_D39 AE25 AA22 DDR_A_D39
(8) DDR_CS0_DIMMA# DDR_A_CLK#1 (8)
2

MA0_CS_L0 MA0_CLK_L1 DDR_B_D38 MB_DATA39 MA_DATA39 DDR_A_D38


AD26 MB_DATA38 MA_DATA38 Y22
DDR_CS3_DIMMB# Y26 AF18 DDR_B_CLK2 DDR_B_D37 AA25 W21 DDR_A_D37
(9) DDR_CS3_DIMMB# MB0_CS_L3 MB0_CLK_H2 DDR_B_CLK2 (9) MB_DATA37 MA_DATA37
DDR_CS2_DIMMB# J24 AF17 DDR_B_CLK#2 DDR_B_D36 AA26 W22 DDR_A_D36
(9) DDR_CS2_DIMMB# MB0_CS_L2 MB0_CLK_L2 DDR_B_CLK#2 (9) MB_DATA36 MA_DATA36
DDR_CS1_DIMMB# W24 A17 DDR_B_CLK1 DDR_B_D35 AE24 AA21 DDR_A_D35
(9) DDR_CS1_DIMMB# MB0_CS_L1 MB0_CLK_H1 DDR_B_CLK1 (9) MB_DATA35 MA_DATA35
PLACE THEM CLOSE TO DDR_CS0_DIMMB# U23 A18 DDR_B_CLK#1 DDR_B_D34 AD24 AB22 DDR_A_D34
(9) DDR_CS0_DIMMB# MB0_CS_L0 MB0_CLK_L1 DDR_B_CLK#1 (9) MB_DATA34 MA_DATA34
DDR_B_D33 AA23 AB24 DDR_A_D33
CPU WITHIN 1" DDR_CKE1_DIMMB DDR_B_ODT1 DDR_B_D32 MB_DATA33 MA_DATA33 DDR_A_D32
(9) DDR_CKE1_DIMMB H26 MB_CKE1 MB0_ODT1 W23 DDR_B_ODT1 (9) AA24 MB_DATA32 MA_DATA32 Y24
DDR_CKE0_DIMMB J23 W26 DDR_B_ODT0 DDR_B_D31 G24 H22 DDR_A_D31
(9) DDR_CKE0_DIMMB MB_CKE0 MB0_ODT0 DDR_B_ODT0 (9) MB_DATA31 MA_DATA31
DDR_CKE1_DIMMA J20 V20 DDR_A_ODT1 DDR_B_D30 G23 H20 DDR_A_D30
(8) DDR_CKE1_DIMMA MA_CKE1 MA0_ODT1 DDR_A_ODT1 (8) MB_DATA30 MA_DATA30
DDR_CKE0_DIMMA J21 U19 DDR_A_ODT0 DDR_B_D29 D26 E22 DDR_A_D29
(8) DDR_CKE0_DIMMA MA_CKE0 MA0_ODT0 DDR_A_ODT0 (8) MB_DATA29 MA_DATA29
DDR_B_D28 C26 E21 DDR_A_D28
(8) DDR_A_MA[15..0] DDR_B_MA[15..0] (9) MB_DATA28 MA_DATA28
DDR_A_MA15 K19 J25 DDR_B_MA15 DDR_B_D27 G26 J19 DDR_A_D27
DDR_A_MA14 MA_ADD15 MB_ADD15 DDR_B_MA14 DDR_B_D26 MB_DATA27 MA_DATA27 DDR_A_D26
K20 MA_ADD14 MB_ADD14 J26 G25 MB_DATA26 MA_DATA26 H24
DDR_A_MA13 V24 W25 DDR_B_MA13 DDR_B_D25 E24 F22 DDR_A_D25

To normal SODIMM socket


To reverse SODIMM socket
DDR_A_MA12 MA_ADD13 MB_ADD13 DDR_B_MA12 DDR_B_D24 MB_DATA25 MA_DATA25 DDR_A_D24
K24 MA_ADD12 MB_ADD12 L23 E23 MB_DATA24 MA_DATA24 F20

DDRII Data
DDR_A_MA11 L20 L25 DDR_B_MA11 DDR_B_D23 C24 C23 DDR_A_D23
DDR_A_MA10 MA_ADD11 MB_ADD11 DDR_B_MA10 DDR_B_D22 MB_DATA23 MA_DATA23 DDR_A_D22
R19 MA_ADD10 MB_ADD10 U25 B24 MB_DATA22 MA_DATA22 B22
DDR_A_MA9 L19 L24 DDR_B_MA9 DDR_B_D21 C20 F18 DDR_A_D21
DDR_A_MA8 MA_ADD9 MB_ADD9 DDR_B_MA8 DDR_B_D20 MB_DATA21 MA_DATA21 DDR_A_D20
L22 MA_ADD8 MB_ADD8 M26 B20 MB_DATA20 MA_DATA20 E18
DDR_A_MA7 L21 L26 DDR_B_MA7 DDR_B_D19 C25 E20 DDR_A_D19
DDR_A_MA6 MA_ADD7 MB_ADD7 DDR_B_MA6 DDR_B_D18 MB_DATA19 MA_DATA19 DDR_A_D18
M19 MA_ADD6 MB_ADD6 N23 D24 MB_DATA18 MA_DATA18 D22
DDR_A_MA5 M20 N24 DDR_B_MA5 DDR_B_D17 A21 C19 DDR_A_D17
3 DDR_A_MA4 MA_ADD5 MB_ADD5 DDR_B_MA4 DDR_B_D16 MB_DATA17 MA_DATA17 DDR_A_D16 3
M24 MA_ADD4 MB_ADD4 N25 D20 MB_DATA16 MA_DATA16 G18
DDR_A_MA3 M22 N26 DDR_B_MA3 DDR_B_D15 D18 G17 DDR_A_D15
DDR_A_MA2 MA_ADD3 MB_ADD3 DDR_B_MA2 DDR_B_D14 MB_DATA15 MA_DATA15 DDR_A_D14
N22 MA_ADD2 MB_ADD2 P24 C18 MB_DATA14 MA_DATA14 C17
DDR_A_MA1 N21 P26 DDR_B_MA1 DDR_B_D13 D14 F14 DDR_A_D13
DDR_A_MA0 MA_ADD1 MB_ADD1 DDR_B_MA0 DDR_B_D12 MB_DATA13 MA_DATA13 DDR_A_D12
R21 MA_ADD0 MB_ADD0 T24 C14 MB_DATA12 MA_DATA12 E14
DDR_B_D11 A20 H17 DDR_A_D11
DDR_A_BS#2 MB_DATA11 MA_DATA11
(8) DDR_A_BS#2 K22 MA_BANK2 MB_BANK2 K26 DDR_B_BS#2 DDR_B_BS#2 (9)
DDR_B_D10 A19 MB_DATA10 MA_DATA10 E17 DDR_A_D10
DDR_A_BS#1 R20 T26 DDR_B_BS#1 DDR_B_D9 A16 E15 DDR_A_D9
(8) DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 (9) MB_DATA9 MA_DATA9
DDR_A_BS#0 T22 U26 DDR_B_BS#0 DDR_B_D8 A15 H15 DDR_A_D8
(8) DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 (9) MB_DATA8 MA_DATA8
DDR_B_D7 A13 E13 DDR_A_D7
DDR_A_RAS# MB_DATA7 MA_DATA7
(8) DDR_A_RAS# T20 MA_RAS_L MB_RAS_L U24 DDR_B_RAS# DDR_B_RAS# (9)
DDR_B_D6 D12 MB_DATA6 MA_DATA6 C13 DDR_A_D6
DDR_A_CAS# U20 V26 DDR_B_CAS# DDR_B_D5 E11 H12 DDR_A_D5
(8) DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# (9) MB_DATA5 MA_DATA5
DDR_A_WE# U21 U22 DDR_B_WE# DDR_B_D4 G11 H11 DDR_A_D4
(8) DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# (9) MB_DATA4 MA_DATA4
DDR_B_D3 B14 G14 DDR_A_D3
FOX_PZ63823-284S-41F DDR_B_D2 MB_DATA3 MA_DATA3 DDR_A_D2
A14 MB_DATA2 MA_DATA2 H14
Athlon 64 S1 DDR_B_D1 A11 F12 DDR_A_D1
Processor DDR_B_D0 MB_DATA1 MA_DATA1 DDR_A_D0
C11 MB_DATA0 MA_DATA0 G12
Socket
(9) DDR_B_DM[7..0] DDR_A_DM[7..0] (8)
DDR_B_DM7 AD12 Y13 DDR_A_DM7
DDR_B_DM6 MB_DM7 MA_DM7 DDR_A_DM6
AC16 MB_DM6 MA_DM6 AB16
DDR_B_DM5 AE22 Y19 DDR_A_DM5
DDR_B_DM4 MB_DM5 MA_DM5 DDR_A_DM4
AB26 MB_DM4 MA_DM4 AC24
DDR_A_CLK2 DDR_B_CLK2 DDR_B_DM3 E25 F24 DDR_A_DM3
DDR_B_DM2 MB_DM3 MA_DM3 DDR_A_DM2
1 1 A22 MB_DM2 MA_DM2 E19
DDR_B_DM1 B16 C15 DDR_A_DM1
C336 C349 DDR_B_DM0 MB_DM1 MA_DM1 DDR_A_DM0
A12 MB_DM0 MA_DM0 E12
1.5P_0402_50V8C 1.5P_0402_50V8C
DDR_A_CLK#2 2 DDR_B_CLK#2 2 DDR_B_DQS7 DDR_A_DQS7
(9) DDR_B_DQS7 AF12 MB_DQS_H7 MA_DQS_H7 W12 DDR_A_DQS7 (8)
DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
(9) DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 (8)
DDR_A_CLK1 DDR_B_CLK1 DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
(9) DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 (8)
1 1 DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
(9) DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 (8)
DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
(9) DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 (8)
C344 C348 DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
1.5P_0402_50V8C 1.5P_0402_50V8C (9) DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 (8)
DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
2 2 (9) DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 (8)
DDR_A_CLK#1 DDR_B_CLK#1 DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
(9) DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 (8)
DDR_B_DQS3 F26 G22 DDR_A_DQS3
(9) DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 (8)
DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
(9) DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 (8)
PLACE CLOSE TO PROCESSOR PLACE CLOSE TO PROCESSOR DDR_B_DQS2 A24 C22 DDR_A_DQS2
2 (9) DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 (8) 2
DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
WITHIN 1.2 INCH WITHIN 1.2 INCH (9) DDR_B_DQS#2
DDR_B_DQS1 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS1
DDR_A_DQS#2 (8)
(9) DDR_B_DQS1 D16 MB_DQS_H1 MA_DQS_H1 G16 DDR_A_DQS1 (8)
DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
(9) DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 (8)
DDR_B_DQS0 C12 G13 DDR_A_DQS0
(9) DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 (8)
DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
(9) DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 (8)

FOX_PZ63823-284S-41F
Athlon 64 S1
Processor Socket
+1.8V
1

R228

1K_0402_1% +0.9VREF_CPU
2

CPU_VREF_REF
A1 A26
1 1 1 1 1
1

C358 C363 C345 C357 C350


R222
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V4Z
1K_0402_1% 2 2 2 2 2

Athlon 64 S1g1
2

1000P_0402_50V7K 1000P_0402_50V7K
uPGA638
Top View
VDD_VREF_SUS_CPU
LAYOUT:PLACE CLOSE TO CPU
1
AF1 1

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
AMD CPU DDRII MEMORY I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 5 of 42
A B C D E
5 4 3 2 1

ATHLON Control and Debug +1.8V

LAYOUT: ROUTE VDDA TRACE APPROX.

1
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
R155 R156
+2.5VS 300_0402_5% 300_0402_5%
W=50mils JP22D

2
1 2 L28 +2.5VS_VDDA F8 AF6 H_THERMTRIP_S#
VDDA2 THERMTRIP_L
1 1 1 1 F9 VDDA1 PROCHOT_L AC7 CPU_PROCHOT#_1.8
C266 FCM2012C-800_0805 C276 C271
C277 CPU_HT_RESET# B7
22U_0805_6.3V6M 3300P_0402_50V7K R370 300_0402_5% CPU_ALL_PWROK RESET_L
+1.8V 1 2 A7 PWROK
2 2 2 2 R371 300_0402_5% CPU_LDTSTOP#
1 2 F10 LDTSTOP_L
D 4.7U_0805_10V4Z 0.22U_0603_16V7K VID5 D
VID5 A5 VID5 (41)
R369 1 2 0_0402_5% CPU_SIC_R AF4 C6 VID4
(15) CPU_SIC SIC VID4 VID4 (41)
R368 1 2 0_0402_5% CPU_SID_R AF5 A6 VID3
(15) CPU_SID SID VID3 VID3 (41)
A4 VID2
VID2 VID2 (41)
+1.2V_HT R378 1 2 44.2_0603_1% CPU_HTREF1 P6 C5 VID1
HTREF1 VID1 VID1 (41)
R376 1 2 44.2_0603_1% CPU_HTREF0 R6 B5 VID0
HTREF0 VID0 VID0 (41)
+1.8V +3VS +1.8V
5:10 AC6 CPU_PRESENT#
CPU_VCC_SENSE CPU_PRESENT_L
(41) CPU_VCC_SENSE F6 VDD_FB_H

1
R381 place them to CPU within 1" CPU_VSS_SENSE E6 A3 PSI#
(41) CPU_VSS_SENSE VDD_FB_L PSI_L PSI# (41)
4.7K_0402_5% C543 0.1U_0402_16V4Z

1
@ 1 2 PAD TP3 W9
R379 PAD TP1 VDDIO_FB_H
Y9 VDDIO_FB_L

5
300_0402_5% U26

2
2 C5451 2 CPU_CLKIN_SC_P A9

P
B (10) CPUCLK CLKIN_H
4 1 2 CPU_ALL_PWROK CPU_CLKIN_SC_N A8

2
Y CLKIN_L

1
1 R383 0_0402_5% 3900P_0402_50V7K
(10) HTCPU_PWRGD A

G
@ R382 CPU_DBRDY G10 E10 CPU_DBREQ#
NC7SZ08P5X_NL_SC70-5 169_0402_1% DBRDY DBREQ_L

3
@ CPU_TMS AA9
CPU_TCK TMS
AC9 AE9 CPU_TDO

2
C5441 CPU_TRST# TCK TDO
1 2 (10) CPUCLK# 2 AD9 TRST_L
R380 0_0402_5% CPU_TDI AF9
3900P_0402_50V7K TDI R384
+1.8V CPU_TEST25_H_BYPASSCLK_H E9 C9 CPU_TEST29_H_FBCLKOUT_P 1 2
+1.8V CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST29_H CPU_TEST29_L_FBCLKOUT_N 80.6_0402_1%
E8 TEST25_L TEST29_L C8 ROUTE AS 80 Ohm DIFFERENTIAL PAIR
CPU_TEST19_PLLTEST0 PLACE IT CLOSE TO CPU WITHIN 1"
G9 TEST19 5:5:5
1

CPU_TEST18_PLLTEST1 H10 TEST18

MISC
R184 AA7 TEST13

5
300_0402_5% U9 C2 TEST9
2 D7 AE7
P
B CPU_LDTSTOP# TEST17 TEST24
4 1 2 E7 AD7
2

Y R189 0_0402_5% TEST16 TEST23


(10) HTCPU_STOP# 1 A F7 TEST15 TEST22 AE8
G
@ C7 TEST14 TEST21 AB8 CPU_TEST21_SCANEN
NC7SZ08P5X_NL_SC70-5 AC8 AF7
3

@ TEST12 TEST20
C3 TEST7 TEST28_H J7
1 2 AA6 TEST6 TEST28_L H8
C R183 0_0402_5% CPU_THERMDC C
W7 THERMDC TEST27 AF8
CPU_THERMDA W8 AE6 CPU_TEST26_BURNIN#
+1.8V THERMDA TEST26
10:10 Y6
AB6
TEST3 TEST10 K8
C4
TEST2 TEST8
P20 RSVD0 RSVD8 H16
1

P19 RSVD1 RSVD9 B18


R373 +1.8V +1.8V N20
300_0402_5% RSVD2
N19 RSVD3 RSVD10 B3
R375 C1
0_0402_5% @ RSVD11
2

U25 CPU_TEST26_BURNIN# R199 1 2 300_0402_5% H6


MCP_PWRGD_R CPU_PRESENT# R198 1 RSVD12
1 2 2 2 1K_0402_5% G6
P

(15,18,27,28) MCP_PWRGD B RSVD13


4 1 2 CPU_HT_RESET# CPU_TEST25_H_BYPASSCLK_H R188 1 2 510_0402_5% D5
Y R377 0_0402_5% RSVD14
(10) HTCPU_RST# 1 A
G

@ R24
NC7SZ08P5X_NL_SC70-5 CPU_TEST21_SCANEN R197 300_0402_5% RSVD15
1 2 W18
3

@ CPU_TEST25_L_BYPASSCLK_L R387 510_0402_5% RSVD16


1 2 R26 RSVD4 RSVD17 R23
CPU_TEST19_PLLTEST0 R385 1 2 300_0402_5% R25 AA8
CPU_TEST18_PLLTEST1 R215 300_0402_5% RSVD5 RSVD18
1 2 P22 RSVD6 RSVD19 H18
1 2 R22 RSVD7 RSVD20 H19
R374 0_0402_5%

FOX_PZ63823-284S-41F

AMD NPT S1 SOCKET


HT@

Processor Socket

+1.8V
220_0402_5%HT@

220_0402_5%HT@

220_0402_5%HT@

220_0402_5%HT@
220_0402_5%

HDT Connector +1.8V +1.8V +3V +3V

1
R163 1

R162 1

R161 1

R160 1

R159 1

1
B +1.8V B
JP7 R114 R127 R117

1
300_0402_5% 1K_0402_5% @ 1K_0402_5%
1 2 +3VS +3V

2
3 4 R116
2

2 2
CPU_DBREQ# 5 6 10K_0402_5%
7 8

2
CPU_DBRDY Q15

2
9 10
1

CPU_TCK R113 Q16 MMBT3904_SOT23


CPU_TMS 11 12 H_THERMTRIP_S#
13 14
220_0402_5% 3 1H_THERMTRIP# 3 1 @ MAINPWON (35,36,37)
CPU_TDI HT@ MMBT3904_SOT23
CPU_TRST# 15 16
17 18
2

CPU_TDO
G

1 2 H_THERMTRIP# (10)
2

19 20 R115 0_0402_5%
21 22 3V_LDT_RST# CPU_HT_RESET# @
23 24 1 2 1 3
R535 0_0402_5%
D

26 @
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY. SAMTEC_ASP-68200-07 Q14
@ 2N7002_SOT23
HT@
+1.8V +3VS
PVT Modify 2007/03/22

1
+3VS R133 R130
10K_0402_5% 4.7K_0402_5%

2CPU_PH_G 2

2
1
1

C269
R186
0.1U_0402_16V4Z @ 10K_0402_5%
2
1

B
C275 Q19
2

U4

E
2200P_0402_50V7K CPU_THERMDA 2 1 1 2 CPU_PROCHOT#_1.8 3 1
2 D+ VDD1 (10) PROCHOT# EC_THERM# (15,27,28)

C
A R141 0_0402_5% MMBT3904_SOT23 A
CPU_THERMDC 3 6 @
D- ALERT#
EC_SMB_CK2 8 4
(27,28) EC_SMB_CK2 SCLK THERM#
EC_SMB_DA2 7 5
(27,28) EC_SMB_DA2 SDATA GND Connect to MCP67
ADM1032ARM_RM8

Security Classification Compal Secret Data


U2 CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PLACE Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

CLOSE TO PROCESSOR WITHIN 1" INCH


AMD CPU CTRL & DEBUG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 6 of 42
5 4 3 2 1
5 4 3 2 1

+CPU_CORE

1 1 1 1
+ C548 + C550 + C546 + C547

470U_D2E_2VM_R9 470U_D2E_2VM_R9 470U_D2E_2VM_R9 330U_D2E_2.5VM_R9


2 2 2 2

D D

+CPU_CORE +CPU_CORE
C287 C288 C289
10U_0805_10V6M 10U_0805_10V6M 10U_0805_10V6M
1 1 1 1 1 1 1 1

PROCESSOR POWER AND GROUND 2 2 2 2 2 2 2


+ C551
820U_E9_2.5V_M_R7
45@
C279 C280 C282 C281 2
10U_0805_10V6M 10U_0805_10V6M 10U_0805_10V6M 10U_0805_10V6M

JP22F
AA4 VSS1 VSS66 J6 10/2 Modify
AA11 VSS2 VSS67 J8
+CPU_CORE +CPU_CORE AA13 J10
JP22E AA15
VSS3
VSS4
VSS68
VSS69 J12 CPU SOCKET S1 DECOUPLING
AC4 VDD1 VDD43 V12 AA17 VSS5 VSS70 J14
AD2 VDD2 VDD44 V14 AA19 VSS6 VSS71 J16
G4 VDD3 VDD45 W4 AB2 VSS7 VSS72 J18
H2 VDD4 Y2 AB7 K2 +CPU_CORE
VDD46 VSS8 VSS73
J9 VDD5 VDD47 J15 AB9 VSS9 VSS74 K7
J11 VDD6 VDD48 K16 AB23 VSS10 VSS75 K9
J13 VDD7 VDD49 L15 AB25 VSS11 VSS76 K11 1 1 1 1 1 1 1 1 1
K6 VDD8 M16 AC11 K13 C315 C326 C332 C333 C327 C328 C324 C316 C334
VDD50 VSS12 VSS77
K10 VDD9 VDD51 P16 AC13 VSS13 VSS78 K15
K12 VDD10 T16 AC15 K17 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_10V6M 22U_0805_6.3V6M 10U_0805_10V6M 10U_0805_10V6M 10U_0805_10V6M 10U_0805_10V6M 22U_0805_6.3V6M
VDD52 VSS14 VSS79 2 2 2 2 2 2 2 2 2
K14 VDD11 VDD53 U15 AC17 VSS15 VSS80 L6
L4 VDD12 VDD54 V16 AC19 VSS16 VSS81 L8
L7 VDD13 +1.8V AC21 L10
VSS17 VSS82
L9 VDD14 AD6 VSS18 VSS83 L12
L11 VDD15 VDDIO1 H25 AD8 VSS19 VSS84 L14
L13 VDD16 VDDIO2 J17 AD25 VSS20 VSS85 L16
M2 VDD17 VDDIO3 K18 AE11 VSS21 VSS86 L18
C +CPU_CORE +1.8V C
M6 VDD18 VDDIO4 K21 AE13 VSS22 VSS87 M7
M8 VDD19 VDDIO5 K23 AE15 VSS23 VSS88 M9
M10 VDD20 VDDIO6 K25 AE17 VSS24 VSS89 M11
Power

N7 VDD21 VDDIO7 L17 AE19 VSS25 VSS90 M17 1 1 1 1 1 1 1 1


N9 VDD22 M18 AE21 N4 C318 C308 C319 C309 C353 C343 C361 C356
VDDIO8 VSS26 VSS91
N11 VDD23 VDDIO9 M21 AE23 VSS27 VSS92 N8
P8 VDD24 M23 B4 N10 0.22U_0402_10V4Z 0.22U_0402_10V4Z 180P_0402_50V8J 0.01U_0402_16V7K 10U_0805_10V6M 10U_0805_10V6M 0.22U_0402_10V4Z 0.22U_0402_10V4Z
VDDIO10 VSS28 VSS93 2 2 2 2 2 2 2 2
P10 VDD25 VDDIO11 M25 B6 VSS29 VSS94 N16
R4 VDD26 VDDIO12 N17 B8 VSS30 VSS95 N18

Ground
R7 VDD27 VDDIO13 P18 B9 VSS31 VSS96 P2
R9 VDD28 VDDIO14 P21 B11 VSS32 VSS97 P7
R11 VDD29 VDDIO15 P23 B13 VSS33 VSS98 P9
T2 VDD30 VDDIO16 P25 B15 VSS34 VSS99 P11
T6 VDD31 VDDIO17 R17 B17 VSS35 VSS100 P17
T8 VDD32 VDDIO18 T18 B19 VSS36 VSS101 R8
T10 VDD33 VDDIO19 T21 B21 VSS37 VSS102 R10
T12 VDD34 VDDIO20 T23 B23 VSS38 VSS103 R16
T14 VDD35 VDDIO21 T25 B25 VSS39 VSS104 R18
U7 VDD36 VDDIO22 U17 D6 VSS40 VSS105 T7
U9 VDD37 V18 D8 T9
U11 VDD38
U13 VDD39
VDDIO23
VDDIO24 V21
V23
D9
D11
VSS41
VSS42
VSS106
VSS107 T11
T13
DECOUPLING BETWEEN PROCESSOR AND DIMMs
VDDIO25 VSS43 VSS108
V6 VDD40 V25 D13 T15
V8 VDD41
VDDIO26
VDDIO27 Y25 D15
VSS44
VSS45
VSS109
VSS110 T17 PLACE CLOSE TO PROCESSOR AS POSSIBLE
V10 VDD42 D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
FOX_PZ63823-284S-41F D21 U8 +1.8V
VSS48 VSS113
D23 VSS49 VSS114 U10
Athlon 64 S1 D25 U12
Processor Socket VSS50 VSS115
E4 VSS51 VSS116 U14 1 1 1 1 1 1 1
F2 U16 C352 C342 C351 C388 C362 C386 C383
VSS52 VSS117
F11 VSS53 VSS118 U18
F13 V2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z
VSS54 VSS119 2 2 2 2 2 2 2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
B A1 A26 F23
F25
VSS59 VSS124 V15
V17 B
VSS60 VSS125
H7 VSS61 VSS126 W6 1 1 1 1 1
H9 Y21 C381 C385 C382 C340 C360
VSS62 VSS127
H21 VSS63 VSS128 Y23
H23 N6 0.22U_0402_10V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 180P_0402_50V8J 180P_0402_50V8J
VSS64 VSS129 2 2 2 2 2
J4 VSS65
Athlon 64 S1g1 FOX_PZ63823-284S-41F
uPGA638 Athlon 64 S1
Processor Socket
Top View +0.9V

1 1 1 1 1 1 1 1
C304 C320 C303 C302 C313 C312 C314 C298
AF1 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z
2 2 2 2 2 2 2 2

1 1 1 1 1 1 1 1
C299 C300 C307 C306 C305 C297 C296 C295

1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J


2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
AMD CPU PWR & GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 7 of 42
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V +DIMM_VREF +1.8V +1.8V

C579

C428
C399 C414 C427 C425 C577 C575

1
R275 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K
JP28 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 VREF VSS 2 1 1
3 4 DDR_A_D4 1K_0402_1% C573
DDR_A_D0 VSS DQ4 DDR_A_D5 0.22U_0603_16V7K
5 6

2
DDR_A_D1 DQ0 DQ5 2 2 2 2 2 2 2 2 2 2 2 2 2 2
7 DQ1 VSS 8
DDR_A_DM0 2 2 C413 C398 C424 C426 C578 C576 C574
9 VSS DM0 10

4.7U_0805_10V4Z

0.1U_0402_16V4Z
D DDR_A_DQS#0 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K0.22U_0603_16V7K D
11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6

1
15 16 DDR_A_D7 R274
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18
DDR_A_D3 19 20 DDR_A_D12
DQ3 DQ12 DDR_A_D13 1K_0402_1%
21 VSS DQ13 22
DDR_A_D8 23 24

2
DDR_A_D9 DQ8 VSS DDR_A_DM1 +1.8V
25 DQ9 DM1 26
27 VSS VSS 28
DDR_A_DQS#1 29 30 DDR_A_CLK1
DQS1# CK0 DDR_A_CLK1 (5)
DDR_A_DQS1 31 32 DDR_A_CLK#1
DQS1 CK0# DDR_A_CLK#1 (5)
33 VSS VSS 34
DDR_A_D10 35 36 DDR_A_D14
DQ10 DQ14

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
DDR_A_D11 37 38 DDR_A_D15 1
DQ11 DQ15
39 VSS VSS 40 1 1 1 1 1 1 1 1 1 1
+ C628
220U_D2_4VM_R15

C407

C408

C409

C410

C411

C412

C415

C416

C417

C418
41 VSS VSS 42
DDR_A_D16 DDR_A_D20 2 2 2 2 2 2 2 2 2 2 2
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21 DDR_A_D[0..63]
DQ17 DQ21 (5) DDR_A_D[0..63]
47 VSS VSS 48
DDR_A_DQS#2 49 50 DDR_A_DM[0..7]
DQS2# NC (5) DDR_A_DM[0..7]
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2 DDR_A_DQS[0..7]
53 VSS VSS 54 (5) DDR_A_DQS[0..7]
DDR_A_D18 55 56 DDR_A_D22
DDR_A_D19 DQ18 DQ22 DDR_A_D23 DDR_A_MA[0..15]
57 DQ19 DQ23 58 (5) DDR_A_MA[0..15]
59 VSS VSS 60
DDR_A_D24 61 62 DDR_A_D28 DDR_A_DQS#[0..7]
DDR_A_D25 DQ24 DQ28 DDR_A_D29 (5) DDR_A_DQS#[0..7] +0.9V
63 DQ25 DQ29 64
65 VSS VSS 66
C DDR_A_DM3 DDR_A_DQS#3 C
67 DM3 DQS3# 68
69 70 DDR_A_DQS3
NC DQS3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D30 1
DDR_A_D27 DQ26 DQ30 DDR_A_D31 C422
75 DQ27 DQ31 76 1 1 1 1 1 1 1 1 1 1 1 1 1 1
77 78 +
DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA
(5) DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA (5)
81 82 150U_D2_6.3VM
DDR_CS2_DIMMA# VDD VDD DDR_A_MA15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
(5) DDR_CS2_DIMMA# 83 NC NC/A15 84

C437

C436

C435

C434

C433

C431

C432

C453

C452

C451

C450

C449

C448

C447
DDR_A_BS#2 85 86 DDR_A_MA14
(5) DDR_A_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 A8 A6 94 DDR_A_MA6 Layout Note:
95 96
DDR_A_MA5 97
VDD VDD
98 DDR_A_MA4 Place one cap close to every 2 pullup
A5 A4
DDR_A_MA3 99 A3 A2 100 DDR_A_MA2 resistors terminated to +0.9V
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1 +0.9V
A10/AP BA1 DDR_A_BS#1 (5)
DDR_A_BS#0 107 108 DDR_A_RAS#
(5) DDR_A_BS#0 BA0 RAS# DDR_A_RAS# (5)
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
(5) DDR_A_WE# WE# S0# DDR_CS0_DIMMA# (5)
111 112 DDR_CKE0_DIMMA 1 4
DDR_A_CAS# VDD VDD DDR_A_ODT0 DDR_CS2_DIMMA#
(5) DDR_A_CAS# 113 CAS# ODT0 114 DDR_A_ODT0 (5) 2 3
DDR_CS1_DIMMA# 115 116 DDR_A_MA13 RP10 47_0404_4P2R_5%
(5) DDR_CS1_DIMMA# NC/S1# NC/A13
117 118 DDR_A_BS#2 1 4 1 4 DDR_A_MA14
DDR_A_ODT1 VDD VDD DDR_CS3_DIMMA# DDR_A_MA12 DDR_A_MA15
(5) DDR_A_ODT1 119 NC/ODT1 NC 120 DDR_CS3_DIMMA# (5) 2 3 2 3
121 122 RP11 47_0404_4P2R_5% RP15 47_0404_4P2R_5%
DDR_A_D32 VSS VSS DDR_A_D36 DDR_A_MA9 DDR_A_MA7
123 DQ32 DQ36 124 1 4 1 4
DDR_A_D33 125 126 DDR_A_D37 DDR_A_MA8 2 3 2 3 DDR_CKE1_DIMMA
B DQ33 DQ37 RP12 47_0404_4P2R_5% RP16 47_0404_4P2R_5% B
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4 DDR_A_MA5 1 4 1 4 DDR_A_MA6
DDR_A_DQS4 DQS4# DM4 DDR_A_MA3 DDR_A_MA11
131 DQS4 VSS 132 2 3 2 3
133 134 DDR_A_D38 RP13 47_0404_4P2R_5% RP17 47_0404_4P2R_5%
DDR_A_D34 VSS DQ38 DDR_A_D39 DDR_A_MA1 DDR_A_MA2
135 DQ34 DQ39 136 1 4 1 4
DDR_A_D35 137 138 DDR_A_MA10 2 3 2 3 DDR_A_MA4
DQ35 VSS DDR_A_D44 RP14 47_0404_4P2R_5% RP20 47_0404_4P2R_5%
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D45 DDR_A_BS#0 1 4 1 4 DDR_A_BS#1
DDR_A_D41 DQ40 DQ45 DDR_A_WE# DDR_A_MA0
143 DQ41 VSS 144 2 3 2 3
145 146 DDR_A_DQS#5 RP9 47_0404_4P2R_5% RP18 47_0404_4P2R_5%
DDR_A_DM5 VSS DQS5# DDR_A_DQS5 DDR_A_CAS# DDR_CS0_DIMMA#
147 DM5 DQS5 148 1 4 1 4
149 150 DDR_CS1_DIMMA# 2 3 2 3 DDR_A_RAS#
DDR_A_D42 VSS VSS DDR_A_D46 RP8 47_0404_4P2R_5% RP19 47_0404_4P2R_5%
151 DQ42 DQ46 152
DDR_A_D43 153 154 DDR_A_D47 DDR_A_ODT1 R277 1 2 47_0402_1% 1 4 DDR_A_MA13
DQ43 DQ47 DDR_CS3_DIMMA# R280
155 VSS VSS 156 1 2 47_0402_1% 2 3 DDR_A_ODT0
DDR_A_D48 157 158 DDR_A_D52 RP21 47_0404_4P2R_5%
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDR_A_CLK2 +1.8V
NC,TEST CK1 DDR_A_CLK2 (5)
165 166 DDR_A_CLK#2
VSS CK1# DDR_A_CLK#2 (5)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172 1 1 1 1 1 1 1 1 1
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 DDR_A_D60 2 2 2 2 2 2 2 2 2
179 DQ56 DQ60 180

C443

C438

C439

C445

C446

C440

C441

C442

C444
DDR_A_D57 181 182 DDR_A_D61
DQ57 DQ61
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7 +0.9V
A DM7 DQS7# DDR_A_DQS7 A
187 VSS DQS7 188
DDR_A_D58 189 DQ58 VSS 190 Layout Note:
DDR_A_D59 191 192 DDR_A_D62
193
DQ59 DQ62
194 DDR_A_D63 Place one 0.1uF cap close to every 2 pullup
VSS DQ63
(9,15) MEM_SMBDATA
MEM_SMBDATA 195 SDA VSS 196 resistors terminated to +0.9V
MEM_SMBCLK 197 198 R281 1 2 10K_0402_5%
(9,15) MEM_SMBCLK SCL SAO
199 200 R282 1 2 10K_0402_5% Security Classification Compal Secret Data
+3VS VDDSPD SA1
1
C429 Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
FOX_AS0A426-M2RN-7F DDR2 SO-DIMM I
0.1U_0402_16V4Z <BOM Structure> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DIMM1 REV H:5.2mm (BOT) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom ICW50 / ICY70 LA-3581P 1.0

Date: Friday, April 20, 2007 Sheet 8 of 42


5 4 3 2 1
5 4 3 2 1

DDR_B_D[0..63]
+1.8V +1.8V +DIMM_VREF (5) DDR_B_D[0..63] +1.8V
DDR_B_DM[0..7] C654 C656
(5) DDR_B_DM[0..7]
1000P_0402_50V7K 1000P_0402_50V7K
DDR_B_DQS[0..7]
(5) DDR_B_DQS[0..7]

0.1U_0402_16V4Z
1 1 1 1

4.7U_0805_10V4Z

C455

C459
JP29 DDR_B_MA[0..15]
(5) DDR_B_MA[0..15]
1 VREF VSS 2 1 1
3 4 DDR_B_D4 DDR_B_DQS#[0..7]
DDR_B_D0 VSS DQ4 DDR_B_D5 (5) DDR_B_DQS#[0..7] 2 2 2 2
5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0 2 2 C653 C655
9 VSS DM0 10
D DDR_B_DQS#0 1000P_0402_50V7K 1000P_0402_50V7K D
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
DDR_B_D2 17 18 +1.8V
DDR_B_D3 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
21 22 DDR_B_D13
DDR_B_D8 VSS DQ13
23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
27 VSS VSS 28 1
DDR_B_DQS#1 29 30 DDR_B_CLK1 1 1 1 1 1 1 1 1 1 1
DQS1# CK0 DDR_B_CLK1 (5) + C629
DDR_B_DQS1 31 32 DDR_B_CLK#1
DQS1 CK0# DDR_B_CLK#1 (5)
33 34 220U_D2_4VM_R15
VSS VSS

C625

C624

C623

C622

C627

C626

C632

C633

C630

C631
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15 2 2 2 2 2 2 2 2 2 2 2
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDR_B_D16 43 44 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_B_DQS#2 49 50 +0.9V
DDR_B_DQS2 DQS2# NC DDR_B_DM2
51 DQS2 DM2 52
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DQ18 DQ22

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D19 57 58 DDR_B_D23
DQ19 DQ23
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D28 1 1 1 1 1 1 1 1 1 1 1 1
DDR_B_D25 DQ24 DQ28 DDR_B_D29
63 DQ25 DQ29 64
65 VSS VSS 66
C DDR_B_DM3 DDR_B_DQS#3 C
67 DM3 DQS3# 68
DDR_B_DQS3 2 2 2 2 2 2 2 2 2 2 2 2
69 NC DQS3 70

C483

C482

C481

C480

C479

C478

C466

C464

C465

C463

C462

C461
71 VSS VSS 72
DDR_B_D26 73 74 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB
(5) DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB (5)
81 VDD VDD 82 Layout Note:
DDR_CS2_DIMMB# 83 84 DDR_B_MA15
(5) DDR_CS2_DIMMB#
DDR_B_BS#2 85
NC NC/A15
86 DDR_B_MA14 Place one cap close to every 2 pullup
(5) DDR_B_BS#2 BA2 NC/A14
87 VDD VDD 88 resistors terminated to +0.9V
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4 +0.9V
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0 DDR_CS2_DIMMB#
103 VDD VDD 104 1 4
DDR_B_MA10 105 106 DDR_B_BS#1 DDR_CKE0_DIMMB 2 3
A10/AP BA1 DDR_B_BS#1 (5)
DDR_B_BS#0 107 108 DDR_B_RAS# RP22 47_0404_4P2R_5%
(5) DDR_B_BS#0 BA0 RAS# DDR_B_RAS# (5)
DDR_B_WE# 109 110 DDR_CS0_DIMMB# DDR_B_MA12 1 4 1 4 DDR_CKE1_DIMMB
(5) DDR_B_WE# WE# S0# DDR_CS0_DIMMB# (5)
111 112 DDR_B_BS#2 2 3 2 3 DDR_B_MA15
DDR_B_CAS# VDD VDD DDR_B_ODT0 RP23 47_0404_4P2R_5% RP30 47_0404_4P2R_5%
(5) DDR_B_CAS# 113 CAS# ODT0 114 DDR_B_ODT0 (5)
DDR_CS1_DIMMB# 115 116 DDR_B_MA13 DDR_B_MA8 1 4 1 4 DDR_B_MA14
(5) DDR_CS1_DIMMB# NC/S1# NC/A13
117 118 DDR_B_MA9 2 3 2 3 DDR_B_MA11
DDR_B_ODT1 VDD VDD DDR_CS3_DIMMB# RP24 47_0404_4P2R_5% RP31 47_0404_4P2R_5%
(5) DDR_B_ODT1 119 NC/ODT1 NC 120 DDR_CS3_DIMMB# (5)
121 122 DDR_B_MA3 1 4 1 4 DDR_B_MA7
DDR_B_D32 VSS VSS DDR_B_D36 DDR_B_MA5 DDR_B_MA6
123 DQ32 DQ36 124 2 3 2 3
DDR_B_D33 125 126 DDR_B_D37 RP25 47_0404_4P2R_5% RP32 47_0404_4P2R_5%
B DQ33 DQ37 DDR_B_MA10 DDR_B_MA4 B
127 VSS VSS 128 1 4 1 4
DDR_B_DQS#4 129 130 DDR_B_DM4 DDR_B_MA1 2 3 2 3 DDR_B_MA2
DDR_B_DQS4 DQS4# DM4 RP26 47_0404_4P2R_5% RP33 47_0404_4P2R_5%
131 DQS4 VSS 132
133 134 DDR_B_D38 DDR_B_WE# 1 4 1 4 DDR_B_MA0
DDR_B_D34 VSS DQ38 DDR_B_D39 DDR_B_BS#0 DDR_B_BS#1
135 DQ34 DQ39 136 2 3 2 3
DDR_B_D35 137 138 RP27 47_0404_4P2R_5% RP34 47_0404_4P2R_5%
DQ35 VSS DDR_B_D44 DDR_CS0_DIMMB# DDR_B_CAS#
139 VSS DQ44 140 1 4 1 4
DDR_B_D40 141 142 DDR_B_D45 DDR_B_RAS# 2 3 2 3 DDR_CS1_DIMMB#
DDR_B_D41 DQ40 DQ45 RP29 47_0404_4P2R_5% RP28 47_0404_4P2R_5%
143 DQ41 VSS 144
145 146 DDR_B_DQS#5 DDR_B_ODT1 R286 1 2 47_0402_1% 1 4 DDR_B_ODT0
DDR_B_DM5 VSS DQS5# DDR_B_DQS5 DDR_CS3_DIMMB# R287
147 DM5 DQS5 148 1 2 47_0402_1% 2 3 DDR_B_MA13
149 150 RP35 47_0404_4P2R_5%
DDR_B_D42 VSS VSS DDR_B_D46
151 DQ42 DQ46 152
DDR_B_D43 153 154 DDR_B_D47
DQ43 DQ47
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162 +1.8V
163 164 DDR_B_CLK2
NC,TEST CK1 DDR_B_CLK2 (5)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
165 166 DDR_B_CLK#2
VSS CK1# DDR_B_CLK#2 (5)
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170 1 1 1 1 1 1 1 1 1 1 1
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
2 2 2 2 2 2 2 2 2 2 2
177 VSS VSS 178

C476

C472

C471

C470

C469

C457

C458

C477

C486

C485

C484
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184 +0.9V
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7#
A
187 VSS DQS7 188 DDR_B_DQS7 Layout Note: A
DDR_B_D58 189 190
DDR_B_D59 191
DQ58 VSS
192 DDR_B_D62 Place one 0.1uF cap close to every 2 pullup
DQ59 DQ62
193 VSS DQ63 194 DDR_B_D63 resistors terminated to +0.9V
MEM_SMBDATA 195 196
(8,15) MEM_SMBDATA SDA VSS
MEM_SMBCLK 197 198 R289 1 2 10K_0402_5% +3VS
(8,15) MEM_SMBCLK SCL SAO
199 200 R288 1 2 10K_0402_5% Security Classification Compal Secret Data
+3VS VDDSPD SA1
1
C456 Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
FOX_AS0A426-MARG-7F DDR2 SO-DIMM II
0.1U_0402_16V4Z Change PCB Footprint THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
DIMM0 REV H:9.2mm (BOT) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 9 of 42
5 4 3 2 1
5 4 3 2 1

U23A
MCP67
H_CADOP0
PART 1 OF 8 H_CADIP0
(4) H_CADOP0 AF16 HT_MCP_RXD0_P HT_MCP_TXD0_P AK27 H_CADIP0 (4)
H_CADON0 AG16 AJ27 H_CADIN0
(4) H_CADON0 HT_MCP_RXD0_N HT_MCP_TXD0_N H_CADIN0 (4)
H_CADOP1 AH16 AK26 H_CADIP1
(4) H_CADOP1 HT_MCP_RXD1_P HT_MCP_TXD1_P H_CADIP1 (4)
H_CADON1 AJ16 AL26 H_CADIN1
D (4) H_CADON1 HT_MCP_RXD1_N HT_MCP_TXD1_N H_CADIN1 (4) D
H_CADOP2 AJ15 AK25 H_CADIP2
(4) H_CADOP2 HT_MCP_RXD2_P HT_MCP_TXD2_P H_CADIP2 (4)
H_CADON2 AK15 AL25 H_CADIN2
(4) H_CADON2 HT_MCP_RXD2_N HT_MCP_TXD2_N H_CADIN2 (4)
H_CADOP3 AK16 AL24 H_CADIP3
(4) H_CADOP3 HT_MCP_RXD3_P HT_MCP_TXD3_P H_CADIP3 (4)
H_CADON3 AL16 AK24 H_CADIN3
(4) H_CADON3 HT_MCP_RXD3_N HT_MCP_TXD3_N H_CADIN3 (4)
H_CADOP4 AG17 AK22 H_CADIP4
(4) H_CADOP4 HT_MCP_RXD4_P HT_MCP_TXD4_P H_CADIP4 (4)
H_CADON4 AF17 AL22 H_CADIN4
(4) H_CADON4 HT_MCP_RXD4_N HT_MCP_TXD4_N H_CADIN4 (4)
H_CADOP5 AL17 AK21 H_CADIP5
(4) H_CADOP5 HT_MCP_RXD5_P HT_MCP_TXD5_P H_CADIP5 (4)
H_CADON5 AK17 AL21 H_CADIN5
(4) H_CADON5 HT_MCP_RXD5_N HT_MCP_TXD5_N H_CADIN5 (4)
H_CADOP6 AL18 AH21 H_CADIP6
(4)
(4)
H_CADOP6
H_CADON6
H_CADON6
H_CADOP7
AK18
HT_MCP_RXD6_P
HT_MCP_RXD6_N
HT HT_MCP_TXD6_P
HT_MCP_TXD6_N AJ21 H_CADIN6
H_CADIP7
H_CADIP6
H_CADIN6
(4)
(4)
(4) H_CADOP7 AJ19 HT_MCP_RXD7_P HT_MCP_TXD7_P AL20 H_CADIP7 (4)
H_CADON7 AK19 AM20 H_CADIN7
(4) H_CADON7 HT_MCP_RXD7_N HT_MCP_TXD7_N H_CADIN7 (4)
H_CADOP8 AD14 AG27 H_CADIP8
(4) H_CADOP8 HT_MCP_RXD8_P HT_MCP_TXD8_P H_CADIP8 (4)
H_CADON8 AE14 AH27 H_CADIN8
(4) H_CADON8 HT_MCP_RXD8_N HT_MCP_TXD8_N H_CADIN8 (4)
H_CADOP9 AF14 AF25 H_CADIP9
(4) H_CADOP9 HT_MCP_RXD9_P HT_MCP_TXD9_P H_CADIP9 (4)
H_CADON9 AG14 AG25 H_CADIN9
(4) H_CADON9 HT_MCP_RXD9_N HT_MCP_TXD9_N H_CADIN9 (4)
H_CADOP10 AH14 AH25 H_CADIP10
(4) H_CADOP10 HT_MCP_RXD10_P HT_MCP_TXD10_P H_CADIP10 (4)
H_CADON10 AJ14 AJ25 H_CADIN10
(4) H_CADON10 HT_MCP_RXD10_N HT_MCP_TXD10_N H_CADIN10 (4)
H_CADOP11 AL13 AE23 H_CADIP11
(4) H_CADOP11 HT_MCP_RXD11_P HT_MCP_TXD11_P H_CADIP11 (4)
H_CADON11 AK13 AF23 H_CADIN11
(4) H_CADON11 HT_MCP_RXD11_N HT_MCP_TXD11_N H_CADIN11 (4)
H_CADOP12 AC15 AD21 H_CADIP12
(4) H_CADOP12 HT_MCP_RXD12_P HT_MCP_TXD12_P H_CADIP12 (4)
H_CADON12 AD15 AE21 H_CADIN12
(4) H_CADON12 HT_MCP_RXD12_N HT_MCP_TXD12_N H_CADIN12 (4)
H_CADOP13 AD16 AF21 H_CADIP13
(4) H_CADOP13 HT_MCP_RXD13_P HT_MCP_TXD13_P H_CADIP13 (4)
H_CADON13 AE16 AG21 H_CADIN13
(4) H_CADON13 HT_MCP_RXD13_N HT_MCP_TXD13_N H_CADIN13 (4)
H_CADOP14 AE17 AC20 H_CADIP14
(4) H_CADOP14 HT_MCP_RXD14_P HT_MCP_TXD14_P H_CADIP14 (4)
H_CADON14 AD17 AD20 H_CADIN14
(4) H_CADON14 HT_MCP_RXD14_N HT_MCP_TXD14_N H_CADIN14 (4)
H_CADOP15 AB17 AE19 H_CADIP15
(4) H_CADOP15 HT_MCP_RXD15_P HT_MCP_TXD15_P H_CADIP15 (4)
H_CADON15 AC17 AF19 H_CADIN15
(4) H_CADON15 HT_MCP_RXD15_N HT_MCP_TXD15_N H_CADIN15 (4)
C C

H_CLKOP0 AJ17 AK23 H_CLKIP0 9/25 Modify TO +3VS


(4) H_CLKOP0 HT_MCP_RX_CLK0_P HT_MCP_TX_CLK0_P H_CLKIP0 (4)
H_CLKON0 AH17 AJ23 H_CLKIN0
(4) H_CLKON0 HT_MCP_RX_CLK0_N HT_MCP_TX_CLK0_N H_CLKIN0 (4)
H_CLKOP1 AL14 AG23 H_CLKIP1
(4) H_CLKOP1 HT_MCP_RX_CLK1_P HT_MCP_TX_CLK1_P H_CLKIP1 (4)
H_CLKON1 AK14 AH23 H_CLKIN1
(4) H_CLKON1 HT_MCP_RX_CLK1_N HT_MCP_TX_CLK1_N H_CLKIN1 (4) +3VS

H_CTLOP0 AH19 AK20 H_CTLIP0


(4) H_CTLOP0 HT_MCP_RXCTL0_P HT_MCP_TXCTL0_P H_CTLIP0 (4)

1
H_CTLON0 AG19 AJ20 H_CTLIN0
(4) H_CTLON0 HT_MCP_RXCTL0_N HT_MCP_TXCTL0_N H_CTLIN0 (4)
AC18 AD19 R164
HT_MCP_RXCTL1_P/RESERVED RESERVED/HT_MCP_TXCTL1_P
AD18 HT_MCP_RXCTL1_N/RESERVED RESERVED/HT_MCP_TXCTL1_N AC19 22K_0402_5%

2
AC13 AD23 HTCPU_REQ#
(6) H_THERMTRIP# THERMTRIP#/GPIO_58 HT_MCP_REQ#
AB13 AB20 HTCPU_STOP#
(6) PROCHOT# PROCHOT#/GPIO_20 HT_MCP_STOP# HTCPU_STOP# (6)
AC21 HTCPU_RST#
HT_MCP_RST# HTCPU_RST# (6)
AD22 HTCPU_PWRGD
HT_MCP_PWRGD HTCPU_PWRGD (6)
C46 C43
+3VS L7 1 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z +3.3V_PLL_CPU AB16
MBK1608121YZF_0603 +3.3V_PLL_CPU
CLKOUT_200MHZ_P AL28 CPUCLK (6)
1 1 CLKOUT_200MHZ_N AM28 CPUCLK# (6)
+1.2V_PLL_CPU_HT AB15 +1.2V_PLL_CPU_HT
+1.2V_HT +1.2V_HT
2 2 TP4 PAD
CLKOUT_25MHZ AK28
1 2 AM12 HT_MCP_COMP_VDD
R364 150_0402_1% AG28
CPU_SBVREF
B 1 2 AL12 AJ28 B
C141 R366 150_0402_1% HT_MCP_COMP_GND CLK200_TERM_GND

+1.2V_HT L13 1 2 10U_0805_10V4Z

1
MBK1608121YZF_0603 C101 MCP67-MV_PBGA836 1
1 1 0.1U_0402_16V4Z R123
2.37K_0402_1% C136
0.1U_0402_16V4Z
2

2
2 2

A A

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
MCP67 HT LINK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 10 of 42
5 4 3 2 1
5 4 3 2 1

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
(18) PCIE_GTX_C_MRX_P[0..15] (18) PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
(18) PCIE_GTX_C_MRX_N[0..15] (18) PCIE_MTX_C_GRX_N[0..15]
U23B CLOSE TO CONNECT
MVP67
PCIE_GTX_C_MRX_P0
PART 2 OF 8 PCIE_MTX_GRX_P0 VGA@ C193 PCIE_MTX_C_GRX_P0
F23 PE0_RX0_P PE0_TX0_P D24 1 2 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N0 G23 C24 PCIE_MTX_GRX_N0 C194 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N0
PCIE_GTX_C_MRX_P1 PE0_RX0_N PE0_TX0_N PCIE_MTX_GRX_P1 VGA@ C166 PCIE_MTX_C_GRX_P1
F24 PE0_RX1_P PE0_TX1_P A24 1 2 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N1 F25 B24 PCIE_MTX_GRX_N1 C167 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N1
PCIE_GTX_C_MRX_P2 PE0_RX1_N PE0_TX1_N PCIE_MTX_GRX_P2 VGA@ C195 PCIE_MTX_C_GRX_P2
D25 PE0_RX2_P PE0_TX2_P B25 1 2 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N2 D26 C25 PCIE_MTX_GRX_N2 C196 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N2
D PCIE_GTX_C_MRX_P3 PE0_RX2_N PE0_TX2_N PCIE_MTX_GRX_P3 VGA@ C168 PCIE_MTX_C_GRX_P3 D
C28 PE0_RX3_P PE0_TX3_P B26 1 2 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N3 D28 C26 PCIE_MTX_GRX_N3 C169 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 PE0_RX3_N PE0_TX3_N PCIE_MTX_GRX_P4 VGA@ C197
C29 PE0_RX4_P PE0_TX4_P C27 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_GTX_C_MRX_N4 C30 D27 PCIE_MTX_GRX_N4 C198 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N4
PCIE_GTX_C_MRX_P5 PE0_RX4_N PE0_TX4_N PCIE_MTX_GRX_P5 VGA@ C170 PCIE_MTX_C_GRX_P5
D29 PE0_RX5_P PE0_TX5_P A28 1 2 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N5 PCIE_MTX_GRX_N5 C171 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N5

PCIE GFX I/F


D30 PE0_RX5_N PE0_TX5_N B28
PCIE_GTX_C_MRX_P6 F26 A29 PCIE_MTX_GRX_P6 VGA@ C199 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_N6 PE0_RX6_P PE0_TX6_P PCIE_MTX_GRX_N6 C200 1
F27 PE0_RX6_N PE0_TX6_N B29 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N6
PCIE_GTX_C_MRX_P7 F28 A30 PCIE_MTX_GRX_P7 VGA@ C172 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_N7 PE0_RX7_P PE0_TX7_P PCIE_MTX_GRX_N7 C173 1 PCIE_MTX_C_GRX_N7
F29 PE0_RX7_N PE0_TX7_N B30 2 0.1U_0402_16V7K VGA@
PCIE_GTX_C_MRX_P8 H23 B31 PCIE_MTX_GRX_P8 VGA@ C201 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_GTX_C_MRX_N8 PE0_RX8_P PE0_TX8_P PCIE_MTX_GRX_N8 C202 1 PCIE_MTX_C_GRX_N8
H24 PE0_RX8_N PE0_TX8_N B32 2 0.1U_0402_16V7K VGA@
PCIE_GTX_C_MRX_P9 H25 C31 PCIE_MTX_GRX_P9 VGA@ C174 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 PE0_RX9_P PE0_TX9_P PCIE_MTX_GRX_N9 C175 1 PCIE_MTX_C_GRX_N9
H26 PE0_RX9_N PE0_TX9_N C32 2 0.1U_0402_16V7K VGA@
PCIE_GTX_C_MRX_P10 H27 D31 PCIE_MTX_GRX_P10 VGA@ C203 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_GTX_C_MRX_N10 PE0_RX10_P PE0_TX10_P PCIE_MTX_GRX_N10 C204 1 PCIE_MTX_C_GRX_N10
H28 PE0_RX10_N PE0_TX10_N D32 2 0.1U_0402_16V7K VGA@
PCIE_GTX_C_MRX_P11 K24 E31 PCIE_MTX_GRX_P11 VGA@ C176 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_GTX_C_MRX_N11 PE0_RX11_P PE0_TX11_P PCIE_MTX_GRX_N11 C177 1
K25 PE0_RX11_N PE0_TX11_N E30 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N11
PCIE_GTX_C_MRX_P12 K27 F31 PCIE_MTX_GRX_P12 VGA@ C228 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_GTX_C_MRX_N12 PE0_RX12_P PE0_TX12_P PCIE_MTX_GRX_N12 C229 1 PCIE_MTX_C_GRX_N12
K26 PE0_RX12_N PE0_TX12_N F30 2 0.1U_0402_16V7K VGA@
+3V PCIE_GTX_C_MRX_P13 K28 G29 PCIE_MTX_GRX_P13 VGA@ C237 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PCIE_GTX_C_MRX_N13 PE0_RX13_P PE0_TX13_P PCIE_MTX_GRX_N13 C238 1 PCIE_MTX_C_GRX_N13
K29 PE0_RX13_N PE0_TX13_N G30 2 0.1U_0402_16V7K VGA@
PCIE_GTX_C_MRX_P14 J31 H29 PCIE_MTX_GRX_P14 VGA@ C230 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PE0_RX14_P PE0_TX14_P

1
PCIE_GTX_C_MRX_N14 J30 H30 PCIE_MTX_GRX_N14 C231 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N14
R45 PCIE_GTX_C_MRX_P15 PE0_RX14_N PE0_TX14_N PCIE_MTX_GRX_P15 VGA@ C239 PCIE_MTX_C_GRX_P15
K31 PE0_RX15_P PE0_TX15_P H32 1 2 0.1U_0402_16V7K
10K_0402_5% PCIE_GTX_C_MRX_N15 K30 H31 PCIE_MTX_GRX_N15 C240 1 2 0.1U_0402_16V7K VGA@ PCIE_MTX_C_GRX_N15
PE0_RX15_N PE0_TX15_N
@

(25,26,27) MCP_PCIE_WAKE# 2 MCP_PCIE_WAKE# H17 PE_WAKE#/GPIO_21 PE0_REFCLK_P R29 CLK_PCIE_VGA CLK_PCIE_VGA (18)
R365 2 1 10K_0402_5% @ U31 PE0_PRSNTX1#/DDC_CLK1 PE0_REFCLK_N R30 CLK_PCIE_VGA# CLK_PCIE_VGA# (18)
C R367 2 1 10K_0402_5% @ U30 C
R149 2 PE0_PRSNTX4#/DDC_DATA1
1 10K_0402_5% @ U29 PE0_PRSNTX8#/EXP_EN
(18) PE_PRSNTX16# U28 PE0_PRSNTX16#
EXPRESS@ EXPRESS@
R146 1 2 0_0402_5% PCIE_MRX_PTX_P1_R L29 M28 PCIE_MTX_PRX_P1 C249 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_P1
(26) PCIE_MRX_PTX_P1 PE1_RX_P PE1_TX_P PCIE_MTX_C_PRX_P1 (26)
(26) PCIE_MRX_PTX_N1
R147 1 2 0_0402_5% PCIE_MRX_PTX_N1_R L30 PE1_RX_N PE1_TX_N M29 PCIE_MTX_PRX_N1 C248 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_N1
PCIE_MTX_C_PRX_N1 (26) NEW CARD
EXPRESS@ W27 T32 CLK_PCIE_CARD
(26) EXP_CLKREQ# PEA_CLKREQ# PE1_REFCLK_P CLK_PCIE_CARD (26)
+3VS R152 2 1 10K_0402_5% W28 T31 EXPRESS@ CLK_PCIE_CARD#
PEA_PRSNT# PE1_REFCLK_N CLK_PCIE_CARD# (26)
PEA_PRSNT# EXPRESS@
MINI2@
(25) PCIE_MRX_PTX_P2
R139 1 2 0_0402_5% MINI2@ PCIE_MRX_PTX_P2_R M26 PE2_RX_P PE2_TX_P M24 PCIE_MTX_PRX_P2 C220 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_P2 PCIE_MTX_C_PRX_P2 (25) MINI_CARD(WLAN)
R140 1 2 0_0402_5% MINI2@ PCIE_MRX_PTX_N2_R M27 M25 PCIE_MTX_PRX_N2 C219 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_N2 PCIE_MTX_C_PRX_N2 (25)
(25) PCIE_MRX_PTX_N2 PE2_RX_N PE2_TX_N
(25) MINI2_CLKREQ# U26 T29 CLK_PCIE_MINI2
PEB_CLKREQ# PE2_REFCLK_P CLK_PCIE_MINI2 (25)
+3VS R118 2 1 10K_0402_5% U27 T30 MINI2@ CLK_PCIE_MINI2#
PEB_PRSNT# PE2_REFCLK_N CLK_PCIE_MINI2# (25)
PEB_PRSNT# MINI2@
MINI1@ MINI1@
(25) PCIE_MRX_PTX_P3
R134 1 2 0_0402_5% PCIE_MRX_PTX_P3_R N23 PE3_RX_P PE3_TX_P M22 PCIE_MTX_PRX_P3 C235 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_P3 PCIE_MTX_C_PRX_P3 (25) MINI_CARD(TV)
R135 1 2 0_0402_5% PCIE_MRX_PTX_N3_R N22 M23 PCIE_MTX_PRX_N3 C234 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_N3 PCIE_MTX_C_PRX_N3 (25)
(25) PCIE_MRX_PTX_N3 PE3_RX_N PE3_TX_N
(25) MINI1_CLKREQ# MINI1@ U25 T27 CLK_PCIE_MINI1
PEC_CLKREQ# PE3_REFCLK_P CLK_PCIE_MINI1 (25)
+3VS R148 2 1 10K_0402_5% U24 T28 MINI1@ CLK_PCIE_MINI1#
PEC_PRSNT# PE3_REFCLK_N CLK_PCIE_MINI1# (25)
PEC_PRSNT# MINI1@

N30 PE4_RX_P PE4_TX_P M30


N31 PE4_RX_N PE4_TX_N M31
R22 PED_CLKREQ#/GPIO_16 PE4_REFCLK_P T25
U23 PED_PRSNT# PE4_REFCLK_N T26

P31 PE5_RX_P PE5_TX_P P29


B P30 P28 B
PE5_RX_N PE5_TX_N +3V
T22 PEE_CLKREQ#/GPIO_17 PE5_REFCLK_P T23
V31 PEE_PRSNT# PE5_REFCLK_N T24
1
C115 C105 C267
+1.2VS L19 1 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z P26 P24 0.1U_0402_16V4Z
MBK1608121YZF_0603 PE6_RX_P PE6_TX_P
P27 PE6_RX_N PE6_TX_N P25
2
1 1 U22 PEF_CLKREQ#/GPIO_18 PE6_REFCLK_P P23

5
V30 R23 U5
PEF_PRSNT# PE6_REFCLK_N (15,31) HT_VLD HT_VLD 2

P
B PCIE_RST#
Y 4 PCIE_RST# (18,26)
2 2 +1.2V_PLL_PE_SS1 PE_RST0#
U19 +1.2V_PLL_PE_SS1 1 A

G
U20 +1.2V_PLL_PE_SS2 NC7SZ08P5X_NL_SC70-5 FOR VGA,LAN,NEW CARD

3
@

+1.2VS L5 1 2 +1.2V_PLL_PE1 R20 W30 PE_RST0#


MBK1608121YZF_0603 +1.2V_PLL_PE1 PEX_RST#
R19 +1.2V_PLL_PE2 R170 1 2 0_0402_5%

C18 C104
+3VS L6 1 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z +3.3V_PLL_PE_SS1 P19 W29 R165 1 2 0_0402_5% PCIE_RST1#
+3.3V_PLL_PE_SS1 PEX_RST1# PCIE_RST1# (25)
MBK1608121YZF_0603
MP 2007/4/12 Added 1 1 1 1
P20 +3.3V_PLL_PE_SS2
FOR MINI CARD
2 1 @ PEA_PRSNT#
R550 1K_0402_1% V24
2 2 2 2 PE_CLK_COMP
2 1 MINI2@ PEB_PRSNT# @ R169 0_0402_5%
1

R551 1K_0402_1% MCP67-MV_PBGA836 PCIE_RST1# 1 2 PCIE_RST#


A C25 C26 R145 A
2 1 MINI1@ PEC_PRSNT# 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2.37K_0402_1%
R552 1K_0402_1% @
2

PEA_PRSNT# 1 2 EXP_CLKREQ# Security Classification Compal Secret Data


R553 0_0402_5% @
PEB_PRSNT# 1 2 MINI2_CLKREQ# Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
R554 0_0402_5% @ (14,26) CP_PE# 1 2 PEA_PRSNT# MCP67 PCIE LINK
PEC_PRSNT# 1 2 MINI1_CLKREQ# R563 0_0402_5% EXPRESS@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R555 0_0402_5% @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 11 of 42
5 4 3 2 1
5 4 3 2 1

+3V +3VMAC

+3VMAC +1.2VALW +3VMAC


U23C
1 2 MCP67 R52 0_0603_5%
R556 @ 0_0805_5% PART 3 OF 8 L14 1 2
+3.3V_DUAL_RMGT

1
RXD0 B20
+3VMAC +3VMAC (22) RXD0 RGMII_RXD0/MII_RXD0
+3VAUX RXD1 R79 0_0603_5% @ R472
(22) RXD1
RXD2
C20
E19
RGMII_RXD1/MII_RXD1 LAN N18 +1.2VALW_MAC 1 2 10K_0402_5%
(22) RXD2 RGMII_RXD2/MII_RXD2 +1.2V_DUAL_RMGT
RXD3 F19 1 C44 @
(22) RXD3 RGMII_RXD3/MII_RXD3
1 2 RXCLK G19 J19 TXD0_R R473 1 2 22_0402_5% TXD0 (22) 0.1U_0402_16V4Z
(22) RXCLK

2
R557 0_0805_5% RXCTL RGMII_RXC/MII_RXCLK RGMII_TXD0/MII_TXD0 TXD1_R R471 22_0402_5% RGMII_PWRDWN#
(22) RXCTL J20 RGMII_RXCTL/MII_RXDV RGMII_TXD1/MII_TXD1 K19 1 2 TXD1 (22)

1
D +3VMAC L19 TXD2_R R474 1 2 22_0402_5% D
RGMII_TXD2/MII_TXD2 TXD2 (22)

1
TXD3_R R475 22_0402_5% 2
C19 MII_RXER/GPIO_36 RGMII_TXD3/MII_TXD3 L18 1 2 TXD3 (22)
40 mil R479 2 1 10K_0402_5% @ J18 H19 TXCLK_R R476 1 2 33_0402_5% TXCLK R478
L9 R321 10K_0402_5% @ MII_COL/MI2C_DATA RGMII_TXCLK/MII_TXCLK TXCTL_R R477 22_0402_5% +3VMAC 10K_0402_5%
D19 MII_CRS/MI2C_CLK RGMII_TXCTL/MII_TXEN K18 1 2 TXCTL (22)
MBK1608121YZF_0603 2 1 RGMII_INTR_R
MP Modify 2007/04/13 K20 RGMII_MDC (22)

2
RGMII_INTR RGMII/MII_MDC
(22) RGMII_INTR 1 2 RGMII_INTR_R B18 RGMII/MII_INTR/GPIO35 RGMII/MII_MDIO L20 RGMII_MDIO (22)

1
R349 R514 0_0402_5%
C51 49.9_0402_1% N13 +3.3V_PLL_MAC_DUAL RGMII/MII_PWRDWN#/GPIO_37 D17 RGMII_PWRDWN# R69
4.7U_0805_10V4Z 1.47K_0402_1%
B17 G17 R94 1 2 10K_0402_5%
MII_COMP_3P3V BUF_25MHZ @
1 1 C17

2
MII_COMP_GND
MII_RESET# C18 MII_RST (22) C40
H20 0.1U_0402_16V4Z
MII_VREF
2 2 C53
MP Modify 2007/04/19

1
0.1U_0402_16V4Z 1

1
1 1 R61
K21 B21 UMA_CRT_R 1.47K_0402_1% TXCLK_R
RGB_DAC_RSET RGB_DAC_RED UMA_CRT_R (19)
R68 UMA_CRT_G
D21 RGB_DAC_VREF DACS RGB_DAC_GREEN C21 UMA_CRT_G (19)

1
49.9_0402_1% UMA_CRT_B 2
B22 UMA_CRT_B (19)

2
R67 C55 2 R66 2 C103 RGB_DAC_BLUE C658
E23
2

2
124_0402_1% 0.01U_0402_16V7K 124_0402_1% 0.01U_0402_16V7K H22 TV_DAC_RSET 33P_0402_50V8K
G21 UMA_CRT_HSYNC (19)

2
TV_DAC_VREF RGB_DAC_HSYNC @
RGB_DAC_VSYNC H21 UMA_CRT_VSYNC (19) +3VS
+3.3V_PLL N15 +3.3V_PLL_DISP DDC_CLK0 G8 UMA_CRT_CLK (19)
NB_XTALIN E17 H8
NB_XTALOUT TV_XTALIN DDC_DATA0 C42 UMA_CRT_DATA (19) L8 TXCLK
F17 TV_XTALOUT
+3V +3V +3V Y3 E21 0.1U_0402_16V4Z 1 2
+3.3V_RGB_DAC

1
1 2 1 1 C36 MBK2012121YZF_0805
C C
1 1 4.7U_0805_10V4Z C681
1

1 27MHZ_20P_7A27000010 1 1 C58 1 C38 33P_0402_50V8K

2
R525 UMA&TV@ 0.1U_0402_16V4Z 4.7U_0805_10V4Z @
1

10K_0402_5% C508 C507 C66 2 2 C61


R526 22P_0402_50V8J 22P_0402_50V8J 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2
2 UMA&TV@ 2 UMA&TV@ 2 2
10K_0402_5%
2

@ U40
+3.3V_TV_DAC F21
TXCLK 1 8 U11 UMA@
2

CLKIN NC GPIO_6/FERR//SYS_SERR/IGPU_GPIO_6* UMA_TV_CRMA UMA_CRT_R R63 1


T11 GPIO_7/NFERR//SYS_PERR/IGPU_GPIO_7* TV_DAC_RED C23 UMA_TV_CRMA (19) 2 150_0402_1%
2 7 C22 UMA_TV_LUMA UMA@
SS% NC C682 TV_DAC_GREEN UMA_TV_LUMA (19)
D23 UMA_TV_COMPS UMA_CRT_G R62 1 2 150_0402_1%
TV_DAC_BLUE UMA_TV_COMPS (19)
3 6 1 2 AD24 UMA@
GND VDD (20,27,28) DPST_PWM LCD_BKL_CTL
(18,27,28) ENBKL 1 2 LCD_BKLT_EN AE25 LCD_BKL_ON
UMA_CRT_B R64 1 2 150_0402_1%
1

4 5 R121 0_0402_5% UMA@ AE27 AE30 UMA_TXCLK+


SSON CLKOUT 0.1U_0402_16V4Z (20) UMA_ENVDD LCD_PANEL_PWR IFPA_TXC_P UMA_TXCLK+ (20)
R527 AE31 UMA_TXCLK-
IFPA_TXC_N UMA_TXCLK- (20)
10K_0402_5% S IC PCS3P23Z01DG-08-TR TSSOP 8P
TXCLK_PHY_R 1 2 TXCLK_PHY TXCLK_PHY (22) AL29
R528 22_0402_5% HDMI_TXC_P UMA_TXOUT0+
AM29 AC30 UMA_TXOUT0+ (20)
2

HDMI_TXC_N IFPA_TXD0_P UMA_TXOUT0- UMA&TV@


IFPA_TXD0_N AC29 UMA_TXOUT0- (20)
AC27 UMA_TXOUT1+ UMA_TV_CRMA R3321 2 150_0402_1%
IFPA_TXD1_P UMA_TXOUT1+ (20)
AK29 AC28 UMA_TXOUT1- UMA&TV@
HDMI_TXD0_P IFPA_TXD1_N UMA_TXOUT1- (20)
TXCLK 2 TXCLK_PHY_R UMA_TXOUT2+ UMA_TV_LUMA R3241 2 150_0402_1%
1
R529 0_0402_5% @
AJ29 HDMI_TXD0_N FLAT PANEL IFPA_TXD2_P AD30
UMA_TXOUT2-
UMA_TXOUT2+ (20)
UMA&TV@
PVT Modify 2007/03/12 AM30
AL30
HDMI_TXD1_P IFPA_TXD2_N AD29
AD31
UMA_TXOUT2- (20)
UMA_TV_COMPS R3251 2 150_0402_1%
HDMI_TXD1_N IFPA_TXD3_P
AK30 HDMI_TXD2_P IFPA_TXD3_N AD32
+1.8VS +3VS +3VS +3VS AJ30 HDMI_TXD2_N UMA_TZCLK+
IFPB_TXC_P AJ31 UMA_TZCLK+ (20)
AJ32 UMA_TZCLK-
IFPB_TXC_N UMA_TZCLK- (20)
R24 1 2 22K_0402_5% AE26 HPLUG_DET3
1

L25 L20 R138 1 2 6.2K_0402_5% AL32 AE28 UMA_TZOUT0+


HPLUG_DET2 IFPB_TXD4_P UMA_TZOUT0+ (20)
1

B MBK1608121YZF_0603 MBK1608121YZF_0603 AE29 UMA_TZOUT0- B


IFPB_TXD4_N UMA_TZOUT0- (20) +3VS
L22 AD25 AF30 UMA_TZOUT1+
HDCP_ROM_SCLK IFPB_TXD5_P UMA_TZOUT1+ (20)
L24 MBK1608121YZF_0603 +3VS R136 1 2 10K_0402_5% AC26 AF31 UMA_TZOUT1-
HDCP_ROM_SDATA IFPB_TXD5_N UMA_TZOUT1- (20)
MBK1608121YZF_0603 AG30 UMA_TZOUT2+ UMA@
IFPB_TXD6_P UMA_TZOUT2+ (20)
@ AG29 UMA_TZOUT2- R361 1 2 2.7K_0402_5% UMA_LCD_CLK
UMA_TZOUT2- (20)
2

C210 C190 IFPB_TXD6_N


AC24 AH31
2

+1.8V_IFP_MCP +1.8V_IFPA IFPB_TXD7_P


4.7U_0805_10V4Z 1U_0402_6.3V4Z AC25 +1.8V_IFPB IFPB_TXD7_N AH30 R359 1 2 2.7K_0402_5% UMA_LCD_DATA

1 1 1 C221 +3.3V_PLL_IFPP AC23 L21 UMA_LCD_CLK UMA_LCD_CLK (20)


0.1U_0402_16V4Z +3.3V_IFPAB_HVDD DDC_CLK2 UMA_LCD_DATA
AC22 +3.3V_HDMI_PLL_HVDD DDC_DATA2 J22 UMA_LCD_DATA (20)

1 1 1 DDC_CLK3 L22
2 2 2 +3.3V_HDMI DDC_DATA3 DDC_DATA3
AH29 +3.3V_HDMI DDC_DATA3 K22 1 2
R57 10K_0402_5%
C148
0.1U_0402_16V4Z 2 2 2 C212
AK31 HDMI_RSET
C211 0.01U_0402_16V7K AK32 AB31 IFPAB_RSET
4.7U_0805_10V4Z HDMI_VPROBE IFPAB_RSET IFPAB_PROBE
IFPAB_VPROBE AB30
1

1
1 1
C178 MCP67-MV_PBGA836
4.7U_0805_10V4Z R144 C160 R372
1K_0402_1% 0.1U_0402_16V4Z 1K_0402_1%
@ 2 @ 2 C528 @
1
2

2
+3V +3V 0.01U_0402_16V7K
MP Modify 2007/04/13 +1.2VALW
1
@
2
1

2 C163
R558 0.1U_0402_16V4Z
1

A R559 10K_0402_5% A
20K_0402_1% PVT Modify 2007/03/12
PVT Modify 2007/03/12
2

S
G
2 Q62
2

AO3413_SOT23-3
1

D
Security Classification Compal Secret Data
D
1

1 2 2 Q63
(15,22) SLP_RMGT#
G 2N7002_SOT23 +1.2VALW_MAC 1 C691 Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
R560 S 0.1U_0402_16V4Z MCP67 LAN/ CRT/ LVDS
3

0_0402_5% 6 mil THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2 Custom ICW50 / ICY70 LA-3581P 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 12 of 42
5 4 3 2 1
5 4 3 2 1

+3V
SBPWR_EN# (34)
RP3
1 8 PCI_REQ#0 U23D
+3VS

1
2 7 PCI_REQ#1 MCP67 U32
3 6 PCI_REQ#2 PART 4 OF 8

OE#
4 5 PCI_REQ#3 (23) PCI_REQ#0 PCI_REQ#0 E10 F10 PCI_GNT#0 PCI_GNT#0 (23) PCI_PME# 2 4 EC_PME#
PCI_REQ0# PCI_GNT0# A Y EC_PME# (27,28)
PCI_REQ#1 G10 H10
PCI_REQ1# PCI_GNT1#

G
8.2K_1206_8P4R_5% PCI_REQ#2 J10 K10 Internal PU
PCI_REQ#3 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_GNT2#/GPIO_41/RS232_DTR# SN74AHCT1G125DCKR_SC70-5
M11 L10

3
PCI_REQ#4 PCI_REQ3#/GPIO_38/RS232_CTS# PCI_GNT3#/GPIO_39/RS232_RTS#
E8 PCI_REQ4#/GPIO_52/RS232_SIN# PCI_GNT4#/GPIO_53/RS232_SOUT# F8 @
D D
RP6 PCI_CBE#[3..0]
PCI_CBE#[3..0] (23)
1 8 PCI_PIRQE# PCI_AD[31..0] K12 PCI_CBE#0
+3VS (23) PCI_AD[31..0] PCI_CBE0#
2 7 PCI_PIRQF# PCI_AD0 D10 K13 PCI_CBE#1
PCI_PIRQG# PCI_AD1 PCI_AD0 PCI_CBE1# PCI_CBE#2 +3VS
3 6 B10 F14
4 5 PCI_PIRQH# PCI_AD2
PCI_AD3
C10
L12
PCI_AD1
PCI_AD2 PCI PCI_CBE2#
PCI_CBE3# K16 PCI_CBE#3

8.2K_1206_8P4R_5% PCI_AD4 PCI_AD3 PCI_DEVSEL# RP2


K11 PCI_AD4 PCI_DEVSEL# L13 PCI_DEVSEL# (23)
PCI_AD5 J11 J14 PCI_FRAME# PCI_FRAME# (23)
PCI_AD6 PCI_AD5 PCI_FRAME# PCI_IRDY# LPC_AD0
D11 PCI_AD6 PCI_IRDY# H14 PCI_IRDY# (23) 1 8
PCI_AD7 C11 B14 PCI_PAR PCI_PAR (23) LPC_AD1 2 7
RP5 PCI_AD8 PCI_AD7 PCI_PAR PCI_PERR# LPC_AD2
J12 PCI_AD8 PCI_PERR#/GPIO_43/RS232_DCD# J13 PCI_PERR# (23) 3 6
1 8 PCI_SERR# PCI_AD9 H12 C13 PCI_SERR# PCI_SERR# (23) LPC_AD3 4 5
+3VS PCI_AD9 PCI_SERR#
2 7 PCI_TRDY# PCI_AD10 G12 B13 PCI_STOP# PCI_STOP# (23)
PCI_FRAME# PCI_AD11 PCI_AD10 PCI_STOP# 8.2K_1206_8P4R_5%
3 6 F12 PCI_AD11
4 5 PCI_STOP# PCI_AD12 E12 C16 PCI_PME# @
PCI_AD13 PCI_AD12 PCI_PME#/GPIO_30 LPC_DRQ#0 R38
D12 PCI_AD13 1 2 8.2K_0402_5% @
8.2K_1206_8P4R_5% PCI_AD14 C12 LPC_DRQ#1 R72 1 2 8.2K_0402_5% @
PCI_AD15 PCI_AD14 R30
B12 PCI_AD15 PCI_RESET0# J9 1 2 33_0402_5% PCI_RST1394# (23) SERIRQ R36 1 2 10K_0402_5% @
PCI_AD16 G14
PCI_AD17 PCI_AD16 R33
E14 PCI_AD17 PCI_RESET1# K9 1 2 33_0402_5% PCIRST_IDE# (21)
RP4 PCI_AD18 D14 CLK_PCI_LPC_R
PCI_AD19 PCI_AD18
+3VS 1 8 J15 PCI_AD19 PCI_RESET2# K8 PAD T4 1 C37
2 7 PCI_IRDY# PCI_AD20 C14 10P_0402_50V8J
PCI_PERR# PCI_AD21 PCI_AD20
3 6 D15 PCI_AD21 PCI_RESET3# L9 PAD T5
4 5 PCI_DEVSEL# PCI_AD22 K15
PCI_AD23 PCI_AD22 @ 2
C15 PCI_AD23
8.2K_1206_8P4R_5% PCI_AD24 L16
PCI_AD25 PCI_AD24 CLK_PCI_1394_R R40
G16 PCI_AD25 PCI_CLK0 C9 1 2 22_0402_5% CLK_PCI_1394 (23)
PCI_AD26 J16 B9
C PCI_AD27 PCI_AD26 PCI_CLK1 C
E16 PCI_AD27 PCI_CLK2 B8
RP1 PCI_AD28 H16 A8
PCI_REQ#4 PCI_AD29 PCI_AD28 PCI_CLK3 PCI_CLK4 R46
+3VS 1 8 D16 PCI_AD29 PCI_CLK4 C8 1 2 22_0402_5%
2 7 PCI_AD30 F16 D8 PCI_CLKIN
PM_CLKRUN# PCI_AD31 PCI_AD30 PCI_CLKIN
3 6 A16 PCI_AD31
4 5 1 C31 1
(23) PCI_PIRQE# PCI_PIRQE# L17 10P_0402_50V8J
8.2K_1206_8P4R_5% PCI_PIRQF# PCI_INTW# C30
(23) PCI_PIRQF# J17 PCI_INTX#
PCI_PIRQG# B16 10P_0402_50V8J JP35
PCI_PIRQH# PCI_INTY# 2 2
K17 PCI_INTZ# 1 NC NC 2
3 NC NC 4
(23) PCI_TRDY# PCI_TRDY# K14 9/20 Added
PCI_TRDY# PCI_CBE#0 Debug Port
5 CLK0 CLK1 6

LPC_DRQ#1 C6 D7 R329 1 2 22_0402_5%LPC_FRAME# LPC_FRAME# (14,27,28) PCI_AD31 7 8 PCI_AD15


LPC_DRQ#0 LPC_DRQ1#/GPIO19/FANRPM1 LPC_FRAME# PCI_AD30 A3<7> A1<7> PCI_AD14
LPC_DRQ#0 B6 LPC_DRQ0#/GPIO_50 LPC_PWRDWN#/GPIO_54/EXT_NMI# B3 PAD T6 9 A3<6> A1<6> 10
PCI_AD29 11 12 PCI_AD13
SERIRQ R54 PCI_AD28 A3<5> A1<5> PCI_AD12
D6 C7 1 2 33_0402_5% PLT_RST# (27,28) 13 14
(23,27,28) SERIRQ
(23,27,28) PM_CLKRUN#
PM_CLKRUN# D5
LPC_SERIRQ
LPC_CLKRUN/GPIO_42 LPC LPC_RESET# PCI_AD27
PCI_AD26
15
17
A3<4>
A3<3>
A3<2>
A1<4>
A1<3>
A1<2>
16
18
PCI_AD11
PCI_AD10
A4 R333 1 2 22_0402_5% LPC_AD0 LPC_AD0 (27,28) PCI_AD25 19 20 PCI_AD9
IDE_D0 LPC_AD0 R328 22_0402_5% LPC_AD1 PCI_AD24 A3<1> A1<1> PCI_AD8
AF10 IDE_DATA_P0 LPC_AD1 B4 1 2 LPC_AD1 (27,28) 21 A3<0> A1<0> 22
IDE_D1 AL9 C4 R335 1 2 22_0402_5% LPC_AD2 LPC_AD2 (27,28)
IDE_D2 IDE_DATA_P1 LPC_AD2 R311 22_0402_5% LPC_AD3 PCI_AD23 PCI_AD7
AK8 IDE_DATA_P2 LPC_AD3 A3 1 2 LPC_AD3 (27,28) 23 A2<7> A0<7> 24
IDE_D3 AK7 B5 CLK_PCI_LPC_R R59 1 2 22_0402_5% PCI_AD22 25 26 PCI_AD6
IDE_DATA_P3 LPC_CLK0 CLK_PCI_LPC (27,28) A2<6> A0<6>
IDE_D4 AK6 PCI_AD21 27 28 PCI_AD5
IDE_D5 IDE_DATA_P4 PCI_AD20 A2<5> A0<5> PCI_AD4
AJ6 IDE_DATA_P5 LPC_CLK1 C5 29 A2<4> A0<4> 30
IDE_D6 AL5 PCI_AD19 31 32 PCI_AD3
IDE_D7 IDE_DATA_P6 PCI_AD18 A2<3> A0<3> PCI_AD2
AL4 IDE_DATA_P7 33 A2<2> A0<2> 34
IDE_D8 AJ5 AG12 IDE_A0 IDE_A0 (21) PCI_AD17 35 36 PCI_AD1
B IDE_D9 IDE_DATA_P8 IDE_ADDR_P0 IDE_A1 PCI_AD16 A2<1> A0<1> PCI_AD0 B
AK5 IDE_DATA_P9 IDE_ADDR_P1 AE12 IDE_A1 (21) 37 A2<0> A0<0> 38
IDE_D10 AL6 AH12 IDE_A2 IDE_A2 (21)
IDE_D11 IDE_DATA_P10 IDE_ADDR_P2
AJ7 39
IDE_D12
IDE_D13
AJ8
AL8
IDE_DATA_P11
IDE_DATA_P12
IDE_DATA_P13
IDE IDE_CS1_P#
IDE_CS3_P#
AJ12
AK12
IDE_CS1#
IDE_CS3#
IDE_CS1# (21)
IDE_CS3# (21)
+3VS 40
41
GND
GND
GND
IDE_D14 AK9 AJ11 IDE_DACK# IDE_DACK# (21) 42
IDE_DATA_P14 IDE_DACK_P# GND

1
IDE_D15 AG10 43
IDE_D[15..0] IDE_DATA_P15 R29 GND
(21) IDE_D[15..0]
(21) IDE_DREQ IDE_DREQ AK11 AJ10 IDE_IOW# IDE_IOW# (21) 121_0402_1% S W-CONN AMP 2-767004-2 38P
IDE_IRQ IDE_DREQ_P IDE_IOW_P# @
(21) IDE_IRQ AH10 IDE_INTR_P
(21) IDE_IORDY IDE_IORDY AK10

2
IDE_IOR# IDE_RDY_P
(21) IDE_IOR# 1 2 AL10 IDE_IOR_P# IDE_COMP_3P3V AM4
R362 2 1 33_0402_5%AF12 AK4
R43 15K_0402_5% CABLE_DET_P/GPIO_63 IDE_COMP_GND

1
MCP67-MV_PBGA836 R51
121_0402_1%

9/21 Add 33ohm for IDE_IOR#

2
A A

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
MCP67 PCI/ LPC/ IDE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 13 of 42
5 4 3 2 1
5 4 3 2 1

PLACE SATA AC COUPLING


CAPS CLOSE TO MCP67 U23E
MCP67
PAR 5 OF 8
(21) SATA_STX_C_DRX_P0
SATA_STX_C_DRX_P0 0.01U_0402_16V7K 1 2 C512 SATA_STX_DRX_P0 AE4 SATA_A0_TX_P USB0_P U3 USB20_P0 USB20_P0 (26) USB PORT_1
SATA_STX_C_DRX_N0 0.01U_0402_16V7K 1 2 C511 SATA_STX_DRX_N0 AE5 U2 USB20_N0 USB20_N0 (26)
(21) SATA_STX_C_DRX_N0 SATA_A0_TX_N USB0_N
1 2 1 2
SATA_DTX_C_SRX_N0 AG5 R343 15K_0402_5% R346 15K_0402_5%
(21) SATA_DTX_C_SRX_N0 SATA_A0_RX_N
(21) SATA_DTX_C_SRX_P0
SATA_DTX_C_SRX_P0 AG6 SATA_A0_RX_P USB1_P U4 USB20_P1 USB20_P1 (26) USB PORT_1
D U5 USB20_N1 D
USB1_N USB20_N1 (26)
1 2 1 2
R342 15K_0402_5% R341 15K_0402_5%
USB2_P U6 USB20_P2 USB20_P2 (25) USB/B
AD1 U7 USB20_N2 USB20_N2 (25) Connector
SATA_A1_TX_P USB2_N
AD2 SATA_A1_TX_N 1 2 1 2
R84 15K_0402_5% R80 15K_0402_5%
AE2 SATA_A1_RX_N USB3_P V3 USB20_P3 USB20_P3 (25) USB/B
AE3 V2 USB20_N3 USB20_N3 (25) Connector
SATA_A1_RX_P USB3_N
1 2 1 2
R345 15K_0402_5% R348 15K_0402_5%

SATA2@
SATA USB USB4_P
USB4_N
W4
W3
USB20_P4
USB20_N4
USB20_P4 (20)
USB20_N4 (20)
USB CAMERA
SATA_STX_C_DRX_P1 0.01U_0402_16V7K 1 2 C514 SATA_STX_DRX_P1 AG4 1 2 1 2
(21) SATA_STX_C_DRX_P1 SATA_B0_TX_P
SATA_STX_C_DRX_N1 0.01U_0402_16V7K 1 2 C513 SATA_STX_DRX_N1 AG3 R347 15K_0402_5% R344 15K_0402_5%
(21) SATA_STX_C_DRX_N1 SATA_B0_TX_N
USB5_P W5 USB20_P5 CMOS@ CMOS@ USB20_P5 (30) BLUETOOTH
SATA_DTX_C_SRX_N1 SATA2@ AH3 W6 USB20_N5 USB20_N5 (30)
(21) SATA_DTX_C_SRX_N1 SATA_B0_RX_N USB5_N
SATA_DTX_C_SRX_P1 AH2 1 2 1 2
(21) SATA_DTX_C_SRX_P1 SATA_B0_RX_P R353 15K_0402_5% R357 15K_0402_5%
USB6_P W7 USB20_P6 BT@ BT@ USB20_P6 (25) MINI1
W8 USB20_N6 USB20_N6 (25)
+3VS USB6_N
1 2 1 2
AG7 R360 15K_0402_5% R358 15K_0402_5%
SATA_B1_TX_P
JUMPER AG8 SATA_B1_TX_N USB7_P Y2 USB20_P7 MINI1@ MINI1@ USB20_P7 (25) MINI2
R320 10K_0402_5% @ Y3 USB20_N7 USB20_N7 (25)
USB7_N
1 2 AF2 SATA_B1_RX_N 1 2 1 2

HDA_SDOUT

LPC_FRAME
R319 10K_0402_5% AF3 R352 15K_0402_5% R355 15K_0402_5%
SATA_B1_RX_P
1 2 HDA_SDOUT_ICH
USB8_P AA3 USB20_P8 MINI2@ MINI2@ USB20_P8 (26) NEW CARD
R44 10K_0402_5% @ FUNCTION AA2 USB20_N8 USB20_N8 (26)
USB8_N
1 2 1 2 1 2
C R41 10K_0402_5% R350 15K_0402_5% R356 15K_0402_5% C
1 2 LPC_FRAME# LPC_FRAME# (13,27,28) AL1 RESERVED/SATA_C0_TX_P USB9_P AA5 USB20_P9 EXPRESS@ EXPRESS@ USB20_P9 NON-USE
AL2 AA4 USB20_N9 USB20_N9
RESERVED/SATA_C0_TX_N USB9_N
1 2 1 2
AK3 R351 15K_0402_5% R354 15K_0402_5%
RESERVED/SATA_C0_RX_N @ @
"0" "0" LPC BIOS* AL3 RESERVED/SATA_C0_RX_P RESERVED/USB10_P AA7
RESERVED/USB10_N AA6

"0" "1" PCI BIOS


RESERVED/USB11_P AB3
+3VS AB2 +3V
RESERVED/USB11_N
"1" "0" SPI BIOS AJ1 RESERVED/SATA_C1_TX_P
AJ2 1 2 USB_OC#4
RESERVED/SATA_C1_TX_N
1

AC3 R86 10K_0402_5%


R35 RESERVED USB_OC#3
"1" "1" RESERVED AK1 RESERVED/SATA_C1_RX_N RESERVED AC4 1 2
AK2 R87 10K_0402_5%
RESERVED/SATA_C1_RX_P
10K_0402_5% 1 2 HDA_RST_ICH#
*DEFAULT T1 1 2 R316 10K_0402_5%
2

USB_RBIAS_GND R338
1 2 AJ4 1.1K_0402_1% +3V
SATA_LED# R108 2.49K_0402_1% SATA_TERMP HDA_SYNC_ICH
1 2
T2 R313 10K_0402_5%
USB_OC0#/GPIO_25 USB_OC#0 (26)
USB_OC1#/GPIO_26 T3 USB_OC#1 (25)
(27,28) SATA_LED# SATA_LED# D4 T4 1 1
SATA_LED#/GPIO_57 USB_OC2#/GPIO_27 CP_PE# (11,26)
T5 C57 C63
USB_OC3#/GPIO_28/MGPIO_1 USB_OC#3
T6 0.1U_0402_16V4Z 0.1U_0402_16V4Z
USB_OC4#/GPIO_29/MGPIO_3 USB_OC#4
+3VS +3VS 2 2

+3.3V_USB_DUAL1 Y8
+3.3V_USB_DUAL2 Y9
B W13 B
U36 +1.2V_PLL_SP_VDD +1.2V_PLL_SP_VDD
+1.2VS V13 +1.2V_PLL_SP_SS
HDA_BITCLK_ICH_R 1 7
CLKIN VDD
1

1 D2 HDA_BITCLK_ICH_R HDA_BITCLK_ICH 1 2
HDA_BITCLK HDA_BITCLK_MDC (30)
R459 2 6 HDA_BITCLK_ICH R13 33_0402_5% R314
10K_0402_5%
@ 8
NC

NC
CLKOUT

SSON 5
1
C640
+3.3V_PLL
P13
+3.3V_PLL_SP_SS

+3.3V_PLL_LEG
HDA
0.1U_0402_16V4Z 2 C140
2

3 4 0.1U_0402_16V4Z B1 HDA_SDOUT_ICH 1 2 HDA_BITCLK_ICH


SS GND 2 HDA_SDATA_OUT/GPIO_45 HDA_SDOUT_MDC (30)
22_0402_5% R318 HDA_SYNC_ICH
1

ASM3P623S00CF-08TR_TSSOP8 HDA_RST_ICH#
R460 @ B2 HDA_SDIN0 HDA_SDIN0 (32) HDA_SDOUT_ICH
HDA_SDATA_IN0/GPIO_22 HDA_SDIN1 C23 C17
10K_0402_5% HDA_SDATA_IN1/GPIO_23/MGPIO_0 A2 HDA_SDIN1 (30)
@ D1 HDA_SDIN2 10P_0402_50V8J 10P_0402_50V8J
HDA_SDATA_IN2/GPIO_24/MGPIO_2
1 @ 1 @ 1 C22 1
2

C2 HDA_RST_ICH# 1 2
HDA_RESET# HDA_RST_MDC# (30)
22_0402_5% R315
2 2 2 2 C20
HDA_BITCLK_ICH_R 1 2 HDA_BITCLK_ICH C1 HDA_SYNC_ICH 1 2 HDA_SYNC_MDC (30) 10P_0402_50V8J 10P_0402_50V8J
R461 0_0402_5% HDA_SYNC/GPIO_44 22_0402_5% R312

HDA_DOCK_EN#/GPIO_51 D3
HDA_DOCK_RST#/GPIO_46 C3
HDA_BITCLK_ICH 1 2 HDA_BITCLK_AUDIO (32)
33_0402_5% R25
HDA_SYNC_ICH 1 2 HDA_SYNC_AUDIO (32)
+1.2VS +1.2V_PLL_SP_VDD +3VS +3.3V_PLL MCP67-MV_PBGA836 22_0402_5% R23
HDA_RST_ICH# 1 2 HDA_RST_AUDIO# (32)
22_0402_5% R26
A C145 C149 HDA_SDOUT_ICH 1 2 A
HDA_SDOUT_AUDIO (32)
L10 1 2 L14 1 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 22_0402_5% R27
MBK1608121YZF_0603 MBK1608121YZF_0603
1 1 1 1 1 1
C54
10U_0805_10V4Z
2 2 C50 2 2 2 2 Security Classification Compal Secret Data
0.1U_0402_16V4Z Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
C143 C153 MCP67 SATA/ USB/ HDAUDIO
0.1U_0402_16V4Z 0.1U_0402_16V4Z THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 14 of 42
5 4 3 2 1
5 4 3 2 1

+3V

1 2 EC_LID_OUT# CRT_DET 2 1 +3V


R469 10K_0402_5% @ R445 @ 100K_0402_5%
+3V
1 2 CRT_DET +3VS
R470 10K_0402_5% @
1 2 LID#
R78 100K_0402_5%
1 2 LLB#
R53 10K_0402_5% @ U23F
MCP67 MCP_SPKR 1 2
D R101 10K_0402_5% D
PAR 6 OF 8
IDE_HRESET# P6 R3 PM_SLP_S3# PM_SLP_S3# (27,28) 1 2
(21) IDE_HRESET# GPIO_1/PWRDN_OK/SPI_CS1 SLP_S3#
@ R92 1 2 0_0402_5% N11 P3 SLP_RMGT# SLP_RMGT# (12,22) R104 10K_0402_5% @
(27,28) EC_SWI# GPIO_2/NMI/PS2_CLK0 SLP_RMGT#
D24 R97 1 2 0_0402_5% @ R11 R4 PM_SLP_S5# PM_SLP_S5# (27,28)
(27,28) EC_SMI# GPIO_3/SMI#/PS2_DATA0 SLP_S5#
RB751V_SOD323 M9
ACIN_R GPIO_4/SCI/INTR/PS2_CLK1
(18,27,28,37) ACIN 2 1 2 1 M10 GPIO_5/INIT#/PS2_DATA1
R542 20K_0402_1% H5
@ MCP_VID0/GPIO_13
MCP_VID1/GPIO_14 H6

1
EC_LID_OUT# 1 2 RI# M4 H7
(27,28) EC_LID_OUT# GPIO_12/SUS_STAT# MCP_VID2/GPIO_15
R464 0_0402_5% @ R283
470K_0402_5%
+RTCVCC @
K4 MCP_SPKR
MSIC MCP_SPKR (32)

2
SPKR Q10
R340 MP Modify 2007/04/12 2N7002_SOT23
1M_0402_5%
1

EC_GA20 SMBCLK1 M_SMBCLK MEM_SMBCLK

S
(27,28) EC_GA20 K7 A20GATE/GPIO_55 SMB_CLK0 E3 SMBCLK1 (25,26) 1 3 MEM_SMBCLK (8,9)
EC_KBRST# K6 G3 SMBDATA1 SMBDATA1 (25,26)
(27,28) EC_KBRST# KBRDRSTIN#/GPIO_56 SMB_DATA0
R91 1 2 0_0402_5% SIO_PME# M6 E2 M_SMBCLK
(27,28) EC_SCI# SIO_PME#/GPIO_31 SMB_CLK1/MSMB_CLK
R96 1 2 0_0402_5% EXT_SMI# P4 F2 M_SMBDATA

G
(27,28) EC_SMI#

2
RI# EXT_SMI#/GPIO_32 SMB_DATA1/MSMB_DATA SMB_ALERT#
P8 F3 +3VS
2

SM_INTRUDER# RI#/GPIO33 SMB_ALERT#/GPIO_64


L3 INTRUDER#

2
G
1

R93 R463 0_0402_5% K5 M_SMBDATA 1 3 MEM_SMBDATA


THERM#/GPIO_59 EC_THERM# (6,27,28) MEM_SMBDATA (8,9)
49.9K_0402_1% CRT_DET 1 2 LID# P5

S
(19) CRT_DET LID#
C29 LLB# N10
1U_0603_10V4Z LLB# 2N7002_SOT23
1 2 AC14 CPU_SIC (6) Q9
2

THERM_SIC/GPIO_48
C PVT Modify 2007/03/12 THERM_SID0/GPIO_49 AB14
AD12
CPU_SID (6) C
PBTN_OUT# THERM_SID1/GPIO_47/PWR_LED#
(27,28) PBTN_OUT# R10 PWRBTN#
Close To RAM Door +3V 2 1 RSTBTN# P9 RSTBTN#
R90 10K_0402_5% 1 2 SMBCLK1
+3V
2 1 M5 F6 1 2 R65 2.7K_0402_5%
J1 @ JOPEN RTC_RST# FANRPM0/GPIO_60 R438 15K_0402_5% SMBDATA1
FANCTL0/GPIO_61 F5 1 2
EC_RSMRST# L4 F4 R70 2.7K_0402_5%
(27,28) EC_RSMRST# PWRGD_SB FANCTL1/GPIO_62
T10 PWRGD 1 2 SMB_ALERT#
C60 (6,18,27,28) MCP_PWRGD MEM_VLD M8 R34 2.7K_0402_5%
1U_0603_10V4Z (31,40) MEM_VLD HT_VLD MEM_VLD
P7 MCP_VLD/HT_VLD
1 2 (11,31) HT_VLD M3 N3 1 2 M_SMBCLK
(41) VGATE CPU_VLD MCPVDD_EN/HTVDD_EN VLDT_EN (34) +3VS
M2 R73 2.7K_0402_5%
CPUVDD_EN VR_ON (41)
D29 1 2 M_SMBDATA
U9 RB751V_SOD323 R60 2.7K_0402_5%
JTAG_TDI ACIN_L
T8 JTAG_TDO 2 1 ACIN (18,27,28,37)
T7 JTAG_TMS SPI_CS0/GPIO_10 K2
2 1 U8 JTAG_TRST# SPI_CLK/GPIO_11 K3 1 2
10K_0402_5%2 1 R81 T9 M7 R74 10K_0402_5% @
10K_0402_5% R95 JTAG_TCK SPI_DI/GPIO_8 ACIN_L
SPI_DO/GPIO_9 J2 1 2 +3V 1 2
R56 10K_0402_5% @ R543 470K_0402_5%

SUS_CLK/GPIO_34 P2 1 2
XTALIN R339 10K_0402_5% @
XTALOUT
H4
H3
XTALIN MP Modify 2007/04/12
X1 XTALOUT
1 2
1 1 BUF_SIO_CLK J3
25MHZ_20P
C34 C35 C503 1 C16
B 18P_0402_50V8J 10P_0402_50V8J B
27P_0402_50V8J 27P_0402_50V8J
2 2 XTALIN_RTC @
2 1 H2 XTALIN_RTC
@ H1 P11 R540 2.2K_0402_5%
XTALOUT_RTC TEST_MODE_EN 2
+3VS 1 2 MEM_SMBCLK
2
10M_0402_5%

X2 R541 2.2K_0402_5%
2 NC IN 1 PKG_TEST P10 1 2 MEM_SMBDATA
9/25 Added for EMI
R334

3 NC OUT 4
MCP67-MV_PBGA836
1

1
32.768KHZ_12.5P_MC-306
2 1 XTAOUT_RTC R71 R100 PVT Modify 2007/03/23
0_0402_5% 1K_0402_1%
18P_0402_50V8J
C504

2
A A

Security Classification Compal Secret Data


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
MCP67 MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 15 of 42
5 4 3 2 1
5 4 3 2 1

C152 C527 C73 C100 C114


10U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +1.2VS

1 1 1 1 1 1 1 1 1 1

U23G 2 2 2 2 2 2 2 2 2 2
D D
MCP67
PART 7 OF 8 C525 C74 C108 C109 C120
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
V15 AA22 C526 C147 C125 C132 C131 C134
+1.2V_RBB1 +1.2V1 150U_D2_6.3VM 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
V16 +1.2V_RBB2 +1.2V10 V19
W16 W20 1
+3V +3VS W15
+1.2V_RBB3
+1.2V_RBB4 POWER +1.2V11
+1.2V12
+1.2V13
Y20
Y19 +
1 1 1 1 1 1 1 1 1 1 1

+1.2V14 V17
C107 C48 C39 AB21
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K +1.2V15 2 2 2 2 2 2 2 2 2 2 2 2
AJ9 +3.3V1 +1.2V16 AA23
AG9 +3.3V2 +1.2V17 Y30
1 1 1 1 1 1 F11 U17 C151 C159 C130 C135 C139 C144
+3.3V3 +1.2V18 22U_0805_6.3V6M 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
H11 +3.3V4 +1.2V19 U18
1

+1.2V2 Y31
R77 W17
2 2 2 2 2 2 +1.2V20
0_0603_5% +1.2V21 Y18
C102 C110 C47 L6 U16 +1.2V_HT
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3.3V_DUAL1 +1.2V22
L8 AA24
2

+3.3V_DUAL2 +1.2V23
+1.2V24 V18

1
C45 AA25
0.1U_0402_16V4Z +3.3V_DUAL1 +1.2V25 R102 +1.2VS +1.2VS
+1.2V26 AA26
+RTCVCC N2 AB22 C106 0_0603_5%
+3.3V_VBAT +1.2V27 0.1U_0402_16V4Z
1 1 +1.2V28 W18
1 AB23 1 C529

2
C506 +1.2V29 +1.2V_HT1 150U_D2_6.3VM
+1.2V3 AA27
0.1U_0402_16V4Z AA28 +@
2 2 +1.2V4
+1.2V5 AA29
C41 2
AD9 GND +1.2V6 W19 1 1 C67 C121 C124
2
0.1U_0402_16V4Z AH6 AA30 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C GND +1.2V7 C
AE32 GND +1.2V8 AA31
Y32 V20 +1.2VS
RTC Battery GND +1.2V9 1 1 1

1
2 2
AD8 GND
M32 L17
GND
AE18 Y15 KC FBM-L11-201209-221LMAT_0805
- BATT1
+ +RTCBATT AB25
AB27
GND
GND
GND
+1.2V_HT1
+1.2V_HT2
+1.2V_HT3
Y17
Y16
2 2
C112
2

U15 0.1U_0402_16V4Z

2
GND

1
2 1 +RTCBATT AE11 V23 +1.2V_PED
GND +1.2V_PED1 C117 C128 C156 R110
Update Footprint V27 GND +1.2V_PED2 W25
R27 W24 +1.2V_PEA 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z C189 0_0805_5%
GND +1.2V_PED3 10U_0805_10V4Z
N27 GND +1.2V_PED4 V22
ML1220T13RE G27 W26 1 1 1 1 1 1 1 1

2
GND +1.2V_PED5
1

45@ Y14 GND


F15 GND +1.2V_PEA1 Y22
R539 V29 Y23
1K_0402_1% GND +1.2V_PEA2 2 2 2 2 2 2 2 2
AC12 GND +1.2V_PEA3 Y27
AB19 Y29 C123 C126 C157 C162
2

GND +1.2V_PEA4 0.1U_0402_16V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M 10U_0805_10V4Z


PVT Modify 2007/03/22 AM9
AB12
GND +1.2V_PEA5 Y25
W22
GND +1.2V_PEA6
AM8 GND +1.2V_PEA7 W23
1

AF8 Y24 +1.2V_SP_D


D22 GND +1.2V_PEA8 C68 C111 C71 C119
AH4 GND
E27 GND +1.2V_SP_D1 AE8 1 1 1 1 1 1 1 1
BAS40-04_SOT23-3 AM31 AE7 0.01U_0402_16V7K 10U_0805_10V4Z +1.2VS 0.1U_0402_16V4Z 10U_0805_10V4Z
+RTCVCC GND +1.2V_SP_D2
F22 GND +1.2V_SP_D3 AE9
AF4 AE6
3

GND +1.2V_SP_D4 2 2 2 2 2 2 2 2
AM32 GND
AG11 AB11 C62 C116 C72 C118
+CHGRTC GND +1.2V_SP_A1
L15 AB10 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
B GND +1.2V_SP_A2 B
1 1 AD27 GND +1.2V_SP_A3 AD10
P22 GND +1.2V_SP_A4 AC10
C519 C520 AD11 AE10 +1.2V_SP_A L12 1 2 MBK2012121YZF_0805
4.7U_0805_10V4Z 0.1U_0402_16V4Z GND +1.2V_SP_A5 C75 C518
V11 GND
2 2
L23 GND +1.2V_DUAL1 N16 1 1 1 1
P15 N17 0.1U_0402_16V4Z 4.7U_0805_10V4Z
GND +1.2V_DUAL2

2 2 2 2
MCP67-MV POWER STATES MCP67-MV_PBGA836 C64 C516
Power Signal S0 S1 S3 S4/S5 G3 0.1U_0402_16V4Z 4.7U_0805_10V4Z

ON ON OFF OFF OFF +1.2VALW

ON ON OFF OFF OFF


ON ON OFF OFF OFF C59 C56
0.1U_0402_16V4Z
ON ON OFF OFF OFF 0.1U_0402_16V4Z
1 1
ON ON OFF OFF OFF
ON ON OFF OFF OFF 2 2
ON ON OFF OFF OFF
ON ON OFF OFF OFF
ON ON OFF OFF OFF
A ON ON OFF OFF OFF A

ON ON OFF OFF OFF


ON ON OFF OFF OFF
ON ON OFF OFF OFF Security Classification Compal Secret Data
ON ON OFF OFF OFF Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
MCP67 POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ICW50 / ICY70 LA-3581P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 20, 2007 Sheet 16 of 42
5 4 3 2 1
5 4 3 2 1

U23H
MCP67
PAR 8 OF 8
AB9 WUSB_VREF WUSB_PCLK AC7
AC6 WUSB_CCA_STATUS WUSB_DATA_EN AB8
D AC8 V9 D
WUSB_SERIAL_DATA WUSB_DATA7
AA8 WUSB_PHY_RESET* WUSB_DATA6 W11
AD3 WUSB_TX_EN WUSB_DATA5 W10
AD4 WUSB_RX_EN WUSB_DATA4 W9
AA9 WUSB_PHY_ACTIVE WUSB_DATA3 Y11
AC5 WUSB_STOPC WUSB_DATA2 Y10
AC9 WUSB_VDD WUSB_DATA1 AA11
WUSB_DATA0 AA10
L11 GND
V8 GND GND R18
H13 H9
N6
AA1
GND
GND
GND
GROUND GND
GND
GND
R17
A1
AD13 GND GND D9
K23 GND GND AG26
AM16 GND GND G4
AH1 GND GND AB6
U13 GND GND J25
R6 GND GND R25
R8 GND GND T16
M1 GND GND T15
N1 GND GND J29
U1 GND GND W14
J1 GND GND AD6
J4 GND GND AB24
J6 GND GND AM13
Y13 GND GND R16
AE1 GND GND V6
Y6 GND GND A13
A5 GND GND N32
C A12 AM25 C
GND GND
N8 GND GND F9
E6 GND GND N9
AC11 GND GND AL31
H15 GND GND G25
T17 GND GND AB18
J21 GND GND AH32
D18 GND GND D13
A20 GND GND N25
N4 GND GND A25
G6 GND GND R9
AG22 GND GND R14
P16 GND GND AF27
T19 GND GND AH8
AE24 GND GND A32
AJ26 GND GND P14
AJ24 GND GND E29
U32 GND GND E32
T20 GND GND V10
AM24 GND GND J23
AF29 GND GND N14
AJ13 GND GND AB29
AA32 GND GND E4
AG13 GND GND AE13
AE15 GND GND L27
F13 GND GND J27
AF6 GND GND A9
AB4 GND GND J32
AG15 GND GND AE20
E25 GND GND AJ22
B AM17 AG18 B
GND GND
R15 GND GND AG20
A17 GND GND V14
AG24 GND GND F18
N20 GND GND F20
N24 GND GND D20
AM1 GND GND E1
AM21 GND GND V4
A21 GND GND J8
V25 GND GND F7
AJ3 GND GND T18
L25 GND GND J24
P17 GND GND A31
H18 GND GND Y1
L24 GND GND T13
AM5 GND GND D22
U14 GND GND Y4
AC16 GND GND P18
U10 GND GND AJ18
N29 GND GND AE22
AM2 GND GND R24
AM3 GND GND N19
GND T14

MCP67-MV_PBGA836

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCP67 GROUND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICW50 / ICY70 LA-3581P
Date: Friday, April 20, 2007 Sheet 17 of 42
5 4 3 2 1
5 4 3 2 1

1 2 MCP_PWRGD (6,15,27,28)
R125
0_0402_5%
PCIE_MTX_C_GRX_N[0..15] 2 VGA@
(11) PCIE_MTX_C_GRX_N[0..15]
C182
PCIE_MTX_C_GRX_P[0..15] 0.1U_0402_16V4Z
(11) PCIE_MTX_C_GRX_P[0..15]
VGA@
PCIE_GTX_C_MRX_N[0..15] 1
(11) PCIE_GTX_C_MRX_N[0..15]
D PCIE_GTX_C_MRX_P[0..15] D
(11) PCIE_GTX_C_MRX_P[0..15]

1 2 VGA_ON (27)
L18 R122
KC FBM-L11-201209-221LMAT_0805 JP19A 0_0402_5% @ JP19B
VGA@
B+ 1 2 1 PWR_SRC 2 +1.8VS PCIE_GTX_C_MRX_N1 109 110
VGA@ 1V8RUN PCIE_GTX_C_MRX_P1 PEX_RX1# GND PCIE_MTX_C_GRX_N1
3 PWR_SRC 1V8RUN 4 111 PEX_RX1 PEX_TX1# 112
1 2 5 PWR_SRC 6 113 114 PCIE_MTX_C_GRX_P1
1V8RUN PCIE_GTX_C_MRX_N0 GND PEX_TX1
7 PWR_SRC 1V8RUN 8 115 PEX_RX0# GND 116
9/25 Added for EMI 9 PWR_SRC 10 PCIE_GTX_C_MRX_P0 117 118 PCIE_MTX_C_GRX_N0
1V8RUN PEX_RX0 PEX_TX0# PCIE_MTX_C_GRX_P0
11 PWR_SRC 1V8RUN 12 119 GND PEX_TX0 120
13 PWR_SRC 14 CLK_PCIE_VGA# 121 122 PE_PRSNTX16#
1V8RUN (11) CLK_PCIE_VGA# PEX_REFCLK# PRSNT1# PE_PRSNTX16# (11)
L21 15 16 CLK_PCIE_VGA 123 124 VGA_TV_CRMA
(11) CLK_PCIE_VGA VGA_TV_CRMA (19)
KC FBM-L11-201209-221LMAT_0805 17 PWR_SRC RUNPWROK
18 +5VS 125
PEX_REFCLK TV_C/HDTV_Pr
126
GND 5VRUN CLK_REQ# GND VGA_TV_LUMA
19 GND GND 20 (11,26) PCIE_RST# 127 PEX_RST# TV_Y/HDTV_Y 128 VGA_TV_LUMA (19)
21 GND GND 22 129 RSVD GND 130
23 GND 24 131 132 VGA_TV_COMPS
GND RSVD TV_CVBS/HDTV_Pb VGA_TV_COMPS (19)
D_EC_SMB_DA1 133 134
D_EC_SMB_CK1 SMB_DAT GND VGA_CRT_R
135 SMB_CLK VGA_RED 136 VGA_CRT_R (19)
(27,28) MXM_THERM# 1 2 MXM_THERM_R 137 138
VGA_CRT_HSYNC THERM# GND VGA_CRT_G
(19) VGA_CRT_HSYNC 139 VGA_HSYNC VGA_GRN 140 VGA_CRT_G (19)
R515 (19) VGA_CRT_VSYNC VGA_CRT_VSYNC 141 142
@ 0_0402_5% VGA_DDC_CLK VGA_VSYNC GND VGA_CRT_B
(19) VGA_DDC_CLK 143 DDCA_CLK VGA_BLU 144 VGA_CRT_B (19)
PCIE_GTX_C_MRX_N15 25 26 (19) VGA_DDC_DATA VGA_DDC_DATA 145 146
PCIE_GTX_C_MRX_P15 PEX_RX15# PRSNT2# PCIE_MTX_C_GRX_N15 DDCA_DAT GND VGA_TZCLK-
27 PEX_RX15 PEX_TX15# 28 147 IGP_UCLK# LVDS_UCLK# 148 VGA_TZCLK- (20)
29 30 PCIE_MTX_C_GRX_P15 149 150 VGA_TZCLK+ VGA_TZCLK+ (20)
C PCIE_GTX_C_MRX_N14 GND PEX_TX15 IGP_UCLK LVDS_UCLK C
31 PEX_RX14# GND 32 151 GND GND 152
PCIE_GTX_C_MRX_P14 33 34 PCIE_MTX_C_GRX_N14 153 154
PEX_RX14 PEX_TX14# PCIE_MTX_C_GRX_P14 RSVD LVDS_UTX3#
35 GND PEX_TX14 36 155 RSVD LVDS_UTX3 156
PCIE_GTX_C_MRX_N13 37 38 1 2 157 158
PCIE_GTX_C_MRX_P13 PEX_RX13# GND PCIE_MTX_C_GRX_N13 (15,27,28,37) ACIN R516 RSVD GND VGA_TZOUT2-
39 PEX_RX13 PEX_TX13# 40 159 IGP_UTX2# LVDS_UTX2# 160 VGA_TZOUT2- (20)
41 42 PCIE_MTX_C_GRX_P13 0_0402_5% 161 162 VGA_TZOUT2+ VGA_TZOUT2+ (20)
PCIE_GTX_C_MRX_N12 GND PEX_TX13 @ IGP_UTX2 LVDS_UTX2
43 PEX_RX12# GND 44 163 GND GND 164
PCIE_GTX_C_MRX_P12 45 46 PCIE_MTX_C_GRX_N12 165 166 VGA_TZOUT1- VGA_TZOUT1- (20)
PEX_RX12 PEX_TX12# PCIE_MTX_C_GRX_P12 IGP_UTX1# LVDS_UTX1# VGA_TZOUT1+
47 GND PEX_TX12 48 167 IGP_UTX1 LVDS_UTX1 168 VGA_TZOUT1+ (20)
PCIE_GTX_C_MRX_N11 49 50 169 170
PCIE_GTX_C_MRX_P11 PEX_RX11# GND PCIE_MTX_C_GRX_N11 GND GND VGA_TZOUT0-
51 PEX_RX11 PEX_TX11# 52 171 IGP_UTX0# LVDS_UTX0# 172 VGA_TZOUT0- (20)
53 54 PCIE_MTX_C_GRX_P11 173 174 VGA_TZOUT0+ VGA_TZOUT0+ (20)
PCIE_GTX_C_MRX_N10 GND PEX_TX11 IGP_UTX0 LVDS_UTX0
55 PEX_RX10# GND 56 175 GND GND 176
PCIE_GTX_C_MRX_P10 57 58 PCIE_MTX_C_GRX_N10 177 178 VGA_TXCLK- VGA_TXCLK- (20)
PEX_RX10 PEX_TX10# PCIE_MTX_C_GRX_P10 IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# VGA_TXCLK+
59 GND PEX_TX10 60 179 IGP_LCLK/DVI_B_CLK LVDS_LCLK 180 VGA_TXCLK+ (20)
PCIE_GTX_C_MRX_N9 61 62 181 182
PCIE_GTX_C_MRX_P9 PEX_RX9# GND PCIE_MTX_C_GRX_N9 DVI_B_HPD/GND GND
63 PEX_RX9 PEX_TX9# 64 183 RSVD LVDS_LTX3# 184
65 66 PCIE_MTX_C_GRX_P9 185 186
PCIE_GTX_C_MRX_N8 GND PEX_TX9 RSVD LVDS_LTX3
67 PEX_RX8# GND 68 187 GND GND 188
PCIE_GTX_C_MRX_P8 69 70 PCIE_MTX_C_GRX_N8 189 190 VGA_TXOUT2- VGA_TXOUT2- (20)
PEX_RX8 PEX_TX8# PCIE_MTX_C_GRX_P8 IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# VGA_TXOUT2+
71 GND PEX_TX8 72 191 IGP_LTX2/DVI_B_TX2 LVDS_LTX2 192 VGA_TXOUT2+ (20)
PCIE_GTX_C_MRX_N7 73 74 193 194
PCIE_GTX_C_MRX_P7 PEX_RX7# GND PCIE_MTX_C_GRX_N7 GND GND VGA_TXOUT1-
75 PEX_RX7 PEX_TX7# 76 195 IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# 196 VGA_TXOUT1- (20)
77 78 PCIE_MTX_C_GRX_P7 197 198 VGA_TXOUT1+ VGA_TXOUT1+ (20)
PCIE_GTX_C_MRX_N6 GND PEX_TX7 IGP_LTX1/DVI_B_TX1 LVDS_LTX1
79 PEX_RX6# GND 80 199 GND GND 200
PCIE_GTX_C_MRX_P6 81 82 PCIE_MTX_C_GRX_N6 201 202 VGA_TXOUT0- VGA_TXOUT0- (20)
PEX_RX6 PEX_TX6# PCIE_MTX_C_GRX_P6 IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# VGA_TXOUT0+
83 GND PEX_TX6 84 203 IGP_LTX0/DVI_B_TX0 LVDS_LTX0 204 VGA_TXOUT0+ (20)
PCIE_GTX_C_MRX_N5 85 86 (20) DVI_DET DVI_DET 205 206
PCIE_GTX_C_MRX_P5 PEX_RX5# GND PCIE_MTX_C_GRX_N5 VGA_DVI_TXC- DVI_A_HPD GND I2CC_SDA
87 PEX_RX5 PEX_TX5# 88 (20) VGA_DVI_TXC- 207 DVI_A_CLK# DDCC_DAT 208 I2CC_SDA (20)
B PCIE_MTX_C_GRX_P5 VGA_DVI_TXC+ I2CC_SCL B
89 GND PEX_TX5 90 (20) VGA_DVI_TXC+ 209 DVI_A_CLK DDCC_CLK 210 I2CC_SCL (20)
PCIE_GTX_C_MRX_N4 91 92 211 212 ENVDD
PEX_RX4# GND GND LVDS_PPEN ENVDD (20)
PCIE_GTX_C_MRX_P4 93 94 PCIE_MTX_C_GRX_N4 (20) VGA_DVI_TXD2- VGA_DVI_TXD2- 213 214
PEX_RX4 PEX_TX4# PCIE_MTX_C_GRX_P4 VGA_DVI_TXD2+ DVI_A_TX2# LVDS_BL_BRGHT ENBKL
95 GND PEX_TX4 96 (20) VGA_DVI_TXD2+ 215 DVI_A_TX2 LVDS_BLEN 216 ENBKL (12,27,28)
PCIE_GTX_C_MRX_N3 97 98 217 218 VGA_DVI_SDATA VGA_DVI_SDATA (20)
PCIE_GTX_C_MRX_P3 PEX_RX3# GND PCIE_MTX_C_GRX_N3 VGA_DVI_TXD1- GND DDCB_DAT VGA_DVI_SCLK
99 PEX_RX3 PEX_TX3# 100 (20) VGA_DVI_TXD1- 219 DVI_A_TX1# DDCB_CLK 220 VGA_DVI_SCLK (20)
101 102 PCIE_MTX_C_GRX_P3 (20) VGA_DVI_TXD1+ VGA_DVI_TXD1+ 221 222 +2.5VS
PCIE_GTX_C_MRX_N2 GND PEX_TX3 DVI_A_TX1 2V5RUN
103 PEX_RX2# GND 104 223 GND GND 224
PCIE_GTX_C_MRX_P2 105 106 PCIE_MTX_C_GRX_N2 (20) VGA_DVI_TXD0- VGA_DVI_TXD0- 225 226 +3VS
PEX_RX2 PEX_TX2# PCIE_MTX_C_GRX_P2 VGA_DVI_TXD0+ DVI_A_TX0# 3V3RUN
107 GND PEX_TX2 108 (20) VGA_DVI_TXD0+ 227 DVI_A_TX0 3V3RUN 228
229 GND 3V3RUN 230

ACES_88990-2D08
ACES_88990-2D08 +3VS
VGA@
VGA@

2
B+ B+ B+ +1.8VS +3VS +2.5VS +5VS

G
1 3 D_EC_SMB_DA1
(27,28,29,37) EC_SMB_DA1
C652

S
10U_1206_25V6M 1 1 1 1 1 1 Q54
1

@ C150 C142 C522 C524 C523 C146 VGA@ 2N7002_SOT23


C206

2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

G
0.1U_0603_25V7K
2

C651 VGA@ VGA@ 2 2 VGA@ VGA@ 2 2 VGA@ 2 VGA@ 2 VGA@


10U_1206_25V6M 1 3 D_EC_SMB_CK1
(27,28,29,37) EC_SMB_CK1
VGA@

S
A A
VGA@ Q55
PVT Modify 2007/03/22
2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICW50 / ICY70 LA-3581P
Date: Friday, April 20, 2007 Sheet 18 of 42
5 4 3 2 1
A B C D E

CRT Connector D15 D14 D13


+5VS
W=40mils
+R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D1 F1 W=40mils

1
2 1 1 2

RB411D_SOT23 1.1A_6VDC_FUSE
1
C3

3
0.1U_0402_16V4Z
2
1
+3VS 1
Place closed to chipset

R14 1 2 VGA@ 0_0402_5% CRT_R 1 2 CRT_R_1 JP14


(18) VGA_CRT_R
1 2 L42 FCM2012C-800_0805 6
(12) UMA_CRT_R
R10 UMA@ 0_0402_5% 11
R9 1 2 VGA@ 0_0402_5% CRT_G 1 2 CRT_G_1 1
(18) VGA_CRT_G
1 2 L41 FCM2012C-800_0805 7
(12) UMA_CRT_G
R8 UMA@ 0_0402_5% 12
R6 1 2 VGA@ 0_0402_5% CRT_B 1 2 CRT_B_1 2
(18) VGA_CRT_B
1 2 C499 C494 L40 FCM2012C-800_0805 8
(12) UMA_CRT_B

1
R5 UMA@ 0_0402_5% 10P_0402_50V8J 10P_0402_50V8J 13

1
R304 R303 1 1 1 3
R302 1 1 1 9
14
150_0402_1% C498 C496 C495 4

2
2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10 16

2
150_0402_1% 2 2 2
15 17
150_0402_1% 1 5
C497
10P_0402_50V8J C2 SUYIN_070549FR015S208CR
+CRT_VCC CRT_HSYNC_2 470P_0402_50V7K
1 2 CRT_DET (15)
L39 FCM1608C-121T_0603 2
1 2 2 1 DSUB_12
C492 0.1U_0402_16V4Z R297 10K_0402_5% 1 2 CRT_VSYNC_2
L38 FCM1608C-121T_0603 1

1
U22
1 1 C4

OE#
1 2 CRT_HSYNC 2 4 CRT_HSYNC_1 C491 470P_0402_50V7K
(18) VGA_CRT_HSYNC A Y 2
R301 VGA@ 0_0402_5% C493

G
1 2 10P_0402_50V8K 10P_0402_50V8K DSUB_15
2 (12) UMA_CRT_HSYNC 2 2 2
R300 UMA@ 39_0402_5% SN74AHCT1G125DCKR_SC70-5

3
+CRT_VCC 1

Place closed to chipset C1


1 2 470P_0402_50V7K
C490 0.1U_0402_16V4Z 2

1
U21

OE#
1 2 CRT_VSYNC 2 4 CRT_VSYNC_1
(18) VGA_CRT_VSYNC A Y
R298 VGA@ 0_0402_5%

G
1 2 +3VS
(12) UMA_CRT_VSYNC +CRT_VCC
R299 UMA@ 39_0402_5% SN74AHCT1G125DCKR_SC70-5

1
Place closed to chipset
R11
+3VS 4.7K_0402_5%

1
UMA@

2
TV-OUT Conn. D6 D9 D10
R7
4.7K_0402_5% R1
1 2 R12
VGA@ 0_0402_5% VGA_DDC_DATA (18)

2
@ @ @

G
DAN217_SC59 DAN217_SC59 DAN217_SC59 4.7K_0402_5% R13 UMA@ 0_0402_5%
DSUB_12 1 3 2 1

1
UMA_CRT_DATA (12)

S
Q2

2
2N7002_SOT23

G
DSUB_15 1 3 2 1
R2 UMA_CRT_CLK (12)
Place closed to chipset

S
2

3
Q1 UMA@ 0_0402_5%
3 2N7002_SOT23 3
+3VS
1 2 R3 VGA_DDC_CLK (18)
1 2 VGA@ 0_0402_5%
(18) VGA_TV_LUMA
R76 VGA@ 0_0402_5% JP24
1 2 TV_LUMA 1 2 3
(12) UMA_TV_LUMA

2
R391 UMA&TV@ 0_0402_5% L33 TV@ FCM1608C-121T_0603 TV_CRMA_1 6
1 2 TV_COMPS_1 7 R4
(18) VGA_TV_CRMA
R75 VGA@ 0_0402_5% TV_CRMA 1 2 5 4.7K_0402_5%
1 2 L31 TV@ FCM1608C-121T_0603 2 UMA@
(12) UMA_TV_CRMA
R393 UMA&TV@ 0_0402_5% TV_LUMA_1 4

1
1 2 TV_COMPS 1 2 1
(18) VGA_TV_COMPS
R83 VGA@ 0_0402_5% L29 TV@ FCM1608C-121T_0603 8
1 2 9 +3VS
(12) UMA_TV_COMPS
R392 UMA&TV@ 0_0402_5% C317 C346 C301 C337
1

R202 R214 R220 1 82P_0402_50V8J


1 1 82P_0402_50V8J 1 82P_0402_50V8J
1 1 82P_0402_50V8J
TV@ TV@ TV@ TV@ TV@ TV@ TV@ TV@ SUYIN_030107FR007SX08FU
TV@
150_0402_1%
150_0402_1% 2 2 2 2 2 2
2

150_0402_1%
C335 C323
82P_0402_50V8J 82P_0402_50V8J
TV@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICW50 / ICY70 LA-3581P
Date: Friday, April 20, 2007 Sheet 19 of 42
A B C D E
5 4 3 2 1

LCD POWER CIRCUIT TXOUT0- VGA_TXOUT0-


1 4 VGA_TXOUT0- (18)
TXOUT0+ 2 3 VGA_TXOUT0+
VGA_TXOUT0+ (18)
RP40 VGA@ 0_0404_4P2R_5%
TXOUT1- 1 4 VGA_TXOUT1-
VGA_TXOUT1- (18)
TXOUT1+ 2 3 VGA_TXOUT1+
VGA_TXOUT1+ (18)
RP52 VGA@ 0_0404_4P2R_5%
+3VALW +3VS TXOUT2- VGA_TXOUT2-
1 4 VGA_TXOUT2- (18)
+LCDVDD TXOUT2+ VGA_TXOUT2+
W=60mils 2
RP42
3
VGA@ 0_0404_4P2R_5%
VGA_TXOUT2+ (18)
TXCLK- 1 4 VGA_TXCLK-
VGA_TXCLK- (18)

1
1 TXCLK+ 2 3 VGA_TXCLK+
VGA_TXCLK+ (18)
R19 C10 RP44 VGA@ 0_0404_4P2R_5%
R17 100K_0402_5% TZOUT0- 1 4 VGA_TZOUT0-
D VGA_TZOUT0- (18) D
300_0402_5% 4.7U_0805_10V4Z TZOUT0+ 2 3 VGA_TZOUT0+
2 VGA_TZOUT0+ (18)
RP54 VGA@ 0_0404_4P2R_5%

1 2

2
TZOUT1- 1 4 VGA_TZOUT1-
VGA_TZOUT1- (18)

3
D S
TZOUT1+ VGA_TZOUT1+
G 2 3 VGA_TZOUT1+ (18)
Q4 2 2 1 2 Q3 RP46 VGA@ 0_0404_4P2R_5%
2N7002_SOT23 G R18 1K_0402_5% AO3413_SOT23-3 TZOUT2- 1 4 VGA_TZOUT2-
VGA_TZOUT2- (18)

1
S 1
D TZOUT2+ 2 3 VGA_TZOUT2+
VGA_TZOUT2+ (18)

1
R513 C14 +LCDVDD RP48 VGA@ 0_0404_4P2R_5%
1K_0402_5% W=60mils TZCLK- 1 4 VGA_TZCLK-
VGA_TZCLK- (18)

1
UMA@ D 0.047U_0402_16V7K TZCLK+ VGA_TZCLK+
@ 2 3 VGA_TZCLK+ (18)
R308 1 2
(12) UMA_ENVDD 2 0_0402_5% 2 Q39 RP50 VGA@ 0_0404_4P2R_5%

2
VGA@ G 2N7002_SOT23 1 1
R309 1 2 0_0402_5% S C500 C501
(18) ENVDD

3
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z I2CC_SCL 1 4 UMA_LCD_CLK UMA_LCD_CLK (12)
R310 2 2 I2CC_SDA UMA_LCD_DATA
2 3 UMA_LCD_DATA (12)
100K_0402_5% RP56 UMA@ 0_0404_4P2R_5%
TXOUT0+ 1 4 UMA_TXOUT0+
2 UMA_TXOUT0+ (12)
TXOUT0- 2 3 UMA_TXOUT0-
UMA_TXOUT0- (12)
RP41 UMA@ 0_0404_4P2R_5%
+3VS TXOUT1+ 1 4 UMA_TXOUT1+
UMA_TXOUT1+ (12)
TXOUT1- 2 3 UMA_TXOUT1-
UMA_TXOUT1- (12)
RP53 UMA@ 0_0404_4P2R_5%

1
TXOUT2+ 1 4 UMA_TXOUT2+
UMA_TXOUT2+ (12)
R307 TXOUT2- 2 3 UMA_TXOUT2-
UMA_TXOUT2- (12)
RP43 UMA@ 0_0404_4P2R_5%
4.7K_0402_5% TXCLK+ 1 4 UMA_TXCLK+
UMA_TXCLK+ (12)
D16 TXCLK- 2 3 UMA_TXCLK-
UMA_TXCLK- (12)

2
BKOFF# 1 2 RB751V_SOD323 DISPOFF# RP45 UMA@ 0_0404_4P2R_5%
(27,28) BKOFF#
TZOUT0+ 1 4 UMA_TZOUT0+
UMA_TZOUT0+ (12)
TZOUT0- 2 3 UMA_TZOUT0-
UMA_TZOUT0- (12)
Update Footprint RP55 UMA@ 0_0404_4P2R_5%
C TZOUT1+ UMA_TZOUT1+ C
1 4 UMA_TZOUT1+ (12)
TZOUT1- 2 3 UMA_TZOUT1-
UMA_TZOUT1- (12)
RP47 UMA@ 0_0404_4P2R_5%
TZOUT2+ 1 4 UMA_TZOUT2+
UMA_TZOUT2+ (12)
TZOUT2- 2 3 UMA_TZOUT2-
UMA_TZOUT2- (12)
RP49 UMA@ 0_0404_4P2R_5%
TZCLK+ 1 4 UMA_TZCLK+
UMA_TZCLK+ (12)
TZCLK- 2 3 UMA_TZCLK-
UMA_TZCLK- (12)
RP51 UMA@ 0_0404_4P2R_5%
LCD/PANEL BD. Conn.
JP1 10/2 SWAP PIN
42 GND GND 41
+INVPWR_B+ 40 39 DAC_BRIG W=40mils
40 39 DAC_BRIG (27,28)
38 37 INVTPWM 1 2 INVT_PWM D18
38 37 INVT_PWM (27,28) +DVI_VCC F2
+3VS 36 35 DISPOFF# R15 1 2 0_0402_5% DVI@ RB411D_SOT23
36 35 DPST_PWM (12,27,28)
I2CC_SCL 34 33 R16 @ 0_0402_5% 1.1A_6VDC_FUSE
(18) I2CC_SCL 34 33
I2CC_SDA 32 31 (60 MIL) DVI@ 2 1 1 2 +5VS
(18) I2CC_SDA 32 31
30 29 L4 2 1 +LCDVDD 1
TZOUT0- 30 29 KC FBM-L11-201209-221LMAT_0805
28 28 27 27
TZOUT0+ 26 25 TXOUT0- C502
26 25 TXOUT0+ 0.1U_0402_16V4Z
TZOUT1+
24 24 23 23 9/25 Added for EMI 2
22 21 DVI@
TZOUT1- 22 21 TXOUT1-
20 19

TZOUT2+
18
16
20
18
19
17 17
15
TXOUT1+ DVI-D Connector
TZOUT2- 16 15 TXOUT2+ +3VS
14 14 13 13 +DVI_VCC
12 11 TXOUT2- JP15
12 11

1
TZCLK- 10 9 1 4 DVI_TXD0- 17 14
10 9 (18) VGA_DVI_TXD0- TMDS_DATA0- +5V
@ TZCLK+ 8 7 TXCLK- 2 3 DVI_TXD0+ 18 R327 R331
8 7 (18) VGA_DVI_TXD0+ TMDS_DATA0+
0_0402_5% 6 5 TXCLK+ RP36 DVI@ 0_0404_4P2R_5% 4.7K_0402_5% 4.7K_0402_5%
6 5

2
B R305 USB20_CMOS_N4 DVI_TXD1+ DVI_TXD1- DVI@ DVI@ B

G
(14) USB20_N4 1 2 4 4 3 3 (18) VGA_DVI_TXD1+ 1 4 9 TMDS_DATA1-
R306 1 2 USB20_CMOS_P4 2 1 +3VS 2 3 DVI_TXD1- DVI_TXD1+ 10
(14) USB20_P4 (18) VGA_DVI_TXD1-

2
0_0402_5% 2 1 RP37 DVI@ 0_0404_4P2R_5% TMDS_DATA1+
1 3
@ ACES_88242-4001 1 4 DVI_TXD2- 1

S
(18) VGA_DVI_TXD2- TMDS_DATA2- VGA_DVI_SCLK (18)
2 3 DVI_TXD2+ 2 6 Q44
(18) VGA_DVI_TXD2+ TMDS_DATA2+ DDC_CLOCK

2
RP38 DVI@ 0_0404_4P2R_5% 2N7002_SOT23

G
12 DVI@
TMDS_DATA3-
13 TMDS_DATA3+ DDC_DATA 7 1 3

S
VGA_DVI_SDATA (18)
4 Q45
L3 Fro CMOS Cemera 5
TMDS_DATA4-
TMDS_DATA4+
2N7002_SOT23
USB20_P4 4 3 USB20_CMOS_P4 DVI@
4 3 R337
20 TMDS_DATA5-
21 16 1 2 DVI_DET DVI_DET (18)
USB20_N4 USB20_CMOS_N4 DAC_BRIG TMDS_DATA5+ Hot Plug Detect
1 1 2 2 1 2

1
C7 @ 220P_0402_50V7K 0_0402_5%
WCM2012F2S-900T04_0805 INVTPWM 1 2 1 4 DVI_TXC+ 23 DVI@ R336
(18) VGA_DVI_TXC+ TMDS_Clock+
CMOS@ C11 @ 220P_0402_50V7K 2 3 DVI_TXC- 24 @ D19
(18) VGA_DVI_TXC- TMDS_Clock-
DISPOFF# 1 2 RP39 DVI@ 0_0404_4P2R_5% 100K_0402_5% SKS10-04AT_TSMA@
9/25 Added for EMI C8 @ 220P_0402_50V7K 3

2
TMDS_DATA2/4 shield
TMDS_DATA1/3 shield 11
25 Shield TMDS_DATA0/5 shield 19
26 Shield TMDS_Clock shield 22
27 Shield
+INVPWR_B+ +LCDVDD 28
+3VS Shield
31 Shield
L1 2 1 32
B+ Shield
KC FBM-L11-201209-221LMAT_0805
1 1 1 8 Analog VSYNC GND 15
L2 2 1 C9 C12 C13
KC FBM-L11-201209-221LMAT_0805
1 1 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z SUYIN_070939FR024S531PL
A C6 C5 2 2 2 DVI@ A

680P_0603_50V7K 68P_0402_50V8K (HDQ70)


2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS & DVI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ICW50 / ICY70 LA-3581P
Date: Friday, April 20, 2007 Sheet 20 of 42
5 4 3 2 1
5 4 3 2 1

+3VS

1
IDE_D[0..15] C311
(13) IDE_D[0..15] +3VS R216 1 2 0.1U_0402_16V4Z
IDE_A[0..2] 4.7K_0402_5%
(13) IDE_A[0..2]
@ @

5
U12

2
IDE_HRESET# 2 B

P
(15) IDE_HRESET#
R203 4.7K_0402_5% 4 IDE_RESET#
IDE_IORDY PCIRST_IDE# Y
1 2 1
CDROM CONN (13) PCIRST_IDE# A

G
D D
IDE_D7 R217 1 2 10K_0402_5% NC7SZ08P5X_NL_SC70-5

3
@
JP25 IDE_IRQ R190 1 2 10K_0402_5%
1 2
3 4 IDE_DREQ R209 1 2 5.6K_0402_5%
IDE_RESET# 5 6 IDE_D8
IDE_D7 7 8 IDE_D9 IDE_PDIAG# R219 1 2 10K_0402_5% @
IDE_D6 9 10 IDE_D10
IDE_D5 11 12 IDE_D11 R389 33_0402_5%
IDE_D4 13 14 IDE_D12 1 2
+5VS IDE_D3 15 16 IDE_D13
IDE_D2 17 18 IDE_D14
IDE_D1 19 20 IDE_D15
IDE_D0 21 22 IDE_DREQ
IDE_DREQ (13)
1

23 24 IDE_IOR#
IDE_IOR# (13)
R187 IDE_IOW# 25 26 +5VS
(13) IDE_IOW#
100K_0402_5% IDE_IORDY 27 28 IDE_DACK#
(13) IDE_IORDY IDE_DACK# (13)
IDE_IRQ 29 30
(13) IDE_IRQ
IDE_A1 31 32 IDE_PDIAG# 0.1U_0402_16V4Z
2

IDE_A0 33 34 IDE_A2
IDE_CS1# 35 36 IDE_CS3# 1 1 1 1
(13) IDE_CS1# IDE_CS3# (13)
IDE_LED# IDE_LED# 37 38 C274