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Sequential logic

• Latches

• Flip-flops

• Counters

Real-Time Systems: Sequential

Logic

Time

Until now: we have essentially ignored the

issue of time

• We have assumed that our digital logic

circuits perform their computations

instantaneously

• Our digital logic circuits have been

“stateless”

– Once you present a new input, they forget

everything about previous inputs

Real-Time Systems: Sequential

Logic

Time

In reality, time is an important issue:

• Even our logic gates induce a small

amount of delay (on the order of a few

nanoseconds)

• For much of what we do – we actually

want our circuits to have some form of

memory

Real-Time Systems: Sequential

Logic

Timing Notation

high

In transition

low

(undetermined)

X

time

Real-Time Systems: Sequential

Logic

Timing Notation

Either high or low (but well

In transition

defined and constant)

(undetermined)

time

low

Real-Time Systems: Sequential

Logic

NAND Latch

What does this circuit do?

Real-Time Systems: Sequential

Logic

NAND Latch

Consider this initial state

1

0

1

1

Is this a stable state?

Andrew H. Fagg: Embedded

Yes! 7

Real-Time Systems: Sequential

Logic

NAND Latch

What happens with S is set to 0?

0

0->?

1->?

1

Real-Time Systems: Sequential

Logic

NAND Latch

What happens with S is set to 0?

0

0->1

1->0

1

Q becomes 1 (thus S ‘sets’ Q)

Andrew H. Fagg: Embedded 9

Real-Time Systems: Sequential

Logic

NAND Latch

Now S is set 1 – what happens?

1

1->?

0->?

1

Real-Time Systems: Sequential

Logic

NAND Latch

Q and Q’ remain the same!

1

1->1

0->1

1

So Q and Q’ retain a memory of past state!

Andrew H. Fagg: Embedded 11

Real-Time Systems: Sequential

Logic

NAND Latch

Now set R to 0 – what happens?

1

1->?

0->?

0

Real-Time Systems: Sequential

Logic

NAND Latch

Now set R to 0 – what happens?

1

1->0

0->1

0

The state flips back (Q is ‘reset’)

Andrew H. Fagg: Embedded 13

Real-Time Systems: Sequential

Logic

NAND Latch

Finally: set R to 1 – what happens?

1

0->?

1->?

1

Real-Time Systems: Sequential

Logic

NAND Latch

Finally: set R to 1 – what happens?

1

0->0

1->1

1

Q and Q’ do not change state

Andrew H. Fagg: Embedded 15

Real-Time Systems: Sequential

Logic

Timing Diagram Representation

Q

?

Q’

Real-Time Systems: Sequential

Logic

Timing Diagram Representation

S

Q’

Real-Time Systems: Sequential

Logic

Timing Diagram Representation

S

When S returns to high –

R both Q and Q’ remain in

the same state

Q

Q’

Real-Time Systems: Sequential

Logic

Timing Diagram Representation

Q

?

Q’

Real-Time Systems: Sequential

Logic

Timing Diagram Representation

R

Q and Q’ flip

state

Q

Q’

Real-Time Systems: Sequential

Logic

Timing Diagram Representation

Q’

Real-Time Systems: Sequential

Logic

Timing Diagram Representation

Q

No change in Q and Q’

Q’

Real-Time Systems: Sequential

Logic

Latches

Provide us with a simple form of memory

• State of the circuit depends not only on

the current inputs, but also on the recent

history of the inputs

Real-Time Systems: Sequential

Logic

Latches

But: our circuit responds any time the inputs

are low

• We want to limit the state change to a very

narrow time period

• This will allow us to synchronize the state

change of several devices

Andrew H. Fagg: Embedded 24

Real-Time Systems: Sequential

Logic

Flip Flops

• Add one more input to the circuit: a “clock”

signal

• We will only allow the state of the output to

change in response to S & R when the

clock transitions from 1 to 0

Real-Time Systems: Sequential

Logic

Flip Flops

• Add one more input to the circuit: a “clock”

signal

• We will only allow the state of the output to

change in response to S & R when the

clock transitions from 1 to 0

Real-Time Systems: Sequential

Logic

Flip Flops

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Initial state

0 1 1

0 0

0 1 1

1

0 0

1

Note that the meaning of S & R has been inverted

Andrew H. Fagg: Embedded 28

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Clock goes high

0 1 1

0 0

0->1 1 1

1

0 0->1

1->0

No change in Q and Q’

Andrew H. Fagg: Embedded 29

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Clock goes low again

0 1 1

0 0

1->0 1 1

1

0 1->0

0->1

Still no change in Q and Q’

Andrew H. Fagg: Embedded 30

Real-Time Systems: Sequential

Logic

R-S Flip Flop

S goes high

0->1 1 1

0 0

0 1 1

1

0 0

1

Nothing in the circuit changes

Andrew H. Fagg: Embedded 31

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Now: clock goes high

1 1->0 1

0->1 0

0->1 1->0 1

1

0 0->1

1->0

The state of the first latch changes

Andrew H. Fagg: Embedded 32

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Now: clock goes low

1 0->1 1->0

1 0->1

1->0 0 1->0

1

0 1

0->1

The state of the second latch changes!

Andrew H. Fagg: Embedded 33

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Timing Diagram Representation

only after the

clock goes low

Q

Q’

Andrew H. Fagg: Embedded 34

Real-Time Systems: Sequential

Logic

R-S Flip Flop

The timing of the drop of S is not critical

• But it must do so before the clock goes

low

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Timing Diagram Representation

require a

specified amount

Q of “setup time”

Q’

Andrew H. Fagg: Embedded 36

Real-Time Systems: Sequential

Logic

R-S Flip Flop Summary

Behaves like an R-S latch – but:

• The flip flop will only “pay attention” to the

R-S inputs on the falling edge of the clock

Real-Time Systems: Sequential

Logic

Next Time

• D flip flops

• Binary number encoding

• Shift registers

• Counters

Real-Time Systems: Sequential

Logic

Last Time

• Project 1 specification

• Sequential logic:

– R-S Latch

– R-S Flip flop

Real-Time Systems: Sequential

Logic

Today

Sequential circuits continued

• Clocked R-S latch

• D Flip flop

• Binary coding

• Shift registers

• Counters

Real-Time Systems: Sequential

Logic

Administrivia

• Mark back?

• Homework 1 is out:

– Due Feb 17th @ 5:00

• Project 1:

– Worth 8% of your final grade

– The group that demonstrates successfully first

will receive an extra 0.5% of extra credit

Real-Time Systems: Sequential

Logic

Latch vs Flip flop

• Latch implements a simple form of

memory

• A flip flop adds:

– Precise control over when the state of the

memory changes

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

Allows some control over when the latch

changes state

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

State can only change when the clock is

high

Note that R or S must be high to cause a

reset or a set

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

when the clock is

high

Q

Q’

Andrew H. Fagg: Embedded 45

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

How is this different than our R-S flip flop?

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

Q What do Q and Q’

do?

Q’

Andrew H. Fagg: Embedded 47

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

Q

Clock triggers flip

Q’

Andrew H. Fagg: Embedded 48

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

Q

R triggers reset

Q’

Andrew H. Fagg: Embedded 49

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

Q S triggers set

Q’

Andrew H. Fagg: Embedded 50

Real-Time Systems: Sequential

Logic

Clocked R-S Latch

C No further

changes in state

Q

Q’

Andrew H. Fagg: Embedded 51

Real-Time Systems: Sequential

Logic

R-S Latch vs Flip Flop

What would the R-S flip flop do?

Real-Time Systems: Sequential

Logic

R-S Flip Flop

Q What happens to

Q and Q’?

Q’

Andrew H. Fagg: Embedded 53

Real-Time Systems: Sequential

Logic

R-S Flip Flop

R

State change only

C on downward

edge of the clock

Q

Q’

Andrew H. Fagg: Embedded 54

Real-Time Systems: Sequential

Logic

R-S Flip Flop

State change happens at a very precise time

Real-Time Systems: Sequential

Logic

R-S Flip Flop

State change happens at a very precise time

But:

• We must guarantee that R and S are

never high at the same time

• We would like to be able to store the

high/low state of a single line

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

Replace R/S with D

• In essence, R is replaced with D’

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

D=1 results in a ‘set’ of the latch

1 0

1

1

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

D=1 results in a ‘set’ of the latch

1 0 1 1

1

1 0 1

0

Andrew H. Fagg: Embedded 59

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

Clock transitions from high to low

1 0->1 1 1->0

1->0

1 0 1

0->1

Andrew H. Fagg: Embedded 60

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

Clock transition -> ‘set’ of the slave latch

1 0->1 1 1->0 1

1->0

1 0 1 0

0->1

Andrew H. Fagg: Embedded 61

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

D=0 results in a ‘reset’ of the latch

0 1

1

0

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

D=0 results in a ‘reset’ of the latch

0 1

0 1

1

0 1 1

0

Andrew H. Fagg: Embedded 63

Real-Time Systems: Sequential

Logic

D-Type Flip Flop

Clock transitions from high to low results in a

‘reset’ of the slave latch

0 1

0 1 0

1->0

1 1

0->1 1->0

0->1

Andrew H. Fagg: Embedded 64

Real-Time Systems: Sequential

Logic

D Flip Flop

What happens to

Q Q and Q’?

Q’

Andrew H. Fagg: Embedded 65

Real-Time Systems: Sequential

Logic

D Flip Flop

What happens to

Q Q and Q’?

Q’

Andrew H. Fagg: Embedded 66

Real-Time Systems: Sequential

Logic

D Flip Flop

What happens to

Q Q and Q’?

Q’

Andrew H. Fagg: Embedded 67

Real-Time Systems: Sequential

Logic

D Flip Flop

No change

in state

Q

Q’

Andrew H. Fagg: Embedded 68

Real-Time Systems: Sequential

Logic

D Flip Flops

Clock

Real-Time Systems: Sequential

Logic

An Application of D Flip Flops

What does this circuit do?

Real-Time Systems: Sequential

Logic

Shift Register

On each clock transition from high to low:

• X0 takes on the current value of D

• X1 <- X0

• X2 <- X1

Real-Time Systems: Sequential

Logic

Another D Flip Flop Circuit

How does this circuit behave?

Real-Time Systems: Sequential

Logic

Frequency Divider

How does this circuit behave?

CLK

Real-Time Systems: Sequential

Logic

Frequency Divider

Q flips state on every downward edge of the

clock

CLK

Real-Time Systems: Sequential

Logic

A Bit About Binary Encoding

www.thinkgeek.com

If a boolean variable

can only encode two

different values, how

do we represent a

larger number of

values?

Real-Time Systems: Sequential

Logic

Binary Encoding

How do we represent a larger number of

values?

• As with our decimal number system: we

concatenate binary digits (or “bits”) into

strings

Real-Time Systems: Sequential

Logic

Binary Encoding

• The first (rightmost) bit is the 1’s digit

• The second bit is the 2’s digit

• The ith bit is the 2i-1 ’s digit

Real-Time Systems: Sequential

Logic

Binary Encoding

B2 B1 B0 decimal

How do we

convert from 0 0 0 0

binary to 0 0 1 1

decimal in 0 1 0 2

general? 0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

Andrew H. Fagg: Embedded 78

Real-Time Systems: Sequential

Logic

Last Time

Sequential Logic

• D Flip Flops

• Shift registers

• Ripple Counters

Real-Time Systems: Sequential

Logic

Today

• A little more on number systems

• Arithmetic operators

• Representing negative numbers

• Multiplication with shift registers

• Arithmetic logic units

Real-Time Systems: Sequential

Logic

Administrivia

• Homework 1 due in 1 week

• Project 1:

– One robot is now up and stable

– A complete set of power supplies will be

available today

Real-Time Systems: Sequential

Logic

Binary to Decimal Conversion

value = B0 + B1 * 2 + B2 * 2 + B3 * 2 + K

1 2 3

N −1

i

value = ∑ Bi * 2

i =0

to binary?

Real-Time Systems: Sequential

Logic

Decimal to Binary Conversion

∀i : Bi ← 0

while(value ≠ 0)

{

i +1 i

Find i suchthat 2 > value ≥ 2

Bi ← 1

i

value ← value − 2

}

Andrew H. Fagg: Embedded 83

Real-Time Systems: Sequential

Logic

Binary Counter

How would we build a B2 B1 B0

circuit that counts the 0 0 0

number of clock ticks 0 0 1

that have gone by? 0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Andrew H. Fagg: Embedded 84

Real-Time Systems: Sequential

Logic

Binary Counter

How would we build a B2 B1 B0

circuit that counts the 0 0 0

number of clock ticks 0 0 1

that have gone by?

0 1 0

Insight:

• B1 changes state at half 0 1 1

the frequency that B0 1 0 0

does 1 0 1

• B2 changes state at half 1 1 0

the frequency of B1

1 1 1

Andrew H. Fagg: Embedded 85

Real-Time Systems: Sequential

Logic

Ripple Counter

The carry “ripples” down the chain …

Real-Time Systems: Sequential

Logic

J-K Flip Flops

Behave similarly to R-S flip flops, but:

• Deal properly with the case where both R

and S inputs are 1

– The R-S flip flop will arbitrarily choose one of

the possible output states

• The master latch (on the input side) can

only change state once while the clock is

high

Real-Time Systems: Sequential

Logic

T Flip Flops

• J-K flip flop with R and S tied high

• Every downward clock edge causes the

flip flop to change state

connected to Q’

Real-Time Systems: Sequential

Logic

Next Time

Binary Arithmetic:

• Addition

• Representing negative numbers &

subtraction

• A little bit on multiplication

Other number systems

• Octal

• Hexadecimal

Real-Time Systems: Sequential

Logic

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