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Points Addressed in this Lecture

• Design of FSMs
• Delays
• Ring Counter
Lecture 13: Applications • Serial Data
• Serial Adder
Professor Peter Cheung • Schmitt Trigger
Department of EEE, Imperial College London

E1.2 Digital Electronics I 13.1 Dec 2007 E1.2 Digital Electronics I 13.2 Dec 2007

FSM Example - A Sequence Detector A Sequence Detector (Con’t)


• To detect the occurrence of the binary sequence 1010. • Draw the State Diagram (use Mealy model)
"1010" detector

input D output Z
D
state "bubble"
Serial data input Detector output 1/0
Z 1/0
CLK 0/0
CLK 1/0
0/0 1/0
IDLE 01 11 10
• D input changes on falling edge of CLK, detector changes state 00
on rising edge of CLK.
0/0
CLK assigned state value
0/1
D state transition S1 S0

E1.2 Digital Electronics I 13.3 Dec 2007 E1.2 Digital Electronics I 13.4 Dec 2007
A Sequence Detector (Con’t)
input D output Z
A Sequence Detector (Con’t)
state "bubble"
1/0
• Draw State Transition Table 1/0
0/0 1/0 • Design hardware
0/0 1/0
IDLE 01 11 10
00

Inputs Outputs 0/0


assigned state value
S1 S0 D N1 N0 Z 0/1
state transition S1 S0
0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 1 0

0 1 1 0 1 0

1 1 0 0 0 0

1 1 1 1 0 0

1 0 0 0 0 1

1 0 1 0 1 0

E1.2 Digital Electronics I 13.5 Dec 2007 E1.2 Digital Electronics I 13.6 Dec 2007

A Sequence Detector (Con’t) A Sequence Detector (Con’t)


• Draw Karnaugh Map • Derive Boolean Equations
Map for N1 Inputs Outputs
Map for N1
D/ S1:S0 00 01 11 10 S1 S0 D N1 N0 Z
D/ S1:S0 00 01 11 10
0 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0
1 0 0 1 0
0 0 1 0 1 0
1 0 0 1 0 N 1 = D • S1 • S 0 + D • S1 • S 0
Map for N0 0 1 0 1 1 0 Map for N0 N 0 = S1 • S 0 + D • S 0
D/ S1:S0 00 01 11 10 0 1 1 0 1 0 D/ S1:S0 00 01 11 10
0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 Z = D • S1 • S 0
1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1
Map for Z 1 0 0 0 0 1 Map for Z
D/ S1:S0 00 01 11 10 1 0 1 0 1 0 D/ S1:S0 00 01 11 10
0 0 0 0 1 0 0 0 0 1
1 0 0 0 0 1 0 0 0 0

E1.2 Digital Electronics I 13.7 Dec 2007 E1.2 Digital Electronics I 13.8 Dec 2007
Delays

• A shift register can be used as a delay element • Synchronous Delay


– Each Q output lags behind the D input by successive numbers of – The input signal DIN is aligned with the clock
clock periods – The outputs Q0, Q1, Q2 will be delayed by 1,2 and 3 CLOCK
periods respectively
• Asynchronous Delay
SRG3
CLOCK C1 – The input signal DIN is NOT aligned with the clock
– The Q0 output will be delayed by up to 1 clock period
DIN Q0
1D – Q1 and Q2 will be delayed by further whole clock periods
Q1

Q2

E1.2 Digital Electronics I 13.9 Dec 2007 E1.2 Digital Electronics I 13.10 Dec 2007

Timing Diagram of Shift Register Ring Counter

CLOCK CLOCK
• A ring counter is made from a shift register with the
DIN DIN
output of the last bit fed to the input of the first bit
Q0 Q0

Q1 Q1

Q2 Q2
SRG4
CLOCK C1
Asynchronous Input Synchronous Input
DIN Q0
1D
Q1

Q2
Note: These timing diagrams do not show
the CLOCK-to-Q delays of the flip-flops. Q3

In practice, changes in output will follow


slightly later than the rising edge of the CLOCK

E1.2 Digital Electronics I 13.11 Dec 2007 E1.2 Digital Electronics I 13.12 Dec 2007
Serial Adder
• Transition Table
– The above can be summarised in the following table • Bit-serial data
– Normally when we think of binary numbers represented in digital
Q3 DIN Q0:3 (Q0:3)+ electronic hardware, we think of parallel data
0 0 n 2n • one connection per bit
0 1 n 2n+1 • all bits processed together
1 0 n 2n-16 – In bit-serial data, the bits making up a binary number are
1 1 n 2n-15 processed one bit at a time
• takes longer but
• simplifies the hardware
– Now reconnect the feedback from Q3 to DIN
– the operation of the ring counter follows the top and bottom Eg.
lines of the table only
– to add two 8-bit numbers in parallel requires 8 full adders
– to add two 8-bit numbers bit-serially requires only 1 full adder
and some registers

E1.2 Digital Electronics I 13.13 Dec 2007 E1.2 Digital Electronics I 13.14 Dec 2007

Circuit Diagram for Bit-serial Adder


Schmitt Trigger
• The 2 numbers to be
SRG8
• Slowly changing input transitions may cause oscillations on
LOAD
added (A0:7 and B0:7) M2
the output of digital devices
are stored in shift CLOCK C1 5V
registers. – EG: inverter input
A7 1,2D
• The bits of A and B are A6 LOAD R 0V
A5 CLOCK C1
presented to a 1-bit A4 5V
A3 1D
adder one bit at a time A2 output
A1
starting with the LSB. A0
Σ 0V
CIN CO
• The flip-flop stores the SRG8 P SRG8
LOAD
carry from the previous M2
Q
Σ • Schmitt Trigger circuits produce “clean” outputs
CLOCK C1 CLOCK C1
summation and is 5V
initialised to 0, ie. B7 1,2D 1D S7 input
CIN=0 for the addition B6 S6 – this is achieve by having different
B5 S5 0V
of the LSBs B4 S4 thresholds for low-to-high and
B3 S3 5V
• After 8 clock periods B2 S2 high-to-low transitions. output
B1 S1
the result is stored in B0 S0
– known as hysteresis 0V
the output shift register
S0:7.
E1.2 Digital Electronics I 13.15 Dec 2007 E1.2 Digital Electronics I 13.16 Dec 2007
FSM Example – Vending Machine Step 2: Draw State Diagram
00/00
• Step 1: Define the problem inputs/output = p20:p10/vend:change
– Accepts 10p and 20p coins S0
– Delivers a can of drink costing 30p
– Provide change where appropriate S1
00/00
S2
p10 vend
coins Input Output Drink & 00/00
FSM
Conditioning p20 change Drivers change
S3

Clock
00/00
• Assumptions:
– One coin at a time • FSM remains in S0 until there is a p20 or p10 input
– Generate pulse p10 or p20 lasting for one clock cycle when coin inserted • S1 represents 10p credit
– vend = 1 for one clock period to deliver a coke • S2 represent 20p credit
– change = 1 for one clock period to return a 10p coin • S3 represent 40p credit

E1.2 Digital Electronics I 13.17 Dec 2007 E1.2 Digital Electronics I 13.18 Dec 2007

Step 3: Reduce state diagram Step 4: Ensure no undefined states

00/00

inputs/output = p20:p10/vend:change inputs/output = p20:p10/vend:change 00/00


S3
S0 xx/00
01/00
01/10 10/00 S0
10/10 01/00
S1 10/11 01/10 10/00
00/00 S2
00/00
01/00 S1 10/10 10/11
00/00 S2
00/00
• Two states are said to be equivalent if they have 01/00
– identical next states
– Identical outputs

• Therefore S3≡S2

E1.2 Digital Electronics I 13.19 Dec 2007 E1.2 Digital Electronics I 13.20 Dec 2007
Step 5: Draw State Transition Table Step 6: Assign binary value to states
S0p = 00
S10p = 01
Outputs S20p = 11 Outputs
Next State
vend: change Sbad = 10 vend: change
Next State n1: n0

Inputs p20: p10 Inputs p20: p10

00 01 11 10 00 01 11 10

S0p S0p,00 S10p,00 xx,xx S20p,00 S0p 00,00 01,00 xx,xx 11,00
Current State

Current State
S10p S10p,00 S20p,00 xx,xx S0p,10 S10p 01,00 11,00 xx,xx 00,10
S20p S20p,00 S0p,10 xx,xx S0p,11 S20p 11,00 00,10 xx,xx 00,11
Sbad S0p,00 S0p,00 xx,xx S0p,00 Sbad 00,00 00,00 xx,xx 00,00

E1.2 Digital Electronics I 13.21 Dec 2007 E1.2 Digital Electronics I 13.22 Dec 2007

Step 7: Hardware design Step 8: Draw Karnaugh Map for each output variable
clock
C1
p20 Inputs p20: p10 Inputs p20: p10
1D vend

Current State s1:s0


Current State s1:s0
p10 Combinational
Logic gates change n1 00 01 11 10 n0 00 01 11 10
n1
n0
s1 00 0 0 x 1 00 0 1 x 1
s0 01 0 1 x 0 01 1 1 x 0
Outputs 11 1 0 x 0 11 1 0 x 0
Next State Inputs p20: p10 vend: change
n1: n0 10 0 0 x 0 10 0 0 x 0
00 01 11 10
Current State s1:s0

00 00,00 01,00 xx,xx 11,00


n1 = s1 s0 p20 p10 + s1 s0 p10 + s1 s0 p 20
01 01,00 11,00 xx,xx 00,10
11 11,00 00,10 xx,xx 00,11 n0 = s0 p 20 p10 + s1 p10 + n1 n0 p 20
10 00,00 00,00 xx,xx 00,00

E1.2 Digital Electronics I 13.23 Dec 2007 E1.2 Digital Electronics I 13.24 Dec 2007
Inputs p20: p10 Inputs p20: p10

Current State s1:s0


Current State s1:s0

vend 00 01 11 10 change 00 01 11 10
00 0 0 x 0 00 0 0 x 0
01 0 0 x 1 01 0 0 x 0

11 0 1 x 1 11 0 0 x 1
10 0 0 x 0 10 0 0 x 0

vend = s1 s0 p10 + s0 p 20 change = s1 s0 p 20

E1.2 Digital Electronics I 13.25 Dec 2007