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Following is an example of the Moore Machine with Asynchronous Reset, "RESET".

• 4 states: s1, s2, s3, s4
• 5 transitions
• 1 input: "x1"
• 1 output: "outp"

This model is represented by the following bubble diagram:

Related Constraints

Related constraints are:

• FSM_extract
• FSM_encoding
• FSM_fftype
• ENUM_encoding

FSM with 1 Process

Please note, in this example output signal "outp" is a register.


Following is the VHDL code for an FSM with a single process.

library IEEE;
use IEEE.std_logic_1164.all;

begin process (clk. architecture beh1 of fsm is type state_type is (s1. when s4 => state <= s1. the output is associated with the transitions as indicated on the following state diagram (Figure 6). outp <= '0'. end if.s2.s4). when s2 => state <= s4.s3. outp : OUT std_logic). outp <= '1'. mealy machine seq detector Example of a Mealy Machine The sequence following detector recognizes the input bit sequence X: "1011". end if. reset.reset) begin if (reset ='1') then state <=s1. else state <= s3. The VHDL file is given below. The machine will keep checking for the proper bit sequence and does not reset to the initial state after it recognizes the string. end entity. outp <= '0'. signal state: state_type . . realized as a Mealy Machine. x1 : IN std_logic. Figure 6: Sequence detector (1011). end process. outp <= '1'. end case. when s3 => state <= s4. In case we are implementing a Mealy machine. end beh1. elsif (clk='1' and clk'event) then case state is when s1 => if x1='1' then state <= s2.entity fsm is port ( clk. outp<='1'.

SYMBOLIC ENCODED state machine: Sreg0 type Sreg0_type is (S1. entity myvhdl is port (CLK. Z: out STD_LOGIC). VHDL file for a sequence detector (1011) implemented as a Mealy Machine library ieee. . end. S2. begin --concurrent signal assignments Sreg0_machine: process (CLK) begin if CLK'event and CLK = '1' then if RST='1' then Sreg0 <= S1. S3. S4).all. RST. X: in STD_LOGIC.std_logic_1164. use ieee. signal Sreg0: Sreg0_type. architecture myvhdl_arch of myvhdl is -. else case Sreg0 is when S1 => if X='0' then Sreg0 <= S1.

end if. when S4 => if X='0' then Sreg0 <= S3. end if. elsif X='1' then Sreg0 <= S2. elsif X='0' then Sreg0 <= S3. elsif X='1' then Sreg0 <= S2. when S2 => if X='1' then Sreg0 <= S2. elsif X='0' then Sreg0 <= S1. end if. end if. when others => . when S3 => if X='1' then Sreg0 <= S4.

end myvhdl_arch. end if. end case. . null. end if. -. end process.signal assignment statements for combinatorial outputs Z_assignment: Z <= '0' when (Sreg0 = S1 and X='0') else '0' when (Sreg0 = S1 and X='1') else '0' when (Sreg0 = S2 and X='1') else '0' when (Sreg0 = S2 and X='0') else '0' when (Sreg0 = S3 and X='1') else '0' when (Sreg0 = S3 and X='0') else '0' when (Sreg0 = S4 and X='0') else '1' when (Sreg0 = S4 and X='1') else '1'.