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VCS® / VCS® MX Beta Feature Descriptions

Version C-2009.06 Beta December 2008

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Copyright © 2008 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

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Contents
1. VCS SystemVerilog Features SystemVerilog Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . Parameterized Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . String Casting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Array Literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemVerilog Linked Lists . . . . . . . . . . . . . . . . . . . . . . . . . . New SystemVerilog Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Task and Function Calls Using Virtual Interface Variables. . . The $typename Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fine-Grained Process Control Using the process Class . . . . Assignment Patterns Using %p . . . . . . . . . . . . . . . . . . . . . . . Signal Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nested Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ’__FILE__ and ’__LINE__ Compiler Directives . . . . . . . . . . . Extension to SystemVerilog $readmemb/$readmemh . . . . . . . . Loading Memories with $readmemb and $readmemh. . . . . . 13 14 16 16 18 19 19 20 22 30 32 33 34 35 35

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2. Assertions Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overlapping Operators in Multiclock Environment . . . . . . . . . . . Deferred Immediate Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . Property Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weak and Strong Sequence Operators . . . . . . . . . . . . . . . . . Implication and Equivalence Operators . . . . . . . . . . . . . . . . . until Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nexttime Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . always Operator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eventually Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . followed-by Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed Strength Property Reporting . . . . . . . . . . . . . . . . . . . . Modeling Abort Conditions: accept_on, reject_on . . . . . . . . . Inferred Value Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recursive Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Variable Initialization and Input . . . . . . . . . . . . . . . . . . . . . Global Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Past and Future Sampled Value Functions . . . . . . . . . . . . . . let Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Support for New Constructs . . . . . . . . . . . . . . . . . . . . Note on Cross Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 43 44 44 45 46 47 47 48 48 49 50 51 52 52 54 54 57 57 57 58

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3. Coverage Enhancements SystemVerilog Language Enhancements . . . . . . . . . . . . . . . . . . Wildcard Support in binsof Expressions . . . . . . . . . . . . . . . . Wildcard Array Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Bin Names as States in Transition Sequences . . . . . . . OpenVera Language Enhancement . . . . . . . . . . . . . . . . . . . . . . Wildcard Support in binsof Expressions . . . . . . . . . . . . . . . . Coverage Exclusion Enhancement . . . . . . . . . . . . . . . . . . . . . . . Understanding Half-Toggle Exclusion . . . . . . . . . . . . . . . . . . Unified Coverage Reporting Enhancements . . . . . . . . . . . . . . . . Reporting Only Uncovered Objects . . . . . . . . . . . . . . . . . . . . Understanding Covergroup Page Splitting. . . . . . . . . . . . . . . DVE Coverage Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . Branch Coverage and Implied Branches . . . . . . . . . . . . . . . . DVE Coverage Source / Database File Relocation . . . . . . . . Container Exclusion State Markers . . . . . . . . . . . . . . . . . . . . 4. Coverage Convergence Technology Compile-Time Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coverage Convergence Option . . . . . . . . . . . . . . . . . . . . . . . Coverage Model Autogeneration Options . . . . . . . . . . . . . . . Coverage Convergence Runtime Options . . . . . . . . . . . . . . . . . URG Options for Bias File Generation . . . . . . . . . . . . . . . . . . . . Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 94 94 95 97 98 60 60 65 66 69 69 73 73 75 75 86 88 88 88 90

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Constraints and Coverage Model on the Same Variables . . No Procedural Overwriting of Values Generated by the Solver

98 98

Coverage Should Be Sampled Between Consecutive Calls to randomize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Use Open Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoid Explicit or Implicit Partitioning in Constraints . . . . . . . 99 100

Avoid In-line Constraints and the Use of “constraint_mode” and “rand_mode” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Automatic Generation a Coverage Model from Constraints . . . . Coverage Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contribution to Coverage Scoring . . . . . . . . . . . . . . . . . . . . . Coverage Model Inference for In-line Constraints . . . . . . . . . Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Understanding Bias Files and Coverage Convergence. . . . . . . . Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Is a “Test”? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 101 108 108 109 110 110 110

Using Coverage Convergence Bias File to Pick Target Coverage Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Automatic Generation of Coverage Convergence Bias Files . . . Repeatability of Test Results for Parallel Regression Runs . . . . Usage Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running a Single Test with Randomized Configurations . . . . Running a Single Test with Randomized Transactions . . . . . Using a Bias File for a Parallel Regression . . . . . . . . . . . . . . Autogenerating a Coverage Model . . . . . . . . . . . . . . . . . . . . 113 114 114 115 115 116 117

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Methodology and Flow Issues . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Scenario: All Tests Have the Same Constraints and Coverage Space (Recommended). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Scenario: Tests Are Grouped Into Categories With Each Category Having Specific Test Constraints . . . . . . . . . . . . . . . . . . . 119 Scenario: Coverage Database Being Loaded in the Beginning of a Test Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5. DVE Features Back Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Back Trace Properties . . . . . . . . . . . . . . . . . . . . . Using the Back Trace Schematic Toolbar . . . . . . . . . . . . . . . Editing the Bus Bit Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating and Updating Counters. . . . . . . . . . . . . . . . . . . . . . . . . Deleting Signal Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 124 125 125 126 129

Creating Multiple Groups when Adding Multiple Scopes into Wave View 130 Visualizing X at all Zoom Levels . . . . . . . . . . . . . . . . . . . . . . . . . Using Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Interfaces as Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. Viewing values in Symbolic format 7. Constraints Features SystemVerilog Constraint Features . . . . . . . . . . . . . . . . . . . . . . . 142 130 131 132 134

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. . . . . . . . . . Solver Overview. . . . . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classes of Constraint Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Model for Toggle and Functional Coverage .Array and XMR Support in std::randomize() . . . . . . . . . . . . . . . . . . VPD File. . Using the Constraint Solver Diagnostics . . . . . . . . . Running Parallel Simulation . . . . Constraint Debugging and Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . Methodology for Using Unidirectional Constraints . . . . . . . . . . . . . . Use Model for Assertion Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . Constraint Solver Search Space and Solution Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 145 148 148 151 154 155 156 158 159 160 163 172 173 174 174 175 175 175 176 176 178 179 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Hierarchical Constraint Debugger Report . . . Parallel VCS Parallel VCS Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging Constraint Solver Diagnostics . . . . . . . . . . . . . . . . . . Design Simulation . . . . . . . . . . . . . . . . . . . . . . . Toggle Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . XMR Support in Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Search Space Reduction And Random Assignment . . . . . . . . . Use Model for VPD Dumping. Functional Coverage . . . . . . . . . Using Constraint Profiling . . . . . . . . . . Use Model for Design Profiling and Simulation . . . . . . . . . . . . . . Assertion Simulation . . . . .

. . . . Writing Firmware Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running PVCS Examples . . . . . . . Specifying Partitions . . . . . . . . . . . . . . . . . . Execution Timeline. . . . . . . . . . . . . . . . VMM Additions and Enhancements VMM RAL C Interface . . . vmm_opts::get_bit() . . . . . . . vmm_opts::get_string() . . . . . . . . . VMM Standard Library Class Additions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::stream_id . . . . . . vmm_opts::get_int() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 181 182 183 198 205 205 208 209 212 214 218 219 220 221 222 223 224 225 226 227 228 229 7 . . . . . . . . Profiling a Parallel Simulation . . . . vmm_opts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entry Point . . . . . . . . . . . . . . . . .Profiling a Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::repeated . . . . . . . . . . . . vmm_scenario::scenario_id . . . . Current Limitations . . . . . . . . . . . . . . . . . . Supported Platforms . vmm_scenario::scenario_kind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Profiling a Serial Simulation . . . . . . . . . . . . . . . . . . . . . vmm_scenario::length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario . . . . vmm_opts::get_help() . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . vmm_object::new . . . . . . . . . . . . . 230 231 232 233 234 235 236 237 238 239 240 241 243 244 245 246 247 248 249 250 251 252 253 254 255 256 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::DONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::define_scenario() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::get_n_scenarios() . . . . . . . . . . . . . . . vmm_ms_scenario_gen::stop_after_n_insts . . . . . . . . vmm_object . vmm_ms_scenario_gen::stop_after_n_scenarios . . . . . . . . . . . . . . . . . vmm_scenario::get_parent_scenario() . . . . . . vmm_scenario::repetition. . . . . . . . . . . . vmm_scenario::set_parent_scenario(). . . . . . . . . vmm_scenario::redefine_scenario(). . . . . . . . . . . . . . . . . . vmm_object::get_hier_inst_name() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::scenario_name(). . .vmm_scenario::repeat_thresh . . . . . vmm_ms_scenario_gen::get_n_insts() . . . . . . . . . . . . . . . vmm_object::get_type() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_object::get_parent() . . . . . . . . . . vmm_object::type_e. . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::inst_count . . . . . . . . . vmm_object::psdisplay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::psdisplay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::scenario_count . . . . . . . . . vmm_ms_scenario_gen::GENERATED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_object::set_parent() . . . . . . . . . . . . . . vmm_object::display() . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::unregister_channel() . . . . . . . vmm_ms_scenario_gen::unregister_ms_scenario() . . . . . vmm_ms_scenario_gen::unregister_ms_scenario_by_name() vmm_ms_scenario_gen::select_scenario . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::get_ms_scenario_gen_name() . . . . vmm_ms_scenario_gen::scenario_set[$] . . . . . . vmm_ms_scenario_gen::get_names_by_channel() . . . . . . . vmm_ms_scenario_gen::register_channel() . . . . . . . . vmm_ms_scenario_gen::get_names_by_ms_scenario() . . . . . . . . . . .vmm_ms_scenario_gen::register_ms_scenario() . vmm_ms_scenario_gen::get_ms_scenario() . . . . . . . . . . vmm_ms_scenario_gen::register_ms_scenario_gen() . . . . . vmm_ms_scenario_gen::get_ms_scenario_gen() . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::get_all_channel_names() . . vmm_ms_scenario_gen::get_channel(). . . . . . . . vmm_ms_scenario_gen::ms_scenario_exists(). . . . . . . . . . . . . . . vmm_ms_scenario_gen::replace_ms_scenario() . . . . . . . . . . . vmm_ms_scenario_gen::channel_exists(). vmm_ms_scenario_gen::get_names_by_ms_scenario_gen() 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 9 . vmm_ms_scenario_gen::get_ms_scenario_index() . . . . vmm_ms_scenario_gen::get_channel_name() . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::ms_scenario_gen_exists(). . vmm_ms_scenario_gen::unregister_channel_by_name() . . . . . . . . vmm_ms_scenario_gen::get_all_ms_scenario_names(). . . . . . . vmm_ms_scenario_gen::replace_channel() . . . . . . vmm_ms_scenario_gen::get_ms_scenario_name() . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_test::get_name() . . . . . . . . . . . . . . . . . vmm_channel . . . vmm_channel::playback() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_test::run() . . . . . . vmm_test::get_doc() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ral_block_or_sys Base Class Additions. . . . . . . . . . . . . . . . . . . . . . . . vmm_test_begin() . . . . . . . . . . . . . . . . . . . . . . . vmm_xactor_iter::new() . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::unregister_ms_scenario_gen() . . . . . . . . . . . . . . . . . . . vmm_log::catch() . . . . . . . . vmm_test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_channel::record() . . . . . . . . vmm_xactor_iter::first() . . . . ‘foreach_vmm_xactor() . . . . . . vmm_xactor_iter::next() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vmm_ms_scenario_gen::get_all_ms_scenario_gen_names() vmm_ms_scenario_gen::replace_ms_scenario_gen() . . . . . . . . . . . . . vmm_test::new() . . . vmm_test::log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario::get_channel(). vmm_test_end() . . . . . . 287 288 289 290 291 292 293 295 296 297 298 299 300 301 303 304 305 306 308 311 10 . 283 284 285 vmm_ms_scenario_gen::unregister_ms_scenario_gen_by_name() 286 vmm_xactor_iter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_xactor_iter::xactor() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging the Doc Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ral_block_or_sys::get_reg_by_offset() . . . . . . . . . . . . . . . . . . . . Measure Score Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [Style|Table] Keyword Indicator . . . Unique Error Code in Error Messages. . . . . . . . . . . . Capturing a Verification Plan in Doc XML Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 322 322 326 331 331 332 334 334 335 336 337 11 . . . . How to Get Scores Back-Annotated in the Doc. . . . . Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Navigating Down to a Subplan . . . . . . . . . . . . . . . . . . . . . License Model . . . . . . . . . . 10. . Table Keyword . . . . . . . . . . . . . . . . . Other Contents. . . . . . . . . . . Built-In Styles . . . . . . Use Model . . . . Plan/Feature Score Summary . . . . . . . . . VMM Planner MS Doc Annotation Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Flow .vmm_ral_block_or_sys::set_offset() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 313 316 317 318 318 319 Compatibility with the VMM Planner Spreadsheet Annotation Flow 319 hvp annotate Command Arguments . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . New –show hvpprob Command for Problem Reports . . . . . Test Metric Coloring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incompleteness Checks. . . . . . . . . . . . . . . . . . . . . . . Run Command run Command . . . . . . . . . . . . . . . . . . 347 339 340 341 342 342 343 343 344 344 345 345 12 . . . . . . . . . . . . . . . Omitting Filtered Features . . . . . . . . . . . Predictable Page Naming Convention . . .11. . . . . . Platform Support . . . . . . . . . . . . . . . . . . . . 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dumping User Data . . . . . . . . . . . . License Model . . . . . . . . . . . . . . . . . Add New Hyperlinks from group bin and group instance. . . . . . . . . . . . . . . . . . . . . . . . . . . . Improved HTML Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . URG Enhancements New URG Features and Changes. .

These features are described in the SystemVerilog Language Reference Manual: • • Strings in structs Queues in unpacked structs VCS SystemVerilog Features 13 .1 VCS SystemVerilog Features This chapter contains the following topics: • • • “SystemVerilog Enhancements” “New SystemVerilog Features” “Extension to SystemVerilog $readmemb/$readmemh” 1 SystemVerilog Enhancements Enhancements have been made to the following features.

• • • • • • • • Associative arrays of unpacked structs Multidimensional queues Arrays of queues Multidimensional associative arrays Multidimensional queues Integer indexed arrays Selecting an array word connected to a task ref port Casting of derived class with base class Additional SystemVerilog enhancements are described in the following sections: • • • • “Parameterized Mailboxes” “String Casting” “Array Literals” “SystemVerilog Linked Lists” Parameterized Mailboxes The default mailbox has no type. A mailbox can send and receive any type of data. When a mailbox is used to transfer a particular message type. it is useful to detect type mismatches at compile time. For a parameterized mailbox. This can result in runtime errors due to type mismatches between a message and the type of the variable to which the message gets assigned. the VCS SystemVerilog Features 14 .

compiler checks that calls to the mailbox methods use the same argument types as the mailbox type so that type mismatches are caught by the compiler. s_mbox sm = new. .get( s ).. Example You declare a parameterized mailbox of a particular type by specifying the type as in the following example.. Syntax mailbox #(type = dynamic_type) where dynamic_type is a type that enables runtime type checking (the default). Parameterized mailboxes use the same parameter syntax as parameterized classes. and interfaces. which are: • num() • new() • get() • peek() • put() VCS SystemVerilog Features 15 . typedef mailbox #(string) s_mbox."hello" Parameterized mailboxes provide the same methods as dynamic mailboxes.put( "hello" ). // s <. sm. sm. modules. string s.

end endprogram Array Literals Any unpacked array can be written one entry at a time. See “Limitations on Variable-Sized Arrays” for restrictions on this feature. String Casting String literals can be cast to a packed or unpacked array. following the same rules as those for assigning a literal string to a packed or unpacked array. try_put(). Example program rb. try_peek(). string realstring. initial begin logic [39:0] StringLogic = "hello".• try_get() • try_peek() • try_put() The compiler checks that calls to the put(). StringLogic. The syntax for associative arrays is: VCS SystemVerilog Features 16 . get(). realstring). realstring = string'(StringLogic). $display("%s -. and try_get() methods use the same argument type as the parameterized mailbox type. or all the array contents can be replaced using an array literal. peek().%s\n".

val2. Table 1-1 Default values for associative array elements Type of array 4-state integral type 2-state integral type string enumeration Default value ‘X ‘0 “” base type default initial value VCS SystemVerilog Features 17 . '{5:'{5.333}}.1}.3}. // An associative array of 4-state integers indexed by // strings integer tab [string] = '{"Peter":20.2.9.33}. if a nonexistent element is read. Example 1-1 Variable-sized arrays // Nested array literals int mix7[][*][3]='{'{0:'{11. 11:'{111. // An associative array of strings indexed by 2-state // integers string words [int]. '{3:'{1.'{index:value} The syntax for other unpacked dimensions is: '{val1.1}}. array literals can be nested. "Paul":22. For an associative array. the default initial value shown in Table 1-1 is returned.9}}}.8. "Mary":23 }.22.3}. 1:'{'1. 7:'{9.2.222.1. val3} or '{default: value} In arrays that have multiple unpacked dimensions. 4:'{3.

This can have unexpected results. VCS SystemVerilog Features 18 . SystemVerilog Linked Lists VCS provides a library implementation for SystemVerilog linked lists as specified in the SystemVerilog Language Reference Manual. Assignments such as "aa = '{0:aa[1]. 1:aa[0]}" are executed as if they were separate assignments. The VCS Users Guide provides details of how to use this feature. in associative arrays Only the following types of associative array indexes are supported: • • integer literal string literal identifier Cross-module references into multidimensional associative arrays structure element type An associative array declared with a non-constant RHS initializer may be initialized before expressions referred to in the RHS are initialized.Limitations on Variable-Sized Arrays The following features are not supported: • • • '{default: value} for associative arrays Identifiers imported from packages.

Bus b(). logic [31:0] rdata = 256. the Read_data() function in the Bus interface is called using the vB virtual interface variable in the test program : interface Bus. data). $display("Data Received = %0d". In the following example. function void Read_data(logic [31:0] data).06: • • • • • • • “Task and Function Calls Using Virtual Interface Variables” “The $typename Function” “Fine-Grained Process Control Using the process Class” “Assignment Patterns Using %p” “Signal Aliasing” “Nested Classes” “’__FILE__ and ’__LINE__ Compiler Directives” Task and Function Calls Using Virtual Interface Variables Tasks and functions in a virtual interface can be called using a variable of that virtual interface type. VCS SystemVerilog Features 19 .New SystemVerilog Features The following SystemVerilog features have been implemented in 2009. endfunction endinterface module Cpu_process.

and enums. A typedef that creates an equivalent type is resolved back to built-in or user-defined types. VCS SystemVerilog Features 20 . The default signing is removed.Read_data(Cpu_process.endmodule program test.rdata). A ‘$’ is used as the placeholder for the name of an anonymous unpacked array. 6.b. unions. User-defined type names are prefixed with their defining package or scope name space. end endprogram The $typename Function The $typename system function returns a string that represents the resolved type of its argument. 5. Actual encoded values are appended with enumeration named constants. Syntax $typename (expression | data_type) The return string is constructed using the following steps: 1. System-generated names are created for anonymous structs. 2. 3. even if present explicitly in the source. 4. initial begin vB. virtual Bus vB = Cpu_process.

VCS SystemVerilog Features 21 . except that simple bit vectors types with predefined widths are distinguished from those with user-defined widths. White space in the source is removed and a single space is added to separate identifiers and keywords from each other. Thus $typename can be used in string comparisons for stricter type comparison of arrays than with type references.7. but never evaluated. $typename returns a string that represents the self-determined type result of the expression. 8. When called with an expression as its argument. Array ranges are represented as unsized decimal numbers. This process is similar to the way that type matching is computed. When used as an elaboration time constant. The expression’s return type is determined during elaboration. the expression shall not contain any hierarchical references or references to elements of dynamic objects.

WAITING.}top. endpackage : A import A::*. int signed Y.} AB_t. package A.AB_t$[0:9]" Source code typedef bit node. and can become members of other classes.B.Example 1-2 Values returned by $typename for different types of variables Value returned by $typename "bit" "bit signed[2:0]" "int" "enum{A=32'd0. The prototype for the process class is as follows: class process. task suspend(). typedef struct {node A.bit B. task await(). node signed [2:0] X. task resume(). SUSPENDED. RUNNING.B. enum {A. typedef bit [9:1'b1] word. Processes can be passed to tasks or functions. KILLED }. function state status().B=32'd1. static function process self(). endmodule Fine-Grained Process Control Using the process Class A process is a built-in class that allows one process to access and control another process once it has started running. enum state { FINISHED. task kill().C=99} X.C='32d99 }A::e$1" "A::bit[9:1]" "struct{bit A. endclass VCS SystemVerilog Features 22 . AB_t AB[10]. module top.

join represents any of the fork-join/join_any/ join_none statements. You cannot use new to create an object of the process class... otherwise the existing handle is returned. process Class Members self() The self() function returns a process class handle corresponding to the process thread in which the function call is executed. An error is issued if this is attempted. Process status is marked RUNNING. The following terms are used below: • • • fork. . Example process p.. The handle can be used for controlling the process and accessing its status using process class methods.A process handle can be created only by a call to the process class self() static method. An error is issued if this is attempted. where n denotes the number of the thread of the fork. fork thread_1 VCS SystemVerilog Features 23 . tf_n represents a task or function call. If the handle does not exist already a new handle is allocated and returned. thread_n is a thread of a fork. A process cannot be extended..

RUNNING. process handle "p" belong to "thread_1". KILLED – The process was killed by a kill() call or disable. KILLED }. the process state is updated to RUNNING. RUNNING – The process is running (not blocked).. The process status is updated upon a change in the process execution and follows the process execution state.tf_1 tf_2 p = process::self thread_2 join . The process is not executing at all. Every time a process blocks. state/status() The status() function returns the current state of the process. Upon unblocking of the process. The possible states are: FINISHED – The process finished execution normally. WAITING – The process is blocked by a delay/@/wait. enum state { FINISHED. or due to a condition such as a blocking mailbox or semaphore call. WAITING. SUSPENDED – The process has been stopped by a suspend() call. SUSPENDED. the process state is updated to WAITING. VCS SystemVerilog Features 24 ..

VCS SystemVerilog Features 25 . . fork thread_1 tf_1 tf_2 p = process::self #10. thread_2 join_none #1.Example process p. Process status is marked as KILLED. A process can be killed if it is not already finished. fork thread_1 tf_1 tf_2 p = process::self #10. kill() The kill() task terminates the process and all its child processes. .. thread_2 join_none #1. estate = p... .status(). process::state estate... // WAITING ... process::state estate.. Example process p. $display("I was killed"). just like disable.

.. Example process p.await(). It unblocks once the awaited process has finished execution normally. . $display("I’m waiting for thread_1 to finish"). await() The await() task blocks the current thread.. fork thread_1 tf_1 tf_2 p = process::self #10. If the awaited process is killed.. .p.) If the process has already finished execution. Calling await() on the current process is a runtime error. suspend()/ resume() VCS SystemVerilog Features 26 .. (A process cannot wait for its own completion.. await() will never unblock... #1 p.. process::state estate.kill()... then await() does not block. thread_2 join_none . .

It can be called on the current process (a process can suspend itself). then it cannot resume. Effects of suspend() on Waiting Processes The following sections describe the effects of the suspend() task on process that are waiting due to different reasons. Unlike kill(). then it cannot continue execution upon resumption.. It must wait for maturity of the blocking condition. . fork VCS SystemVerilog Features 27 . Call resume() on a process that suspended itself causes the process to continue executing at the statement following the call to suspend(). the suspend() and resume() tasks act only on the process on which they are called and do not affect execution of its child processes in any way. then.Waiting on delay If a process gets suspended while waiting for a delay to mature.The suspend() task suspends the execution of the process. . upon resumption. If the process is killed or terminated while it is suspended. the process waits for the remaining delay time. Example process p. A killed or finished process cannot be suspended. The process status is marked as SUSPENDED. process::state estate.. The process status is marked as RUNNING. If the process has pending delay or waiting events. The resume() task restarts a previously suspended process.

then the process will unblock from waiting but it will not continue executing until its resume() task is called. and that method unblocks while the process is suspended.resume().Waiting on @(static_variable) or wait(static_expression) VCS SystemVerilog Features 28 .Waiting on @(SV_event) If a process gets suspended while waiting for a SystemVerilog event. . $display("I’ll resume at time 110"). . . p. then the process will unblock from waiting but it will not continue executing until its resume() task is called. This is independent of the amount of time the process spent in suspension. it must wait for 7 more time units before it can continue execution. and that event triggers while the process is suspended. #100.suspend(). If the process is suspended after 3 time units. then. The process p above must wait for a delay of 10 time units to mature. p. thread_2 join_none #3.Waiting on blocking mailbox or semaphore methods If a process is suspended while waiting for a mailbox or semaphore method to complete. upon resumption.thread_1 tf_1 tf_2 process = process::self #10.

then the previous value does not change. no matter how many times the dynamic variable or expression changes. or associative array. If the expression changes after the process thread is suspended.Waiting on @(dynamic_variable) or wait(dynamic_expression) A dynamic variable or expression is one that contains a dynamic type such as a class handle. Unlike the static variable case. no matter how many times the static variable or expression changes. The value used as the previous value for computing the change of the dynamic expression is the value of the expression at the time of the suspension. associative arrays. dynamic array. upon resumption. and so on. but @(dynamic_variable) can unblock upon resumption if the value during suspension is different from the value at resumption. using the last value as the previous value. in which the previous value gets updated every time the variable’s value changes. . dynamic arrays. @(static_variable) cannot unblock upon resumption. or a class reference using any of those. srandom() VCS SystemVerilog Features 29 . Therefore. A process waiting on a static variable or expression will not unblock while it is suspended.A static variable or expression is one that does not contain any dynamic types such as class handles. checking for a change of the static variable is done. A process waiting on a dynamic variable or expression will not unblock while it is suspended.

which allows seeding of underlying process threads. This works the same as calling srandom() directly in the process scope. Otherwise the value prints according to the base type of the enumeration. it prints “tag:value” along with the currently valid element. Limitations • The process::self.The srandom() method can be called on a process handle. only the first declared elements are printed.srandom() syntax is not supported • • Debug is not supported DPI calls are not supported Assignment Patterns Using %p The %p format specifier can be used to print aggregate expressions such as packed structures and arrays. An enumerated data type prints its value as an enumeration name if the value is valid for that type. A string data type or string literal prints its value as a string. For unions. In the case of a tagged union. while providing the flexibility of seeding a process from outside its scope. The value of each element that is a singular type is printed as follows: • A packed structure data type prints its value as an assignment pattern with named elements. Each element is printed under one of these rules. • • VCS SystemVerilog Features 30 . using the process handle. It prints the value as an assignment pattern with named elements.

20 : '{OFF. s:switch10}. VCS SystemVerilog Features 31 .switch10}. except that a null handle value prints the word null. $display("va[10]. s:switch20}} . switch20} switch_s. $display("va[int] = %0p. typedef struct packed {switch_e sw. switch_s s. OFF} switch_e.". pair_t va[int] = '{10 : '{ON. Example module top.s = %p. s:switch20}} . or virtual interface prints a pointer. s:switch10}. switch20}}. The %p format specifier can also be used to print singular expressions. initial begin $display("va[int] = %p. va[10]. in which case the expression is formatted as an element of an aggregate expression described above. 20:'{sw:OFF.".} pair_t. end endmodule : top The example above prints this: va[int] = '{10:'{sw:ON.va). class handle.va). event.". va[int] = '{10:'{sw:ON. typedef enum {switch10.s). All other singular data types print their values unformatted.s = switch10.• • A chandle. 20:'{sw:OFF. va[10]. typedef enum {ON.

]. VCS SystemVerilog Features 32 .. Note: Standard SystemVerilog restrictions on hierarchical references in alias statements and on aliasing a net or signal to itself do not apply in the VCS implementation. it is an error to use an alias statement to connect a wand net to a wor net.. See the SystemVerilog Language Reference Manual for additional information about net aliasing. For example. The same nets can appear in multiple alias statements. so that a net can belong to several aliases. Example alias net_a = net_b = net_c = net_d. The members of an alias list are signals whose bits are on the same physical nets. Syntax alias net-expr|bit-expr = alias-expr [ = alias-expr . alias net_b = net_d. Variables are not allowed in alias statements. Each member must be the same size and the nets must be of compatible types. alias net_c = net_d.Signal Aliasing An alias statement declares multiple names for the same physical net or slice of bits in a net. The statement above results in three aliases: alias net_a = net_d.

Node left. Parameterized outer classes are not supported for this feature. string name. and nested class declarations.Nested Classes The class scope resolution operator applies to all static elements of a class: static class properties. Declaring types within a class helps prevent name collisions and the cluttering of the outer scope with symbols that are used only by that class. They can also be used as the name of a type or a method call. endclass endclass // StringList::Node is different from StringTree::Node VCS SystemVerilog Features 33 . or triggered (in event expressions). enumerations. Class scope resolved expressions can be read (in expressions). class Node. unions. static methods. Like modules. right. structures. Example 1-3 Nested classes in a linked list and in a binary tree class StringList. classes are scopes and can nest. Nesting allows hiding of local names and local allocation of resources. // Nested class for a node in a linked list string name. class Node. This is often desirable when a new type is needed as part of the implementation of a class. endclass endclass class StringTree. written (in assignments or subroutine calls). Node link. // Nested class for a node in a binary tree. Type declarations nested inside a class scope are public and can be accessed outside the class. typedefs.

These directives are described in "Compiler Directives" in the SystemVerilog Language Reference Manual. This is the path by which a tool opened the file. A ’line directive changes ’__LINE__ and might also change ’__FILE__ . the expansions of ’__FILE__ and ’__LINE__ revert to the values they had before the ’include and `__LINE__ is then incremented by one as processing moves to the line after the `include. when processing resumes on the input file that contained the ’include directive. An ’include directive changes the expansions of ’__FILE__ and `’__LINE__ to correspond to the included file.".’__FILE__ and ’__LINE__ Compiler Directives The ’__FILE__ and ’__LINE__ compiler directives have been implemented in this release. The message can state the line in the source at which the problem was detected. Example 1-4 ’__FILE__ and ’__LINE__ usage $display("Internal error: null handle at %s. not the short name specified in ’include or as a tool’s input file name argument. as described below. At the end of that file. `__FILE__. line %d. VCS SystemVerilog Features 34 . ’__FILE__ and ’__LINE__ are useful in generating error messages to report problems. `__LINE__). ’__LINE__ expands to the decimal current input line number. ’__FILE__ expands to the string literal name of the current input file.

finish_addr]]).Extension to SystemVerilog $readmemb/$readmemh The following SystemVerilog $readmemb/$readmemh tasks have been extended as described in the following section: • “Loading Memories with $readmemb and $readmemh” Loading Memories with $readmemb and $readmemh The $readmemb and $readmemh tasks described in "System Tasks and Functions" in the SystemVerilog Language Reference Manual. start_addr [. start_addr [. Syntax $readmemb ("file_name". $readmemh ("file_name". memory_name [. VCS SystemVerilog Features 35 . associative arrays of packed data. the system tasks treat each packed element as the vector equivalent and perform the normal operation. for use in simulating memories at runtime. and dynamic arrays of packed data. In such cases. $readmemb and $readmemh are system tasks that allow you to load memory from a file on the disk. memory_name [. have been extended. unpacked arrays of packed data. $readmemb reads in binary and $readmemh reads in hexadecimal numbers. Reading Packed Data $readmemb and $readmemh are extended to queues. finish_addr]]). Their functionality is described in this section.

Reading 2-state Types $readmemb and $readmemh are extended to packed data of 2-state types. the file data represents the numeric values associated with each element of the enumerated type. indexes must be of integral types. VCS SystemVerilog Features 36 . address entries in the pattern file are in numeric format and correspond to the numeric values associated with the elements of the enumerated type. If a numeric value is out of range for a given type. Note: The real data type is not supported with these system tasks.g. The space for dynamic array doesn’t exist until the array is explicitly created at runtime The syntax to declare a dynamic array is: data_type array_name[]. reading proceeds the same as for conventional Verilog variable types (e. When an associative array’s index is of an enumerated type. $readmemb and $readmemh for Dynamic Data Types Dynamic Arrays A dynamic array is any dimension of an unpacked array whose size can be set or changed at runtime. such as int or enumerated types.. For 2-state integer types.When working with associative arrays. with the exception that X or Z data are converted to 0. then an error shall be issued and no further reading shall take place. integer). where data_type is the data type of the array elements. Dynamic arrays support the equivalent types as fixed-size arrays. For enumerated types.

then the required finish address is calculated and a new array is allocated and filled. The start address can be a higher-numbered address than the finish address. (for example.Initializing and Loading Dynamic Arrays • When loading a memory that has not been initialized yet. a = new[10]). For an uninitialized array and a memory file that has holes in it. • When loading a dynamic array that has been initialized. Strings. A queue supports constant-time access to all its elements as well as constant-time insertion and removal at the beginning or VCS SystemVerilog Features 37 . if the file requires a smaller or larger array than the existing array. it starts from address 10). If there is a start address specified in the $readmemb or $readmemh call for an uninitialized dynamic array. the array must be initialized with the size of the given file (for example. the first 10 elements of the array are filled with the default value for the data type for the array. Elements of the array that are not filled from the memory file are filled with default values for the data type of the array. then the array is resized to the size of the file. You can also use the @ operator to make the memory file load into the array in the reverse direction. The contents of the memory file can be loaded into the array in either ascending or descending order. • • • • • • Smart Queues A queue is a variable-size. chandles and class objects are not supported as memory elements of memories by $readmemb or $readmemh. ordered collection of homogeneous elements.

a queue of size finish address + 1. if there are more entries in the file than the finish address of the queue. • For an uninitialized queue with start address 0 and no finish address specified. The maximum size of a queue can be limited by specifying its optional right bound (last index). slicing operator syntax. but specifying $ as the array size. Thus. For an existing queue. queues can be manipulated using the indexing. and if the start address is 0. a new queue is created with the size specified by the finish address.the end of the queue. Each element in a queue is identified by an ordinal number that represents its position within the queue. with 0 representing the first. is created If the memory file is larger than the queue can hold. a new queue is created with the required size. but the queue is filled up to the specified finish address. and $ representing the last. Queues are declared using the same syntax as unpacked arrays. • • • VCS SystemVerilog Features 38 . Initializing and Loading Smart Queues • If an uninitialized queue with start and finish addresses specified is being loaded. Queue positions for which no values are present in the memory file are filled with the default values for the data type of the queue. the memory file is loaded until the end of the file is reached. an error is issued. like arrays. and equality operators. a new queue is created and filled. concatenation. For an uninitialized queue with start address 0 and a specified finish address. a new queue with a size equal to the size of the memory file is created. If the start address is greater than 0. A queue is analogous to a one-dimensional unpacked array that grows and shrinks automatically. If no finish address is specified.

and imposes an ordering. an associative array is a better option. For an existing new queue. and the index expression is not restricted to integral expressions. the queue elements that are not present in the memory file are filled with default values for the data type. For an uninitialized queue whose address file starts with an address higher than 0.• For an existing queue with start index greater than the finish index. chandles and class objects are not supported as memory elements of memories by $readmemb or $readmemh. An associative array does not have any storage allocated until it is used. When the size of the collection is unknown or the data space is sparse. For an uninitialized array and a memory file that has holes in it. Strings. it starts from address 10). (for example. only those elements within the size of the existing queue are filled. an error is issued. the first 10 elements of the array are filled with the default value for the data type for the array. You can also use the @ operator to make the memory file load into the array in the reverse direction. The data type to be used as an index serves as the lookup key. if the @ operator is trying to fill a position larger than the current size of the queue. • • • • Associative Arrays Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically. An associative array implements a lookup table of the elements of its declared type. an error is issued. VCS SystemVerilog Features 39 . If the finish address is greater than the current size of the queue. but can be of any type.

VCS SystemVerilog Features 40 . Initializing and Loading Associative Arrays Strings and class objects are not allowed as associative array indexes. array_id is the name of the array being declared. Otherwise. An index type restricts the indexing expressions to a particular type. It can be any type allowed for fixed-size arrays.The syntax to declare an associative array is: data_type array_id [index_type]. It shall be illegal for index_type to declare a type. or *. where: data_type is the data type of the array elements. index_type is the data type to be used as an index. initializing and loading of associative arrays is the same as for dynamic arrays. then the array is indexed by any integral expression of arbitrary size. If * is specified.

Many of these features are part of SV LRM 2009 (draft) and detailed descriptions for them is available in the LRM. This chapter contains the following sections: “Use Model” on page 2-40 “Overlapping Operators in Multiclock Environment” on page 2-40 “Deferred Immediate Assertions” on page 2-41 “Property Operators” on page 2-42 “Inferred Value Functions” on page 2-49 “Recursive Properties” on page 2-50 Assertions 39 .2 Assertions 1 This chapter describes the implementation of beta features for SystemVerilog Assertions.

and #-# in multiclock environments. |->.“Local Variable Initialization and Input” “Global Clocking” on page 2-52 “let Operator” on page 2-55 “Limitations” on page 2-55 Use Model You must use the –assert svaext compile time option for all the new SVA features . Note: The –assert svaext option must be used at analysis phase (vlogan) for the UUM flow. Overlapping Operators in Multiclock Environment SV 1800-2005 LRM allowed only non-overlapping implication (|=>) operator to be used in multiclock properties. if … else. This is at times difficult and restricts the usage. You can use the operators ##0. LRM 2009 relaxes this and allows overlapping operators as well. @clk1 a ##0 @clk2 b @clk1 s |-> @clk2 p @clk1 if (b) @clk2 p1 else @clk3 p2 Assertions 40 .

end Assertions 41 . and Verification Language. or it may occur in a future time step after clk1 This feature is implemented in conformance with the IEEE P18002009 Standard for SystemVerilog — Unified Hardware Design. clk3) may occur in the same time step. The syntax for Deferred assertion is: assert #0 (expression) action_block always_comb begin : b1 def_final_check: assert #0 (not_a != a). They may produce unnecessary noise in simulation reports. settled value of a given time step thereby producing single report line.Either clk 1 and clk2 (resp. when a changes. Deferred Immediate Assertions Immediate assertions used in combinational always blocks may fire on 0-width glitches. assign not_a = !a. always will execute 2x and the assertion will fire on a transient value. It triggers the simulation report on the final. Specification. always_comb begin : b1 glitch_prone_check: assert (not_a != a). In the example below. end Deferred assertions help in such cases.

logic a. and Verification Language. always_comb begin equiv_def_assert: assert #0 (a == b). end endmodule : def_assert_ex Property Operators This section describes implemented property operators implemented in conformance with the IEEE P1800-2009 Standard for SystemVerilog — Unified Hardware Design. module def_assert_ex.Immediate assertions can an also be used in non-procedural context (implicit always_comb). conc_def_assert: assert #0 (a == b). Specification.b. Weak and Strong Sequence Operators The weak and strong sequence property operators are defined as follows: weak (sequence_expr) Assertions 42 . logic a. endmodule : def_assert_ex This is equivalent to: module def_assert_ex. Immediate cover is also supported in deferred version.b.

A success occurs if there is a match or incomplete evaluation when the simulation finishes. By default. sequence_expr property is • • Weak in assert and assume Strong in cover property Implication and Equivalence Operators Implication and equivalence operators are implemented for expression and property levels: • • At the expression level expression1 -> expression2 is shorthand for (!expression1 || expression2) • expression1 <-> expression2 is shorthand for (!expression1 || expression2) && (!expression2 || expression1) • • • At the property level property1 implies property2 is shorthand for (not property1) or property2 property1 iff property2 is shorthand for ((not property1) or property2) and (not property2) or property1) Assertions 43 . otherwise a mismatch results. strong (sequence_expr) Success requires a match during simulation.

VCS supports 4 forms of until operator: weak until (Non-overlapping) strong until (Non-overlapping) weak until_with (Overlapping) strong until_with (Overlapping) Weak versions • • property_expr1 until property_expr2 is the weak non-overlapping form. Assertions 44 . property_expr1 s_until_with property_expr2 is the strong overlapping form. This form requires that property_expr2 eventually evaluates true for until to succeed. property_expr1 until_with property_expr2 is the weak overlapping form. Strong versions: • • property_expr1 s_until property_expr2 is the strong non-overlapping form. This form requires that property_expr2 eventually evaluates true for until to succeed.until Operator SystemVerilog 2009 adds the until operator.

It must have enough ticks for the range. • Note that assert property(p) has an implicit always. It may not have enough ticks for the range. s_always [constant_range] property_expr strong is true during the range. s_nexttime [N] property_expr is strong nexttime and evaluates the expression at the N-th tick. nexttime [N] property_expr is weak and evaluates the expression at the N-th tick. always Operator The always operator has two variants: • • always property_expr is weak and is true as long as there is a tick. if it exists. A clock tick must occur.nexttime Operator There are four variants of the nexttime property operator: • • • • nexttime property_expr is weak and evaluates the expression at the next clock tick. N clock ticks must occur. always [cycle_delay_const_range_expression] property_expr is weak and is true during the range. s_nexttime property_expr is strong nexttime and evaluates the expression at the next tick. Assertions 45 .

it remains low forever. #=#) is useful when a sequence needs to be followed by a property within a specified interval.Example This property sets an assumption that once reset is HIGH for 5 continuous clocks. initial rst_stays_low : assume property (reset[*5] #=# always !reset) . |=>. It may not have enough ticks for the range. It must be true in the range of ticks and must have ticks for the range. s_eventually property_expr is strong. respectively. It evaluates the expression. It is a dual operator of |-> . • seq #-# prop is the same as not (seq |-> not prop) Assertions 46 . For example. s_eventually [cycle_delay_const_range_expression] is strong. which must be true in the future. • • followed-by Operator The followed-by operator (#-#. It must have enough ticks for it to be true. The followed-by operator #=# is discussed in LRM and also below in this document. It evaluates the expression within the range of ticks in the future. eventually Operator The eventually operator evaluates an expression within a range of ticks. It has three variants: • eventually [constant_range] property_expr is weak.

In all cases. Since typical simulations complete in finite number of clock ticks. In VCS. the property always a is safety since it is violated only if after finitely many clock ticks there is a clock tick at which a is false. if a property evaluation attempt did not complete evaluation. When prop is a sequence strong(seq1) then • • seq #-# strong(seq1) is the same as strong(seq ##0 seq1) seq #=# strong(seq1) is the same as strong(seq ##1 seq1) Mixed Strength Property Reporting The concept of weak and strong operators is closely related to an important notion of safety properties. VCS has implemented a flexible means for users to interpret the result of a strong and weak operators. a failure of the property s_eventually a on a computation with infinitely many clock ticks cannot be identified at a finite time: if it is violated..• seq #=# prop is the same as not (seq |=> not prop) seq must have at least one match followed by a success of prop. For example. even if there are infinitely many clock ticks in the computation. strong and weak properties are not distinguished as to the reporting at the end of simulation. the value of a must be false at each of the infinitely many clock ticks. To the contrary. it will be reported as Assertions 47 . Safety properties have the characteristic that all their failures happen at a finite time.

• accept_on makes the property true when the expression becomes true. reject_on(expression) property_expr accept_on and reject_on can be nested within properties. abort dominates. Assertions 48 . rather than success or failure. If abort occurs simultaneous with property result."unfinished evaluation attempt". accept_on (expression) property_expr • reject_on makes the property false when the expression becomes true. If abort occurs simultaneous with property result. the user may then decide the effective outcome. abort dominates. Depending on the property. Synchronous versions are sync_accept_on and sync_reject_on. Synchronous versions are sync_accept_on and sync_reject_on. In which case: • • If simultaneous aborts occur the one at the higher level in syntax order dominates. Modeling Abort Conditions: accept_on. reject_on Abort properties model abort conditions by controlling asynchronous aborts based on sampled values of expressions.

Assertions 49 . Specification. It is obtained by applying clock flow rules to the point where $inferred_clock is called. disable expression. and enable condition. There must be a current resolved event expression when $inferred_clock is encountered or an error is issued. Returns the inferred disable expression. $inferred_disable $inferred_enable $inferred_clock and $inferred_disable are instantiated in conformance with the IEEE P1800-2009 Standard for SystemVerilog — Unified Hardware Design.Example assert property (@(clk) go ##1 get[*2] |-> reject_on(stop) put[->2]). The inferred clocking event expression is the current resolved event expression that can be used in a clocking event definition. Returns the inferred enable condition. and Verification Language. $inferred_clock Returns the expression of the inferred clocking event. Inferred Value Functions Use elaboration-time system functions to query the inferred clocking event expression. $inferred_enable is a VCS extension to the Inferred functions and not a standard LRM feature.

p). Recursive properties substitute in assertions and unfold until all unique property instances are reached (as in a tree structure with feedback references for recursion). and Verification Language. Local Variable Initialization and Input The use of local variables allows arguments of sequences and properties to serve as local variable declarations. Example property prop_always(p). endproperty is a recursive property that says that the formal argument property p must hold at every cycle. p and (1'b1 |=> prop_always(p)). This example is useful if the ongoing requirement that property p hold applies after a complicated triggering condition encoded in sequences: property p1(s. s |=> prop_always(p). local variable initializers: Assertions 50 . Operators are instantiated following the tree in postorder and loops are closed by passing handles. In this release. Specification.Recursive Properties Recursive properties are implemented in this release. endproperty Support for recursive properties is an update in conformance with IEEE Std 1800™-2005 Standard for SystemVerilog — Unified Hardware Design.

by reference for output direction. implicitly creates a local variable declaration and initialization by the actual argument. Assertions 51 . On input and inout. int b = a+2. Assign initial values in the order of the local variable declarations. int b = a+2. endproperty Local variable input and initialization are implimented in conformance with the IEEE P1800-2009 Standard for SystemVerilog — Unified Hardware Design. Can initialize by actual argument and preceding local variables in an expression. and Verification Language. … endproperty A local variable argument: • • • • Passes “by value” of actual argument for input direction. On inout and output in sequences assigns the local value to the external local variable actual arg. Can be used in recursive properties and LTL property p(local input int x). @clk (dut_y == x. property p().• • • Allow initialization of local variables in the declaration. int a = x. Specification. int a = 1. a+=1) … .

They may be used only if global clocking is defined. The syntax for the global clocking specification statement is as follows: global clocking [clocking_identifier ] clocking_event . Global Clocking Global clocking is to represent a system clock. SystemVerilog provides a system function to refer to the global clocking. and Verification Language. Specification. endclocking [ : clocking_identifier ] There can be only one global clocking block per system. The following functions are provided: Assertions 52 .This system function $global_clock returns the event expression specified in the global clocking statement. This feature is implemented in conformance with the IEEE P1800 Standard for SystemVerilog — Unified Hardware Design. The function has no arguments. This helps in writing generic assertions. and Verification Language. Past and Future Sampled Value Functions Use the global clocking system functions to access past and future shifted sampled value at the global clock tick that immediately precedes or follows the timestep at which the function is called. Specification.Support for use of local variables with property operators is an update in conformance with IEEE Std 1800™-2005 Standard for SystemVerilog — Unified Hardware Design.

Otherwise. Returns true if the sampled value of expression changed to 1 from its sampled value at the previous global clocking tick. $rose_gclk should read something like this: $rose_gclk is true whenever the sampled value of b changed to 1 from its sampled value at the previous global clocking tick. it returns false. Returns true if the sampled value of expression did not change at the previous global clocking tick.Sampling Past Value Functions Global clocking past sampled value functions report the past shifted times. The functions are: Global clocking past sampled value functions are: $past_gclk(expression) $rose_gclk(expression) $fell_gclk(expression) $stable_gclk(expression) $changed_gclk(expression) Where: $past_gclk (expression) Returns sampled value of expression at the previous global clocking tick. it returns false. Otherwise. it returns false. Assertions 53 $stable_gclk(expression) . Otherwise. $rose_gclk(expression) $fell_gclk(expression) Returns true if the sampled value of expression changed to 0 from its sampled value at the previous global clocking tick.

Otherwise. it returns false. Returns true if the sampled value of expression changes to 0 from its sampled value at the next global clocking tick. it returns false. the future value access is implemented by shifting the whole assertion by one gclk tick into the past. it returns false. Otherwise. Otherwise. Otherwise. Returns true if the sampled value of expression does not change at the next global clocking tick. Returns true if the sampled value of expression changes to 1 from its sampled value at the next global clocking tick. The future value functions are: $future_gclk(expression) $rising_gclk(expression) $falling_gclk(expression) $steady_gclk(expression) $changing_gclk(expression) Where: $future_gclk (expression) Returns sampled value of expression at the next global clocking tick. it returns false. $rising_gclk(expression) $falling_gclk(expression) $steady_gclk(expression) Assertions 54 .$changed_gclk(expression) Returns true if the sampled value of expression changed at the previous global clocking tick. Sampling Future Value Functions In VCS.

end_time for every attempt and statistics for every assertion/cover. it returns false. Limitations This section describes known limitations.$changing_gclk(expression) Returns true if the sampled value of expression changes at the next global clocking tick. assertion tracing in DVE not supported completely. While basic debug support is available with this release. let Operator Use of the let operator is facilitated when you use -assert svaext. DVE provides information such as: start_time. Assertions 55 . UCLI support for new assertions is not fully qualified. DVE also groups all signals involved in an assertion on tracing an attempt.There is no need fto enter the -assert let option. Debug Support for New Constructs Use -assert dve at compile/elab to enable debug for assertions. However the extra "hints" that are provided for SVA 2005 constructs are not available for new constructs as of now. Otherwise.

Please check with Synopsys support if there are unexpected results with cross feature behavior for these new constructs. Assertions 56 .Note on Cross Features Some of the features in new assertions have known limitations with cross feature support. Some known issues: • • –cm property_path is not available for most of the new constructs New sequence operators when used as sampling event for covergroups may not function well. Coverage. such as Debug.

“State Bin Names as States in Transition Sequences” on page 70 • “OpenVera Language Enhancement” on page 73 .4 Coverage Enhancements This chapter provides details on the following coverage enhancements: • “SystemVerilog Language Enhancements” on page 64 .“Wildcard Support in binsof Expressions” on page 73 • “Coverage Exclusion Enhancement” on page 77 .“Understanding Half-Toggle Exclusion” on page 77 1 63 .“Wildcard Support in binsof Expressions” on page 64 .“Wildcard Array Bins” on page 69 .

Specification.• “Unified Coverage Reporting Enhancements” on page 79 .“Reporting Only Uncovered Objects” on page 79 . and Verification Language (IEEE Std 1800™-2005). z.“Branch Coverage and Implied Branches” on page 92 .“Understanding Covergroup Page Splitting” on page 90 • “DVE Coverage Enhancements” on page 92 . ?) to specify ranges in the binsof expression.“Container Exclusion State Markers” on page 94 SystemVerilog Language Enhancements Wildcard Support in binsof Expressions You can use wildcards (x. (This document is referred to herein as the SystemVerilog Language Reference Manual. cross_item } 64 .“DVE Coverage Source / Database File Relocation” on page 92 . These wildcards are an extension of SystemVerilog syntax and are not part of the IEEE Standard for SystemVerilog— Unified Hardware Design. cross_item { .) SystemVerilog Syntax Extensions The following non-standard extensions have been made to SystemVerilog syntax: cover_cross ::= [ cover_point_identifier : ] cross list_of_coverpoints [ iff ( expression ) ] select_bins_or_empty list_of_coverpoints ::= cross_item .

bins_selection_or_option ::= { attribute_instance } coverage_option | { attribute_instance } bins_selection bins_selection ::= [ wildcard ] bins_keyword bin_identifier = select_expression [ iff ( expression ) ] select_expression ::= select_condition | ! select_condition | select_expression && select_expression | select_expression || select_expression | ( select_expression ) select_condition ::= binsof ( bins_expression ) [ intersect { open_range_list } ] bins_expression ::= variable_identifier | cover_point_identifier [ . 65 . open_value_range } open_value_range ::= value_range Understanding Wildcard Usage An optional keyword wildcard is included in the cross bin definition. The wildcard bins definition causes all x.cross_item ::= cover_point_identifier | variable_identifier select_bins_or_empty ::= { { bins_selection_or_option . Consider the following example: wildcard bins g12_16 = binsof( x ) intersect { 4’b11?? }. but using one wildcard consistently helps prevent confusion. z. and ? to be treated as wildcards for 0 or 1 (similar to the ==? operator). z. and ? as wildcards. You can use one or all of x. } } | . bins_identifier ] open_range_list ::= open_value_range { .

b { wildcard bins c1 = binsof(a) intersect {4’b11??}. v_b. bins a2 = { [4:7] }. bins b3 = { [9:13] }. } c : cross a. Thus. bins b2 = { [1:8] }. covergroup cg @(posedge clk). bins a4 = { [12:15] }. The following is an example of user-defined cross coverage and select expressions. sampled values containing x and/or z are excluded. // The above shows 4 cross products wildcard bins c2 = ! binsof(b) intersect {4’b1?0?}. the range of values covered by a wildcard bin is established by replacing every wildcard digit by 0 to compute the low bound and 1 to compute the high bound. } b: coverpoint v_b { bins b1 = {0}. bins b4 = { [14:15] }. bit [3:0] v_a. a: coverpoint v_a { bins a1 = { [0:3] }. // The above shows 8 cross products } endgroup 66 . bins a3 = { [8:11] }.Only bins of x whose associated values intersect values between 12 and 16 are included: 1100 1101 1110 1111 A wildcard bin definition only considers 2-state values.

cross products • a1. • a4.b1 • a1. that is. Cross definition c specifies the cross coverage of the two coverage points v_a and v_b.b3 • a1.b3 • a4. Coverage point b (associated with variable v_b) defines four bins for each possible value of variable v_b.b1 • a4.b4 67 .The example above defines a coverage group named cg that samples its coverage points on the positive edge of signal clk (not shown).b2 • a1.. Coverage point a (associated with variable v_a) defines four equalsized bins for each possible value of variable v_a. The coverage group includes two coverage points.b4 • .. a and b. one for each of the two 4-bit variables. If the cross coverage of coverage points a and b were defined without any additional cross bins (select expressions).b2 • a4. then cross coverage of a and b would include 16 cross products corresponding to all combinations of bins a1 through a4 with bins b1 through b4.

b4 • a3. This select expression excludes bins b2 and b3. c1 will cover only four cross products of • • • • a4. and a3. specifies that bin c2 should include only cross products of coverage point b that do not intersect the value range of 1000 to 1001 and 1100 to 1101.b1 • a1.b2 a4.b4 • a4.b4 This is similar to the behavior of following code: bins c1 = binsof(a) intersect {[12:15]}. c1. Thus. This select expression excludes bins a1.b4 68 . specifies that c1 should include only cross products of coverage point a that intersect the value range of 1100 to 1111. c2.b3 a4.The first user-defined cross bin.b1 • a2. a2. Thus.b4 • a2.b1 • a3.b1 • a4.b1 a4. The second user-defined cross bin. c2 covers only four cross products of • a1.

wildcard bins b3[] = (4’bx1xx => 4’bxx1x). Consider the following examples: wildcard bins b1[] = {4’b01??}. This syntax creates three bins by dividing the number of total possible transitions into three bins and putting the remaining transition in the last bin.Wildcard Array Bins Wildcard array bins are useful if you want to express array bin ranges as wildcard patterns. a separate bin is created for each value the wildcard pattern can represent. 4’b11?1}. in the first example. wildcard bins b2[] = {4’b100?. or “z”. In each of the examples above. 69 . For example. four bins are created for each of the following values: • • • • 4’b0100 4’b0101 4’b0110 4’b0111 You can also constrain bins in the following fashion: wildcard bins b3[3] = (4’bx1xx => 4’bxx1x). “x”. You can use any of the following symbols as a wildcard: “?”.

The syntax example above has a total of 64 transitions. (trans_set)} trans_set ::= trans_range_list {=> trans_range_list} | state_bin_name {=> state_bin_name} state_bin_name ::= identifier 70 . the SV extensions are not compliant with the standard SystemVerilog Language Reference Manual. section 18. illustration “Syntax 18-3’: trans_list ::= (trans_set) {. The first and second bins contain 64/3 = 21 transitions.4. the hit count for the transition bin is incremented only if the hit counts of the state bins in the sequences were incremented in the prior occurences of the sampling event.1. With this new syntax. However. Note: These extensions are allowed for both SystemVerilog and OpenVera testbenches. The syntax for specifying bins for transitions appears in the SystemVerilog Language Reference Manual. and the third bin contains 21 + 1 = 22 transitions. State Bin Names as States in Transition Sequences The syntax for specifying transition bins has been extended to allow state bin names to be used as individual states of a transition sequence. Revised SystemVerilog Syntax for Transition Bin Specifications This section outlines the extension to SystemVerilog syntax that implement this feature.

trans_bin_name Represents the name of the transition bin. coverpoint cp { bins s0 = {[0:7]} iff (x > 0). The following example illustrates the use of thes state bin name syntax: int cp . m_state bin. 71 . state_bin_name Represents the name of a state bin defined in the same sample construct. m_bad_state bin or “all” state bin.state_bin_name Represents a state bin. This name must be a user-defined state bin name. bins s1 = {[16:20]} iff (y < 3). bins newt1 = (s0=>s1). trans trans_bin_name(state_bin_name [repeated_transition_values] -> state_bin_name [repeated_transition_values] -> …) [conditional]. It cannot be the name of bad_state bin. covergroup gc @ (posedge clk). } endgroup Revised OpenVera Syntax for Transition Bin Specifications This section outlines the changes in OpenVera syntax that implement this feature.

Use the following constructs: [*constant] | [*min_constant:max_constant] The constant construct must represent an unsigned integer constant. The following example illustrates the use of the state bin name syntax: coverage_group COV1 { sample x { state s1(1).repeated_transition_values (optional) Specifies the number of times a particular value is to be repeated in a transition sequence. State bin names can be specified after their names are used in a transition bin specification. } sample_event = wait_var(x) async. The state preceding the constant must be repeated a fixed number of times. 72 . state s2(2). } There is no dependency on the order of specification of state bins and transition bins where the state bin names are used. The min_constant:max_constant construct must represent unsigned integer constants. The state preceding the constants must be repeated at least min_constant times and not more than max_constant times. trans t0sbn(s1->s2).

The following definitions apply to the preceding syntax: wildcard 73 . These wildcards are an extension of OpenVera syntax and are not part of the OpenVera Language Reference Manual: Native Testbench. [.OpenVera Language Enhancement Wildcard Support in binsof Expressions You can use wildcards (x and z) to specify ranges in the binsof expression. using the following syntax: [wildcard] state state_name ((select_expression)[logical_operator (select_expression)]) [ if (expression) ]. The cross_bin_definition defines a cross coverage bin that combines several cross products into a single named bin or equivalence class. coverage _point. Extensions to OpenVera Syntax The following extensions have been made to the OpenVera® syntax: cross cross_name (coverage_point.coverage_point_name]) { [cross_bin_definitions] [attribute_definitions] } An optional keyword wildcard is included in the cross bin definition.

ignored. 74 . state a2 (4:7). The following code provides an example wildcard usage. state_name Represents a user-specified name for the cross bin. a bit with a value of x must match a sampled value of x for a cross bin counter to be incremented. state Can be state. See the OpenVera Language Reference Manual: Native Testbench for details on bins_expression. or bad_state. The wildcard keyword treats the x value as a wildcard in the state declarations: Note: Here wildcard essentially means either 1 or 0 at the specified location. select_expression Represents a subset of bins_expression. coverage_group cg { sample_event = @(posedge CLOCK). logical_operator Represents && or ||. sample v_a { state a1 (0:3).Treats the x or z values as wildcards in the state declarations. Understanding Wildcard Usage By default.

state a4 (12:15). } cross c (v_a. wildcard state c2 (!binsof(v_b) intersect {4'b1x0x}). Sample v_a defines four equal-sized bins for each possible value of variable v_a. state b4 (14:15). state b2 (1:8). one for each of the two 4-bit variables v_a and v_b.b1 a1. cross products • • a1. then cross coverage of v_a and v_b would include 16 cross products corresponding to all combinations of bins a1 through a4 with bins b1 through b4. } sample v_b { state b1 (0). v_b) { wildcard state c1 (binsof(v_a) intersect {4'b11zx}). Cross definition c specifies the cross coverage of the two samples v and v_b. The coverage group includes two samples.state a3 (8:11). } } The example above defines a coverage group named cg that samples its coverage points on the positive edge of signal clk (not shown). Sample v_b defines four bins for each possible value of variable v_b. If the cross coverage of samples v_a and v_b were defined without any additional cross bins (select expressions). that is. state b3 (9:13).b2 75 .

. c1 will cover only four cross products of • • • • a4.b1 76 .b3 a4. b1 a4. Thus.b4 This is similar to the behavior of the following code: state c1 (binsof(a) intersect {[12:15]}).b3 a1. and a3.b2 a4.b2 a4.• • • • • • • a1. a4. specifies that c1 should include only cross products of sample v_a that intersect the value range of 1100 to 1111.b4 .b1 a4. Thus. The second user-defined cross bin.b4 The first user-defined cross bin. This select expression excludes bins a1.b3 a4. c2 covers only four cross products of • a1.. a2. specifies that bin c2 should include only cross products of samples v_b that do not intersect the value range of 1000 to 1001 and 1100 to 1101. This select expression excludes bins b2 and b3. c2. c1.

b1 a3.b4 a2. p[0] has a 0-to-1 transition and p[1] has a 1-to0 transition.• • • • • • • a1. Consider the following example: reg [1:0] p.b1 a2. This can have an impact on the overall toggle coverage score.b4 a3. Without half-toggle exclusion. #1 p = 2’b01. when you exclude an element from toggle coverage. Full-toggle exclusion for a signal p[1] gives a coverage toggle report of 50%. p = 2’b10. In this simulation.b4 Coverage Exclusion Enhancement Understanding Half-Toggle Exclusion Toggle coverage monitors each net and register for any value transition from 0 to 1 and 1 to 0. Such monitoring provides an indication of the amount of activity on each element. VCS and VCS MX exclude both transitions. which can be broken down as follows: 77 .b4 a4.b1 a4. even if one of the transitions is covered.

Half-toggle exclusion is active for x[0].p[0] p[0] p[1] p[1] 0->1 1->0 0->1 1->0 Covered Not covered Excluded (not counted) Excluded (not counted) Half-toggle exclusion gives you better control of the granularity of the transitions to be ignored. res[4]. The overall coverage score becomes 66. res[3]. as shown below: p[0] p[0] p[1] p[1] 0->1 1->0 0->1 1->0 Covered Not covered Excluded (not counted) Covered This is the BNF syntax for the half-toggle exclusion functionality: toggle_spec : mod_or_inst : mod_or_inst_name {toggle_data} mod_or_inst : MODULE | INSTANCE toggle_data : Toggle {direction} {signal_spec} direction: 0to1 | 1to0 | NULL signal_spec : name [index] index: ID r_id r_id: COLON ID | NULL This is an example of exclusion for toggle coverage: INSTANCE: top Toggle y[0] Toggle 1to0 x [0] Toggle res[3] Toggle res[4] Toggle res[5] In the above example.67% (2/3). and res[5]. 78 . full-toggle exclusion is active for y[0]. In this example. you can exclude the p[1] 0->1 transition and still cover the p[1] 1->0 transition.

as well as the summary for each top-level instance. The total coverage summary for the design is still shown. 79 .Unified Coverage Reporting Enhancements Reporting Only Uncovered Objects This section describes how URG allows you to create reports only for uncovered objects (instead of creating reports for all coverable objects). Command-Line Access URG supports a command-line option that causes only uncovered objects to be shown in the report: % urg –show brief You can use this option in combination with text mode to generate a brief text report: % urg –show text –format brief Report Changes This section describes how each report section changes when you use the -show brief option. Dashboard The dashboard report does not change.

assume the module list report looks like this: In brief mode the module list report would only show the following modules: Hierarchy The hierarchy report omits any instances that have no coverable objects in their subtree or whose entire subtree has a score of 100% (for all reported metrics). Modules with no coverable objects in them (for any reported metric) are not listed. For example.Module List Only modules with an overall coverage score less than 100% are shown. URG does not produce a comment or other indication that such an instance has been omitted. 80 .

and the subtree rooted at HNPSIDEDJI_0 is omitted because it has 100% coverage. Assume the full report looks like this: In brief mode. the only parts of the hierarchy that will be deleted from the report are those entire subtrees that have coverage scores of 100%. 81 .In other words. or that have no coverable objects in them at all. the report would show only the following modules: Note that HNUCKIDVOXUSFT_0 is omitted because it has no coverable objects.

URG generates module. Tests The tests report does not change. Module and Instance Header Sections In brief mode.Groups The groups report omits any groups that have a 100% score. Assertions Report URG lists in any of the tables only assertions that are not covered or that failed. Module Header URG lists the same header for modules. Like the hierarchy.html. including all selfinstances—even those self-instances that have 100% coverage. and group reports only for those regions that have coverage scores less than 100%. Only covers and assertions that are not covered are listed. only entire subtrees are omitted (if any). the self-instances with 100% coverage do not link to any 82 . instance. The total number of assertions is still reported the same way in asserts. However. HVP The HVP format omits any features whose subtrees are either 100% covered or which have no coverable measures in them.

including a list of all subtrees. Within each region. URG shows the detailed report for a given metric only if that metric does not have 100% coverage in that region. the module header still appears at the top of the module page because the module header contains useful information for the whole page. 83 . but its instances are reported. if a module has 100% line coverage and 50% condition coverage. If a module is hidden from the module list page. For example. Instance Header URG shows the same instance header. Note also that the condition coverage report only shows uncovered objects. URG shows all selfinstances because you can see how URG computed the scores for the module.report because their reports are not generated. Detailed Coverage Reports URG shows detailed coverage reports only for regions that do not have 100% coverage. URG generates a detailed report for condition coverage but no detailed report for line coverage.

URG shows only the lines that contain uncovered statements (“uncovered lines”). Line Coverage For line coverage reports (which provide annotated source code that shows coverable objects and which objects are not covered). along with two lines of context before and after each uncovered line. URG would not provide either this table or any toggle coverage details.URG shows the entire summary table for a metric it reports. if the module had 100% toggle coverage in all rows. For example. in which case the statement would be truncated. Showing some context is important because the coverage database does not know the extent of a statement—a statement could cross over several lines. URG provides two lines of context above and below a statement: 84 . the following summary table for toggle coverage would not omit the “1 -> 0” rows even though they are all at 100%: However.

URG shows only this information: if (some condition) if (some other condition) a <= (b ? c : ( d ? e : ( f ? g : If several uncovered lines are grouped together. if (yet another condition) begin 85 . For example: if (some condition) begin if (some other condition) begin a <= b. they are all grouped together in the report. If the statement is uncovered. rather than reporting the information in two separate sections: if (some other condition) begin a <= b. end end end The report for the above example would show the following text.if (some condition) if (some other condition) a <= (b ? c : ( d ? e : ( f ? g : ( h ? i : ( j ? k : l ))))). if (yet another condition) begin x <= y.

If a condition is not fully covered. URG still shows the complete report for that condition (and the not-fully-covered subcondition).x <= y. then URG shows the condition’s complete report (all vectors). 86 . end end Condition Coverage If a condition and all of its subconditions are completely covered (all vectors). then URG omits the report for it and its subconditions. If a condition is fully covered but one of its subconditions is not.

consider the following report:   87 .For example.

88 . with no (uncovered) subconditions.The brief report would appear as follows:   Note that URG shows the first condition because its subcondition (the second) is not fully covered. The brief report shows both the condition on line 510 and its subcondition—even though the condition itself is fully covered— because one vector of the subcondition is not covered. The condition at line 505 is omitted in the brief report because the condition was fully covered.

For example.Toggle Coverage In the detailed table. URG lists only signals that are not fully covered. consider the following full report: The brief report shows only these items: 89 .

URG lists only bins that are not covered. URG lists all of the FSM’s states. Important: The page-splitting functionality applies only to HTML reports. these FSMs are shown in the FSM summary table—with only the FSM name and its score. Understanding Covergroup Page Splitting The HTML version of the detailed covergroup report can become quite large. Only uncovered “covers” are listed. However. If an FSM is not fully covered.FSM Coverage URG omits from the report any FSMs that are fully covered (all states and transitions). which can cause difficulties when you load and view this report. Assertion Coverage URG list only assertions that have failed or are not covered. Group Report Inside a group report. URG omits the FSM it will be omitted (even if the sequence score is less than 100). Note the following page-splitting guidelines for covergroup reports: 90 . If an FSM is fully covered except for its sequences. and only its uncovered transitions and sequences. not text reports.

In this situation. URG never splits a group report. after splitting: Page for covergroup a: Group a Group instance a1 91 . URG checks the size of the current page and creates a new page if the report exceeds the value you defined with -split N. • Bin table splitting: If the bin table is so large that the previous splitting strategy is not enough to make the page fit in the page size limit. The following examples show how a report for a hypothetical covergroup a is split: Page for covergroup a. the covergroup page displays a note alerting you to the multiple-page splitting that URG has performed. When URG generates a report for any group instance. The covergroup page also contains links to the various pages. before splitting: Group a Group instance a1 Group instance a2 Group instance a3 Group instance a4 Pages for covergroup a. URG splits the bin table across several pages. Each page that is split contains a summary table of coverage information.• Instance splitting: URG splitting behavior for covergroup instances resembles code coverage splitting for module instances.

You can exclude any branches tagged in this fashion.Subpage 1: Group instance a2 Group instance a3 Subpage 2: Group instance a4 DVE Coverage Enhancements Branch Coverage and Implied Branches The DVE Coverage GUI shows implied branches in the source window (when you use dve -cov) only when you view branch coverage or are analyzing the branch metric. if you change the location of a coverage file. or source file by using information built into the coverage database at compilation and runtime. DVE Coverage Source / Database File Relocation DVE normally determines the location of a coverage database. (In this discussion. DVE displays a dialog asking you to provide the new location of the file.) However. the word "file" includes any of the preceding three items. 92 . source directory. and then attempt to load that file with DVE. The implied branches of case and if statements are indicated by MISSING_ELSE and MISSING_DEFAULT tags.

v But assume that you moved the file to this location. Moreover.v (as specified in the coverage database) is as follows: /A/B/C/foo.v Thereafter. For example. then DVE displays a dialog asking for the correct location of the file. based on database information: /A/B/E/bar. the correct location of this file: /X/Y/E/bar. assume that the location of a file foo. DVE subsequently uses both the built-in location and the new location information you have provided.v Instead of looking in /A/B. DVE searches in /X/Y. DVE compares the two locations to make a more intelligent attempt at locating the file.v If DVE cannot find the file using the default location. determines that the following location is the new root directory for design files is as follows: /X/Y Assume now that DVE performs a search for the following file. which you provided to DVE: /X/Y/C/foo. 93 . working from right to left.After you provide DVE with the new location of the file. DVE compares these two locations and.

DVE can only remember one root location directory at a time. DVE replaces any earlier root location directory with whichever new location you specify. Container Exclusion State Markers The following DVE exclusion markers indicate the exclusion state of items within a container. for example. • Partially Excluded—When some. When DVE marks a container as “Attempted” in strict mode. Note: In this discussion of “Attempted” state markers. be aware that DVE displays the “Attempted” state marker only in strict mode. the container is marked with the “Partially Excluded” state marker: The following illustration shows how the Partially Excluded marker appears in the DVE GUI in relation to the container: Partially Excluded state marker 94 . but not all. without the need to open the container to inspect the exclusion state of the individual items in the container. when you use the -excl_strict switch. of the items in a container are excluded. a module or entity. A container is a structural element that contains other data. this means that the item was already covered and cannot be excluded. that is.

the container is marked with the “Partially Excluded” and “Attempted” state markers: The following illustration shows how the Partially Excluded and Attempted state markers appear in the DVE GUI in relation to the container and its contents: Partially Excluded marker Attempted state marker • Attempted—When DVE has attempted to exclude some or all covered items in a container. the container is marked with the “Attempted” state marker: 95 . and some have been marked as attempted.• Partially Excluded and Attempted—When some of the items in a container are excluded.

The following illustration shows how the Attempted state marker appears in the DVE GUI in relation to the container: Attempted state marker The Source window also displays container exclusion information: Partially Excluded and Attempted state markers 96 .

For coverage convergence to occur. Note that using these options does not guarantee that coverage convergence will occur.5 Coverage Convergence Technology 1 This document describes the coverage convergence technology. This chapter describes all coverage-convergence-specific options. Some common user flows are also provided. This chapter also includes coding guidelines that allow you to get the most out of the coverage convergence technology. Compile-Time Options This section describes the options you use to enable the coverage convergence technology when using the VCS compiler. the constraints and coverage model need to meet certain requirements. Coverage Convergence Technology 89 . You need a special license for both compile-time and runtime usage.

coverage convergence writes automatically inferred cover groups (if any) to the directory ${SIMV_DIR}/cct_cov_gen. for a class that contains random variables and/or constraints. When you specify this option.sv Coverage Model Autogeneration Options -ntb_opts cct_cov_gen Generates a coverage model for a stimulus object—that is. Coverage Convergence Technology 90 .You also need to specify the options described in this chapter (as appropriate) when you execute simulation (that is. You can specify a different directory with the -ntb_opts cct_cov_gen_dir option. Example for OpenVera testbench: vcs -ntb -ntb_opts cct foo. Coverage Convergence Option -ntb_opts cct Ensures that the required coverage-convergence-related processing is done for all relevant coverage points. when you run simv). See “Automatic Generation a Coverage Model from Constraints” on page 96 for details on how a coverage model is inferred from constraints.vr Example for SystemVerilog testbench: vcs -sverilog -ntb_opts cct foo.

Coverage Convergence Technology 91 .Note that if the cct_cov_gen directory already exists. -cct_enable Enables coverage convergence at runtime. The names of the files created (and the names of the coverage groups themselves) depend on the names of the classes and constraints blocks in the source file./my_dir foo. specify the following command-line options when executing the simv generated by VCS. any files in that directory will be clobbered when you rerun coverage convergence with the -ntb_opts cct_cov_gen option. Example for OpenVera testbench: vcs -ntb -ntb_opts cct_cov_gen foo./cct_cov_gen) into which coverage convergence writes automatically inferred covergroups.vr Example for SystemVerilog testbench: vcs -sverilog -ntb_opts cct_cov_gen foo. Example: vcs -ntb -ntb_opts cct_cov_gen -ntb_opts cct_cov_gen_dir .vr Coverage Convergence Runtime Options To enable the coverage convergence functionality.sv -ntb_opts cct_cov_gen_dir <directory_name> Overrides the default directory (.

-cct_bias_file=<file_name> Specifies the bias file to be used for the test run. When you specify the -cct_bias_file option.The -cct_enable option is required for running coverage convergence. the -cct_enable=on_start option is automatically enabled. the targeting of holes does not start until coverage convergence determines that merely running pure random stimulus (based on constraints) is no longer resulting in increasing coverage. For the bias file to have any effect. The following arguments are optional. we recommend that you generate the bias file using the URG utility. you must enable other options (such as -cct_enable). By default. Different runs of the test can use different bias files as input. This option is also enabled automatically when you use bias file options. You can use this option when few randomize calls occurring in the test so each randomize call can be coverage-aware. The bias file specifies the coverage holes that the test should target in the current run. See “URG Options for Bias File Generation ” on page 93 for more details. Coverage Convergence Technology 92 . Although it is possible to create a bias file manually. -cct_enable=on_start Tells coverage convergence to target coverage holes from the very first call to randomize.

URG Options for Bias File Generation This section describes the URG options related to coverage convergence. Coverage convergence creates the directory if the directory does not exist. Coverage convergence writes the bias files to the . Coverage Convergence Technology 93 . such as -dir and -format./biasConfigs directory. However. The bias files are text files that represent coverage holes. if you choose to edit the bias files. You use the bias files to bias coverage convergence to target specific coverage holes. the bias files are written into the . You can use each bias file generated with the cct_gen_bias option as an input to a test run. Avoid editing the bias files by hand./biasConfigs directory. See “Understanding Bias Files and Coverage Convergence” on page 106 for more details. The URG options described in this section are in addition to other required URG options. do not deviate from the bias file format. By default./<my_dir> Overrides the default directory setting that determines where the bias files are written. These options generate bias files. -group cct_gen_bias <non-zero integer> Instructs URG to partition all the coverage holes in the input database into the specified number of bias files. -group cct_gen_bias_dir .

No Procedural Overwriting of Values Generated by the Solver Coverage convergence works by generating constraints for all the coverage holes and by enabling these “coverage constraints” during consecutive calls to randomize. then it is possible that coverage bins might not be hit. In other words. If there is procedural code (in post_randomize for example) which overwrites the values generated by the solver. Constraints and the coverage model should be in the same class. even though the solver is generating the right values for the random variables. Coverage Convergence Technology 94 . the cover points (and cover point expressions) should be the rand variables that represent the stimulus.Coding Guidelines The following sections provide coding guidelines for using coverage convergence. Further. the randomize and coverage sampling should happen on the same instance of the generator class. Constraints and Coverage Model on the Same Variables Coverage convergence works when the coverage model is on the stimulus variables.

then load a preexisting coverage database before starting the stimulus generation. to ensure that all generated values are sampled.Coverage Should Be Sampled Between Consecutive Calls to randomize The sampling event for the coverage model should be triggered between consecutive calls to randomize. Use Open Constraints In an ideal scenario. If you want to focus the solver in coverage convergence mode. An alternative is to use the @randomize sample event. you should specify only the legal (or environment) constraints when running coverage convergence. Using this sample event ensures that the cover points are sampled as soon as randomization is completed. Test constraints further constrain the legal environment to focus the solver on a specific part of the legal space. Do not use test constraints. With coverage convergence enabled. Coverage convergence will not target anything that is covered in the loaded database. Coverage Convergence Technology 95 . the solver is automatically focussed on the portion of the legal space that is covered by the coverage model.

If the structure of the constraints is changed using in-line constraints or turning constraints or randness off and on using “constraint_mode” and “rand_mode”. and automatically cover it. If partitioning does happen and coverage convergence is enabled. then the performance of coverage convergence might be compromised.Avoid Explicit or Implicit Partitioning in Constraints Coverage convergence might not work efficiently when there are explicit or implicit partitions in the constraint problems. Avoid In-line Constraints and the Use of “constraint_mode” and “rand_mode” Coverage convergence is designed to work on the static structure of the constraints and coverage. Explicit partitioning is enabled by using “solve before” constructs. Implicit partitioning is enabled when there are function calls in constraints or when object allocation is enabled. The intuition is that a better sampling of the stimulus space will exercise the design behaviors more exhaustively. then partitioning might lead to some loss of efficiency for coverage convergence: some coverage bins might be targeted but not covered. increasing the likelihood of hitting coverage goals. Automatic Generation a Coverage Model from Constraints One of the goals of coverage convergence is to extract a functional coverage model from the constraint expressions. Coverage Convergence Technology 96 .

The members of the cover group (cover points. For example: enum PktType = {Type1.The plan is to provide a first-class “contract” to the user which specifies how the coverage model is inferred and how goals are named. Type2}. A cover group will be generated for each class to contain the coverage model derived from variable declarations in the class. The following sections detail the types of cover points and crosses that will be inferred. Coverage Groups A cover group will be generated for each class by default. Cover Points Variable Coverage Each rand variable will have a cover point associated with it. rand PktType p. in any of the constraint blocks of the class. except for variables that have an unguarded set membership constraint at the top-level. PktType prevp. The cover group for the class that will contain the coverage model for variables will be called covg_<class_name>. The cover groups will contain items as described below. rand bit[7:0] x. crosses) will be annotated with comment attributes in a manner that will allow tracking back to the original constraint expressions. Coverage Convergence Technology 97 .

<cover_point_id> is a unique integer identifier for every cover point. with the bins for x having the ranges 0–3. Note that a set membership cover point will be inferred for x. But the collection of coverage for such variables will continue irrespective of the mode change. with a maximum of 64 bins. 252–255.constraint c1 { x in {0:1. . rand PktType p. but not for x or prevp. . The cover points for variables will be called covp_<cover_point_id>. The built-in function rand_mode can be used to turn off the randomness of a rand variable. 4–7. The cover point expression will be just the variable. autobinned cover points will be created for x and p. rand bit[31:0] y. Coverage Convergence Technology 98 . For example: rand bit[7:0] x. The following rules apply to the creation of bins: • • Autobinning for enum type variables. In the above example. and the bins for p having the values Type1 and Type2. 5}.. a cover point will be inferred for p. Equal volume autobinning.. The comment for the cover point will indicate details about the variable. } Here. for variables with precision 8 bits or less. The autobins for the cover points will be named by the usual naming convention for autobins.

For example: if (p || (q && r)) { . Condition Coverage (Sensitized) Each sensitizing guard condition will have a Boolean cover bin associated with it. Coverage Convergence Technology 99 . For example: if (p) { if (q) { x == y.. there will be a cover point with expressions p || (q && r) with one bin corresponding to the case when expression p is ON (or true) and one bin corresponding to the case when expression q&&r is true. The idea is to make sure that the conditional expression becomes true at least once for every implicant in the expression being true.. The cover points will be guarded by the conjunction of all the enclosing conditional guards. } } In the above example. there will be a coverpoint with the expression p&&q. } In the above example. The comment for the cover point will have the expression string. The cover point expression will be the conjunction of all the enclosing conditional guards.Branch Coverage Each conditional block will have an associated Boolean cover point.

whereas x >= 0 && x <= 5. Set Membership Coverage We will infer a cover point for constraints coded using the in and dist operations.. When the condition expression is a set expression. } Here the cover point expression will be p. and the sensitizing conditions are defined over these atomic subexpressions. 7 will be created. For membership in sets with constant members: Coverage Convergence Technology 100 . and the bins 0. 4. The comment for the cover point will have the expression string. Also. results in an inferred cover point. 1–3.. ||.Note: The subexpressions of the guard expression involving operators other than &&. ! are considered as atomic. use of set membership in complex constraints does not result in an inferred cover point. Equivalent ways of writing the same constraints using other operators might not result in an inferred coverage model. does not result in an inferred cover point. 7}) { . the condition coverage model will be generated like the set membership coverage model. For example: x in {0:5}. For example: if (p in {0:4.

• • • • • A single cover point will be created. For example: x in {0:5. 5. A bin will be created for the high value of each range. 7 will be created.A bin with the expression (range_low_expression). The functional coverage language does not allow dynamic variables (those that are not parameters to the coverage groups) to describe bin ranges. 7}. A bin will be created for the range excluding the low and high values of each range. . Coverage Convergence Technology 101 . 1–4. A bin will be created for the low value of each range. In the above example. for membership in sets with nonconstant members: • A cover point with three Boolean cover bins will be created for each of the ranges as follows: . b}. a cover point with expression x and four bins.A bin with the expression (range_low_expression + 1 : range_high_expression -1). The sample expression will be the same as the LHS value in the set membership constraint. . for nonsingleton ranges. if the resulting range is non-empty.A bin with the expression (range_high_expression). 0. Hence. For example: x in {a:5.

Note: All the cover points above will be guarded by the conjunction of all the enclosing conditional guards. One bin with value 5. y will be generated. y.In the above example. then the first two bins would not be inferred. Coverage Convergence Technology 102 . The cross will be autobinned. if a in the above example were specified as rand. The cover points and bins for x. Cross on Variables Within a Class If a class contains control variables x. Note: If the set membership range expressions use random variables. Crosses Combinations of control variables in the class. For example. a cover point will be created for variable x with the following bins: • • • • One bin with value a. y will be as described in the section on variable coverage. then no coverage bin will be inferred for that range. One bin with value range (a+1:4). One bin with value b. will be used to generate crosses. for which a variable coverage cover point is generated. We will define control variables as variables that are of enumerated types or bit-vectors that are 8 bits wide or less. then a cross x.

Coverage Convergence Technology 103 . This cross will be autobinned. } In the above example. etc. Cover points for the condition expression will be generated. 7}. In the case of set membership constraints inside conditionals. then a new cross will be created. If more control variables still remain after previous step.). For example: if (p || (q && r)) { x in {0:5. A cross for the two cover points will be generated. The crosses will be called covc_<cross_id>.The set of variables that participate in one cross is determined as follows: Control variables will be added to a cross until the total number of expected bins (product of underlying cover point bins) of the cross does not exceed 64000. file. Sampling Event A special built-in sample event called @(randomize) will be used to determine the sampling for the generated coverage groups. Cross of Condition and Constraint Expressions The sections on condition coverage and set membership described two kinds of cover points. The comment for the cross will indicate details about the crossed variables (class name. <cross_id> is a unique integer identifier for the cross. cover points for x will be generated from the set membership constraint. line. we will generate a cross of the cover points for coverage of the condition (sensitizing).

coverage is tracked for the instance and/or the cover group definition (that is. hence before @(randomize) is triggered. In fact. The @(randomize) event is triggered on all rand objects in the context being randomized. The event istriggered when an instance of this class is randomized. we will not infer a coverage model from such constraints.}) is recommended for use in the specification of test constraints. then the allocation of the objects is done before the values are populated back. If objects are being allocated by randomize. When the event is triggered.0. after the solver is done. either directly or through containment inan instance of another class being randomized. we expect the use of test constraints to be minimized after coverage driven stimulus generation is implemented. Coverage Convergence Technology 104 . Coverage Model Inference for In-line Constraints Since in-line constraints (randomize with {.This event can be used in user defined cover groups that are embedded in classes. cumulative). Contribution to Coverage Scoring The automatically generated coverage model will contribute to the coverage score by default with a weight of 1.. and values have been populated in the objects.

The VCS compiler does not compile the design when cct_cov_gen is specified (that is. Coverage Convergence Technology 105 . The language in which the coverage model will be generated is the same as the syntax of the testbench.Use Model Autogeneration of coverage model is done as part of the VCS compile step. The cct_cov_gen directory will be present wherever the simv. the class where the constraints and random variables are specified).daidir and simv files are generated by VCS compiler. vcs -sverilog -ntb_opts cct_cov_gen foo. Both System Verilog and OpenVera testbench formats are supported. The switch to enable coverage model generation is -ntb_opts cct_cov_gen. All the coverage models will be written out as text files in the cct_cov_gen directory. Then the user will include the coverage model into their testbench (using `include or #include directives) and then make sure the coverage model is instantiated in the new task for the enclosing class (that is.vr Example command line for a SystemVerilog testbench.sv It is expected that the user will first create a coverage model using the auto_gen option. Example command line for an OpenVera testbench: vcs -ntb -ntb_opts cct_cov_gen foo. The user is encouraged to view the autogenerated coverage model and make changes if required. no simv is created).

The source files (testbench files. that is. In most customer environments. such as different random seeds or configuration files and the simulation results can be observed. simv generated by VCS). each test be able to target different portions of the coverage space in order to meet the coverage goals in the shortest possible clock time. coverage convergence tries to hit coverage holes within a test. Coverage convergence seeks to automatically target coverage holes by identifying the coverage holes and directing the constraints solver to generate stimulus such that the coverage holes will be hit.Understanding Bias Files and Coverage Convergence Motivation Coverage convergence is a new technology that enables coverage convergence for testbench functional coverage. with each simulation being assigned a different random seed. The executable can then be invoked multiple times with different runtime options. Coverage convergence works at a test level. coverage models.) are compiled by VCS compiler and linked with the simulation engine to create the executable. It is desirable that with coverage convergence enabled. that is. Note that the executable is created once. where multiple copies of the tests are being executed in parallel on different machines in the farm. verification tests are run on a regression farm. design files etc. that is. cover groups. the source files (constraint. Coverage Convergence Technology 106 . What Is a “Test”? A test for the purpose of this document is an executable that can be simulated (for example.

This file can be modified by the user if needed. The different options passed with every execution lead to different behavior of the simulation. This is a file that contains a list of coverage holes which the coverage convergence engine will target when the test starts running. The bias file approach described below works best with tests using an open set of constraints and a full coverage model.transactors. This is typically done to focus the test towards some verification targets such as coverage or specific features. modules etc.) do not change with every execution. Using Coverage Convergence Bias File to Pick Target Coverage Holes The user can influence the coverage holes being targeted by coverage convergence in a test run is by using a coverage convergence bias file. From the coverage convergence point of view. Thus any invocation of the simulation executable can target any of the existing valid coverage holes. The coverage convergence bias file format is a text file representing coverage holes. the constraints in a “test” consist of the legal constraints as well as a set of test constraints that limit the solution space of the legal stimulus. a “test” should consist of a testbench with an “open” set of constraints: the constraints should represent the entire legal stimulus space. Coverage Convergence Technology 107 . Note that in many existing methodologies.

Runtime Option to Specify a Bias File The coverage convergence bias file will be passed in as a runtime argument for the test run. The test does not need to be recompiled if the bias file is changed or a new bias file is to be used for the test. If the data in the bias file is for a coverage group which cannot be targeted by coverage convergence. that is. no coverage hole will be targeted. • The holes in the coverage convergence bias file are all at a coverage group definition level. After all the holes are targeted. They will apply to all instances of the coverage group in the test. The bias file has no impact on the coverage engine and on coverage reporting. then all the data for that coverage group is ignored by the coverage convergence engine. the coverage convergence engine will read the bias file and populate its in-memory coverage hole database with the data from the coverage convergence bias file. It will only influence coverage convergence. When the test starts executing. The bias file will be read and processed by the coverage convergence runtime engine. then they will not be reactive. if more randomize calls occur. • • • • Coverage Convergence Technology 108 . The test will run as though no bias file has been specified. If the coverage convergence bias file as pointed to by the -cct_bias_file option cannot be read. using -cct_bias_file=<path_to_cct_bias_file>. for which reactivity can be applied and can be enabled. Only the coverage holes present in the bias file will be targeted. then an error will be issued the file will be ignored. Then it will systematically start targeting the holes.

The bias file will provide a guideline as to what coverage bins are targeted by coverage convergence. Since the coverage convergence bias file represents coverage bins at a coverage group definition level. Automatic Generation of Coverage Convergence Bias Files URG automatically generates coverage convergence bias files for a particular test. It is an error if N is greater than the number of coverage bins in the coverage database. Other URG options (such as –format) can also be used simultaneously to process the coverage data. The bias files will be written out in the ${PWD}/ cctBiasConfigs directory as config0. config1.• • There are no restrictions on the name of the coverage convergence bias file. The utility can be invoked as follows: $VCS_HOME/bin/urg –dir <coverage_db_dir> -group cct_gen_bias <number_of_bias_files_required> The utility will enumerate all the coverage bins in the input database files and will create N random partitions of the holes where N is supplied by the users using the num_bias_files argument. URG can be invoked on a coverage database file and will generate N bias files. For example. but coverage convergence can choose to override these guidelines in certain situations. where N is supplied by the user. config(N-1). coverage convergence will not target coverage bins that have been assigned a zero weight by the user or coverage bins belonging to disabled by the user using the collect attribute or by using coverage_control system task. it will be assumed that there is only one shape for Coverage Convergence Technology 109 .

If multiple coverage definitions are detected. The bias files generated by URG can then be used as input to tests being run in parallel. and the arguments are the random seed and the -cct_bias_file argument. Note that this means that the regression system needs to preserve the bias file used by a test in addition to other test source code and scripts. Here the inputs are the bias file and the test source code. In all the scenarios in this section. then an error will be issued and not bias files will be generated. the sequence of values generated by the solver will be exactly the same. and so on). it is assumed that the guidelines mentioned in the previous section are being followed (for example. it should fail in exactly the same manner when run on its own.every coverage definition in the input coverage database. Coverage convergence ensures that given the same inputs and the same command line arguments. coverage and constraints are on the same variables. if a test fails in the parallel regression run. Repeatability of Test Results for Parallel Regression Runs An essential requirement for the approach outlined above is that it should be possible to reproduce the results of a test run in a parallel regression environment in a stand alone manner. Usage Scenarios This section discusses coverage convergence usage in various common verification scenarios. Coverage Convergence Technology 110 . More specifically.

Running a Single Test with Randomized Configurations This scenario generally applies to multimedia devices. The object of verification is to exercise all the interesting configurations of the device. Configurations for a device are typically chosen (through randomize) a few times per test run. Coverage Convergence Technology 111 . By doing so. In the extreme case. so that the coverage data from the database can be loaded in the proper (in-memory) runtime database. config. In this scenario it is important to preload the coverage database to ensure that already-selected configurations are not chosen. The coverage database must be loaded after all the testbench components have been instantiated. and then data (possibly random) is passed through the device. the current run can focus only on uncovered bins. Running a Single Test with Randomized Transactions This scenario applies to transaction-based verification environments. This scenario is required for packet-processing devices or instruction-based processor verification.randomize is performed only once).You can load a preexisting coverage database in every scenario to screen out already-covered coverage bins. configurations are selected. in which the device has many interfaces and many modes and the device can be configured to select some interfaces and some modes. only one configuration might be selected (for example. In the testbench.

you use the bias file generation utility to bias inputs for different parallel test runs. If you assume that many transactions will be generated (randomized). and then multiple transactions are generated and passed through the device. In this scenario. Run the first batch of tests using the following commands: $SIM -cct_enable +ntb_random_seed = ${SEED} Assume that each batch contains 100 tests.randomize(). 2. 3.randomize(). status = transObj. Merge the coverage results for all 100 tests in the first batch and store the results in merged. or repeat (1000) { transObj = new. You use constraints to generate the transaction objects. then it is appropriate for the convergence heuristics to take over and apply reactive calls as needed. Perform bias file generation for the next batch of tests using the following command: Coverage Convergence Technology 112 . 1. status = transObj. Wait for first batch run to complete.The device is set in some mode. you can use the default arguments for coverage convergence. } Using a Bias File for a Parallel Regression In this scenario. 4.vdb.

1. Add the declaration for the generated cover group as part of the class member declarations. Coverage Convergence Technology 113 . If coverage has not reached your coverage goal. 2. Merge results from the second batch of runs. then repeat steps 3 through 5. Autogenerating a Coverage Model Coverage convergence can generate a coverage model from the constraints specification. Examine the generated model to determine if the model meets your expectations. 5. 7. Run the second batch of 100 tests with each test using a different bias file as an input: $SIM -cct_enable -cct_bias_file=<bias_filename> 6./cct_cov_gen/MyClass. 3. However.$VCS_HOME/bin/urg -dir merged.vr.vdb -group cct_gen_bias 100 This command distributes the remaining coverage holes into 100 bias files. Autogenerate the coverage model: vcs -ntb -ntb_opts cct_cov_gen foo. you must instantiate the coverage model that you intend to use in the simulation.vr Coverage convergence generates the model in the file .

Methodology and Flow Issues This section addresses methodology and regression execution issues. the declaration and instantiation can be done once during testbench development phase. the constraints are exactly the same for all the tests). if the name of the covergroup is MyCov and it is of the class MyClass. 6. Perform the instantiation with the following statement: MyCov = new. Make the cover group instantiation the last statement of the new task. The input Coverage Convergence Technology 114 . 4. The autogenerated coverage group must be instantiated in the new task of the enclosing class. then the coverage convergence bias file approach can be used to achieve high efficiency test runs. If the new task does not exist.For example. 5. Scenario: All Tests Have the Same Constraints and Coverage Space (Recommended) When all the tests being executed in parallel have exactly the same coverage space and the same legal stimulus space (that is. Each test should have its own bias file. then you must add the task to the cover group instantiation. then you must add to the other member declarations for the class MyClass: coverage_group MyCov. Because the name of the autogenerated cover group is deterministic.

It is desirable that the number of times the stimulus objects are randomized in a test be at least equal to the average number of coverage bins in the bias files. the Coverage Convergence Technology 115 . The test writer can then modify this template to include the hittable coverage bins. (Coverage bins whose value ranges lie outside the space of the test constraints cannot be hit). Coverage convergence may use some cycles in the test run to try to target unhittable bins. then the bias files have to be generated once and can be used for multiple regression runs. Even if all the bins in a bias file are not hittable. but remaining cycles will still target hittable coverage bins. tests have test specific test constraints which further constrain the legal stimulus space and thus also reduce the hittable coverage bins. Each test within this category can use the same bias file but with a different random seed. all it causes is less efficient utilization of resources. Scenario: Tests Are Grouped Into Categories With Each Category Having Specific Test Constraints In this scenario. As in the previous scenario. assuming test constraints remain constant across regression runs. It is possible but not efficient to use both the random seed and the bias file for every test. A bias file can be created for every category of tests. In this scenario too. the coverage database from all the tests can be merged to get the final coverage number. After all the tests are done running.database for the URG utility can be obtained by running any test and using the output coverage database. (Note that the URG does not look at test constraints when generating the bias files). they can be used again and again for repeated regression runs. The number of test runs should be used as the value for the cct_gen_bias argument for URG. The bias file should be such that all the coverage bins in the file are hittable given the test constraints for that category. Once the bias files are generated. The URG bias generation utility can be used to generate a bias file template.

This is useful in a batch mode type of regression environment. then there is no need to use a coverage convergence bias file. For this final sequential run. Then a sequential run can be used to target any remaining coverage holes. the coverage databases are merged and the merged database is used as input for the next batch of tests. the merged coverage database can be used as an input along with the fully open constraints. Coverage convergence will only target coverage bins that are not covered in the loaded database. the input database associated with a test needs to be preserved in case the test needs to be run in a stand alone mode. Coverage Convergence Technology 116 . but one batch of tests is run at one time. then a random seed can be used so that each test targets different holes. Scenario: Coverage Database Being Loaded in the Beginning of a Test Run If a coverage database is being loaded as part of the configuration for a test. Here all tests have the same constraints and coverage space. so it is already biased in some sense. After the batch is complete.coverage data from all the tests can be collected and merged. that is. If the same database is loaded in multiple tests. then it will override the bias from the loaded coverage database. If a coverage convergence bias file is used. Hence it does not make sense to use both coverage database load and coverage convergence bias file approaches for a test. Note that for repeatability purposes. holes in the bias file will be targeted even if they are marked as covered in the loaded coverage database.

6 DVE Features 1 The following features are included in this release of the Discovery Visual Environment (DVE): • • • • • • • • “Back Tracing” on page 118 “Editing the Bus Bit Range” on page 121 “Creating and Updating Counters” on page 122 “Deleting Signal Group” on page 125 “Creating Multiple Groups when Adding Multiple Scopes into Wave View” on page 126 “Visualizing X at all Zoom Levels” on page 126 “Using Filters” on page 127 “Viewing Interfaces as Ports” on page 128 DVE Features 117 .

You can close the Wave view if not needed.Back Tracing Back Tracing helps you debug a particular signal by traversing the design backwards both structurally and temporally. Open DVE and click File > Open Database. The Wave view provides a temporal view and provides information to decide which signals need further tracing. To back trace a signal 1. across gates to identify the signal that caused the X value. You can invoke the Back Trace Schematic view from any of the following windows: • • • • Waveform Schematic Path Schematic Data Pane The Back Trace Schematic consists of two panes . The Path Schematic pane is the main structural view.a Wave View pane and a Path Schematic pane. DVE Features 118 . You can use the Back Tracing feature for doing the following tasks: • • • Remove the steady state and zero delay restriction for usage Reduce the number of drivers identified as causes for an X value Interactively drive the tracing process Back Tracing in DVE is performed by Back Trace Schematic view. You can back trace an X value to its source signals. for example.

A wave group and Waveform view of the selected signal is automatically created at the current simulation time. 4. Note: Only one-level can be expanded for non-X signals. The traced signal "fetch" is added to the Wave view and its drivers are added to the Schematic view. Select the Fetch signal in the Data pane. The Back Trace Schematic view opens. The input pins of the driving cell are annotated with the values and times of the next signal transition. Select a scope in the Hierarchy pane. 3. The current simulation time and value pair are annotated on the output pins of the driving cell.The database is loaded in the Hierarchy pane. Also. The first transitions are added to the inputs to the drivers. right-click and select Back Trace Schematic. right-click and select Back Trace to fetch signal for further back tracing. DVE Features 119 . 2. Select the Reset signal in the Data Pane. The signals are displayed in the Data pane. the current simulation time is moved to the earliest time over all driver inputs.

To set the Back Trace properties 1. Select Trace Parameters or click the Trace Parameters button on the toolbar. So instead of expanding one level.Number of levels to trace .Maximum time threshold . "Miss Match". "Rising".Add traced signals to wave group . the default is the time annotated by back tracing. DVE Features 120 . .Adds the signals on the traced path to the wave group and displayed in the wave view.Controls the maximum number of levels to search backwards when automatically searching for X values. "X Value". "Match".Controls the maximum amount of time to search backward in a waveform for a value change. or "Value". so that tracing X signals can automatically trace back multiple levels following the X value over time. you can draw multiple levels and add multiple signals on the traced path to the Wave view. "Falling". The delay from an input to output will determine the time window where a value change can occur.Trace stop at . You can specify to stop at "Any Edge".Setting the Back Trace Properties The Back Trace Properties window is used to add multiple levels of trace.Controls the time to stop the trace. There are several ways to search the waveform for the specified signal. . Once a signal is selected. . The Back Trace Properties window opens that contains the following options: .

Editing the Bus Bit Range You can edit the bus bit range by simply changing either the MSB (most significant bit) or the LSB (least significant bit) of the bus. Searches signals forward/backward. 2. Stars back tracing the signal. To edit the bus bit range 1. Double-click the signal and edit the range. Controls the maximum number of levels to search backwards when automatically searching for X values. Select the bus in the Data pane or from the Wave view signal pane and select Signal > Set Bus from the menu. The Bus/Expression dialog box appears. DVE Features 121 .Using the Back Trace Schematic Toolbar The Back Trace Schematic toolbar contains the following options: Table 6-1 Options Show/Hide Wave View Trace Parameter Search Forward/Search Backward Back Trace Trace Levels Back Trace Schematic toolbar Description Shows or hides the Wave view in the Back Trace Schematic. Opens the Trace Parameter dialog. You can also drag and drop the signal in the Bus/Expression dialog.

and click on create/update. DVE Features 122 . You need to enter the correct format to save the bit range. The signal is expanded in the same order as specified in the name. In interactive mode. a[6]. You can perform all the toolbar operations on the expanded signals. define a signal ias a[0:7]. 3. Select the signal and click the “+” icon to expand. A bus will be created/updated with the selected 2 bits as a[7]. a[1:3] signal will expand to a[1]. To create and update a counter 1. If you enter a wrong range. the count result will be updated as other signals in the Wave view. with simulation going on. change the bit range to a[7:6].a[3]. The counter is supported both in post processing mode and interactive mode.a[2]. Creating and Updating Counters You can create counter signal to count the value transitions for expression or signal. Select a signal in the Data pane and select Signal > Set Expressions from the menu. The Bus/Expressions dialog box is displayed.For example. For example. Counter is treated as a special expression and you can create or update counter in the same way as you create an expression in the Bus/Expression dialog box. a warning message is displayed and the text color of the signal becomes red.

3. Type a counter name in the Name field. For example. 4. then drag and drop the signal that you want to create for expression counter from the Wave view or Source view under the Expression area. Click the Expression tab. EXP:mycount. Select the checkbox Expression is used as a counter (counting for non-zero results) to create a signal that represents the value transitions of the expression.2. DVE Features 123 .

. 5.This option is for any expression/signal.The Counter Edge radio buttons get enabled. Select any of the following Counter Edge as desired.Any Edge . Whenever the value of the expression/signal changes. counter signal counts this transaction. DVE Features 124 .

- Rising - (Default) This option is only for bit type signals. Whenever the expression/signal changes from low to high, counter signal counts the transaction. - Falling - This option is only for bit type signals. Whenever the expression/signal changes from high to low, counter signal counts the transaction. 6. Click Create. The newly created expression counter is displayed in the Bus/ Expressions dialog box. You can also view the count results in the Wave view. 7. Drag and drop the counter in the Bus/Expression dialog box to update it. For example, you can update the counter edge from “Rising” to “Any Value”. 8. Click the Update button. The counter is updated. You can view the count results in the Wave view.

Deleting Signal Group
When you delete a signal from the Wave view, it will be deleted globally. If the same signal is present in few other views, and you want to delete it, a warning message is displayed. You can either select to delete or hide the signal. Once you select to delete the signal, it would be deleted globally from all views. If you select to hide the signal, it will be hidden in the current view.

DVE Features 125

If the signal groups are deleted, save session will not have the deleted signal groups. If you hide the signal, it will be hidden when you are saving or reloading the session.

Creating Multiple Groups when Adding Multiple Scopes into Wave View
When you add the scopes to the waves, lists, or groups from the Hierarchy pane, the signal groups will be created based on their respective scopes. If you select Display signal group exclusively in the Application Preference dialog box, and add multiple scopes to Wave view, multiple scopes will be created, but only the last group will be displayed.

Visualizing X at all Zoom Levels
While debugging a design, you can visualize the X value in the Wave view at all zoom levels. To visualize X value 1. Select a signal in the Signal pane with many value changes. 2. Zoom out the signal until the waveforms are condensed to yellow bar. 3. Right-click the signal and select Highlight X Values or select Signal > Highlight X Values from the menu.

DVE Features 126

The waveform is refreshed in the Wave view and X values are displayed as red color lines for all the zoom levels.

Using Filters
You can enter the filter strings in three different styles: • • • Explicit wildcard (Default) Implicit wildcard (*) at the beginning and end of filter string Regular expression strings

The logical OR operator "||" is supported in Explicit and Implicit wildcard strings. The Filter drop-down is also available in the Data pane, Wave Viewer, and Signal Search Results Dialog. To use the filter 1. Click Edit > Preferences. The Application Preferences dialog box opens. 2. Click the Global category. 3. In the View Filters group box, select the following options, as appropriate: - Apply view filters immediately when typed - Case sensitive - Syntax - The following options comprise the Syntax drop-down list:

DVE Features 127

-Wildcards - Input the wildcard pattern to filter items. The default string is “*”. -Simple - Input the regular expression pattern to filter items. The default string is ““. -Regular Expressions - Input the simple string to filter items. The default string is “.*”.

Viewing Interfaces as Ports
You can view Interface/Modport in the Data pane when it is passed as port. You need to select the module name in the Hierarchy pane to view the port in the Data pane. You can add the interface/modport port to the Wave view, List View, or Watch view. To view the interface port in Data pane 1. Load the database in DVE. The module is displayed in the Hierarchy pane. 2. Select the module.

DVE Features 128

The interface/modport port and its type is displayed in the Data pane. The tooltip shows the interface/modport used.

3. Click the “+” button under the Variable column in the Data pane to expand the interface/modport port. The signals under the interface/modport port are displayed. 4. Right-click the interface/modport port in the Data pane and select Show Source. The source of interface/modport is shown in the Source viewer. You can also drag and drop the interface/modport from the Data pane to the Source viewer. 5. Use the Text filter or Type filter drop-down and select the Interface/ Modport port filter to filter the signals.

DVE Features 129

6. Select the interface/modport port in the Data pane and select Signal > Show Definition from the menu or right-click the signal and select Show Definition. The definition is shown in the Hierarchy pane, signals of interface/ modport port in the Data pane, and the definition location is shown in the Source viewer. 7. Drag and drop the interface/modport port from the Data pane to the Wave view or right-click and select Add to Waves.

The Interface/Modport port is shown in the Wave view.

Limitations
The following are few limitations of this feature: • Interface array port is not displayed in the Data pane.

DVE Features 130

Driver/Load, schematic/path schematic operations do not support interface port and signals of interface port. A warning message is displayed when you perform these operations. Follow signal doesn't work for interface port and signals of interface port. Modport clocking port is not shown in the Data pane.

• •

DVE Features 131

DVE Features 132

7
Viewing values in Symbolic format 1
You can view the values of signals/variables in the same radix as specified in the source code. In addition to existing radixes decimal, hexadecimal, binary, and octal, UCLI supports the symbolic radix that will enable you to view the values in the same radix. The default radix will hence be symbolic. To change the default radix from symbolic to any other (binary, hexadecimal, octal, and decimal), use the following command option:
ucli> config -radix hexadecimal

This will set the radix format to hexadecimal. If the default radix is changed to any other, you can still view the values with the default symbolic radix by passing symbolic argument to –radix.
-radix symbolic
“Viewing values in Symbolic format” 133

Example:
ucli> show –value top.dut.x –radix symbolic

“Viewing values in Symbolic format” 134

struct1_type struct1= '{1." enum {red. reg [15:0] reg16_1 =15'h8001. green} light=yellow. integer int_vec [1:0]='{15. logic16_1 'b1000000000000001 struct1 {(opcode => 'b00000001. yellow." logic [15:0] logic16_1='h8001. } struct1_type. string_sig verilog_string “Viewing values in Symbolic format” 135 . 16'h123f}. light 1 int_vec (15.21}.addr => typedef struct 'b0001001000111111)} { bit [7:0] opcode. Table 7-1 Verilog/SystemVerilog Data Types Symbolic output wire4_1 'b01xz reg16_1 'b1000000000000001 Example wire [3:0] wire4_1 = 4'b01xz.-21) string string_sig="verilog_string".The following tables list various data types’ use model and illustrate the output format for the symbolic radix. bit [15:0] addr.

BIT_ARRAY_SIG ('b00.'b01) signal char_sig : character := 'P'. ("01")). STRING_SIG {THIS IS A MESSAGE} signal time_sig : time := 5 ns.2000000000000002.Table 7-2 VHDL Data Types Example signal stdl : std_logic := 'H'. Symbolic output STDL 'bH STDL_VEC'bUX01ZWLHH signal real_sig:real := 2. TIME_SIG 5 “Viewing values in Symbolic format” 136 . CHAR_SIG P signal string_sig : STRING(1 to 17) := "THIS IS A MESSAGE". signal bit_array_sig : bit_array_type := (("00"). REAL_SIG 2. signal stdl_vec : std_logic_vector (0 to 8) := "UX01ZWLHH”.200000e+00 type bit_array_type is array (0 to 1) of bit_vector (0 to 1).

“XMR Support in Constraints” on page 141 • “Constraint Debugging and Profiling” on page 144 .“Using Constraint Profiling” on page 144 .“Solver Overview” on page 151 1 “Constraints Features” 137 .8 Constraints Features This chapter contains the following sections: • “SystemVerilog Constraint Features” on page 138 .“Array and XMR Support in std::randomize()” on page 138 .“Using the Hierarchical Constraint Debugger Report” on page 147 • “Debugging Constraint Solver Diagnostics” on page 150 .

“Using the Constraint Solver Diagnostics” on page 156 .“Classes of Constraint Diagnostics” on page 159 SystemVerilog Constraint Features The following SystemVerilog constraint features are new: • • “Array and XMR Support in std::randomize()” on page 138 “XMR Support in Constraints” on page 141 Array and XMR Support in std::randomize() VCS allows you to use cross-module references (XMRs) in class constraints and inline constraints.“Methodology for Using Unidirectional Constraints” on page 152 . VCS std::randomize() support has been enhanced to allow the use of arrays and cross-module references (XMRs) as arguments. VCS supports all types of arrays: • fixed-size arrays “Constraints Features” 138 . Here.“Search Space Reduction And Random Assignment” on page 155 .“Constraint Solver Search Space and Solution Space” on page 154 . in all applicable contexts. XMR means a variable with static storage (anything accessed as a global variable)..

and XMRs as arguments to std::randomize(). VCS supports all types of XMRs: • • • • • • class XMRs package XMRs interface XMRs module XMRs static variable XMRs any combination of the above You can use arrays. Syntax integer fa[3]. variable-sized arrays. Array elements are also supported as arguments to std::randomize().• • • • associative arrays dynamic arrays multidimensional arrays smart queues Note: VCS does not support multidimensional. success= std::randomize(fa). array elements. “Constraints Features” 139 . success= std::randomize(fa[2]). success= std::randomize(pkg::xmr).

fa[i]). VCS prints the following error message: Error-[CNST-VOAE] Constraint variable outside array error Random variables are not allowed as part of an array index. success = std::randomize(fa). i. integer fa[3]. Error Conditions If you specify an argument to a std::randomize() array element which is outside the range of the array. integer i. all arguments have rand mode ON. i. success. and none of them are randc. initial begin foreach(fa[i]) $display("%d %d\n". fa[i]). VCS prints an error message. This is consistent with how std::randomize() is specified in the SystemVerilog LRM. foreach(fa[i]) $display("%d %d\n".Example module test. and that XMR that cannot be resolved. If you specify an XMR argument in a std::randomize() call. This means that for purposes of std::randomize() calls. “Constraints Features” 140 . end endmodule When std::randomize() is called. VCS ignores any rand mode specified on class member arrays or array elements that are used as arguments.

randomize with { a. rand int i1 [3:0]. } c. “Constraints Features” 141 . You can refer to XMR variables directly or by specifying the full hierarchical name. arrays. You can use XMRs for all data types. including scalars. VCS supports all types of XMRs: • • • • • • class XMRs package XMRs interface XMRs module XMRs static variable XMRs any combination of the above Syntax constraint general { varxmr1 == 3. int x = 10.XMR Support in Constraints You can use XMRs in class constraints and inlined constraints. and class objects. pkg::varxmr2 == 4.b == 5. class cls1. where appropriate. enums. } Examples Here is an example of a module XMR: // xmr from module module mod1.

randomize() with {pkg::C::stren == STRONG. $display("%d". VCS first tries to resolve an XMR “Constraints Features” 142 . initial begin inst.x + 5. class C.STRONG} STRENGTH.rand int i2. end endmodule Here is an example of a package XMR: package pkg.x. choosing to which variable VCS binds an XMR variable) is consistent with XMR resolution in procedural SystemVerilog code. pkg::C::stren). constraint constr { foreach(i1[a]) i1[a] == mod1. endclass pkg::C inst = new.}.randomize() with {i2 == mod1. end endmodule Functional Clarifications XMR resolution in constraints (that is.}. endpackage module test. typedef enum {WEAK. import pkg::*. static rand STRENGTH stren. initial begin c1. } endclass cls1 c1 = new().

until it finds the variable.reference in the local scope. and so on. VCS errors out and prints an error message. If you specify an XMR variable that cannot be resolved in any parent scopes of the constraint/scope where it is used. If the variable is not found in the local scope. “Constraints Features” 143 . VCS searches for it in the immediate upper enclosing scope.

These features are explained in the following sections: • • “Using Constraint Profiling” on page 144 “Using the Hierarchical Constraint Debugger Report” on page 147 Note: You can use both of these reporting features at once.Constraint Debugging and Profiling VCS can generate constraint profiling reports and hierarchical constraint debugger reports during the simulation run. To run your simulation with constraint profiling on. Profiling reports also show cumulative statistics and allow you to cross-probe into the hierarchical constraint debugger reports. invoke an HMTL browser on the cstr_html/profile./simv +NTB_CSTR_DEBUG_PROFILE=1 After the simulation completes. Using Constraint Profiling You can use VCS constraint profiling reports to find out how much runtime and memory is spent on each randomize call in your testbench. For example: % firefox $cwd/cstr_html/profile.xml “Constraints Features” 144 . use the following runtime switch: % .xml file. Just add the appropriate switches to your simulation run command line.

Note that this illustration shows just the top of the report. When you use +ntb_solver_model=1. the majority of memory blowup cases are due to binary decision diagram (BDD) blowup.Figure 8-1 on page 146 shows some sample profiler results. The profiler report also shows the node count of the largest partitions (the more nodes. including randomize calls that are consuming the most time and memory. From the report. “Constraints Features” 145 . the more memory used). you can click the randomize call identifier or the partition identifier to cross-probe to its corresponding constraint hierarchical debug (trace) section.

Figure 8-1 VCS Constraint Profiling Example “Constraints Features” 146 .

xml file. “Constraints Features” 147 . invoke an HMTL browser on the cstr_html/trace. add the following runtime switch: % .xml Figure 8-2 on page 148 shows some sample hierarchical trace debugger results. Note: VCS uses SystemVerilog syntax instead of OpenVera syntax when printing constraints in the trace.Using the Hierarchical Constraint Debugger Report VCS can also generate a hierarchical constraint debugging report after your simulation run completes. For example: % firefox $cwd/cstr_html/trace. To run your simulation with hierarchical constraint debugging on. Note that this illustration shows just the top of the report./simv +NTB_ENABLE_XML_SOLVER_TRACE=1 After the simulation completes.

randomize()call. all the items are collapsed. Click a specific item to make it expand.Figure 8-2 VCS Hierarchical Constraint Debugger Report When you first bring up the HTML randomizer report. “Constraints Features” 148 . For each obj. VCS prints the: • File name and line number in your SystemVerilog or OpenVera source code where that randomize() call is made.

Avoiding Duplicate Printing of Original Constraint Set VCS does not print the original set of constraints twice when the constraint debugger or solver_trace=2 are turned ON. VCS uses color coding to identify constraint blocks and rand vars that are turned ON. test. a randomize() call inside a for loop has test. • • • Color Coding Constraint Blocks and rand vars In the randomize reports. // constraint c // “Constraints Features” 149 . // rand integer x. and different colors for those that are turned OFF. Figure 8-3 Constraint Debugging Report solving following set of constraints rand_mode = ON rand_mode = ON rand_mode = ON (from this) (constraint_mode = ON) Solver failed when rand integer y. each randomize() call has a number of constraint blocks and variables (rand vars and state vars). File name and line number of the class where each variable is defined. The default printing mode only displays the failure subset instead of both (see Figure 8-3).sv:20@1. This visit count is also referenced in the profiling tables (see Figure 8-1 on page 146). File name and line number for each variable to point to the place where it is defined. and so on.• Visit count. For example. and for each full randomize call. Runtime and memory usage for each partition.sv:20@2. // rand integer z. incremented each time the same randomize() call occurs.

“Constraints Features” 150 . 3: Print only the failure problem. 5 . You can use the +ntb_enable_solver_trace_on_failure=0. Debugging Constraint Solver Diagnostics This section explains how to use the VCS constraint solver diagnostic feature to debug testbench constraints. 7 : 11 } ) .{ ( ( } x x < 1 ) . This is useful when the solver fails to determine the minimum subset. the solver has two modes: reactive and proactive.2. 2: Print the entire constraint problem and failure subset. Use the constraint solver diagnostics feature to analyze solver performance or when a simulation timeout occurs at a randomize() call. 1: Print only the failure subset (this is the default). Other sections contain detailed explanations of the diagnostic messages and coding recommendations for the reported constraints.3 runtime option as follows: • • • • 0: Print a one-line failure message with no details. in { 3 .1. Also included is an overview of the constraint solver that provides insights into the underlying performance issues with certain constraint expressions. When performing diagnostics.

Messages that indicate the source of constraint issues. Based on the diagnostic information in the report. you can modify the constraints to prevent potential performance issues or timeouts when randomize() is called. complex Boolean expressions. The constraint solver diagnostics feature analyzes a specific set of constraint expressions that are known to have performance impacts. The diagnostic report displays: • • Specific constraints that contributed to the timeout or simulation halt. and mixed integer and register expressions. When used in the proactive mode. the constraint solver treats all constraint expression operators bidirectionally and solves for all random variables and constraints simultaneously. Solver Overview The VCS constraint solver can solve a wide spectrum of difficult problems such as algebraic factoring.In reactive mode. This set of expressions is documented in the section “Classes of Constraint Diagnostics” on page 159. The solver issues an error message when no combination of random values satisfies the specified constraints. The diagnostic report displays constraints that could cause performance issues. This behavior prevents implicit “Constraints Features” 151 . VCS issues diagnostic messages for actual constraints applied to a specific randomize() call. This problem can be caused by over-constraining the random variables. the constraint solver diagnostics are based on a pre-solve analysis. By default.

This is the recommended best practice. Example 8-1 Unidirectional Constraint class C.partitioning of constraints by the solver. “Constraints Features” 152 . as shown in Example 8-1. However. The bidirectional nature of constraints and the simultaneous solving of all random variables and constraints increases the complexity of problems handled by the solver. Control variables are random variables that allow solutions for other random variables regardless of the values assigned to them. in a CPU instruction sequence generator. you can use unidirectional constraints to improve performance. the opcode can be used as a control variable. a common problem in other industry solvers. You can reduce the complexity by using the unidirectional constraint feature to explicitly partition random variables in constraints. Use unidirectional constraints to create separate partitions for control variables.. which impacts the solver performance. Methodology for Using Unidirectional Constraints The default solver behavior does not impose implicit partitioning. This results in improved solver performance overall. For example. rand integer x. The solver takes the partition information and breaks down a single complex problem into a sequence of simpler problems. The solver then solves the random variables in the order determined by the partitions. if you run into performance issues. the solver does not over-constrain random variables or create spurious failures. As a result.

x == 2. typedef enum { T1. opcode is a control variable you can solve for first to break the solver problem into smaller subsets. constraint d1 { foreach (c [i]) { if (opcode == T1) { c[i].x == 1. you can use the $void() function: foreach (c [i]) { if ($void(opcode) == T1) { c[i].x == 2. rand C c[$].constraint c1 { x > 0. T2 } trans. “Constraints Features” 153 . rand trans opcode.x == 1.x == 1.x == 2. } endclass: C class D. } } } endclass: D In Example 8-1. } else if (opcode == T2) { c[i]. } } or use the solve-before-hard directive: foreach (c [i]) { if (opcode == T1) { c[i]. To do this. } else if (opcode == T2) { c[i]. } else if (opcode == T2) { c[i].

Constraint Solver Search Space and Solution Space For each random variable in a constraint network. the initial search space for varA has 232 values. the set of values that actually meets the constraints you specify is typically much smaller than the search space. For example. “Constraints Features” 154 . is determined by the constraints on the random variables. high} pair. To see how this works. For example. However. This set of values (the solution space). The initial search space of a random variable is equal to all possible values of the data type. the initial search space of an unsigned 32-bit variable is: {0 . the initial search space for a partition with five unsigned 32-bit variables is: (232)5 = 2160 However. the solution space is limited to the 16 values specified by the inside constraint.} solve opcode before c[i]. consider Example 8-2. the range of possible values (the search space) is represented by a {low. } If the control variable partitions do not result in sufficiently improved solver performance.232-1} The initial search space of a partition is the composite range that all random variables of the partition can fall into.x hard. create additional partitions for the non-control variables. Here.

In the second phase. In the first phase. The process of selecting a valid solution involves two phases: search space reduction and random assignment. This ensures that if a valid solution exists. the solver algorithm assigns a randomly picked value from the search space to a random variable and performs implication. constraint varA_range { varA inside {[0:15]}. the solver narrows down the search space to match the solution space as closely as possible. it is reached without being prematurely eliminated from consideration. Implication is the process of simulating the constraint network using the value assigned to a random variable to check that no constraint is violated.Example 8-2 Search Space Reduced by “in” Constraint class B. while ensuring that the values satisfy the constraints on those variables. } endclass: B Search Space Reduction And Random Assignment The goal of the constraint solver is to assign randomly selected values to random variables. “Constraints Features” 155 . while not removing any element of the solution space from the search space. rand bit[31:0] varA.

• Enabling Diagnostics You enable the constraint solver diagnostic feature using a set of runtime options or by passing a macro argument to randomize() on a per-call basis. The diagnostic report does not provide information related to constraint solver failures (for example.Using the Constraint Solver Diagnostics You can use the constraint solver diagnostic feature to troubleshoot solver performance issues. ntb_enable_solver_diagnostics The +ntb_enable_solver_diagnostics=value option enables the constraint solver diagnostics. “Constraints Features” 156 . Choosing a Display Mode There are two display modes for the diagnostic report: non-verbose and verbose. This option enables display for the entire simulation. • Non-verbose Mode—The diagnostic report displays the search space of variables to be randomized in the current partition only if at least one diagnostic message is reported. inconsistent constraints or dependency loops). You use the value argument to specify the desired diagnostic mode. Verbose Mode—The diagnostic report always displays the search space of variables to be randomized in the current partition. even if no diagnostic message is reported.

It is a good idea to run a short simulation with few randomize() calls when using this feature. • 3 — Reactive. verbose mode Select this mode if you want verbose information in reactive mode.Syntax +ntb_enable_solver_diagnostics=value where value can be: • • 0 — Constraint solver diagnostics is off (this is the default) 1 — Reactive. ntb_enable_solver_diagnostics_on_failure The +ntb_enable_solver_diagnostics_on_failure option enables the constraint solver diagnostics and reports diagnostic information only when the solver times out. verbose mode Select this mode if you want verbose information in proactive mode. “Constraints Features” 157 . Note: Solver diagnostic output is verbose. • 4 — Proactive. non-verbose mode Select this mode if complex constraints exist and you want to check for expressions that have potential performance impact. • 2 — Proactive. non-verbose mode Select this mode if constraints are solved successfully but the solver performance is unacceptable.

Printing of diagnostic information starts only when a solver timeout occurs. Syntax +ntb_solver_diagnostics_filename=filename “Constraints Features” 158 . non-verbose mode Diagnostic behavior is the same as the +ntb_enable_solver_diagnostics=1 option (reactive.Syntax +ntb_enable_solver_diagnostics_on_failure=value where value can be: • • 0 — Constraint solver diagnostics is off (this is the default) 1 — Reactive. • 2 — Reactive. Printing of diagnostic information starts only when a solver timeout occurs. verbose mode) except in the printing of the diagnostic information. Use the +ntb_solver_diagnostics_filename option to specify a file for storing the diagnostic information. verbose mode Diagnostic behavior is the same as the +ntb_enable_solver_diagnostics=3 option (reactive. Saving Diagnostic Reports ntb_solver_diagnostics_filename By default. VCS displays diagnostic information on standard I/O. non-verbose mode) except in the printing of the diagnostic information.

the diagnostic information reported for each constraint is organized and displayed in the following four sections: • • • • Diagnostic message Variables (random and non-random) involved in the reported constraint Reported constraint Search space for random variables involved in the current partition Classes of Constraint Diagnostics The constraint solver diagnostics target a set of specific constraint expressions that are known to have performance impacts. Each of these constraint expressions. • • • “Operator that Splits Value Ranges Resulting in Sparse Solution Set” on page 160 “Low Probability of a Successful Solution—Factorization of a Constant” on page 161 “Relational Operator On The Result Of A Shift Operation— Behavior of Expression” on page 163 “Constraints Features” 159 . and possible solutions are discussed in the following sections.In the report. the corresponding diagnostic messages.

Operator that Splits Value Ranges Resulting in Sparse Solution Set In Example 8-3. Example 8-3 Operator Splits Value Ranges class modulus. // rand_mode = ON constraint residue // (from this) (constraint_mode = ON) { ( ( base % 621 ) == 0 ) . The probability of finding a solution is very low (1/621). rand bit [64:0] base. and the size of the resulting range is small {{0:0}}. constraint residue { base % 621 == 0. rand bit[64:0] base. This causes a solver timeout. the result of the modulus operation is constrained to a singleton value. } *** The search spaces for the random variables are: base: (000000000000000000000000:00000001ffffffffffffffff) *** “Constraints Features” 160 . } endclass: modulus Diagnostics Report MSG 3: There is a low probability of a successful assignment based on the existing values of the operand. The divisor is large (621).

if the range of possible values of the RHSExp is small.Changing the Size of a Divisor In Example 8-4. “Constraints Features” 161 . the solver may not be able to find values for varA and varB such that varA*varB is in the range of the RHSExp. constraint factorization { varA * varB == varC. Example 8-5 Factorization of a Constants class A. rand bit [3:0] res. Consider this next example (Example 8-5). varB. rand bit [32:0] varA. constraint residue { base % 621 == res. or if the RHSExp is a constant. varC. //solve varA before varC. } endclass: B Low Probability of a Successful Solution—Factorization of a Constant For constraint expressions in the form varA*varB == RHSExp. rand bit [64:0] base. either decrease the size of the divisor or expand the options in the RHS to increase the probability of finding a solution. This can happen when VCS solves for random variables in the RHSExp before it solves for the random variables in the multiplication operator. varA > varB. Example 8-4 Changing Size of Divisor class B.

} *** The search spaces for the random variables are: varA: (0000000000000001:00000001ffffffff) varB: (0000000000000000:00000001fffffffe) varC: (0000000000000000:00000001ffffffff) *** Specifying Solve Order for Random Variables In Example 8-6. if varC is solved first. the probability of finding a solution that satisfies the constraint varA*varB == varC is low. rand bit[32:0] varA. varC. Example 8-6 Specifying Solving Order for Random Variables class B. In the absence of the solve-before constraints.//solve varB before varC. // rand_mode = ON rand bit[32:0] varB. varB. In this case if you add the solve-before constraints. Example 8-5. Diagnostic Report MSG 14: The expression with the multi-node causes problems. “Constraints Features” 162 . the constraint solver solves the two operands of the multiplier (varA and varB) before varC. the probability of finding a solution for the constraint varA*varB == varC is exceedingly low. // rand_mode = ON rand bit[32:0] varC. this situation causes a solver timeout. rand bit [32:0] varA. } endclass: A In. // rand_mode = ON constraint base_and_limit // (from this) (constraint_mode = ON) { ( ( varA * varB ) == varC ) .

solve varA. ==) forces a very specific value for the result of the shift operation. Relational Operator On The Result Of A Shift Operation—Behavior of Expression A shift operation (for example. varB before varC. the probability of finding a solution increases. ((window_shift+window_size) < 30). } endclass: B In Example 8-6. varA > varB. } “Constraints Features” 163 .constraint factorization { varA * varB == varC. the probability of finding a solution is extremely low and results in a solver timeout. mask == (((1<<window_size)-1) << window_shift). (window_shift > 4). rand bit [28:0] mask. Example 8-7 Relational Operator on Shift Operation Result rand integer window_size. //solve window_size. constraint use_window_params { (window_size > 0). varC. WIth this change. window_shift. Consider this next example (Example 8-7). the solve-before directive specifies that the varA and varB multipliers be solved before the random variable on the RHS. In this case.window_shift before mask. <<) that fans out to a relational operator (for example.

window_shift. window_shift before mask. } endclass: B “Constraints Features” 164 . mask == (((1<<window_size)-1) << window_shift). rand bit[28:0] mask. solve window_size. the probability of finding a solution that satisfies the constraints is extremely low. the probability of finding a solution is 23/229 (almost zero). constraint use_window_params { (window_size > 0). rand integer window_size. // rand_mode = ON constraint use_window_params // (from this)(constraint_mode = ON) { (mask == (((1 << window_size). (window_shift > 4).1)<< window_shift)). Example 8-8 Using solve-before Directive class B.In Example 8-7. the last constraint combines random shift operations to match a random mask. If a random selection for the mask value results in only one digit set to 1. // rand_mode = ON rand integer window_shift. // rand_mode = ON rand integer window_size. if mask is solved first and results in a single digit set to 1. ((window_shift+window_size) < 30). Diagnostics Report MSG 19: The shift node fans out arithmetic/relational operators which may have a low probability of success. rand bit [28:0] mask. } Using the solve-before Directive In Example 8-8.

the solve-before directive specifies that the shift amount be solved before the mask.In Example 8-8. “Constraints Features” 165 . This ensures that the value of mask is calculated rather than randomly assigned.

“Constraints Features” 166 .

9 Parallel VCS Parallel VCS (PVCS) takes advantage of the computing power of multiple processors in one machine to improve simulation turnaround time Use the following Parallel VCS options in a simulation: • • • • • Design profiling and simulation Assertion profiling and simulation Toggle coverage Parallel functional coverage VPD dumping 1 Parallel VCS 165 .

Parallel VCS 166 .Parallel VCS Options You use the VCS -parallel option to invoke parallel compilation. sva[=NCONS] Enables Parallel SVA and with NCONS specifying the number of parallel SVA consumers.. fc[=NCONS] Enables Parallel Functional Coverage and with NCONS specifying the number of PFC consumers. vpd[=NCONS] Enables Parallel VCD+ Dumping and specifies the number of parallel VCD+ consumers. profile_value Enables value-based design level profiling. profile Enables design and assertion level profiling. tgl[=NCONS] Enables Parallel Toggle Coverage and specifies the number of parallel toggle coverage consumers. Note: this option is available at compiletime only. The syntax is: vcs -parallel [+options | +option[_only] [-o PVCS_executable_name] [+option(s)] design=FILENAME Enables all parallel VCS options and specifies the name of the partition configuration file. show_features Shows enabled PVCS features.

See “Profiling a Serial Simulation” on page 9-175. The VCS profiler tells you the subhierarchies in your design that use the most CPU time.vpd_sidebuf=MULT Sets the size of PVPD side buffer to MULT times the size of the main buffer. It can be used with any PVCS option and any other PVCS options can follow _only. See “Specifying Partitions” on page 9-176.pdaidir. Specify the partitions in the PVCS configuration file. Parallel VCS 167 . The default path name is simv. PVCS-specific data is stored in a directory executable_name. _only Conserves processor resources by enabling only the processing of the PVCS option specified. to enable the design and vpd options enter: vcs -parallel+design_only=FILENAME+vpd [-o PVCS_executable_name] Using the VCS -o option to specify the simulation executable binary filename allows work on multiple simultaneous PVCS compiles and runs.pdaidir. Compile and simulate your design using the conventional serial mode (compiling and simulating the design on one processor). _only must immediately follow the -parallel VCS option. Use Model for Design Profiling and Simulation The use model for PVCS is as follows: 1. For example. 2. Run the VCS profiler during simulation.

See “Design Simulation” on page 9-169. additional steps follow: 5. Run the PVCS profiler. 8. See “Profiling a Parallel Simulation” on page 9-177. and/or the PVCS fc option for functional coverage. See “Examining the PVCS Profiler Results” on page 9-179. Run parallel compilation specifying the PVCS tgl option and coverage metric options for toggle coverage. If you wish to increase the performance gains from PVCS. These results could call for you to reorganize you partitions or your Verilog source code. Parallel VCS 168 . 6. 2. Examine the PVCS profiler results. run parallel compilation and simulation over again. See “Design Simulation” on page 9-169. Run parallel simulation. 7.. Run parallel compilation specifying the sva option. Run parallel simulation again and this time collect data for the PVCS profiler. Use Model for Assertion Simulation 1. 4. specifying the PVCS configuration file. After making the changes called for by the results. You can optionally specify the number of consumers for each. Use Model for Toggle and Functional Coverage 1. Run parallel simulation.3. 2. Run the simulation to generate coverage results. Run parallel compilation.

Generate coverage result reports. 2. Run parallel compilation specifying the vpd option. Parallel VCS 169 . Running Parallel Simulation Parallel VCS (PVCS) takes advantage of the computing power of multiple processors to improve simulation turnaround time You can generate results for one of all the following Parallel VCS options in a simulation: • • • • • Design simulation Assertion simulation Toggle coverage Functional coverage VPD file generation Design Simulation Once you have profiled your design and created a partition configuration file as described in the previous chapter. Run the simulation to generate the VPD file. you can simulate only the design or simulate the design with other PVCS options. Use Model for VPD Dumping 1.3.

1. Compile using the PVCS -parallel option and other PVCS and VCS options.
vcs filename(s).v -parallel+(design | design_only)=partition_filename.cfg parallel_vcs_options vcs_options

2. Run the simulation with VCS and PVCS run-time options.
simv

Assertion Simulation
You can process only assertion level results or assertion level results along with other PVCS options. 1. Compile using the PVCS -parallel option, the assertion compilation option or options, and other PVCS and VCS options.
vcs filename(s).v -parallel+[sva[=NCONS]] [-ntb_opts] [ parallel_vcs_options vcs_options

2. Run the simulation with VCS and PVCS run-time options.
simv

Toggle Coverage
Generate results for only toggle coverage or toggle coverage along with other results by compiling the design with PVCS options and VCS coverage metrics options. You can use the +count option to report total executed transactions. After generating coverage results, you can examine them using the Unified Report Generator. tgl[+count] Report total executed transactions.
Parallel VCS 170

1. Compile using the PVCS -parallel option, coverage option or options, and other PVCS and VCS options.
vcs filename(s).v -parallel+tgl[=NCONS] -cm tgl [parallel_vcs_options] [vcs_options]

2. Run the simulation to generate coverage results.
simv -cm tgl [vcs_options]

3. Generate coverage result reports:
urg -dir coverage_directory.cm urg_options

Example In this example, toggle coverage results only are generated and the URG report is produced in the default HTML format.
% vcs -cm_tgl mda -q -cm_dir pragmaTest1.cm -cm tgl -sverilog -parallel+tgl=2 pragmaTest1.v % simv -cm tgl % vcs -cm_pp -cm_dir pragmaTest1.cm % urg -dir pragmaTest1.cm

Parallel VCS 171

Results can then be examined in your default browser.

Functional Coverage
Generate results for only functional coverage or functional coverage along with other results by compiling the design with PVCS options and VCS coverage metrics options. After generating coverage results, you can examine them using the Unified Report Generator. 1. Compile using the PVCS -parallel option, coverage option or options, and other PVCS and VCS options.
vcs filename(s).v -sverilog -parallel+fc[=NCONS] [parallel_vcs_options] [vcs_options]

2. Run the simulation to generate coverage results.
simv

3. Generate coverage result reports:

Parallel VCS 172

urg -dir coverage_directory.cm urg_options

Example In this example, functional coverage results only are generated and the URG report is produced in the default HTML format.
% % % % % vcs iemIntf.v -ntb_opts dtm -sverilog -parallel+fc=2 simv -covg_cont_on_error $urg -dir simv.vdb cat urgReport/gr*

Results can then be examined in your default browser.

VPD File
You can enable Parallel VCD+ Dumping and specify the number of parallel VCD+ consumers using the PVCS vpd option.

Parallel VCS 173

1. Compile using the PVCS -parallel option with the vpd[=NCONS] option, and other PVCS and VCS options.
vcs filename(s).v -debug_pp -parallel+vpd[=NCONS] [parallel_vcs_options] [vcs_options]

2. Run the simulation.
simv

You can post-process the results with the generated +vcd database. Example In this example, a VCD+ file with three specified consumers is generated.
% vcs -debug_pp -parallel+vpd=3 design.v % simv

Profiling a Simulation
You can profile your PVCS simulation to ensure efficient use of resources. This chapters details the profiling process. It contains the following sections: • • • • Profiling a Serial Simulation Specifying Partitions Profiling a Parallel Simulation Running PVCS Examples

Parallel VCS 174

Profiling a Serial Simulation
You can profile your simulation to determine if it is a good candidate for parallel simulation and identify partitions to use. You do this by telling VCS to run its profiler during simulation with the +prof compile-time option.
vcs +prof filename(s)

The VCS profiler tells you, among other things, what module instances use the most CPU time. The CPU time percentages are for the instance and all instances hierarchically under the instance. The CPU time percentage thus represents the subhierarchy in which the instance is the top-level instance. The VCS profiler writes its profile information in the vcs.prof file in the current directory. Look at the INSTANCE VIEW section in this file. This section, or view, tells you the percentage of CPU time used by each subhierarchy. Figure 9-1 shows this view. Figure 9-1 Instance View in a vcs.prof File

========================================================== INSTANCE VIEW ========================================================== Instance %Totaltime top (1) 100 top.A1 (2) 30 top.A2 (3) 30 top.A3 (4) 30 ----------------------------------------------------------

The subhierarchies that use the most CPU time are good candidates for PVCS partitions. In Figure 9-1 you would use separate partitions for the subhierarchies.

Parallel VCS 175

Specifying Partitions
The -design option requires a partition configuration file. You specify the partitions in the PVCS configuration file using the following syntax:
partition {hierarchical_name(module_identifier),...} ; partition {hierarchical_name(module_identifier),...} ; partition {hierarchical_name(module_identifier),...} ; . . .

The syntax is as follows:
partition

The keyword that specifies that what follows are the contents of one partition.
hierarchical_name

The hierarchical name of a Verilog module instance that is the top-level instance of the subhierarchy that you want to simulate as a partition.
module_identifier

The name of the module definition that corresponds to the toplevel instance. All parts of the design not covered in any of the specified partitions together form an implicitly defined master partition. The userspecified partitions are called slave partitions. Example 9-1 PVCS Configuration File

In this example, there is a separate line for each partition. Each hierarchical name for a top-level module instance must be followed by its module name in parentheses. You can specify more than one subhierarchy in a partition.
Parallel VCS 176

Parallel VCS wrote the data files that the PVCS profiler needs to report on the parallel simulation.partition {top. partition {top. blanks. and comments. Its syntax is as follows: Parallel VCS 177 . Example 9-2 A Free Format Configuration File You can also enter a free format of the specifications in a configuration file entering new lines.bus1 (MyBus).A1(A1)}. Note: You can use the Verilog comment syntax to comment your partition file. partition {top. see the VCS User Guide.cpu (CPU) }. partition { top.A2(A2)}. For more information on creating configuration files. top. The syntax for this command line is as follows: simv -parallel+profile [VCS_runtime_options] Parallel Profiling Options If you entered the profile option on the simv command line. // two instances per partition partition { top.bus2 (MyBus) } /* one instance per partition */ Profiling a Parallel Simulation Run the simulation by entering a command line with the name of the master executable (by default named simv) and runtime options. You start the PVCS profiler with the pvcsProfiler command.A3(A3)}.

The default height is 250. Parallel VCS 178 . The default argument is 1.pvcsProfiler [profileDumpDir=simvName. The default width is 1000. The directory is the name you specified for the simulation executable binary file with the extenstion . the profiler does not make this calculation or produce the graphs. doTimeProfiling=1|0 Calculate the time accumulation and produce the graphs. Use profileDumpDir to specify the directory containing the dump files that the profiler reads.pdaidir. By default the profiler creates the ppResults_0 directory and writes these files in this directory. If the argument is 0. the profiler does not make this calculation. graphImWidth=integer Width of the full size graphs in pixels. graphTnHeight=integer Height of the thumbnails size graphs in pixels.pdaidir. The default argument is 1. graphImHeight=integer Height of the full size graphs in pixels. The default height is 1000.If the argument is 0. The default path name is simv.pdaidir] [doTimeProfiling=1|0] [doToggleProfiling=0|1] [graphImHeight=integer] [graphImWidth=integer] [graphTnHeight=integer] [graphTnWidth=integer] [lowerSimTimeBound=float] [runVersion=string] [toggleCutOff=float] [upperSimTimeBound=float] [-help] These arguments and properties are as follows: profileDumpDir=simvName. doToggleProfiling=0|1 Calculate the partition port toggle counts and produce the high count listing.pdaidir The PVCS profiler writes HTML files that display profile information about the master and slave simulations.

upperSimTimeBound=float A floating point number for the simulation time when profiling stops. The default argument is 1.html file (as viewed in a regular web browser): Parallel VCS 179 . -help Displays the valid properties and their definitions. The default argument is 1e+100. The default argument is 0.0. With this property the profiler creates the ppResultsstring directory. runVersion=string By default the profiler creates the ppResults_0 directory in the current directory and writes its output HTML files in this directory. If you want a different name for this directory. The default width is 250.html. lowerSimTimeBound=float A floating point number for the simulation time when profiling starts. By default it writes it in a directory named ppResults_0 in the current directory. enter this property.graphTnWidth=integer Width of the thumbnails size graphs in pixels.0. Examining the PVCS Profiler Results The main results file that the profiler writes is named results. toggleCutOff=float Specifies that the port toggle count cutoff for a partition is equal to this percentage of highest toggle count. The following is an example of a results.

html File Click here to see how to read the graphs Click on a graph to see a larger image of the graph The results.html is a hypertext link to an HTML file with a larger image of the graph. Parallel VCS 180 .html) Each image in results.Figure 9-1 results.html file contains four graphs: • • • • The Processor Segment Totals (graph1.html) The Active PVCS Features (graph4.html) The Processor Delta Time Totals (graph2.html) The S1 Balance Distribution (graph3.

Figure 9-2 A Good Processor Segment Totals Graph Parallel VCS 181 . showing a balanced design with a good deal of parallelism.There is a link to the howtoInterpretGraphs. The following are a series of examples of these graphs that show different results from the PVCS profiler. The first three graphs are from a design where the profiler results are good.html file that explains how to interpret the graphs. Examples of Good Parallelism This Processor Segment Totals graph shows that each partition is doing the same amount of work.

indicating good parallelism. Parallel VCS 182 . which is good. Figure 9-3 A Good Processor Delta Time Totals Graph In Figure 9-4 the bars are all to the right.A delta is a set of events in one or more partitions that cause subsequent simulation events in other partitions. Figure 9-3 shows only two deltas. where each partition did its work in the same delta. Delta d0. and d1. in which the design generated the clock signal.

Parallel VCS 183 . are doing a significant amount of waiting for events in other partitions. Some partitions. Figure 9-5 shows that the partitions are not doing the same amount of work.Figure 9-4 A Good S1 Balance Distribution Graph Examples of Uneven or Bad Parallelism The next three graphs are from a design in which the amount of work done by the partitions is uneven or unbalanced. as indicated by the dark color at the top of their bars.

which is good.Figure 9-5 An Uneven Processor Segment Totals Graph Figure 9-6 shows a small number of deltas. but also indicates that the partitions are doing different amounts of work. Parallel VCS 184 .

Figure 9-6 An Uneven Processor Delta Time Totals Graph Figure 9-7 shows that the bars are more to the left. indicating less parallelism. Parallel VCS 185 .

causing each partition to wait for events in the other partitions. Clock signal values propagate from the output of one partition to the input of another.Figure 9-7 An Uneven S1 Balance Distribution Example of a Design in Need of Clock Signal Analysis The next four graphs are from a design in need of the clock signal optimization. Parallel VCS 186 .

Figure 9-8 Clock Signals Processor Segment Totals Graph Figure 9-9 shows Partition A3 has a #1 delay before its activity Parallel VCS 187 . but they are spending much of their time waiting for events in other partitions.Figure 9-8 Shows that the partitions are doing the same amount of work.

Parallel VCS 188 .Figure 9-9 Clock Signal Processor Delta Time Totals Graph Figure 9-10 show workloads are balanced. but partition A3 does not execute in parallel with A1 and A2.

Figure 9-10 Clock Signal S1 Balance Distribution Examples of Worst Case Scenario The next four graphs are from a design in which the partitions get their clocks together. but they are spending most of their time waiting for events in other partitions. Figure 9-11 Shows that the partitions are doing the same amount of work. Workloads are balanced. Parallel VCS 189 . but the partitions do now execute in parallel. This example is slower than a serial run.

Parallel VCS 190 .Figure 9-11 Clock Signals Processor Segment Totals Graph Figure 9-12 shows that all the work for each partition is done in a different delta.

indicating that there is no parallelism in the design.Figure 9-12 Clock Signal Processor Delta Time Totals Graph Figure 9-13 shows the bars completely to the left. Parallel VCS 191 .

Figure 9-13 Clock Signal S1 Balance Distribution Running PVCS Examples Included in your installation is a design example and suite of scripts that allow you to perform serial / parallel performance comparisons on your system and profile the results. The tests include: • • A serial run A parallel run Parallel VCS 192 .

Tue Oct 10 10:13:11 PDT 2006 Parallel VCS 193 .A run in which a clock is passed from partition to partition causing non-parallel execution Please contact VCS Support if you are looking for these examples.parallel for the wallclock time taken for parallel simulation as shown below. Examine DATE.An unbalanced workload parallel run . Run the script run_balanced. 2.A run with a delay in a partition causing one partition not to run in parallel with the other two partitions . 1. 2. Run the script run_serial. Examine DATE.csh .A balanced workload parallel run . Tue Oct 10 09:59:22 PDT 2006 Tue Oct 10 10:00:45 PDT 2006 Parallel Run Time The balanced parallel run example allows you to view wallclock time for comparison with the serial run.serial for the wallclock time taken for serial simulation as shown below. Serial Run Time The serial run example allows you to view wallclock time for comparison with the parallel run.• Profiler runs .csh . 1.

2.A3 (1) (2) (3) (4) 100 30 30 30 ---------------------------------------------------------- Parallel Runs +define+BALANCED This example is the best-case scenario. Run the script run_balanced_prof.html as shown in Figure 9-15. 2.A2 and top.Tue Oct 10 10:13:42 PDT 2006 Profiler Runs Serial Run to Identify Partitions This is example of a serial run used to identify partitions.A3 are candidates for partitions. 1. top. Parallel VCS 194 .A1. as shown in Figure 9-14.prof to see that instances top. Examine the output in the ppResults_balanced directory by opening the file results.csh .A1 top. The script for the serial profiler run is run_serial_prof.csh . Figure 9-14 Instance View from a Serial Run ========================================================== INSTANCE VIEW ========================================================== Instance %Totaltime top top.A2 top. 1. Examine the INSTANCE VIEW section in vcs.

the Processor Delta Time Totals Graph shows two deltas. d0. the Processor Segment Totals graph shows that each partition is doing the same amount of work and the partitions receive their clocks together. double-click on a graph in your browser to view the results in a full-screen.Figure 9-15 Balanced Parallel Run Partitions receive clocks together. and d1. Partitions have same amount of activity. On the right. where each partition did its work in the same delta and has the same amount of activity. Parallel VCS 195 . the Balance distribution graph shows that workloads of the partitions are balanced and execute in parallel. In he center. • • +define+UNBALANCED In this parallel run unbalanced workloads hinder performance. In this example: • On the left. in which the design generated the clock signal. Workloads of the partitions are balanced and execute in parallel. To view details.

Some partitions are doing a significant amount of waiting for events in other partitions. On the right.1. the Processor Delta Time Totals Graph. Partitions run in parallel. workloads are unbalanced.html as shown in Figure 9-16. Examine the output is in the ppResults_unbalanced directory by opening the file results. the Balance distribution graph shows that partitions execute in parallel.csh. but the workloads are unbalanced. 2. shows uneven processor delta time. The center graph. but Partitions have differing amount of activity. In this example: • The left chart. indicating uneven work distribution among the partitions. • • Parallel VCS 196 . Figure 9-16 Unbalanced Parallel Run Partitions get clocks together. the Processor Segment Totals graph shows that the partitions are not doing the same amount of work. Run the script run_unbalanced_prof.

In this example: • The left chart. Partitions have same amount of activity. Hence workloads are balanced. Figure 9-17 shows Partition A3 with a #1 delay before its activity. Parallel VCS 197 . Figure 9-17 A Delay in a Partition Partitions get clocks together. Examine the output is in the ppResults_delay directory by opening the file results. but partition A3 does not execute in parallel with A1 and A2.html.csh. 1. the Processor Segment Totals graph shows that each partition is doing the same amount of work but are spends significant amounts of time waiting for events in other partitions. Run the script run_delay_prof. 2.+define+BALANCED+DELAY This is an example of a delay in a partition causing one partition not to run in parallel with the other two partitions. Partition A3 has a #1 delay before its activity.

A2. shows the partitions have the same amount of activity. and A3 gets its clock from A2. and will be slower than the serial run. the Balance distribution graph shows that workloads of the partitions are balanced. 2. Run the script run_clock_prof.• The center graph. but partition A3 does not execute in parallel with A1 and A2. • +define+BALANCED+CLOCK This is an example of a clock being passed from partition to partition causing non-parallel execution. This is the worst-case scenario. but none of A1. 1. Figure 9-18 A Clock Passed from Partition to Partition Partitions get clocks together. the Processor Delta Time Totals Graph. Workloads are balanced.html.A3 execute in parallel.csh. Partitions have same amount of activity. Parallel VCS 198 . Examine the output is in the ppResults_clock directory by opening the file results. but they execute across two deltas On the right. Figure 9-18 shows the example in which Partition A2 gets its clock from A1.

the Balance distribution graph shows that workloads of the partitions are balanced.Use of SV data types logic and bit types are allowed. Solaris 32 bit: Multi-core Multi-proceesor machine. the Processor Delta Time Totals Graph. Current Limitations +race +race is not supported Partial Elab This flow is not supported. On the right.In this example: • The left chart. Parallel VCS 199 . The center graph. but the work for each partition is done in a different delta. SystemVerilog . but none of the three partitions execute in parallel. Certain dynamic types are not allowed inside slave partitions.0 : Multi-core multi-processor machine. the Processor Segment Totals graph shows that each partition is doing the same amount of work but are spending most of the time waiting for events in other partitions. shows the partitions have the same amount of activity. • • Supported Platforms • • Linux 32/64bit RH4.

VHDL testbench and Verilog gate-level netlist will work very well. and AMS These flows are not supported.VCS-MX • • Only Verilog instances can be added as partitions. SystemC-C. All VHDL will run in the master partition. For example. Parallel VCS 200 . VMC.

10 VMM Additions and Enhancements 1 New features and functionality in VMM are described in the following sections: • • • VMM RAL C Interface VMM Standard Library Class Additions vmm_ral_block_or_sys Base Class Additions For more information on these features. VMM Additions and Enhancements 205 . see the VMM Register Abstraction Layer User Guide and the VMM User Guide.

eliminating the need for an instruction set simulator or a RTL model of the processor. As illustrated in Figure 10-1. One is designed to interface to the RAL model running in the SystemVerilog simulator using the Direct Programming Interface. The C code is executed natively on the same workstation that is running the SystemVerilog simulation.VMM RAL C Interface The RAL C interface allows firmware and application-level code to be developped and debugged on a simulation of the design. The same C code can later be compiled for the target execution processor. The fields. VMM Additions and Enhancements 206 . unmodified. two versions of the RAL C API can be generated. This allows the firmware and application-level code to be verified against a simulation then used. in the final application. The other is pure stand-alone C code and is designed to be compiled on the target processor in the final application. registers and memories included in a RAL model can be accessed in C code through a C API.

registers or memories. as shown in Example 10-1. There are two kinds of entry points: application entry points and service entry points. To that end. as specified in Appendix C. it is necessary for the C code to be called by the simulation to be executed. typically in the same file that defines the verification environment. They only differ in their intent and timing of the invocation. the application software’s main() routine must be replaced by one or more entry points known to the simulation. The RAL model reference is a size_t on the C side The C-side reference is then used by the RAL C API to access required fields. Entry points must be declared in the $unit scope. The arguments must require at least one instance of a block or system base address. Both use the same interface mechanism. VMM Additions and Enhancements 207 . All entry points must take at least one argument that will receive the base address of the RAL model to be used by the C code.Figure 10-1 RAL-Generated APIs Firmware or Application Code C + SV ralgen C SV Simulator RALF file Synthesis C Compiler RTL H/W Entry Point When executing the C code within a simulation.

It replaces the application’s main() routine that would normally be automatically invoked by the host operating system. If the application software includes (or is) the device configuration firmware.sv" import "DPI-C" context task C_func_name(int blk). If the application software VMM Additions and Enhancements 208 .Example 10-1 Entry point declaration ‘include "vmm-ral. as shown in Example 10-3. as shown in Example 10-2. at the beginning of the simulation. The entry point must correspond to a void C function with a corresponding size_t argument for the base address of the toplevel block or system. corresponding to Example 10-1 void C_func_name(size_t blk) { . An application entry point may or may not complete and return control of the execution thread back to the SystemVerilog side. An application entry point should be invoked by the testcase or verification environment at a point where the simulated design is ready to be used by the application software. } Application Entry Point An application entry point is invoked only once. Example 10-2 Entry point declaration in C. the entry point should be invoked as the implementation of the cfg_dut() method... the entry point for each application or application fragment may be called by the simulation or internally by a top-level entry point. If a simulation contains more than one "application" or if the application software is fragmented into different functions.

C_addr_of()).cfg_dut(). Example 10-3 Invoking application containing configuration firmware import "DPI-C" context task appsw(vmm_ral_block blk). initial begin env.. end endprogram VMM Additions and Enhancements 209 . fork appsw(this..start(). fork appsw(env. Note how each entry point invocation is forked to allow for an application software that never completes. join_none endtask .. join_none env. program test.requires a fully functional and configured model of the design. . class my_env extends vmm_env..run().ral_model.C_addr_of()). as shown in Example 10-4. super. virtual task cfg_dut(). its entry point should be invoked after the environment has been started.ral_model. tb_env env = new. endclass Example 10-4 Application requiring pre-configured simulation import "DPI-C" context task appsw(vmm_ral_sys sys).

int === 1’b1). Unlike an application entry point. VMM Additions and Enhancements 210 . class my_env extends vmm_env..int signal is asserted. Example 10-5 Invoking application containing configuration firmware import "DPI-C" context task isr(vmm_ral_sys sys). . It is unlike the real application code running as object code on a real processor. where the execution of the code happens concurrently with other processing in the neighboring hardware. Notice how its invocation is embedded in a forever loop to ensure that interrupts will be serviced whenver the tb_top. whenever a condition requiring software servicing is detected..ral_model). end join_none endtask . isr(this. a service entry point always returns. at which point it may be invoked again. all C code executes atomically..Service Entry Point A service entry point is invoked multiple times. endclass Execution Timeline When executing with a simulation of the design. fork forever begin wait (tb_top. A typical service entry point is the invocation of the interrupt service code in the application software.start(). virtual task start().. as illustrated in Example 10-5. super.

once the read or write operation completes and the control is returned back to the C code. With physical device. It would likely require many hundreds of such read cycles for the design to reach a state that is relevant and significant for the application software. This execution timeline is illustrated in Figure 10-2. or for the C code to perform a read or write operation through the RAL model. is for the C code to return. that is not an issue as this can happens in less than a microsecond. the simulation is again frozen. But in a simulation. In the latter case. If an interrupt-driven strategy is used. the simulation will have the opportunity to advance only during the execution of the repeated polling read cycles. The execution timeline is the cause of the important impact on run-time performance of how the C code interacts with the design. the simulation will proceed until something of interest to the application software has happened before transfering the control to the C code (through a service entry VMM Additions and Enhancements 211 . Figure 10-2 C code and Simulated Design Execution Timeline C Code Simulation (read) (write) t If a polling strategy is used. The only way for the design simulation to proceed. The entire execution timeline in the C code occurs in zero-time in the simulation timeline.When C code executes. this would require a lot of processing for simulating essentially useless read cycles and exchanging data between the C world and the simulation world. only that code performs any form of processing and the simulation of the rest of the design is frozen.

.. the RAL C API hides the physical addresses of registers and the position and size of fields. while preserving as much as possible the abstraction offered by the RAL model..point) and only the necessary read and write operations would need to be performed. Figure 10-3 Example register layout 31 11 5 0 0x....0104 0x.0100 0x. If the application software requires such synchronization...... Writing Firmware Code The RAL C API is designed to ultimately yield compact and efficient firmware code.....010C 0x.... it should similarly use an asynchronous servicedriven approach............0108 0x. To that effect.0110 a2 a2 29 X 6 a1 Y R1 R2 R3 a1 a1 Example 10-6 Example RALF specification block myblk { VMM Additions and Enhancements 212 ..... It is also very important that the execution of the C code not be blocked by an external event—such as waiting for user input or a file to be unlocked—as it will prevent the simulation from moving forward while it is blocked.. The hiding is performed by functions and macros rather than an object-oriented structure like the native RAL model in SystemVerilog This is to eliminate the need to compile a complete object-oriented model in an embedded processor object code with limited amount of memory.. It is thus important that a service-based approach be used as much as possible.

} } register R3 @0x110{ bytes 4. Example 10-7 shows a single-segment. } } memory m { bits 32 size 1024 } Accessing Registers Ideally. would be accessed. } field X { bits 7. Registers can be accessed using the ral_read_<reg>_in_<block> and ral_write_<reg>_in_<block> macros. The RAL C interface supports single-segment as well as multi-segment registers. field a1 { bits 32. access rw. such as register R1 specified in Figure 10-3. register R1 @0x0100 { bytes 4. field a1 { bits 4. } field Y @32 { bits 7. registers and memories should be of the same size as the native data bus size of the target process—typically the int type in the C code—and thus live at a single physical address (called "segment"). access rw. access rw. access rw. } } register R2 @0x104 { bytes 12. } field a2 @64 { bits 30. access rw. access rw. endian big. field a1 { bits 32. Example 10-7 Accessing single-segment register from C void C_func_name(void* blk) VMM Additions and Enhancements 213 . access rw. This allows each register to be accessed or updated using a single read or write operation. } field a2 { bits 21.} bytes 4.

then there will also be macros named ral_read_<field>_in_<block> and ral_write_<field>_in_<block> with identical respective functionality VMM Additions and Enhancements 214 . ral_read_R2_in_myblk(blk. the entire register can be accessed using the same macros but by using an array of int with one element per physical location. If the field has a unique name in its enclosing block. r2 = {0x0. &r1). &r1). r2). 0x1234. ral_write_R2_in_myblk(blk. RAL models that use FIFO ordering are not supported. 0x0}. 0x5678}. 0x0.{ } unsigned int r1 = 0xABCD. If a register spans multiple physical locations. such as register R2 in Figure 10-3. irrespective of their actual hardware layout as specified in the RALF file. r1 = 0. ral_read_R1_in_myblk(blk. Endian Support The RAL C interface always read multi-segment registers into the 'int' array ('r2' in Example 10-8) in little-endian order. Accessing Fields Individual fields can be accessed using the corresponding ral_read_<field>_in_<block>_<reg> and ral_write_<field>_in_<block>_<reg> macros. ral_write_R1_in_myblk(blk. as shown in Example 10-8. r2). Example 10-8 Accessing an entire multi-address register int r2[3]. This means that the segments of a multi-segment register in a big-endian block or system will be in the reverse order in the C int array. r2 = {0xABCD.

as illustrated in Figure 10-3. &x). Accessing Memories Memories can be accessed using the ral_read_<mem>_in_<block> and ral_write_<mem>_in_<block> macros. or fields need to span more than one physical address. &mem_loc). Example 10-11 Accessing a single-segment memory location unsigned int mem_loc = 0xAABBCCDD. it will be necessary access them using the multi-segment register access procedures and the resulting array-of-int value. VMM Additions and Enhancements 215 .as the previous set of macros. &x). ral_write_X_in_myblk_R1(ral_addr_of_R1_in_myblk(blk). 0x100. Example 10-10 Accessing field in a specific register unsigned int x = 0x0F. ral_write_X_in_myblk(blk. ral_read_X_in_myblk_R1(ral_addr_of_R1_in_myblk(blk). Currently. offset 0x100 of memory 'm' specified in Example 10-6. mem_loc = 0. &x). If larger fields are required. &mem_loc). x = 0. fields with a size greater than sizeof(int) and fields spanning multiple physical addresses are not supported. would be accessed. Example 10-9 Accessing a block-unique field unsigned int x = 0x0F. Example 10-9 and Example 1010shows how the field named X. Example 10-11 shows how to read and write a memory location. &x). x = 0. ral_read_m_in_myblk(blk. ral_write_m_in_myblk(blk. ral_read_X_in_myblk(blk. 0x100.

The only difference is that a suitably sized array of int would need to be supplied to hold the memory location value to be read or written.Note that a multi-segment memory location would be accessed using the same macro. VMM Standard Library Class Additions Classes and members that have been added to the VMM Standard Library are described in the following sections: • • • • • • • vmm_opts vmm_scenario vmm_object vmm_ms_scenario_gen vmm_xactor_iter vmm_test vmm_channel VMM Additions and Enhancements 216 .

Its functionality is accessed strictly through static methods. or as separate command-line options prefixed with "+vmm_". Summary • • • • vmm_opts::get_bit() vmm_opts::get_int() vmm_opts::get_string() vmm_opts::get_help() VMM Additions and Enhancements 217 . Using the former is preferable as a warning will be issued if an unknown option is specified. No constructor is documented because this class is implemented using a singleton pattern.vmm_opts This class provides an interface to define and access run-time options. Run-time options can be specified using a combination of command-line arguments and option files specified using a plusseperated list of filenames to the "+vmm_opts_file=" command-line option. Command-line options can be specified using a plus-separated list of run-time options to the +vmm_opts command-line option.

Returns FALSE otherwise. the documentation is not redefined. Description Return TRUE if the specified option name was specified. VMM Additions and Enhancements 218 . string doc = ""). If it has been previsouly defined for the specified option through a prior call of this method.+foo+. SystemVerilog static function bit get_bit(string name. The "doc" argument is a short description of the run-time argument that will be displayed by the vmm_opts::get_help() method." command-line option. The boolean run-time option "foo" would be supplied using the "+vmm_opts+.. or the line "+foo" in the option file...vmm_opts::get_bit() Get a boolean option value.. or "+vmm_foo" command-line option.

.. If the run-time option was not supplied.vmm_opts::get_int() Get an integer option value.+foo=5+. the documentation is not redefined. SystemVerilog static function int get_int(string name. Description Returns the integer value specified as the argument of the specified run-time option. int dflt = 0. string doc = ""). VMM Additions and Enhancements 219 ... The "doc" argument is a short description of the run-time argument that will be displayed by the vmm_opts::get_help() method. Different calls specifying the same option may have different default values." command-line option. If it has been previsouly defined for the specified option through a prior call of this method. returns the specified default value. or "+vmm_foo=5" command-line option. or the line "+foo=5" in the option file. The integer value "5" for run-time option "foo" would be supplied using the "+vmm_opts+.

." command-line option.. string doc = ""). If it has been previsouly defined for the specified option through a prior call of this method. or "+vmm_foo=bar" command-line option. the documentation is not redefined. or the line "+foo=bar" in the option file. The string value "bar" for run-time option "foo" would be supplied using the "+vmm_opts+.. If the run-time option was not supplied. Different calls specifying the same option may have different default values. returns the specified default value. SystemVerilog static function string get_string(string name. The "doc" argument is a short description of the run-time argument that will be displayed by the vmm_opts::get_help() method. VMM Additions and Enhancements 220 . string dflt = "". Description Returns the string value specified as the argument of the specified run-time option.+foo=bar+..vmm_opts::get_string() Get a string option value.

end . $finish. super. Description Display a human-readable list of all run-time options queried so far.. followed by a call to $finish().start(). Examples Example 10-12 virtual task tb_env::start(). endtask VMM Additions and Enhancements 221 . if ($test$plusargs("tb_help")) begin vmm_opts::get_help().vmm_opts::get_help() Display a list of all known run-time options. SystemVerilog static function void get_help().. This method is automatically called. by the vmm_env::reset_dut() method if the +vmm_help command-line option is supplied.

This class extends from vmm_data. Summary • • • • • • • • • • • • • vmm_scenario::stream_id vmm_scenario::scenario_id vmm_scenario::scenario_kind vmm_scenario::length vmm_scenario::repeated vmm_scenario::repeat_thresh vmm_scenario::repetition vmm_scenario::define_scenario() vmm_scenario::redefine_scenario() vmm_scenario::scenario_name() vmm_scenario::psdisplay() vmm_scenario::set_parent_scenario() vmm_scenario::get_parent_scenario() VMM Additions and Enhancements 222 .vmm_scenario Base class for all user-defined scenarios.

VMM Additions and Enhancements 223 .vmm_scenario::stream_id Stream identifier of the randomizing generator. This state variable can be used to specifiy stream-specific constraints or to differentiate stimulus from different streams in a scoreboard. SystemVerilog int stream_id Description This data member is set by the scenario generator before randomization to the generator’s stream identifier.

vmm_scenario::scenario_id Scenario identifier of the randomizing generator. SystemVerilog int scenario_id Description This data member is set by the scenario generator before randomization to the generator’s current scenario counter value. VMM Additions and Enhancements 224 . This state variable can be used to specifiy scenario-specific constraints or to identify the order of different scenarios within a stream.

VMM Additions and Enhancements 225 .vmm_scenario::scenario_kind Scenario kind identified. SystemVerilog rand int unsigned scenario_kind Description Used to randomly select one of the scenario kinds defined in this random scenario descriptor.

Constrained to be less than or equal to the maximum number of transactions in the selected scenario kind. SystemVerilog rand int unsigned length Description Random number of transaction descriptor in this random scenario.vmm_scenario::length Length of the scenario. VMM Additions and Enhancements 226 .

vmm_scenario::repeated Scenario identifier of the randomizing generator. VMM Additions and Enhancements 227 . Constrained to zero by default by the “vmm_scenario::repetition” constraint block. hence will be applied only once. Note that is is best to repeat the same transaction instead of creating a scenario of many transactions constrained to be identical. A repetition value of zero specifies that the scenario will not be repeated. SystemVerilog rand int unsigned repeated Description The number of time the entire scenario is repeated.

vmm_scenario::repeat_thresh Repetition warning threshold. VMM Additions and Enhancements 228 . SystemVerilog static int unsigned repeat_thresh Description Specifies a threshold value that triggers a warning about possibly unconstrained “vmm_scenario::repeated”data member. Defaults to 100.

can cause stimulus to be erroneously repeatedly applied over 2 billion times on average. } endclass VMM Additions and Enhancements 229 . SystemVerilog constraint repetition { repeated == 0.vmm_scenario::repetition Constraint preventing the scenario from being repeated. } Description The “vmm_scenario::repeated” data member specifies the number of times a scenario is repeated. constraint repetition { repeated < 10. This constraint block constrains this data member to prevent repetition by default. Examples Example 10-13 class many_atomic_scenario extends eth_frame_atomic_scenario. It is not often used but. simply override this constraint block. To have a scenario be repeated a random number of times. if left unconstrained.

The “vmm_scenario::scenario_kind”data member will randomly select one of the defined scenario kinds. Description Defines a new scenario kind included in this scenario descriptor and return a unique scenario kind identifier. The new scenario kind may have up to the specified number of random transactions. int unsigned max_len).vmm_scenario::define_scenario() Define a new scenario kind. The scenario kind identifier should be stored in a state variable that can then be subsequently used to specified kind-specific constraints. VMM Additions and Enhancements 230 . SystemVerilog function int unsigned define_scenario(string name.

The scenario kind may be redefined with a different name or maximum number of random transactions. int unsigned max_len).vmm_scenario::redefine_scenario() Redefine an existing scenario kind. SystemVerilog function void redefine_scenario(int unsigned scenario_kind. refine or replace an existing scenario kind in a pre-defined scenario descriptor. string name. VMM Additions and Enhancements 231 . Use this method to modify. Description Redefines an existing scenario kind included in this scenario descriptor.

as defined by the “vmm_scenario::define_scenario()” or “vmm_scenario::redefine_scenario()” methods. SystemVerilog function string scenario_name(int unsigned scenario_kind). Description Return the name of the specified scenario kind. VMM Additions and Enhancements 232 .vmm_scenario::scenario_name() Name of a scenario kind.

VMM Additions and Enhancements 233 .vmm_scenario::psdisplay() Create an image of the scenario descriptor. SystemVerilog virtual function string psdisplay(string prefix = "") Description Create human-readable image of the content of the scenario descriptor.

vmm_scenario::set_parent_scenario() Define higher-level hierarchical scenario. This will allow this scenario to grab a channel that has already been grabbed by the parent scenario. SystemVerilog function void set_parent_scenario( vmm_scenario parent) Description Specify the single stream or multiple-stream scenario that is the parent of this scenario. VMM Additions and Enhancements 234 .

A scenario with no parent is a top-level scenario.vmm_scenario::get_parent_scenario() Get the higher-level hierarchical scenario. VMM Additions and Enhancements 235 . SystemVerilog function vmm_scenario get_parent_scenario() Description Get the single stream or multiple-stream scenario that was specified as the parent of this scenario.

% vcs . vmm_notify.sv \ ... vmm_xactor.sv \ . \ +define+VMM_PRE_INCLUDE=$VMM_HOME/sv/std_lib/opt/vmm_object.... \ +define+VMM_PRE_INCLUDE=$VCS_HOME/etc/rvm/sv/std_lib/opt/vmm_object. vmm_consensus and vmm_test classes. vmm_subenv.svh \ +define_VMM_POST_INCLUDE=$VCS_HOME/etc/rvm/sv/std_lib/opt/vmm_object. Summary • • • • • • • • vmm_object::type_e vmm_object::new vmm_object::set_parent() vmm_object::get_parent() vmm_object::get_type() vmm_object::get_hier_inst_name() vmm_object::display() vmm_object::psdisplay() VMM Additions and Enhancements 236 .svh \ +define_VMM_POST_INCLUDE=$VMM_HOME/sv/std_lib/opt/vmm_object.. This option is enabled by loading the customization definitions files as follows: % vcs . vmm_scenario.. vmm_channel.. vmm_ms_scenario. vmm_env.vmm_object The vmm_object class is an optional common base class for the vmm_data.

vmm_object::type_e Type of this object. Once the type is known. VMM_SUBENV. The VMM_OBJECT is returned when the type of the object cannot be determined. a reference to a vmm_object can be cast into the corresponding class type. VMM Additions and Enhancements 237 . VMM_CONSENSUS. VMM_NOTIFY. SystemVerilog typedef enum { VMM_UNKNOWN. VMM_ENV. VMM_XACTOR. VMM_SCENARIO. VMM_CHANNEL. VMM_DATA. VMM_TEST } type_e Description Value returned by the “vmm_object::type_e”method to identify the type of this vmm_object extension. or to specify any object type to the “vmm_object::type_e”method. The VMM_UNKNOWN type is an internal value and never returned by the “vmm_object::type_e”method. VMM_OBJECT. VMM_MS_SCENARIO.

Description Optionally specify a parent object to this object when constructing a vmm_object instance. SystemVerilog function new(vmm_object parent = NULL). See “vmm_object::type_e” for more details on specifying a parent object. VMM Additions and Enhancements 238 .vmm_object::new Constructor.

This macro will call this method if the vmm_object base class is present but do nothing if not. Description Specify a new parent object to this object. If this object and the parent object are known to contain their own instance of the message service interface.vmm_object::set_parent() Specify a parent object. An object may have only one parent.log).is_above(this). the vmm_log instance in the parent is specified as being above the vmm_log instance in the chil by calling parent. SystemVerilog function void set_parent(vmm_object parent). but the identity of a parent can be changed dynamically.notify = new(this. it is not possible to call this method in code designed to be reusable with and without this base class. _child) macro should be used instead. VMM Additions and Enhancements 239 . the ‘VMM_OBJECT_SET_PARENT(_parent. To that effect. The instance names of the message service interfaces can then be subsequently made hierarchical by using the “vmm_log::use_hier_inst_name()” method. The presence of the vmm_object base class being optional. Examples Example 10-14 this. Specifying a NULL parent breaks the any current parent/child relationship.

notify.log). ‘VMM_OBJECT_SET_PARENT(this. this) VMM Additions and Enhancements 240 . Example 10-15 this.notify = new(this.set_parent(this).notify.this.

if any. Description Return the parent object of the specified type. VMM Additions and Enhancements 241 . Specifying VMM_OBJECT returns the immediate parent of any type.vmm_object::get_parent() Get a parent object. Returns NULL if no such parent is found. SystemVerilog function vmm_object get_parent( vmm_object::type_e typ = VMM_OBJECT).

Description Return the type of this vmm_object extension.vmm_object::get_type() Get the type of the object. SystemVerilog function vmm_object::type_e get_type(). Returns VMM_OBJECT if it is not one of the known VMM class extensions. VMM Additions and Enhancements 242 . VMM_UNKNOWN is purely an internal value and is never returned.

vmm_object::get_hier_inst_name() Get the hierarchical instance name of the object. Description Return the hierarchical instance name of the object. SystemVerilog function string get_hier_inst_name(). The instance name is composed of the dot-separated instance names of the message service interface of all the parents of the object. The hierarchical name is return whether or not the message services interfaces are using hierarchical or flat names. VMM Additions and Enhancements 243 .

vmm_object::display() Display a description of the object to stdout SystemVerilog virtual function void display(string prefix = ""). VMM Additions and Enhancements 244 . If this method conflicts with a previously declared method in a class now based on the vmm_object class. it can be removed by defining the ‘VMM_OBJECT_NO_DISPLAY symbol at compile-time. Description Display the image returned by “vmm_object::type_e”to the standard output.

If this method conflicts with a previously declared method in a class now based on the vmm_object class. Each line of the image is prefixed with the specified prefix. The description should not contain a final newline character. it can be removed by defining the ‘VMM_OBJECT_NO_DISPLAY symbol at compile-time. VMM Additions and Enhancements 245 . Description Creates a human-readable image of the content of the object and returns it as a string.vmm_object::psdisplay() Create a description of the object SystemVerilog virtual function string psdisplay(string prefix = "").

Summary • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • vmm_ms_scenario_gen::stop_after_n_scenarios vmm_ms_scenario_gen::inst_count vmm_ms_scenario_gen::scenario_count vmm_ms_scenario_gen::inst_count vmm_ms_scenario_gen::get_n_scenarios() vmm_ms_scenario_gen::get_n_insts() vmm_ms_scenario_gen::GENERATED vmm_ms_scenario_gen::DONE vmm_ms_scenario_gen::register_ms_scenario() vmm_ms_scenario_gen::ms_scenario_exists() vmm_ms_scenario_gen::get_ms_scenario() vmm_ms_scenario_gen::get_ms_scenario_name() vmm_ms_scenario_gen::get_ms_scenario_index() vmm_ms_scenario_gen::get_names_by_ms_scenario() vmm_ms_scenario_gen::get_all_ms_scenario_names() vmm_ms_scenario_gen::replace_ms_scenario() vmm_ms_scenario_gen::unregister_ms_scenario() vmm_ms_scenario_gen::unregister_ms_scenario_by_name() vmm_ms_scenario_gen::select_scenario vmm_ms_scenario_gen::scenario_set[$] vmm_ms_scenario_gen::register_channel() vmm_ms_scenario_gen::channel_exists() vmm_ms_scenario_gen::get_channel() vmm_ms_scenario_gen::get_channel_name() vmm_ms_scenario_gen::get_names_by_channel() vmm_ms_scenario_gen::get_all_channel_names() vmm_ms_scenario_gen::replace_channel() vmm_ms_scenario_gen::unregister_channel() vmm_ms_scenario_gen::unregister_channel_by_name() vmm_ms_scenario_gen::register_ms_scenario_gen() vmm_ms_scenario_gen::ms_scenario_gen_exists() vmm_ms_scenario_gen::get_ms_scenario_gen() vmm_ms_scenario_gen::get_ms_scenario_gen_name() vmm_ms_scenario_gen::get_all_ms_scenario_gen_names() vmm_ms_scenario_gen::replace_ms_scenario_gen() vmm_ms_scenario_gen::unregister_ms_scenario_gen() vmm_ms_scenario_gen::unregister_ms_scenario_gen_by_name() VMM Additions and Enhancements 246 .vmm_ms_scenario_gen This class is a pre-defined multi-stream scenario generator. The following methods are available. See Xref for guidelines on how the multi-stream scenario generator can be used and how multistream scenarios—including hierarchical scenarios—are defined and executed.

SystemVerilog int unsigned stop_after_n_scenarios Description Automatically stop the multi-stream scenario generator when the number of generated multi-streams scenarios reaches or surpasses the specified value. A value of zero specifies an infinite number of multi-stream scenarios.vmm_ms_scenario_gen::stop_after_n_scenarios Number of multi-stream scenarios to generate. VMM Additions and Enhancements 247 . Sub-scenarios executed as part of a higher-level multi-stream scenario are not counted. Only the multi-stream scenarios explicitly executed by this instance of the multi-stream scenario generator are counted.

vmm_ms_scenario_gen::stop_after_n_insts Number of transaction descriptor to generate. The number of transaction descriptor instances generated by the execution of a multi-stream scenario is the number of transactions reported by the vmm_ms_scenario::execute() method when it returns. SystemVerilog int unsigned stop_after_n_insts Description Automatically stop the multi-stream scenario generator when the number of generated transaction descriptors reaches or surpasses the specified value. Entire scenarios are executed before the generator is stopped so the actual number of transaction descriptors generated may be greater than the specified value. VMM Additions and Enhancements 248 . A value of zero indicates an infinite number of transaction descriptors.

SystemVerilog protected int scenario_count. the generator stops. Sub-scenarios executed as part of a higher-level multi-stream scenario are not counted. When is reaches or surpasses the value in vmm_ms_scenario_gen::stop_after_n_scenarios. Description Current count of the number of top-level multi-stream scenarios generated the multi-stream scenario generator.vmm_ms_scenario_gen::scenario_count Number of multi-stream scenarios generated so far. Only the multi-stream scenarios explicitly executed by this instance of the multi-stream scenario generator are counted. VMM Additions and Enhancements 249 .

SystemVerilog protected int inst_count. VMM Additions and Enhancements 250 .vmm_ms_scenario_gen::inst_count Number of transaction descriptor generated so far. The number of transaction descriptor instances generated by the execution of a multi-stream scenario is the number of transactions reported by the vmm_ms_scenario::execute() method when it returns. When is reaches or surpasses the value in vmm_ms_scenario_gen::stop_after_n_insts. the generator stops. Description Current count of the number of individual transaction descriptor instances generated by the multi-stream scenario generator.

SystemVerilog function int unsigned get_n_scenarios() Description Return the current value of the vmm_ms_scenario_gen::scenario_count property.vmm_ms_scenario_gen::get_n_scenarios() Number of multi-stream scenarios generated so far. VMM Additions and Enhancements 251 .

SystemVerilog function int unsigned get_n_insts() Description Return the current value of the vmm_ms_scenario_gen::inst_count property.vmm_ms_scenario_gen::get_n_insts() Number of transaction descriptors generated so far. VMM Additions and Enhancements 252 .

SystemVerilog typedef enum int {GENERATED} symbols_e Description Notification in vmm_xactor::notify that is indicated every time a new multi-stream scenario is generated and about to be executed. VMM Additions and Enhancements 253 .vmm_ms_scenario_gen::GENERATED Notification of a newly generated scenario.

VMM Additions and Enhancements 254 .vmm_ms_scenario_gen::DONE Notification of a generation completed. SystemVerilog typedef enum int {DONE} symbols_e Description Notification in vmm_xactor::notify that is indicated when the generation process has completed as specified by the scenvmm_ms_scenario_gen::stop_after_n_scenarios and vmm_ms_scenario_gen::stop_after_n_insts class properties.

vmm_ms_scenario scenario) Description Registers the specified multi-stream scenario under the specified name. Registering a scenario implicitly appends it to the scenario set if it is not already in the vmm_ms_scenario_gen::scenario_set[$] array. scenario descriptor SystemVerilog virtual function void register_ms_scenario(string name. VMM Additions and Enhancements 255 .vmm_ms_scenario_gen::register_ms_scenario() Register a multi-strea. thus creating an alias to the same scenario. Use vmm_ms_scenario_gen::replace_ms_scenario() to replace a registered scenario. It is an error to attempt to register a scenario under a name that already exists. The same scenario may be registered multiple times under different names.

vmm_ms_scenario_gen::ms_scenario_exists() Checks if a scenario is registered under a specified name SystemVerilog virtual function bit ms_scenario_exists(string name) Description Returns TRUE if there is a multi-stream scenario registered under the specified name. VMM Additions and Enhancements 256 . Returns FALSE otherwise. Use vmm_ms_scenario_gen::get_ms_scenario() to retrieve a scenario under a specified name.

Issues a warning message and returns NULL if there are no scenarios registered under that name. VMM Additions and Enhancements 257 .vmm_ms_scenario_gen::get_ms_scenario() Get the scenario registered under a specified name SystemVerilog virtual function vmm_ms_scenario get_ms_scenario( string name) Description Returns the multi-stream scenario descriptor registered under the specified name.

VMM Additions and Enhancements 258 .vmm_ms_scenario_gen::get_ms_scenario_name() Get a name under which a scenario is registered SystemVerilog virtual function string get_names_by_ms_scenario( vmm_ms_scenario scenario) Description Returns a name under which the specified multi-stream scenario descriptor is registered. Returns "" if the scenario is not registered.

VMM Additions and Enhancements 259 .vmm_ms_scenario_gen::get_ms_scenario_index() Get the index of the specified scenario SystemVerilog virtual function int get_ms_scenario_index( vmm_ms_scenario scenario) Description Returns the index of the specified scenario descriptor in the vmm_ms_scenario_gen::scenario_set[$] array. A warning message is issued and returns -1 if the scenario descriptor is not found in the scenario set.

Returns the number of names that were added to the array.vmm_ms_scenario_gen::get_names_by_ms_scenario( ) Get the names under which a scenario is registered SystemVerilog virtual function int get_names_by_ms_scenario( vmm_ms_scenario scenario. VMM Additions and Enhancements 260 . ref string name[$]) Description Appends the names under which the specified multi-stream scenario descriptor is registered.

Returns the number of names that were added to the array.vmm_ms_scenario_gen::get_all_ms_scenario_names( ) Get all the names in the scenario registry SystemVerilog virtual function int get_all_ms_scenario_names( ref string name[$]) Description Appends the names under which a multi-stream scenario descriptor is registered. VMM Additions and Enhancements 261 .

The same scenario may be registered multiple times under different names. thus creating an alias to the same scenario. The replaced scenario is removed from vmm_ms_scenario_gen::scenario_set[$] if it is not also registered under another name. replacing the scenario previously registered under that name (if any). vmm_ms_scenario scenario) Description Registers the specified multi-stream scenario under the specified name.vmm_ms_scenario_gen::replace_ms_scenario() Replace a scenario descriptor SystemVerilog virtual function void replace_ms_scenario(string name. VMM Additions and Enhancements 262 . Registering a scenario implicitly appends it to the scenario set if it is not already in the vmm_ms_scenario_gen::scenario_set[$] array.

vmm_ms_scenario_gen::unregister_ms_scenario() Unregister a scenario descriptor SystemVerilog virtual function bit unregister_ms_scenario( vmm_ms_scenario scenario) Description Completely unregisters the specified multi-stream scenario descriptor and returns TRUE if it exists in the registry. VMM Additions and Enhancements 263 . The unregistered scenario is also removed from the vmm_ms_scenario_gen::scenario_set[$] array.

Returns NULL if there is no scenario registered under the specified name. VMM Additions and Enhancements 264 . The unregistered scenario descriptor is removed from vmm_ms_scenario_gen::scenario_set[$] if it is not also registered under another name.vmm_ms_scenario_gen::unregister_ms_scenario_by_ name() Unregister a scenario descriptor SystemVerilog virtual function vmm_ms_scenario unregister_ms_scenario( string name) Description Unregisters the multi-stream scenario under the specified name and returns the unregistered scenario descriptor.

VMM Additions and Enhancements 265 . The default election instance may be replaced by a user-defined extension to modify the scenario election policy.vmm_ms_scenario_gen::select_scenario Scenario selection factory SystemVerilog vmm_ms_scenario_election select_scenario Description Randomly select the next multi-stream scenario to execute from the vmm_ms_scenario_gen::scenario_set[$] array. The selection is performed by calling randomize() on this class property then executing the multi-stream scenario found in the vmm_ms_scenario_gen::scenario_set[$] array at the index specified by the vmm_ms_scenario_election::select class property.

The scenario executed next is selected by randomizing the vmm_ms_scenario_gen::select_scenario class property.vmm_ms_scenario_gen::scenario_set[$] Multi-stream scenarios available for execution SystemVerilog vmm_ms_scenario scenatio_set[$] Description Multi-stream scenarios available for execution by this generator. VMM Additions and Enhancements 266 . vmm_ms_scenario_gen::replace_ms_scenario() and vmm_ms_scenario_gen::unregister_ms_scenario() methods. Multi-stream scenario instances in this array should be managed through the vmm_ms_scenario_gen::register_ms_scenario().

Once registered. Use vmm_ms_scenario_gen::replace_channel() to replace a registered scenario. thus creating an alias to the same channel.vmm_ms_scenario_gen::register_channel() Register an output channel SystemVerilog virtual function void register_channel(string name. The same channel may be registered multiple times under different names. vmm_channel chan) Description Registers the specified output channel under the specified logical name. the output channel becomes available under the specified logical name to multi-stream scenarios via the vmm_ms_scenario::get_channel() method. It is an error to attempt to register a channel under a name that already exists. VMM Additions and Enhancements 267 .

VMM Additions and Enhancements 268 . Use vmm_ms_scenario_gen::get_channel() to retrieve a channel under a specified name.vmm_ms_scenario_gen::channel_exists() Checks if a channel is registered under a specified name SystemVerilog virtual function bit channel_exists(string name) Description Returns TRUE if there is an output channel registered under the specified name. Returns FALSE otherwise.

vmm_ms_scenario_gen::get_channel() Get the channel registered under a specified name SystemVerilog virtual function vmm_channel get_channel( string name) Description Returns the output channel registered under the specified name. Issues a warning message and returns NULL if there are no channels registered under that name. VMM Additions and Enhancements 269 .

VMM Additions and Enhancements 270 . Returns "" if the channel is not registered.vmm_ms_scenario_gen::get_channel_name() Get a name under which a channel is registered SystemVerilog virtual function string get_names_by_channel( vmm_channel chan) Description Return a names under which the specified channel is registered.

vmm_ms_scenario_gen::get_names_by_channel() Get the names under which a channel is registered SystemVerilog virtual function int get_names_by_channel( vmm_channel chan. Returns the number of names that were added to the array. ref string name[$]) Description Appends the names under which the specified output channel is registered. VMM Additions and Enhancements 271 .

VMM Additions and Enhancements 272 . Returns the number of names that were added to the array.vmm_ms_scenario_gen::get_all_channel_names() Get all the names in the channel registry SystemVerilog virtual function int get_all_channel_names( ref string name[$]) Description Appends the names under which an output channel is registered.

thus creating an alias to the same output channel. VMM Additions and Enhancements 273 .vmm_ms_scenario_gen::replace_channel() Replace an output channel SystemVerilog virtual function void replace_channel(string name. vmm_channel chan) Description Registers the specified output channel under the specified name. The same channel may be registered multiple times under different names. replacing the channel previously registered under that name (if any).

VMM Additions and Enhancements 274 .vmm_ms_scenario_gen::unregister_channel() Unregister an output channel SystemVerilog virtual function bit unregister_channel( vmm_channel chan) Description Completely unregisters the specified output channel and returns TRUE if it exists in the registry.

vmm_ms_scenario_gen::unregister_channel_by_nam e() Unregister an output channel SystemVerilog virtual function vmm_channel unregister_channel( string name) Description Unregisters the output channel under the specified name and returns the unregistered channel. VMM Additions and Enhancements 275 . Returns NULL if there is no channel registered under the specified name.

the multi-stream generator becomes available under the specified logical name to multi-stream scenarios via the vmm_ms_scenario::get_ms_scenario() method to create hierarchical multi-stream scenarios.vmm_ms_scenario_gen::register_ms_scenario_gen() Register a sub-generator SystemVerilog virtual function void register_ms_scenario_gen(string name. It is an error to attempt to register a generator under a name that already exists. Once registered. Use vmm_ms_scenario_gen::replace_ms_scenario_gen() to replace a registered generator. vmm_ms_scenario_gen gen) Description Registers the specified sub-generator under the specified logical name. VMM Additions and Enhancements 276 . thus creating an alias to the same generator. The same generator may be registered multiple times under different names.

Returns FALSE otherwise. Use vmm_ms_scenario_gen::get_ms_scenario_gen() to retrieve a sub-generator under a specified name. VMM Additions and Enhancements 277 .vmm_ms_scenario_gen::ms_scenario_gen_exists() Checks if a generator is registered under a specified name SystemVerilog virtual function bit ms_scenario_gen_exists(string name) Description Returns TRUE if there is a sub-generator registered under the specified name.

VMM Additions and Enhancements 278 . Issues a warning message and returns NULL if there are no generators registered under that name.vmm_ms_scenario_gen::get_ms_scenario_gen() Get the sub-generator registered under a specified name SystemVerilog virtual function vmm_ms_scenario_gen get_ms_scenario_gen( string name) Description Returns the sub-generator registered under the specified name.

VMM Additions and Enhancements 279 .vmm_ms_scenario_gen::get_ms_scenario_gen_name( ) Get a names under which a generator is registered SystemVerilog virtual function string get_names_by_ms_scenario_gen( vmm_ms_scenario_gen gen) Description Returns a names under which the specified sub-generator is registered. Returns "" if the generator is not registered.

vmm_ms_scenario_gen::get_names_by_ms_scenario _gen() Get the names under which a generator is registered SystemVerilog virtual function int get_names_by_ms_scenario_gen( vmm_ms_scenario_gen gen. ref string name[$]) Description Appends the names under which the specified sub-generator is registered. Returns the number of names that were added to the array. VMM Additions and Enhancements 280 .

VMM Additions and Enhancements 281 . Returns the number of names that were added to the array.vmm_ms_scenario_gen::get_all_ms_scenario_gen_na mes() Get all the names in the generator registry SystemVerilog virtual function int get_all_ms_scenario_gen_names( ref string name[$]) Description Appends the names under which a sub-generator is registered.

vmm_ms_scenario_gen::replace_ms_scenario_gen() Replace a sub-generator SystemVerilog virtual function void replace_ms_scenario_gen(string name. The same generator may be registered multiple times under different names. thus creating an alias to the same sub-generator. VMM Additions and Enhancements 282 . vmm_ms_scenario_gen gen) Description Registers the specified sub-generator under the specified name. replacing the generator previously registered under that name (if any).

vmm_ms_scenario_gen::unregister_ms_scenario_gen () Unregister a sub-generator SystemVerilog virtual function bit unregister_ms_scenario_gen( vmm_ms_scenario_gen gen) Description Completely unregisters the specified sub-generator and returns TRUE if it exists in the registry. VMM Additions and Enhancements 283 .

Returns NULL if there is no generator registered under the specified name.vmm_ms_scenario_gen::unregister_ms_scenario_gen _by_name() Unregister a sub-generator SystemVerilog virtual function vmm_ms_scenario_gen unregister_ms_scenario_gen( string name) Description Unregisters the generator under the specified name and returns the unregistered generator. VMM Additions and Enhancements 284 .

based on the names and instance names. regardless of their location in the class hierarchy.vmm_xactor_iter This class can iterate over all known vmm_xactor instances. Summary • • • • vmm_xactor_iter::new() vmm_xactor_iter::first() vmm_xactor_iter::xactor() vmm_xactor_iter::next() VMM Additions and Enhancements 285 .

if ($cast(ahb. end VMM Additions and Enhancements 286 .. “vmm_xactor_iter::first()”is implicitly called. SystemVerilog function void new(string name string inst = "/.vmm_xactor_iter::new() Create a new transactor iterator. using the “vmm_xactor_iter::next()” method./"). = "/. The subsequent transactors can be iterated on. So once created.next(). they are interpreted as the full name or instance name to match.. Examples Example 10-16 vmm_xactor_iter iter = new("/AHB/"). the first transactor matching the specified name and instance name patterns is available using the “vmm_xactor_iter::xactor()” method. while (iter. Description Create a new transactor iterator and initialize it using the specified name and instance name. If the specified name or instance name is enclosed between ’/’ characters./". one at a time. Otherwise. iter. their are interpreted as regular expressions.xactor() != null) begin ahb_master ahb.xactor()) begin . end iter.

The order in which transactors are iterated on is unspecified. VMM Additions and Enhancements 287 .vmm_xactor_iter::first() Reset the iterator to the first transactor. Description Reset the iterator to the first transactor matching the name and instance name patterns specified when the iterator was created using vmm_xactor_iter::new() and return a reference to it. if found. Returns null if no transactors match. SystemVerilog function vmm_xactor first().

SystemVerilog function vmm_xactor xactor(). Description Return a reference to a transactor matching the name and instance name patterns specified when the iterator was created using vmm_xactor_iter::new(). VMM Additions and Enhancements 288 . Returns null if no transactors match.vmm_xactor_iter::xactor() Return the current transactor iterated on.

SystemVerilog function vmm_xactor next().vmm_xactor_iter::next() Move the iterator to the next transactor. The order in which transactors are iterated on is unspecified. Returns null if no transactors match. VMM Additions and Enhancements 289 . if found. Description Move the iterator to the next transactor matching the name and instance name patterns specified when the iterator was created using vmm_xactor_iter::new() and return a reference to it.

matching a specific name and instance name. A variable named "xact" of the type specified as the first argument to the macro is implicitly declared and iteratively set to each transactor of the specified type that matches the specified name and instance name..). end end VMM Additions and Enhancements 290 . The macro must be located immediately after a "begin" keyword.. "/. name../". end Description Short-hand macro to simplify the creating and operation of a transactor iterator instance. inst) begin xact. The subsequent statement is executed for each transactor iterated on. Examples Example 10-17 Iterating over all transactors of type "ahb_master" begin ‘foreach_vmm_xactor(ahb_master.‘foreach_vmm_xactor() Short-hand transactor iterator macro.register_callback(. SystemVerilog ‘foreach_vmm_xactor(type./") begin xact. looking for transactors of a specific type.. "/.

issued by the specified message service interface instances. string text = ""). User-defined message handlers are considered in reverse order of installation i. string inst = "". A user-defined message handler may choose to explicitly issue the message using the vmm_log_catcher::issue() method or throw the message back to the message service by using the vmm_log_catcher::throw() method to be potentially caught by another suitable message handler or be issued. catches all messages issued by this message service interface instance.e. By default. VMM Additions and Enhancements 291 . Description Install the specified message handler to catch any message of the specified type and severity.vmm_log::catch() Add a user-defined message handler SystemVerilog function int catch( vmm_log_catcher catcher. A unique message handler identifier is returned that can be used to later uninstall the message handler using vmm_log::uncatch(). int severity = ALL_SEVS. int typs = ALL_TYPS. which contains the specified text. messages are handed off to the vmm_log_catcher::caught() method and will not be issued. string name = "". bit recurse = 0. the last handler installed will be considered first. Messages will be considered caught by the first user-defined handler found that can handle the message. Once caught.

the modified message will trigger applicable watchpoints.Watchpoints are triggered after message catching. VMM Additions and Enhancements 292 . If the message has been modified in the catcher. if any.

It enables runtime selection of the testcase to run on an environment.vmm_test This base class may be used to implement testcases. Summary • • • • • • • vmm_test::log vmm_test::new() vmm_test::get_name() vmm_test::get_doc() vmm_test::run() vmm_test_begin() vmm_test_end() VMM Additions and Enhancements 293 .

The name of the message service interface is "Testcase" and the instance name is the name specified to the vmm_test::new() method. VMM Additions and Enhancements 294 . Description Message service interface instance that can be used to issue messages in the vmm_test::run() method. SystemVerilog vmm_log log.vmm_test::log Message service interface for the testcase.

function new(). A short description of the testcase may also be specified.. endtask endclass VMM Additions and Enhancements 295 . its message service interface and registers it in the global testcase registry under the specified name.new("my_test"). SystemVerilog function new(string name. virtual task run(vmm_env env). Description Create an instance of the testcase. super. . endfunction static my_test this_test = new(). string doc = "")..vmm_test::new() Create a test. Examples Example 10-18 class my_test extends vmm_test.

super. SystemVerilog function string get_name(). function new(). virtual task run(vmm_env env).vmm_test::get_name() Get the name of a test. .. endfunction static my_test this_test = new()..get_name()}). {"Running test ". ‘vmm_note(this. Examples Example 10-19 class my_test extends vmm_test.new("my_test").log. Description Return the name of the test that was specify in the constructor. endtask endclass VMM Additions and Enhancements 296 . this.

new("my_test"). super. {"Running test ".vmm_test::get_doc() Get the description of a test. endfunction static my_test this_test = new(). virtual task run(vmm_env env).get_name()}). . ‘vmm_note(this.. this. SystemVerilog function string get_doc(). function new().. Description Return the short description of the test that was specify in the constructor.log. endtask endclass VMM Additions and Enhancements 297 . Examples Example 10-20 class my_test extends vmm_test.

my_env. my_env.vmm_test::run() Run a test.build(). my_env. env).run().run(). Examples Example 10-21 class my_test extends vmm_test..run(). Description The test itself.. virtual task run(vmm_env env). If a different test implementation is required. SystemVerilog virtual task run(vmm_env env). tb_env my_env.stop_xactor(). This method should not call vmm_log::report(). the default implementation of this method must not be invoked using super. .gen[0]. $cast(my_env. endtask endclass VMM Additions and Enhancements 298 . The default implementation of this method calls env.

The second argument is the name of the environment class that will be used to execute the testcase. envclassname. It must be preceeded by any import statement required by the test implementation.env". This macro can then be followed by variable declarations and procedural statements. The third argument is a string documenting the purpose of the test. VMM Additions and Enhancements 299 . The instance of the verification environment of the specified type can be accessed as "this. ready to be used.vmm_test_begin() Short-hand macro to define a testcase class. The first argument is the name of the testcase class and will also be used as the name of the testcase in the global testcase registry. Examples This example shows how the testcase from Example 2-72 and Example 2-75 can be implemented using short-hand macros Example 10-22 import tb_env_pkg::*. A data member of that type named "env" will be defined and assigned. doc string) Description Short-hand macro that may be used to define a user-defined testcase implemented using a class based on the vmm_test class. SystemVerilog ‘vmm_test_begin(testclassname. This macro can be used to create the testcase class up to and including the declaration of the vmm_test::run() method.

‘vmm_test_begin(my_test, tb_env, "Simple test") this.env.build(); this.env.gen[0].stop_xactor(); this.env.run(); ‘vmm_test_end(my_test)

VMM Additions and Enhancements 300

vmm_test_end()
Short-hand macro to define a testcase class.

SystemVerilog
‘vmm_test_end(testclassname)

Description
Short-hand macro that may be used to define a user-defined testcase implemented using a class based on the vmm_test class. The first argument must be the same name specified as the first argument of the vmm_test_begin() macro. This macro can be used to end the testcase class, including the implementation of the vmm_test::run() method.

Examples
This example shows how the testcase from Example 2-72 and Example 2-75 can be implemented using short-hand macros Example 10-23
‘vmm_test_begin(my_test, tb_env) this.env.build(); this.env.gen[0].stop_xactor(); this.env.run(); ‘vmm_test_end(my_test)

VMM Additions and Enhancements 301

vmm_ms_scenario::get_channel()
Get a registered output channel.

SystemVerilog
function vmm_channel get_channel(string name)

Description
Get the output channel registered under the specified logical name in the multi-stream generator where the multi-stream scenario generator is registered. Returns NULL of no such channel exists.

VMM Additions and Enhancements 302

vmm_channel
The following function and task have been added to the vmm_channel base class: • • vmm_channel::record() vmm_channel::playback()

VMM Additions and Enhancements 303

vmm_channel::record()
Records transaction descriptions, relative flow sequence, and timing in the specified file. Syntax
function bit record(string filename);

Description Starts recording the flow of transaction descriptors through the channel instance in the specified file. The vmm_data::byte_pack() or vmm_data::save() method must be implemented for the flowing transaction descriptors. A transaction descriptor is recorded when it is injected into the channel by the vmm_channel::put() or vmm_channel::sneak() method. Recording is also done when an attempt is made to vmm_channel::unput() a transaction descriptor from the channel. This function works as an ON-OFF switch. When called with a valid filename, it turns ON recording of transactions. When called with a null (empty string) filename, recording is stopped. Calling this function with a valid filename while recording is ON results in a warning, and no action is taken. Likewise, calling this function with a null (empty string) filename while recording is OFF results in a warning, and no action will be taken. This function returns TRUE if recording was successful. While recording is on, RECORDING notification is indicated by vmm_channel::notify().

VMM Additions and Enhancements 304

Usage Example
string filename = "./record.dat"; xactor.in_chan.record(filename); //start recording // Information about all transactions flowing through // "xactor.in_chan" will be recorded in ’filename’ … xactor.in_chan.record(""); //stops recording

VMM Additions and Enhancements 305

vmm_channel::playback()
Executes the recorded transaction operations into the channel instance.

Syntax
task playback(output bit success, input string filename, input vmm_data factory, input bit metered = 0);

Description
This task executes the recorded transaction operations (put/unput/ sneak), in the same sequence in which they were recorded, into the channel instance. It acts as a producer for the channel instance. Playback does not have to happen in the same simulation run as recording: it can be executed in a different simulation run. The vmm_data::byte_unpack() or vmm_data::load() method, must be implemented for the transaction descriptor, passed to the factory argument. You must provide a non-null factory argument, of the same transaction descriptor type as that with which recording was done. The transaction descriptors are played back one by one in the order specified in the file. If the metered argument is TRUE, the transaction descriptors are played back (that is, by sneak/put/ unput) to the channel in the same relative simulation time interval as the one in which they were originally recorded. While playback is executing on a channel, all other sources of the channel are locked (vmm_channel::put is not allowed from any other source). Sneak is still allowed from other sources, but a warning is printed on any such attempt.

VMM Additions and Enhancements 306

data_packet factory. PLAYBACK_DONE notification is indicated by vmm_channel::notify()./record. vmm_channel bit metered."vmm_channel::playback() function failed").playback( //this. bit success. then success is set to FALSE. // Other start code … `ifndef PLAY_DATA this.success) `vmm_error(this. VMM Additions and Enhancements 307 .filename. // Playback with same timing as recording endfunction task start(). or an empty file. Example Example 10-24 string filename = ".start_xactor(). //this.this.metered). When playback is completed. … factory = new./record.factory. If playback encounters an error condition such as a null (empty string) filename. class packet_env extends vmm_env. string filename = ".in_chan. … function new(). a corrupt file.dat".generator.success.xactor. `else fork begin //Start playback this.Output parameter success is set to TRUE if the playback was successful.this. if(!this.dat".log. metered = 1’b1.

end join_none `endif endtask endclass::packet_env VMM Additions and Enhancements 308 .

vmm_ral_block_or_sys Base Class Additions The following functions have been added to the the vmm_ral_block_or_sys class: • • “vmm_ral_block_or_sys::set_offset()” “vmm_ral_block_or_sys::get_reg_by_offset()” VMM Additions and Enhancements 309 .

vmm_ral_block_or_sys::set_offset() Modify the base address of the block or system. the behavior of the RAL model will be different from the RALF specification. Note that after using this method. It is not possible to relocate the base address of the top-level system because is it not instantiated anywhere. string domain = "") Description Dynamically relocate the base address of the specified domain in the block or subsystem in the address space of the immediately instantiating system. Returns TRUE of the relocation was succesful. The new address range for the block or subsystem must not be occupied by another block or subsystem. SystemVerilog virtual function bit set_offset(bit [63:0] offset. VMM Additions and Enhancements 310 . Returns FALSE if the specified domain does not exist in the immediately enclosing system or the new base address creates an overlap between this block or subsystem address range and another block or subsystem.

this function looks for the start (lowest) address of the register’s address space. returns NULL. which takes more memory than the default version. If no register is found at the specified offset. In the default (slower) version. The entire register may occupy more than one offset within the address space of the block or system if it is wider than the physical interface. short-circuiting the search wherever possible. to check if a register exists at the specified block/system level offset/address. VMM Additions and Enhancements 311 . SystemVerilog virtual function vmm_ral_reg get_reg_by_offset( bit [63:0] offset. string domain = "") Description Finds the register located at the specified offset within the block or system address space in the specified domain and returns its descriptor.vmm_ral_block_or_sys::get_reg_by_offset() Gets the register at the specified offset in this block or system. all registers of the underlying blocks and subsystems are searched. In such cases. This function has a default version and a faster version.

which helps to speed up the search. due to caching. Memory consumption is higher in the faster version. VMM Additions and Enhancements 312 . You can activate the faster version by defining the runtime macro VMM_RAL_FAST_SRCH.The faster version uses associative arrays to cache block level register offsets. given an offset.

The hvp annotate command and most of its switches can be used for back-annotation the same way that they are used with the spreadsheet annotator.doc) documents. The . VMM Planner MS Word Annotation 303 .doc verification plan. Note: Unlike the VMM Planner Spreadsheet annotator flow. and back-annotation of coverage and other scores into the . Either MS-Word 2003 or later can be used to create the .11 VMM Planner MS Doc Annotation 1 The VMM Planner Doc annotator enables creation of verification plans using Microsoft Office (.doc plan. the Word Doc flow does not currently support OpenOffice input.doc verification plan must be formatted properly with predefined styles and keywords built into the VMM Planner Doc annotator. Back-annotation is an extension of the existing VMM Planner Spreadsheet annotator flow.

charts. text alignment. VMM Planner MS Word Annotation 304 . The same doc XML file is used by VMM Planner as a verification plan and as an annotated report.This section contains the following topics: • • • • • • “Introduction” on page 304 “Use Model” on page 305 “hvp annotate Command Arguments” on page 307 “Capturing a Verification Plan in Doc XML Format” on page 310 “Debugging the Doc Plan” on page 319 “How to Get Scores Back-Annotated in the Doc” on page 322 Introduction The VMM Planner Doc annotator is used: • • To provide simple hooks in MS Word-compliant documents to interface with VMM Planner-enabled applications. To provide flexibility in formatting verification plan doc XML for nicely formatted coverage reports. tables and descriptions are applied in both the plan and the annotated output report. Formatting features such as selectable fonts. graphics.

Use Model Figure 11-1 Word Doc annotator use model External Doc Plan XML .hvp Files External Debugging External Doc XML Synopsys Unified Coverage Database hvp annotate Annotated External Doc XML HVP User Data This section contains the following topics: • • • • “Process Flow” on page 306 “License Model” on page 306 “Supported Platforms” on page 307 “Compatibility with the VMM Planner Spreadsheet Annotation Flow” on page 307 VMM Planner MS Word Annotation 305 .

Even if you do not see any errors.xml.xml to see the annotated scores. and copying and pasting Synopsys-defined tables.Process Flow 1. 2. Capture your verification plan in Doc XML format.06 Beta is a Beta feature. open the filename. This is typically done by starting with a Synopsys-provided template file and marking key paragraphs in the created doc with Synopsys-defined styles. 5.xml file and check to make sure that VMM Planner processed your verification plan hierarchy and contents as you intended. this debug check step can be skipped when annotating with new coverage databases. covdb. VMM Planner MS Word Annotation 306 . You can find more error information in filename. If there are no errors. Run hvp annotate with the XML plan.dbg. Fix any errors you see. 4. open filename. Prepare Synopsys coverage database and HVP user data files. so a Beta license key is needed in order to use the Doc XML annotation flow. License Model VMM Planner in C-2009. This debug check process only needs to be done on newly created or recently edited plans. Once the plan becomes stable. 3. userdata and other desired switches.ann.dbg.

When an XML plan file is specified in -plan planfile. The hvp annotate command is completely backward compatible with the existing VMM Planner Spreadsheet annotator. VMM Planner automatically detects the XML file format and invokes the proper process depending on the format of the XML.Supported Platforms linux amd64 suse32 suse64 sparc64 sparcOS5 Compatibility with the VMM Planner Spreadsheet Annotation Flow The VMM Planner Spreadsheet annotator flow and Doc annotator flow share the hvp annotate command and most of its switches. hvp annotate Command Arguments Syntax hvp annotate -plan planfile [-h] [-mod hvpfiles] [-plan_out annfile] [-feature "hierarchies"|-featurefile txtfile] [-dir covdbpath|-f txtfile] [-userdata vedata|-userdatafile txtfile] [-userdata_out outvedata] VMM Planner MS Word Annotation 307 .

[-metric_prefix prefix] [-group ratio|merge_across_scopes] [-show_ratio] [-show_incomplete] [-v] [-q] Options -plan planfile Spreadsheet. Specify HVP scopes that you want to annotate with the given covdb coverage database or ve.xml extension is generated.. Example: -plan myplan.data are annotated to entire plan.. Enclose the string with double quotes. if -hier is not used. Example: -mod override. covdb and ve. **. doc XML or HVP file for your verification plan. Multiple scopes can be specified.]" VMM Planner MS Word Annotation 308 .hvp filter. They are applied in the order in which they are entered.ann. ?) can be used.hvp -mod hvpfiles -plan_out annfile Specify the name for the output annotated spreadsheet or doc XML file. This switch is mandatory. and wildcards (*. -feature "hierarchy [hierarchy.xml -h Show this help message and exit. Filter or override files in HVP language format multiple files can be specified. If -plan_out is not entered. a file with the original filename and . Subhierarchies of matched scopes are automatically annotated.data.

separated by commas.*" -featurefile txtfile A text file that contains list of hierarchical filters. -userdata_out outvedata -metric_prefix prefix -group ratio | merge_across_scopes VMM Planner MS Word Annotation 309 . Specify the path to a Synopsys coverage database (cm.txt bugcount.Example: -feature "myplan. vdb).rec_feat. Multiple paths can be entered. separated by commas. Dump an annotated score of all measures into the specified outvedata user data file.play_feat. Example: -dir wishbone. The given prefix is used to change a metric name in the output user database file used by -userdata_out. Example: -userdata result.* myplan.vdb -dir covdbpath -f txtfile Specify a text file that contains list of covdb coverage database paths.data file path.cm wishbone.txt -userdata vedata -userdatafile txtfile Specify a text file that contains a list of user database file paths. Specify a ve. Multiple paths can be entered.

A template document VMM Planner MS Word Annotation 310 . VMM Planner extracts the contents and their styles to establish the HVP hierarchy. -show_incomplete -v -q Capturing a Verification Plan in Doc XML Format This section contains the following topics: • • • “Built-In Styles” on page 310 “Table Keyword” on page 314 “Other Contents” on page 319 Built-In Styles In the Doc XML plan template. Quiet mode: Turn off all warning messages. there are predefined styles that are prefixed with “HVP”.-group ratio: Aggregate the group metric score as a ratio type (covered/coverable) instead of as a percent. -show_ratio Display ratio type scores in a ratio form instead of a percent. Indicate incomplete scores with [inc]. Verbose mode: Show progress status messages. -group merge_across_scopes: Merge the group score across scopes.

Use this style only once in the plan. typically at the very top of the document. HVP Plan Style Content with the style “HVP Plan” is assigned as the name of the HVP Plan.containing predefined styles is provided with the VMM Planner Doc annotator. Make a copy of that template and then use your copy as a basis to create a new plan. VMM Planner MS Word Annotation 311 .

which means that “HVP Feature 1” can be followed by another “HVP Feature 1” or “HVP Feature 2”. If “HVP Feature 2” is found. for example. You cannot create a plan with more than nine levels of features. VMM Planner MS Word Annotation 312 . This limited number of styles also limits the number of levels of hierarchical depth in a verification plan.HVP Feature 1 to HVP Feature 9 There are nine levels of “HVP Feature” styles. which are used to represent HVP feature hierarchy. if one exists. it will be sibling of the previous “HVP Feature 1”. the feature will be a subfeature of the previous “HVP Feature 1”. The index must be seamless in terms of hierarchy. but not by “HVP Feature 3” or “HVP Feature 4”. If “HVP Feature 1” is found.

Since VMM Planner does not allow the same instance name in the same node. which is the same syntax as in the HVP language. you must add one more feature level to instantiate multiple subplans with the same plan. You can also pass attributes and annotation value overrides the using #() syntax. as shown in the following example. VMM Planner MS Word Annotation 313 .You can also use “HVP Feature number” for subplan declaration. To instantiate a subplan. use subplan name-of-plan.

You can also use an “HVP Assignment” table to override description values. VMM Planner looks at the contents in the first cell of the table. The following keywords are reserved: • • • • • “HVP Assignment” on page 315 “HVP Measure name” on page 315 “HVP Metric name” on page 317 “HVP Attribute name. and determines whether the table needs to be interpreted as part of the HVP hierarchy.HVP Description The paragraph with the “HVP description” style is extracted as the built-in description attribute in the HVP feature. Table Keyword When a table is found. HVP Annotation name” on page 318 “HVP Include File” on page 319 VMM Planner MS Word Annotation 314 .

VMM Planner searches for the names of attributes. The left cell must have the name of an attribute or annotation to override the value of the name or annotation. annotations. or the name of a metric to override a goal expression. HVP Measure name The table with the HVP Measure name keyword in the first cell is used to declare HVP measure statements. The keyword cell is followed by two-column rows. annotations and goals for metrics. VMM Planner MS Word Annotation 315 . annotations or metrics in this table must be defined in the plan. Otherwise. All names of attributes. HVP Assignment phase owner 2 Snps Note: Although the HVP language is case sensitive. because Word sometimes capitalizes the first character of a word. then VMM Planner automatically generates a measure name. If no measure name is entered. VMM Planner generates warnings and ignores the undefined names.HVP Assignment A table with an “HVP Assignment” style is used to override attributes. and metrics in its definition tables with case-insensitive matching. You can specify a unique measure name or leave it blank.

testbench::cpu::cpu_cov. The annotation process fills each empty cell with its score. with a metric name in the left cell of each of those rows. You specify at least one source string.The keyword cell is followed by two-column rows. To specify multiple sources. After the source row. or add multiple rows with the source keyword in the left cell of each row. Leave the right cell empty. you can list multiple source strings in the same cell separated by commas.my_cpu0 VMM Planner MS Word Annotation 316 . group: memsys_test_top2 group: memsys_test_top group: memsys_test_top2 group instance: memsys_test_top. HVP Measure m1 source Group HVP Measure source source Group HVP Measure source Group Assert group: memsys_test_top. append one or more two-column rows.

real. a unique metric name must be specified after HVP Metric (“bugs” in the example table below). The following are rules for creating an HVP metric table: • • One table per one metric definition. . percent.HVP Metric name A table with an HVP Metric name keyword in the first cell is used to define an HVP metric. ratio. HVP metric bugs type aggregator goal Integer Sum bugs < 3 VMM Planner MS Word Annotation 317 . Following the first row. Aggregator can be one of: sum. Rows for type and aggregator are mandatory. min. use two-column rows with predefined keywords in the left cell.}.. In the keyword cell. enum {entry1. Goal is an expression for the coverage goal.. average. Type can be one of: integer. A row for goal is optional. Not all entries are available for all types. max. entry2. See “Using the HVP Language” for more information.

respectively. two-column rows with predefined keywords type and default in the left cells.}. . Following the first row. real. and “spec” in the second example table). Type can be one of: integer.. In the keyword cell. HVP attribute phase type default Integer 1 HVP annotation spec type default String VMM Planner MS Word Annotation 318 . • Default is the default value of the attribute or annotation.. a unique name must be specified after the HVP Attribute or HVP Annotation keyword (“phase” in the first example table below. enum {entry1. The following are rules for creating an HVP metric table: • • One table per one definition. percent. HVP Annotation name A table with an HVP Attribute name or HVP Annotation name keyword in the first cell is used to define an HVP attribute or annotation. use two. ratio. entry2.HVP Attribute name.

HVP Include File A table with the HVP Include File keyword in the first cell is used to declare other XML plans to be included as subplans.xml dram_wordplan.doc verification plan. and appears in the annotated plan exactly as it appears in the original plan document. The XML plans that are included in this table can be used as subplans. is ignored during the annotation process. and charts. Formatting is limited to the formatting features that are allowed in Microsoft Word 2003 XML . that is neither in a predefined HVP style nor in a table with a predefined keyword. You might.doc format. select the wrong style.xml Other Contents All other content such as text. images. for example. it is difficult to find where the error occurred. HVP include file sram_wordplan. Add as many one-column rows containing XML filenames as you need. incorrect styles. Debugging the Doc Plan When an error is detected in a . not knowing that VMM Planner MS Word Annotation 319 . and so on. In addition. VMM Planner might interpret your verification plan in a different way than what you intended or expected due to reasons such as typographic errors. This is because the paragraph styles are essentially invisible in the normal WYSIWYG view of the document.

If you do not see [Style|Table] where you expect to see it. When you run hvp annotate.dbg.xml is created for each plan file. [Style|Table]. indicates that the section was either a predefined HVP style or a predefined HVP table.dbg. Several examples are shown below. there is an error in your HVP file such as a wrongly used style or a typographic error. a filename. VMM Planner MS Word Annotation 320 . This section contains the following topics: • • “[Style|Table] Keyword Indicator” on page 320 “Unique Error Code in Error Messages” on page 322 [Style|Table] Keyword Indicator In the filename.VMM Planner will not recognize the paragraph properly.xml. which provides detailed debugging information. a blue term enclosed in square brackets.

VMM Planner MS Word Annotation 321 .

Unique Error Code in Error Messages The following error while running hvp annotate indicates that an invalid metric.xml.xml files.dbg.ann.xml is produced.xml:ERR001: Invalid metric name(Group1) was used in Measure(_m1) in Feature(1. then VMM Planner produces filename. you can open the file named memsys_wordplan.xml and search for the ERR001 string. Group 1. If your plan does not include any subplans.xml and so on.2. then only one filename. ERR001 is a unique string in the filename. VMM Planner produces one filename.dbg. so you can easily find the location of the error. How to Get Scores Back-Annotated in the Doc Running hvp annotate. Then you can open the original plan and edit it to fix the error. was found at the location of ERR001: Error:[DOC_060] memsys_wordplan.ann. filename.1. cpu1) To find where Group1 was used. creates one or more filename. VMM Planner MS Word Annotation 322 .xml file. If a plan is used as subplan multiple times.ann.xml file per plan or subplan instance in the HVP hierarchy.2.ann.ann.

Red indicates that the goal was not met • If no goal was specified: For Synopsys coverage. Each score cell in the score summary table is filled in with a color determined by the score and the goal. .xml file and navigate to any subplan . .*.Green indicates 100% coverage . You can open only the top-level plan .Red indicates 0% coverage .xml from there.It is not necessary to open the *ann. This section contains the following topics: • • • “Plan/Feature Score Summary” on page 323 “Measure Score Table” on page 324 “Navigating Down to a Subplan” on page 325 Plan/Feature Score Summary Running hvp annotate produces a score summary table for each plan or feature.ann.xml file to view a subplan. The meanings of the colors are: • If a goal was specified.A coverage score between 0 and 100% is indicated by one of six different colors (see the Unified Coverage Reporting User Guide for information about setting the colors) VMM Planner MS Word Annotation 323 .Green indicates that the goal was met .ann.

the score cell is colored using the same scheme as the “Plan/Feature Score Summary”. . Measure Score Table In the measure score table.Red indicates a pass/total ratio of 0 (0%) . If no score is available.Green indicates a pass/total ratio of 1 (100%) . then the cell contains “N/A”. VMM Planner MS Word Annotation 324 .For a test metric.A coverage score between 0 and 100% is indicated by one of six different colors (see the Unified Coverage Reporting User Guide for information about setting the colors) Some examples are shown below.

appears in front of any source string that does not match any of the regions in the coverage database or user data. Hold down Ctrl and click the subplan name (for example.If the –show_incomplete switch is used. in orange. Navigating Down to a Subplan In a filename. VMM Planner MS Word Annotation 325 .xml file for the subplan instance.xml file. clicking on a subplan name that uses the HVP Feature style opens the ann. the name starting with subplan sram_plan in the example below) to open the file. “[incomplete]”.ann.

VMM Planner MS Word Annotation 326 .

12 URG Enhancements This chapter contains the following sections: • • • “New URG Features and Changes” on page 327 “License Model” on page 333 “Platform Support” on page 333 1 New URG Features and Changes The following section contains a summary of each enhancement: • • • “Improved HTML Page Format” on page 328 “Incompleteness Checks” on page 329 “Omitting Filtered Features” on page 330 URG Enhancements 327 .

the HVP pages are more consistent with other URG data pages. Also.html page format. This allows for more information to be displayed per page.html page.html page format has been changed to the more compact format used by the hierarchy. With these changes. which reduces the amount of scrolling necessary to read the report. Figure 12-1 shows an example of the new hvp*.html pages can be sorted by column. linear tables on the feature*.• • • • • “Dumping User Data” on page 330 “Predictable Page Naming Convention” on page 331 “Add New Hyperlinks from group bin and group instance” on page 331 “New –show hvpprob Command for Problem Reports” on page 332 “Test Metric Coloring” on page 332 Improved HTML Page Format The hvp*. URG Enhancements 328 .

then determines the cause of the warnings. Other HVP applications that load both the . Use Model The user runs URG and observes warning messages about unbound source statements. After fixing the code and the plan. the user runs URG again. enabling the user to identify and correct those problems.hvp plan and the coverage database can compare those measure sources against the database and highlight problems where no match is found. URG Enhancements 329 .Figure 12-1 hvp*. This is repeated if there are more incompletness warnings.html page format Incompleteness Checks You can bind HVP features to coverage regions via the measure statement of the HVP file.

Use Model When questions arise about how top level scores are reported. but it still displayed them in the report as null/grey features. resulting in visual clutter. URG did not annotate those pruned branches.html pages to drill down to the raw ve. allowing you to drill down all the way to the raw data. resulting in a more concise and usable report. when such a fliter was applied. you must also provide text files (userdata) containing the raw data. That user-defined data is dumped to the HVP report and hyperlinks are inserted from the measure sources to the new raw data report. the user can invoke multiple URG runs. For multiple filtered reports of the same master design. This provides a more complete report. Those filtered features are removed altogether. Previously.Omitting Filtered Features A core feature of all HVP applications is the ability to filter out or prune branches of the verification plan. the user can use the hyperlinks pointing from the feature*.data listings. URG Enhancements 330 . In conjunction with those extended metrics. Dumping User Data HVP allows you to extend the set of metrics measured by the plan. Use Model The user can enter the –mod command line argument to supply a filter modifier.

A. URG Enhancements 331 . After URG is run. There was no easy way to know in advance which feature was placed on which page. Previously. For example.html. you could form a URL like feature named.html and feature123. those pages had serialized names like hvp1. URG has been enhanced with a predictable naming convention based on the actual feature hierarchy so that users can translate a feature’s absolute name into a URL. to produce an external document containing the results for feature A. This feature is exploited in the hvp annotate application allowing MS Word and MS Excel documents to hyperlink to URG reports.B.html.C.The –userdata runtime option specifies user-defined data sources Predictable Page Naming Convention Users may want to directly reference specific hvp* and feature* pages in the URG report from other programs.C. That deficiency has been corrected. the urgReport would contain a file with that name. enabling drill-down debug and raw data queries. the user must know the absolute path in terms of feature names to reach the feature that they seek. the metric source types group bin and group instance were not properly hyperlinked to their respective raw data pages. Use Model To reference HVP results from external documents. Add New Hyperlinks from group bin and group instance Previously.B. and reference that directly.

URG Enhancements 332 . The -show hvpprob option produces a report that omits all non-problem features. There is an implication that the metric’s default coverage score should be based on a percentage of passes over the total number of tests. Use Model When the –show hvpprob option is used. If the user overrides the default test metric goal then coloring reverts to the binary red/green cell coloring. New –show hvpprob Command for Problem Reports When a user has a very large plan that is nearing tapeout.Use Model Hyperlinks can be used to drill down to raw functional coverage information. A problem is defined as a feature that fails the goals set for one or more of its metrics. This feature computes that percentage and then applies the default red-yellow-green spectrum of colors that are used for other URG metrics.html report shows only the problems. the default hvp*. it might be helpful to view a report that contains only problems. Test Metric Coloring The built-in test metric is an enum metric type.

Platform Support linux amd64 suse32 suse64 sparc64 sparcOS5 aix URG Enhancements 333 .License Model The –lca command line flag is required to invoke any HVP feature within URG.

URG Enhancements 334 .

12 Run Command This chapter describes the options added in the run command in this release. Syntax run [0] run [-delta] run [-nba] [0] Run Command 347 . 1 run Command The run command runs all the simulation time units.

This ensures all deltas (sched0 queues) are executed and all blocking assignments are completed. Run Command 348 . all such events are processed until things stabilizes at the end of current time. before process execution for the last delta. The simulation stops after signal update phase. [-delta] Runs one set of deltas at a time and stops before the next delta. You can inspect values of newly deposited signals/variables at that time..Runs all of the deltas of a particular simulation time and stops just before the end of that simulation time. If there are no more events. the simulation advances to the next time step and stops at the end of the first delta of the new time step. The simulation advances to the next delta and return to UCLI soon after the signal update phase (before process execution). This command is useful for delta cycle level debugging especially when it comes to viewing values instantaneously due to forces and values propagation or debugging races. If UCLI generates more events by forces or release etc. The simulation goes into interactive mode right before the NBA queue starts executing during SemiLER queue execution. [-nba] Runs all deltas and stops before a new NBA (non-blocking assignments).