VCS® / VCS® MX Beta Feature Descriptions

Version C-2009.06 Beta December 2008

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Contents
1. VCS SystemVerilog Features SystemVerilog Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . Parameterized Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . String Casting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Array Literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemVerilog Linked Lists . . . . . . . . . . . . . . . . . . . . . . . . . . New SystemVerilog Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Task and Function Calls Using Virtual Interface Variables. . . The $typename Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fine-Grained Process Control Using the process Class . . . . Assignment Patterns Using %p . . . . . . . . . . . . . . . . . . . . . . . Signal Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nested Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ’__FILE__ and ’__LINE__ Compiler Directives . . . . . . . . . . . Extension to SystemVerilog $readmemb/$readmemh . . . . . . . . Loading Memories with $readmemb and $readmemh. . . . . . 13 14 16 16 18 19 19 20 22 30 32 33 34 35 35

1

2. Assertions Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overlapping Operators in Multiclock Environment . . . . . . . . . . . Deferred Immediate Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . Property Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weak and Strong Sequence Operators . . . . . . . . . . . . . . . . . Implication and Equivalence Operators . . . . . . . . . . . . . . . . . until Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nexttime Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . always Operator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eventually Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . followed-by Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed Strength Property Reporting . . . . . . . . . . . . . . . . . . . . Modeling Abort Conditions: accept_on, reject_on . . . . . . . . . Inferred Value Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recursive Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Variable Initialization and Input . . . . . . . . . . . . . . . . . . . . . Global Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Past and Future Sampled Value Functions . . . . . . . . . . . . . . let Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Support for New Constructs . . . . . . . . . . . . . . . . . . . . Note on Cross Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 43 44 44 45 46 47 47 48 48 49 50 51 52 52 54 54 57 57 57 58

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3. Coverage Enhancements SystemVerilog Language Enhancements . . . . . . . . . . . . . . . . . . Wildcard Support in binsof Expressions . . . . . . . . . . . . . . . . Wildcard Array Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Bin Names as States in Transition Sequences . . . . . . . OpenVera Language Enhancement . . . . . . . . . . . . . . . . . . . . . . Wildcard Support in binsof Expressions . . . . . . . . . . . . . . . . Coverage Exclusion Enhancement . . . . . . . . . . . . . . . . . . . . . . . Understanding Half-Toggle Exclusion . . . . . . . . . . . . . . . . . . Unified Coverage Reporting Enhancements . . . . . . . . . . . . . . . . Reporting Only Uncovered Objects . . . . . . . . . . . . . . . . . . . . Understanding Covergroup Page Splitting. . . . . . . . . . . . . . . DVE Coverage Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . Branch Coverage and Implied Branches . . . . . . . . . . . . . . . . DVE Coverage Source / Database File Relocation . . . . . . . . Container Exclusion State Markers . . . . . . . . . . . . . . . . . . . . 4. Coverage Convergence Technology Compile-Time Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coverage Convergence Option . . . . . . . . . . . . . . . . . . . . . . . Coverage Model Autogeneration Options . . . . . . . . . . . . . . . Coverage Convergence Runtime Options . . . . . . . . . . . . . . . . . URG Options for Bias File Generation . . . . . . . . . . . . . . . . . . . . Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 94 94 95 97 98 60 60 65 66 69 69 73 73 75 75 86 88 88 88 90

3

Constraints and Coverage Model on the Same Variables . . No Procedural Overwriting of Values Generated by the Solver

98 98

Coverage Should Be Sampled Between Consecutive Calls to randomize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Use Open Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoid Explicit or Implicit Partitioning in Constraints . . . . . . . 99 100

Avoid In-line Constraints and the Use of “constraint_mode” and “rand_mode” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Automatic Generation a Coverage Model from Constraints . . . . Coverage Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contribution to Coverage Scoring . . . . . . . . . . . . . . . . . . . . . Coverage Model Inference for In-line Constraints . . . . . . . . . Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Understanding Bias Files and Coverage Convergence. . . . . . . . Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Is a “Test”? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 101 108 108 109 110 110 110

Using Coverage Convergence Bias File to Pick Target Coverage Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Automatic Generation of Coverage Convergence Bias Files . . . Repeatability of Test Results for Parallel Regression Runs . . . . Usage Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running a Single Test with Randomized Configurations . . . . Running a Single Test with Randomized Transactions . . . . . Using a Bias File for a Parallel Regression . . . . . . . . . . . . . . Autogenerating a Coverage Model . . . . . . . . . . . . . . . . . . . . 113 114 114 115 115 116 117

4

Methodology and Flow Issues . . . . . . . . . . . . . . . . . . . . . . . . . . .

118

Scenario: All Tests Have the Same Constraints and Coverage Space (Recommended). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Scenario: Tests Are Grouped Into Categories With Each Category Having Specific Test Constraints . . . . . . . . . . . . . . . . . . . 119 Scenario: Coverage Database Being Loaded in the Beginning of a Test Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5. DVE Features Back Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Back Trace Properties . . . . . . . . . . . . . . . . . . . . . Using the Back Trace Schematic Toolbar . . . . . . . . . . . . . . . Editing the Bus Bit Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating and Updating Counters. . . . . . . . . . . . . . . . . . . . . . . . . Deleting Signal Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 124 125 125 126 129

Creating Multiple Groups when Adding Multiple Scopes into Wave View 130 Visualizing X at all Zoom Levels . . . . . . . . . . . . . . . . . . . . . . . . . Using Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Interfaces as Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. Viewing values in Symbolic format 7. Constraints Features SystemVerilog Constraint Features . . . . . . . . . . . . . . . . . . . . . . . 142 130 131 132 134

5

. . . . . . . . . . . . . . . . . . . . . . . . . . . Methodology for Using Unidirectional Constraints . Parallel VCS Parallel VCS Options. . . . Solver Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Constraint Solver Diagnostics . . Constraint Solver Search Space and Solution Space . . Using the Hierarchical Constraint Debugger Report . . . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . Classes of Constraint Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Array and XMR Support in std::randomize() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Constraint Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging Constraint Solver Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . VPD File. . . . Use Model for Assertion Simulation. . . . . . . . . . Use Model for Toggle and Functional Coverage . . . . 142 145 148 148 151 154 155 156 158 159 160 163 172 173 174 174 175 175 175 176 176 178 179 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running Parallel Simulation . . . . . . . . . . . . Search Space Reduction And Random Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constraint Debugging and Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XMR Support in Constraints . . . . . . . . . Assertion Simulation . Use Model for Design Profiling and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Model for VPD Dumping. . . . . Design Simulation . . . . . . . . . . . . . . . . Toggle Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Coverage . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_opts . . Supported Platforms . . . . . . . . . . . . . . . . . . . . VMM Additions and Enhancements VMM RAL C Interface . . . . vmm_opts::get_help() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::scenario_kind . . . . . . . . vmm_scenario::scenario_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::length . . . . . 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::stream_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMM Standard Library Class Additions . . . . vmm_opts::get_int() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 181 182 183 198 205 205 208 209 212 214 218 219 220 221 222 223 224 225 226 227 228 229 7 . . . . . . . . . . . vmm_opts::get_bit() . . . . . vmm_scenario::repeated . . . . . . . . . . . Profiling a Serial Simulation . . . . . . . . . . . . . . Execution Timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_opts::get_string() . . . . . . . . . . . .Profiling a Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Partitions . vmm_scenario . . Entry Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Profiling a Parallel Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limitations . . . . . . . . . . . Running PVCS Examples . . . . . . . . . Writing Firmware Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vmm_scenario::scenario_name(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::stop_after_n_scenarios . . . . vmm_object::display() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_object::get_hier_inst_name() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_object::set_parent() . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::define_scenario() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::DONE . . . . . . . . . . . . . . 230 231 232 233 234 235 236 237 238 239 240 241 243 244 245 246 247 248 249 250 251 252 253 254 255 256 8 . . . . . . . . vmm_scenario::psdisplay() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::get_n_insts() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_object::get_parent() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_object::psdisplay() . . . . . . . . . . . . .vmm_scenario::repeat_thresh . . vmm_object::get_type() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::set_parent_scenario(). . . vmm_ms_scenario_gen::get_n_scenarios() . . . . . . . . . . . . vmm_object::new . . . . . . . . . . . . . . . . . . . . . . . . vmm_scenario::get_parent_scenario() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_object . vmm_scenario::redefine_scenario(). . . . . . . vmm_ms_scenario_gen::stop_after_n_insts . . . . . . . . . vmm_ms_scenario_gen::scenario_count . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen . . . . . . . . . . . . . . . . . . . vmm_object::type_e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::GENERATED. . . vmm_ms_scenario_gen::inst_count . . . . . . . . vmm_scenario::repetition. . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::scenario_set[$] . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::unregister_channel_by_name() . . . . . . . .vmm_ms_scenario_gen::register_ms_scenario() . . . . . . . . . . vmm_ms_scenario_gen::unregister_ms_scenario() . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::get_ms_scenario_name() . . vmm_ms_scenario_gen::get_all_channel_names() . . . . . . . . . . . . . . . vmm_ms_scenario_gen::channel_exists(). . . . vmm_ms_scenario_gen::get_ms_scenario_index() . vmm_ms_scenario_gen::get_all_ms_scenario_names(). . . vmm_ms_scenario_gen::register_channel() . . . . . . . . vmm_ms_scenario_gen::replace_ms_scenario() . . . . . . . . vmm_ms_scenario_gen::get_ms_scenario_gen_name() . . . vmm_ms_scenario_gen::get_names_by_channel() . . . vmm_ms_scenario_gen::unregister_ms_scenario_by_name() vmm_ms_scenario_gen::select_scenario . . . . . . . . . . vmm_ms_scenario_gen::get_names_by_ms_scenario() . . . . . . . . . . vmm_ms_scenario_gen::replace_channel() . . vmm_ms_scenario_gen::get_names_by_ms_scenario_gen() 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 9 . . . . . . . . . . . . . vmm_ms_scenario_gen::get_channel(). . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::register_ms_scenario_gen() . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::ms_scenario_gen_exists(). . . vmm_ms_scenario_gen::ms_scenario_exists(). vmm_ms_scenario_gen::get_channel_name() . . . . vmm_ms_scenario_gen::unregister_channel() . . . . vmm_ms_scenario_gen::get_ms_scenario_gen() . . vmm_ms_scenario_gen::get_ms_scenario() . . .

. . . . . . . . . . . . . . . . . . . . . . vmm_xactor_iter::next() . . . . . . . . . . . . . . . . . . . . . . vmm_channel::record() . . . . . . . . . . . . . . . . . . . . . . . . . vmm_log::catch() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_xactor_iter::xactor() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_ms_scenario_gen::unregister_ms_scenario_gen() . . . . . . . . . . . . . . vmm_ral_block_or_sys Base Class Additions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_test::get_name() . . . . . . . vmm_test_begin() . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_test::run() . . . . . . . . . . . . . vmm_xactor_iter::first() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_test::log . . . . . . . . . . . . . . . . . . . . . . . 283 284 285 vmm_ms_scenario_gen::unregister_ms_scenario_gen_by_name() 286 vmm_xactor_iter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_test. . . . . . . . . . vmm_test_end() . . . . . . . vmm_test::get_doc() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 288 289 290 291 292 293 295 296 297 298 299 300 301 303 304 305 306 308 311 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vmm_channel . . . vmm_test::new() . . . . vmm_xactor_iter::new() . . . . . vmm_ms_scenario::get_channel(). . . . . . . . . . . . . . . . . . . . .vmm_ms_scenario_gen::get_all_ms_scenario_gen_names() vmm_ms_scenario_gen::replace_ms_scenario_gen() . vmm_channel::playback() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ‘foreach_vmm_xactor() . . . . . . . . . . . . . . . . . . . . .

. . 312 313 316 317 318 318 319 Compatibility with the VMM Planner Spreadsheet Annotation Flow 319 hvp annotate Command Arguments . . . . . . . . . . . 10. . Capturing a Verification Plan in Doc XML Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unique Error Code in Error Messages. . . . . . . . . . . Process Flow . . . . . . . . . . . Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plan/Feature Score Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measure Score Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vmm_ral_block_or_sys::set_offset() . . . . . . . . . . . . . . . . . . . Debugging the Doc Plan . . . . . . . . . . Table Keyword . vmm_ral_block_or_sys::get_reg_by_offset() . . . . [Style|Table] Keyword Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . Navigating Down to a Subplan . . . . . . . . . . . . . . . How to Get Scores Back-Annotated in the Doc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Built-In Styles . . . . . . . VMM Planner MS Doc Annotation Introduction . . . . . . . . License Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Contents. . . . . . 319 322 322 326 331 331 332 334 334 335 336 337 11 . . . . . . . . . . . . . . Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . Incompleteness Checks. . . . . Run Command run Command . . . . . . . . . . . . . . . . License Model . . . . . URG Enhancements New URG Features and Changes. . . . . . . . . . . . . . . . . . . . . . . Omitting Filtered Features . . . . . . . . . . . . 12. . . . . . . . . . . . Predictable Page Naming Convention . . . . . Platform Support . . . . . Dumping User Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Add New Hyperlinks from group bin and group instance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Metric Coloring . . . . . . . . . . Improved HTML Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . New –show hvpprob Command for Problem Reports . . 347 339 340 341 342 342 343 343 344 344 345 345 12 . . . . .

These features are described in the SystemVerilog Language Reference Manual: • • Strings in structs Queues in unpacked structs VCS SystemVerilog Features 13 .1 VCS SystemVerilog Features This chapter contains the following topics: • • • “SystemVerilog Enhancements” “New SystemVerilog Features” “Extension to SystemVerilog $readmemb/$readmemh” 1 SystemVerilog Enhancements Enhancements have been made to the following features.

This can result in runtime errors due to type mismatches between a message and the type of the variable to which the message gets assigned. For a parameterized mailbox. A mailbox can send and receive any type of data.• • • • • • • • Associative arrays of unpacked structs Multidimensional queues Arrays of queues Multidimensional associative arrays Multidimensional queues Integer indexed arrays Selecting an array word connected to a task ref port Casting of derived class with base class Additional SystemVerilog enhancements are described in the following sections: • • • • “Parameterized Mailboxes” “String Casting” “Array Literals” “SystemVerilog Linked Lists” Parameterized Mailboxes The default mailbox has no type. it is useful to detect type mismatches at compile time. When a mailbox is used to transfer a particular message type. the VCS SystemVerilog Features 14 .

sm.compiler checks that calls to the mailbox methods use the same argument types as the mailbox type so that type mismatches are caught by the compiler. sm."hello" Parameterized mailboxes provide the same methods as dynamic mailboxes. // s <. Parameterized mailboxes use the same parameter syntax as parameterized classes. which are: • num() • new() • get() • peek() • put() VCS SystemVerilog Features 15 .. and interfaces. . typedef mailbox #(string) s_mbox. string s. modules. s_mbox sm = new. Syntax mailbox #(type = dynamic_type) where dynamic_type is a type that enables runtime type checking (the default). Example You declare a parameterized mailbox of a particular type by specifying the type as in the following example..put( "hello" ).get( s ).

See “Limitations on Variable-Sized Arrays” for restrictions on this feature. StringLogic. realstring). initial begin logic [39:0] StringLogic = "hello". end endprogram Array Literals Any unpacked array can be written one entry at a time. or all the array contents can be replaced using an array literal. try_peek(). following the same rules as those for assigning a literal string to a packed or unpacked array. peek().• try_get() • try_peek() • try_put() The compiler checks that calls to the put(). String Casting String literals can be cast to a packed or unpacked array. $display("%s -. and try_get() methods use the same argument type as the parameterized mailbox type.%s\n". realstring = string'(StringLogic). try_put(). Example program rb. The syntax for associative arrays is: VCS SystemVerilog Features 16 . get(). string realstring.

1:'{'1. "Paul":22.3}. val3} or '{default: value} In arrays that have multiple unpacked dimensions. the default initial value shown in Table 1-1 is returned. For an associative array.1.333}}. '{3:'{1. val2. // An associative array of strings indexed by 2-state // integers string words [int].3}. 7:'{9.8. 4:'{3. if a nonexistent element is read.33}.1}}.9. '{5:'{5. Table 1-1 Default values for associative array elements Type of array 4-state integral type 2-state integral type string enumeration Default value ‘X ‘0 “” base type default initial value VCS SystemVerilog Features 17 .9}}}. // An associative array of 4-state integers indexed by // strings integer tab [string] = '{"Peter":20. array literals can be nested.1}.22.222.2.2. Example 1-1 Variable-sized arrays // Nested array literals int mix7[][*][3]='{'{0:'{11. "Mary":23 }.'{index:value} The syntax for other unpacked dimensions is: '{val1. 11:'{111.

1:aa[0]}" are executed as if they were separate assignments.Limitations on Variable-Sized Arrays The following features are not supported: • • • '{default: value} for associative arrays Identifiers imported from packages. Assignments such as "aa = '{0:aa[1]. SystemVerilog Linked Lists VCS provides a library implementation for SystemVerilog linked lists as specified in the SystemVerilog Language Reference Manual. This can have unexpected results. The VCS Users Guide provides details of how to use this feature. in associative arrays Only the following types of associative array indexes are supported: • • integer literal string literal identifier Cross-module references into multidimensional associative arrays structure element type An associative array declared with a non-constant RHS initializer may be initialized before expressions referred to in the RHS are initialized. VCS SystemVerilog Features 18 .

logic [31:0] rdata = 256. $display("Data Received = %0d". endfunction endinterface module Cpu_process.06: • • • • • • • “Task and Function Calls Using Virtual Interface Variables” “The $typename Function” “Fine-Grained Process Control Using the process Class” “Assignment Patterns Using %p” “Signal Aliasing” “Nested Classes” “’__FILE__ and ’__LINE__ Compiler Directives” Task and Function Calls Using Virtual Interface Variables Tasks and functions in a virtual interface can be called using a variable of that virtual interface type. VCS SystemVerilog Features 19 . function void Read_data(logic [31:0] data). Bus b().New SystemVerilog Features The following SystemVerilog features have been implemented in 2009. the Read_data() function in the Bus interface is called using the vB virtual interface variable in the test program : interface Bus. data). In the following example.

3.b. A ‘$’ is used as the placeholder for the name of an anonymous unpacked array. and enums. 6. Actual encoded values are appended with enumeration named constants. 4.rdata).Read_data(Cpu_process. end endprogram The $typename Function The $typename system function returns a string that represents the resolved type of its argument. The default signing is removed. VCS SystemVerilog Features 20 . virtual Bus vB = Cpu_process. System-generated names are created for anonymous structs. even if present explicitly in the source. initial begin vB. 2.endmodule program test. 5. User-defined type names are prefixed with their defining package or scope name space. A typedef that creates an equivalent type is resolved back to built-in or user-defined types. unions. Syntax $typename (expression | data_type) The return string is constructed using the following steps: 1.

White space in the source is removed and a single space is added to separate identifiers and keywords from each other. VCS SystemVerilog Features 21 . $typename returns a string that represents the self-determined type result of the expression. When used as an elaboration time constant. Thus $typename can be used in string comparisons for stricter type comparison of arrays than with type references.7. When called with an expression as its argument. Array ranges are represented as unsized decimal numbers. 8. This process is similar to the way that type matching is computed. except that simple bit vectors types with predefined widths are distinguished from those with user-defined widths. but never evaluated. The expression’s return type is determined during elaboration. the expression shall not contain any hierarchical references or references to elements of dynamic objects.

AB_t AB[10]. enum state { FINISHED. KILLED }.C=99} X.B=32'd1.B.AB_t$[0:9]" Source code typedef bit node. package A.B. endpackage : A import A::*. int signed Y.} AB_t. The prototype for the process class is as follows: class process. RUNNING. enum {A.Example 1-2 Values returned by $typename for different types of variables Value returned by $typename "bit" "bit signed[2:0]" "int" "enum{A=32'd0.bit B. Processes can be passed to tasks or functions. task kill(). task await(). module top. endmodule Fine-Grained Process Control Using the process Class A process is a built-in class that allows one process to access and control another process once it has started running. endclass VCS SystemVerilog Features 22 . WAITING. typedef bit [9:1'b1] word. task resume(). node signed [2:0] X. function state status().C='32d99 }A::e$1" "A::bit[9:1]" "struct{bit A. SUSPENDED. static function process self(). and can become members of other classes. typedef struct {node A. task suspend().}top.

Process status is marked RUNNING. . A process cannot be extended. Example process p.. tf_n represents a task or function call. The following terms are used below: • • • fork. where n denotes the number of the thread of the fork. If the handle does not exist already a new handle is allocated and returned. The handle can be used for controlling the process and accessing its status using process class methods.A process handle can be created only by a call to the process class self() static method. An error is issued if this is attempted. otherwise the existing handle is returned..join represents any of the fork-join/join_any/ join_none statements. An error is issued if this is attempted.. You cannot use new to create an object of the process class. thread_n is a thread of a fork. fork thread_1 VCS SystemVerilog Features 23 .. process Class Members self() The self() function returns a process class handle corresponding to the process thread in which the function call is executed.

enum state { FINISHED. VCS SystemVerilog Features 24 . RUNNING. process handle "p" belong to "thread_1". SUSPENDED – The process has been stopped by a suspend() call. state/status() The status() function returns the current state of the process. KILLED }. Every time a process blocks. the process state is updated to RUNNING. KILLED – The process was killed by a kill() call or disable. The process status is updated upon a change in the process execution and follows the process execution state.. SUSPENDED. the process state is updated to WAITING. WAITING – The process is blocked by a delay/@/wait. Upon unblocking of the process. RUNNING – The process is running (not blocked). WAITING.. The process is not executing at all.tf_1 tf_2 p = process::self thread_2 join . or due to a condition such as a blocking mailbox or semaphore call. The possible states are: FINISHED – The process finished execution normally.

. process::state estate. kill() The kill() task terminates the process and all its child processes.. just like disable.. Process status is marked as KILLED.. fork thread_1 tf_1 tf_2 p = process::self #10. A process can be killed if it is not already finished.. . // WAITING .. . process::state estate.status(). thread_2 join_none #1.. estate = p. Example process p. $display("I was killed"). VCS SystemVerilog Features 25 . thread_2 join_none #1. . fork thread_1 tf_1 tf_2 p = process::self #10..Example process p.

p. #1 p. .. await() The await() task blocks the current thread. . Calling await() on the current process is a runtime error. .) If the process has already finished execution. Example process p. thread_2 join_none . process::state estate..await(). $display("I’m waiting for thread_1 to finish"). then await() does not block... fork thread_1 tf_1 tf_2 p = process::self #10..... (A process cannot wait for its own completion.. await() will never unblock.kill(). If the awaited process is killed. . It unblocks once the awaited process has finished execution normally.. suspend()/ resume() VCS SystemVerilog Features 26 .

A killed or finished process cannot be suspended. It can be called on the current process (a process can suspend itself). The process status is marked as SUSPENDED. the process waits for the remaining delay time. Effects of suspend() on Waiting Processes The following sections describe the effects of the suspend() task on process that are waiting due to different reasons. then it cannot resume. then it cannot continue execution upon resumption.. the suspend() and resume() tasks act only on the process on which they are called and do not affect execution of its child processes in any way.The suspend() task suspends the execution of the process. process::state estate. . upon resumption. . Example process p. The process status is marked as RUNNING. It must wait for maturity of the blocking condition.. fork VCS SystemVerilog Features 27 . If the process has pending delay or waiting events. The resume() task restarts a previously suspended process. then. If the process is killed or terminated while it is suspended.Waiting on delay If a process gets suspended while waiting for a delay to mature. Unlike kill(). Call resume() on a process that suspended itself causes the process to continue executing at the statement following the call to suspend().

Waiting on @(static_variable) or wait(static_expression) VCS SystemVerilog Features 28 . then.suspend(). . and that event triggers while the process is suspended. If the process is suspended after 3 time units. . upon resumption. and that method unblocks while the process is suspended. p. then the process will unblock from waiting but it will not continue executing until its resume() task is called.Waiting on blocking mailbox or semaphore methods If a process is suspended while waiting for a mailbox or semaphore method to complete. #100. This is independent of the amount of time the process spent in suspension.thread_1 tf_1 tf_2 process = process::self #10. it must wait for 7 more time units before it can continue execution. . The process p above must wait for a delay of 10 time units to mature. then the process will unblock from waiting but it will not continue executing until its resume() task is called. $display("I’ll resume at time 110"). thread_2 join_none #3. p.Waiting on @(SV_event) If a process gets suspended while waiting for a SystemVerilog event.resume().

and so on. upon resumption. dynamic arrays. checking for a change of the static variable is done. . or a class reference using any of those. Therefore. associative arrays. no matter how many times the dynamic variable or expression changes.Waiting on @(dynamic_variable) or wait(dynamic_expression) A dynamic variable or expression is one that contains a dynamic type such as a class handle.A static variable or expression is one that does not contain any dynamic types such as class handles. @(static_variable) cannot unblock upon resumption. but @(dynamic_variable) can unblock upon resumption if the value during suspension is different from the value at resumption. using the last value as the previous value. or associative array. The value used as the previous value for computing the change of the dynamic expression is the value of the expression at the time of the suspension. then the previous value does not change. If the expression changes after the process thread is suspended. A process waiting on a static variable or expression will not unblock while it is suspended. in which the previous value gets updated every time the variable’s value changes. dynamic array. srandom() VCS SystemVerilog Features 29 . A process waiting on a dynamic variable or expression will not unblock while it is suspended. no matter how many times the static variable or expression changes. Unlike the static variable case.

The srandom() method can be called on a process handle. it prints “tag:value” along with the currently valid element. Otherwise the value prints according to the base type of the enumeration. In the case of a tagged union. • • VCS SystemVerilog Features 30 . while providing the flexibility of seeding a process from outside its scope. A string data type or string literal prints its value as a string.srandom() syntax is not supported • • Debug is not supported DPI calls are not supported Assignment Patterns Using %p The %p format specifier can be used to print aggregate expressions such as packed structures and arrays. The value of each element that is a singular type is printed as follows: • A packed structure data type prints its value as an assignment pattern with named elements. For unions. Each element is printed under one of these rules. It prints the value as an assignment pattern with named elements. using the process handle. This works the same as calling srandom() directly in the process scope. only the first declared elements are printed. Limitations • The process::self. An enumerated data type prints its value as an enumeration name if the value is valid for that type. which allows seeding of underlying process threads.

va).} pair_t. class handle. All other singular data types print their values unformatted. VCS SystemVerilog Features 31 .va). switch20} switch_s. $display("va[int] = %0p. or virtual interface prints a pointer. switch20}}. 20 : '{OFF.switch10}. va[10]. s:switch10}. switch_s s. Example module top. s:switch20}} . event. va[10].s = %p.". OFF} switch_e. s:switch20}} . typedef enum {ON. 20:'{sw:OFF. initial begin $display("va[int] = %p. $display("va[10]. end endmodule : top The example above prints this: va[int] = '{10:'{sw:ON.s). va[int] = '{10:'{sw:ON. typedef enum {switch10. except that a null handle value prints the word null. s:switch10}.". in which case the expression is formatted as an element of an aggregate expression described above.". pair_t va[int] = '{10 : '{ON.s = switch10.• • A chandle. typedef struct packed {switch_e sw. 20:'{sw:OFF. The %p format specifier can also be used to print singular expressions.

alias net_c = net_d.. The members of an alias list are signals whose bits are on the same physical nets. so that a net can belong to several aliases. VCS SystemVerilog Features 32 .Signal Aliasing An alias statement declares multiple names for the same physical net or slice of bits in a net. Example alias net_a = net_b = net_c = net_d. Note: Standard SystemVerilog restrictions on hierarchical references in alias statements and on aliasing a net or signal to itself do not apply in the VCS implementation.. it is an error to use an alias statement to connect a wand net to a wor net. The same nets can appear in multiple alias statements. Syntax alias net-expr|bit-expr = alias-expr [ = alias-expr . Each member must be the same size and the nets must be of compatible types.]. See the SystemVerilog Language Reference Manual for additional information about net aliasing. The statement above results in three aliases: alias net_a = net_d. Variables are not allowed in alias statements. alias net_b = net_d. For example.

written (in assignments or subroutine calls). Example 1-3 Nested classes in a linked list and in a binary tree class StringList. typedefs. Nesting allows hiding of local names and local allocation of resources. structures. They can also be used as the name of a type or a method call. string name. class Node. unions. Node left. static methods. right. Class scope resolved expressions can be read (in expressions). Node link. Like modules. // Nested class for a node in a binary tree. Type declarations nested inside a class scope are public and can be accessed outside the class. endclass endclass // StringList::Node is different from StringTree::Node VCS SystemVerilog Features 33 . Parameterized outer classes are not supported for this feature. classes are scopes and can nest. // Nested class for a node in a linked list string name. This is often desirable when a new type is needed as part of the implementation of a class. class Node. or triggered (in event expressions). Declaring types within a class helps prevent name collisions and the cluttering of the outer scope with symbols that are used only by that class. and nested class declarations. enumerations.Nested Classes The class scope resolution operator applies to all static elements of a class: static class properties. endclass endclass class StringTree.

as described below. At the end of that file. VCS SystemVerilog Features 34 . ’__FILE__ and ’__LINE__ are useful in generating error messages to report problems. when processing resumes on the input file that contained the ’include directive. line %d. `__FILE__. An ’include directive changes the expansions of ’__FILE__ and `’__LINE__ to correspond to the included file. `__LINE__). A ’line directive changes ’__LINE__ and might also change ’__FILE__ . The message can state the line in the source at which the problem was detected. Example 1-4 ’__FILE__ and ’__LINE__ usage $display("Internal error: null handle at %s. ’__FILE__ expands to the string literal name of the current input file.’__FILE__ and ’__LINE__ Compiler Directives The ’__FILE__ and ’__LINE__ compiler directives have been implemented in this release. the expansions of ’__FILE__ and ’__LINE__ revert to the values they had before the ’include and `__LINE__ is then incremented by one as processing moves to the line after the `include.". ’__LINE__ expands to the decimal current input line number. This is the path by which a tool opened the file. These directives are described in "Compiler Directives" in the SystemVerilog Language Reference Manual. not the short name specified in ’include or as a tool’s input file name argument.

and dynamic arrays of packed data. start_addr [.Extension to SystemVerilog $readmemb/$readmemh The following SystemVerilog $readmemb/$readmemh tasks have been extended as described in the following section: • “Loading Memories with $readmemb and $readmemh” Loading Memories with $readmemb and $readmemh The $readmemb and $readmemh tasks described in "System Tasks and Functions" in the SystemVerilog Language Reference Manual. Reading Packed Data $readmemb and $readmemh are extended to queues. $readmemb and $readmemh are system tasks that allow you to load memory from a file on the disk. Their functionality is described in this section. memory_name [. start_addr [. finish_addr]]). In such cases. unpacked arrays of packed data. for use in simulating memories at runtime. the system tasks treat each packed element as the vector equivalent and perform the normal operation. memory_name [. VCS SystemVerilog Features 35 . finish_addr]]). have been extended. $readmemb reads in binary and $readmemh reads in hexadecimal numbers. associative arrays of packed data. Syntax $readmemb ("file_name". $readmemh ("file_name".

reading proceeds the same as for conventional Verilog variable types (e. such as int or enumerated types. address entries in the pattern file are in numeric format and correspond to the numeric values associated with the elements of the enumerated type. indexes must be of integral types.When working with associative arrays.. When an associative array’s index is of an enumerated type. with the exception that X or Z data are converted to 0. integer). For 2-state integer types. If a numeric value is out of range for a given type. then an error shall be issued and no further reading shall take place. For enumerated types. Dynamic arrays support the equivalent types as fixed-size arrays. VCS SystemVerilog Features 36 . where data_type is the data type of the array elements. The space for dynamic array doesn’t exist until the array is explicitly created at runtime The syntax to declare a dynamic array is: data_type array_name[]. Note: The real data type is not supported with these system tasks. the file data represents the numeric values associated with each element of the enumerated type.g. $readmemb and $readmemh for Dynamic Data Types Dynamic Arrays A dynamic array is any dimension of an unpacked array whose size can be set or changed at runtime. Reading 2-state Types $readmemb and $readmemh are extended to packed data of 2-state types.

If there is a start address specified in the $readmemb or $readmemh call for an uninitialized dynamic array. then the required finish address is calculated and a new array is allocated and filled. Elements of the array that are not filled from the memory file are filled with default values for the data type of the array. if the file requires a smaller or larger array than the existing array. a = new[10]). then the array is resized to the size of the file. • When loading a dynamic array that has been initialized. Strings. the array must be initialized with the size of the given file (for example. it starts from address 10). chandles and class objects are not supported as memory elements of memories by $readmemb or $readmemh. For an uninitialized array and a memory file that has holes in it. • • • • • • Smart Queues A queue is a variable-size. ordered collection of homogeneous elements. the first 10 elements of the array are filled with the default value for the data type for the array. You can also use the @ operator to make the memory file load into the array in the reverse direction. A queue supports constant-time access to all its elements as well as constant-time insertion and removal at the beginning or VCS SystemVerilog Features 37 . (for example.Initializing and Loading Dynamic Arrays • When loading a memory that has not been initialized yet. The contents of the memory file can be loaded into the array in either ascending or descending order. The start address can be a higher-numbered address than the finish address.

and equality operators. Thus. queues can be manipulated using the indexing. a new queue is created with the size specified by the finish address. If the start address is greater than 0. the memory file is loaded until the end of the file is reached. If no finish address is specified. Queue positions for which no values are present in the memory file are filled with the default values for the data type of the queue. A queue is analogous to a one-dimensional unpacked array that grows and shrinks automatically. if there are more entries in the file than the finish address of the queue. a new queue is created and filled. like arrays. is created If the memory file is larger than the queue can hold. an error is issued. • • • VCS SystemVerilog Features 38 . a new queue with a size equal to the size of the memory file is created. slicing operator syntax. but specifying $ as the array size. • For an uninitialized queue with start address 0 and no finish address specified. a queue of size finish address + 1. Queues are declared using the same syntax as unpacked arrays. For an existing queue. a new queue is created with the required size. and $ representing the last. The maximum size of a queue can be limited by specifying its optional right bound (last index).the end of the queue. and if the start address is 0. For an uninitialized queue with start address 0 and a specified finish address. Each element in a queue is identified by an ordinal number that represents its position within the queue. with 0 representing the first. but the queue is filled up to the specified finish address. concatenation. Initializing and Loading Smart Queues • If an uninitialized queue with start and finish addresses specified is being loaded.

an error is issued. VCS SystemVerilog Features 39 . An associative array implements a lookup table of the elements of its declared type. For an existing new queue. and the index expression is not restricted to integral expressions. an associative array is a better option. it starts from address 10). an error is issued. Strings. When the size of the collection is unknown or the data space is sparse. (for example. The data type to be used as an index serves as the lookup key. but can be of any type. For an uninitialized queue whose address file starts with an address higher than 0. only those elements within the size of the existing queue are filled. the first 10 elements of the array are filled with the default value for the data type for the array. • • • • Associative Arrays Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically.• For an existing queue with start index greater than the finish index. If the finish address is greater than the current size of the queue. An associative array does not have any storage allocated until it is used. For an uninitialized array and a memory file that has holes in it. You can also use the @ operator to make the memory file load into the array in the reverse direction. if the @ operator is trying to fill a position larger than the current size of the queue. the queue elements that are not present in the memory file are filled with default values for the data type. and imposes an ordering. chandles and class objects are not supported as memory elements of memories by $readmemb or $readmemh.

It can be any type allowed for fixed-size arrays. VCS SystemVerilog Features 40 . index_type is the data type to be used as an index. Otherwise. or *. then the array is indexed by any integral expression of arbitrary size. Initializing and Loading Associative Arrays Strings and class objects are not allowed as associative array indexes. initializing and loading of associative arrays is the same as for dynamic arrays. It shall be illegal for index_type to declare a type. An index type restricts the indexing expressions to a particular type. where: data_type is the data type of the array elements. array_id is the name of the array being declared. If * is specified.The syntax to declare an associative array is: data_type array_id [index_type].

Many of these features are part of SV LRM 2009 (draft) and detailed descriptions for them is available in the LRM.2 Assertions 1 This chapter describes the implementation of beta features for SystemVerilog Assertions. This chapter contains the following sections: “Use Model” on page 2-40 “Overlapping Operators in Multiclock Environment” on page 2-40 “Deferred Immediate Assertions” on page 2-41 “Property Operators” on page 2-42 “Inferred Value Functions” on page 2-49 “Recursive Properties” on page 2-50 Assertions 39 .

You can use the operators ##0. Overlapping Operators in Multiclock Environment SV 1800-2005 LRM allowed only non-overlapping implication (|=>) operator to be used in multiclock properties. if … else. |->. @clk1 a ##0 @clk2 b @clk1 s |-> @clk2 p @clk1 if (b) @clk2 p1 else @clk3 p2 Assertions 40 . Note: The –assert svaext option must be used at analysis phase (vlogan) for the UUM flow. and #-# in multiclock environments. This is at times difficult and restricts the usage.“Local Variable Initialization and Input” “Global Clocking” on page 2-52 “let Operator” on page 2-55 “Limitations” on page 2-55 Use Model You must use the –assert svaext compile time option for all the new SVA features . LRM 2009 relaxes this and allows overlapping operators as well.

or it may occur in a future time step after clk1 This feature is implemented in conformance with the IEEE P18002009 Standard for SystemVerilog — Unified Hardware Design. Specification. end Deferred assertions help in such cases. The syntax for Deferred assertion is: assert #0 (expression) action_block always_comb begin : b1 def_final_check: assert #0 (not_a != a). assign not_a = !a. always will execute 2x and the assertion will fire on a transient value. It triggers the simulation report on the final. clk3) may occur in the same time step. end Assertions 41 . when a changes. They may produce unnecessary noise in simulation reports. In the example below. always_comb begin : b1 glitch_prone_check: assert (not_a != a).Either clk 1 and clk2 (resp. and Verification Language. Deferred Immediate Assertions Immediate assertions used in combinational always blocks may fire on 0-width glitches. settled value of a given time step thereby producing single report line.

Immediate cover is also supported in deferred version. Weak and Strong Sequence Operators The weak and strong sequence property operators are defined as follows: weak (sequence_expr) Assertions 42 . logic a. always_comb begin equiv_def_assert: assert #0 (a == b). endmodule : def_assert_ex This is equivalent to: module def_assert_ex. logic a.Immediate assertions can an also be used in non-procedural context (implicit always_comb). module def_assert_ex. and Verification Language.b. Specification. end endmodule : def_assert_ex Property Operators This section describes implemented property operators implemented in conformance with the IEEE P1800-2009 Standard for SystemVerilog — Unified Hardware Design.b. conc_def_assert: assert #0 (a == b).

A success occurs if there is a match or incomplete evaluation when the simulation finishes. sequence_expr property is • • Weak in assert and assume Strong in cover property Implication and Equivalence Operators Implication and equivalence operators are implemented for expression and property levels: • • At the expression level expression1 -> expression2 is shorthand for (!expression1 || expression2) • expression1 <-> expression2 is shorthand for (!expression1 || expression2) && (!expression2 || expression1) • • • At the property level property1 implies property2 is shorthand for (not property1) or property2 property1 iff property2 is shorthand for ((not property1) or property2) and (not property2) or property1) Assertions 43 . strong (sequence_expr) Success requires a match during simulation. By default. otherwise a mismatch results.

Assertions 44 . Strong versions: • • property_expr1 s_until property_expr2 is the strong non-overlapping form. This form requires that property_expr2 eventually evaluates true for until to succeed. VCS supports 4 forms of until operator: weak until (Non-overlapping) strong until (Non-overlapping) weak until_with (Overlapping) strong until_with (Overlapping) Weak versions • • property_expr1 until property_expr2 is the weak non-overlapping form. This form requires that property_expr2 eventually evaluates true for until to succeed.until Operator SystemVerilog 2009 adds the until operator. property_expr1 s_until_with property_expr2 is the strong overlapping form. property_expr1 until_with property_expr2 is the weak overlapping form.

s_always [constant_range] property_expr strong is true during the range. N clock ticks must occur. It may not have enough ticks for the range. if it exists. nexttime [N] property_expr is weak and evaluates the expression at the N-th tick. Assertions 45 .nexttime Operator There are four variants of the nexttime property operator: • • • • nexttime property_expr is weak and evaluates the expression at the next clock tick. s_nexttime property_expr is strong nexttime and evaluates the expression at the next tick. • Note that assert property(p) has an implicit always. A clock tick must occur. s_nexttime [N] property_expr is strong nexttime and evaluates the expression at the N-th tick. always Operator The always operator has two variants: • • always property_expr is weak and is true as long as there is a tick. always [cycle_delay_const_range_expression] property_expr is weak and is true during the range. It must have enough ticks for the range.

• seq #-# prop is the same as not (seq |-> not prop) Assertions 46 . which must be true in the future. initial rst_stays_low : assume property (reset[*5] #=# always !reset) . • • followed-by Operator The followed-by operator (#-#. For example. It has three variants: • eventually [constant_range] property_expr is weak. It evaluates the expression within the range of ticks in the future. s_eventually property_expr is strong. It evaluates the expression. it remains low forever. It may not have enough ticks for the range. |=>. s_eventually [cycle_delay_const_range_expression] is strong. It is a dual operator of |-> .Example This property sets an assumption that once reset is HIGH for 5 continuous clocks. #=#) is useful when a sequence needs to be followed by a property within a specified interval. The followed-by operator #=# is discussed in LRM and also below in this document. respectively. eventually Operator The eventually operator evaluates an expression within a range of ticks. It must have enough ticks for it to be true. It must be true in the range of ticks and must have ticks for the range.

For example. if a property evaluation attempt did not complete evaluation. In VCS. the value of a must be false at each of the infinitely many clock ticks. the property always a is safety since it is violated only if after finitely many clock ticks there is a clock tick at which a is false.• seq #=# prop is the same as not (seq |=> not prop) seq must have at least one match followed by a success of prop. it will be reported as Assertions 47 . Safety properties have the characteristic that all their failures happen at a finite time.. a failure of the property s_eventually a on a computation with infinitely many clock ticks cannot be identified at a finite time: if it is violated. When prop is a sequence strong(seq1) then • • seq #-# strong(seq1) is the same as strong(seq ##0 seq1) seq #=# strong(seq1) is the same as strong(seq ##1 seq1) Mixed Strength Property Reporting The concept of weak and strong operators is closely related to an important notion of safety properties. Since typical simulations complete in finite number of clock ticks. To the contrary. even if there are infinitely many clock ticks in the computation. VCS has implemented a flexible means for users to interpret the result of a strong and weak operators. In all cases. strong and weak properties are not distinguished as to the reporting at the end of simulation.

reject_on(expression) property_expr accept_on and reject_on can be nested within properties. the user may then decide the effective outcome. • accept_on makes the property true when the expression becomes true. rather than success or failure. Synchronous versions are sync_accept_on and sync_reject_on. If abort occurs simultaneous with property result. In which case: • • If simultaneous aborts occur the one at the higher level in syntax order dominates. Assertions 48 . abort dominates. reject_on Abort properties model abort conditions by controlling asynchronous aborts based on sampled values of expressions. abort dominates."unfinished evaluation attempt". Depending on the property. Synchronous versions are sync_accept_on and sync_reject_on. If abort occurs simultaneous with property result. accept_on (expression) property_expr • reject_on makes the property false when the expression becomes true. Modeling Abort Conditions: accept_on.

and enable condition. Returns the inferred disable expression. Inferred Value Functions Use elaboration-time system functions to query the inferred clocking event expression. $inferred_enable is a VCS extension to the Inferred functions and not a standard LRM feature. Returns the inferred enable condition. $inferred_disable $inferred_enable $inferred_clock and $inferred_disable are instantiated in conformance with the IEEE P1800-2009 Standard for SystemVerilog — Unified Hardware Design.Example assert property (@(clk) go ##1 get[*2] |-> reject_on(stop) put[->2]). Specification. and Verification Language. There must be a current resolved event expression when $inferred_clock is encountered or an error is issued. disable expression. $inferred_clock Returns the expression of the inferred clocking event. It is obtained by applying clock flow rules to the point where $inferred_clock is called. The inferred clocking event expression is the current resolved event expression that can be used in a clocking event definition. Assertions 49 .

Specification.p). endproperty is a recursive property that says that the formal argument property p must hold at every cycle.Recursive Properties Recursive properties are implemented in this release. s |=> prop_always(p). Example property prop_always(p). endproperty Support for recursive properties is an update in conformance with IEEE Std 1800™-2005 Standard for SystemVerilog — Unified Hardware Design. and Verification Language. Recursive properties substitute in assertions and unfold until all unique property instances are reached (as in a tree structure with feedback references for recursion). Local Variable Initialization and Input The use of local variables allows arguments of sequences and properties to serve as local variable declarations. In this release. This example is useful if the ongoing requirement that property p hold applies after a complicated triggering condition encoded in sequences: property p1(s. local variable initializers: Assertions 50 . p and (1'b1 |=> prop_always(p)). Operators are instantiated following the tree in postorder and loops are closed by passing handles.

Can initialize by actual argument and preceding local variables in an expression. On input and inout. int a = 1. endproperty Local variable input and initialization are implimented in conformance with the IEEE P1800-2009 Standard for SystemVerilog — Unified Hardware Design. property p(). @clk (dut_y == x. Assertions 51 . implicitly creates a local variable declaration and initialization by the actual argument. Assign initial values in the order of the local variable declarations. Specification. int a = x. Can be used in recursive properties and LTL property p(local input int x). a+=1) … . int b = a+2.• • • Allow initialization of local variables in the declaration. On inout and output in sequences assigns the local value to the external local variable actual arg. and Verification Language. by reference for output direction. … endproperty A local variable argument: • • • • Passes “by value” of actual argument for input direction. int b = a+2.

Past and Future Sampled Value Functions Use the global clocking system functions to access past and future shifted sampled value at the global clock tick that immediately precedes or follows the timestep at which the function is called. endclocking [ : clocking_identifier ] There can be only one global clocking block per system. This feature is implemented in conformance with the IEEE P1800 Standard for SystemVerilog — Unified Hardware Design. and Verification Language. They may be used only if global clocking is defined. The function has no arguments. The syntax for the global clocking specification statement is as follows: global clocking [clocking_identifier ] clocking_event . Global Clocking Global clocking is to represent a system clock. and Verification Language. The following functions are provided: Assertions 52 .This system function $global_clock returns the event expression specified in the global clocking statement. SystemVerilog provides a system function to refer to the global clocking. Specification.Support for use of local variables with property operators is an update in conformance with IEEE Std 1800™-2005 Standard for SystemVerilog — Unified Hardware Design. Specification. This helps in writing generic assertions.

it returns false. Assertions 53 $stable_gclk(expression) . it returns false. it returns false. Otherwise. Otherwise. The functions are: Global clocking past sampled value functions are: $past_gclk(expression) $rose_gclk(expression) $fell_gclk(expression) $stable_gclk(expression) $changed_gclk(expression) Where: $past_gclk (expression) Returns sampled value of expression at the previous global clocking tick. Returns true if the sampled value of expression changed to 1 from its sampled value at the previous global clocking tick. $rose_gclk(expression) $fell_gclk(expression) Returns true if the sampled value of expression changed to 0 from its sampled value at the previous global clocking tick.Sampling Past Value Functions Global clocking past sampled value functions report the past shifted times. Returns true if the sampled value of expression did not change at the previous global clocking tick. $rose_gclk should read something like this: $rose_gclk is true whenever the sampled value of b changed to 1 from its sampled value at the previous global clocking tick. Otherwise.

it returns false. Otherwise. it returns false. The future value functions are: $future_gclk(expression) $rising_gclk(expression) $falling_gclk(expression) $steady_gclk(expression) $changing_gclk(expression) Where: $future_gclk (expression) Returns sampled value of expression at the next global clocking tick. Otherwise. the future value access is implemented by shifting the whole assertion by one gclk tick into the past. Otherwise. $rising_gclk(expression) $falling_gclk(expression) $steady_gclk(expression) Assertions 54 .$changed_gclk(expression) Returns true if the sampled value of expression changed at the previous global clocking tick. Returns true if the sampled value of expression does not change at the next global clocking tick. Returns true if the sampled value of expression changes to 0 from its sampled value at the next global clocking tick. Otherwise. it returns false. it returns false. Sampling Future Value Functions In VCS. Returns true if the sampled value of expression changes to 1 from its sampled value at the next global clocking tick.

end_time for every attempt and statistics for every assertion/cover. While basic debug support is available with this release. Otherwise. it returns false. UCLI support for new assertions is not fully qualified. DVE also groups all signals involved in an assertion on tracing an attempt. DVE provides information such as: start_time. let Operator Use of the let operator is facilitated when you use -assert svaext. assertion tracing in DVE not supported completely.$changing_gclk(expression) Returns true if the sampled value of expression changes at the next global clocking tick. Assertions 55 . Limitations This section describes known limitations. Debug Support for New Constructs Use -assert dve at compile/elab to enable debug for assertions.There is no need fto enter the -assert let option. However the extra "hints" that are provided for SVA 2005 constructs are not available for new constructs as of now.

Note on Cross Features Some of the features in new assertions have known limitations with cross feature support. Assertions 56 . Some known issues: • • –cm property_path is not available for most of the new constructs New sequence operators when used as sampling event for covergroups may not function well. Coverage. such as Debug. Please check with Synopsys support if there are unexpected results with cross feature behavior for these new constructs.

“Wildcard Support in binsof Expressions” on page 64 .“Wildcard Support in binsof Expressions” on page 73 • “Coverage Exclusion Enhancement” on page 77 .4 Coverage Enhancements This chapter provides details on the following coverage enhancements: • “SystemVerilog Language Enhancements” on page 64 .“State Bin Names as States in Transition Sequences” on page 70 • “OpenVera Language Enhancement” on page 73 .“Understanding Half-Toggle Exclusion” on page 77 1 63 .“Wildcard Array Bins” on page 69 .

(This document is referred to herein as the SystemVerilog Language Reference Manual.“Understanding Covergroup Page Splitting” on page 90 • “DVE Coverage Enhancements” on page 92 .“Container Exclusion State Markers” on page 94 SystemVerilog Language Enhancements Wildcard Support in binsof Expressions You can use wildcards (x.) SystemVerilog Syntax Extensions The following non-standard extensions have been made to SystemVerilog syntax: cover_cross ::= [ cover_point_identifier : ] cross list_of_coverpoints [ iff ( expression ) ] select_bins_or_empty list_of_coverpoints ::= cross_item .“Reporting Only Uncovered Objects” on page 79 . cross_item } 64 .• “Unified Coverage Reporting Enhancements” on page 79 . and Verification Language (IEEE Std 1800™-2005). These wildcards are an extension of SystemVerilog syntax and are not part of the IEEE Standard for SystemVerilog— Unified Hardware Design. cross_item { . z. ?) to specify ranges in the binsof expression. Specification.“DVE Coverage Source / Database File Relocation” on page 92 .“Branch Coverage and Implied Branches” on page 92 .

Consider the following example: wildcard bins g12_16 = binsof( x ) intersect { 4’b11?? }. but using one wildcard consistently helps prevent confusion. and ? as wildcards. bins_identifier ] open_range_list ::= open_value_range { . z. The wildcard bins definition causes all x. z. } } | . and ? to be treated as wildcards for 0 or 1 (similar to the ==? operator). open_value_range } open_value_range ::= value_range Understanding Wildcard Usage An optional keyword wildcard is included in the cross bin definition. You can use one or all of x. 65 .cross_item ::= cover_point_identifier | variable_identifier select_bins_or_empty ::= { { bins_selection_or_option . bins_selection_or_option ::= { attribute_instance } coverage_option | { attribute_instance } bins_selection bins_selection ::= [ wildcard ] bins_keyword bin_identifier = select_expression [ iff ( expression ) ] select_expression ::= select_condition | ! select_condition | select_expression && select_expression | select_expression || select_expression | ( select_expression ) select_condition ::= binsof ( bins_expression ) [ intersect { open_range_list } ] bins_expression ::= variable_identifier | cover_point_identifier [ .

// The above shows 8 cross products } endgroup 66 . the range of values covered by a wildcard bin is established by replacing every wildcard digit by 0 to compute the low bound and 1 to compute the high bound. bins b2 = { [1:8] }. bit [3:0] v_a. sampled values containing x and/or z are excluded. bins b4 = { [14:15] }. bins a3 = { [8:11] }. v_b. The following is an example of user-defined cross coverage and select expressions. bins a2 = { [4:7] }. Thus. covergroup cg @(posedge clk). bins b3 = { [9:13] }. // The above shows 4 cross products wildcard bins c2 = ! binsof(b) intersect {4’b1?0?}.Only bins of x whose associated values intersect values between 12 and 16 are included: 1100 1101 1110 1111 A wildcard bin definition only considers 2-state values. } c : cross a. a: coverpoint v_a { bins a1 = { [0:3] }. bins a4 = { [12:15] }. } b: coverpoint v_b { bins b1 = {0}. b { wildcard bins c1 = binsof(a) intersect {4’b11??}.

then cross coverage of a and b would include 16 cross products corresponding to all combinations of bins a1 through a4 with bins b1 through b4.b1 • a1.b4 • . cross products • a1. Coverage point a (associated with variable v_a) defines four equalsized bins for each possible value of variable v_a. one for each of the two 4-bit variables. If the cross coverage of coverage points a and b were defined without any additional cross bins (select expressions).b4 67 . The coverage group includes two coverage points. a and b. Cross definition c specifies the cross coverage of the two coverage points v_a and v_b.b2 • a1.b1 • a4. Coverage point b (associated with variable v_b) defines four bins for each possible value of variable v_b.b3 • a1.b3 • a4. • a4. that is.The example above defines a coverage group named cg that samples its coverage points on the positive edge of signal clk (not shown)..b2 • a4..

This select expression excludes bins b2 and b3. and a3. specifies that c1 should include only cross products of coverage point a that intersect the value range of 1100 to 1111.b1 • a2. c2. Thus. The second user-defined cross bin.b1 • a1.b1 • a3.b4 • a2. c1 will cover only four cross products of • • • • a4.b4 • a4.b4 • a3. specifies that bin c2 should include only cross products of coverage point b that do not intersect the value range of 1000 to 1001 and 1100 to 1101.b3 a4. c2 covers only four cross products of • a1. c1. a2.b4 68 . This select expression excludes bins a1.b2 a4. Thus.b1 • a4.b4 This is similar to the behavior of following code: bins c1 = binsof(a) intersect {[12:15]}.b1 a4.The first user-defined cross bin.

or “z”. You can use any of the following symbols as a wildcard: “?”. 69 . in the first example. This syntax creates three bins by dividing the number of total possible transitions into three bins and putting the remaining transition in the last bin. wildcard bins b3[] = (4’bx1xx => 4’bxx1x). In each of the examples above. Consider the following examples: wildcard bins b1[] = {4’b01??}. For example. 4’b11?1}. wildcard bins b2[] = {4’b100?. four bins are created for each of the following values: • • • • 4’b0100 4’b0101 4’b0110 4’b0111 You can also constrain bins in the following fashion: wildcard bins b3[3] = (4’bx1xx => 4’bxx1x).Wildcard Array Bins Wildcard array bins are useful if you want to express array bin ranges as wildcard patterns. a separate bin is created for each value the wildcard pattern can represent. “x”.

(trans_set)} trans_set ::= trans_range_list {=> trans_range_list} | state_bin_name {=> state_bin_name} state_bin_name ::= identifier 70 . the hit count for the transition bin is incremented only if the hit counts of the state bins in the sequences were incremented in the prior occurences of the sampling event. and the third bin contains 21 + 1 = 22 transitions. the SV extensions are not compliant with the standard SystemVerilog Language Reference Manual. section 18. The first and second bins contain 64/3 = 21 transitions.The syntax example above has a total of 64 transitions. State Bin Names as States in Transition Sequences The syntax for specifying transition bins has been extended to allow state bin names to be used as individual states of a transition sequence.1. The syntax for specifying bins for transitions appears in the SystemVerilog Language Reference Manual. Note: These extensions are allowed for both SystemVerilog and OpenVera testbenches. illustration “Syntax 18-3’: trans_list ::= (trans_set) {.4. Revised SystemVerilog Syntax for Transition Bin Specifications This section outlines the extension to SystemVerilog syntax that implement this feature. However. With this new syntax.

This name must be a user-defined state bin name. covergroup gc @ (posedge clk). It cannot be the name of bad_state bin. bins s1 = {[16:20]} iff (y < 3). The following example illustrates the use of thes state bin name syntax: int cp . bins newt1 = (s0=>s1). } endgroup Revised OpenVera Syntax for Transition Bin Specifications This section outlines the changes in OpenVera syntax that implement this feature. state_bin_name Represents the name of a state bin defined in the same sample construct.state_bin_name Represents a state bin. trans trans_bin_name(state_bin_name [repeated_transition_values] -> state_bin_name [repeated_transition_values] -> …) [conditional]. 71 . m_state bin. coverpoint cp { bins s0 = {[0:7]} iff (x > 0). m_bad_state bin or “all” state bin. trans_bin_name Represents the name of the transition bin.

state s2(2). } There is no dependency on the order of specification of state bins and transition bins where the state bin names are used. } sample_event = wait_var(x) async.repeated_transition_values (optional) Specifies the number of times a particular value is to be repeated in a transition sequence. Use the following constructs: [*constant] | [*min_constant:max_constant] The constant construct must represent an unsigned integer constant. The state preceding the constants must be repeated at least min_constant times and not more than max_constant times. The state preceding the constant must be repeated a fixed number of times. The following example illustrates the use of the state bin name syntax: coverage_group COV1 { sample x { state s1(1). 72 . State bin names can be specified after their names are used in a transition bin specification. trans t0sbn(s1->s2). The min_constant:max_constant construct must represent unsigned integer constants.

The cross_bin_definition defines a cross coverage bin that combines several cross products into a single named bin or equivalence class. using the following syntax: [wildcard] state state_name ((select_expression)[logical_operator (select_expression)]) [ if (expression) ]. [. The following definitions apply to the preceding syntax: wildcard 73 . These wildcards are an extension of OpenVera syntax and are not part of the OpenVera Language Reference Manual: Native Testbench.OpenVera Language Enhancement Wildcard Support in binsof Expressions You can use wildcards (x and z) to specify ranges in the binsof expression.coverage_point_name]) { [cross_bin_definitions] [attribute_definitions] } An optional keyword wildcard is included in the cross bin definition. Extensions to OpenVera Syntax The following extensions have been made to the OpenVera® syntax: cross cross_name (coverage_point. coverage _point.

Understanding Wildcard Usage By default.Treats the x or z values as wildcards in the state declarations. select_expression Represents a subset of bins_expression. state a2 (4:7). state Can be state. The wildcard keyword treats the x value as a wildcard in the state declarations: Note: Here wildcard essentially means either 1 or 0 at the specified location. logical_operator Represents && or ||. The following code provides an example wildcard usage. a bit with a value of x must match a sampled value of x for a cross bin counter to be incremented. state_name Represents a user-specified name for the cross bin. See the OpenVera Language Reference Manual: Native Testbench for details on bins_expression. coverage_group cg { sample_event = @(posedge CLOCK). sample v_a { state a1 (0:3). ignored. or bad_state. 74 .

} sample v_b { state b1 (0). } } The example above defines a coverage group named cg that samples its coverage points on the positive edge of signal clk (not shown). that is. Sample v_b defines four bins for each possible value of variable v_b. } cross c (v_a. Cross definition c specifies the cross coverage of the two samples v and v_b. state b2 (1:8). state b4 (14:15). state b3 (9:13). state a4 (12:15).b2 75 . wildcard state c2 (!binsof(v_b) intersect {4'b1x0x}). one for each of the two 4-bit variables v_a and v_b. The coverage group includes two samples. v_b) { wildcard state c1 (binsof(v_a) intersect {4'b11zx}). then cross coverage of v_a and v_b would include 16 cross products corresponding to all combinations of bins a1 through a4 with bins b1 through b4. cross products • • a1.state a3 (8:11).b1 a1. If the cross coverage of samples v_a and v_b were defined without any additional cross bins (select expressions). Sample v_a defines four equal-sized bins for each possible value of variable v_a.

b3 a1. a2.• • • • • • • a1. c2 covers only four cross products of • a1.b4 The first user-defined cross bin. The second user-defined cross bin.b1 a4.b3 a4.b3 a4. Thus. specifies that bin c2 should include only cross products of samples v_b that do not intersect the value range of 1000 to 1001 and 1100 to 1101. a4. and a3.b4 This is similar to the behavior of the following code: state c1 (binsof(a) intersect {[12:15]}). c1. c1 will cover only four cross products of • • • • a4. This select expression excludes bins b2 and b3.b2 a4. b1 a4.b1 76 . specifies that c1 should include only cross products of sample v_a that intersect the value range of 1100 to 1111.b4 .b2 a4.. Thus.. This select expression excludes bins a1. c2.

b4 a4.• • • • • • • a1.b4 a3. Full-toggle exclusion for a signal p[1] gives a coverage toggle report of 50%. In this simulation. Without half-toggle exclusion.b4 a2. p[0] has a 0-to-1 transition and p[1] has a 1-to0 transition. #1 p = 2’b01. This can have an impact on the overall toggle coverage score. even if one of the transitions is covered.b1 a2. when you exclude an element from toggle coverage. Consider the following example: reg [1:0] p.b1 a3. Such monitoring provides an indication of the amount of activity on each element. which can be broken down as follows: 77 . VCS and VCS MX exclude both transitions.b4 Coverage Exclusion Enhancement Understanding Half-Toggle Exclusion Toggle coverage monitors each net and register for any value transition from 0 to 1 and 1 to 0. p = 2’b10.b1 a4.

res[3]. full-toggle exclusion is active for y[0]. In this example.p[0] p[0] p[1] p[1] 0->1 1->0 0->1 1->0 Covered Not covered Excluded (not counted) Excluded (not counted) Half-toggle exclusion gives you better control of the granularity of the transitions to be ignored. Half-toggle exclusion is active for x[0]. 78 . as shown below: p[0] p[0] p[1] p[1] 0->1 1->0 0->1 1->0 Covered Not covered Excluded (not counted) Covered This is the BNF syntax for the half-toggle exclusion functionality: toggle_spec : mod_or_inst : mod_or_inst_name {toggle_data} mod_or_inst : MODULE | INSTANCE toggle_data : Toggle {direction} {signal_spec} direction: 0to1 | 1to0 | NULL signal_spec : name [index] index: ID r_id r_id: COLON ID | NULL This is an example of exclusion for toggle coverage: INSTANCE: top Toggle y[0] Toggle 1to0 x [0] Toggle res[3] Toggle res[4] Toggle res[5] In the above example. The overall coverage score becomes 66. you can exclude the p[1] 0->1 transition and still cover the p[1] 1->0 transition. res[4].67% (2/3). and res[5].

The total coverage summary for the design is still shown. as well as the summary for each top-level instance.Unified Coverage Reporting Enhancements Reporting Only Uncovered Objects This section describes how URG allows you to create reports only for uncovered objects (instead of creating reports for all coverable objects). Command-Line Access URG supports a command-line option that causes only uncovered objects to be shown in the report: % urg –show brief You can use this option in combination with text mode to generate a brief text report: % urg –show text –format brief Report Changes This section describes how each report section changes when you use the -show brief option. 79 . Dashboard The dashboard report does not change.

Module List Only modules with an overall coverage score less than 100% are shown. For example. Modules with no coverable objects in them (for any reported metric) are not listed. URG does not produce a comment or other indication that such an instance has been omitted. 80 . assume the module list report looks like this: In brief mode the module list report would only show the following modules: Hierarchy The hierarchy report omits any instances that have no coverable objects in their subtree or whose entire subtree has a score of 100% (for all reported metrics).

the report would show only the following modules: Note that HNUCKIDVOXUSFT_0 is omitted because it has no coverable objects. and the subtree rooted at HNPSIDEDJI_0 is omitted because it has 100% coverage. the only parts of the hierarchy that will be deleted from the report are those entire subtrees that have coverage scores of 100%.In other words. 81 . Assume the full report looks like this: In brief mode. or that have no coverable objects in them at all.

Groups The groups report omits any groups that have a 100% score. Assertions Report URG lists in any of the tables only assertions that are not covered or that failed. Only covers and assertions that are not covered are listed. URG generates module. and group reports only for those regions that have coverage scores less than 100%. Module Header URG lists the same header for modules. However. the self-instances with 100% coverage do not link to any 82 . only entire subtrees are omitted (if any). Module and Instance Header Sections In brief mode. The total number of assertions is still reported the same way in asserts. Like the hierarchy. Tests The tests report does not change. HVP The HVP format omits any features whose subtrees are either 100% covered or which have no coverable measures in them. instance.html. including all selfinstances—even those self-instances that have 100% coverage.

If a module is hidden from the module list page. Detailed Coverage Reports URG shows detailed coverage reports only for regions that do not have 100% coverage. URG generates a detailed report for condition coverage but no detailed report for line coverage. For example. Instance Header URG shows the same instance header. URG shows the detailed report for a given metric only if that metric does not have 100% coverage in that region.report because their reports are not generated. URG shows all selfinstances because you can see how URG computed the scores for the module. Note also that the condition coverage report only shows uncovered objects. but its instances are reported. Within each region. including a list of all subtrees. the module header still appears at the top of the module page because the module header contains useful information for the whole page. if a module has 100% line coverage and 50% condition coverage. 83 .

in which case the statement would be truncated. if the module had 100% toggle coverage in all rows. URG shows only the lines that contain uncovered statements (“uncovered lines”). URG provides two lines of context above and below a statement: 84 . URG would not provide either this table or any toggle coverage details. For example. Line Coverage For line coverage reports (which provide annotated source code that shows coverable objects and which objects are not covered). along with two lines of context before and after each uncovered line. Showing some context is important because the coverage database does not know the extent of a statement—a statement could cross over several lines.URG shows the entire summary table for a metric it reports. the following summary table for toggle coverage would not omit the “1 -> 0” rows even though they are all at 100%: However.

URG shows only this information: if (some condition) if (some other condition) a <= (b ? c : ( d ? e : ( f ? g : If several uncovered lines are grouped together.if (some condition) if (some other condition) a <= (b ? c : ( d ? e : ( f ? g : ( h ? i : ( j ? k : l ))))). if (yet another condition) begin x <= y. they are all grouped together in the report. rather than reporting the information in two separate sections: if (some other condition) begin a <= b. If the statement is uncovered. For example: if (some condition) begin if (some other condition) begin a <= b. end end end The report for the above example would show the following text. if (yet another condition) begin 85 .

URG still shows the complete report for that condition (and the not-fully-covered subcondition). If a condition is fully covered but one of its subconditions is not. 86 . then URG shows the condition’s complete report (all vectors). end end Condition Coverage If a condition and all of its subconditions are completely covered (all vectors).x <= y. then URG omits the report for it and its subconditions. If a condition is not fully covered.

For example. consider the following report:   87 .

The condition at line 505 is omitted in the brief report because the condition was fully covered. with no (uncovered) subconditions. 88 . The brief report shows both the condition on line 510 and its subcondition—even though the condition itself is fully covered— because one vector of the subcondition is not covered.The brief report would appear as follows:   Note that URG shows the first condition because its subcondition (the second) is not fully covered.

URG lists only signals that are not fully covered. consider the following full report: The brief report shows only these items: 89 .Toggle Coverage In the detailed table. For example.

FSM Coverage URG omits from the report any FSMs that are fully covered (all states and transitions). Important: The page-splitting functionality applies only to HTML reports. Group Report Inside a group report. If an FSM is fully covered except for its sequences. which can cause difficulties when you load and view this report. Assertion Coverage URG list only assertions that have failed or are not covered. If an FSM is not fully covered. URG lists only bins that are not covered. URG omits the FSM it will be omitted (even if the sequence score is less than 100). these FSMs are shown in the FSM summary table—with only the FSM name and its score. However. and only its uncovered transitions and sequences. Only uncovered “covers” are listed. URG lists all of the FSM’s states. Understanding Covergroup Page Splitting The HTML version of the detailed covergroup report can become quite large. not text reports. Note the following page-splitting guidelines for covergroup reports: 90 .

Each page that is split contains a summary table of coverage information.• Instance splitting: URG splitting behavior for covergroup instances resembles code coverage splitting for module instances. after splitting: Page for covergroup a: Group a Group instance a1 91 . URG splits the bin table across several pages. When URG generates a report for any group instance. the covergroup page displays a note alerting you to the multiple-page splitting that URG has performed. before splitting: Group a Group instance a1 Group instance a2 Group instance a3 Group instance a4 Pages for covergroup a. URG checks the size of the current page and creates a new page if the report exceeds the value you defined with -split N. • Bin table splitting: If the bin table is so large that the previous splitting strategy is not enough to make the page fit in the page size limit. In this situation. The covergroup page also contains links to the various pages. URG never splits a group report. The following examples show how a report for a hypothetical covergroup a is split: Page for covergroup a.

Subpage 1: Group instance a2 Group instance a3 Subpage 2: Group instance a4 DVE Coverage Enhancements Branch Coverage and Implied Branches The DVE Coverage GUI shows implied branches in the source window (when you use dve -cov) only when you view branch coverage or are analyzing the branch metric. and then attempt to load that file with DVE. You can exclude any branches tagged in this fashion. 92 .) However. if you change the location of a coverage file. (In this discussion. the word "file" includes any of the preceding three items. DVE Coverage Source / Database File Relocation DVE normally determines the location of a coverage database. or source file by using information built into the coverage database at compilation and runtime. DVE displays a dialog asking you to provide the new location of the file. source directory. The implied branches of case and if statements are indicated by MISSING_ELSE and MISSING_DEFAULT tags.

which you provided to DVE: /X/Y/C/foo. then DVE displays a dialog asking for the correct location of the file. determines that the following location is the new root directory for design files is as follows: /X/Y Assume now that DVE performs a search for the following file. DVE subsequently uses both the built-in location and the new location information you have provided. working from right to left.v (as specified in the coverage database) is as follows: /A/B/C/foo. For example. DVE searches in /X/Y.v Thereafter. Moreover.After you provide DVE with the new location of the file.v Instead of looking in /A/B. the correct location of this file: /X/Y/E/bar. based on database information: /A/B/E/bar.v If DVE cannot find the file using the default location. 93 . DVE compares these two locations and.v But assume that you moved the file to this location. DVE compares the two locations to make a more intelligent attempt at locating the file. assume that the location of a file foo.

but not all. Note: In this discussion of “Attempted” state markers. DVE replaces any earlier root location directory with whichever new location you specify. Container Exclusion State Markers The following DVE exclusion markers indicate the exclusion state of items within a container. be aware that DVE displays the “Attempted” state marker only in strict mode. for example. the container is marked with the “Partially Excluded” state marker: The following illustration shows how the Partially Excluded marker appears in the DVE GUI in relation to the container: Partially Excluded state marker 94 . this means that the item was already covered and cannot be excluded. when you use the -excl_strict switch. When DVE marks a container as “Attempted” in strict mode. of the items in a container are excluded. that is. • Partially Excluded—When some.DVE can only remember one root location directory at a time. A container is a structural element that contains other data. a module or entity. without the need to open the container to inspect the exclusion state of the individual items in the container.

and some have been marked as attempted.• Partially Excluded and Attempted—When some of the items in a container are excluded. the container is marked with the “Attempted” state marker: 95 . the container is marked with the “Partially Excluded” and “Attempted” state markers: The following illustration shows how the Partially Excluded and Attempted state markers appear in the DVE GUI in relation to the container and its contents: Partially Excluded marker Attempted state marker • Attempted—When DVE has attempted to exclude some or all covered items in a container.

The following illustration shows how the Attempted state marker appears in the DVE GUI in relation to the container: Attempted state marker The Source window also displays container exclusion information: Partially Excluded and Attempted state markers 96 .

Note that using these options does not guarantee that coverage convergence will occur. Coverage Convergence Technology 89 . You need a special license for both compile-time and runtime usage. Some common user flows are also provided.5 Coverage Convergence Technology 1 This document describes the coverage convergence technology. This chapter describes all coverage-convergence-specific options. the constraints and coverage model need to meet certain requirements. For coverage convergence to occur. Compile-Time Options This section describes the options you use to enable the coverage convergence technology when using the VCS compiler. This chapter also includes coding guidelines that allow you to get the most out of the coverage convergence technology.

vr Example for SystemVerilog testbench: vcs -sverilog -ntb_opts cct foo. Example for OpenVera testbench: vcs -ntb -ntb_opts cct foo. coverage convergence writes automatically inferred cover groups (if any) to the directory ${SIMV_DIR}/cct_cov_gen. for a class that contains random variables and/or constraints. When you specify this option. Coverage Convergence Technology 90 .sv Coverage Model Autogeneration Options -ntb_opts cct_cov_gen Generates a coverage model for a stimulus object—that is. See “Automatic Generation a Coverage Model from Constraints” on page 96 for details on how a coverage model is inferred from constraints. Coverage Convergence Option -ntb_opts cct Ensures that the required coverage-convergence-related processing is done for all relevant coverage points. You can specify a different directory with the -ntb_opts cct_cov_gen_dir option. when you run simv).You also need to specify the options described in this chapter (as appropriate) when you execute simulation (that is.

vr Example for SystemVerilog testbench: vcs -sverilog -ntb_opts cct_cov_gen foo. -cct_enable Enables coverage convergence at runtime. Coverage Convergence Technology 91 .Note that if the cct_cov_gen directory already exists. specify the following command-line options when executing the simv generated by VCS. Example for OpenVera testbench: vcs -ntb -ntb_opts cct_cov_gen foo. Example: vcs -ntb -ntb_opts cct_cov_gen -ntb_opts cct_cov_gen_dir . The names of the files created (and the names of the coverage groups themselves) depend on the names of the classes and constraints blocks in the source file.vr Coverage Convergence Runtime Options To enable the coverage convergence functionality. any files in that directory will be clobbered when you rerun coverage convergence with the -ntb_opts cct_cov_gen option.sv -ntb_opts cct_cov_gen_dir <directory_name> Overrides the default directory (./cct_cov_gen) into which coverage convergence writes automatically inferred covergroups./my_dir foo.

The following arguments are optional. The bias file specifies the coverage holes that the test should target in the current run. When you specify the -cct_bias_file option. the targeting of holes does not start until coverage convergence determines that merely running pure random stimulus (based on constraints) is no longer resulting in increasing coverage. -cct_bias_file=<file_name> Specifies the bias file to be used for the test run. you must enable other options (such as -cct_enable). we recommend that you generate the bias file using the URG utility. the -cct_enable=on_start option is automatically enabled. See “URG Options for Bias File Generation ” on page 93 for more details.The -cct_enable option is required for running coverage convergence. By default. Coverage Convergence Technology 92 . Different runs of the test can use different bias files as input. -cct_enable=on_start Tells coverage convergence to target coverage holes from the very first call to randomize. This option is also enabled automatically when you use bias file options. Although it is possible to create a bias file manually. You can use this option when few randomize calls occurring in the test so each randomize call can be coverage-aware. For the bias file to have any effect.

These options generate bias files./biasConfigs directory. See “Understanding Bias Files and Coverage Convergence” on page 106 for more details. By default. the bias files are written into the ./<my_dir> Overrides the default directory setting that determines where the bias files are written. if you choose to edit the bias files. do not deviate from the bias file format.URG Options for Bias File Generation This section describes the URG options related to coverage convergence. such as -dir and -format. Coverage convergence creates the directory if the directory does not exist. The bias files are text files that represent coverage holes. -group cct_gen_bias <non-zero integer> Instructs URG to partition all the coverage holes in the input database into the specified number of bias files. Coverage convergence writes the bias files to the . Coverage Convergence Technology 93 . Avoid editing the bias files by hand./biasConfigs directory. You use the bias files to bias coverage convergence to target specific coverage holes. -group cct_gen_bias_dir . You can use each bias file generated with the cct_gen_bias option as an input to a test run. The URG options described in this section are in addition to other required URG options. However.

Coverage Convergence Technology 94 . In other words. then it is possible that coverage bins might not be hit. the randomize and coverage sampling should happen on the same instance of the generator class. If there is procedural code (in post_randomize for example) which overwrites the values generated by the solver.Coding Guidelines The following sections provide coding guidelines for using coverage convergence. even though the solver is generating the right values for the random variables. Constraints and Coverage Model on the Same Variables Coverage convergence works when the coverage model is on the stimulus variables. No Procedural Overwriting of Values Generated by the Solver Coverage convergence works by generating constraints for all the coverage holes and by enabling these “coverage constraints” during consecutive calls to randomize. Constraints and the coverage model should be in the same class. Further. the cover points (and cover point expressions) should be the rand variables that represent the stimulus.

With coverage convergence enabled.Coverage Should Be Sampled Between Consecutive Calls to randomize The sampling event for the coverage model should be triggered between consecutive calls to randomize. then load a preexisting coverage database before starting the stimulus generation. the solver is automatically focussed on the portion of the legal space that is covered by the coverage model. Use Open Constraints In an ideal scenario. Do not use test constraints. Coverage convergence will not target anything that is covered in the loaded database. An alternative is to use the @randomize sample event. Using this sample event ensures that the cover points are sampled as soon as randomization is completed. to ensure that all generated values are sampled. Coverage Convergence Technology 95 . Test constraints further constrain the legal environment to focus the solver on a specific part of the legal space. If you want to focus the solver in coverage convergence mode. you should specify only the legal (or environment) constraints when running coverage convergence.

Avoid Explicit or Implicit Partitioning in Constraints Coverage convergence might not work efficiently when there are explicit or implicit partitions in the constraint problems. The intuition is that a better sampling of the stimulus space will exercise the design behaviors more exhaustively. increasing the likelihood of hitting coverage goals. If the structure of the constraints is changed using in-line constraints or turning constraints or randness off and on using “constraint_mode” and “rand_mode”. then the performance of coverage convergence might be compromised. Explicit partitioning is enabled by using “solve before” constructs. If partitioning does happen and coverage convergence is enabled. Coverage Convergence Technology 96 . Implicit partitioning is enabled when there are function calls in constraints or when object allocation is enabled. Avoid In-line Constraints and the Use of “constraint_mode” and “rand_mode” Coverage convergence is designed to work on the static structure of the constraints and coverage. Automatic Generation a Coverage Model from Constraints One of the goals of coverage convergence is to extract a functional coverage model from the constraint expressions. and automatically cover it. then partitioning might lead to some loss of efficiency for coverage convergence: some coverage bins might be targeted but not covered.

The cover groups will contain items as described below. The cover group for the class that will contain the coverage model for variables will be called covg_<class_name>. A cover group will be generated for each class to contain the coverage model derived from variable declarations in the class. Coverage Convergence Technology 97 . except for variables that have an unguarded set membership constraint at the top-level. For example: enum PktType = {Type1. The following sections detail the types of cover points and crosses that will be inferred. The members of the cover group (cover points. Cover Points Variable Coverage Each rand variable will have a cover point associated with it. rand bit[7:0] x. Coverage Groups A cover group will be generated for each class by default. rand PktType p. crosses) will be annotated with comment attributes in a manner that will allow tracking back to the original constraint expressions. Type2}. PktType prevp. in any of the constraint blocks of the class.The plan is to provide a first-class “contract” to the user which specifies how the coverage model is inferred and how goals are named.

. 5}. a cover point will be inferred for p. autobinned cover points will be created for x and p. In the above example. The built-in function rand_mode can be used to turn off the randomness of a rand variable. <cover_point_id> is a unique integer identifier for every cover point. The autobins for the cover points will be named by the usual naming convention for autobins. . } Here. rand bit[31:0] y.constraint c1 { x in {0:1. Coverage Convergence Technology 98 . For example: rand bit[7:0] x. The cover point expression will be just the variable. But the collection of coverage for such variables will continue irrespective of the mode change. for variables with precision 8 bits or less. with a maximum of 64 bins.. . Equal volume autobinning. with the bins for x having the ranges 0–3. and the bins for p having the values Type1 and Type2. Note that a set membership cover point will be inferred for x. 4–7. 252–255. The comment for the cover point will indicate details about the variable. rand PktType p. but not for x or prevp. The following rules apply to the creation of bins: • • Autobinning for enum type variables. The cover points for variables will be called covp_<cover_point_id>.

The cover points will be guarded by the conjunction of all the enclosing conditional guards. The cover point expression will be the conjunction of all the enclosing conditional guards. For example: if (p || (q && r)) { . Coverage Convergence Technology 99 . Condition Coverage (Sensitized) Each sensitizing guard condition will have a Boolean cover bin associated with it.. there will be a coverpoint with the expression p&&q. The idea is to make sure that the conditional expression becomes true at least once for every implicant in the expression being true. For example: if (p) { if (q) { x == y. } In the above example. there will be a cover point with expressions p || (q && r) with one bin corresponding to the case when expression p is ON (or true) and one bin corresponding to the case when expression q&&r is true. The comment for the cover point will have the expression string.Branch Coverage Each conditional block will have an associated Boolean cover point.. } } In the above example.

For example: if (p in {0:4. } Here the cover point expression will be p. and the sensitizing conditions are defined over these atomic subexpressions. does not result in an inferred cover point. 7}) { . For membership in sets with constant members: Coverage Convergence Technology 100 .. whereas x >= 0 && x <= 5. Set Membership Coverage We will infer a cover point for constraints coded using the in and dist operations. and the bins 0. Also. use of set membership in complex constraints does not result in an inferred cover point. The comment for the cover point will have the expression string. the condition coverage model will be generated like the set membership coverage model. ! are considered as atomic. ||.Note: The subexpressions of the guard expression involving operators other than &&. 1–3. Equivalent ways of writing the same constraints using other operators might not result in an inferred coverage model. When the condition expression is a set expression. 7 will be created. For example: x in {0:5}. 4.. results in an inferred cover point.

5. 1–4. 7}. The sample expression will be the same as the LHS value in the set membership constraint. for membership in sets with nonconstant members: • A cover point with three Boolean cover bins will be created for each of the ranges as follows: .A bin with the expression (range_high_expression). In the above example.• • • • • A single cover point will be created. For example: x in {0:5. 7 will be created. b}. Coverage Convergence Technology 101 . For example: x in {a:5. A bin will be created for the low value of each range.A bin with the expression (range_low_expression). . . Hence. if the resulting range is non-empty. The functional coverage language does not allow dynamic variables (those that are not parameters to the coverage groups) to describe bin ranges. A bin will be created for the range excluding the low and high values of each range. 0. a cover point with expression x and four bins. for nonsingleton ranges.A bin with the expression (range_low_expression + 1 : range_high_expression -1). A bin will be created for the high value of each range.

then no coverage bin will be inferred for that range. One bin with value range (a+1:4). The cover points and bins for x. We will define control variables as variables that are of enumerated types or bit-vectors that are 8 bits wide or less. then the first two bins would not be inferred. y will be generated. will be used to generate crosses. Crosses Combinations of control variables in the class. Coverage Convergence Technology 102 . then a cross x. Note: All the cover points above will be guarded by the conjunction of all the enclosing conditional guards. for which a variable coverage cover point is generated. if a in the above example were specified as rand. The cross will be autobinned. y. Cross on Variables Within a Class If a class contains control variables x. a cover point will be created for variable x with the following bins: • • • • One bin with value a.In the above example. y will be as described in the section on variable coverage. For example. Note: If the set membership range expressions use random variables. One bin with value b. One bin with value 5.

cover points for x will be generated from the set membership constraint. we will generate a cross of the cover points for coverage of the condition (sensitizing). This cross will be autobinned. Cross of Condition and Constraint Expressions The sections on condition coverage and set membership described two kinds of cover points. A cross for the two cover points will be generated.). The crosses will be called covc_<cross_id>. Cover points for the condition expression will be generated. Coverage Convergence Technology 103 . If more control variables still remain after previous step. 7}. In the case of set membership constraints inside conditionals.The set of variables that participate in one cross is determined as follows: Control variables will be added to a cross until the total number of expected bins (product of underlying cover point bins) of the cross does not exceed 64000. then a new cross will be created. For example: if (p || (q && r)) { x in {0:5. The comment for the cross will indicate details about the crossed variables (class name. line. } In the above example. Sampling Event A special built-in sample event called @(randomize) will be used to determine the sampling for the generated coverage groups. file. etc. <cross_id> is a unique integer identifier for the cross.

. In fact. then the allocation of the objects is done before the values are populated back. Coverage Model Inference for In-line Constraints Since in-line constraints (randomize with {.This event can be used in user defined cover groups that are embedded in classes. coverage is tracked for the instance and/or the cover group definition (that is. after the solver is done. The @(randomize) event is triggered on all rand objects in the context being randomized. Coverage Convergence Technology 104 . hence before @(randomize) is triggered. either directly or through containment inan instance of another class being randomized.0. we will not infer a coverage model from such constraints. cumulative). Contribution to Coverage Scoring The automatically generated coverage model will contribute to the coverage score by default with a weight of 1. When the event is triggered. If objects are being allocated by randomize. The event istriggered when an instance of this class is randomized.}) is recommended for use in the specification of test constraints. and values have been populated in the objects. we expect the use of test constraints to be minimized after coverage driven stimulus generation is implemented.

All the coverage models will be written out as text files in the cct_cov_gen directory. The user is encouraged to view the autogenerated coverage model and make changes if required. The VCS compiler does not compile the design when cct_cov_gen is specified (that is. no simv is created). Both System Verilog and OpenVera testbench formats are supported.vr Example command line for a SystemVerilog testbench. Example command line for an OpenVera testbench: vcs -ntb -ntb_opts cct_cov_gen foo. Coverage Convergence Technology 105 . The language in which the coverage model will be generated is the same as the syntax of the testbench. vcs -sverilog -ntb_opts cct_cov_gen foo.Use Model Autogeneration of coverage model is done as part of the VCS compile step. The switch to enable coverage model generation is -ntb_opts cct_cov_gen.daidir and simv files are generated by VCS compiler. Then the user will include the coverage model into their testbench (using `include or #include directives) and then make sure the coverage model is instantiated in the new task for the enclosing class (that is. The cct_cov_gen directory will be present wherever the simv. the class where the constraints and random variables are specified).sv It is expected that the user will first create a coverage model using the auto_gen option.

the source files (constraint. Coverage convergence seeks to automatically target coverage holes by identifying the coverage holes and directing the constraints solver to generate stimulus such that the coverage holes will be hit. Coverage Convergence Technology 106 . with each simulation being assigned a different random seed. What Is a “Test”? A test for the purpose of this document is an executable that can be simulated (for example. such as different random seeds or configuration files and the simulation results can be observed. coverage convergence tries to hit coverage holes within a test. It is desirable that with coverage convergence enabled. Coverage convergence works at a test level. that is. design files etc. simv generated by VCS). Note that the executable is created once. each test be able to target different portions of the coverage space in order to meet the coverage goals in the shortest possible clock time.Understanding Bias Files and Coverage Convergence Motivation Coverage convergence is a new technology that enables coverage convergence for testbench functional coverage. The executable can then be invoked multiple times with different runtime options. verification tests are run on a regression farm. The source files (testbench files. where multiple copies of the tests are being executed in parallel on different machines in the farm. coverage models. cover groups. that is. that is.) are compiled by VCS compiler and linked with the simulation engine to create the executable. In most customer environments.

Thus any invocation of the simulation executable can target any of the existing valid coverage holes. Note that in many existing methodologies. Using Coverage Convergence Bias File to Pick Target Coverage Holes The user can influence the coverage holes being targeted by coverage convergence in a test run is by using a coverage convergence bias file. The coverage convergence bias file format is a text file representing coverage holes. modules etc. Coverage Convergence Technology 107 . The bias file approach described below works best with tests using an open set of constraints and a full coverage model.) do not change with every execution. From the coverage convergence point of view. This file can be modified by the user if needed.transactors. This is typically done to focus the test towards some verification targets such as coverage or specific features. The different options passed with every execution lead to different behavior of the simulation. This is a file that contains a list of coverage holes which the coverage convergence engine will target when the test starts running. a “test” should consist of a testbench with an “open” set of constraints: the constraints should represent the entire legal stimulus space. the constraints in a “test” consist of the legal constraints as well as a set of test constraints that limit the solution space of the legal stimulus.

the coverage convergence engine will read the bias file and populate its in-memory coverage hole database with the data from the coverage convergence bias file. then they will not be reactive.Runtime Option to Specify a Bias File The coverage convergence bias file will be passed in as a runtime argument for the test run. that is. If the data in the bias file is for a coverage group which cannot be targeted by coverage convergence. • • • • Coverage Convergence Technology 108 . if more randomize calls occur. It will only influence coverage convergence. After all the holes are targeted. The bias file has no impact on the coverage engine and on coverage reporting. If the coverage convergence bias file as pointed to by the -cct_bias_file option cannot be read. Then it will systematically start targeting the holes. When the test starts executing. The bias file will be read and processed by the coverage convergence runtime engine. Only the coverage holes present in the bias file will be targeted. • The holes in the coverage convergence bias file are all at a coverage group definition level. They will apply to all instances of the coverage group in the test. using -cct_bias_file=<path_to_cct_bias_file>. The test will run as though no bias file has been specified. then an error will be issued the file will be ignored. for which reactivity can be applied and can be enabled. then all the data for that coverage group is ignored by the coverage convergence engine. The test does not need to be recompiled if the bias file is changed or a new bias file is to be used for the test. no coverage hole will be targeted.

For example.• • There are no restrictions on the name of the coverage convergence bias file. It is an error if N is greater than the number of coverage bins in the coverage database. The bias files will be written out in the ${PWD}/ cctBiasConfigs directory as config0. config(N-1). but coverage convergence can choose to override these guidelines in certain situations. it will be assumed that there is only one shape for Coverage Convergence Technology 109 . config1. The bias file will provide a guideline as to what coverage bins are targeted by coverage convergence. coverage convergence will not target coverage bins that have been assigned a zero weight by the user or coverage bins belonging to disabled by the user using the collect attribute or by using coverage_control system task. Automatic Generation of Coverage Convergence Bias Files URG automatically generates coverage convergence bias files for a particular test. Other URG options (such as –format) can also be used simultaneously to process the coverage data. The utility can be invoked as follows: $VCS_HOME/bin/urg –dir <coverage_db_dir> -group cct_gen_bias <number_of_bias_files_required> The utility will enumerate all the coverage bins in the input database files and will create N random partitions of the holes where N is supplied by the users using the num_bias_files argument. where N is supplied by the user. Since the coverage convergence bias file represents coverage bins at a coverage group definition level. URG can be invoked on a coverage database file and will generate N bias files.

the sequence of values generated by the solver will be exactly the same. If multiple coverage definitions are detected. Coverage convergence ensures that given the same inputs and the same command line arguments. Repeatability of Test Results for Parallel Regression Runs An essential requirement for the approach outlined above is that it should be possible to reproduce the results of a test run in a parallel regression environment in a stand alone manner. if a test fails in the parallel regression run. it should fail in exactly the same manner when run on its own. and the arguments are the random seed and the -cct_bias_file argument. Usage Scenarios This section discusses coverage convergence usage in various common verification scenarios. More specifically. coverage and constraints are on the same variables. Here the inputs are the bias file and the test source code. it is assumed that the guidelines mentioned in the previous section are being followed (for example.every coverage definition in the input coverage database. In all the scenarios in this section. then an error will be issued and not bias files will be generated. The bias files generated by URG can then be used as input to tests being run in parallel. and so on). Note that this means that the regression system needs to preserve the bias file used by a test in addition to other test source code and scripts. Coverage Convergence Technology 110 .

configurations are selected. This scenario is required for packet-processing devices or instruction-based processor verification. in which the device has many interfaces and many modes and the device can be configured to select some interfaces and some modes. Coverage Convergence Technology 111 . The coverage database must be loaded after all the testbench components have been instantiated. only one configuration might be selected (for example.randomize is performed only once).You can load a preexisting coverage database in every scenario to screen out already-covered coverage bins. In this scenario it is important to preload the coverage database to ensure that already-selected configurations are not chosen. By doing so. and then data (possibly random) is passed through the device. In the testbench. Running a Single Test with Randomized Transactions This scenario applies to transaction-based verification environments. Running a Single Test with Randomized Configurations This scenario generally applies to multimedia devices. In the extreme case. The object of verification is to exercise all the interesting configurations of the device. so that the coverage data from the database can be loaded in the proper (in-memory) runtime database. the current run can focus only on uncovered bins. Configurations for a device are typically chosen (through randomize) a few times per test run. config.

2. Perform bias file generation for the next batch of tests using the following command: Coverage Convergence Technology 112 .The device is set in some mode. status = transObj.randomize(). If you assume that many transactions will be generated (randomized). then it is appropriate for the convergence heuristics to take over and apply reactive calls as needed. you can use the default arguments for coverage convergence. Merge the coverage results for all 100 tests in the first batch and store the results in merged. You use constraints to generate the transaction objects. and then multiple transactions are generated and passed through the device. 4. 1. } Using a Bias File for a Parallel Regression In this scenario. you use the bias file generation utility to bias inputs for different parallel test runs. status = transObj. Wait for first batch run to complete. 3.vdb. or repeat (1000) { transObj = new. In this scenario.randomize(). Run the first batch of tests using the following commands: $SIM -cct_enable +ntb_random_seed = ${SEED} Assume that each batch contains 100 tests.

/cct_cov_gen/MyClass. Add the declaration for the generated cover group as part of the class member declarations.$VCS_HOME/bin/urg -dir merged. Coverage Convergence Technology 113 .vr Coverage convergence generates the model in the file . However. 1. Autogenerating a Coverage Model Coverage convergence can generate a coverage model from the constraints specification. 7. If coverage has not reached your coverage goal. you must instantiate the coverage model that you intend to use in the simulation. Run the second batch of 100 tests with each test using a different bias file as an input: $SIM -cct_enable -cct_bias_file=<bias_filename> 6.vdb -group cct_gen_bias 100 This command distributes the remaining coverage holes into 100 bias files. Examine the generated model to determine if the model meets your expectations. Merge results from the second batch of runs. then repeat steps 3 through 5. Autogenerate the coverage model: vcs -ntb -ntb_opts cct_cov_gen foo.vr. 2. 5. 3.

Make the cover group instantiation the last statement of the new task. 5. then you must add to the other member declarations for the class MyClass: coverage_group MyCov. then you must add the task to the cover group instantiation. the constraints are exactly the same for all the tests). Each test should have its own bias file. If the new task does not exist. Because the name of the autogenerated cover group is deterministic. The autogenerated coverage group must be instantiated in the new task of the enclosing class. Perform the instantiation with the following statement: MyCov = new. then the coverage convergence bias file approach can be used to achieve high efficiency test runs. Scenario: All Tests Have the Same Constraints and Coverage Space (Recommended) When all the tests being executed in parallel have exactly the same coverage space and the same legal stimulus space (that is. the declaration and instantiation can be done once during testbench development phase. 6. The input Coverage Convergence Technology 114 .For example. 4. Methodology and Flow Issues This section addresses methodology and regression execution issues. if the name of the covergroup is MyCov and it is of the class MyClass.

After all the tests are done running. The URG bias generation utility can be used to generate a bias file template. tests have test specific test constraints which further constrain the legal stimulus space and thus also reduce the hittable coverage bins. It is desirable that the number of times the stimulus objects are randomized in a test be at least equal to the average number of coverage bins in the bias files. all it causes is less efficient utilization of resources. It is possible but not efficient to use both the random seed and the bias file for every test. In this scenario too. Once the bias files are generated. The test writer can then modify this template to include the hittable coverage bins. then the bias files have to be generated once and can be used for multiple regression runs. Each test within this category can use the same bias file but with a different random seed. Scenario: Tests Are Grouped Into Categories With Each Category Having Specific Test Constraints In this scenario. A bias file can be created for every category of tests. Coverage convergence may use some cycles in the test run to try to target unhittable bins. they can be used again and again for repeated regression runs. assuming test constraints remain constant across regression runs. but remaining cycles will still target hittable coverage bins. (Coverage bins whose value ranges lie outside the space of the test constraints cannot be hit). the Coverage Convergence Technology 115 . Even if all the bins in a bias file are not hittable. (Note that the URG does not look at test constraints when generating the bias files). As in the previous scenario.database for the URG utility can be obtained by running any test and using the output coverage database. the coverage database from all the tests can be merged to get the final coverage number. The bias file should be such that all the coverage bins in the file are hittable given the test constraints for that category. The number of test runs should be used as the value for the cct_gen_bias argument for URG.

Note that for repeatability purposes. the coverage databases are merged and the merged database is used as input for the next batch of tests.coverage data from all the tests can be collected and merged. then there is no need to use a coverage convergence bias file. For this final sequential run. then a random seed can be used so that each test targets different holes. so it is already biased in some sense. but one batch of tests is run at one time. Hence it does not make sense to use both coverage database load and coverage convergence bias file approaches for a test. the input database associated with a test needs to be preserved in case the test needs to be run in a stand alone mode. holes in the bias file will be targeted even if they are marked as covered in the loaded coverage database. the merged coverage database can be used as an input along with the fully open constraints. Scenario: Coverage Database Being Loaded in the Beginning of a Test Run If a coverage database is being loaded as part of the configuration for a test. that is. then it will override the bias from the loaded coverage database. If a coverage convergence bias file is used. This is useful in a batch mode type of regression environment. If the same database is loaded in multiple tests. Then a sequential run can be used to target any remaining coverage holes. After the batch is complete. Here all tests have the same constraints and coverage space. Coverage convergence will only target coverage bins that are not covered in the loaded database. Coverage Convergence Technology 116 .

6 DVE Features 1 The following features are included in this release of the Discovery Visual Environment (DVE): • • • • • • • • “Back Tracing” on page 118 “Editing the Bus Bit Range” on page 121 “Creating and Updating Counters” on page 122 “Deleting Signal Group” on page 125 “Creating Multiple Groups when Adding Multiple Scopes into Wave View” on page 126 “Visualizing X at all Zoom Levels” on page 126 “Using Filters” on page 127 “Viewing Interfaces as Ports” on page 128 DVE Features 117 .

The Wave view provides a temporal view and provides information to decide which signals need further tracing. To back trace a signal 1. You can invoke the Back Trace Schematic view from any of the following windows: • • • • Waveform Schematic Path Schematic Data Pane The Back Trace Schematic consists of two panes .a Wave View pane and a Path Schematic pane. Open DVE and click File > Open Database. across gates to identify the signal that caused the X value. for example. You can back trace an X value to its source signals.Back Tracing Back Tracing helps you debug a particular signal by traversing the design backwards both structurally and temporally. You can close the Wave view if not needed. DVE Features 118 . The Path Schematic pane is the main structural view. You can use the Back Tracing feature for doing the following tasks: • • • Remove the steady state and zero delay restriction for usage Reduce the number of drivers identified as causes for an X value Interactively drive the tracing process Back Tracing in DVE is performed by Back Trace Schematic view.

The database is loaded in the Hierarchy pane. Note: Only one-level can be expanded for non-X signals. The input pins of the driving cell are annotated with the values and times of the next signal transition. right-click and select Back Trace to fetch signal for further back tracing. 2. the current simulation time is moved to the earliest time over all driver inputs. The Back Trace Schematic view opens. right-click and select Back Trace Schematic. The current simulation time and value pair are annotated on the output pins of the driving cell. The traced signal "fetch" is added to the Wave view and its drivers are added to the Schematic view. A wave group and Waveform view of the selected signal is automatically created at the current simulation time. 3. 4. Select a scope in the Hierarchy pane. Select the Reset signal in the Data Pane. The first transitions are added to the inputs to the drivers. DVE Features 119 . Select the Fetch signal in the Data pane. The signals are displayed in the Data pane. Also.

"Match".Adds the signals on the traced path to the wave group and displayed in the wave view. so that tracing X signals can automatically trace back multiple levels following the X value over time.Maximum time threshold . The delay from an input to output will determine the time window where a value change can occur.Setting the Back Trace Properties The Back Trace Properties window is used to add multiple levels of trace. "Rising". There are several ways to search the waveform for the specified signal.Controls the maximum number of levels to search backwards when automatically searching for X values.Controls the maximum amount of time to search backward in a waveform for a value change.Controls the time to stop the trace. DVE Features 120 . .Trace stop at . "X Value". . .Number of levels to trace . "Miss Match". Select Trace Parameters or click the Trace Parameters button on the toolbar. you can draw multiple levels and add multiple signals on the traced path to the Wave view.Add traced signals to wave group . You can specify to stop at "Any Edge". Once a signal is selected. or "Value". The Back Trace Properties window opens that contains the following options: . To set the Back Trace properties 1. the default is the time annotated by back tracing. "Falling". So instead of expanding one level.

Editing the Bus Bit Range You can edit the bus bit range by simply changing either the MSB (most significant bit) or the LSB (least significant bit) of the bus. You can also drag and drop the signal in the Bus/Expression dialog. DVE Features 121 . 2. Controls the maximum number of levels to search backwards when automatically searching for X values. To edit the bus bit range 1. Opens the Trace Parameter dialog.Using the Back Trace Schematic Toolbar The Back Trace Schematic toolbar contains the following options: Table 6-1 Options Show/Hide Wave View Trace Parameter Search Forward/Search Backward Back Trace Trace Levels Back Trace Schematic toolbar Description Shows or hides the Wave view in the Back Trace Schematic. Searches signals forward/backward. Select the bus in the Data pane or from the Wave view signal pane and select Signal > Set Bus from the menu. The Bus/Expression dialog box appears. Double-click the signal and edit the range. Stars back tracing the signal.

The counter is supported both in post processing mode and interactive mode.a[3]. Counter is treated as a special expression and you can create or update counter in the same way as you create an expression in the Bus/Expression dialog box. and click on create/update. You need to enter the correct format to save the bit range. To create and update a counter 1. with simulation going on. In interactive mode. a warning message is displayed and the text color of the signal becomes red. DVE Features 122 . You can perform all the toolbar operations on the expanded signals. The Bus/Expressions dialog box is displayed. Select the signal and click the “+” icon to expand. 3. define a signal ias a[0:7]. For example. a[1:3] signal will expand to a[1]. Select a signal in the Data pane and select Signal > Set Expressions from the menu.a[2]. a[6].For example. A bus will be created/updated with the selected 2 bits as a[7]. If you enter a wrong range. The signal is expanded in the same order as specified in the name. the count result will be updated as other signals in the Wave view. Creating and Updating Counters You can create counter signal to count the value transitions for expression or signal. change the bit range to a[7:6].

then drag and drop the signal that you want to create for expression counter from the Wave view or Source view under the Expression area. EXP:mycount. 3.2. For example. 4. DVE Features 123 . Type a counter name in the Name field. Click the Expression tab. Select the checkbox Expression is used as a counter (counting for non-zero results) to create a signal that represents the value transitions of the expression.

5. counter signal counts this transaction. DVE Features 124 . .This option is for any expression/signal. Whenever the value of the expression/signal changes. Select any of the following Counter Edge as desired.Any Edge .The Counter Edge radio buttons get enabled.

- Rising - (Default) This option is only for bit type signals. Whenever the expression/signal changes from low to high, counter signal counts the transaction. - Falling - This option is only for bit type signals. Whenever the expression/signal changes from high to low, counter signal counts the transaction. 6. Click Create. The newly created expression counter is displayed in the Bus/ Expressions dialog box. You can also view the count results in the Wave view. 7. Drag and drop the counter in the Bus/Expression dialog box to update it. For example, you can update the counter edge from “Rising” to “Any Value”. 8. Click the Update button. The counter is updated. You can view the count results in the Wave view.

Deleting Signal Group
When you delete a signal from the Wave view, it will be deleted globally. If the same signal is present in few other views, and you want to delete it, a warning message is displayed. You can either select to delete or hide the signal. Once you select to delete the signal, it would be deleted globally from all views. If you select to hide the signal, it will be hidden in the current view.

DVE Features 125

If the signal groups are deleted, save session will not have the deleted signal groups. If you hide the signal, it will be hidden when you are saving or reloading the session.

Creating Multiple Groups when Adding Multiple Scopes into Wave View
When you add the scopes to the waves, lists, or groups from the Hierarchy pane, the signal groups will be created based on their respective scopes. If you select Display signal group exclusively in the Application Preference dialog box, and add multiple scopes to Wave view, multiple scopes will be created, but only the last group will be displayed.

Visualizing X at all Zoom Levels
While debugging a design, you can visualize the X value in the Wave view at all zoom levels. To visualize X value 1. Select a signal in the Signal pane with many value changes. 2. Zoom out the signal until the waveforms are condensed to yellow bar. 3. Right-click the signal and select Highlight X Values or select Signal > Highlight X Values from the menu.

DVE Features 126

The waveform is refreshed in the Wave view and X values are displayed as red color lines for all the zoom levels.

Using Filters
You can enter the filter strings in three different styles: • • • Explicit wildcard (Default) Implicit wildcard (*) at the beginning and end of filter string Regular expression strings

The logical OR operator "||" is supported in Explicit and Implicit wildcard strings. The Filter drop-down is also available in the Data pane, Wave Viewer, and Signal Search Results Dialog. To use the filter 1. Click Edit > Preferences. The Application Preferences dialog box opens. 2. Click the Global category. 3. In the View Filters group box, select the following options, as appropriate: - Apply view filters immediately when typed - Case sensitive - Syntax - The following options comprise the Syntax drop-down list:

DVE Features 127

-Wildcards - Input the wildcard pattern to filter items. The default string is “*”. -Simple - Input the regular expression pattern to filter items. The default string is ““. -Regular Expressions - Input the simple string to filter items. The default string is “.*”.

Viewing Interfaces as Ports
You can view Interface/Modport in the Data pane when it is passed as port. You need to select the module name in the Hierarchy pane to view the port in the Data pane. You can add the interface/modport port to the Wave view, List View, or Watch view. To view the interface port in Data pane 1. Load the database in DVE. The module is displayed in the Hierarchy pane. 2. Select the module.

DVE Features 128

The interface/modport port and its type is displayed in the Data pane. The tooltip shows the interface/modport used.

3. Click the “+” button under the Variable column in the Data pane to expand the interface/modport port. The signals under the interface/modport port are displayed. 4. Right-click the interface/modport port in the Data pane and select Show Source. The source of interface/modport is shown in the Source viewer. You can also drag and drop the interface/modport from the Data pane to the Source viewer. 5. Use the Text filter or Type filter drop-down and select the Interface/ Modport port filter to filter the signals.

DVE Features 129

6. Select the interface/modport port in the Data pane and select Signal > Show Definition from the menu or right-click the signal and select Show Definition. The definition is shown in the Hierarchy pane, signals of interface/ modport port in the Data pane, and the definition location is shown in the Source viewer. 7. Drag and drop the interface/modport port from the Data pane to the Wave view or right-click and select Add to Waves.

The Interface/Modport port is shown in the Wave view.

Limitations
The following are few limitations of this feature: • Interface array port is not displayed in the Data pane.

DVE Features 130

Driver/Load, schematic/path schematic operations do not support interface port and signals of interface port. A warning message is displayed when you perform these operations. Follow signal doesn't work for interface port and signals of interface port. Modport clocking port is not shown in the Data pane.

• •

DVE Features 131

DVE Features 132

7
Viewing values in Symbolic format 1
You can view the values of signals/variables in the same radix as specified in the source code. In addition to existing radixes decimal, hexadecimal, binary, and octal, UCLI supports the symbolic radix that will enable you to view the values in the same radix. The default radix will hence be symbolic. To change the default radix from symbolic to any other (binary, hexadecimal, octal, and decimal), use the following command option:
ucli> config -radix hexadecimal

This will set the radix format to hexadecimal. If the default radix is changed to any other, you can still view the values with the default symbolic radix by passing symbolic argument to –radix.
-radix symbolic
“Viewing values in Symbolic format” 133

Example:
ucli> show –value top.dut.x –radix symbolic

“Viewing values in Symbolic format” 134

addr => typedef struct 'b0001001000111111)} { bit [7:0] opcode. struct1_type struct1= '{1. light 1 int_vec (15. logic16_1 'b1000000000000001 struct1 {(opcode => 'b00000001. Table 7-1 Verilog/SystemVerilog Data Types Symbolic output wire4_1 'b01xz reg16_1 'b1000000000000001 Example wire [3:0] wire4_1 = 4'b01xz." enum {red.-21) string string_sig="verilog_string"." logic [15:0] logic16_1='h8001. integer int_vec [1:0]='{15. green} light=yellow.21}. 16'h123f}. } struct1_type. reg [15:0] reg16_1 =15'h8001. string_sig verilog_string “Viewing values in Symbolic format” 135 .The following tables list various data types’ use model and illustrate the output format for the symbolic radix. bit [15:0] addr. yellow.

BIT_ARRAY_SIG ('b00. Symbolic output STDL 'bH STDL_VEC'bUX01ZWLHH signal real_sig:real := 2. REAL_SIG 2.2000000000000002. signal bit_array_sig : bit_array_type := (("00").200000e+00 type bit_array_type is array (0 to 1) of bit_vector (0 to 1). CHAR_SIG P signal string_sig : STRING(1 to 17) := "THIS IS A MESSAGE". signal stdl_vec : std_logic_vector (0 to 8) := "UX01ZWLHH”. TIME_SIG 5 “Viewing values in Symbolic format” 136 .'b01) signal char_sig : character := 'P'. STRING_SIG {THIS IS A MESSAGE} signal time_sig : time := 5 ns.Table 7-2 VHDL Data Types Example signal stdl : std_logic := 'H'. ("01")).

“XMR Support in Constraints” on page 141 • “Constraint Debugging and Profiling” on page 144 .8 Constraints Features This chapter contains the following sections: • “SystemVerilog Constraint Features” on page 138 .“Array and XMR Support in std::randomize()” on page 138 .“Using the Hierarchical Constraint Debugger Report” on page 147 • “Debugging Constraint Solver Diagnostics” on page 150 .“Using Constraint Profiling” on page 144 .“Solver Overview” on page 151 1 “Constraints Features” 137 .

VCS supports all types of arrays: • fixed-size arrays “Constraints Features” 138 . VCS std::randomize() support has been enhanced to allow the use of arrays and cross-module references (XMRs) as arguments.“Classes of Constraint Diagnostics” on page 159 SystemVerilog Constraint Features The following SystemVerilog constraint features are new: • • “Array and XMR Support in std::randomize()” on page 138 “XMR Support in Constraints” on page 141 Array and XMR Support in std::randomize() VCS allows you to use cross-module references (XMRs) in class constraints and inline constraints.“Using the Constraint Solver Diagnostics” on page 156 .“Methodology for Using Unidirectional Constraints” on page 152 .“Search Space Reduction And Random Assignment” on page 155 .“Constraint Solver Search Space and Solution Space” on page 154 .. in all applicable contexts. XMR means a variable with static storage (anything accessed as a global variable). Here.

success= std::randomize(fa[2]). variable-sized arrays. success= std::randomize(pkg::xmr). Syntax integer fa[3]. and XMRs as arguments to std::randomize(). “Constraints Features” 139 . Array elements are also supported as arguments to std::randomize(). array elements. success= std::randomize(fa).• • • • associative arrays dynamic arrays multidimensional arrays smart queues Note: VCS does not support multidimensional. VCS supports all types of XMRs: • • • • • • class XMRs package XMRs interface XMRs module XMRs static variable XMRs any combination of the above You can use arrays.

VCS prints the following error message: Error-[CNST-VOAE] Constraint variable outside array error Random variables are not allowed as part of an array index. foreach(fa[i]) $display("%d %d\n". i. all arguments have rand mode ON. and that XMR that cannot be resolved. success = std::randomize(fa). fa[i]). This is consistent with how std::randomize() is specified in the SystemVerilog LRM. i. “Constraints Features” 140 . success. VCS ignores any rand mode specified on class member arrays or array elements that are used as arguments.Example module test. initial begin foreach(fa[i]) $display("%d %d\n". integer i. integer fa[3]. fa[i]). Error Conditions If you specify an argument to a std::randomize() array element which is outside the range of the array. VCS prints an error message. and none of them are randc. end endmodule When std::randomize() is called. This means that for purposes of std::randomize() calls. If you specify an XMR argument in a std::randomize() call.

You can refer to XMR variables directly or by specifying the full hierarchical name.randomize with { a. int x = 10. pkg::varxmr2 == 4.b == 5. arrays.XMR Support in Constraints You can use XMRs in class constraints and inlined constraints. class cls1. VCS supports all types of XMRs: • • • • • • class XMRs package XMRs interface XMRs module XMRs static variable XMRs any combination of the above Syntax constraint general { varxmr1 == 3. enums. } Examples Here is an example of a module XMR: // xmr from module module mod1. including scalars. where appropriate. } c. and class objects. You can use XMRs for all data types. “Constraints Features” 141 . rand int i1 [3:0].

}. static rand STRENGTH stren.STRONG} STRENGTH. class C. end endmodule Functional Clarifications XMR resolution in constraints (that is. end endmodule Here is an example of a package XMR: package pkg. initial begin inst. endclass pkg::C inst = new.randomize() with {pkg::C::stren == STRONG. typedef enum {WEAK. constraint constr { foreach(i1[a]) i1[a] == mod1.}. choosing to which variable VCS binds an XMR variable) is consistent with XMR resolution in procedural SystemVerilog code.x. } endclass cls1 c1 = new(). initial begin c1. VCS first tries to resolve an XMR “Constraints Features” 142 . $display("%d". endpackage module test. import pkg::*. pkg::C::stren).randomize() with {i2 == mod1.x + 5.rand int i2.

“Constraints Features” 143 .reference in the local scope. VCS errors out and prints an error message. If you specify an XMR variable that cannot be resolved in any parent scopes of the constraint/scope where it is used. and so on. until it finds the variable. If the variable is not found in the local scope. VCS searches for it in the immediate upper enclosing scope.

Constraint Debugging and Profiling VCS can generate constraint profiling reports and hierarchical constraint debugger reports during the simulation run. invoke an HMTL browser on the cstr_html/profile. To run your simulation with constraint profiling on.xml file. These features are explained in the following sections: • • “Using Constraint Profiling” on page 144 “Using the Hierarchical Constraint Debugger Report” on page 147 Note: You can use both of these reporting features at once. Using Constraint Profiling You can use VCS constraint profiling reports to find out how much runtime and memory is spent on each randomize call in your testbench. use the following runtime switch: % . For example: % firefox $cwd/cstr_html/profile. Just add the appropriate switches to your simulation run command line./simv +NTB_CSTR_DEBUG_PROFILE=1 After the simulation completes.xml “Constraints Features” 144 . Profiling reports also show cumulative statistics and allow you to cross-probe into the hierarchical constraint debugger reports.

Note that this illustration shows just the top of the report. including randomize calls that are consuming the most time and memory. you can click the randomize call identifier or the partition identifier to cross-probe to its corresponding constraint hierarchical debug (trace) section. When you use +ntb_solver_model=1. the more memory used). From the report.Figure 8-1 on page 146 shows some sample profiler results. the majority of memory blowup cases are due to binary decision diagram (BDD) blowup. The profiler report also shows the node count of the largest partitions (the more nodes. “Constraints Features” 145 .

Figure 8-1 VCS Constraint Profiling Example “Constraints Features” 146 .

xml Figure 8-2 on page 148 shows some sample hierarchical trace debugger results. For example: % firefox $cwd/cstr_html/trace./simv +NTB_ENABLE_XML_SOLVER_TRACE=1 After the simulation completes.Using the Hierarchical Constraint Debugger Report VCS can also generate a hierarchical constraint debugging report after your simulation run completes. “Constraints Features” 147 .xml file. invoke an HMTL browser on the cstr_html/trace. add the following runtime switch: % . Note that this illustration shows just the top of the report. Note: VCS uses SystemVerilog syntax instead of OpenVera syntax when printing constraints in the trace. To run your simulation with hierarchical constraint debugging on.

randomize()call. For each obj. Click a specific item to make it expand.Figure 8-2 VCS Hierarchical Constraint Debugger Report When you first bring up the HTML randomizer report. “Constraints Features” 148 . all the items are collapsed. VCS prints the: • File name and line number in your SystemVerilog or OpenVera source code where that randomize() call is made.

• Visit count. and different colors for those that are turned OFF. • • • Color Coding Constraint Blocks and rand vars In the randomize reports. and so on. each randomize() call has a number of constraint blocks and variables (rand vars and state vars). Figure 8-3 Constraint Debugging Report solving following set of constraints rand_mode = ON rand_mode = ON rand_mode = ON (from this) (constraint_mode = ON) Solver failed when rand integer y. For example.sv:20@1. a randomize() call inside a for loop has test. test. The default printing mode only displays the failure subset instead of both (see Figure 8-3). Runtime and memory usage for each partition. // constraint c // “Constraints Features” 149 . Avoiding Duplicate Printing of Original Constraint Set VCS does not print the original set of constraints twice when the constraint debugger or solver_trace=2 are turned ON. // rand integer z. This visit count is also referenced in the profiling tables (see Figure 8-1 on page 146). File name and line number for each variable to point to the place where it is defined. incremented each time the same randomize() call occurs. // rand integer x. File name and line number of the class where each variable is defined. and for each full randomize call. VCS uses color coding to identify constraint blocks and rand vars that are turned ON.sv:20@2.

3 runtime option as follows: • • • • 0: Print a one-line failure message with no details. This is useful when the solver fails to determine the minimum subset. in { 3 .{ ( ( } x x < 1 ) . When performing diagnostics. “Constraints Features” 150 . 5 . Use the constraint solver diagnostics feature to analyze solver performance or when a simulation timeout occurs at a randomize() call. Other sections contain detailed explanations of the diagnostic messages and coding recommendations for the reported constraints. Also included is an overview of the constraint solver that provides insights into the underlying performance issues with certain constraint expressions. 2: Print the entire constraint problem and failure subset. 1: Print only the failure subset (this is the default). 7 : 11 } ) . Debugging Constraint Solver Diagnostics This section explains how to use the VCS constraint solver diagnostic feature to debug testbench constraints.1. the solver has two modes: reactive and proactive. You can use the +ntb_enable_solver_trace_on_failure=0. 3: Print only the failure problem.2.

Messages that indicate the source of constraint issues. This behavior prevents implicit “Constraints Features” 151 . When used in the proactive mode. The diagnostic report displays: • • Specific constraints that contributed to the timeout or simulation halt. VCS issues diagnostic messages for actual constraints applied to a specific randomize() call. By default. The constraint solver diagnostics feature analyzes a specific set of constraint expressions that are known to have performance impacts. the constraint solver diagnostics are based on a pre-solve analysis. The solver issues an error message when no combination of random values satisfies the specified constraints. Solver Overview The VCS constraint solver can solve a wide spectrum of difficult problems such as algebraic factoring. the constraint solver treats all constraint expression operators bidirectionally and solves for all random variables and constraints simultaneously. The diagnostic report displays constraints that could cause performance issues. Based on the diagnostic information in the report. and mixed integer and register expressions.In reactive mode. This problem can be caused by over-constraining the random variables. complex Boolean expressions. you can modify the constraints to prevent potential performance issues or timeouts when randomize() is called. This set of expressions is documented in the section “Classes of Constraint Diagnostics” on page 159.

This results in improved solver performance overall. However.. the solver does not over-constrain random variables or create spurious failures. The bidirectional nature of constraints and the simultaneous solving of all random variables and constraints increases the complexity of problems handled by the solver. Control variables are random variables that allow solutions for other random variables regardless of the values assigned to them. Example 8-1 Unidirectional Constraint class C. Use unidirectional constraints to create separate partitions for control variables.partitioning of constraints by the solver. You can reduce the complexity by using the unidirectional constraint feature to explicitly partition random variables in constraints. in a CPU instruction sequence generator. The solver then solves the random variables in the order determined by the partitions. For example. which impacts the solver performance. the opcode can be used as a control variable. as shown in Example 8-1. The solver takes the partition information and breaks down a single complex problem into a sequence of simpler problems. you can use unidirectional constraints to improve performance. if you run into performance issues. This is the recommended best practice. As a result. a common problem in other industry solvers. “Constraints Features” 152 . rand integer x. Methodology for Using Unidirectional Constraints The default solver behavior does not impose implicit partitioning.

you can use the $void() function: foreach (c [i]) { if ($void(opcode) == T1) { c[i]. rand trans opcode. “Constraints Features” 153 . T2 } trans. } } or use the solve-before-hard directive: foreach (c [i]) { if (opcode == T1) { c[i]. } endclass: C class D. To do this. } } } endclass: D In Example 8-1.x == 2. opcode is a control variable you can solve for first to break the solver problem into smaller subsets. } else if (opcode == T2) { c[i].x == 1. rand C c[$]. } else if (opcode == T2) { c[i]. typedef enum { T1. constraint d1 { foreach (c [i]) { if (opcode == T1) { c[i]. } else if (opcode == T2) { c[i].x == 1.x == 2.x == 1.x == 2.constraint c1 { x > 0.

the solution space is limited to the 16 values specified by the inside constraint. This set of values (the solution space). For example. the initial search space of an unsigned 32-bit variable is: {0 . For example. However. is determined by the constraints on the random variables. consider Example 8-2. To see how this works. the range of possible values (the search space) is represented by a {low.} solve opcode before c[i].x hard. Here. the initial search space for varA has 232 values. The initial search space of a random variable is equal to all possible values of the data type. the set of values that actually meets the constraints you specify is typically much smaller than the search space. the initial search space for a partition with five unsigned 32-bit variables is: (232)5 = 2160 However. high} pair. “Constraints Features” 154 . Constraint Solver Search Space and Solution Space For each random variable in a constraint network.232-1} The initial search space of a partition is the composite range that all random variables of the partition can fall into. } If the control variable partitions do not result in sufficiently improved solver performance. create additional partitions for the non-control variables.

constraint varA_range { varA inside {[0:15]}.Example 8-2 Search Space Reduced by “in” Constraint class B. This ensures that if a valid solution exists. In the second phase. The process of selecting a valid solution involves two phases: search space reduction and random assignment. } endclass: B Search Space Reduction And Random Assignment The goal of the constraint solver is to assign randomly selected values to random variables. rand bit[31:0] varA. while not removing any element of the solution space from the search space. the solver algorithm assigns a randomly picked value from the search space to a random variable and performs implication. the solver narrows down the search space to match the solution space as closely as possible. Implication is the process of simulating the constraint network using the value assigned to a random variable to check that no constraint is violated. it is reached without being prematurely eliminated from consideration. while ensuring that the values satisfy the constraints on those variables. “Constraints Features” 155 . In the first phase.

You use the value argument to specify the desired diagnostic mode. Verbose Mode—The diagnostic report always displays the search space of variables to be randomized in the current partition. inconsistent constraints or dependency loops). This option enables display for the entire simulation. • Non-verbose Mode—The diagnostic report displays the search space of variables to be randomized in the current partition only if at least one diagnostic message is reported. Choosing a Display Mode There are two display modes for the diagnostic report: non-verbose and verbose. “Constraints Features” 156 . even if no diagnostic message is reported. The diagnostic report does not provide information related to constraint solver failures (for example.Using the Constraint Solver Diagnostics You can use the constraint solver diagnostic feature to troubleshoot solver performance issues. ntb_enable_solver_diagnostics The +ntb_enable_solver_diagnostics=value option enables the constraint solver diagnostics. • Enabling Diagnostics You enable the constraint solver diagnostic feature using a set of runtime options or by passing a macro argument to randomize() on a per-call basis.

Syntax +ntb_enable_solver_diagnostics=value where value can be: • • 0 — Constraint solver diagnostics is off (this is the default) 1 — Reactive. • 4 — Proactive. “Constraints Features” 157 . • 3 — Reactive. verbose mode Select this mode if you want verbose information in proactive mode. It is a good idea to run a short simulation with few randomize() calls when using this feature. non-verbose mode Select this mode if constraints are solved successfully but the solver performance is unacceptable. • 2 — Proactive. non-verbose mode Select this mode if complex constraints exist and you want to check for expressions that have potential performance impact. ntb_enable_solver_diagnostics_on_failure The +ntb_enable_solver_diagnostics_on_failure option enables the constraint solver diagnostics and reports diagnostic information only when the solver times out. verbose mode Select this mode if you want verbose information in reactive mode. Note: Solver diagnostic output is verbose.

Use the +ntb_solver_diagnostics_filename option to specify a file for storing the diagnostic information.Syntax +ntb_enable_solver_diagnostics_on_failure=value where value can be: • • 0 — Constraint solver diagnostics is off (this is the default) 1 — Reactive. • 2 — Reactive. non-verbose mode) except in the printing of the diagnostic information. non-verbose mode Diagnostic behavior is the same as the +ntb_enable_solver_diagnostics=1 option (reactive. verbose mode Diagnostic behavior is the same as the +ntb_enable_solver_diagnostics=3 option (reactive. verbose mode) except in the printing of the diagnostic information. Syntax +ntb_solver_diagnostics_filename=filename “Constraints Features” 158 . Printing of diagnostic information starts only when a solver timeout occurs. Saving Diagnostic Reports ntb_solver_diagnostics_filename By default. Printing of diagnostic information starts only when a solver timeout occurs. VCS displays diagnostic information on standard I/O.

the corresponding diagnostic messages.In the report. the diagnostic information reported for each constraint is organized and displayed in the following four sections: • • • • Diagnostic message Variables (random and non-random) involved in the reported constraint Reported constraint Search space for random variables involved in the current partition Classes of Constraint Diagnostics The constraint solver diagnostics target a set of specific constraint expressions that are known to have performance impacts. Each of these constraint expressions. • • • “Operator that Splits Value Ranges Resulting in Sparse Solution Set” on page 160 “Low Probability of a Successful Solution—Factorization of a Constant” on page 161 “Relational Operator On The Result Of A Shift Operation— Behavior of Expression” on page 163 “Constraints Features” 159 . and possible solutions are discussed in the following sections.

rand bit [64:0] base. } *** The search spaces for the random variables are: base: (000000000000000000000000:00000001ffffffffffffffff) *** “Constraints Features” 160 . The probability of finding a solution is very low (1/621). constraint residue { base % 621 == 0. the result of the modulus operation is constrained to a singleton value.Operator that Splits Value Ranges Resulting in Sparse Solution Set In Example 8-3. Example 8-3 Operator Splits Value Ranges class modulus. This causes a solver timeout. and the size of the resulting range is small {{0:0}}. The divisor is large (621). } endclass: modulus Diagnostics Report MSG 3: There is a low probability of a successful assignment based on the existing values of the operand. // rand_mode = ON constraint residue // (from this) (constraint_mode = ON) { ( ( base % 621 ) == 0 ) . rand bit[64:0] base.

//solve varA before varC. Consider this next example (Example 8-5). the solver may not be able to find values for varA and varB such that varA*varB is in the range of the RHSExp. if the range of possible values of the RHSExp is small. } endclass: B Low Probability of a Successful Solution—Factorization of a Constant For constraint expressions in the form varA*varB == RHSExp. “Constraints Features” 161 .Changing the Size of a Divisor In Example 8-4. rand bit [32:0] varA. Example 8-5 Factorization of a Constants class A. constraint residue { base % 621 == res. constraint factorization { varA * varB == varC. Example 8-4 Changing Size of Divisor class B. rand bit [3:0] res. varA > varB. either decrease the size of the divisor or expand the options in the RHS to increase the probability of finding a solution. rand bit [64:0] base. varC. varB. This can happen when VCS solves for random variables in the RHSExp before it solves for the random variables in the multiplication operator. or if the RHSExp is a constant.

// rand_mode = ON rand bit[32:0] varC. the constraint solver solves the two operands of the multiplier (varA and varB) before varC. } *** The search spaces for the random variables are: varA: (0000000000000001:00000001ffffffff) varB: (0000000000000000:00000001fffffffe) varC: (0000000000000000:00000001ffffffff) *** Specifying Solve Order for Random Variables In Example 8-6. “Constraints Features” 162 . Diagnostic Report MSG 14: The expression with the multi-node causes problems. In this case if you add the solve-before constraints. // rand_mode = ON constraint base_and_limit // (from this) (constraint_mode = ON) { ( ( varA * varB ) == varC ) . varB. In the absence of the solve-before constraints. // rand_mode = ON rand bit[32:0] varB. varC. rand bit [32:0] varA. } endclass: A In. this situation causes a solver timeout. if varC is solved first. the probability of finding a solution for the constraint varA*varB == varC is exceedingly low.//solve varB before varC. Example 8-5. Example 8-6 Specifying Solving Order for Random Variables class B. the probability of finding a solution that satisfies the constraint varA*varB == varC is low. rand bit[32:0] varA.

==) forces a very specific value for the result of the shift operation. } “Constraints Features” 163 . ((window_shift+window_size) < 30). solve varA. } endclass: B In Example 8-6. the solve-before directive specifies that the varA and varB multipliers be solved before the random variable on the RHS.window_shift before mask. //solve window_size. varB before varC. In this case. Consider this next example (Example 8-7). rand bit [28:0] mask. the probability of finding a solution increases. Example 8-7 Relational Operator on Shift Operation Result rand integer window_size. window_shift. the probability of finding a solution is extremely low and results in a solver timeout.constraint factorization { varA * varB == varC. varA > varB. (window_shift > 4). varC. mask == (((1<<window_size)-1) << window_shift). WIth this change. constraint use_window_params { (window_size > 0). <<) that fans out to a relational operator (for example. Relational Operator On The Result Of A Shift Operation—Behavior of Expression A shift operation (for example.

the probability of finding a solution is 23/229 (almost zero). window_shift. } Using the solve-before Directive In Example 8-8. Example 8-8 Using solve-before Directive class B. solve window_size. if mask is solved first and results in a single digit set to 1. // rand_mode = ON rand integer window_shift. mask == (((1<<window_size)-1) << window_shift). rand bit [28:0] mask. the probability of finding a solution that satisfies the constraints is extremely low. window_shift before mask. constraint use_window_params { (window_size > 0). Diagnostics Report MSG 19: The shift node fans out arithmetic/relational operators which may have a low probability of success. ((window_shift+window_size) < 30). } endclass: B “Constraints Features” 164 .1)<< window_shift)). (window_shift > 4). // rand_mode = ON rand integer window_size. If a random selection for the mask value results in only one digit set to 1. // rand_mode = ON constraint use_window_params // (from this)(constraint_mode = ON) { (mask == (((1 << window_size).In Example 8-7. rand bit[28:0] mask. rand integer window_size. the last constraint combines random shift operations to match a random mask.

“Constraints Features” 165 . This ensures that the value of mask is calculated rather than randomly assigned.In Example 8-8. the solve-before directive specifies that the shift amount be solved before the mask.

“Constraints Features” 166 .

9 Parallel VCS Parallel VCS (PVCS) takes advantage of the computing power of multiple processors in one machine to improve simulation turnaround time Use the following Parallel VCS options in a simulation: • • • • • Design profiling and simulation Assertion profiling and simulation Toggle coverage Parallel functional coverage VPD dumping 1 Parallel VCS 165 .

profile Enables design and assertion level profiling. profile_value Enables value-based design level profiling. Note: this option is available at compiletime only. sva[=NCONS] Enables Parallel SVA and with NCONS specifying the number of parallel SVA consumers.. The syntax is: vcs -parallel [+options | +option[_only] [-o PVCS_executable_name] [+option(s)] design=FILENAME Enables all parallel VCS options and specifies the name of the partition configuration file. fc[=NCONS] Enables Parallel Functional Coverage and with NCONS specifying the number of PFC consumers. Parallel VCS 166 . tgl[=NCONS] Enables Parallel Toggle Coverage and specifies the number of parallel toggle coverage consumers. show_features Shows enabled PVCS features. vpd[=NCONS] Enables Parallel VCD+ Dumping and specifies the number of parallel VCD+ consumers.Parallel VCS Options You use the VCS -parallel option to invoke parallel compilation.

PVCS-specific data is stored in a directory executable_name. The default path name is simv. See “Profiling a Serial Simulation” on page 9-175. Run the VCS profiler during simulation. Use Model for Design Profiling and Simulation The use model for PVCS is as follows: 1. The VCS profiler tells you the subhierarchies in your design that use the most CPU time. to enable the design and vpd options enter: vcs -parallel+design_only=FILENAME+vpd [-o PVCS_executable_name] Using the VCS -o option to specify the simulation executable binary filename allows work on multiple simultaneous PVCS compiles and runs.pdaidir. _only must immediately follow the -parallel VCS option. 2. Parallel VCS 167 . See “Specifying Partitions” on page 9-176.vpd_sidebuf=MULT Sets the size of PVPD side buffer to MULT times the size of the main buffer. Compile and simulate your design using the conventional serial mode (compiling and simulating the design on one processor). It can be used with any PVCS option and any other PVCS options can follow _only. For example.pdaidir. Specify the partitions in the PVCS configuration file. _only Conserves processor resources by enabling only the processing of the PVCS option specified.

After making the changes called for by the results. See “Profiling a Parallel Simulation” on page 9-177. You can optionally specify the number of consumers for each. 8. Use Model for Toggle and Functional Coverage 1. run parallel compilation and simulation over again. See “Design Simulation” on page 9-169. 6. Run parallel compilation specifying the sva option. 2. Use Model for Assertion Simulation 1. Run the PVCS profiler. Run parallel simulation again and this time collect data for the PVCS profiler. See “Examining the PVCS Profiler Results” on page 9-179. If you wish to increase the performance gains from PVCS. 4. 7. Run parallel simulation. and/or the PVCS fc option for functional coverage.. These results could call for you to reorganize you partitions or your Verilog source code. Run parallel simulation. Parallel VCS 168 . specifying the PVCS configuration file. Run the simulation to generate coverage results. 2. Run parallel compilation. Run parallel compilation specifying the PVCS tgl option and coverage metric options for toggle coverage. Examine the PVCS profiler results. additional steps follow: 5.3. See “Design Simulation” on page 9-169.

3. Parallel VCS 169 . Run parallel compilation specifying the vpd option. Generate coverage result reports. 2. Run the simulation to generate the VPD file. Use Model for VPD Dumping 1. you can simulate only the design or simulate the design with other PVCS options. Running Parallel Simulation Parallel VCS (PVCS) takes advantage of the computing power of multiple processors to improve simulation turnaround time You can generate results for one of all the following Parallel VCS options in a simulation: • • • • • Design simulation Assertion simulation Toggle coverage Functional coverage VPD file generation Design Simulation Once you have profiled your design and created a partition configuration file as described in the previous chapter.

1. Compile using the PVCS -parallel option and other PVCS and VCS options.
vcs filename(s).v -parallel+(design | design_only)=partition_filename.cfg parallel_vcs_options vcs_options

2. Run the simulation with VCS and PVCS run-time options.
simv

Assertion Simulation
You can process only assertion level results or assertion level results along with other PVCS options. 1. Compile using the PVCS -parallel option, the assertion compilation option or options, and other PVCS and VCS options.
vcs filename(s).v -parallel+[sva[=NCONS]] [-ntb_opts] [ parallel_vcs_options vcs_options

2. Run the simulation with VCS and PVCS run-time options.
simv

Toggle Coverage
Generate results for only toggle coverage or toggle coverage along with other results by compiling the design with PVCS options and VCS coverage metrics options. You can use the +count option to report total executed transactions. After generating coverage results, you can examine them using the Unified Report Generator. tgl[+count] Report total executed transactions.
Parallel VCS 170

1. Compile using the PVCS -parallel option, coverage option or options, and other PVCS and VCS options.
vcs filename(s).v -parallel+tgl[=NCONS] -cm tgl [parallel_vcs_options] [vcs_options]

2. Run the simulation to generate coverage results.
simv -cm tgl [vcs_options]

3. Generate coverage result reports:
urg -dir coverage_directory.cm urg_options

Example In this example, toggle coverage results only are generated and the URG report is produced in the default HTML format.
% vcs -cm_tgl mda -q -cm_dir pragmaTest1.cm -cm tgl -sverilog -parallel+tgl=2 pragmaTest1.v % simv -cm tgl % vcs -cm_pp -cm_dir pragmaTest1.cm % urg -dir pragmaTest1.cm

Parallel VCS 171

Results can then be examined in your default browser.

Functional Coverage
Generate results for only functional coverage or functional coverage along with other results by compiling the design with PVCS options and VCS coverage metrics options. After generating coverage results, you can examine them using the Unified Report Generator. 1. Compile using the PVCS -parallel option, coverage option or options, and other PVCS and VCS options.
vcs filename(s).v -sverilog -parallel+fc[=NCONS] [parallel_vcs_options] [vcs_options]

2. Run the simulation to generate coverage results.
simv

3. Generate coverage result reports:

Parallel VCS 172

urg -dir coverage_directory.cm urg_options

Example In this example, functional coverage results only are generated and the URG report is produced in the default HTML format.
% % % % % vcs iemIntf.v -ntb_opts dtm -sverilog -parallel+fc=2 simv -covg_cont_on_error $urg -dir simv.vdb cat urgReport/gr*

Results can then be examined in your default browser.

VPD File
You can enable Parallel VCD+ Dumping and specify the number of parallel VCD+ consumers using the PVCS vpd option.

Parallel VCS 173

1. Compile using the PVCS -parallel option with the vpd[=NCONS] option, and other PVCS and VCS options.
vcs filename(s).v -debug_pp -parallel+vpd[=NCONS] [parallel_vcs_options] [vcs_options]

2. Run the simulation.
simv

You can post-process the results with the generated +vcd database. Example In this example, a VCD+ file with three specified consumers is generated.
% vcs -debug_pp -parallel+vpd=3 design.v % simv

Profiling a Simulation
You can profile your PVCS simulation to ensure efficient use of resources. This chapters details the profiling process. It contains the following sections: • • • • Profiling a Serial Simulation Specifying Partitions Profiling a Parallel Simulation Running PVCS Examples

Parallel VCS 174

Profiling a Serial Simulation
You can profile your simulation to determine if it is a good candidate for parallel simulation and identify partitions to use. You do this by telling VCS to run its profiler during simulation with the +prof compile-time option.
vcs +prof filename(s)

The VCS profiler tells you, among other things, what module instances use the most CPU time. The CPU time percentages are for the instance and all instances hierarchically under the instance. The CPU time percentage thus represents the subhierarchy in which the instance is the top-level instance. The VCS profiler writes its profile information in the vcs.prof file in the current directory. Look at the INSTANCE VIEW section in this file. This section, or view, tells you the percentage of CPU time used by each subhierarchy. Figure 9-1 shows this view. Figure 9-1 Instance View in a vcs.prof File

========================================================== INSTANCE VIEW ========================================================== Instance %Totaltime top (1) 100 top.A1 (2) 30 top.A2 (3) 30 top.A3 (4) 30 ----------------------------------------------------------

The subhierarchies that use the most CPU time are good candidates for PVCS partitions. In Figure 9-1 you would use separate partitions for the subhierarchies.

Parallel VCS 175

Specifying Partitions
The -design option requires a partition configuration file. You specify the partitions in the PVCS configuration file using the following syntax:
partition {hierarchical_name(module_identifier),...} ; partition {hierarchical_name(module_identifier),...} ; partition {hierarchical_name(module_identifier),...} ; . . .

The syntax is as follows:
partition

The keyword that specifies that what follows are the contents of one partition.
hierarchical_name

The hierarchical name of a Verilog module instance that is the top-level instance of the subhierarchy that you want to simulate as a partition.
module_identifier

The name of the module definition that corresponds to the toplevel instance. All parts of the design not covered in any of the specified partitions together form an implicitly defined master partition. The userspecified partitions are called slave partitions. Example 9-1 PVCS Configuration File

In this example, there is a separate line for each partition. Each hierarchical name for a top-level module instance must be followed by its module name in parentheses. You can specify more than one subhierarchy in a partition.
Parallel VCS 176

// two instances per partition partition { top. Its syntax is as follows: Parallel VCS 177 .bus2 (MyBus) } /* one instance per partition */ Profiling a Parallel Simulation Run the simulation by entering a command line with the name of the master executable (by default named simv) and runtime options.partition {top. top. partition {top.bus1 (MyBus). partition { top.A3(A3)}. partition {top.A1(A1)}. blanks. see the VCS User Guide. Parallel VCS wrote the data files that the PVCS profiler needs to report on the parallel simulation.cpu (CPU) }. You start the PVCS profiler with the pvcsProfiler command. Example 9-2 A Free Format Configuration File You can also enter a free format of the specifications in a configuration file entering new lines. and comments. For more information on creating configuration files.A2(A2)}. The syntax for this command line is as follows: simv -parallel+profile [VCS_runtime_options] Parallel Profiling Options If you entered the profile option on the simv command line. Note: You can use the Verilog comment syntax to comment your partition file.

the profiler does not make this calculation. The default path name is simv. The default height is 250. doTimeProfiling=1|0 Calculate the time accumulation and produce the graphs. doToggleProfiling=0|1 Calculate the partition port toggle counts and produce the high count listing.If the argument is 0. graphTnHeight=integer Height of the thumbnails size graphs in pixels.pdaidir. The default height is 1000. the profiler does not make this calculation or produce the graphs. If the argument is 0.pdaidir. The directory is the name you specified for the simulation executable binary file with the extenstion . graphImWidth=integer Width of the full size graphs in pixels. Use profileDumpDir to specify the directory containing the dump files that the profiler reads. The default argument is 1. By default the profiler creates the ppResults_0 directory and writes these files in this directory. Parallel VCS 178 . The default argument is 1.pvcsProfiler [profileDumpDir=simvName.pdaidir] [doTimeProfiling=1|0] [doToggleProfiling=0|1] [graphImHeight=integer] [graphImWidth=integer] [graphTnHeight=integer] [graphTnWidth=integer] [lowerSimTimeBound=float] [runVersion=string] [toggleCutOff=float] [upperSimTimeBound=float] [-help] These arguments and properties are as follows: profileDumpDir=simvName. The default width is 1000.pdaidir The PVCS profiler writes HTML files that display profile information about the master and slave simulations. graphImHeight=integer Height of the full size graphs in pixels.

If you want a different name for this directory. toggleCutOff=float Specifies that the port toggle count cutoff for a partition is equal to this percentage of highest toggle count. The following is an example of a results. -help Displays the valid properties and their definitions.0. upperSimTimeBound=float A floating point number for the simulation time when profiling stops. The default argument is 0. With this property the profiler creates the ppResultsstring directory.html file (as viewed in a regular web browser): Parallel VCS 179 . Examining the PVCS Profiler Results The main results file that the profiler writes is named results. By default it writes it in a directory named ppResults_0 in the current directory.html. runVersion=string By default the profiler creates the ppResults_0 directory in the current directory and writes its output HTML files in this directory. lowerSimTimeBound=float A floating point number for the simulation time when profiling starts.0. The default width is 250. The default argument is 1e+100. The default argument is 1. enter this property.graphTnWidth=integer Width of the thumbnails size graphs in pixels.

html file contains four graphs: • • • • The Processor Segment Totals (graph1.html) The Active PVCS Features (graph4.html File Click here to see how to read the graphs Click on a graph to see a larger image of the graph The results. Parallel VCS 180 .Figure 9-1 results.html is a hypertext link to an HTML file with a larger image of the graph.html) The S1 Balance Distribution (graph3.html) Each image in results.html) The Processor Delta Time Totals (graph2.

Examples of Good Parallelism This Processor Segment Totals graph shows that each partition is doing the same amount of work. showing a balanced design with a good deal of parallelism.html file that explains how to interpret the graphs. The first three graphs are from a design where the profiler results are good. Figure 9-2 A Good Processor Segment Totals Graph Parallel VCS 181 .There is a link to the howtoInterpretGraphs. The following are a series of examples of these graphs that show different results from the PVCS profiler.

indicating good parallelism. which is good. Figure 9-3 A Good Processor Delta Time Totals Graph In Figure 9-4 the bars are all to the right.A delta is a set of events in one or more partitions that cause subsequent simulation events in other partitions. Delta d0. in which the design generated the clock signal. where each partition did its work in the same delta. Parallel VCS 182 . Figure 9-3 shows only two deltas. and d1.

are doing a significant amount of waiting for events in other partitions. as indicated by the dark color at the top of their bars. Parallel VCS 183 . Some partitions.Figure 9-4 A Good S1 Balance Distribution Graph Examples of Uneven or Bad Parallelism The next three graphs are from a design in which the amount of work done by the partitions is uneven or unbalanced. Figure 9-5 shows that the partitions are not doing the same amount of work.

Parallel VCS 184 . but also indicates that the partitions are doing different amounts of work.Figure 9-5 An Uneven Processor Segment Totals Graph Figure 9-6 shows a small number of deltas. which is good.

Figure 9-6 An Uneven Processor Delta Time Totals Graph Figure 9-7 shows that the bars are more to the left. indicating less parallelism. Parallel VCS 185 .

Figure 9-7 An Uneven S1 Balance Distribution Example of a Design in Need of Clock Signal Analysis The next four graphs are from a design in need of the clock signal optimization. causing each partition to wait for events in the other partitions. Clock signal values propagate from the output of one partition to the input of another. Parallel VCS 186 .

Figure 9-8 Clock Signals Processor Segment Totals Graph Figure 9-9 shows Partition A3 has a #1 delay before its activity Parallel VCS 187 . but they are spending much of their time waiting for events in other partitions.Figure 9-8 Shows that the partitions are doing the same amount of work.

Parallel VCS 188 .Figure 9-9 Clock Signal Processor Delta Time Totals Graph Figure 9-10 show workloads are balanced. but partition A3 does not execute in parallel with A1 and A2.

Figure 9-11 Shows that the partitions are doing the same amount of work. Workloads are balanced. Parallel VCS 189 . This example is slower than a serial run. but they are spending most of their time waiting for events in other partitions.Figure 9-10 Clock Signal S1 Balance Distribution Examples of Worst Case Scenario The next four graphs are from a design in which the partitions get their clocks together. but the partitions do now execute in parallel.

Figure 9-11 Clock Signals Processor Segment Totals Graph Figure 9-12 shows that all the work for each partition is done in a different delta. Parallel VCS 190 .

indicating that there is no parallelism in the design.Figure 9-12 Clock Signal Processor Delta Time Totals Graph Figure 9-13 shows the bars completely to the left. Parallel VCS 191 .

The tests include: • • A serial run A parallel run Parallel VCS 192 .Figure 9-13 Clock Signal S1 Balance Distribution Running PVCS Examples Included in your installation is a design example and suite of scripts that allow you to perform serial / parallel performance comparisons on your system and profile the results.

csh . Examine DATE. 1. Serial Run Time The serial run example allows you to view wallclock time for comparison with the parallel run. Examine DATE.A run with a delay in a partition causing one partition not to run in parallel with the other two partitions . Tue Oct 10 10:13:11 PDT 2006 Parallel VCS 193 . Run the script run_balanced. Tue Oct 10 09:59:22 PDT 2006 Tue Oct 10 10:00:45 PDT 2006 Parallel Run Time The balanced parallel run example allows you to view wallclock time for comparison with the serial run.csh .serial for the wallclock time taken for serial simulation as shown below. 2. 2.parallel for the wallclock time taken for parallel simulation as shown below. Run the script run_serial.A run in which a clock is passed from partition to partition causing non-parallel execution Please contact VCS Support if you are looking for these examples.A balanced workload parallel run .• Profiler runs . 1.An unbalanced workload parallel run .

2.A3 (1) (2) (3) (4) 100 30 30 30 ---------------------------------------------------------- Parallel Runs +define+BALANCED This example is the best-case scenario. Figure 9-14 Instance View from a Serial Run ========================================================== INSTANCE VIEW ========================================================== Instance %Totaltime top top. Examine the INSTANCE VIEW section in vcs.prof to see that instances top. Parallel VCS 194 . 1. Run the script run_balanced_prof. Examine the output in the ppResults_balanced directory by opening the file results.Tue Oct 10 10:13:42 PDT 2006 Profiler Runs Serial Run to Identify Partitions This is example of a serial run used to identify partitions.A1. top. as shown in Figure 9-14.csh .csh .A1 top. 2.A3 are candidates for partitions.A2 top. 1.html as shown in Figure 9-15. The script for the serial profiler run is run_serial_prof.A2 and top.

d0. where each partition did its work in the same delta and has the same amount of activity.Figure 9-15 Balanced Parallel Run Partitions receive clocks together. To view details. double-click on a graph in your browser to view the results in a full-screen. Workloads of the partitions are balanced and execute in parallel. in which the design generated the clock signal. Partitions have same amount of activity. the Processor Delta Time Totals Graph shows two deltas. On the right. the Processor Segment Totals graph shows that each partition is doing the same amount of work and the partitions receive their clocks together. • • +define+UNBALANCED In this parallel run unbalanced workloads hinder performance. In he center. and d1. In this example: • On the left. Parallel VCS 195 . the Balance distribution graph shows that workloads of the partitions are balanced and execute in parallel.

On the right.1.html as shown in Figure 9-16. the Balance distribution graph shows that partitions execute in parallel. indicating uneven work distribution among the partitions. workloads are unbalanced. the Processor Segment Totals graph shows that the partitions are not doing the same amount of work. but the workloads are unbalanced. the Processor Delta Time Totals Graph. Examine the output is in the ppResults_unbalanced directory by opening the file results. but Partitions have differing amount of activity. Figure 9-16 Unbalanced Parallel Run Partitions get clocks together. Run the script run_unbalanced_prof. The center graph.csh. shows uneven processor delta time. 2. Some partitions are doing a significant amount of waiting for events in other partitions. Partitions run in parallel. • • Parallel VCS 196 . In this example: • The left chart.

1. Figure 9-17 A Delay in a Partition Partitions get clocks together.csh.+define+BALANCED+DELAY This is an example of a delay in a partition causing one partition not to run in parallel with the other two partitions. but partition A3 does not execute in parallel with A1 and A2. In this example: • The left chart. Hence workloads are balanced. Partitions have same amount of activity. 2. Partition A3 has a #1 delay before its activity. the Processor Segment Totals graph shows that each partition is doing the same amount of work but are spends significant amounts of time waiting for events in other partitions. Parallel VCS 197 . Figure 9-17 shows Partition A3 with a #1 delay before its activity. Examine the output is in the ppResults_delay directory by opening the file results. Run the script run_delay_prof.html.

Workloads are balanced. Figure 9-18 shows the example in which Partition A2 gets its clock from A1.A2.• The center graph. and A3 gets its clock from A2. 1. Examine the output is in the ppResults_clock directory by opening the file results. but none of A1. shows the partitions have the same amount of activity. but they execute across two deltas On the right. This is the worst-case scenario.html. and will be slower than the serial run. Parallel VCS 198 . the Processor Delta Time Totals Graph. Run the script run_clock_prof. Figure 9-18 A Clock Passed from Partition to Partition Partitions get clocks together. • +define+BALANCED+CLOCK This is an example of a clock being passed from partition to partition causing non-parallel execution.A3 execute in parallel. Partitions have same amount of activity. but partition A3 does not execute in parallel with A1 and A2. the Balance distribution graph shows that workloads of the partitions are balanced.csh. 2.

SystemVerilog . Current Limitations +race +race is not supported Partial Elab This flow is not supported. Parallel VCS 199 . Solaris 32 bit: Multi-core Multi-proceesor machine. but none of the three partitions execute in parallel. the Processor Delta Time Totals Graph. On the right. but the work for each partition is done in a different delta. • • Supported Platforms • • Linux 32/64bit RH4.In this example: • The left chart. shows the partitions have the same amount of activity. the Balance distribution graph shows that workloads of the partitions are balanced. the Processor Segment Totals graph shows that each partition is doing the same amount of work but are spending most of the time waiting for events in other partitions.0 : Multi-core multi-processor machine. Certain dynamic types are not allowed inside slave partitions.Use of SV data types logic and bit types are allowed. The center graph.

SystemC-C. All VHDL will run in the master partition. VHDL testbench and Verilog gate-level netlist will work very well. and AMS These flows are not supported. Parallel VCS 200 . VMC.VCS-MX • • Only Verilog instances can be added as partitions. For example.

VMM Additions and Enhancements 205 . see the VMM Register Abstraction Layer User Guide and the VMM User Guide.10 VMM Additions and Enhancements 1 New features and functionality in VMM are described in the following sections: • • • VMM RAL C Interface VMM Standard Library Class Additions vmm_ral_block_or_sys Base Class Additions For more information on these features.

registers and memories included in a RAL model can be accessed in C code through a C API. unmodified. The C code is executed natively on the same workstation that is running the SystemVerilog simulation. The other is pure stand-alone C code and is designed to be compiled on the target processor in the final application. The same C code can later be compiled for the target execution processor. VMM Additions and Enhancements 206 . two versions of the RAL C API can be generated. eliminating the need for an instruction set simulator or a RTL model of the processor. As illustrated in Figure 10-1. This allows the firmware and application-level code to be verified against a simulation then used. The fields. One is designed to interface to the RAL model running in the SystemVerilog simulator using the Direct Programming Interface. in the final application.VMM RAL C Interface The RAL C interface allows firmware and application-level code to be developped and debugged on a simulation of the design.

Both use the same interface mechanism. the application software’s main() routine must be replaced by one or more entry points known to the simulation. The RAL model reference is a size_t on the C side The C-side reference is then used by the RAL C API to access required fields. it is necessary for the C code to be called by the simulation to be executed. typically in the same file that defines the verification environment. VMM Additions and Enhancements 207 . The arguments must require at least one instance of a block or system base address. as shown in Example 10-1. To that end. registers or memories. They only differ in their intent and timing of the invocation.Figure 10-1 RAL-Generated APIs Firmware or Application Code C + SV ralgen C SV Simulator RALF file Synthesis C Compiler RTL H/W Entry Point When executing the C code within a simulation. There are two kinds of entry points: application entry points and service entry points. Entry points must be declared in the $unit scope. All entry points must take at least one argument that will receive the base address of the RAL model to be used by the C code. as specified in Appendix C.

as shown in Example 10-3... as shown in Example 10-2. } Application Entry Point An application entry point is invoked only once. If a simulation contains more than one "application" or if the application software is fragmented into different functions. the entry point should be invoked as the implementation of the cfg_dut() method.sv" import "DPI-C" context task C_func_name(int blk). It replaces the application’s main() routine that would normally be automatically invoked by the host operating system. The entry point must correspond to a void C function with a corresponding size_t argument for the base address of the toplevel block or system. Example 10-2 Entry point declaration in C. An application entry point should be invoked by the testcase or verification environment at a point where the simulated design is ready to be used by the application software. If the application software includes (or is) the device configuration firmware. If the application software VMM Additions and Enhancements 208 . An application entry point may or may not complete and return control of the execution thread back to the SystemVerilog side. at the beginning of the simulation. the entry point for each application or application fragment may be called by the simulation or internally by a top-level entry point.Example 10-1 Entry point declaration ‘include "vmm-ral. corresponding to Example 10-1 void C_func_name(size_t blk) { .

. Example 10-3 Invoking application containing configuration firmware import "DPI-C" context task appsw(vmm_ral_block blk). program test.requires a fully functional and configured model of the design..run(). class my_env extends vmm_env. join_none env.. tb_env env = new. super.cfg_dut(). virtual task cfg_dut(). endclass Example 10-4 Application requiring pre-configured simulation import "DPI-C" context task appsw(vmm_ral_sys sys).C_addr_of()). Note how each entry point invocation is forked to allow for an application software that never completes.ral_model. join_none endtask . its entry point should be invoked after the environment has been started... fork appsw(this. fork appsw(env. as shown in Example 10-4.start(). initial begin env. end endprogram VMM Additions and Enhancements 209 .ral_model.C_addr_of()).

fork forever begin wait (tb_top.int signal is asserted. Example 10-5 Invoking application containing configuration firmware import "DPI-C" context task isr(vmm_ral_sys sys). as illustrated in Example 10-5. endclass Execution Timeline When executing with a simulation of the design. .Service Entry Point A service entry point is invoked multiple times. Notice how its invocation is embedded in a forever loop to ensure that interrupts will be serviced whenver the tb_top. It is unlike the real application code running as object code on a real processor. whenever a condition requiring software servicing is detected..ral_model). end join_none endtask . isr(this. super. at which point it may be invoked again.. class my_env extends vmm_env... a service entry point always returns. VMM Additions and Enhancements 210 . A typical service entry point is the invocation of the interrupt service code in the application software.start(). all C code executes atomically.int === 1’b1). Unlike an application entry point. virtual task start(). where the execution of the code happens concurrently with other processing in the neighboring hardware.

If an interrupt-driven strategy is used. that is not an issue as this can happens in less than a microsecond. the simulation will have the opportunity to advance only during the execution of the repeated polling read cycles. The entire execution timeline in the C code occurs in zero-time in the simulation timeline. The only way for the design simulation to proceed. once the read or write operation completes and the control is returned back to the C code. This execution timeline is illustrated in Figure 10-2. the simulation is again frozen. In the latter case. this would require a lot of processing for simulating essentially useless read cycles and exchanging data between the C world and the simulation world. It would likely require many hundreds of such read cycles for the design to reach a state that is relevant and significant for the application software. Figure 10-2 C code and Simulated Design Execution Timeline C Code Simulation (read) (write) t If a polling strategy is used. the simulation will proceed until something of interest to the application software has happened before transfering the control to the C code (through a service entry VMM Additions and Enhancements 211 . With physical device. is for the C code to return. only that code performs any form of processing and the simulation of the rest of the design is frozen. The execution timeline is the cause of the important impact on run-time performance of how the C code interacts with the design.When C code executes. or for the C code to perform a read or write operation through the RAL model. But in a simulation.

010C 0x... Figure 10-3 Example register layout 31 11 5 0 0x.... To that effect..point) and only the necessary read and write operations would need to be performed. while preserving as much as possible the abstraction offered by the RAL model.... the RAL C API hides the physical addresses of registers and the position and size of fields..0100 0x.0110 a2 a2 29 X 6 a1 Y R1 R2 R3 a1 a1 Example 10-6 Example RALF specification block myblk { VMM Additions and Enhancements 212 .... If the application software requires such synchronization.. It is also very important that the execution of the C code not be blocked by an external event—such as waiting for user input or a file to be unlocked—as it will prevent the simulation from moving forward while it is blocked......0104 0x... The hiding is performed by functions and macros rather than an object-oriented structure like the native RAL model in SystemVerilog This is to eliminate the need to compile a complete object-oriented model in an embedded processor object code with limited amount of memory.0108 0x.. Writing Firmware Code The RAL C API is designed to ultimately yield compact and efficient firmware code. It is thus important that a service-based approach be used as much as possible....... it should similarly use an asynchronous servicedriven approach........

field a1 { bits 4. access rw. access rw. field a1 { bits 32. would be accessed. access rw. } } register R2 @0x104 { bytes 12. field a1 { bits 32. } field a2 @64 { bits 30. Example 10-7 shows a single-segment. } } register R3 @0x110{ bytes 4.} bytes 4. access rw. } field X { bits 7. access rw. } field Y @32 { bits 7. } } memory m { bits 32 size 1024 } Accessing Registers Ideally. register R1 @0x0100 { bytes 4. such as register R1 specified in Figure 10-3. endian big. Registers can be accessed using the ral_read_<reg>_in_<block> and ral_write_<reg>_in_<block> macros. Example 10-7 Accessing single-segment register from C void C_func_name(void* blk) VMM Additions and Enhancements 213 . This allows each register to be accessed or updated using a single read or write operation. access rw. registers and memories should be of the same size as the native data bus size of the target process—typically the int type in the C code—and thus live at a single physical address (called "segment"). The RAL C interface supports single-segment as well as multi-segment registers. } field a2 { bits 21. access rw.

0x5678}. If the field has a unique name in its enclosing block. then there will also be macros named ral_read_<field>_in_<block> and ral_write_<field>_in_<block> with identical respective functionality VMM Additions and Enhancements 214 . Accessing Fields Individual fields can be accessed using the corresponding ral_read_<field>_in_<block>_<reg> and ral_write_<field>_in_<block>_<reg> macros. r2). ral_write_R2_in_myblk(blk. as shown in Example 10-8. the entire register can be accessed using the same macros but by using an array of int with one element per physical location. &r1). Endian Support The RAL C interface always read multi-segment registers into the 'int' array ('r2' in Example 10-8) in little-endian order. such as register R2 in Figure 10-3. ral_write_R1_in_myblk(blk. 0x0. Example 10-8 Accessing an entire multi-address register int r2[3]. RAL models that use FIFO ordering are not supported. irrespective of their actual hardware layout as specified in the RALF file. This means that the segments of a multi-segment register in a big-endian block or system will be in the reverse order in the C int array. ral_read_R2_in_myblk(blk. r2).{ } unsigned int r1 = 0xABCD. &r1). ral_read_R1_in_myblk(blk. 0x0}. r1 = 0. r2 = {0xABCD. If a register spans multiple physical locations. r2 = {0x0. 0x1234.

&x). it will be necessary access them using the multi-segment register access procedures and the resulting array-of-int value. 0x100. Example 10-11 Accessing a single-segment memory location unsigned int mem_loc = 0xAABBCCDD. &x). VMM Additions and Enhancements 215 . would be accessed. ral_write_X_in_myblk_R1(ral_addr_of_R1_in_myblk(blk). &mem_loc). &x). offset 0x100 of memory 'm' specified in Example 10-6. or fields need to span more than one physical address. &mem_loc). ral_read_m_in_myblk(blk. Example 10-11 shows how to read and write a memory location.as the previous set of macros. ral_write_X_in_myblk(blk. as illustrated in Figure 10-3. Accessing Memories Memories can be accessed using the ral_read_<mem>_in_<block> and ral_write_<mem>_in_<block> macros. x = 0. Currently. ral_write_m_in_myblk(blk. fields with a size greater than sizeof(int) and fields spanning multiple physical addresses are not supported. ral_read_X_in_myblk(blk. Example 10-9 and Example 1010shows how the field named X. Example 10-10 Accessing field in a specific register unsigned int x = 0x0F. mem_loc = 0. 0x100. If larger fields are required. x = 0. Example 10-9 Accessing a block-unique field unsigned int x = 0x0F. &x). ral_read_X_in_myblk_R1(ral_addr_of_R1_in_myblk(blk).

Note that a multi-segment memory location would be accessed using the same macro. The only difference is that a suitably sized array of int would need to be supplied to hold the memory location value to be read or written. VMM Standard Library Class Additions Classes and members that have been added to the VMM Standard Library are described in the following sections: • • • • • • • vmm_opts vmm_scenario vmm_object vmm_ms_scenario_gen vmm_xactor_iter vmm_test vmm_channel VMM Additions and Enhancements 216 .

Summary • • • • vmm_opts::get_bit() vmm_opts::get_int() vmm_opts::get_string() vmm_opts::get_help() VMM Additions and Enhancements 217 . or as separate command-line options prefixed with "+vmm_".vmm_opts This class provides an interface to define and access run-time options. Its functionality is accessed strictly through static methods. Run-time options can be specified using a combination of command-line arguments and option files specified using a plusseperated list of filenames to the "+vmm_opts_file=" command-line option. No constructor is documented because this class is implemented using a singleton pattern. Using the former is preferable as a warning will be issued if an unknown option is specified. Command-line options can be specified using a plus-separated list of run-time options to the +vmm_opts command-line option.

SystemVerilog static function bit get_bit(string name. The "doc" argument is a short description of the run-time argument that will be displayed by the vmm_opts::get_help() method.+foo+.. or the line "+foo" in the option file. The boolean run-time option "foo" would be supplied using the "+vmm_opts+. or "+vmm_foo" command-line option. the documentation is not redefined. string doc = "").. If it has been previsouly defined for the specified option through a prior call of this method. VMM Additions and Enhancements 218 . Returns FALSE otherwise..vmm_opts::get_bit() Get a boolean option value." command-line option.. Description Return TRUE if the specified option name was specified.

+foo=5+." command-line option. Different calls specifying the same option may have different default values.vmm_opts::get_int() Get an integer option value. If the run-time option was not supplied. SystemVerilog static function int get_int(string name. If it has been previsouly defined for the specified option through a prior call of this method.. VMM Additions and Enhancements 219 . or the line "+foo=5" in the option file.. string doc = ""). or "+vmm_foo=5" command-line option. int dflt = 0. Description Returns the integer value specified as the argument of the specified run-time option... The "doc" argument is a short description of the run-time argument that will be displayed by the vmm_opts::get_help() method. the documentation is not redefined. The integer value "5" for run-time option "foo" would be supplied using the "+vmm_opts+. returns the specified default value.

SystemVerilog static function string get_string(string name.." command-line option. VMM Additions and Enhancements 220 .+foo=bar+. Description Returns the string value specified as the argument of the specified run-time option.. returns the specified default value. or the line "+foo=bar" in the option file. or "+vmm_foo=bar" command-line option..vmm_opts::get_string() Get a string option value. string doc = ""). If the run-time option was not supplied.. The string value "bar" for run-time option "foo" would be supplied using the "+vmm_opts+. The "doc" argument is a short description of the run-time argument that will be displayed by the vmm_opts::get_help() method. If it has been previsouly defined for the specified option through a prior call of this method. the documentation is not redefined. string dflt = "". Different calls specifying the same option may have different default values.

vmm_opts::get_help() Display a list of all known run-time options.. if ($test$plusargs("tb_help")) begin vmm_opts::get_help(). Examples Example 10-12 virtual task tb_env::start().start(). Description Display a human-readable list of all run-time options queried so far. endtask VMM Additions and Enhancements 221 . followed by a call to $finish(). super.. This method is automatically called. end . $finish. SystemVerilog static function void get_help(). by the vmm_env::reset_dut() method if the +vmm_help command-line option is supplied.

vmm_scenario Base class for all user-defined scenarios. Summary • • • • • • • • • • • • • vmm_scenario::stream_id vmm_scenario::scenario_id vmm_scenario::scenario_kind vmm_scenario::length vmm_scenario::repeated vmm_scenario::repeat_thresh vmm_scenario::repetition vmm_scenario::define_scenario() vmm_scenario::redefine_scenario() vmm_scenario::scenario_name() vmm_scenario::psdisplay() vmm_scenario::set_parent_scenario() vmm_scenario::get_parent_scenario() VMM Additions and Enhancements 222 . This class extends from vmm_data.

SystemVerilog int stream_id Description This data member is set by the scenario generator before randomization to the generator’s stream identifier. This state variable can be used to specifiy stream-specific constraints or to differentiate stimulus from different streams in a scoreboard. VMM Additions and Enhancements 223 .vmm_scenario::stream_id Stream identifier of the randomizing generator.

vmm_scenario::scenario_id Scenario identifier of the randomizing generator. This state variable can be used to specifiy scenario-specific constraints or to identify the order of different scenarios within a stream. VMM Additions and Enhancements 224 . SystemVerilog int scenario_id Description This data member is set by the scenario generator before randomization to the generator’s current scenario counter value.

vmm_scenario::scenario_kind Scenario kind identified. SystemVerilog rand int unsigned scenario_kind Description Used to randomly select one of the scenario kinds defined in this random scenario descriptor. VMM Additions and Enhancements 225 .

VMM Additions and Enhancements 226 . SystemVerilog rand int unsigned length Description Random number of transaction descriptor in this random scenario.vmm_scenario::length Length of the scenario. Constrained to be less than or equal to the maximum number of transactions in the selected scenario kind.

Constrained to zero by default by the “vmm_scenario::repetition” constraint block. Note that is is best to repeat the same transaction instead of creating a scenario of many transactions constrained to be identical. VMM Additions and Enhancements 227 . A repetition value of zero specifies that the scenario will not be repeated. SystemVerilog rand int unsigned repeated Description The number of time the entire scenario is repeated. hence will be applied only once.vmm_scenario::repeated Scenario identifier of the randomizing generator.

vmm_scenario::repeat_thresh Repetition warning threshold. SystemVerilog static int unsigned repeat_thresh Description Specifies a threshold value that triggers a warning about possibly unconstrained “vmm_scenario::repeated”data member. VMM Additions and Enhancements 228 . Defaults to 100.

constraint repetition { repeated < 10. SystemVerilog constraint repetition { repeated == 0. It is not often used but. can cause stimulus to be erroneously repeatedly applied over 2 billion times on average. This constraint block constrains this data member to prevent repetition by default. if left unconstrained. } Description The “vmm_scenario::repeated” data member specifies the number of times a scenario is repeated. } endclass VMM Additions and Enhancements 229 .vmm_scenario::repetition Constraint preventing the scenario from being repeated. To have a scenario be repeated a random number of times. Examples Example 10-13 class many_atomic_scenario extends eth_frame_atomic_scenario. simply override this constraint block.

VMM Additions and Enhancements 230 .vmm_scenario::define_scenario() Define a new scenario kind. The new scenario kind may have up to the specified number of random transactions. Description Defines a new scenario kind included in this scenario descriptor and return a unique scenario kind identifier. The scenario kind identifier should be stored in a state variable that can then be subsequently used to specified kind-specific constraints. int unsigned max_len). SystemVerilog function int unsigned define_scenario(string name. The “vmm_scenario::scenario_kind”data member will randomly select one of the defined scenario kinds.

int unsigned max_len). The scenario kind may be redefined with a different name or maximum number of random transactions. SystemVerilog function void redefine_scenario(int unsigned scenario_kind. Use this method to modify.vmm_scenario::redefine_scenario() Redefine an existing scenario kind. VMM Additions and Enhancements 231 . refine or replace an existing scenario kind in a pre-defined scenario descriptor. string name. Description Redefines an existing scenario kind included in this scenario descriptor.

VMM Additions and Enhancements 232 .vmm_scenario::scenario_name() Name of a scenario kind. SystemVerilog function string scenario_name(int unsigned scenario_kind). Description Return the name of the specified scenario kind. as defined by the “vmm_scenario::define_scenario()” or “vmm_scenario::redefine_scenario()” methods.

vmm_scenario::psdisplay() Create an image of the scenario descriptor. SystemVerilog virtual function string psdisplay(string prefix = "") Description Create human-readable image of the content of the scenario descriptor. VMM Additions and Enhancements 233 .

This will allow this scenario to grab a channel that has already been grabbed by the parent scenario. SystemVerilog function void set_parent_scenario( vmm_scenario parent) Description Specify the single stream or multiple-stream scenario that is the parent of this scenario.vmm_scenario::set_parent_scenario() Define higher-level hierarchical scenario. VMM Additions and Enhancements 234 .

SystemVerilog function vmm_scenario get_parent_scenario() Description Get the single stream or multiple-stream scenario that was specified as the parent of this scenario.vmm_scenario::get_parent_scenario() Get the higher-level hierarchical scenario. A scenario with no parent is a top-level scenario. VMM Additions and Enhancements 235 .

vmm_xactor. vmm_subenv.. vmm_consensus and vmm_test classes. \ +define+VMM_PRE_INCLUDE=$VMM_HOME/sv/std_lib/opt/vmm_object...sv \ .sv \ . vmm_env....svh \ +define_VMM_POST_INCLUDE=$VCS_HOME/etc/rvm/sv/std_lib/opt/vmm_object. Summary • • • • • • • • vmm_object::type_e vmm_object::new vmm_object::set_parent() vmm_object::get_parent() vmm_object::get_type() vmm_object::get_hier_inst_name() vmm_object::display() vmm_object::psdisplay() VMM Additions and Enhancements 236 .svh \ +define_VMM_POST_INCLUDE=$VMM_HOME/sv/std_lib/opt/vmm_object.. % vcs . vmm_notify. vmm_scenario. vmm_ms_scenario.vmm_object The vmm_object class is an optional common base class for the vmm_data. This option is enabled by loading the customization definitions files as follows: % vcs . vmm_channel.. \ +define+VMM_PRE_INCLUDE=$VCS_HOME/etc/rvm/sv/std_lib/opt/vmm_object.

or to specify any object type to the “vmm_object::type_e”method. VMM_XACTOR. VMM_CONSENSUS. VMM_DATA.vmm_object::type_e Type of this object. VMM_SUBENV. VMM Additions and Enhancements 237 . VMM_MS_SCENARIO. VMM_ENV. a reference to a vmm_object can be cast into the corresponding class type. SystemVerilog typedef enum { VMM_UNKNOWN. The VMM_OBJECT is returned when the type of the object cannot be determined. VMM_NOTIFY. VMM_SCENARIO. Once the type is known. VMM_OBJECT. VMM_TEST } type_e Description Value returned by the “vmm_object::type_e”method to identify the type of this vmm_object extension. The VMM_UNKNOWN type is an internal value and never returned by the “vmm_object::type_e”method. VMM_CHANNEL.

Description Optionally specify a parent object to this object when constructing a vmm_object instance. See “vmm_object::type_e” for more details on specifying a parent object. VMM Additions and Enhancements 238 .vmm_object::new Constructor. SystemVerilog function new(vmm_object parent = NULL).

Specifying a NULL parent breaks the any current parent/child relationship. If this object and the parent object are known to contain their own instance of the message service interface.vmm_object::set_parent() Specify a parent object. the ‘VMM_OBJECT_SET_PARENT(_parent. This macro will call this method if the vmm_object base class is present but do nothing if not. An object may have only one parent. Description Specify a new parent object to this object. SystemVerilog function void set_parent(vmm_object parent). VMM Additions and Enhancements 239 . _child) macro should be used instead.is_above(this). it is not possible to call this method in code designed to be reusable with and without this base class. To that effect. The presence of the vmm_object base class being optional. The instance names of the message service interfaces can then be subsequently made hierarchical by using the “vmm_log::use_hier_inst_name()” method.log).notify = new(this. but the identity of a parent can be changed dynamically. the vmm_log instance in the parent is specified as being above the vmm_log instance in the chil by calling parent. Examples Example 10-14 this.

‘VMM_OBJECT_SET_PARENT(this. this) VMM Additions and Enhancements 240 .notify.notify. Example 10-15 this.this.set_parent(this).log).notify = new(this.

Returns NULL if no such parent is found. VMM Additions and Enhancements 241 .vmm_object::get_parent() Get a parent object. if any. SystemVerilog function vmm_object get_parent( vmm_object::type_e typ = VMM_OBJECT). Specifying VMM_OBJECT returns the immediate parent of any type. Description Return the parent object of the specified type.

Description Return the type of this vmm_object extension.vmm_object::get_type() Get the type of the object. SystemVerilog function vmm_object::type_e get_type(). Returns VMM_OBJECT if it is not one of the known VMM class extensions. VMM Additions and Enhancements 242 . VMM_UNKNOWN is purely an internal value and is never returned.

The hierarchical name is return whether or not the message services interfaces are using hierarchical or flat names.vmm_object::get_hier_inst_name() Get the hierarchical instance name of the object. SystemVerilog function string get_hier_inst_name(). VMM Additions and Enhancements 243 . Description Return the hierarchical instance name of the object. The instance name is composed of the dot-separated instance names of the message service interface of all the parents of the object.

VMM Additions and Enhancements 244 . If this method conflicts with a previously declared method in a class now based on the vmm_object class. it can be removed by defining the ‘VMM_OBJECT_NO_DISPLAY symbol at compile-time. Description Display the image returned by “vmm_object::type_e”to the standard output.vmm_object::display() Display a description of the object to stdout SystemVerilog virtual function void display(string prefix = "").

Description Creates a human-readable image of the content of the object and returns it as a string. If this method conflicts with a previously declared method in a class now based on the vmm_object class.vmm_object::psdisplay() Create a description of the object SystemVerilog virtual function string psdisplay(string prefix = ""). VMM Additions and Enhancements 245 . The description should not contain a final newline character. Each line of the image is prefixed with the specified prefix. it can be removed by defining the ‘VMM_OBJECT_NO_DISPLAY symbol at compile-time.

The following methods are available. See Xref for guidelines on how the multi-stream scenario generator can be used and how multistream scenarios—including hierarchical scenarios—are defined and executed. Summary • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • vmm_ms_scenario_gen::stop_after_n_scenarios vmm_ms_scenario_gen::inst_count vmm_ms_scenario_gen::scenario_count vmm_ms_scenario_gen::inst_count vmm_ms_scenario_gen::get_n_scenarios() vmm_ms_scenario_gen::get_n_insts() vmm_ms_scenario_gen::GENERATED vmm_ms_scenario_gen::DONE vmm_ms_scenario_gen::register_ms_scenario() vmm_ms_scenario_gen::ms_scenario_exists() vmm_ms_scenario_gen::get_ms_scenario() vmm_ms_scenario_gen::get_ms_scenario_name() vmm_ms_scenario_gen::get_ms_scenario_index() vmm_ms_scenario_gen::get_names_by_ms_scenario() vmm_ms_scenario_gen::get_all_ms_scenario_names() vmm_ms_scenario_gen::replace_ms_scenario() vmm_ms_scenario_gen::unregister_ms_scenario() vmm_ms_scenario_gen::unregister_ms_scenario_by_name() vmm_ms_scenario_gen::select_scenario vmm_ms_scenario_gen::scenario_set[$] vmm_ms_scenario_gen::register_channel() vmm_ms_scenario_gen::channel_exists() vmm_ms_scenario_gen::get_channel() vmm_ms_scenario_gen::get_channel_name() vmm_ms_scenario_gen::get_names_by_channel() vmm_ms_scenario_gen::get_all_channel_names() vmm_ms_scenario_gen::replace_channel() vmm_ms_scenario_gen::unregister_channel() vmm_ms_scenario_gen::unregister_channel_by_name() vmm_ms_scenario_gen::register_ms_scenario_gen() vmm_ms_scenario_gen::ms_scenario_gen_exists() vmm_ms_scenario_gen::get_ms_scenario_gen() vmm_ms_scenario_gen::get_ms_scenario_gen_name() vmm_ms_scenario_gen::get_all_ms_scenario_gen_names() vmm_ms_scenario_gen::replace_ms_scenario_gen() vmm_ms_scenario_gen::unregister_ms_scenario_gen() vmm_ms_scenario_gen::unregister_ms_scenario_gen_by_name() VMM Additions and Enhancements 246 .vmm_ms_scenario_gen This class is a pre-defined multi-stream scenario generator.

Sub-scenarios executed as part of a higher-level multi-stream scenario are not counted. SystemVerilog int unsigned stop_after_n_scenarios Description Automatically stop the multi-stream scenario generator when the number of generated multi-streams scenarios reaches or surpasses the specified value. VMM Additions and Enhancements 247 .vmm_ms_scenario_gen::stop_after_n_scenarios Number of multi-stream scenarios to generate. A value of zero specifies an infinite number of multi-stream scenarios. Only the multi-stream scenarios explicitly executed by this instance of the multi-stream scenario generator are counted.

VMM Additions and Enhancements 248 .vmm_ms_scenario_gen::stop_after_n_insts Number of transaction descriptor to generate. A value of zero indicates an infinite number of transaction descriptors. SystemVerilog int unsigned stop_after_n_insts Description Automatically stop the multi-stream scenario generator when the number of generated transaction descriptors reaches or surpasses the specified value. The number of transaction descriptor instances generated by the execution of a multi-stream scenario is the number of transactions reported by the vmm_ms_scenario::execute() method when it returns. Entire scenarios are executed before the generator is stopped so the actual number of transaction descriptors generated may be greater than the specified value.

SystemVerilog protected int scenario_count. Description Current count of the number of top-level multi-stream scenarios generated the multi-stream scenario generator. Only the multi-stream scenarios explicitly executed by this instance of the multi-stream scenario generator are counted. the generator stops. When is reaches or surpasses the value in vmm_ms_scenario_gen::stop_after_n_scenarios. VMM Additions and Enhancements 249 .vmm_ms_scenario_gen::scenario_count Number of multi-stream scenarios generated so far. Sub-scenarios executed as part of a higher-level multi-stream scenario are not counted.

SystemVerilog protected int inst_count. When is reaches or surpasses the value in vmm_ms_scenario_gen::stop_after_n_insts.vmm_ms_scenario_gen::inst_count Number of transaction descriptor generated so far. VMM Additions and Enhancements 250 . The number of transaction descriptor instances generated by the execution of a multi-stream scenario is the number of transactions reported by the vmm_ms_scenario::execute() method when it returns. the generator stops. Description Current count of the number of individual transaction descriptor instances generated by the multi-stream scenario generator.

VMM Additions and Enhancements 251 .vmm_ms_scenario_gen::get_n_scenarios() Number of multi-stream scenarios generated so far. SystemVerilog function int unsigned get_n_scenarios() Description Return the current value of the vmm_ms_scenario_gen::scenario_count property.

SystemVerilog function int unsigned get_n_insts() Description Return the current value of the vmm_ms_scenario_gen::inst_count property.vmm_ms_scenario_gen::get_n_insts() Number of transaction descriptors generated so far. VMM Additions and Enhancements 252 .

VMM Additions and Enhancements 253 . SystemVerilog typedef enum int {GENERATED} symbols_e Description Notification in vmm_xactor::notify that is indicated every time a new multi-stream scenario is generated and about to be executed.vmm_ms_scenario_gen::GENERATED Notification of a newly generated scenario.

SystemVerilog typedef enum int {DONE} symbols_e Description Notification in vmm_xactor::notify that is indicated when the generation process has completed as specified by the scenvmm_ms_scenario_gen::stop_after_n_scenarios and vmm_ms_scenario_gen::stop_after_n_insts class properties. VMM Additions and Enhancements 254 .vmm_ms_scenario_gen::DONE Notification of a generation completed.

thus creating an alias to the same scenario. The same scenario may be registered multiple times under different names. vmm_ms_scenario scenario) Description Registers the specified multi-stream scenario under the specified name. Use vmm_ms_scenario_gen::replace_ms_scenario() to replace a registered scenario. Registering a scenario implicitly appends it to the scenario set if it is not already in the vmm_ms_scenario_gen::scenario_set[$] array.vmm_ms_scenario_gen::register_ms_scenario() Register a multi-strea. It is an error to attempt to register a scenario under a name that already exists. scenario descriptor SystemVerilog virtual function void register_ms_scenario(string name. VMM Additions and Enhancements 255 .

VMM Additions and Enhancements 256 .vmm_ms_scenario_gen::ms_scenario_exists() Checks if a scenario is registered under a specified name SystemVerilog virtual function bit ms_scenario_exists(string name) Description Returns TRUE if there is a multi-stream scenario registered under the specified name. Returns FALSE otherwise. Use vmm_ms_scenario_gen::get_ms_scenario() to retrieve a scenario under a specified name.

vmm_ms_scenario_gen::get_ms_scenario() Get the scenario registered under a specified name SystemVerilog virtual function vmm_ms_scenario get_ms_scenario( string name) Description Returns the multi-stream scenario descriptor registered under the specified name. VMM Additions and Enhancements 257 . Issues a warning message and returns NULL if there are no scenarios registered under that name.

VMM Additions and Enhancements 258 . Returns "" if the scenario is not registered.vmm_ms_scenario_gen::get_ms_scenario_name() Get a name under which a scenario is registered SystemVerilog virtual function string get_names_by_ms_scenario( vmm_ms_scenario scenario) Description Returns a name under which the specified multi-stream scenario descriptor is registered.

VMM Additions and Enhancements 259 . A warning message is issued and returns -1 if the scenario descriptor is not found in the scenario set.vmm_ms_scenario_gen::get_ms_scenario_index() Get the index of the specified scenario SystemVerilog virtual function int get_ms_scenario_index( vmm_ms_scenario scenario) Description Returns the index of the specified scenario descriptor in the vmm_ms_scenario_gen::scenario_set[$] array.

ref string name[$]) Description Appends the names under which the specified multi-stream scenario descriptor is registered.vmm_ms_scenario_gen::get_names_by_ms_scenario( ) Get the names under which a scenario is registered SystemVerilog virtual function int get_names_by_ms_scenario( vmm_ms_scenario scenario. Returns the number of names that were added to the array. VMM Additions and Enhancements 260 .

vmm_ms_scenario_gen::get_all_ms_scenario_names( ) Get all the names in the scenario registry SystemVerilog virtual function int get_all_ms_scenario_names( ref string name[$]) Description Appends the names under which a multi-stream scenario descriptor is registered. Returns the number of names that were added to the array. VMM Additions and Enhancements 261 .

vmm_ms_scenario scenario) Description Registers the specified multi-stream scenario under the specified name. Registering a scenario implicitly appends it to the scenario set if it is not already in the vmm_ms_scenario_gen::scenario_set[$] array. The same scenario may be registered multiple times under different names. replacing the scenario previously registered under that name (if any). The replaced scenario is removed from vmm_ms_scenario_gen::scenario_set[$] if it is not also registered under another name. VMM Additions and Enhancements 262 .vmm_ms_scenario_gen::replace_ms_scenario() Replace a scenario descriptor SystemVerilog virtual function void replace_ms_scenario(string name. thus creating an alias to the same scenario.

The unregistered scenario is also removed from the vmm_ms_scenario_gen::scenario_set[$] array. VMM Additions and Enhancements 263 .vmm_ms_scenario_gen::unregister_ms_scenario() Unregister a scenario descriptor SystemVerilog virtual function bit unregister_ms_scenario( vmm_ms_scenario scenario) Description Completely unregisters the specified multi-stream scenario descriptor and returns TRUE if it exists in the registry.

The unregistered scenario descriptor is removed from vmm_ms_scenario_gen::scenario_set[$] if it is not also registered under another name. VMM Additions and Enhancements 264 .vmm_ms_scenario_gen::unregister_ms_scenario_by_ name() Unregister a scenario descriptor SystemVerilog virtual function vmm_ms_scenario unregister_ms_scenario( string name) Description Unregisters the multi-stream scenario under the specified name and returns the unregistered scenario descriptor. Returns NULL if there is no scenario registered under the specified name.

VMM Additions and Enhancements 265 . The selection is performed by calling randomize() on this class property then executing the multi-stream scenario found in the vmm_ms_scenario_gen::scenario_set[$] array at the index specified by the vmm_ms_scenario_election::select class property. The default election instance may be replaced by a user-defined extension to modify the scenario election policy.vmm_ms_scenario_gen::select_scenario Scenario selection factory SystemVerilog vmm_ms_scenario_election select_scenario Description Randomly select the next multi-stream scenario to execute from the vmm_ms_scenario_gen::scenario_set[$] array.

Multi-stream scenario instances in this array should be managed through the vmm_ms_scenario_gen::register_ms_scenario().vmm_ms_scenario_gen::scenario_set[$] Multi-stream scenarios available for execution SystemVerilog vmm_ms_scenario scenatio_set[$] Description Multi-stream scenarios available for execution by this generator. VMM Additions and Enhancements 266 . The scenario executed next is selected by randomizing the vmm_ms_scenario_gen::select_scenario class property. vmm_ms_scenario_gen::replace_ms_scenario() and vmm_ms_scenario_gen::unregister_ms_scenario() methods.

Use vmm_ms_scenario_gen::replace_channel() to replace a registered scenario. Once registered.vmm_ms_scenario_gen::register_channel() Register an output channel SystemVerilog virtual function void register_channel(string name. VMM Additions and Enhancements 267 . thus creating an alias to the same channel. vmm_channel chan) Description Registers the specified output channel under the specified logical name. It is an error to attempt to register a channel under a name that already exists. the output channel becomes available under the specified logical name to multi-stream scenarios via the vmm_ms_scenario::get_channel() method. The same channel may be registered multiple times under different names.

VMM Additions and Enhancements 268 . Use vmm_ms_scenario_gen::get_channel() to retrieve a channel under a specified name. Returns FALSE otherwise.vmm_ms_scenario_gen::channel_exists() Checks if a channel is registered under a specified name SystemVerilog virtual function bit channel_exists(string name) Description Returns TRUE if there is an output channel registered under the specified name.

vmm_ms_scenario_gen::get_channel() Get the channel registered under a specified name SystemVerilog virtual function vmm_channel get_channel( string name) Description Returns the output channel registered under the specified name. Issues a warning message and returns NULL if there are no channels registered under that name. VMM Additions and Enhancements 269 .

VMM Additions and Enhancements 270 .vmm_ms_scenario_gen::get_channel_name() Get a name under which a channel is registered SystemVerilog virtual function string get_names_by_channel( vmm_channel chan) Description Return a names under which the specified channel is registered. Returns "" if the channel is not registered.

VMM Additions and Enhancements 271 . ref string name[$]) Description Appends the names under which the specified output channel is registered.vmm_ms_scenario_gen::get_names_by_channel() Get the names under which a channel is registered SystemVerilog virtual function int get_names_by_channel( vmm_channel chan. Returns the number of names that were added to the array.

VMM Additions and Enhancements 272 . Returns the number of names that were added to the array.vmm_ms_scenario_gen::get_all_channel_names() Get all the names in the channel registry SystemVerilog virtual function int get_all_channel_names( ref string name[$]) Description Appends the names under which an output channel is registered.

vmm_ms_scenario_gen::replace_channel() Replace an output channel SystemVerilog virtual function void replace_channel(string name. The same channel may be registered multiple times under different names. VMM Additions and Enhancements 273 . replacing the channel previously registered under that name (if any). thus creating an alias to the same output channel. vmm_channel chan) Description Registers the specified output channel under the specified name.

VMM Additions and Enhancements 274 .vmm_ms_scenario_gen::unregister_channel() Unregister an output channel SystemVerilog virtual function bit unregister_channel( vmm_channel chan) Description Completely unregisters the specified output channel and returns TRUE if it exists in the registry.

vmm_ms_scenario_gen::unregister_channel_by_nam e() Unregister an output channel SystemVerilog virtual function vmm_channel unregister_channel( string name) Description Unregisters the output channel under the specified name and returns the unregistered channel. Returns NULL if there is no channel registered under the specified name. VMM Additions and Enhancements 275 .

Once registered. thus creating an alias to the same generator. VMM Additions and Enhancements 276 . It is an error to attempt to register a generator under a name that already exists.vmm_ms_scenario_gen::register_ms_scenario_gen() Register a sub-generator SystemVerilog virtual function void register_ms_scenario_gen(string name. vmm_ms_scenario_gen gen) Description Registers the specified sub-generator under the specified logical name. The same generator may be registered multiple times under different names. the multi-stream generator becomes available under the specified logical name to multi-stream scenarios via the vmm_ms_scenario::get_ms_scenario() method to create hierarchical multi-stream scenarios. Use vmm_ms_scenario_gen::replace_ms_scenario_gen() to replace a registered generator.

Use vmm_ms_scenario_gen::get_ms_scenario_gen() to retrieve a sub-generator under a specified name. VMM Additions and Enhancements 277 . Returns FALSE otherwise.vmm_ms_scenario_gen::ms_scenario_gen_exists() Checks if a generator is registered under a specified name SystemVerilog virtual function bit ms_scenario_gen_exists(string name) Description Returns TRUE if there is a sub-generator registered under the specified name.

vmm_ms_scenario_gen::get_ms_scenario_gen() Get the sub-generator registered under a specified name SystemVerilog virtual function vmm_ms_scenario_gen get_ms_scenario_gen( string name) Description Returns the sub-generator registered under the specified name. VMM Additions and Enhancements 278 . Issues a warning message and returns NULL if there are no generators registered under that name.

Returns "" if the generator is not registered. VMM Additions and Enhancements 279 .vmm_ms_scenario_gen::get_ms_scenario_gen_name( ) Get a names under which a generator is registered SystemVerilog virtual function string get_names_by_ms_scenario_gen( vmm_ms_scenario_gen gen) Description Returns a names under which the specified sub-generator is registered.

vmm_ms_scenario_gen::get_names_by_ms_scenario _gen() Get the names under which a generator is registered SystemVerilog virtual function int get_names_by_ms_scenario_gen( vmm_ms_scenario_gen gen. VMM Additions and Enhancements 280 . ref string name[$]) Description Appends the names under which the specified sub-generator is registered. Returns the number of names that were added to the array.

vmm_ms_scenario_gen::get_all_ms_scenario_gen_na mes() Get all the names in the generator registry SystemVerilog virtual function int get_all_ms_scenario_gen_names( ref string name[$]) Description Appends the names under which a sub-generator is registered. Returns the number of names that were added to the array. VMM Additions and Enhancements 281 .

vmm_ms_scenario_gen::replace_ms_scenario_gen() Replace a sub-generator SystemVerilog virtual function void replace_ms_scenario_gen(string name. The same generator may be registered multiple times under different names. replacing the generator previously registered under that name (if any). thus creating an alias to the same sub-generator. vmm_ms_scenario_gen gen) Description Registers the specified sub-generator under the specified name. VMM Additions and Enhancements 282 .

VMM Additions and Enhancements 283 .vmm_ms_scenario_gen::unregister_ms_scenario_gen () Unregister a sub-generator SystemVerilog virtual function bit unregister_ms_scenario_gen( vmm_ms_scenario_gen gen) Description Completely unregisters the specified sub-generator and returns TRUE if it exists in the registry.

Returns NULL if there is no generator registered under the specified name.vmm_ms_scenario_gen::unregister_ms_scenario_gen _by_name() Unregister a sub-generator SystemVerilog virtual function vmm_ms_scenario_gen unregister_ms_scenario_gen( string name) Description Unregisters the generator under the specified name and returns the unregistered generator. VMM Additions and Enhancements 284 .

vmm_xactor_iter This class can iterate over all known vmm_xactor instances. based on the names and instance names. regardless of their location in the class hierarchy. Summary • • • • vmm_xactor_iter::new() vmm_xactor_iter::first() vmm_xactor_iter::xactor() vmm_xactor_iter::next() VMM Additions and Enhancements 285 .

next(). Otherwise.. end iter. The subsequent transactors can be iterated on. the first transactor matching the specified name and instance name patterns is available using the “vmm_xactor_iter::xactor()” method.xactor() != null) begin ahb_master ahb. Description Create a new transactor iterator and initialize it using the specified name and instance name. while (iter. end VMM Additions and Enhancements 286 . “vmm_xactor_iter::first()”is implicitly called.xactor()) begin ./").vmm_xactor_iter::new() Create a new transactor iterator. If the specified name or instance name is enclosed between ’/’ characters. So once created. they are interpreted as the full name or instance name to match. Examples Example 10-16 vmm_xactor_iter iter = new("/AHB/").. using the “vmm_xactor_iter::next()” method./". if ($cast(ahb. SystemVerilog function void new(string name string inst = "/. iter. = "/. their are interpreted as regular expressions. one at a time.

vmm_xactor_iter::first() Reset the iterator to the first transactor. Returns null if no transactors match. if found. SystemVerilog function vmm_xactor first(). The order in which transactors are iterated on is unspecified. VMM Additions and Enhancements 287 . Description Reset the iterator to the first transactor matching the name and instance name patterns specified when the iterator was created using vmm_xactor_iter::new() and return a reference to it.

SystemVerilog function vmm_xactor xactor(). VMM Additions and Enhancements 288 . Description Return a reference to a transactor matching the name and instance name patterns specified when the iterator was created using vmm_xactor_iter::new(). Returns null if no transactors match.vmm_xactor_iter::xactor() Return the current transactor iterated on.

SystemVerilog function vmm_xactor next(). if found.vmm_xactor_iter::next() Move the iterator to the next transactor. Returns null if no transactors match. The order in which transactors are iterated on is unspecified. VMM Additions and Enhancements 289 . Description Move the iterator to the next transactor matching the name and instance name patterns specified when the iterator was created using vmm_xactor_iter::new() and return a reference to it.

/". name.). end end VMM Additions and Enhancements 290 . looking for transactors of a specific type. "/. "/. The macro must be located immediately after a "begin" keyword.‘foreach_vmm_xactor() Short-hand transactor iterator macro. matching a specific name and instance name. SystemVerilog ‘foreach_vmm_xactor(type. end Description Short-hand macro to simplify the creating and operation of a transactor iterator instance.register_callback(. The subsequent statement is executed for each transactor iterated on... A variable named "xact" of the type specified as the first argument to the macro is implicitly declared and iteratively set to each transactor of the specified type that matches the specified name and instance name... Examples Example 10-17 Iterating over all transactors of type "ahb_master" begin ‘foreach_vmm_xactor(ahb_master. inst) begin xact./") begin xact.

By default.e. string name = "". catches all messages issued by this message service interface instance. string inst = "".vmm_log::catch() Add a user-defined message handler SystemVerilog function int catch( vmm_log_catcher catcher. the last handler installed will be considered first. User-defined message handlers are considered in reverse order of installation i. int severity = ALL_SEVS. bit recurse = 0. VMM Additions and Enhancements 291 . which contains the specified text. Once caught. string text = ""). A unique message handler identifier is returned that can be used to later uninstall the message handler using vmm_log::uncatch(). Messages will be considered caught by the first user-defined handler found that can handle the message. messages are handed off to the vmm_log_catcher::caught() method and will not be issued. A user-defined message handler may choose to explicitly issue the message using the vmm_log_catcher::issue() method or throw the message back to the message service by using the vmm_log_catcher::throw() method to be potentially caught by another suitable message handler or be issued. int typs = ALL_TYPS. issued by the specified message service interface instances. Description Install the specified message handler to catch any message of the specified type and severity.

the modified message will trigger applicable watchpoints.Watchpoints are triggered after message catching. if any. VMM Additions and Enhancements 292 . If the message has been modified in the catcher.

Summary • • • • • • • vmm_test::log vmm_test::new() vmm_test::get_name() vmm_test::get_doc() vmm_test::run() vmm_test_begin() vmm_test_end() VMM Additions and Enhancements 293 .vmm_test This base class may be used to implement testcases. It enables runtime selection of the testcase to run on an environment.

vmm_test::log Message service interface for the testcase. The name of the message service interface is "Testcase" and the instance name is the name specified to the vmm_test::new() method. SystemVerilog vmm_log log. VMM Additions and Enhancements 294 . Description Message service interface instance that can be used to issue messages in the vmm_test::run() method.

.vmm_test::new() Create a test. function new(). virtual task run(vmm_env env).. super. its message service interface and registers it in the global testcase registry under the specified name. endfunction static my_test this_test = new(). A short description of the testcase may also be specified. SystemVerilog function new(string name. Examples Example 10-18 class my_test extends vmm_test. endtask endclass VMM Additions and Enhancements 295 .new("my_test").. string doc = ""). Description Create an instance of the testcase.

‘vmm_note(this.vmm_test::get_name() Get the name of a test. this.. function new(). SystemVerilog function string get_name().new("my_test"). {"Running test ". .get_name()}). virtual task run(vmm_env env). endfunction static my_test this_test = new().. super.log. endtask endclass VMM Additions and Enhancements 296 . Description Return the name of the test that was specify in the constructor. Examples Example 10-19 class my_test extends vmm_test.

new("my_test"). .vmm_test::get_doc() Get the description of a test.get_name()}). virtual task run(vmm_env env).. super. endtask endclass VMM Additions and Enhancements 297 . ‘vmm_note(this. {"Running test ". Description Return the short description of the test that was specify in the constructor.. Examples Example 10-20 class my_test extends vmm_test. SystemVerilog function string get_doc().log. this. endfunction static my_test this_test = new(). function new().

If a different test implementation is required.stop_xactor().run(). tb_env my_env.run(). endtask endclass VMM Additions and Enhancements 298 . the default implementation of this method must not be invoked using super. SystemVerilog virtual task run(vmm_env env).build().. . Examples Example 10-21 class my_test extends vmm_test. Description The test itself.run(). virtual task run(vmm_env env). my_env.gen[0]..vmm_test::run() Run a test. env). my_env. This method should not call vmm_log::report(). my_env. $cast(my_env. The default implementation of this method calls env.

doc string) Description Short-hand macro that may be used to define a user-defined testcase implemented using a class based on the vmm_test class. It must be preceeded by any import statement required by the test implementation. This macro can then be followed by variable declarations and procedural statements.vmm_test_begin() Short-hand macro to define a testcase class. A data member of that type named "env" will be defined and assigned. SystemVerilog ‘vmm_test_begin(testclassname. envclassname. The instance of the verification environment of the specified type can be accessed as "this. The first argument is the name of the testcase class and will also be used as the name of the testcase in the global testcase registry.env". Examples This example shows how the testcase from Example 2-72 and Example 2-75 can be implemented using short-hand macros Example 10-22 import tb_env_pkg::*. This macro can be used to create the testcase class up to and including the declaration of the vmm_test::run() method. ready to be used. The third argument is a string documenting the purpose of the test. VMM Additions and Enhancements 299 . The second argument is the name of the environment class that will be used to execute the testcase.

‘vmm_test_begin(my_test, tb_env, "Simple test") this.env.build(); this.env.gen[0].stop_xactor(); this.env.run(); ‘vmm_test_end(my_test)

VMM Additions and Enhancements 300

vmm_test_end()
Short-hand macro to define a testcase class.

SystemVerilog
‘vmm_test_end(testclassname)

Description
Short-hand macro that may be used to define a user-defined testcase implemented using a class based on the vmm_test class. The first argument must be the same name specified as the first argument of the vmm_test_begin() macro. This macro can be used to end the testcase class, including the implementation of the vmm_test::run() method.

Examples
This example shows how the testcase from Example 2-72 and Example 2-75 can be implemented using short-hand macros Example 10-23
‘vmm_test_begin(my_test, tb_env) this.env.build(); this.env.gen[0].stop_xactor(); this.env.run(); ‘vmm_test_end(my_test)

VMM Additions and Enhancements 301

vmm_ms_scenario::get_channel()
Get a registered output channel.

SystemVerilog
function vmm_channel get_channel(string name)

Description
Get the output channel registered under the specified logical name in the multi-stream generator where the multi-stream scenario generator is registered. Returns NULL of no such channel exists.

VMM Additions and Enhancements 302

vmm_channel
The following function and task have been added to the vmm_channel base class: • • vmm_channel::record() vmm_channel::playback()

VMM Additions and Enhancements 303

vmm_channel::record()
Records transaction descriptions, relative flow sequence, and timing in the specified file. Syntax
function bit record(string filename);

Description Starts recording the flow of transaction descriptors through the channel instance in the specified file. The vmm_data::byte_pack() or vmm_data::save() method must be implemented for the flowing transaction descriptors. A transaction descriptor is recorded when it is injected into the channel by the vmm_channel::put() or vmm_channel::sneak() method. Recording is also done when an attempt is made to vmm_channel::unput() a transaction descriptor from the channel. This function works as an ON-OFF switch. When called with a valid filename, it turns ON recording of transactions. When called with a null (empty string) filename, recording is stopped. Calling this function with a valid filename while recording is ON results in a warning, and no action is taken. Likewise, calling this function with a null (empty string) filename while recording is OFF results in a warning, and no action will be taken. This function returns TRUE if recording was successful. While recording is on, RECORDING notification is indicated by vmm_channel::notify().

VMM Additions and Enhancements 304

Usage Example
string filename = "./record.dat"; xactor.in_chan.record(filename); //start recording // Information about all transactions flowing through // "xactor.in_chan" will be recorded in ’filename’ … xactor.in_chan.record(""); //stops recording

VMM Additions and Enhancements 305

vmm_channel::playback()
Executes the recorded transaction operations into the channel instance.

Syntax
task playback(output bit success, input string filename, input vmm_data factory, input bit metered = 0);

Description
This task executes the recorded transaction operations (put/unput/ sneak), in the same sequence in which they were recorded, into the channel instance. It acts as a producer for the channel instance. Playback does not have to happen in the same simulation run as recording: it can be executed in a different simulation run. The vmm_data::byte_unpack() or vmm_data::load() method, must be implemented for the transaction descriptor, passed to the factory argument. You must provide a non-null factory argument, of the same transaction descriptor type as that with which recording was done. The transaction descriptors are played back one by one in the order specified in the file. If the metered argument is TRUE, the transaction descriptors are played back (that is, by sneak/put/ unput) to the channel in the same relative simulation time interval as the one in which they were originally recorded. While playback is executing on a channel, all other sources of the channel are locked (vmm_channel::put is not allowed from any other source). Sneak is still allowed from other sources, but a warning is printed on any such attempt.

VMM Additions and Enhancements 306

//this. PLAYBACK_DONE notification is indicated by vmm_channel::notify().this.generator. then success is set to FALSE."vmm_channel::playback() function failed").dat". a corrupt file.Output parameter success is set to TRUE if the playback was successful.start_xactor(). string filename = ". bit success./record.dat". … factory = new.log.in_chan. // Playback with same timing as recording endfunction task start(). VMM Additions and Enhancements 307 .success. class packet_env extends vmm_env.success) `vmm_error(this.metered).factory. Example Example 10-24 string filename = ".this. metered = 1’b1.playback( //this. or an empty file. `else fork begin //Start playback this.xactor. vmm_channel bit metered. if(!this. … function new()./record.filename. data_packet factory. When playback is completed. // Other start code … `ifndef PLAY_DATA this. If playback encounters an error condition such as a null (empty string) filename.

end join_none `endif endtask endclass::packet_env VMM Additions and Enhancements 308 .

vmm_ral_block_or_sys Base Class Additions The following functions have been added to the the vmm_ral_block_or_sys class: • • “vmm_ral_block_or_sys::set_offset()” “vmm_ral_block_or_sys::get_reg_by_offset()” VMM Additions and Enhancements 309 .

Note that after using this method. The new address range for the block or subsystem must not be occupied by another block or subsystem. string domain = "") Description Dynamically relocate the base address of the specified domain in the block or subsystem in the address space of the immediately instantiating system.vmm_ral_block_or_sys::set_offset() Modify the base address of the block or system. Returns FALSE if the specified domain does not exist in the immediately enclosing system or the new base address creates an overlap between this block or subsystem address range and another block or subsystem. the behavior of the RAL model will be different from the RALF specification. Returns TRUE of the relocation was succesful. VMM Additions and Enhancements 310 . It is not possible to relocate the base address of the top-level system because is it not instantiated anywhere. SystemVerilog virtual function bit set_offset(bit [63:0] offset.

vmm_ral_block_or_sys::get_reg_by_offset() Gets the register at the specified offset in this block or system. which takes more memory than the default version. returns NULL. This function has a default version and a faster version. short-circuiting the search wherever possible. The entire register may occupy more than one offset within the address space of the block or system if it is wider than the physical interface. this function looks for the start (lowest) address of the register’s address space. In the default (slower) version. all registers of the underlying blocks and subsystems are searched. string domain = "") Description Finds the register located at the specified offset within the block or system address space in the specified domain and returns its descriptor. to check if a register exists at the specified block/system level offset/address. VMM Additions and Enhancements 311 . SystemVerilog virtual function vmm_ral_reg get_reg_by_offset( bit [63:0] offset. If no register is found at the specified offset. In such cases.

VMM Additions and Enhancements 312 . You can activate the faster version by defining the runtime macro VMM_RAL_FAST_SRCH.The faster version uses associative arrays to cache block level register offsets. Memory consumption is higher in the faster version. given an offset. which helps to speed up the search. due to caching.

the Word Doc flow does not currently support OpenOffice input. Note: Unlike the VMM Planner Spreadsheet annotator flow. Either MS-Word 2003 or later can be used to create the . VMM Planner MS Word Annotation 303 . Back-annotation is an extension of the existing VMM Planner Spreadsheet annotator flow. The hvp annotate command and most of its switches can be used for back-annotation the same way that they are used with the spreadsheet annotator.doc plan.11 VMM Planner MS Doc Annotation 1 The VMM Planner Doc annotator enables creation of verification plans using Microsoft Office (.doc verification plan. The . and back-annotation of coverage and other scores into the .doc) documents.doc verification plan must be formatted properly with predefined styles and keywords built into the VMM Planner Doc annotator.

charts. Formatting features such as selectable fonts. VMM Planner MS Word Annotation 304 .This section contains the following topics: • • • • • • “Introduction” on page 304 “Use Model” on page 305 “hvp annotate Command Arguments” on page 307 “Capturing a Verification Plan in Doc XML Format” on page 310 “Debugging the Doc Plan” on page 319 “How to Get Scores Back-Annotated in the Doc” on page 322 Introduction The VMM Planner Doc annotator is used: • • To provide simple hooks in MS Word-compliant documents to interface with VMM Planner-enabled applications. text alignment. To provide flexibility in formatting verification plan doc XML for nicely formatted coverage reports. graphics. tables and descriptions are applied in both the plan and the annotated output report. The same doc XML file is used by VMM Planner as a verification plan and as an annotated report.

Use Model Figure 11-1 Word Doc annotator use model External Doc Plan XML .hvp Files External Debugging External Doc XML Synopsys Unified Coverage Database hvp annotate Annotated External Doc XML HVP User Data This section contains the following topics: • • • • “Process Flow” on page 306 “License Model” on page 306 “Supported Platforms” on page 307 “Compatibility with the VMM Planner Spreadsheet Annotation Flow” on page 307 VMM Planner MS Word Annotation 305 .

this debug check step can be skipped when annotating with new coverage databases.dbg.ann.xml to see the annotated scores.06 Beta is a Beta feature.Process Flow 1. Once the plan becomes stable. Prepare Synopsys coverage database and HVP user data files. covdb. This is typically done by starting with a Synopsys-provided template file and marking key paragraphs in the created doc with Synopsys-defined styles. Run hvp annotate with the XML plan. userdata and other desired switches. open the filename.xml. Capture your verification plan in Doc XML format. so a Beta license key is needed in order to use the Doc XML annotation flow. Even if you do not see any errors. If there are no errors. 5. This debug check process only needs to be done on newly created or recently edited plans. 4. 2. License Model VMM Planner in C-2009. and copying and pasting Synopsys-defined tables. 3. Fix any errors you see.dbg.xml file and check to make sure that VMM Planner processed your verification plan hierarchy and contents as you intended. You can find more error information in filename. open filename. VMM Planner MS Word Annotation 306 .

hvp annotate Command Arguments Syntax hvp annotate -plan planfile [-h] [-mod hvpfiles] [-plan_out annfile] [-feature "hierarchies"|-featurefile txtfile] [-dir covdbpath|-f txtfile] [-userdata vedata|-userdatafile txtfile] [-userdata_out outvedata] VMM Planner MS Word Annotation 307 . When an XML plan file is specified in -plan planfile. VMM Planner automatically detects the XML file format and invokes the proper process depending on the format of the XML.Supported Platforms linux amd64 suse32 suse64 sparc64 sparcOS5 Compatibility with the VMM Planner Spreadsheet Annotation Flow The VMM Planner Spreadsheet annotator flow and Doc annotator flow share the hvp annotate command and most of its switches. The hvp annotate command is completely backward compatible with the existing VMM Planner Spreadsheet annotator.

xml extension is generated. Multiple scopes can be specified. Filter or override files in HVP language format multiple files can be specified. If -plan_out is not entered.hvp filter.[-metric_prefix prefix] [-group ratio|merge_across_scopes] [-show_ratio] [-show_incomplete] [-v] [-q] Options -plan planfile Spreadsheet. Example: -plan myplan.ann.]" VMM Planner MS Word Annotation 308 . covdb and ve. a file with the original filename and . -feature "hierarchy [hierarchy.. They are applied in the order in which they are entered. This switch is mandatory. **.hvp -mod hvpfiles -plan_out annfile Specify the name for the output annotated spreadsheet or doc XML file. doc XML or HVP file for your verification plan.data are annotated to entire plan. Example: -mod override. Enclose the string with double quotes. Specify HVP scopes that you want to annotate with the given covdb coverage database or ve. Subhierarchies of matched scopes are automatically annotated.xml -h Show this help message and exit.. if -hier is not used. and wildcards (*.data. ?) can be used.

separated by commas.txt -userdata vedata -userdatafile txtfile Specify a text file that contains a list of user database file paths.cm wishbone. separated by commas. Multiple paths can be entered. Dump an annotated score of all measures into the specified outvedata user data file.Example: -feature "myplan. Example: -userdata result. Example: -dir wishbone. Specify a ve. vdb).rec_feat. Multiple paths can be entered.*" -featurefile txtfile A text file that contains list of hierarchical filters.* myplan. Specify the path to a Synopsys coverage database (cm.txt bugcount.data file path.vdb -dir covdbpath -f txtfile Specify a text file that contains list of covdb coverage database paths. The given prefix is used to change a metric name in the output user database file used by -userdata_out.play_feat. -userdata_out outvedata -metric_prefix prefix -group ratio | merge_across_scopes VMM Planner MS Word Annotation 309 .

-show_incomplete -v -q Capturing a Verification Plan in Doc XML Format This section contains the following topics: • • • “Built-In Styles” on page 310 “Table Keyword” on page 314 “Other Contents” on page 319 Built-In Styles In the Doc XML plan template. VMM Planner extracts the contents and their styles to establish the HVP hierarchy. A template document VMM Planner MS Word Annotation 310 .-group ratio: Aggregate the group metric score as a ratio type (covered/coverable) instead of as a percent. Verbose mode: Show progress status messages. -show_ratio Display ratio type scores in a ratio form instead of a percent. there are predefined styles that are prefixed with “HVP”. Quiet mode: Turn off all warning messages. -group merge_across_scopes: Merge the group score across scopes. Indicate incomplete scores with [inc].

containing predefined styles is provided with the VMM Planner Doc annotator. Use this style only once in the plan. Make a copy of that template and then use your copy as a basis to create a new plan. typically at the very top of the document. HVP Plan Style Content with the style “HVP Plan” is assigned as the name of the HVP Plan. VMM Planner MS Word Annotation 311 .

if one exists. You cannot create a plan with more than nine levels of features. If “HVP Feature 2” is found. which means that “HVP Feature 1” can be followed by another “HVP Feature 1” or “HVP Feature 2”. VMM Planner MS Word Annotation 312 . it will be sibling of the previous “HVP Feature 1”. This limited number of styles also limits the number of levels of hierarchical depth in a verification plan. but not by “HVP Feature 3” or “HVP Feature 4”. If “HVP Feature 1” is found. The index must be seamless in terms of hierarchy. for example. which are used to represent HVP feature hierarchy. the feature will be a subfeature of the previous “HVP Feature 1”.HVP Feature 1 to HVP Feature 9 There are nine levels of “HVP Feature” styles.

You can also pass attributes and annotation value overrides the using #() syntax. as shown in the following example. VMM Planner MS Word Annotation 313 .You can also use “HVP Feature number” for subplan declaration. use subplan name-of-plan. which is the same syntax as in the HVP language. To instantiate a subplan. you must add one more feature level to instantiate multiple subplans with the same plan. Since VMM Planner does not allow the same instance name in the same node.

Table Keyword When a table is found. You can also use an “HVP Assignment” table to override description values.HVP Description The paragraph with the “HVP description” style is extracted as the built-in description attribute in the HVP feature. VMM Planner looks at the contents in the first cell of the table. HVP Annotation name” on page 318 “HVP Include File” on page 319 VMM Planner MS Word Annotation 314 . and determines whether the table needs to be interpreted as part of the HVP hierarchy. The following keywords are reserved: • • • • • “HVP Assignment” on page 315 “HVP Measure name” on page 315 “HVP Metric name” on page 317 “HVP Attribute name.

The keyword cell is followed by two-column rows. Otherwise. or the name of a metric to override a goal expression. VMM Planner searches for the names of attributes. VMM Planner generates warnings and ignores the undefined names. All names of attributes.HVP Assignment A table with an “HVP Assignment” style is used to override attributes. then VMM Planner automatically generates a measure name. If no measure name is entered. HVP Measure name The table with the HVP Measure name keyword in the first cell is used to declare HVP measure statements. because Word sometimes capitalizes the first character of a word. annotations or metrics in this table must be defined in the plan. annotations and goals for metrics. HVP Assignment phase owner 2 Snps Note: Although the HVP language is case sensitive. annotations. You can specify a unique measure name or leave it blank. VMM Planner MS Word Annotation 315 . The left cell must have the name of an attribute or annotation to override the value of the name or annotation. and metrics in its definition tables with case-insensitive matching.

The keyword cell is followed by two-column rows.testbench::cpu::cpu_cov. Leave the right cell empty. HVP Measure m1 source Group HVP Measure source source Group HVP Measure source Group Assert group: memsys_test_top. You specify at least one source string. with a metric name in the left cell of each of those rows.my_cpu0 VMM Planner MS Word Annotation 316 . To specify multiple sources. you can list multiple source strings in the same cell separated by commas. or add multiple rows with the source keyword in the left cell of each row. group: memsys_test_top2 group: memsys_test_top group: memsys_test_top2 group instance: memsys_test_top. append one or more two-column rows. The annotation process fills each empty cell with its score. After the source row.

. max. HVP metric bugs type aggregator goal Integer Sum bugs < 3 VMM Planner MS Word Annotation 317 . In the keyword cell. a unique metric name must be specified after HVP Metric (“bugs” in the example table below). real.. ratio. Not all entries are available for all types. The following are rules for creating an HVP metric table: • • One table per one metric definition. average. See “Using the HVP Language” for more information. enum {entry1. Type can be one of: integer. use two-column rows with predefined keywords in the left cell.. Rows for type and aggregator are mandatory. min. Aggregator can be one of: sum. A row for goal is optional. Following the first row.}.HVP Metric name A table with an HVP Metric name keyword in the first cell is used to define an HVP metric. Goal is an expression for the coverage goal. entry2. percent.

Following the first row.HVP Attribute name. percent. use two. a unique name must be specified after the HVP Attribute or HVP Annotation keyword (“phase” in the first example table below. enum {entry1. • Default is the default value of the attribute or annotation. The following are rules for creating an HVP metric table: • • One table per one definition. respectively.. Type can be one of: integer. and “spec” in the second example table). real. ratio. HVP attribute phase type default Integer 1 HVP annotation spec type default String VMM Planner MS Word Annotation 318 . . HVP Annotation name A table with an HVP Attribute name or HVP Annotation name keyword in the first cell is used to define an HVP attribute or annotation.}. two-column rows with predefined keywords type and default in the left cells. In the keyword cell. entry2..

it is difficult to find where the error occurred. and appears in the annotated plan exactly as it appears in the original plan document.doc format.HVP Include File A table with the HVP Include File keyword in the first cell is used to declare other XML plans to be included as subplans. Formatting is limited to the formatting features that are allowed in Microsoft Word 2003 XML . that is neither in a predefined HVP style nor in a table with a predefined keyword. The XML plans that are included in this table can be used as subplans.doc verification plan. and so on. HVP include file sram_wordplan.xml Other Contents All other content such as text.xml dram_wordplan. incorrect styles. In addition. is ignored during the annotation process. You might. not knowing that VMM Planner MS Word Annotation 319 . select the wrong style. VMM Planner might interpret your verification plan in a different way than what you intended or expected due to reasons such as typographic errors. images. Debugging the Doc Plan When an error is detected in a . for example. This is because the paragraph styles are essentially invisible in the normal WYSIWYG view of the document. Add as many one-column rows containing XML filenames as you need. and charts.

there is an error in your HVP file such as a wrongly used style or a typographic error. a blue term enclosed in square brackets. When you run hvp annotate. This section contains the following topics: • • “[Style|Table] Keyword Indicator” on page 320 “Unique Error Code in Error Messages” on page 322 [Style|Table] Keyword Indicator In the filename. If you do not see [Style|Table] where you expect to see it. which provides detailed debugging information. Several examples are shown below.dbg. [Style|Table].dbg.VMM Planner will not recognize the paragraph properly. a filename. indicates that the section was either a predefined HVP style or a predefined HVP table.xml. VMM Planner MS Word Annotation 320 .xml is created for each plan file.

VMM Planner MS Word Annotation 321 .

dbg.ann. How to Get Scores Back-Annotated in the Doc Running hvp annotate. ERR001 is a unique string in the filename.2. Then you can open the original plan and edit it to fix the error.xml.xml file per plan or subplan instance in the HVP hierarchy. then only one filename. filename. you can open the file named memsys_wordplan.xml files.ann.xml and so on. VMM Planner MS Word Annotation 322 .dbg.xml:ERR001: Invalid metric name(Group1) was used in Measure(_m1) in Feature(1. Group 1.ann. If your plan does not include any subplans.xml is produced.ann.Unique Error Code in Error Messages The following error while running hvp annotate indicates that an invalid metric.xml and search for the ERR001 string. was found at the location of ERR001: Error:[DOC_060] memsys_wordplan. so you can easily find the location of the error.xml file. VMM Planner produces one filename. If a plan is used as subplan multiple times. creates one or more filename. cpu1) To find where Group1 was used.2.ann. then VMM Planner produces filename.1.

*.Red indicates that the goal was not met • If no goal was specified: For Synopsys coverage.Red indicates 0% coverage .ann.xml from there. You can open only the top-level plan .ann.xml file and navigate to any subplan .A coverage score between 0 and 100% is indicated by one of six different colors (see the Unified Coverage Reporting User Guide for information about setting the colors) VMM Planner MS Word Annotation 323 .Green indicates 100% coverage . Each score cell in the score summary table is filled in with a color determined by the score and the goal.It is not necessary to open the *ann.xml file to view a subplan. . .Green indicates that the goal was met . The meanings of the colors are: • If a goal was specified. This section contains the following topics: • • • “Plan/Feature Score Summary” on page 323 “Measure Score Table” on page 324 “Navigating Down to a Subplan” on page 325 Plan/Feature Score Summary Running hvp annotate produces a score summary table for each plan or feature.

then the cell contains “N/A”. the score cell is colored using the same scheme as the “Plan/Feature Score Summary”.Green indicates a pass/total ratio of 1 (100%) .For a test metric. VMM Planner MS Word Annotation 324 . Measure Score Table In the measure score table.Red indicates a pass/total ratio of 0 (0%) . If no score is available.A coverage score between 0 and 100% is indicated by one of six different colors (see the Unified Coverage Reporting User Guide for information about setting the colors) Some examples are shown below. .

clicking on a subplan name that uses the HVP Feature style opens the ann.ann.If the –show_incomplete switch is used. VMM Planner MS Word Annotation 325 . appears in front of any source string that does not match any of the regions in the coverage database or user data. “[incomplete]”.xml file. Navigating Down to a Subplan In a filename. Hold down Ctrl and click the subplan name (for example. the name starting with subplan sram_plan in the example below) to open the file.xml file for the subplan instance. in orange.

VMM Planner MS Word Annotation 326 .

12 URG Enhancements This chapter contains the following sections: • • • “New URG Features and Changes” on page 327 “License Model” on page 333 “Platform Support” on page 333 1 New URG Features and Changes The following section contains a summary of each enhancement: • • • “Improved HTML Page Format” on page 328 “Incompleteness Checks” on page 329 “Omitting Filtered Features” on page 330 URG Enhancements 327 .

html pages can be sorted by column.html page. URG Enhancements 328 . Also.• • • • • “Dumping User Data” on page 330 “Predictable Page Naming Convention” on page 331 “Add New Hyperlinks from group bin and group instance” on page 331 “New –show hvpprob Command for Problem Reports” on page 332 “Test Metric Coloring” on page 332 Improved HTML Page Format The hvp*.html page format. which reduces the amount of scrolling necessary to read the report.html page format has been changed to the more compact format used by the hierarchy. the HVP pages are more consistent with other URG data pages. This allows for more information to be displayed per page. With these changes. linear tables on the feature*. Figure 12-1 shows an example of the new hvp*.

URG Enhancements 329 . Other HVP applications that load both the . Use Model The user runs URG and observes warning messages about unbound source statements. the user runs URG again. After fixing the code and the plan.html page format Incompleteness Checks You can bind HVP features to coverage regions via the measure statement of the HVP file. enabling the user to identify and correct those problems.Figure 12-1 hvp*. then determines the cause of the warnings.hvp plan and the coverage database can compare those measure sources against the database and highlight problems where no match is found. This is repeated if there are more incompletness warnings.

URG did not annotate those pruned branches. the user can use the hyperlinks pointing from the feature*. In conjunction with those extended metrics. resulting in visual clutter.html pages to drill down to the raw ve. Dumping User Data HVP allows you to extend the set of metrics measured by the plan. URG Enhancements 330 . allowing you to drill down all the way to the raw data. resulting in a more concise and usable report. That user-defined data is dumped to the HVP report and hyperlinks are inserted from the measure sources to the new raw data report. the user can invoke multiple URG runs. For multiple filtered reports of the same master design. Those filtered features are removed altogether.Omitting Filtered Features A core feature of all HVP applications is the ability to filter out or prune branches of the verification plan. This provides a more complete report. Use Model The user can enter the –mod command line argument to supply a filter modifier. you must also provide text files (userdata) containing the raw data. when such a fliter was applied. Use Model When questions arise about how top level scores are reported. but it still displayed them in the report as null/grey features. Previously.data listings.

URG has been enhanced with a predictable naming convention based on the actual feature hierarchy so that users can translate a feature’s absolute name into a URL. enabling drill-down debug and raw data queries. Use Model To reference HVP results from external documents. A. There was no easy way to know in advance which feature was placed on which page.html and feature123.C.C.The –userdata runtime option specifies user-defined data sources Predictable Page Naming Convention Users may want to directly reference specific hvp* and feature* pages in the URG report from other programs. This feature is exploited in the hvp annotate application allowing MS Word and MS Excel documents to hyperlink to URG reports. you could form a URL like feature named. For example.B. and reference that directly. Previously. those pages had serialized names like hvp1. the metric source types group bin and group instance were not properly hyperlinked to their respective raw data pages. URG Enhancements 331 . the urgReport would contain a file with that name.html.html. the user must know the absolute path in terms of feature names to reach the feature that they seek. Add New Hyperlinks from group bin and group instance Previously. After URG is run. to produce an external document containing the results for feature A. That deficiency has been corrected.B.

A problem is defined as a feature that fails the goals set for one or more of its metrics. If the user overrides the default test metric goal then coloring reverts to the binary red/green cell coloring.html report shows only the problems. it might be helpful to view a report that contains only problems. URG Enhancements 332 . New –show hvpprob Command for Problem Reports When a user has a very large plan that is nearing tapeout.Use Model Hyperlinks can be used to drill down to raw functional coverage information. Test Metric Coloring The built-in test metric is an enum metric type. Use Model When the –show hvpprob option is used. There is an implication that the metric’s default coverage score should be based on a percentage of passes over the total number of tests. This feature computes that percentage and then applies the default red-yellow-green spectrum of colors that are used for other URG metrics. the default hvp*. The -show hvpprob option produces a report that omits all non-problem features.

License Model The –lca command line flag is required to invoke any HVP feature within URG. Platform Support linux amd64 suse32 suse64 sparc64 sparcOS5 aix URG Enhancements 333 .

URG Enhancements 334 .

Syntax run [0] run [-delta] run [-nba] [0] Run Command 347 .12 Run Command This chapter describes the options added in the run command in this release. 1 run Command The run command runs all the simulation time units.

[-delta] Runs one set of deltas at a time and stops before the next delta.Runs all of the deltas of a particular simulation time and stops just before the end of that simulation time. You can inspect values of newly deposited signals/variables at that time. all such events are processed until things stabilizes at the end of current time. The simulation stops after signal update phase. The simulation advances to the next delta and return to UCLI soon after the signal update phase (before process execution). The simulation goes into interactive mode right before the NBA queue starts executing during SemiLER queue execution.. This ensures all deltas (sched0 queues) are executed and all blocking assignments are completed. Run Command 348 . If UCLI generates more events by forces or release etc. This command is useful for delta cycle level debugging especially when it comes to viewing values instantaneously due to forces and values propagation or debugging races. the simulation advances to the next time step and stops at the end of the first delta of the new time step. before process execution for the last delta. [-nba] Runs all deltas and stops before a new NBA (non-blocking assignments). If there are no more events.

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