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Gates and Logic Networks
This section is a review and expansion of the following material covered in Elec 220: The nature of digital signals Behavioral models of gates: Truth Table & Logical Expressions The definition of gate networks. Analysis of gate networks. Simple synthesis of gate networks. A synthesis technique that uses only NAND or NOR gates. An introduction to Verilog and its use in specifying gate network behavior.
Gates and Logic Networks
Most of the concepts covered in this chapter were introduced in Elec 220. Most of the material in this chapter is covered in a little more depth in Chapter 2: Introduction To Logic Circuits of the Brown & Vranesic book. A few of the topics are covered in chapters 3 and 4.
The negative logic system is covered in section 3.4 (pages 82-83)
of Chapter 3 in Brown & Vranesic. The analysis of multi-level logic networks is covered in section 4.7 (pages 184-189) of Chapter 4 in Brown & Vranesic. A technique for synthesizing simple, two-level NAND and NOR networks is given in Chapter 2 of Brown & Vranesic. The notes present the more general technique (for multi-level networks) given in section 4.6.3 (pages 181-184) of the text.
Gates and Logic Networks
2.1. Binary Valued Signals Signal Values
In any physical system, the voltages can, in theory, take on an unlimited number of different values. A physical measuring device can only detect a finite number of voltages on a wire. The actual number is determined by:
Noise (in the circuit and/or the measuring device). The complexity (cost) of the measuring device.
In a digital system the possible voltages on a wire are grouped into a small number (usually two) of ranges and a unique discrete value assigned to each range.
Now we only need to detect which range the voltage is in. More noise can be tolerated. This is much easier to do, if the signal is not too near a boundary
(i.e., less expensive circuits).
Gates and Logic Networks
If a finite number of ranges is good, using only two ranges should be best.
There is only one boundary. Pick a value th called, the threshold, in the middle of all voltages
possible on a wire.
If the observed voltage is > th, we say the signal has one of the two values. If the observed voltage is < th, we say it has the other.
Binary-valued signals don’t really have only two values, we just
treat them as if they did.
Many models are based on this two-valued assumption. The actual symbol we use for the two values is not very important,
what matters is that there are only two.
Common examples: 0 and 1, Low (L) and High (H),True (T)
Gates and Logic Networks
How do we represent a large number of values with only two values and what is the tradeoff involved?
Use several signals: n signals can represent 2n values. This can increase the cost and complexity enormously. VLSI to the rescue.
It is easier to deal with binary-valued signals if we keep the voltage away from the single threshold.
1 Unstable 0 VL Vmin Vmax VH
If the observed voltage is > VH, call it a 1, High or True. If the observed voltage is < VL call it a 0, Low or False. For TTL, a 1 is anything over 2v and a 0 is anything under 0.8v.
Gates and Logic Networks
6 Gates and Logic Networks . Elec 326 2. Logic Conventions The use of 0 (F) and 1(T) must be associated with the H and L voltages. If 1(T) is assigned to H and 0(F) to L we say we are using the positive logic convention. It does not matter which way it is done. In this course we will use the positive logic convention unless explicitly indicated otherwise. If 0(F) is assigned to H and 1(T) to L we say we are using the negative logic convention.
Noise can alter the voltage on the wire by ±0. Elec 326 2. Circuits that use this signal can only determine voltage values to one digit of accuracy.05v. Determine the number of possible discrete signal values and determine the voltage range associated with each of them. it will round the actual voltage to the nearest integer. so that any actual voltage between 2.5v will be perceived as 3v. That is. Exercise: The signal on a wire can vary between 0 and 10 volts.5v and 3.7 Gates and Logic Networks .
Gates Gate: A simple electronic circuit (a system) that realizes a logical operation.2. The direction of information flow is from the input terminals to the output terminal.Y) Elec 326 2.2. X Y Gate Z = f(X. The transformation of input signals to output signals can be modeled as a logical operation.e. The number of input and output terminals is finite and they carry binary-valued signals (i. 0 and 1).8 Gates and Logic Networks .
Elec 326 2. we can represent the behavior of a gate by simply listing all of it possible input configurations and the corresponding output signal. Such a list is called a truth table. the following gate could have the behavior given by the following truth tables. X Y GATE Z X L L H H Y L H L H Z L H H H X 0 0 1 1 Y 0 1 0 1 Z 0 1 1 1 X 1 1 0 0 Y 1 0 1 0 Z 1 0 0 0 The use of the symbols L and H usually correlates with the high and low voltages. For example. Truth Tables Since there is a finite number of input signal combinations.9 Gates and Logic Networks .
Buffer X Z 0 1 1 0 b. AND Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 d. Exclusive OR Gate X Y Z 0 0 1 0 1 0 1 0 0 1 1 1 h. OR Gate X Y or X Y Z X Y or Z X Y Z X Y Z Z X Y Z X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 e.10 Gates and Logic Networks . Some standard gates and their symbols and truth tables: X X Z X Z Y Z X Y Z X Z 0 0 1 1 a. NAND Gate f. Equivalence Gate Elec 326 2. X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 NOR Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 g. Inverter X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 c.
Gates with more than 3 inputs: AND gates: The output is 1 if and only if … ? OR gates: The output is 1 if and only if … ? NAND gates: The output is 0 if and only if … ? NOR gates: The output is 0 if and only if … ? EXCLUSIVE OR gates: The output is 1 if and only if … ? EQUIVALENCE gates: The output is 1 if and only if … ? Elec 326 2.11 Gates and Logic Networks .
C is 1 iff It is not the case that either A or B is 1. C is 1 iff Both A and B are 1 or both A and B are 0.12 Gates and Logic Networks . Logical Expressions We can also represent the behavior of gates with a logical expressions constructed from variables and logical operations symbols. NEGATION AND OR EXCLUSIVE OR NAND NOR EQUIVALENCE Elec 326 2. The following table gives the most common ones. C is 1 iff A is 1 and B is 1. C is 1 iff A is 1 or B is 1. C is 1 iff A or B is 1. C is 1 iff It is not the case that A and B are both 1. Connective Example C = A' C = A•B C = A+B C = A⊕B C = A↑B C = A↓B C = A≡B Meaning C is 1 iff A is 0. both not both.
There are several different symbols that have been used for the logical connectives. Comments on the logical symbols The NAND and NOR symbols are not very useful. Exercise: Determine how many different two-input gates there can be? How many three-input gates? N 2 3 4 5 6 2n 16 256 65.84 x 1019 Elec 326 2.396 1. 294.536 4.967.13 Gates and Logic Networks .
network input terminals. and network output terminals with the following restrictions: No gate output terminal or network input terminal is connected to another gate output terminal or network input terminal. A Example Network Input Terminals X B Y C Elec 326 2. a network input terminal. Gate Networks A gate network is a finite collection of interconnected gates.2.3. or a gate output terminal.14 Gates and Logic Networks Network Output Terminals . Every network output terminal or gate input terminal is wired (via one or more wires) to a constant value.
A gate network that is not combinational is called a sequential gate network. Sequential networks have loops. Types of networks A combinational gate network is one in which the values of the signals present on its input terminals uniquely determine the signal values at its output terminals. since we can describe its behavior with a logical expression. We call a gate network without loops a logic network. Combinational networks may have loops. does not pass any wire or gate more than once. and terminates back at the starting gate terminal. Elec 326 2.15 Gates and Logic Networks . passes along wires and through gates. A loop in a gate network is a path that starts at a gate terminal. Loop Networks without loops are combinational.
16 Gates and Logic Networks . Exercise: Which of the following networks are combinational and which are sequential? Net 1 Net 2 Net 3 Net 4 Elec 326 2.
Elec 326 2. find a truth table that describes its behavior.17 Gates and Logic Networks Analysis . Design a logic network to have the behavior specified by a given set of logical expressions. Transform a logical expression into an equivalent (and possibly simpler) logical expression. Analysis & Synthesis of Logic Networks Overview Synthesis 7 Truth Table 1 4 3 Logic Network 2 6 Logical Expression 5 1. For a given logic network. 5. 7. Design a logic network to have the behavior specified by a given truth table.2. Transform a truth table into an equivalent logical expression representation. 3. 4. 2. find a set of logical expressions that describes its behavior. 6. For a given logic network.4. Transform a logical expression into the equivalent truth table representation.
18 X Y 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 Gates and Logic Networks Elec 326 . Analysis of Logic Networks Logic Network A B 1 2 3 Z1 4 Z2 Z3 5 Z4 6 X Y C Truth Table Behavioral Description ABC 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Z1 Z2 Z3 Z4 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 2.
Logical Expression Behavioral Description A B 1 2 3 Z1 4 Z2 Z3 5 Z4 6 X Y C X = Z4' X = (Z1+Z2)' X = ((A•B)'+(A⊕B))' Y = Z2•Z3•Z4 Y = (A ⊕B)•(A•C)•(Z1+Z2) Y = (A ⊕B)•(A•C)•((A•B)'+(A ⊕B)) Elec 326 2.19 Gates and Logic Networks .
Elec 326 2.20 Gates and Logic Networks . but very different structurally. The logical expressions for X and Y are also equivalent. Example ABC 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 X 0 0 0 0 0 0 1 1 Y 0 0 0 0 0 1 0 0 A B X C Y X = A•B Y = A•B'•C The networks in these two examples are equivalent because they have the same truth table.
6. 3. Example ABC 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 X 0 0 0 0 0 0 1 1 Y 0 0 0 0 0 1 0 0 List of 1’s: X = Σ A. 1. 5) Y = Π A.. B. 4. Notation: We can represent a truth table by simply listing the indices of the rows that have value 1 or listing those that have value 0. 3. in homework problems). 7) The value of this notation is that it is a more compact way of specifying a logical function than writing the truth table.21 Gates and Logic Networks Elec 326 .g. 4.B. 2.C (6.B.B. 1.C (0. 7) Y = Σ A. It is useful for specifying a function to be designed (e.C (5) List of 0’s: X = ΠA. C (0. 2. 2.
Synthesis of Logic Networks Example Z = (A ⊕ B) + ((C + D)•B') A B B C D (A⊕B) + ((C+D)•B') Z A⊕B Z (C+D)•B' A B C D A B C D C+D B' A B C D B Z Z + ⊕ A B C B • + ' D B Elec 326 2.22 Gates and Logic Networks .
23 Second Simplification Gates and Logic Networks . Example X = ((Α ⊕ B) + C)' Y = (B•C + D)'•E Z = (A + D) + (B•C) A B C X D E Y Z Original Network A B C D E X A B C D E X Y Z Y Z First Simplification Elec 326 2.
24 Y Gates and Logic Networks . Two level gate networks and logical expressions Sum-of-Products (SOP) logical expressions A•B + A•C’ + B•C’•A + C Two level AND-OR Networks A B C Y Product-of-Sums (POS) logical expressions (A+B’)•(B+C’)•A Two level OR-AND Networks A B C Elec 326 2.
25 Gates and Logic Networks .5. OR and NOT gates. Then Transform it to an equivalent network of NAND or NOR gates. Approach: First design the network with AND. A B A B (A•B)' (A + B)' A B A B A' + B' A' • B' Elec 326 2.2. The following alternative NAND and NOR symbols are useful for this. NAND/NOR Networks This topic deals with designing combinational logic networks using only NAND or NOR gates.
One approach is to replace AND and OR gates by the following equivalent NAND or NOR circuits: A B A•B A B A+B NAND: A B A•B A B A+B NOR: A B A•B A B A+B NAND Network Example: A' C' B D A D A' 4 2 5 3 1 Z 4 2 5 3 1 Z C' B D A D AND-OR Network NAND Network Elec 326 2.26 Gates and Logic Networks .
27 Gates and Logic Networks . NOR Network Example A B C D E' AND-OR Network Z A B C D E' Z NOR Network Elec 326 2.
Algorithm 1: (Converts network N1 of inverters. c) Replace all INVERTERS in the diagram of N1 by a direct connection. or (3) from a gate output terminal to a network output terminal. Step 2. odd or even) as the corresponding path in the original network N1.e. Elec 326 2. (2) from a network input terminal to a gate input. NAND gates.28 Gates and Logic Networks . AND gates.. and NOR gates into network N2 containing only NAND Gates) Step 1. a) Replace each AND gate symbol in the diagram of N1 by the symbol for a NAND gate. b) Insert enough INVERTERS in each of these connecting paths so that the number of inversion bubbles on gate inputs or outputs has the same parity (i. OR gates. b) Replace each OR gate or NOR gate symbol in the diagram of N1 by the symbol for a NAND gate. a) Consider each connection (1) from a gate output to a gate input. in the network produced by Step 1.
OR gates. AND gates. Elec 326 2. Algorithm 2: (Converts network N1 of inverters. Same as for Algorithm 1. and NOR gates into network N2 containing only NOR Gates) Step 1. NAND gates. Step 2.29 Gates and Logic Networks . c) Replace all INVERTERS in the diagram of N1 by a direct connection. a) Replace each OR gate symbol in the diagram of N1 by the symbol for a NOR gate. b) Replace each AND gate or NAND gate symbol in the diagram of N1 by the symbol for a NOR gate. Networks with NANDs and NORs The first steps of these previous two algorithms can be easily combined to get an algorithm that produces a network containing both NAND and NOR gates.
Example of Transformation to a NAND Network: A 1 3 B C 2 5 4 6 Z Original Network N1 A B C 1 2 3 4 5 6 Z Intermediate Network After Step 1 A 1 3 4 6 5 Z B C 2 NAND Network N2 Elec 326 2.30 Gates and Logic Networks .
31 Gates and Logic Networks . Example of Transformation to a NAND and a NOR Network: A B C D Z Original Network N1 A B C D Z NAND Network N2 A B C D Z NOR Network N2 Elec 326 2.
Exercise: Derive logical expressions. using only the logical operations • . for the following two networks. A B C D E X Net 1 A B C D E X Net 2 Elec 326 2.32 Gates and Logic Networks . + and '.
33 Gates and Logic Networks . While HDL’s have been around for 30 years. before the implementation details of the systems are developed. Languages such as this are called Hardware Description Languages or HDL’s. An Introduction to Verilog Verilog is a programming language that was developed for describing the behavior and structure of digital systems. Why? Elec 326 2.6. Verilog is an IEEE standard and widely used today. it has only been with the advent of large integrated circuits that they have become popular with digital designers. Verilog is probably most useful for describing systems at a high-level of abstraction.2.
Verilog programs used for generating test patterns are called test benches or test fixtures. When this is possible. Elec 326 2.34 Gates and Logic Networks . Verification of functional behavior Timing analysis Verilog can also be used to specify test patterns for testing Verilog simulation models. Verilog is also used to specify the input to synthesis tools that produce implementations automatically. the designer need not use the classical design techniques. Verilog Uses Verilog can be viewed as a simulation modeling language Enables digital designers to simulate and verify the behavior of their systems before they design a detailed implementation.
Modules have other statements used to define how it transforms the input signals to output signals. Verilog Modules An elementary Verilog program is called a module. Elec 326 2. A module corresponds to a digital circuit. Modules have input and output ports that correspond to the input and output terminals of a digital circuit. They need not give any indication of the structure of the circuit.35 Gates and Logic Networks . Verilog modules can be used to specify the structure or the behavior of a digital circuit. The ports and variables used to represent internal signals are declared at the beginning of the program. Behavior modules specify the output signals as functions of the input signals. Structural modules consist of a list of component modules (defined elsewhere) and a list of wires used to interconnect the modules.
assign Y = ~((B & C) | D) & E. C. Z. Y. Example of a behavioral Verilog module Circuit: E D C B A X Y Z Verilog module: module circuit1b (A. assign X = ~((A ^ B) | C). output X. D. D. B. X. endmodule Elec 326 2. Z). assign Z = A | D | (B & C). C. E. E. B.36 Gates and Logic Networks . input A. Y.
Note that ports must be listed in the module statement (first line) and their direction (input or output) declared in the following statements. Individual signals (e. “out”. B. Comments on the module Case matters in Verilog statements.g. the user has not specified a value for an input signal). A.g.. … in the previous example) can take any of the following four values: 0 = logic value 0 1 = logic value 1 z = tri-state (high impedance) x = unknown value The unknown value is used by simulators to indicate that they do not know how to determine a signals value (e. The tri-state value means that no signal is assigned to the variable..37 Gates and Logic Networks . The symbol string “Out”. and “OUT” represent three different variables. Elec 326 2.
where conventional programming languages are said to be procedural.e.38 Gates and Logic Networks . Elec 326 2. This is necessary to represent timing characteristics of hardware systems. has new data for the variables on its right side) There is no concept of "locus of control" or “program counter” that determines the next instruction to execute. This method of interpreting the execution of assign statements is quite different from that use in conventional programming languages in the following ways: Two or more assignments can execute simultaneously.. the order the assignments are written does not matter This method of assignment statement execution is sometimes called non-procedural or data-driven execution. An assignment executes whenever it is ready (i. The right side of an assign statement is evaluated and its resulting value assigned to the signal on the left side whenever one of the signals used in the right side changes value. Therefore. This type of assignment is also called a continuous assignment. The three assign statements are independent and can execute in any order or concurrently.
Each gate is specified by its name (e.g. and. All gates have a single output and it is always listed first in this list.g. These wire declarations could be omitted as long as the component modules are simple gates. or..39 Gates and Logic Networks . Behavioral vs. Verilog will assume that any gate output signal that is not declared is of type wire. It is also possible to specify a structural description in Verilog that specifies explicitly how a set of smaller components (e.. …) and a list of ports or wires connected to its terminals. gates) are interconnected to form a larger system as shown on the following slide. Elec 326 2. Note that the internal connections from gate outputs to gate inputs are declared to be of type wire. Structural Verilog Descriptions The previous example is a behavioral descriptions because it specifies the logical values of the circuit's outputs as logical equations with no reference to how the gates in a possible implementation might be interconnected.
or(Z. Z). wire T1. T3. Z. D. A. or(T2. and(T3. E. X. E). T4. and(Y. C. C). B. B. T4). B. T5. or(T6. T6. output X. D). B. Y. D). T7. C). or(T4. T3. not(X. endmodule E D C B A T1 T3 T2 T5 X T4 Y T6 T7 Z Elec 326 2.module circuit1s (A. T1. A.40 Gates and Logic Networks . and(T7. T6. C). T7). T5. C. not(T5. Y. B). T2). E. xor(T1. T2. input A. D.
Elec 326 2.41 Gates and Logic Networks . The always block acts like a generalized assign statement where the action that takes place can be specified by sequential code. and the goes back to sleep. in the order they are written)..e. executes its procedural statements. always @(sensitivity_list) begin procedural statements end The sensitivity list is a list of signals separated by or. the always block wakes up. When any one of the signals in the sensitivity list changes value. Always Blocks A procedural block is a construct that contains statements that are executed procedurally (i.
always @(x or y) begin s = x ^ y. Example module always_example(x.42 Gates and Logic Networks . input x. y. end endmodule Elec 326 2. z = x & s. z). y. output z. s. reg z.
the statement z = x & s executes using the new value of s that it received when the first statement was executed. It is said that the assigned value is registered in the variable Whenever x or y changes value. The main advantage of using always blocks to represent combinational circuits is that you can use control statements such as “if then else” as illustrated by the following example Elec 326 2. the always block is executed as follows: First. Variables on the left side of a procedural statement must be declared as type reg. the statement s = x^y executes and registers a new value in s Next. Variables declared as type reg hold their value until they are assigned a new value.43 Gates and Logic Networks . Then the blocks stops executing and waits for either x or y to change again.
input x1. s. Elec 326 2. s. y). x2. s. endmodule module mux2 (x1. always @(x1 or x2 or s) if (s == 1) y = x1.module mux1 (x1. input x1. output y. reg y. x2.44 Gates and Logic Networks . The control statements used in always blocks will be covered in more detail in later chapters. s. output y. x2. x2. assign y = (s & x1) | (~s & x2). y). else y = x2. endmodule Modules mux1 and mux2 do exactly the same thing.
y. always @(x or y or z) begin s = x ^ y. Exercise: Explain how the behaviors of the following two modules differ. output f. y. output f.45 Gates and Logic Networks Elec 326 . end endmodule module assign_example (x. input x. endmodule How would the behavior of each of these modules change if the order of the two assignment statements is reversed? 2. z. f). f). input x. f = z & s. y. module always_example(x. z. y. assign f = z & s. assign s = x ^ y. reg f. wire s. z. z. s.
46 Gates and Logic Networks . wire and input signals that appear on the right side of an assignment statement within the always block must appear in the sensitivity list We call a sensitivity list that satisfies this condition a complete sensitivity list. a rising edge or falling edge). Elec 326 2. All signals in the sensitivity list must appear without edge specifiers All output signals must be assigned a value every time the always block executes These conditions guarantee that the input signals uniquely determine the output signals. so it does it for you.. Some Verilog synthesizers (Including the one in the Xilinx ISE) assume that if you omit one or more of the signals in the sensitivity list. It is recommended that you use this notation for combinational always blocks.g. Edge specifiers indicate that a signal is asserted by a change in value as opposed to its level (e. that you really meant to put them in. They are introduced and utilized in later chapters on sequential circuits. However. Conditions for combinational behavior of always blocks The following conditions are necessary for an always block to represent combinational logic (as opposed to sequential logic) All reg. A sensitivity list of the form @(*) is shorthand for a complete list. which is the very definition of a combinational circuit. it will issue a warning message in this case.
The easiest way to do this is to replace @(a. b) if (a==1) f = b.47 Gates and Logic Networks Elec 326 . this represents a sequential circuit. c. endmodule The input c is missing from the sensitivity list According to the semantics of Verilog. input a. f). else f = c. always @(a.b) by @(*). b. 2. It is better to always use complete sensitivity lists. Example (Incomplete sensitivity list) module example1(a. b. output f. so a circuit it synthesizes from this module will be combinational. Why? Xilinx ISE will assume you meant to put c in the sensitivity list and add it for you. c. reg f.
b. It corresponds to a path from the input node to the output node of a flow chart of the block. and c. endmodule If a is 0 and b or c changes value. b. so f is not uniquely determined by the static values of a. c. the always block executes but does not execute an assignment to f. Xilinx ISE will synthesize this module as a sequential circuit. output f. c. input a. b. Elec 326 2. module example2(a. Example (Missing output signal in a control path) A control path is a sequence of operations (possibly null) that can be performed by an always block. f).48 Gates and Logic Networks . always @(*) if (a==1) f = b&c. reg f.
A two-level NOR-NOR network is equivalent to a two-level OR-AND network and both realize Product-of-Sums logical expressions. Be aware that you can make an inverter from an Exclusive OR Use the alternative NAND/NOR symbols to emphasize the logical functions of the gates.9. Tips and Tricks Think of the bubbles on gates as inverters Thus is equivalent to Think of Exclusive Or and Equivalence as a parity circuits that produce a 1 out if the number of 1's in is odd or even respectively.2. A two-level NAND-NAND network is equivalent to a twolevel AND-OR network and both realize Sum-of-Product logical expressions.49 Gates and Logic Networks . Elec 326 2.
2. they are not wrong. Again. Forgetting that “assign” statements in Verilog are executed in parallel and are “data-driven. but it can make logic diagram more difficult to read and lead to errors.50 Gates and Logic Networks .10. Pitfalls Not realizing that is a NAND gate or is a NOR gate and not using them where appropriate. Not using them is not logically incorrect. just not very useful. Elec 326 2. Using the ↑ and ↓ for NAND and NOR Forgetting that case matters in Verilog names.” Forgetting to use complete sensitivity lists or missing output signals in control paths.
11. The relationship between combination networks. The use of Verilog to specify the behavior or structure of simple combination logic networks Elec 326 2. What are the advantage of binary-valued signals? The relationship between logical networks. and unstable).51 Gates and Logic Networks . The alternative NAND and NOR symbols. logical expressions and truth tables. 1. Review The nature of binary-valued signals and how they relate to continuous measured signal values (the 3 ranges of 0. sequential networks and loops in networks.2.
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