DL121/D Rev.

6, Jan-2000

LS TTL Data
ON Semiconductor
Formerly a Division of Motorola

LS TTL Data
Formerly Titled “FAST and LS TTL Data”

Please Note: As ON Semiconductor has exited the FAST TTL business, all FAST data sheets have been removed from this publication. For further assistance, please contact your local ON Semiconductor representative.

DL121/D Rev. 6, Jan–2000

© SCILLC, 2000 Previous Edition © 1992 “All Rights Reserved’’

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CONTENTS
Page CHAPTER 1 — SELECTION INFORMATION, LS TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 CHAPTER 2 — CIRCUIT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Family Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LS TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Circuit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LS ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CHAPTER 3 — DESIGN CONSIDERATIONS, TESTING AND APPLICATIONS ASSISTANCE FORM . . . . . . DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan-In and Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wired-OR Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnection Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEFINITION OF SYMBOLS AND TERMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Switching Parameters and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATIONS ASSISTANCE FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 16 16 18 18 18 18 19 19 20 21 21 21 22 24 24 25 27

CHAPTER 4 — DATA SHEETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CHAPTER 5 — RELIABILITY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 “RAP” Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 CHAPTER 6 — PACKAGE INFORMATION INCLUDING SURFACE MOUNT . . . . . . . . . . . . . . . . . . . . . . . . . . Surface Mount Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape and Reel Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 265 266 267 269 270

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Device SN74LS00 SN74LS04 SN74LS05 SN74LS08 SN74LS14 SN74LS32 SN74LS38 SN74LS42 SN74LS47 SN74LS74A SN74LS76A SN74LS85 SN74LS86 SN74LS109A SN74LS122 SN74LS125A SN74LS132 SN74LS138 SN74LS139 SN74LS145 SN74LS147 SN74LS151 SN74LS153 SN74LS156 SN74LS157 SN74LS161A SN74LS164 SN74LS165 SN74LS166 SN74LS174 SN74LS175 SN74LS193 SN74LS194A SN74LS195A SN74LS221 SN74LS240 SN74LS245 SN74LS247 SN74LS251 SN74LS253 SN74LS257B SN74LS259 SN74LS260 SN74LS273 SN74LS280 SN74LS283 SN74LS298 SN74LS299 SN74LS365A SN74LS373 SN74LS377 SN74LS393 SN74LS541 SN74LS640 SN74LS670 SN74LS682

Description Quad 2-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schmitt Triggers Dual Gate/Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . One-of-Ten Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual D–Type Positive Edge–Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual JK Flip-Flop with Set and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2–Input Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual JK Positive Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retriggerable Monostable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 3-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Schmitt Trigger NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 1-of-4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-of-10 Decoder/Driver Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-Line–to–4–Line and 8-Line–to–3–Line Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 1-of-4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD Decade Counters/4–Bit Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-In Parallel–Out Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Parallel-To-Serial Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Presettable 4–Bit Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Bidirectional Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal 4-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual Monostable Multivibrators with Schmitt–Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer/Line Driver with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCD–to–Seven–Segment Decoders/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Input Multiplexer with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Input Multiplexer with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 5-Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal D Flip-Flop with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-Bit Odd/Even Parity Generators/Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Binary Full Adder with Fast Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad 2-Input Multiplexer with Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Shift/Storage Register with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-State Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output Octal D Flip-Flop with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual 4-Stage Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Buffer/Line Driver with 3–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 Register File with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit Magnitude Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . http://onsemi.com
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com 5 .CHAPTER 1 Selection Information LS TTL http://onsemi.

with equal or better TTL Family Comparisons General Characteristics for Schottky TTL Logic (All Maximum Ratings) Characteristic Operating Voltage Range Operating Temperature Range Input Current IIN Output Drive Standard Output IOH IOL ISC IOH Buffer Output IOL ISC Symbol VCC TA IIH IIL 74LSxxx 5 ± 5% 0 to 70 20 – 400 – 0. NOTES: 1. LCX or VCX running at 3. The VHC family is faster and lower power with similar drive characteristics compared to LSTTL. http://onsemi. Specifications are shown for the following conditions: NOTES: 1.0 18 33 40 Unit mA mW ns pJ MHz MHz NOTES: 1. Low Power Schottky (LSTTL) was the industry standard logic family for many years. to Schottky-Clamped logic.0 Volt designs. low cost. NOTES: 1. Improvements in electrostatic discharge susceptibility in these newer CMOS products now make them the obviate the need for LSTTL in new designs.GENERAL INFORMATION TTL in Perspective Since its introduction. The popularity of these TTL families stem from their ease of use. medium-to-high speed operation.4 2. Since its inception.0 Vdc (AC). We therefore recommend the VHC. b) TA = 25°C.0 – 20 to – 100 – 15 24 – 40 to – 225 Unit Vdc °C µA mA mA mA mA mA mA performance. a) VCC = 5.com 6 .4 8. Speed/Power Characteristics for Schottky TTL Logic(1) (All Typical Ratings) Characteristic Quiescent Supply Current/Gate Power/Gate (Quiescent) Propagation Delay Speed Power Product Clock Frequency (D-F/F) Clock Frequency (Counter) Symbol IG PG tp — fmax fmax Typ 0. and good output drive capability. It has evolved from the original gold-doped saturated 7400 logic. TTL has become the most popular form of digital logic. We highly recommend new designs use one or more of these CMOS families.3 Volts. c) CL = 15 pF. several more modern families have come out. and finally to the modern advanced families of TTL logic. High Speed and FACT products for all new 5. Further improvements in power reduction can be achieved using the LVX.0 9.

86 1-of-8 1-of-10 Latches Description No. 373 259 Schmitt Triggers Description Hex. CP. Non-Inverting Quad 2-to-1. 139 156 138 42 Exclusive OR Gates Description Quad 2-Input Type of Output 2S No. Inverting Quad 2-Input NAND Gate Type of Output 2S 2S No. 14 132 Transparent. K. 32 Description 4x4 Type of Output 3S No. CD Inputs Dual JK w/Set & Clear Clock Edge Pos Neg Pos No. 04 05 Multiplexers Description Quad 2-to-1. 260 Description Dual 1-of-4 Type of Output 2S OC 2S 2S No. Non-Inverting Type of Output 2S No. 157 257B 258B 153 253 151 251 298 AND Gates Description Quad 2-Input NAND Gates Description Quad 2-Input Type of Output 2S No. 08 8-to-1 Type of Output 2S 3S 3S 2S 3S 2S 3S 2S No. SD. 00 Encoders Description 10-to-4-Line BCD 8-to-3-Line Priority Encoder Type of Output 2S 2S No.Functional Selection Abbreviations S A B = Synchronous = Asynchronous = Both Synchronous and Asynchronous 2S = 2-State Output 3S = 3-State Output OC = Open-Collector Output Inverters Description Hex Type of Output 2S OC No. 147 148 OR Gates Description Quad 2-Input Type of Output 2S Register Files No. of Bits 8 8 Type of Output 3S 2S No. Inverting Dual 4-to-1. Non-Inverting Addressable SSI Flip-Flops Description Dual D w/Set & Clear Dual JK w/Set & Clear Individual J.com 7 . 74A 76A 109A http://onsemi. 670 NOR Gates Description Dual 5-Input Type of Output 2S Decoders/Demultiplexers No.

Non-Inverting No. 245 641 640 642 VCOs and Multivibrators Description Retriggerable Monostable Multivibrator Dual 122 Precision Non-Retriggerable Monostable Multivibrator No. 377 174 273 374 175 D-Type.Shift Registers No. 145* 247* MSI Flip-Flops/Registers Description D-Type. 283 Buffers/Line Drivers Description Quad 2-Input NAND Quad. 122 123 221 http://onsemi. of Bits 8 8 8 4 4 8 Type of Output 2S 2S 2S 2S 2S 3S Mode* SR X X X X X X SL Hold X X X X Reset A A A A A No. Bidirectional * SR = Shift Right * SL = Shift Left X X Asynchronous Counters — Negative Edge-Triggered Description Dual 4-Bit Binary * The 716 and 718 are positive edge-triggered. Inverting Octal. 161A 163A Display Decoders/Drivers with Open-Collector Outputs Description 1-of-10 BCD-to-7 Segment No. Inverting 3S 3S 3S Type of Output OC 3S 3S No. Non-Inverting P=Q X X X X P>Q X X X P<Q X No.com 8 . Non-Inverting Octal. Q and Q Outputs Arithmetic Operators Description 4-Bit Adder No. 85 682 684 688 Hex. 38 125A 126A 365A 367A 368A 244 541 240 Magnitude Comparators Description 4-Bit 8-Bit 8-Bit with Output Enable Type of Output 2S 2S 2S 2S Transceivers Parity Generators/Checkers Description 9-Bit Odd Even Parity Generator Checker No. Load Set Reset X No. Non-Inverting Hex. 393* Cascadable Synchronous Counters — Positive Edge-Triggered Description 4-Bit Binary Type of Output 2S 2S Load S S Reset A S No. Non-Inverting Bus Pinout Octal. of Bits 4 6 8 8 4 Type of Output 2S 2S 2S 3S 2S Set or Reset A A A Clock Enable X No. 280 Description Octal. 164 165 166 194A 195A 299 Description Serial In-Parallel Out Parallel In-Serial Out Parallel In-Parallel Out Parallel In-Parallel Out. Inverting Type of Output 3S OC 3S OC No.

com 9 .CHAPTER 2 Circuit Characteristics http://onsemi.

8K Q1 Q5 3.com 10 . Circuit features of the LS are best understood by examining the TTL 2-input NAND gate (Figure 1). For applications where high drive is required.CIRCUIT CHARACTERISTICS FAMILY CHARACTERISTICS LS TTL CIRCUIT FEATURES The Low Power Schottky (LS TTL) family combines a current and power reduction improvement over standard 7400 TTL by a factor of 5. more modern products such as VHC should be replacing LSTTL in new designs.5K Q3 OUTPUT Figure 1. This is accomplished by using Schottky diode clamping to prevent saturation and advanced processing. LS00 — 2-Input NAND Gate http://onsemi.6K Q2 Q4 5K B D2 D4 15K 2. While LS has been a popular series in the past. 110 Ω VCC 18K A D1 D3 7. FACT is an ideal choice.

All inputs are provided with clamping diodes.6 1.5 1.8 1.8 1 1. Both the diode cluster arrangement and the PNP input configuration have breakdown voltage ratings greater than 7.5 VIN.0 V and the input breakdown voltage is typically 15 V or more.5 1 1.1 0. Most LS elements use a DTL type input circuit with Schottky diodes to perform the AND function. exemplified by D1 and D2 in Figure 1. Compared to the classical multi-emitter structure. These diodes conduct when an input signal goes negative.4 0.0 + 125°C 1. which in turn can steal current from internal nodes of an LS circuit and thus cause logic errors. Another input arrangement often used in LS MSI has three diodes connected as shown in Figure 2.8 http://onsemi.3 1. PNP Input Figure 4 shows the typical input characteristics of LS.2 0. this circuit is faster and increases the input breakdown voltage. Typical Input Current versus Input Voltage Figure 5. as exemplified by D3 and D4 in Figure 1.com 11 . OUTPUT VOLTAGE (VOLTS) 0 –100 LS I IN ( µA) –200 –300 –400 TA = 25°C VCC = 5 V 0 0.INPUT CONFIGURATION ON Semiconductor LSTTL circuits do not use the multi-emitter input structure that originally gave TTL its name. Typical Output versus Input Voltage Characteristic Table 1. Diode Cluster Input INPUT CHARACTERISTICS Figure 3.0 mA and with a duration greater than 500 ns can activate a parasitic lateral NPN transistor. This arrangement also gives a higher input threshold and has VCC the additional advantage of reducing the amount of current that the signal source must sink. 5 V OUT . This configuration gives a slightly higher input threshold than that of Figure 1.5 1. VCC Figure 2.4 1. A third input configuration that is sometimes used in LS TTL employs a vertical PNP transistor as shown in Figure 3.0 V. which limits undershoot and helps to control ringing on long signal lines following a HIGH-to-LOW transition. INPUT VOLTAGE (VOLTS) 2 2.8 2 4 TA = 25°C VCC = 5 V 3 LS 2 1 0 0.2 + 25°C 1.6 0.2 VIN (VOLTS) 1. These diodes are intended only for the suppression of transient currents and should not be used as steady-state clamps in interface applications. Typical Input Threshold Variation with Temperature – 55°C ALS S LS 1.5 Figure 4. Inputs of this type are tested for leakage with an applied input voltage of 7.3 1. A clamp current exceeding 2. Typical transfer characteristics can be found in Figure 5 and input threshold variation with temperature information is provided in Table 1.

the base of the pull-down output transistor Q5 is returned to ground through Q3 and a pair of resistors instead of through a simple resistor. which allows the outputs of two or more such circuits to be connected together in a bus application wherein only one output is enabled at any particular time. In this condition the output circuitry is non-conducting. Referring to Figure 1.OUTPUT CONFIGURATION The output circuitry of LSTTL has several features not found in conventional TTL.com 12 .5 0. This configuration allows the output to pull up to one VBE below VCC for low values of output current. both the phase splitter and the Darlington pull-up are turned off. OUTPUT VOLTAGE (VOLTS) TA = 25°C VCC = 4. OUTPUT CURRENT (mA) Figure 7.5 V 0. For LOW IOL values. Typical 3-State Output Control OUTPUT CHARACTERISTICS Figure 7 shows the LOW-state output characteristics for LS. (a) Output Low Characteristic Figure 7. A few of these features are discussed below. The output pull-up circuit is a 2-transistor Darlington circuit with the base of the output transistor returned through a 5. The squaring network also improves the propagation delay by providing a low resistance path to discharge capacitance at the base of Q5 during turn-off. This arrangement is called a squaring network since it squares up the transfer characteristics (Figure 5) by preventing conduction in the phase splitter Q1 until the input voltage rises high enough to allow Q1 to supply base current to Q5.5 0 0 20 40 IOL. When the Output Enable signal is HIGH.0K resistor to the output terminals. Figure 6 shows the extra circuitry used to obtain the “high Z” condition in 3-state outputs. Figure 8 shows the HIGH-state output characteristics. (b) Output Low Characteristic http://onsemi. 1 V OL . VCC OUTPUT FROM LOGIC OUTPUT ENABLE ACTIVE PULLDOWN Q5 Figure 6. unlike 74H and 74S where it is returned to ground which is a more power consuming configuration. OUTPUT CURRENT (mA) 60 0 50 100 150 200 IOL.5 V LS00 clamped out of deep saturation to shorten the turn-off delay. the pull-down transistor is 1 V OL . OUTPUT VOLTAGE (VOLTS) LS240 TA = 25°C VCC = 4.

and CL = 15 pF (normally. OUTPUT CURRENT (mA) Figure 8.25 VCC. (b) Output High Characteristic AC SWITCHING CHARACTERISTICS The propagation through a logic element depends on power supply voltage.com 13 . PROPAGATION DELAY CHANGE (ns) VCC = 5 V CL = 15 pF LS00 +2 tPLH 0 tPHL –2 For LS TTL. +4 t PD . resistive load has minimal effect on propagation delay) TTL limits are guaranteed over the commercial or military temperature and supply voltage ranges and with CL = 50 pF. limits are guaranteed at 25°C. the delay through a logic-element will increase to some extent when multiple outputs switch simultaneously due to inductance internal to the IC package. (a) Output High Characteristic Figure 8.5 4.5 V 3 LS240 2 2 LS00 1 1 0 –50 –100 –150 0 –50 –100 –150 –200 IOH. OUTPUT VOLTAGE (VOLTS) TA = 25°C VCC = 5. OUTPUT VOLTAGE (VOLTS) V OH. OUTPUT CURRENT (mA) IOH.0 V. Figure 10.75 5 5. VCC = 5. http://onsemi. SUPPLY VOLTAGE (V) 5. and output load. PROPAGATION DELAY CHANGE (ns) TA = +25°C CL = 15 pF LS00 +2 tPLH 0 tPHL –2 –4 –75 –4 –25 +25 +75 TA.5 V 3 4 TA = 25°C VCC = 5. Propagation delays are specified with only one output switching. ambient temperature. The effect of each of these parameters on ac propagation is shown in Figures 9 through 11.5 Figure 9.4 V OH. +4 t PD . AMBIENT TEMPERATURE (°C) +125 4.

MM. It is extremely important to understand that ESD sensitivity values alone are not sufficient when comparing devices. all of which meet Mil-Std-883C requirements. For device specific values reference the following specification: LS: 12MRM 93831A http://onsemi. The continuing improvements of ESD sensitivity through redesigns of ON Semiconductor TTL has resulted in minimum ESD levels for all new products and redesigns of >3500 volts for LS. * ESD CHARACTERISTICS Electrostatic Discharge (ESD) sensitivity for ON Semiconductor TTL is characterized using several methodologies (HBM. LOAD CAPACITANCE (pF) *Data for Figure 11 was taken with only one output switching at a time.com 14 . tester specific information as well as actual device ESD hardness levels are given in controlled documents and are available upon request. CDM). Figure 11. In an attempt to reduce correlation problems between various pieces of test equipment.20 t PD . PROPAGATION DELAY (ns) VCC = 5 V TA = 25°C LS00 16 12 tPLH 8 tPHL 4 0 20 40 60 80 100 CL.

CHAPTER 3 Design Considerations Testing and Applications Assistance Form http://onsemi.com 15 .

3 0. as well as maximum rated load.) = 1.4 0.3 0.5 0.4 0. and/or ALS TTL. 54/74ALS VIL 0.DESIGN CONSIDERATIONS NOISE IMMUNITY When mixing TTL families it is often desirable to know the guaranteed noise immunity for both LOW and HIGH logic levels. TTL devices are more efficient at high frequencies than CMOS.0 2. the input and output loading parameters of all families are normalized to the following values: 1 TTL Unit Load (U.L. Note that Table 3 represents “worst case” limits and assumes a maximum power supply and temperature variation across the IC’s which are interconnected. 93S00 Low Power Schottky TTL 54/74LS Advanced LS TTL. Increased noise immunity can be achieved by designing with decreased maximum allowable operating ranges.4 0.4 2. The numbers given above are guaranteed worst-case values.5 0.0 VOL 0.0 2.7 0.4 2.8 0.8 0.0 2. Table 3. In order to simplify designing with ON Semiconductor TTL devices.0 2.8 0.7 2. all logic families exhibit increased power consumption at high frequencies. Table 3 specifies these noise margins for systems containing LS.4 0.0 2.4 2.0 2. (a) LOW Level Noise Margins (Commercial) To From LS S ALS From “VOL” to “VIL” LS 300 300 300 S 300 300 300 ALS 300 300 300 Unit mV mV mV From Table 3.0 2.com 16 . Worst Case TTL Logic Levels Electrical Characteristics Military (– 55 to +125°C) TTL Families TTL HTTL LPTTL STTL LSTTL ALS TTL Standard TTL 9000.0 2.8 0.4 2.5 2.5 0. 54/74 High Speed TTL 54/74H Low Power TTL 93L00 (MSI) Schottky TTL 54/74S. (b) HIGH Level Noise Margins (Commercial) To LS 700 700 750 500 S 700 700 750 500 ALS 700 700 750 500 Unit mV mV mV mV LS S ALS (5% VCC) ALS (10% VCC) From “VOH” to “VIH” POWER CONSUMPTION FAN–IN AND FAN–OUT With the exception of ECL.0 2. Table 2.8 0.5 VOH 2.4 VOH 2.8 0.4 2.) = 40 µA in the HIGH state (Logic “1”) 1 TTL Unit Load (U.4 2.5 0.8 VIH 2.8 VIH 2.5 2.5 Commercial (0 to 70°C) VIL 0.8 0.4 0.8 0.5 Unit V V V V V V V (5% VCC) (10% VCC) VOL and VOH are the voltages generated at the output VIL and VIH are the voltage required at the input to generate the appropriate levels. Care must be taken when switching multiple gates at high frequencies to assure that their combined dissipation does not exceed package and/or device capabilities.7 2.L.0 2.75 2.0 2.8 0.0 VOL 0.7 0. S.6 mA in the LOW state (Logic “0”) http://onsemi. Table 2 lists the guaranteed logic levels for various TTL families and can be used to calculate noise margin.

L.L.L.L.4 mA and an IIH of 20 µA.L.5 U.Input loading and output drive factors of all products described in this handbook are related to these definitions.L. 1. Table 4.5 U.L. The 74LS95B which has a value of IIL = 0.L.L. LOW 5 U. 1 U. has an input LOW load factor of: 0.0625 U.5 U. 1. 1. The normalized output LOW drive factor is therefore: 16 mA = 10 U.L.6 mA and IIH of 40 µA is specified as having an input load factor of 1 U. 1 U.L.25 U.L. The normalized output LOW drive factor is: 8. The output of the 7400 will sink 16 mA in the LOW (logic “0”) state and source 800 µA in the HIGH (logic “1”) state. 5 U.4 mA or 0. 40 µA 2. 10 U. 10 U.L. 0.0 mA in the LOW state and source 400 µA in the HIGH state. is specified as having an input LOW load factor of: 0. OUTPUT DRIVE Values for MSI devices vary significantly from one element to another. The 74LS00 gate which has an IIL of 0.L.L HIGH 10 U.L.8 mA or 0. 1.L.5 U. 12.25 U.L.L LOW 0.L. 10 U.25 U. Consult the appropriate data sheet for actual characteristics. 3.5 U.L. 1 U.8 mA and IIH of 40 µA on the CP terminal.com 17 . which has a maximum IIL of 1. http://onsemi.L.25 U.L.L.L. 20 U. an input HIGH load factor of 1.L.25 U. 1 U. 40 µA Relative load and drive factors for the basic TTL families are given in Table 4.L 0. 12. 1.6 mA EXAMPLES — OUTPUT DRIVE 20 µA 40 µA or 0. 1.5 U. The output of the 74LS00 will sink 8.6 mA and the output HIGH drive factor is 800 µA or 20 U. A 7400 gate.) 2. (Also called a fan-in of 1 load.6 mA and the output HIGH drive factor is 400 µA or 10 U. 25 U.L. 1. INPUT LOAD FAMILY HIGH 74LS00 7400 9000 74H00 74S00 74 ALS 0.L. 1.L.6 mA and an input HIGH load factor of 40 µA 40 µA or 1 U.0 mA = 5 U. 20 U.25 U.L.L. 25 U. EXAMPLES — INPUT LOAD 1.L.

TTL logic is often used in line driving applications which require various termination techniques to maintain signal http://onsemi. This method.0 mA – 1. INPUT CAPACITANCE LINE DRIVING As a rule of thumb.5 pF. therefore no series resistor.6 mA 4.0 pF for DIP packages.5 V = 2.L. increases the input coupling capacitance and thus reduces the ac noise immunity. CAUTION: Do not connect an unused LS input to another input of the same NAND or AND function.9 kΩ can be used.L.L.WIRED–OR APPLICATIONS Certain TTL devices are provided with an “open” collector output to permit the Wired-OR (actually Wired-AND) function. This is achieved by connecting open collector outputs together and adding an external pull-up resistor.9 kΩ 0.75 V – 2. 2.4 V 4 • 100 µA + 2 • 40 µA = where: N1 N2 (HIGH) N2 (LOW) IOH IOL VOL VOH =4 = 4 • 0. Connect unused input to VCC.5 V) = Output HIGH Voltage Level (2. but should be held between 2.35 V = 4. MINIMUM AND MAXIMUM PULL-UP RESISTOR VALUES RX(MIN) VCC(MAX) – VOL IOL – N2(LOW) • 1. unused TTL inputs should not be left floating. LS TTL inputs have a breakdown voltage >7. Two possible ways of handling unused inputs are: 1.) being Driven = Output HIGH Leakage Current = LOW Level Fan-out Current of Driving Element = Output LOW Voltage Level (0.5 V = 8.4 mA 2.25 V – 0. each additional function adds approximately 1.com 18 . = 1 U. = 100 µA = 8. recommended for normal TTL.4 V Any value of pull-up resistor between 742 Ω and 4.4 V) = Power Supply Voltage Example: Four 74LS03 gate outputs driving four other LS gates or MSI inputs. RX(MIN) = 5. LS TTL inputs have an average capacitance of 5. Connect the unused input to the output of an unused gate that is forced HIGH. Because of its superior capacitive drive characteristics. = 2 U. For an input that serves more than one internal function.L. = RX(MAX) = VCC(MIN) – VOH N1 • IOH + N2(HIGH) • 40 µA = External Pull-up Resistor = Number of Wired-OR Outputs = Number of Input Unit Loads (U.25 U. The lower values yield the fastest speeds while the higher values yield the lowest power dissipation.48 mA RX(MAX) = 4. = 4 • 0.L.75 V = 742 Ω 6.5 U.0 mA = 0.6 mA where: Rx N1 N2 IOH = ICEX IOL VOL VOH VCC The value of the pull-up resistor is determined by considering the fan-out of the OR tie and the number of devices in the OR tie. UNUSED INPUTS For best noise immunity and switching speed.4 V and the absolute maximum input voltage. The pull-up resistor value is chosen from a range between maximum value (established to maintain the required VOH with all the OR tied outputs HIGH) and a minimum value (established so that the OR tie fan-out is not exceeded when only one output is LOW).0 V and require.

OUTPUT RISE AND FALL TIMES provide important information in determining reflection waveforms and crosstalk coefficients. and as it travels back toward the driver it adds to the line voltage. Exceptions occur in systems using ground planes to reduce ground noise during a logic transition. accelerating the transition rate and producing the noticeable change in slope. INTERCONNECTION DELAYS For those parts of a system in which timing is critical. When an interconnection is long enough that its delay is one-fourth to one-half of the signal transition time. This characteristic impedance forms a voltage divider with the driver output impedance. Output rise and fall times become longer as capacitive load is increased.integrity. e. At the instant the reflection arrives at the driver it adds algebraically to the still-rising driver output. ground planes give higher distributed capacitance and delays of about 0. the driver output waveform exhibits noticeable slope changes during a transition.0 –20 to –100 –15 24 –40 to –225 Unit Vdc mA mA mA mA mA mA http://onsemi. whereupon the signal starts doubling. The input and output characteristics graphs of Section 2 (Figures 4. which for transient conditions appears as a resistor returned to the quiescent voltage existing just before the beginning of the transition. This attenuated signal travels to the far end of the interconnection. It is also often necessary to construct load lines to determine reflection waveforms in line driving applications.com 19 .15 ns/inch for the type of interconnections normally used in TTL systems.15 to 0. Typical rise and fall times are approximately 6 ns for LS with a 50 pF load (measured 10 – 90%). 7. tending to produce a signal transition having the same rise or fall time as in the no-load condition but with a reduced amplitude. This is evidence that during the initial portion of the output voltage transition the driver sees the characteristic impedance of the interconnection (normally 100 Ω to 200 Ω). Most interconnections on a logic board are short enough that the wiring and load capacitance can be treated as a lumped capacitance for purposes of estimating their effect on the propagation delay of the driving circuit.22 ns/inch.. Simultaneously. Output Characteristics for Schottky TTL Logic (ALL MAXIMUM RATINGS) Characteristic Operating Voltage Range Output Drive: Standard Output Symbol VCC IOH IOL ISC IOH Buffer Output IOL ISC LS 74LSxxx 5 ± 5% –0. and 8) can be very useful for this purpose.12 to 0. Parameters associated with this application are listed in Table 5. which is essentially an unterminated transmission line. These range from about 0. if the driver output signal is positive-going the reflection will be positive-going.4 8.g. Table 5. designers should take into account the finite delay along the interconnections. a reflection voltage is generated which has the same amplitude and polarity as the original signal.

A good approximation for ordinary TTL interconnections is that distributed load capacitance decreases the characteristic impedance by about one-third and increases the delay by one-half. The successive slowing of the transition rate of the transmitted signal means that it takes longer for the signal to rise or fall to the threshold level of any particular load circuit. In this circumstance the first load circuit to receive a full signal is the one at the far end. — Multiplexer Inputs. in a worst-case situation. because of the doubling effect. Increasing the distributed capacitance of a transmission line reduces its impedance and increases its delay. while the last one to receive a full signal is the one nearest the driver since it must wait for the reflection to complete the transition. When load circuits are distributed along an interconnection.0 V – 0.5 V to + 10 V 5. is subtractive and has the effect of reducing the apparent amplitude of the signal.5 V to + 7. the input capacitance of each will cause a small reflection having a polarity opposite that of the signal transition. Thus. The series of small reflections. arriving back at the driver.com 20 . the attenuated output of the driver has time to reach substantial completion before the reflection arrives. http://onsemi. — Inputs connected to outputs.If an interconnection is of such length that its delay is longer than half the signal transition time. the net contribution to the overall delay is twice the delay of the interconnection because the initial part of the signal must travel to the far end of the line and the reflection must return. Device types having inputs limited to 5. the waveform observed at the driver output is a 2-step signal with a pedestal. ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired) Functional operation under these conditions is not implied. In the limit.5 V are as follows: SN74LS245 SN74LS640/641/642/645 SN74LS299 SN74LS151/251 — Inputs connected to outputs.5 V maximum limits are listed below. A rough but workable approach is to treat the load capacitances as an increase in the intrinsic distributed capacitance of the interconnection. — Certain Inputs.5 V Twice Rated IOL *Either input voltage limit or input current limit is sufficient to protect the inputs — Circuits with 5.0 mA – 0. CHARACTERISTIC Storage Temperature Temperature (Ambient) Under Bias VCC Pin Potential to Ground Pin *Input Voltage (dc) Diode Inputs *Input Current (dc) Voltage Applied to Open Collector Outputs (Output HIGH) High Level Voltage Applied to Disabled 3-State Output Current Applied to Output in Low State (Max) LS – 65°C to + 150°C – 55°C to + 125°C – 0.5 V to +15 V – 30 mA to + 5. and each capacitance also slows the transition rate of the signal as it passes by.

input conditions are chosen to guarantee worst case operation. Positive-going threshold voltage — The input voltage of a variable threshold device (ie. Input LOW voltage — The range of input voltages recognized by the device as a logic LOW. Output LOW voltage — The maximum guaranteed voltage at an output terminal sinking the maximum specified load current IOL. Output short-circuit current — The current flowing out of an output which is in the HIGH state when that output is short circuit to ground (or other specified potential). Input HIGH current — The current flowing into an input when a specified HIGH voltage is applied to that input. Maximum input LOW voltage — The maximum allowed input LOW in a system. When not specified. Output off current HIGH — The current flowing into a disabled 3-state output with a specified HIGH output voltage applied. This value represents the guaranteed input LOW threshold for the device.0 V). This parameter guarantees the integrity of the input diode which is intended to clamp negative ringing at the input terminal.e.DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA BOOK CURRENTS — Positive current is defined as conventional current flow into a device. – 10 V is greater than –1... Input LOW current — The current flowing out of an input when a specified LOW voltage is applied to that input. VCC VIK(MAX) Supply voltage — The range of power supply voltage over which the device is guaranteed to operate within the specified limits.com 21 . Schmitt Trigger) that is interpreted as a VIH as the input transition rises from below VT–(MIN). Minimum input HIGH voltage — The minimum allowed input HIGH in a logic system. Output HIGH voltage — The minimum guaranteed voltage at an output terminal for the specified output current IOH and at the minimum value of VCC. Schmitt Trigger) that is interpreted as a VIL as the input transition falls from above VT+(MAX). The leakage current flowing into a turned off open collector output with a specified HIGH output voltage applied.. This value represents the guaranteed input HIGH threshold for the device. IOL IOS IOZH IOZL VOLTAGES — All voltages are referenced to ground. the IOH is the current flowing out of an output which is in the HIGH state. VIH VIH(MIN) VIL VIL(MAX) VOH(MIN) VOL(MAX) VT+ VT– http://onsemi. Output HIGH current. Negative voltage limits are specified as absolute values (i. All current limits are specified as absolute values. Input HIGH voltage — The range of input voltages recognized by the device as a logic HIGH. Output LOW current — The current flowing into an output which is in the LOW state. ICC IIH IIL IOH Supply Current  The current flowing into the VCC supply terminal of a circuit with the specified input conditions and the outputs open. Output off current LOW — The current flowing out of a disabled 3-state output with a specified LOW output voltage applied. Negative current is defined as conventional current flow out of a device. For devices with a pull-up circuit. Input clamp diode voltage — The most negative voltage at an input when the specified current is forced out of that input terminal. Negative-going threshold voltage — The input voltage of a variable threshold device (ie.

5 for LS Vout http://onsemi. with the 3-state output changing from a high impedance (OFF) state to a HIGH level.com 22 .5 V for LS and VOH – 0. on the input and output voltage waveforms. For Inverting Function For Non-Inverting tPHL VIN Vout tPHL tPLH VIN tPLH tPHL Vout tr tf Waveform Rise Time: LOW to HIGH logic transition time.3 V for FAST. Enable tPZH Enable tPZH tPHZ VOH ≈ 3. with the output changing from the defined LOW level to the defined HIGH level. measured from the 10% to 90% points of the waveform. typically 1. HIGH-TO-LOW propagation delay time: The time delay between specified reference points. Waveform Fall Time: HIGH to LOW logic transition time. tr 90% 90% tf 10% 10% tPHZ Output disable time: HIGH to Z The time delay between the specified reference points on the input and output voltage waveforms.5 V . measured the 90% to the 10% points of the waveform. Reference point on the output voltage waveform is VOH – 0.AC SWITCHING PARAMETERS AND WAVEFORMS tPLH LOW-TO-HIGH propagation delay time : The time delay between specified reference points. with the 3-state output changing from the defined HIGH level to a high impedance (OFF) state. Output enable time: Z to HIGH The time delay between the specified reference points on the input and output voltage waveforms.3 V for LS. typically 1. on the input and output voltage waveforms.3 V for LS. with the output changing from the defined HIGH level to the defined LOW level.

Output enable time: Z to LOW The time delay between the specified reference points on the input and output voltage waveforms with the 3-state output changing from a high impedance (OFF) state to a HIGH level.5 for LS trec Recovery time Time required between an asynchronous signal (SET. A negative setup time indicates that data may be initiated sometime after the active transition of the timing pulse and still be recognized. Enable tPZL Enable Vout tPZL tPLZ VOZ = 1. Asynch Asynch trec Control th Hold Time The interval of time from the active edge of the control signal (usually the clock) to when the data to be recognized is no longer required to ensure proper interpretation of the data. ts VIN ts(L) CP th(L) VIN ts(H) CP th(H) http://onsemi. RESET. A negative hold time indicates that the data may be removed at some time prior to the active edge of the control signal. Setup time The interval of time during which the data to be recognized is required to remain constant prior to the active edge of the control signal to ensure proper data recognition.5 V for LS. Reference point on the output voltage waveform is VOL + 0. to insure that the device will properly respond to the synchronous signal. with the 3-state output changing from the defined LOW level to a high impedance (OFF) state.com 23 .5 V .tPLZ Output disable time: LOW to Z The time delay between the specified reference points on the input and output voltage waveforms. CLEAR or PARALLEL load) and the active edge of a synchronous control signal.

5. twL twH fMAX Toggle frequency/operating frequency The maximum rate at which clock pulses meeting the clock requirements (ie. tWL. or 0. input conditions are selected to produce a worst case condition.tw or tpw Pulse width The time between the specified amplitude points (1. http://onsemi.5. and IOZL TESTS Force 5. and tr. or IIL VIHMIN or VILMAX VIHMIN or VILMAX DUT Io DUT + Vo Vi IOS TEST Measure IOS DUT VIK TEST Force Ii Measure VIK + Vik – DUT Ii = –18 mA IOH.5 V* DUT Outputs Open *Unless otherwise indicated. 2. 2. or 0. IOZH. Guaranteed maximum clock frequency The lowest possible value for fMAX.4 V Measure IIHH. tf) may be applied to a sequential circuit.com 24 .3 V for LS) on the leading and trailing edges of a pulse. 5. tWH..4. IIH.4 V Measure IO DUT Io ICC TEST Measure ICC VCC MAX ± Vo GND or 4. fMAXmin TESTING DC TEST CIRCUITS The following test circuits and forcing functions represent ON Semiconductor’s typical DC test procedures. VOH AND VOL TESTS Force IOHMAX or IOLMAX Measure VOH or VOL IIHH.7. Above this frequency the device may cease to function. IIH AND IIL TESTS Force 7.

http://onsemi.com 25 . The device will oscillate if the input voltage does not exceed the trigger threshold plus the noise generated by the interaction of the test system or given application with the device. VOH VOL VIN Dynamic Threshold Region of output instability. good TTL testing techniques call for hard levels of less than 0. FUNCTIONAL TESTING OF TTL IN A NOISY ENVIRONMENT/“DYNAMIC” THRESHOLD Testing noise (noise generated by the test system itself and noise generated by TTL devices under test interacting with the test system) adds to. the correlation of “Dynamic” threshold cannot be made directly and will have meaning only in a relative sense. So although the Trigger threshold of any given device will correlate well between any test system. AC waveforms and terminology can be found on pages 22 to 24. Dynamic Noise contribution to apparent input threshold The VIN versus VOUT plot shows the practical effect of testing noise on a logic IC device. The Dynamic threshold (that creates Quiescent outputs). The amount of interactive DYNAMIC NOISE can be characterized by the difference between the Trigger threshold and the Dynamic threshold of the device under test. or subtracts from the threshold voltage applied to the TTL device under test.0 V. Input threshold voltages should be tested separately. VOUT Trigger Threshold Instead. is the input logic level required to overcome the interactive DYNAMIC NOISE generated by a device switching states.AC TEST CIRCUITS The following test circuits and conditions represent ON Semiconductor’s typical test procedures.4 V VIH to be applied for functional testing. and only (for noise reasons above) after setting the device state with a hard level. A simple number cannot be assigned to this parameter as it is heavily dependent on any given application or test environment. For this reason ON Semiconductor does not recommend functional testing of TTL devices using threshold levels of 0. The actual device Trigger threshold is represented by the initial low to high output transition.5 V VIL and greater than 2.8 V and 2.

Any frequency measurement over 15 MHz or pulse width less than 30 ns must be performed with a 6 ns input rise time.LS TEST CIRCUITS Test Circuit for Standard Output Devices VCC PULSE GENERATOR SETTINGS (UNLESS OTHERWISE SPECIFIED) LS Frequency = 1 MHz Duty Cycle = 50% 1 TLH (tr) = 6 ns (15)* 1 THL (tf) = 6 ns (15)* Amplitude = 0 to 3 V VIN PULSE GEN 51 Ω DUT 15 pF* VOUT * The specified propagation delay limits can be guaranteed with a 15 ns input rise time on all parameters except those requiring narrow pulse widths.com 26 . Test Circuit for Open Collector Output Devices VCC VCC RL VIN PULSE GEN 51 Ω 15 pF* DUT VOUT *includes all probe and jig capacitance Optional LS Load (Guaranteed—Not Tested) VCC RL CL http://onsemi.

R&QA Dept. please contact your local ON Semiconductor sales office or the ON Semiconductor Help line for assistance. please provide one or two “good” units (ON Semiconductor’s and/or other vendor) for comparison: 7) Describe USER process that device(s) are questionable in: Incoming component inspection {test system = ?}: Design prototyping: Board test/burn-in: Other (please describe): 8) Please describe the device correlation operating parameters as completely as possible for device(s) in question: > Describe all pin conditions (e. ON Semiconductor Device Correlation/Component Analysis Request Form — Please fill out entire form and return with devices to ON Semiconductor. Please fill out as much of the form as is possible if you are contacting ON Semiconductor for assistance or are sending devices back to ON Semiconductor for analysis. high. Func step rate. voltage expected.. stimulated but not under test. 5005 E. Your information can greatly improve the accuracy of analysis and can dramatically improve the correlation response and resolution time. under test. input voltages.). Phoenix. If further information is required. Items 4 thru 8 of the following form contains important questions that can be invaluable in analyzing application or device problems.. http://onsemi. AZ 85008. McDowell.APPLICATIONS ASSISTANCE FORM In the event that you have any questions or concerns about the performance of any ON Semiconductor device listed in this catalog. clamps. driving devices or devices being driven . caps. Potentially critical information includes: Input waveform timing relationships Input edge rates Input Overshoot or Undershoot — Magnitude and Duration Output Overshoot or Undershoot — Magnitude and Duration > Photographs. floating. does customer have viable alternate vendor(s) for device type? Yes No Alternate vendor’s name 6) Date code(s) and Serial Number(s) of devices returned for correlation — If possible. low. you can request direct factory assistance. Ground & VCC measurements should be made as physically close to the device in question as possible. 1) Name of Person Requesting Correlation: Phone No: 2) Alternate Contact: 3) Device Type (user part number): 4) Industry Generic Device Type: 5) # of devices tested/sampled: # of devices in question*: # returned for correlation: * In the event of 100% failure..com 27 Job Title: Phone/Position: Company: . Dynamic characteristics of Ground and VCC during device switching can dramatically effect input and internal operating levels. including any input or output loading conditions (resistors. plots or sketches of relevent inputs and outputs with voltages and time divisions clearly identified for all waveforms are greatly desirable. time to measure. > VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applications and test systems. does Customer have other date codes of ON Semiconductor devices that pass inspection? Yes No Please specify passing date code(s) if applicable If none.. It can be used as a self-help diagnostic guideline or for a baseline of information gathering to begin a dialog with ON Semiconductor representatives.).g. > Are there specific circumstances that seem to make the questionable unit(s) worse? Better? Temperature VCC Input rise/fall time Output loading (current/capacitance) Others > ATE functional data should include pattern with decoding key and critical parameters such as VCC. whatever ..

com 28 .http://onsemi.

CHAPTER 4 LS Data Sheets http://onsemi.com 29 .

6 Publication Order Number: SN74LS00/D .0 Unit V °C mA mA 14 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS00N SN74LS00D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.75 0 Typ 5.4 8.25 70 – 0. 1999 – Rev.com LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.SN74LS00 Quad 2-Input NAND Gate • ESD > 3500 Volts VCC 14 13 12 11 10 9 8 http://onsemi.0 25 Max 5. 1999 30 December. LLC.

IIN = – 18 mA VCC = MIN.0 10 Max 15 15 Unit ns ns Test Conditions VCC = 5. VIN = VIH or VIL per Truth Table IOL = 4.25 VOL Out ut Output LOW Voltage 0.4 mA VCC = MAX – 20 – 0.0 mA VCC = VCC MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current ICC Total. VIN = 0.35 IIH IIL IOS In ut Input HIGH Current 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn–Off Delay. VIN = 7.4 –100 0. Input to Output Turn–On Delay. Input to Output Min Typ 9.0 V CL = 15 pF http://onsemi.SN74LS00 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.65 3. Output HIGH Total.6 4.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 V VCC = MAX. nor for more than 1 second. VIN = VIL or VIH per Truth Table VCC = MAX.7 – 0.5 0.com 31 .0 0.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.0 mA 0.8 – 1. IOH = MAX. VIN = 2.5 20 V µA mA mA mA IOL = 8.4 Min 2.7 V VCC = MAX. Output LOW 1.

1999 32 December.0 Unit V °C mA mA 14 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS04N SN74LS04D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 1999 – Rev.25 70 – 0.0 25 Max 5.75 0 Typ 5. 6 Publication Order Number: SN74LS04/D . LLC.SN74LS04 Hex Inverter VCC 14 13 12 11 10 9 8 http://onsemi.4 8.com 1 2 3 4 5 6 7 GND LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.

4 –100 0. VIN = 2.0 V CL = 15 pF http://onsemi. Input to Output Turn–On Delay.com 33 . Output LOW 2. IOH = MAX.7 – 0.8 – 1.0 mA 0. Input to Output Min Typ 9.5 20 V µA mA mA mA IOL = 8.7 V VCC = MAX. nor for more than 1 second.0 10 Max 15 15 Unit ns ns Test Conditions VCC = 5.25 VOL Out ut Output LOW Voltage 0.SN74LS04 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.0 0.35 IIH IIL IOS In ut Input HIGH Current 0.0 mA VCC = VCC MIN. VIN = 0.4 Min 2. IIN = – 18 mA VCC = MIN. Output HIGH Total. VIN = 7.65 3.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.6 mA VCC = MAX – 20 – 0.4 6. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn–Off Delay.5 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current ICC Total. VIN = VIH or VIL per Truth Table IOL = 4.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = VIL or VIH per Truth Table VCC = MAX.0 V VCC = MAX.

com * 1 2 3 * 4 5 * 6 7 GND LOW POWER SCHOTTKY * OPEN COLLECTOR OUTPUTS GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Voltage – High Output Current – Low Min 4. 1999 – Rev. 6 Publication Order Number: SN74LS05/D .0 Unit V °C V mA 1 14 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS05N SN74LS05D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. LLC.SN74LS05 Hex Inverter VCC 14 13 12 * 11 10 * 9 * 8 http://onsemi. 1999 34 December.5 8.25 70 5.75 0 Typ 5.0 25 Max 5.

RL = 2.4 6.35 IIH IIL In ut Input HIGH Current 0.0 mA VCC = VCC MIN.8 – 1.4 V AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn–Off Delay.4 Typ Max Unit V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. Input to Output Min Typ 17 15 Max 32 28 Unit ns ns Test Conditions VCC = 5.4 0.5 100 0.7 V VCC = MAX.1 Input LOW Current Power Supply Current ICC Total.0 0. VIN = 0.25 Out ut Output LOW Voltage 0.0 mA – 0. Output LOW 2. Input to Output Turn–On Delay. IIN = – 18 mA VCC = MIN. VIN = VIL or VIH per Truth Table mA V VCC = MAX.65 Min 2.5 20 V µA mA mA IOL = 8.0 k W http://onsemi.6 mA VCC = MAX – 0. VOH = MAX IOL = 4. VIN = 2.0 V CL = 15 pF. VIN = 7.com 35 .0 V VCC = MAX.SN74LS05 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0. Output HIGH Total.

SN74LS08 Quad 2-Input AND Gate VCC 14 13 12 11 10 9 8 http://onsemi. 6 Publication Order Number: SN74LS08/D .4 8.0 Unit V °C mA mA 14 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS08N SN74LS08D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.25 70 – 0. 1999 36 December. 1999 – Rev.0 25 Max 5.75 0 Typ 5. LLC.com 1 2 3 4 5 6 7 GND LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.

8 – 1.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.8 8. VIN = VIL or VIH per Truth Table VCC = MAX.8 mA VCC = MAX – 20 – 0.5 20 V µA mA mA mA IOL = 8.0 0.35 IIH IIL IOS In ut Input HIGH Current 0.0 V VCC = MAX.25 VOL Out ut Output LOW Voltage 0.0 mA 0.SN74LS08 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. VIN = 0.0 mA VCC = VCC MIN.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = 2. Input to Output Turn–On Delay.0 V CL = 15 pF http://onsemi. Output LOW 4. IIN = – 18 mA VCC = MIN.4 –100 0.com 37 .1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current ICC Total. Output HIGH Total.4 Min 2. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn–Off Delay.65 3. IOH = MAX. VIN = 7.7 – 0. Input to Output Min Typ 8. VIN = VIH or VIL per Truth Table IOL = 4.0 10 Max 15 20 Unit ns ns Test Conditions VCC = 5.5 0. nor for more than 1 second.7 V VCC = MAX.

The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions.0 25 Max 5. they have greater noise margin than conventional inverters. and provide different input threshold voltages for positive and negative-going transitions. 1999 – Rev. 0 Publication Order Number: SN74LS14/D . jitter-free output signals.4 8. LLC.SN74LS14 Schmitt Triggers Dual Gate/Hex Inverter The SN74LS14 contains logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. http://onsemi. Additionally.com LOW POWER SCHOTTKY LOGIC AND CONNECTION DIAGRAMS VCC 14 13 SN74LS14 12 11 10 9 8 14 1 PLASTIC N SUFFIX CASE 646 1 2 3 4 5 6 7 GND 14 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.0 Unit V °C SOIC D SUFFIX CASE 751A ORDERING INFORMATION mA mA Device SN74LS14N SN74LS14D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.75 0 Typ 5. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. They are capable of transforming slowly changing input signals into sharply defined. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output.25 70 – 0. 1999 38 December.

VIN = 2.25 0. VIN = VIL VCC = MIN. Output LOW Note 1: Not more than one output should be shorted at a time.6 V 0. IOH = – 400 µA. AC Waveforms http://onsemi.SN74LS14 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT+ – VT– VIK VOH VO OL IT+ IT– IIH IIL IOS Parameter Positive-Going Threshold Voltage Negative-Going Threshold Voltage Hysteresis Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 0.0 V VCC = 5.0 mA.0 V VCC = MAX. Output HIGH .18 1.7 V VCC = MAX.0 mA.0 V VCC = 5.4 – 1. nor for more than 1 second.14 – 0.65 3.7 Min 1.0 V. VIN = 2.8 V VOUT 1. IOL = 4.0 20 0.3 V 1.3 V Figure 1.0 1.5 0.0 V. Input to Output Max 22 22 Unit ns ns Test Conditions VCC = 5.0 V CL = 15 pF 3V VIN 0V tPHL tPLH 1.8 – 0.4 –100 16 mA VCC = MAX – 0.com 39 .5 V mA mA µA mA mA mA 2.6 – 0. 12 Total. VOUT = 0 V AC CHARACTERISTICS (TA = 25°C) Symbol tPLH tPHL Parameter Propagation Delay.4 0. VIN = 7. IOL = 8.6 0.0 V VCC = MIN.1 Unit V V V V V V Test Conditions VCC = 5.35 Input Current at Positive-Going Threshold Input Current at Negative-Going Threshold Input HIGH Current 0. VIN = VT– VCC = MAX. VIN = 2. VIN = 0. VIN = VT+ VCC = 5.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current ICC Total.4 0. IIN = – 18 mA VCC = MIN.5 Typ Max 2.0 V VCC = 5. Input to Output Propagation Delay. 21 – 20 8.4 V VCC = MAX.0 V VCC = MIN.

4 0 0 0.3 1. OUTPUT VOLTAGE (VOLTS) 4 2 V T .6 3 1. POWER SUPPLY VOLTAGE (VOLTS) 5.8 2 DVT 1 0.2 VIN. INPUT VOLTAGE (VOLTS) 1. HYSTERESIS (VOLTS) VCC = 5 V TA = 25°C TA = 25°C VT+ 1. Threshold Voltage Hysteresis versus Temperature http://onsemi.5 Figure 2.5 1.9 0.2 VT– 0.25 VCC. AMBIENT TEMPERATURE (°C) 125° Figure 4. VIN versus VOUT Transfer Function 1. Threshold Voltage and Hysteresis versus Power Supply Voltage ∆ VT 0° 25° 75° TA.SN74LS14 5 V O .75 5 5.8 2 0 4.5 4.1 0.com 40 .4 0.7 – 55° VT– VT+ Figure 3.95 1.9 V T . THRESHOLD VOLTAGE (VOLTS) ∆ V T. THRESHOLD VOLTAGE (VOLTS) ∆ V T.7 1. HYSTERESIS (VOLTS) 1.

SN74LS32 Quad 2-Input OR Gate VCC 14 13 12 11 10 9 8 http://onsemi.com 1 2 3 4 5 6 7 GND LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 – Rev. 1999 41 December.0 Unit V °C mA mA 14 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS32N SN74LS32D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.75 0 Typ 5. 6 Publication Order Number: SN74LS32/D .4 8.0 25 Max 5. LLC.25 70 – 0.

5 0. VIN = VIH or VIL per Truth Table IOL = 4.0 V VCC = MAX.5 20 V µA mA mA mA IOL = 8.0 mA VCC = VCC MIN.8 – 1.0 V CL = 15 pF http://onsemi.25 VO OL Output LOW Voltage 0.0 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. Output LOW – 20 – 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.4 –100 6. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 7.SN74LS32 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. IIN = – 18 mA VCC = MIN.65 3.8 0. VIN = 0.7 – 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.4 Min 2. VIN = 2. Input to Output Turn-On Delay.7 V VCC = MAX.2 9.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time. Input to Output Min Typ 14 14 Max 22 22 Unit ns ns Test Conditions VCC = 5. IOH = MAX.com 42 . Output HIGH Total. nor for more than 1 second.35 IIH IIL IOS ICC Input HIGH Current 0.0 mA 0.

75 0 Typ 5.com * 1 2 3 4 5 6 * 7 GND LOW POWER SCHOTTKY * OPEN COLLECTOR OUTPUTS GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Voltage – High Output Current – Low Min 4. 6 Publication Order Number: SN74LS38/D .0 25 Max 5.25 70 5.SN74LS38 Quad 2-Input NAND Buffer VCC 14 13 12 * 11 10 9 * 8 http://onsemi. LLC.5 24 Unit V °C V mA 14 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS38N SN74LS38D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 1999 43 December. 1999 – Rev.

0 V VCC = MAX.SN74LS38 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VO OL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0.35 IIH IIL ICC Input HIGH Current 0. VIN = 0.4 V VCC = MAX.8 – 1. Input to Output Min Typ 20 18 Max 32 28 Unit ns ns Test Conditions VCC = 5. VOH = MAX IOL = 12 mA VCC = VCC MIN. IIN = – 18 mA VCC = MIN.com 44 .4 Typ Max Unit V V V µA V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 12 0.0 V. Input to Output Turn-On Delay. Output HIGH Total. Output LOW – 0. VIN = VIL or VIH per Truth Table VCC = MAX.5 20 V µA mA mA IOL = 24 mA – 0.4 2.1 Input LOW Current Power Supply Current Total.0 0. VIN = 2.65 Min 2. VIN = 7.5 250 0.4 V VCC = MAX mA AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.25 Output LOW Voltage 0. RL = 667 Ω CL = 45 pF http://onsemi.

SN74LS42 One-of-Ten Decoder The LSTTL / MSI SN74LS42 is a Multipurpose Decoder designed to accept four BCD inputs and provide ten mutually exclusive outputs. LLC. 1999 45 December.75 0 Typ 5. 6 Publication Order Number: SN74LS42/D . • Multifunction Capability • Mutually Exclusive Outputs • Demultiplexing Capability • Input Clamp Diodes Limit High Speed Termination Effects http://onsemi.25 70 – 0.0 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS42N SN74LS42D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. The LS42 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. 1999 – Rev.4 8.com LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.0 25 Max 5.

L.) = 40 mA HIGH/1.com 46 . LOW 0.L.L.SN74LS42 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 A0 15 A1 14 A2 13 A3 12 9 11 8 10 7 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.25 U. 1 0 2 1 3 2 4 3 5 4 6 5 7 6 8 GND LOADING (Note a) PIN NAMES A0 – A3 0 to 9 Address Inputs Outputs. Active LOW HIGH 0. NOTES: a) 1 TTL Unit Load (U. 5 U.L. 10 U.5 U. LOGIC SYMBOL 15 14 13 12 A0 A1 A2 A3 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 9 10 11 VCC = PIN 16 GND = PIN 8 LOGIC DIAGRAM A0 15 A1 14 A2 13 A3 12 1 2 3 4 5 6 7 9 10 11 0 1 2 3 4 5 6 7 8 9 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS http://onsemi.6 mA LOW.L.

The most significant input A3 produces a useful inhibit function when the LS42 is used as a one-of-eight decoder.com 47 .SN74LS42 FUNCTIONAL DESCRIPTION The LS42 decoder accepts four active HIGH BCD inputs and provides ten mutually exclusive active LOW outputs. The A3 input can also be used as the Data input in an 8-output demultiplexer application. The logic design of the LS42 ensures that all outputs are HIGH when binary codes greater than nine are applied to the inputs. The active LOW outputs facilitate addressing other MSI units with LOW input enables. as shown by logic symbol or diagram. TRUTH TABLE A0 L H L H L H L H L H L H L H L H A1 L L H H L L H H L L H H L L H H A2 L L L L H H H H L L L L H H H H A3 L L L L L L L L H H H H H H H H 0 L H H H H H H H H H H H H H H H 1 H L H H H H H H H H H H H H H H 2 H H L H H H H H H H H H H H H H 3 H H H L H H H H H H H H H H H H 4 H H H H L H H H H H H H H H H H 5 H H H H H L H H H H H H H H H H 6 H H H H H H L H H H H H H H H H 7 H H H H H H H L H H H H H H H H 8 H H H H H H H H L H H H H H H H 9 H H H H H H H H H L H H H H H H H = HIGH Voltage Level L = LOW Voltage Level http://onsemi.

3 V tPLH 1.4 Min 2.5 0.4 –100 13 0. VIN = 0.SN74LS42 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. http://onsemi.3 V tPHL 1.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.5 20 V µA mA mA mA mA IOL = 8. VIN = VIL or VIH per Truth Table VCC = MAX.3 V 1.com 48 .7 V VCC = MAX.35 IIH IIL IOS ICC Input HIGH Current 0. VIN = VIH or VIL per Truth Table IOL = 4.7 – 0. IOH = MAX.8 – 1.3 V tPHL 1.0 mA VCC = VCC MIN.3 V VIN 1.0 V CL = 15 pF AC WAVEFORMS VIN 1.0 mA 0. VIN = 2. VIN = 7. nor for more than 1 second.0 0.25 VO OL Output LOW Voltage 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay (2 Levels) Propagation Delay (3 Levels) Min Typ 15 15 20 20 Max 25 25 30 30 Unit ns ns Test Conditions Figure 2 Figure 1 VCC = 5.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. Figure 2. IIN = – 18 mA VCC = MIN.65 3.3 V tPLH 1.3 V VOUT VOUT 1.3 V Figure 1.0 V VCC = MAX.

The SN74LS47 incorporates automatic leading and / or trailing-edge zero-blanking control (RBI and RBO). high sink current outputs for driving indicators directly.SN74LS47 BCD to 7-Segment Decoder/Driver The SN74LS47 are Low Power Schottky BCD to 7-Segment Decoder/ Drivers consisting of NAND gates. They offer active LOW. as well as conditions required at the auxiliary inputs. 6 Publication Order Number: SN74LS47/D . blanking input / ripple-blanking output and ripple-blanking input. • Lamp Intensity Modulation Capability (BI/RBO) • Open Collector Outputs • Lamp Test Provision • Leading/ Trailing Zero Suppression • Input Clamp Diodes Limit High-Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High BI/RBO Output Current – Low BI/RBO BI/RBO Off–State Output Voltage a to g On–State Output Current a to g Min 4.75 0 Typ 5. 1999 – Rev.2 Unit V °C http://onsemi. are shown in the truth tables. LLC. Output configurations of the SN74LS47 are designed to withstand the relatively high voltages required for 7-segment indicators. depending on the state of the auxiliary inputs. The circuits accept 4-bit binary-coded-decimal (BCD) and. Indicator segments requiring up to 24 mA of current may be driven directly from the SN74LS47 high performance output transistors.com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS47N SN74LS47D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel mA mA VO(off) IO(on) 15 24 V mA © Semiconductor Components Industries. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. Display patterns for BCD input counts above nine are unique symbols to authenticate input conditions. 1999 49 December. Lamp test (LT) may be performed at any time which the BI / RBO node is a HIGH level.25 70 – 50 3. input buffers and seven AND-OR-INVERT gates. This device also contains an overriding blanking input (BI) which can be used to control the lamp intensity by varying the frequency and duty cycle of the BI input signal or to inhibit the outputs.0 25 Max 5. decodes this data to drive a 7-segment display indicator. These outputs will withstand 15 V with a maximum reverse current of 250 µA. The relative positive-logic output levels. The remaining NAND gate and three input buffers provide lamp test.

L.com 50 .2 U. to g BCD Inputs Ripple–Blanking Input Lamp–Test Input Blanking Input or Ripple–Blanking Output Outputs HIGH 0.L.L.L. 0. 1. 0. b) Output current measured at VOUT = 0. D RBI LT BI/RBO a. for Commercial (74) Temperature Ranges.L.L.25 U.5 U.5 U. 0. 2.5 U.L.L. 0.5 V b) The Output LOW drive factor is 15 U.0 U. 0. Open–Collector LOW 0. 0.) = 40 mA HIGH. 1. LOGIC SYMBOL 7 1 2 6 3 5 A B C D LT RBI BI/ f g RBO a b c d e 13 12 11 10 9 15 14 4 VCC = PIN 16 GND = PIN 8 http://onsemi.5 U.L.SN74LS47 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 f 15 g 14 a 13 b 12 c 11 d 10 e 9 1 B 2 C 3 4 5 6 D 7 A 8 GND LT BI / RBO RBI LOADING (Note a) PIN NAMES A.25 U.75 U.25 U. NOTES: a) 1 Unit Load (U. B.L. 15 U.L.L. C.6 mA LOW.L.

(D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level. C.SN74LS47 LOGIC DIAGRAM a A b B INPUT C D d BLANKING INPUT OR RIPPLE-BLANKING OUTPUT d c c OUTPUT b a e e f LAMP-TEST INPUT RIPPLE-BLANKING INPUT f g g 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS TRUTH TABLE INPUTS DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT OUTPUTS LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X D L L L L L L L L H H H H H H H H X L X C L L L L H H H H L L L L H H H H X L X B L L H H L L H H L L H H L L H H X L X A L H L H L H L H L H L H L H L H X L X BI/RBO H H H H H H H H H H H H H H H H L L H a L H L L H L H L L L H H H L H H H H L b L L L L L H H L L L H H L H H H H H L c L L H L L L L L L L H L H H H H H H L d L H L L H L L H L H L L H L L H H H L e L H L H H H L H L H L H H H L H H H L f L H H H L L L H L L H H L L L H H H L g H H L L L L L H L L L L L L L H H H L NOTE A A B C D H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial NOTES: (A) BI/RBO is wire-AND logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). with the lamp test input at HIGH level. all segment outputs go to a LOW level. all segment outputs go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition). http://onsemi. The blanking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired. B. (C) When ripple-blanking input (RBI) and inputs A. (B) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state of any other input condition.com 51 . X = input may be HIGH or LOW. and a LOW level is applied to lamp test input. and D are at LOW level. and ripple-blanking input (RBI) must be open or at a HIGH level if blanking of a decimal 0 is not desired.

IOH = – 50 µ µA. Output LOW Voltage g BI / RBO Off-State Output Current a thru g On-State Output Voltage g a thru g Input HIGH Current Input LOW Current BI / RBO Any Input except BI / RBO Output Short Circuit Current (Note 1) Power Supply Current – 0.25 0. Figure 2.0 13 Min 2.2 42 0. http://onsemi.5 20 0.3 V VIN 1.3 7.com 52 . Address Input to Segment Output Propagation Delay.5 Typ Max Unit V V V V V V µA V V µA mA mA mA mA Test Conditions Guaranteed Input HIGH Theshold Voltage for All Inputs Guaranteed Input LOW Threshold Voltage for All Inputs VCC = MIN. VIN = 0.35 0. VIN = 2.8 – 1.1 – 1.7 V VCC = MAX. VO (off) = 15 V IO (on) = 12 mA IO (on) = 24 mA VCC = MAX.65 4. VIN = VIN or VIL per Truth Table.4 0.SN74LS47 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VO OH VO OL IO (off) VO (on) ( ) IIH IIL IOS BI / RBO ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage BI / RBO Voltage.6 mA IOL = 3.25 0.3 V tPLH 1.5 250 0. IIN = – 18 mA VCC = MIN.3 V Figure 1.2 – 0. VOUT = 0 V VCC = MAX Note 1: Not more than one output should be shorted at a time.4 0.0 V CL = 15 pF AC WAVEFORMS VIN 1. VIN = 7.4 V VCC = MAX.35 2.3 V tPHL 1.3 V tPHL 1. VIN = VIH or VIL per Truth Table VCC = MAX.3 V 1.3 V tPLH 1.0 0. nor for more than 1 second.3 V VOUT VOUT 1.4 24 – 0. VIN = VIN or VIL per Truth Table IOL = 1.0 0. RBI Input To Segment Output Min Typ Max 100 100 100 100 Unit ns ns ns ns Test Conditions VCC = 5. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPHL tPLH tPHL tPLH Parameter Propagation Delay.4 –2. VIN = VIN or VIL per Truth Table VCC = MAX.0 V VCC = MAX.2 mA VCC = MIN.

SOIC D SUFFIX CASE 751A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.4 8. 1999 – Rev.SN74LS74A Dual D-Type Positive Edge-Triggered Flip-Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. When the clock input is at either the HIGH or the LOW level.com LOW POWER SCHOTTKY MODE SELECT – TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load “1” (Set) Load “0” (Reset) * L H L H H SD H L L H H D X X X h l Q H L H H L Q L H H L H 14 1 OUTPUTS PLASTIC N SUFFIX CASE 646 Both outputs will be HIGH while both SD and CD are LOW. h (q) = Lower case letters indicate the state of the referenced input i. h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition. 1999 53 December. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. h = HIGH Voltage Level L. 14 1 H. http://onsemi.0 Unit V °C mA mA ORDERING INFORMATION Device SN74LS74AN SN74LS74AD Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.25 70 – 0. LLC. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. Each flip-flop has individual clear and set inputs. the D input signal has no effect.0 25 Max 5. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH. but the output states are unpredictable if SD and CD go HIGH simultaneously. 6 Publication Order Number: SN74LS74A/D . I = LOW Voltage Level X = Don’t Care l. and also complementary Q and Q outputs.

com 54 .SN74LS74A LOGIC DIAGRAM (Each Flip-Flop) SET (SD) 4 (10) Q 5 (9) CLEAR (CD) 1 (13) CLOCK 3 (11) D 2 (12) Q 6 (8) LOGIC SYMBOL 4 2 3 D SD Q CP CD Q 1 VCC = PIN 14 GND = PIN 7 6 5 12 11 10 D SD Q CP CD Q 13 8 9 http://onsemi.

IOH = MAX. IIN = – 18 mA VCC = MIN.0 Typ Max Unit ns ns ns Figure 1 ns ns Figure 1 Test Conditions Figure 1 Figure 2 VCC = 5.0 mA 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. nor for more than 1 second.8 – 1.7 – 0.0 V mA mA mA VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX.5 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VCC = 5.0 mA VCC = VCC MIN.0 V http://onsemi.0 V 50 F CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW (H) tW (L) ts th Clock Clear. Clock Set.25 VO OL Output LOW Voltage 0. AC CHARACTERISTICS (TA = 25°C.5 20 40 0. VIN = 2.0 0. Set Data Setup Time — HIGH Data Setup Time — LOW Hold Time Parameter Min 25 25 20 20 5. VIN = 7.com 55 .7 V IIH mA VCC = MAX. VIN = 0.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock.1 0.4 Min 2.2 – 0.35 Input High Current Data. Clear Data. Clock Set. Clear.65 3. Clear IIL IOS ICC Input LOW Current Data.0 V µA IOL = 8.4 – 0.8 –100 8. Clock Clear Set to Output Min 25 Typ 33 13 25 25 40 Max Unit MHz ns ns Test Conditions Figure 1 Figure 1 VCC = 5. VIN = VIH or VIL per Truth Table IOL = 4. Clock Set.SN74LS74A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. Clear Output Short Circuit Current (Note 1) Power Supply Current – 20 0.

Set and Clear to Output Delays. Figure 1.3 V tW CLEAR tPLH 1.3 V th(L) ts(L) 1.3 V *The shaded areas indicate when the input is permitted to change for predictable output performance.3 V tPHL tPLH 1.SN74LS74A AC WAVEFORMS D* 1.3 V tPLH 1. Data Set-Up and Hold Times.3 V 1 fMAX CP tPHL Q 1.3 V tW(H) 1.com 56 .3 V tPHL Q 1.3 V 1.3 V tPHL 1.3 V Q 1. Clock to Output Delays.3 V tPLH 1. Set and Clear Pulse Widths http://onsemi.3 V Figure 2.3 V 1.3 V Q 1.3 V th(H) ts(H) tW(L) 1. Clock Pulse Width tW SET 1.

http://onsemi. PLASTIC N SUFFIX CASE 648 H. h = HIGH Voltage Level L.0 25 Max 5. K. h (q) = Lower case letters indicate the state of the referenced input i. LLC. 6 Publication Order Number: SN74LS76A/D .SN74LS76A Dual JK Flip-Flop with Set and Clear The SN74LS76A offers individual J. but the output states are unpredictable if SD and CD go HIGH simultaneously. h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition 16 1 SOIC D SUFFIX CASE 751B GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.0 Unit V °C mA mA ORDERING INFORMATION Device SN74LS76AN SN74LS76AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. I = LOW Voltage Level X = Immaterial l.25 70 – 0.75 0 Typ 5. the inputs are enabled and data will be accepted. 1999 – Rev. These dual flip-flops are designed so that when the clock goes HIGH. Direct Set and Direct Clear inputs. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.4 8. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Clock Pulse.com LOW POWER SCHOTTKY MODE SELECT – TRUTH TABLE OPERATING MODE Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold * INPUTS SD L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l OUTPUTS Q H L H q L H q Q L H H q H L q 16 1 Both outputs will be HIGH while both SD and CD are LOW. 1999 57 December.

0 Test Conditions http://onsemi. IIN = – 18 mA VCC = MIN.5 20 60 80 V µA IOL = 8.4 – 0. K Clear Clock Input LOW Current Short Circuit Current (Note 1) Power Supply Current J.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock.35 J.0 mA 0. AC CHARACTERISTICS (TA = 25°C. Clear.7 – 0.0 mA VCC = VCC MIN. VIN = 7.4 Min 2.SN74LS76A LOGIC DIAGRAM 2 Q Q 16 1 4 CLEAR (CD) J SET (SD) K K CP J C Q D 3 VCC = PIN 5 GND = PIN 13 CLOCK (CP) 14 SD Q 15 12 6 9 K CP J C Q D 8 10 LOGIC SYMBOL 7 SD Q 11 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. nor for more than 1 second.1 0.0 V 50 CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW tW ts th Parameter Clock Pulse Width High Clear Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.65 3.com 58 . K Clear. VIN = 2.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.3 0. K Clear Clock IIH Input HIGH Current J.8 – 1.5 0.25 VO OL Output LOW Voltage 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 V 0.0 0.7 V IIL IOS ICC mA mA mA VCC = MAX.8 –100 6. Clock Clear Set to Output 15 20 ns Min 30 Typ 45 15 20 Max Unit MHz ns VCC = 5.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. Clock – 20 0. VIN = 0.4 – 0. IOH = MAX. VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = MAX. VCC = 5.

Refer to Applications section of data sheet for high speed method of comparing large words. B0 – B3). and OA = B Outputs Available GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. IA > B. The lower five lines describe the operation under abnormal conditions on the cascading inputs. B3 being the most significant inputs. 1999 – Rev. IA < B. For serial (ripple) expansion.75 0 Typ 5.4 8. These conditions occur when the parallel expansion technique is used. B). 1999 59 December. “A less than B” (OA < B). each word having four Parallel Inputs (A0 – A3.0 25 Max 5.com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS85N SN74LS85D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.SN74LS85 4-Bit Magnitude Comparator The SN74LS85 is a 4-Bit Magnitude Camparator which compares two 4-bit words (A. Three Outputs are provided: “A greater than B” (OA > B).25 70 – 0. the Expander Inputs to the least significant position must be connected as follows: IA < B= IA > B = L. and IA = B Inputs of the next most significant comparator. The Truth Table on the following page describes the operation of the SN74LS85 under all possible logic conditions. “A equal to B” (OA = B). the OA > B. A3. Operation is not restricted to binary codes. 6 Publication Order Number: SN74LS85/D . as shown in Figure 1. IA = B. LLC. the device will work with any monotonic code. The upper 11 lines describe the normal operation under all conditions that will occur in a single device or in a series expansion scheme. OA < B and OA = B Outputs are connected respectively to the IA > B. For proper compare operation. allow cascading without external gates. IA = B = H. OA < B. Three Expander Inputs. • Easily Expandable • Binary or BCD Comparison • OA > B.0 Unit V °C mA mA http://onsemi. IA < B.

SN74LS85
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 A3 15 B2 14 A2 13 A1 12 B1 11 A0 10 B0 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 B3 2 IA<B 3 IA=B 4 IA>B 5 6 8 7 OA<B GND LOADING (Note a) PIN NAMES A0 – A3, B0 – B3 IA = B IA < B, IA > B OA > B OA < B OA = B Parallel Inputs A = B Expander Inputs A < B, A > B, Expander Inputs A Greater than B Output B Greater than A Output A Equal to B Output HIGH 1.5 U.L. 1.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 10 U.L. LOW 0.75 U.L. 0.75 U.L. 0.25 U.L. 5 U.L. 5 U.L. 5 U.L.

OA>B OA=B

NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL
10 12 13 15 9 11 14 1 4 2 3 A0 A1 A2 A3 B0 B1 B2 B3 IA>B OA>B IA<B OA<B IA=B OA=B VCC = PIN 16 GND = PIN 8 5 7 6

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SN74LS85
LOGIC DIAGRAM
(15) (1)

A3 B3

(5) (13)

OA>B

(14) (2) A<B (3) A=B (4) A>B (12) (11)

A2 B2

(6)

OA=B

A1 B1

(7)

OA<B

A0 B0

(10) (9)

TRUTH TABLE
COMPARING INPUTS A3,B3 A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2,B2 X X A2>B2 A2<B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A1,B1 X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A1=B1 A0,B0 X X X X X X A0>B0 A0<B0 A0=B0 A0=B0 A0=B0 A0=B0 A0=B0 CASCADING INPUTS IA>B X X X X X X X X H L X H L IA<B X X X X X X X X L H X H L IA=B X X X X X X X X L L H L L OA>B H L H L H L H L H L L L H OUTPUTS OA<B L H L H L H L H L H L L H OA=B L L L L L L L L L L H L L

H = HIGH Level L = LOW Level X = IMMATERIAL

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61

SN74LS85
A n3 A n2 A n1 B n3 B n2 B n1 An A0 A1 A2 A3 B0 B1 B2 A0 A1 A2 A3 B0 B1 B2 B3 B3 OA > B OA < B OA = B Bn B3 OA > B OA < B OA = B

A0 A1 A2 A3 B0 B1 B2 IA > B IA < B IA = B

L L H

IA > B IA < B IA = B

SN74LS85

SN74LS85

A>B A<B A=B

L = LOW LEVEL H = HIGH LEVEL

Figure 1. Comparing Two n-Bit Words

APPLICATIONS Figure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the technique shown in Figure 1, six levels of device delay result
Table 1
WORD LENGTH 1 – 4 Bits 5 – 24 Bits 25 – 120 Bits NUMBER OF PKGS. 1 2–6 8 – 31

when comparing two 24-bit words. The parallel technique can be expanded to any number of bits, see Table 1.

NOTE: The SN74LS85 can be used as a 5-bit comparator only when the outputs are used to drive the A0–A3 and B0–B3 inputs of another SN74LS85 as shown in Figure 2 in positions #1, 2, 3, and 4.

INPUTS (LSB) A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 IA > B OA > B IA < B IA = B #5 OA < B OA = B (MSB) A20 A21 A22 A23 B20 B21 B22 B23 A0 A1 A2 A3 B0 B1 B2 B3 IA > B OA > B IA < B IA = B #1 OA < B OA = B NC

L L H

A19 B19 L

INPUTS

A5 A6 A7 A8 B5 B6 B7 B8 A0 A1 A2 A3 B0 B1 B2 B3 OA > B #4 IA < B OA < B IA > B IA = B OA = B NC

A10 A11 A12 A13 B10 B11 B12 B13 A0 A1 A2 A3 B0 B1 B2 B3 OA > B #3 OA < B IA < B IA > B IA = B OA = B NC

A15 A16 A17 A18 B15 B16 B17 B18 A0 A1 A2 A3 B0 B1 B2 B3 OA > B #2 OA < B IA < B IA > B IA = B OA = B NC

A4 B4 L

A9 B9 L

A14 B14 L

A0 A1 A2 A3 B0 B1 B2 B3 IA > B OA > B IA < B IA = B #6 OA < B OA = B OUTPUTS

MSB = MOST SIGNIFICANT BIT LSB = LEAST SIGNIFICANT BIT L = LOW LEVEL H = HIGH LEVEL NC = NO CONNECTION

Figure 2. Comparison of Two 24-Bit Words http://onsemi.com
62

SN74LS85
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 – 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 Input HIGH Current A < B, A > B Other Inputs A < B, A > B Other Inputs IIL IOS ICC Input LOW Current A < B, A > B Other Inputs Output Short Circuit Current (Note 1) Power Supply Current – 20 0.5 V µA IOL = 8.0 mA 0.4 Min 2.0 0.8 – 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

IIH

20 60 0.1 0.3 – 0.4 – 1.2 –100 20

VCC = MAX, VIN = 2.7 V

mA

VCC = MAX, VIN = 7.0 V

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Any A or B to A < B, A > B Any A or B to A = B A < B or A = B to A > B A = B to A = B A > B or A = B to A < B Min Typ 24 20 27 23 14 11 13 13 14 11 Max 36 30 45 45 22 17 20 26 22 17 Unit ns ns ns ns ns VCC = 5.0 V CL = 15 pF Test Conditions

AC WAVEFORMS

VIN

1.3 V tPHL

1.3 V tPLH 1.3 V

VIN

1.3 V tPHL

1.3 V tPLH 1.3 V

VOUT

1.3 V

VOUT

1.3 V

Figure 3.

Figure 4.

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63

SN74LS86 Quad 2-Input Exclusive OR Gate
VCC 14 13 12 11 10 9 8

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LOW POWER SCHOTTKY
1 2 3 4 5 6 7 GND

TRUTH TABLE
IN A L L H H B L H L H OUT Z L H H L
14 1

PLASTIC N SUFFIX CASE 646

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 –0.4 8.0 Unit V °C mA mA
14 1

SOIC D SUFFIX CASE 751A

ORDERING INFORMATION
Device SN74LS86N SN74LS86D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel

© Semiconductor Components Industries, LLC, 1999

64

December, 1999 – Rev. 6

Publication Order Number: SN74LS86/D

VIN = VIL or VIH per Truth Table VCC = MAX. VIN = VIH or VIL per Truth Table IOL = 4.8 – 1. IIN = – 18 mA VCC = MIN.0 V VCC = MAX.4 Min 2.7 – 0.65 3. VIN = 0.5 40 V µA mA mA mA mA IOL = 8.0 mA VCC = VCC MIN. IOH = MAX.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.2 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.0 mA 0.SN74LS86 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. VIN = 7.0 0.8 –100 10 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. Other Input LOW Propagation Delay. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay.5 0.25 VO OL Output LOW Voltage 0.7 V VCC = MAX. nor for more than 1 second.0 V CL = 15 pF Test Conditions http://onsemi. VIN = 2. Other Input HIGH Min Typ 12 10 20 13 Max 23 17 30 22 Unit ns ns VCC = 5.35 IIH IIL IOS ICC Input HIGH Current 0.com 65 .

4 8. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. The clocking operation is independent of rise and fall times of the clock waveform. but the output states are unpredictable if SD and CD go HIGH simultaneously. 16 PLASTIC N SUFFIX CASE 648 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition. 6 Publication Order Number: SN74LS109A/D . h (q) = Lower case letters indicate the state of the referenced input i.75 0 Typ 5. h = HIGH Voltage Level L. http://onsemi.0 25 Max 5.com MODE SELECT – TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) * L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H H q q L Q L H H L q q H OUTPUTS LOW POWER SCHOTTKY 16 1 Both outputs will be HIGH while both SD and CD are LOW. LLC. I = LOW Voltage Level X = Don’t Care l.25 70 – 0. 1999 – Rev.0 Unit V °C mA mA SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS109AN SN74LS109AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop The SN74LS109A consists of two high speed completely independent transition clocked JK flip-flops. 1999 66 December. H.

0 mA VCC = VCC MIN.1 0. Clear Output Short Circuit Current (Note 1) Power Supply Current – 20 0. IIN = – 18 mA VCC = MIN.5 20 40 0. K.com 67 . http://onsemi. Clear J.0 0.25 VO OL Output LOW Voltage 0.0 mA 0. K.5 0. Clock Set.0 V mA mA mA VCC = MAX. IOH = MAX. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 2.4 – 0.4 Min 2.2 – 0. VIN = 0. VIN = 7.7 V IIH mA VCC = MAX. Clock Set.35 Input HIGH Current J. Clock Set.7 – 0. nor for more than 1 second.0 V µA IOL = 8.8 – 100 8. K.65 3.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = VIH or VIL per Truth Table IOL = 4.SN74LS109A LOGIC DIAGRAM SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12) Q 6(10) Q 7(9) J 2(14) K 3(13) LOGIC SYMBOL 5 2 4 3 J SD Q CP K C Q D 1 VCC = PIN 16 GND = PIN 8 7 6 14 12 13 11 J SD Q CP K C Q D 15 9 10 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.8 – 1. Clear IIL IOS ICC Input LOW Current J.

0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock Clear Set to Output Clock. Min 25 Typ 33 13 25 25 40 Max Unit MHz ns ns VCC = 5.0 Test Conditions http://onsemi. VCC = 5.0 V) Limits Symbol tW ts th Parameter Clock High Clear.SN74LS109A AC CHARACTERISTICS (TA = 25°C.0 V 50 CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.com 68 . Set Pulse Width Data Setup Time — HIGH Data Setup Time — LOW Hold time Min 25 20 20 5. VCC = 5. Clear.0 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.

0 260 No Restriction 50 pF Unit V °C mA mA k 14 1 SOIC D SUFFIX CASE 751A W 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS122N SN74LS122D SN74LS123N SN74LS123D Package 14 Pin DIP 14 Pin 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. up to 100% Duty Cycle • Internal Timing Resistors on LS122 http://onsemi. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor.4 8.0 25 Max 5. • Overriding Clear Terminates Output Pulse • Compensated for VCC and Temperature Variations • DC Triggered from Active-High or Active-Low Gated Logic Inputs • Retriggerable for Very Long Output Pulses. the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs. The basic pulse width is programmed by selection of external resistance and capacitance values. Once triggered. 6 Publication Order Number: SN74LS122/D . 1999 – Rev. or be reduced by use of the overriding clear.com LOW POWER SCHOTTKY 14 1 PLASTIC N SUFFIX CASE 646 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Rext Cext Rext/Cext Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low External Timing Resistance External Capacitance Wiring Capacitance at Rext/Cext Terminal 5. LLC.0 Min 4.SN74LS122 SN74LS123 Retriggerable Monostable Multivibrators These dc triggered multivibrators feature pulse width control by three methods.25 70 – 0. 1999 69 December.75 0 Typ 5.

SN74LS122 SN74LS123 SN74LS123 (TOP VIEW) (SEE NOTES 1 THRU 4) VCC 16 1 Rext/ 1 Cext Cext 15 14 1Q 13 2Q 12 2 CLR 11 2B 10 2A 9 Q CLR Q 1 1A 2 1B 3 1 CLR 4 1Q 5 2Q Q Q CLR 6 2 Cext 8 7 2 GND Rext/ Cext SN74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4) VCC 14 Rext/ Cext 13 NC 12 Cext 11 NC 10 Rint Q CLR Q 1 A1 2 A2 3 B1 4 B2 5 CLR 6 Q 7 GND Rint 9 Q 8 NC — NO INTERNAL CONNECTION. To obtain variable pulse widths. To use the internal timing resistor of the LS122. 3. connect an external variable resistance between Rint/Cext and VCC.com 70 . For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited. http://onsemi. An external timing capacitor may be connected between Cext and Rext/Cext (positive). 4. connect Rint to VCC. NOTES: 1. 2.

SN74LS122 SN74LS123
LS122 FUNCTIONAL TABLE
INPUTS CLEAR L X X X H H H H H H H ↑ ↑ A1 X H X X L L X X H ↓ ↓ L X A2 X H X X X X L L ↓ ↓ H X L B1 X X L X ↑ H ↑ H H H H H H B2 X X X L H ↑ H ↑ H H H H H OUTPUTS Q L L L L Q H H H H CLEAR L X X H H ↑

LS123 FUNCTIONAL TABLE
INPUTS A X H X L ↓ L B X X L ↑ H H OUTPUTS Q L L L Q H H H

TYPICAL APPLICATION DATA The output pulse tW is a function of the external components, Cext and Rext or Cext and Rint on the LS122. For values of Cext ≥ 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by tW = K Rext Cext where K is nominally 0.45 If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. The Cext terminal of the LS122 and LS123 is an internal connection to ground, however for the best system performance Cext should be hard-wired to ground. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the Rext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be designed into the system for optimum performance to ensure that no false triggering occurs. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if Cext is hard-wired externally to ground, substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. To find the value of K for Cext ≥ 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to change, as can the temperature of the LS123, LS122.

Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in Rext and Cext with temperature are not calculated and included in the graph. As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K, the change in K with respect to Rext is negligible. If Cext ≤ 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K will change for Cext ≤ 1000 pF if VCC and VRC are connected to the same power supply. The pulse width tW in nanoseconds is approximated by tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext In order to trim the output pulse width, it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible. Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept ≥ 1000 pF.

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71

SN74LS122 SN74LS123

WAVEFORMS

RETRIGGER PULSE B INPUT

(See Application Data)

Q OUTPUT tW OUTPUT WITHOUT RETRIGGER

EXTENDING PULSE WIDTH

B INPUT

CLEAR INPUT

CLEAR PULSE

OUTPUT WITHOUT CLEAR PULSE Q OUTPUT

OVERRIDING THE OUTPUT PULSE

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72

SN74LS122 SN74LS123
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 – 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) LS122 Power Supply Current LS123 20 – 20 – 0.4 –100 11 mA VCC = MAX 0.5 20 V µA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 – 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tW min tWQ Parameter Propagation Delay, A to Q g y Propagation Delay, A to Q Propagation Delay, B to Q g y Propagation Delay, B to Q Propagation Delay, Clear to Q g y Propagation Delay, Clear to Q A or B to Q A to B to Q 4.0 Min Typ 23 32 23 34 28 20 116 4.5 Max 33 ns 45 44 ns 56 45 ns 27 200 5.0 ns µs Cext = 1000 pF, Rext = 10 kΩ, CL = 15 pF, RL = 2.0 kΩ Rext = 5.0 kΩ RL = 2.0 kΩ Cext = 0 CL = 15 pF Unit Test Conditions

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits Symbol tW Pulse Width Parameter Min 40 Typ Max Unit ns Test Conditions

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73

SN74LS122 SN74LS123
VCC VRC Rext Cext Cext Rext/ VCC Cext Q CLR 1/2 LS123 B Pin 51 Ω A Q GND 0.1 µF Pout VCC VCC VRC Rext Cext Cext Rext/ VCC CLR Cext Q B2 LS122 B1 A2 Q A1 GND 0.1 µF VCC

Pout

Pin 51 Ω

Figure 1.

Figure 2.

Pin

Pout

tW

RETRIGGER

Figure 3.

10 5K ≤ Rext ≤ 260K EXTERNAL CAPACITANCE, Cext ( µF) 1

0.1

0.01

0.001

0.3

0.35 0.4

K

0.45 0.5

0.55

Figure 4.

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74

SN74LS122 SN74LS123
0.55 VRC = 5 V Cext = 1000 pF 0.5 0.5 – 55°C 0°C 25°C 70°C 0.4 125°C 0.4 125°C 0.4 0°C 0.55 VCC = 5 V Cext = 1000 pF 0.5 – 55°C 0.55 Cext = 1000 pF

– 55°C 25°C

K
0.45

K
0.45 70°C

K
0.45

0°C 25°C 70°C 125°C

0.35 4.5 5 VCC 5.5

0.35 4.5 5 VRC 5.5

0.35 4.5 5 VCC = VRC 5.5

Figure 5. K versus VCC

Figure 6. K versus VRC

Figure 7. K versus VCC and VRC

100000

10000 t W, OUTPUT PULSE WIDTH (ns)

Rext = 260 kΩ Rext = 160 kΩ

1000

100

Rext = 80 kΩ Rext = 40 kΩ Rext = 20 kΩ Rext = 10 kΩ Rext = 5 kΩ 1 10 100 1000

10

Cext, EXTERNAL TIMING CAPACITANCE (pF)

Figure 8.

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75

VCC Rext REMOTE PIN 7 OR 15 Cext PIN 6 OR 14 Rext Figure 10.55 125°C 0.75 5 VCC VOLTS 5.SN74LS122 SN74LS123 0.5 4.65 Cext = 200 pF – 55°C 0.5 4.com 76 . LS123 Remote Trimming Circuit http://onsemi.25 5.6 0°C 25°C 70°C K 0.5 Figure 9.

LS122 Remote Trimming Circuit Without Rext VCC Rext REMOTE PIN 9 PIN 13 PIN 11 Figure 12. LS122 Remote Trimming Circuit with Rint http://onsemi.SN74LS122 SN74LS123 VCC PIN 9 OPEN Rext PIN 13 Cext PIN 11 Rext REMOTE Figure 11.com 77 .

com 1 E 2 D 3 O 4 E 5 D 6 O 7 GND LOW POWER SCHOTTKY LS125A VCC 14 E 13 D 12 O 11 E 10 D 9 O 8 14 1 PLASTIC N SUFFIX CASE 646 1 E 2 D 3 O 4 E 5 D 6 O 7 GND LS126A TRUTH TABLES LS125A INPUTS E L L H D L H X OUTPUT L H (Z) INPUTS E H H L D L H X OUTPUT L H (Z) 14 LS126A 1 SOIC D SUFFIX CASE 751A L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care (Z) = High Impedance (off) ORDERING INFORMATION Device Package 14 Pin DIP 14 Pin 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.SN74LS125A SN74LS126A Quad 3-State Buffers VCC 14 E 13 D 12 O 11 E 10 D 9 O 8 http://onsemi. 1999 – Rev. 6 Publication Order Number: SN74LS125A/D .6 24 Unit V °C mA mA SN74LS125AN SN74LS125AD SN74LS126AN SN74LS126AD © Semiconductor Components Industries.75 0 Typ 5.25 70 – 2. LLC.0 25 Max 5. 1999 78 December.

25 VO OL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 0.0 V CL = 45 pF F RL = 667 Ω Figure 2 Unit Test Conditions tPZL tPHZ tPLZ http://onsemi.7 V VCC = MAX. VCC = 5.65 Min 2. 5 3 Figures 4 5 4. VIN = 2. VIN = 7. IIN = – 18 mA VCC = MIN.0 8.4 V VCC = MAX.0 V VCC = MAX. VOUT = 0.com 79 .SN74LS125A SN74LS126A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.0 12 16 15 21 Max 15 15 ns 18 18 20 ns 25 25 ns 35 20 ns 25 20 ns 25 FIgures 3. nor for more than 1 second.0 V CL = 5 0 pF 5.0 F RL = 667 Ω Figures 3 5 3. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPLH tPHL tPHL tPZH Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time from HIGH Level Output Disable Time from LOW Level Propagation Delay.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0. VIN = 0.8 – 1. Figures 4 5 4. VOUT = 2.0 0. VCC = 5.4 V VCC = MAX.5 V VIN = 0 V.1 Input LOW Current Short Circuit Current (Note 1) LS125A Power Supply Current LS126A 22 – 40 – 0. VE = 4.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.5 20 – 20 20 V µA µA µA mA mA mA IOL = 24 mA 0. g y Data to Output Parameter LS125A LS126A LS125A LS126A LS125A LS126A LS125A LS126A LS125A LS126A LS125A LS126A Min Typ 9.4 –225 20 mA VCC = MAX 0.4 – 0. IOH = MAX.0 7.0 9. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN. VIN = VIL or VIH per Truth Table VCC = MAX.4 0.4 V VCC = MAX VIN = 0 V. VE = 0 V Note 1: Not more than one output should be shorted at a time.

3 V tPLH 1. Figure 2. Figure 4.3 V tPHL 1.3 V VE 1.3 V tPZH 1.3 V VE tPZL VOUT 1.5 V 1.3 V 0.3 V 1.3 V tPHZ > VOH ≈ 1.com 80 .3 V VOUT 1. VE 1.SN74LS125A SN74LS126A VIN VIN 1. SWITCH POSITIONS SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed http://onsemi.3 V VE VOUT Figure 3.3 V VOL 0.3 V tPHL 1.3 V VOUT Figure 1.3 V 1.3 V tPLZ ≈ 1.5 V 1. VCC RL SW1 TO OUTPUT UNDER TEST 5 kΩ SW2 CL Figure 5.3 V tPLH 1.

the gate will respond to the transitions of the other input as shown in Figure 1.0 Unit V °C mA mA ORDERING INFORMATION Device SN74LS132N SN74LS132D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. Each circuit contains a 2-input Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output.com LOW POWER SCHOTTKY 14 1 LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 13 12 11 10 9 8 PLASTIC N SUFFIX CASE 646 14 1 1 2 3 4 5 6 7 GND SOIC D SUFFIX CASE 751A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 81 December. 6 Publication Order Number: SN74LS132/D . 1999 – Rev. they have greater noise margin than conventional NAND Gates. http://onsemi.25 70 – 0. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations. They are capable of transforming slowly changing input signals into sharply defined. LLC. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions. and provide different input threshold voltages for positive and negative-going transitions.0 25 Max 5. Additionally.75 0 Typ 5. As long as one input remains at a more positive voltage than VT+ (MAX).SN74LS132 Quad 2-Input Schmitt Trigger NAND Gate The SN74LS132 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. jitter-free output signals.4 8.

9 8.4 V VCC = MAX.6 0.1 Input LOW Current Output Short Circuit Current Power Supply Current Total. IOH = – 400 µA. VIN = VIL VCC = MIN.com 82 . OUTPUT VOLTAGE (VOLTS) 4 VCC = 5 V TA = 25°C 3 2 1 0 0 0.65 – 1.5 V V 2. INPUT VOLTAGE (VOLTS) 1. VIN = VT+ VCC = 5.14 – 0. IOL = 4.4 0.0 mA. IIN = – 18 mA VCC = MIN.2 VIN.0 V. VIN = 2.2 –100 11 14 Note 1: Not more than one output should be shorted at a time.0 V VCC = MIN. Input to Output Min Typ Max 22 22 Unit ns ns Test Conditions VCC = 5.95 1.7 3.8 2 Figure 1. Output LOW (1) Min 1.0 V VCC = MAX.35 Input Current at Positive-Going Threshold Input Current at Negative-Going Threshold Input HIGH Current 0. VOUT = 0 V VCC = MAX.4 0. Output HIGH Total.0 1. VIN = 2.4 – 20 5. nor for more than 1 second.5 V 0. VIN = 0.5 0.0 V VCC = 5. VIN = 0 V VCC = MAX.0 mA. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay.7 V VCC = MAX.4 Typ Max 2.5 V V mA mA – 0.0 V VCC = 5.8 – 0. VIN = 4.4 0. Input to Output Turn-On Delay.0 V. VIN = VT– VCC = MAX. VIN = 2.0 V VCC = MIN.25 0.0 V CL = 15 pF http://onsemi.1 Unit V V V Test Conditions VCC = 5.SN74LS132 5 VO.18 20 µA mA mA mA mA mA – 0. IOL = 8. VIN versus VOUT Transfer Function DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT + – VT– VIK VOH VO OL IT+ IT– IIH IIL IOS ICC Parameter Positive-Going Threshold Voltage Negative-Going Threshold Voltage Hysteresis Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage 0. VIN = 7.0 V VCC = 5.

7 – 55° VT– ∆ VT 0° 25° 75° TA. HYSTERESIS (VOLTS) 1.6 V 0.5 1.4 0 4.SN74LS132 3V VIN 0V tPHL tPLH 1.6 1.5 4.7 1.com 83 . Threshold Voltage and Hysteresis versus Power Supply Voltage V T.3 1.8 V VOUT 1.5 Figure 3.25 VCC.3 V Figure 2. THRESHOLD VOLTAGE (VOLTS) ∆ V T.9 0. AMBIENT TEMPERATURE (°C) VT+ 125° Figure 4. AC Waveforms V T.8 ∆ VT 0. THRESHOLD VOLTAGE (VOLTS) ∆ V T. Threshold Voltage and Hysteresis versus Temperature http://onsemi.75 5 5. HYSTERESIS (VOLTS) 2 TA = 25°C VT+ 1.1 0. POWER SUPPLY VOLTAGE (VOLTS) 5.2 VT– 0.9 1.3 V 1.

1999 84 December.com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS138N SN74LS138D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. • Demultiplexing Capability • Multiple Input Enable for Easy Expansion • Typical Power Dissipation of 32 mW • Active Low Mutually Exclusive Outputs • Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.0 25 Max 5.75 0 Typ 5. 6 Publication Order Number: SN74LS138/D . This device is ideally suited for high speed bipolar memory chip select address decoding.4 8.0 Unit V °C mA mA 16 1 http://onsemi.SN74LS138 1-of-8 Decoder/ Demultiplexer The LSTTL / MSI SN74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. LLC. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.25 70 – 0. 1999 – Rev.

L.25 U.L. 10 U. 0.6 mA LOW.SN74LS138 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 O0 15 O1 14 O2 13 O3 12 O4 11 O5 10 O6 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 0. 1 A0 2 A1 3 A2 4 E1 5 E2 6 E3 7 O7 8 GND LOADING (Note a) PIN NAMES A0 – A2 E1.L.L.5 U.5 U. 0.5 U.L. LOW 0. 0.com 85 . 5 U.L.25 U.L.) = 40 mA HIGH/1.L. E2 E3 O0 – O7 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs HIGH 0.25 U.L. NOTES: a) 1 TTL Unit Load (U. LOGIC SYMBOL 1 2 3 456 1 23 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 15 14 13 12 11 10 9 7 VCC = PIN 16 GND = PIN 8 http://onsemi.

SN74LS138 LOGIC DIAGRAM A2 3 2 A1 1 A0 4 E1 E2 E3 5 6 VCC = PIN 16 GND = PIN 8 = Pin Numbers 7 9 10 11 12 13 14 15 O7 O6 O5 O4 O3 O2 O1 O0 http://onsemi.com 86 .

com 87 . (See Figure a. E2) and one active HIGH (E3). This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four LS138s and one inverter. A2) and when enabled provides eight mutually exclusive active LOW Outputs (O0 – O7).) The LS138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. two active LOW (E1. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state. The decoder accepts three binary weighted inputs (A0.SN74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with the low power Schottky barrier diode process. The LS138 features three Enable inputs. TRUTH TABLE INPUTS E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H OUTPUTS O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care A0 A1 A2 LS04 A3 A4 H 123 A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E A0 A1 A2 LS138 O0 O1 O2 O3 O4 O5 O6 O7 123 E O0 O31 Figure a http://onsemi. A1.

0 V CL = 15 pF AC WAVEFORMS VIN tPLH 1.3 V 1.4 Min 2.7 – 0. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 7. http://onsemi.3 V Figure 1.4 –100 10 0.8 – 1.5 20 V µA mA mA mA mA IOL = 8.3 V tPLH 1.3 V tPHL 1. nor for more than 1 second. VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.3 V 1. AC CHARACTERISTICS (TA = 25°C) Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address to Output Propagation Delay Address to Output Propagation Delay E1 or E2 Enable to Output Propagation Delay E3 Enable to Output Levels of Delay 2 2 3 3 2 2 3 3 Limits Min Typ 13 27 18 26 12 21 17 25 Max 20 41 27 39 18 32 26 38 Unit ns ns ns ns Test Conditions VCC = 5.35 IIH IIL IOS ICC Input HIGH Current 0. IIN = – 18 mA VCC = MIN.3 V VOUT VIN 1. Figure 2. VIN = VIH or VIL per Truth Table IOL = 4.25 VO OL Output LOW Voltage 0. IOH = MAX.7 V VCC = MAX.0 0.0 mA 0.3 V VOUT 1. VIN = 2.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.0 V VCC = MAX.SN74LS138 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.3 V tPHL 1.0 mA VCC = VCC MIN.65 3.com 88 .5 0.

4 8. 1999 – Rev.SN74LS139 Dual 1-of-4 Decoder/ Demultiplexer The LSTTL/MSI SN74LS139 is a high speed Dual 1-of-4 Decoder/Demultiplexer. each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each decoder has an active LOW Enable input which can be used as a data input for a 4-output demultiplexer.0 Unit V °C mA mA 16 PLASTIC N SUFFIX CASE 648 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS139N SN74LS139D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. The device has two independent decoders. 1999 89 December.75 0 Typ 5.25 70 – 0. Each half of the LS139 can be used as a function generator providing all four minterms of two variables. 6 Publication Order Number: SN74LS139/D .com LOW POWER SCHOTTKY • • • • • • Schottky Process for High Speed Multifunction Capability Two Completely Independent 1-of-4 Decoders Active Low Mutually Exclusive Outputs Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 16 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.0 25 Max 5. LLC. http://onsemi. The LS139 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.

5 U.L. 1 Ea 2 A0a 3 A1a 4 O0a 5 O1a 6 O2a 7 O3a 8 GND LOADING (Note a) PIN NAMES A0. 0.L.25 U. A1 E O0 – O3 Address Inputs Enable (Active LOW) Input Active LOW Outputs HIGH 0.L.com 90 . LOW 0.L. 0.25 U.6 mA LOW. 10 U.) = 40 mA HIGH/1.L.L. 5 U.5 U. NOTES: a) 1 TTL Unit Load (U. LOGIC SYMBOL 1 2 3 15 14 13 E A0 A1 E A0 A1 DECODER a O0 O1 O2 O3 DECODER b O0 O1 O2 O3 4 5 6 7 12 11 10 9 VCC = PIN 16 GND = PIN 8 http://onsemi.L.SN74LS139 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 A0b 14 A1b 13 O0b 12 O1b 11 O2b 10 O3b 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

The device has two independent decoders. When E is HIGH all outputs are forced HIGH. TRUTH TABLE INPUTS E H L L L L A0 X L H L H A1 X L L H H O0 H L H H H OUTPUTS O1 H H L H H O2 H H H L H O3 H H H H L E A0 A1 E A0 A1 E A0 A1 E A0 A1 O0 E A0 A1 E A0 A1 E A0 A1 E A0 A1 O0 O1 O1 O2 O2 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care O3 O3 Figure a http://onsemi. These four minterms are useful in some applications.com 91 . each of which accept two binary weighted inputs (A0. a. Each half of the LS139 generates all four minterms of two variables. and thereby reducing the number of packages required in a logic network.SN74LS139 LOGIC DIAGRAM Ea 1 2 A0a A1a 3 15 Eb A0b A1b 14 13 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 5 6 7 12 11 10 9 O0a O1a O2a O3a O0b O1b O2b O3b FUNCTIONAL DESCRIPTION The LS139 is a high speed dual 1-of-4 decoder/ demultiplexer fabricated with the Schottky barrier diode process. replacing multiple gate functions as shown in Fig. A1) and provide four mutually exclusive active LOW outputs (O0 – O3). The enable can be used as the data input for a 4-output demultiplexer application. Each decoder has an active LOW Enable (E).

nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address to Output Propagation Delay Address to Output Propagation Delay Enable to Output Levels of Delay 2 2 3 3 2 2 Limits Min Typ 13 22 18 25 16 21 Max 20 33 29 38 24 32 Unit ns ns ns VCC = 5.0 V VCC = MAX.65 3.4 –100 11 V µA mA mA mA mA IOL = 8. IIN = – 18 mA VCC = MIN.0 0. Figure 2.0 mA 0. VIN = 0.7 V VCC = MAX. http://onsemi.3 V VOUT 1.3 V tPLH 1.3 V tPHL 1.3 V 1.0 mA VCC = VCC MIN.8 – 1.7 – 0.3 V VOUT VIN 1.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.3 V 1. VIN = 2. VIN = 7.3 V Figure 1.3 V tPHL 1. VIN = VIH or VIL per Truth Table IOL = 4.4 Min 2. IOH = MAX.35 IIH IIL IOS ICC Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 0.0 V CL = 15 pF Test Conditions AC WAVEFORMS VIN tPLH 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.SN74LS139 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.25 VO OL Output LOW Voltage 0.5 0. VIN = VIL or VIH per Truth Table VCC = MAX.5 20 0.1 – 0.com 92 .

Typical power dissipation is 35 mW.SN74LS145 1-of-10 Decoder/Driver Open-Collector The SN74LS145. LLC.25 70 15 24 Unit V °C V mA 16 LOW POWER SCHOTTKY 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS145N SN74LS145D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.com • Low Power Version of 74145 • Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Voltage – High Output Current – Low Min 4. It is designed for use as indicator/relay drivers or as an open-collector logic circuit driver. 6 Publication Order Number: SN74LS145/D . Each of the high breakdown output transistors will sink up to 80 mA of current. 1-of-10 Decoder/Driver.75 0 Typ 5. is designed to accept BCD inputs and provide appropriate outputs to drive 10-digit incandescent displays.0 25 Max 5. 1999 – Rev. 1999 93 December. http://onsemi. All outputs remain off for all invalid binary input conditions. This device is fully compatible with all TTL families.

5 U. 15 U. P1.L.L.L. P2. P3 Q0 – Q9 BCD Inputs Outputs HIGH 0.SN74LS145 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P0 15 P1 14 P2 13 P3 12 Q9 11 Q8 10 Q7 9 1 Q0 2 Q1 3 Q2 4 Q3 5 Q4 6 Q5 7 8 Q6 GND LOADING (Note a) PIN NAMES P0.L.com 94 .25 U.6 mA LOW. LOGIC SYMBOL 15 14 13 12 P0 P1 P2 P3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 1 2 3 4 5 6 7 9 10 11 VCC = PIN 16 GND = PIN 8 http://onsemi. NOTES: a) 1 TTL Unit Load (U. Open Collector LOW 0.) = 40 mA HIGH/1.

com 95 .SN74LS145 LOGIC DIAGRAM INPUTS P0 P1 P2 P3 INPUT INVERTERS 0 0 1 1 2 2 3 3 DECODE/DRIVER GATES Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 OUTPUTS TRUTH TABLE INPUTS P3 L L L L L L L L H H H H H H H H P2 L L L L H H H H L L L L H H H H P1 L L H H L L H H L L H H L L H H P0 L H L H L H L H L H L H L H L H Q0 L H H H H H H H H H H H H H H H Q1 H L H H H H H H H H H H H H H H Q2 H H L H H H H H H H H H H H H H Q3 H H H L H H H H H H H H H H H H OUTPUTS Q4 H H H H L H H H H H H H H H H H Q5 H H H H H L H H H H H H H H H H Q6 H H H H H H L H H H H H H H H H Q7 H H H H H H H L H H H H H H H H Q8 H H H H H H H H L H H H H H H H Q9 H H H H H H H H H L H H H H H H H = HIGH Voltage Level L = LOW Voltage Level http://onsemi.

7 V VCC = MAX.com 96 .4 13 Typ Max Unit V V V µA V V V µA mA mA mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. Figure 2.4 V VCC = MAX.25 Output LOW Voltage 0.3 V tPHL 1. IIN = – 18 mA VCC = MIN.5 3.5 250 0.3 V Figure 1.0 V CL = 45 pF AC WAVEFORMS VIN 1.8 – 1.3 V tPLH 1.4 0.0 V VCC = MAX. VIN = 2.35 2.3 V tPHL 1.SN74LS145 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0. VIN = GND AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPHL tPLH Propagation Delay Pn Input to Qn Output Parameter Min Typ Max 50 50 Unit ns Test Conditions VCC = 5.3 V VOUT 1. VIN = 0.3 IIH IIL ICC Input HIGH Current Input LOW Current Power Supply Current – 0.3 V tPLH 1. VIN = 7.3 V VOUT 1.3 V VIN 1. VIN = VIL or VIH per Truth T bl T h Table VCC = MAX.0 20 0. http://onsemi. VOH = MAX IOL = 12 mA IOL = 24 mA IOL = 80 mA VCC = VCC MIN.1 – 0.65 Min 2.0 0.

SN74LS147 SN74LS148 10-Line-to-4-Line and 8-Line-to-3-Line Priority Encoders The SN74LS147 and the SN74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without needing external circuitry. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. LLC.0 Unit V °C mA mA http://onsemi.4 8. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level.0 25 Max 5. 1999 – Rev. 1999 97 December.25 70 – 0. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal).75 0 Typ 5. 6 Publication Order Number: SN74LS147/D .com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS147N SN74LS147D SN74LS148N SN74LS148D Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. Both devices have data inputs and outputs which are active at the low logic level.

SN74LS147 SN74LS148 SN74LS147 (TOP VIEW) OUTPUT VCC 16 NC 15 D 14 D 4 5 1 4 2 5 6 3 6 INPUTS 7 4 7 8 5 8 C 6 C B 7 B 8 GND 3 13 3 INPUTS 2 12 2 1 11 1 9 10 9 A OUTPUT A 9 OUTPUTS SN74LS148 (TOP VIEW) OUTPUTS VCC 16 EO 15 EO 4 5 1 4 2 5 6 3 6 INPUTS 7 4 7 EI 5 E1 A2 6 A2 GS 14 GS 3 13 3 INPUTS 2 12 2 1 11 1 0 10 0 A0 A1 7 A1 8 GND OUTPUT A0 9 OUTPUTS http://onsemi.com 98 .

com 99 . L = LOW Logic Level. X = Irrelevant FUNCTIONAL BLOCK DIAGRAMS 1 (11) 0 (12) (9) (13) 2 (1) 3 (2) (7) B 4 (3) 5 (4) (6) A 1 (10) (15) (11) (14) EO GS 2 3 (12) (8) (13) (1) (7) A0 4 5 6 7 (2) A1 (3) C 6 (4) 7 (6) 8 9 (5) (10) (14) A2 D (5) EI SN74LS147 SN74LS148 http://onsemi.SN74LS147 SN74LS148 SN74LS147 FUNCTION TABLE INPUTS 1 H X X X X X X X X L 2 H X X X X X X X L H 3 H X X X X X X L H H 4 H X X X X X L H H H 5 H X X X X L H H H H 6 H X X X L H H H H H 7 H X X L H H H H H H 8 H X L H H H H H H H 9 H L H H H H H H H H D H L L H H H H H H H OUTPUTS C H H H L L L L H H H B H H H L L H H L L H A H L H L H L H L H L EI H L L L L L L L L L 0 X H X X X X X X X L 1 X H X X X X X X L H 2 X H X X X X X L H H 3 X H X X X X L H H H SN74LS148 FUNCTION TABLE INPUTS 4 X H X X X L H H H H 5 X H X X L H H H H H 6 X H X L H H H H H H 7 X H L H H H H H H H A2 H H L L L L H H H H OUTPUTS A1 H H L L H H L L H H A0 H H L H L H L H L H GS H H L L L L L L L L EO H L H H H H H H H H H = HIGH Logic Level.

4 V VCC = MAX VCC = MAX.0 V mA mA mA mA VCC = MAX.8 – 100 17 20 V µA IOL = 8.0 mA VCC = VCC MIN.com 100 . VIN = 7.8 – 1. VIN = VIH or VIL per Truth Table IOL = 4.7 V IIH mA VCC = MAX.4 Min 2. Inputs 7 & E1 = GND All Other Inputs = 4.5 20 40 0. nor for more than 1 second.7 – 0. VIN = VIL or VIH per Truth Table VCC = MAX.SN74LS147 SN74LS148 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. http://onsemi.1 0.4 – 0.5 0. All Inputs = 4.65 3. VIN = 0.5 V Note 1: Not more than one output should be shorted at a time. IOH = MAX.35 Input HIGH Current All Others Inputs 1 – 7 (LS148) All Others Inputs 1 – 7 (LS148) IIL IOS ICCH ICCL Input LOW Current All Others Inputs 1 – 7 (LS148) Short Circuit Current (Note 1) Power Supply Current Output HIGH Output LOW – 20 0.0 0.2 – 0. IIN = – 18 mA VCC = MIN.25 VO OL Output LOW Voltage 0. VIN = 2.5 V VCC = MAX.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 mA 0.

A1.SN74LS147 SN74LS148 AC CHARACTERISTICS (VCC = 5. A1.0 kΩ Unit Test Conditions http://onsemi.hase In-phase output Min Typ 14 15 20 16 7. A0 A1 or A2 Limits Waveform In-phase output Out-of-phase output Out-of-phase output In-phase output In-phase output In-phase output In. A1. F RL = 2.0 V. A0 A1 or A2 0 thru 7 GS 0 thru 7 EO 1 thru 7 A0. A0 A1 or A2 From (Input) 1 thru 7 To (Output) A0. TA = 25°C) SN74LS147 Symbol tPLH tPHL tPLH tPHL Any Any From (Input) Any To (Output) Any Limits Waveform In-phase output Out-of-phase output Min Typ 12 12 21 15 Max 18 ns 18 33 ns 23 CL = 15 pF.0 16 12 12 14 12 28 30 Max 18 ns 25 36 ns 29 18 ns 40 55 ns 21 25 ns 25 17 ns 36 21 40 45 ns (LS148) CL = 15 pF.0 kΩ Unit Test Conditions SN74LS148 Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL EI EO EI GS EI A0.com 101 . RL = 2.0 25 35 9.

25 70 – 0. • • • • • http://onsemi.75 0 Typ 5.0 25 Max 5. 1999 – Rev. Both assertion and negation outputs are provided. It provides. 1999 102 December. 6 Publication Order Number: SN74LS151/D . the ability to select one bit of data from up to eight sources. The LS151 can be used as a universal function generator to generate any logic function of four variables.4 8.com Schottky Process for High Speed Multifunction Capability On-Chip Select Logic Decoding Fully Buffered Complementary Outputs Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. LLC. in one package.0 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS151N SN74LS151D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.SN74LS151 8-Input Multiplexer The TTL / MSI SN74LS151 is a high speed 8-input Digital Multiplexer.

SN74LS151 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 I4 15 I5 14 I6 13 I7 12 S0 11 S1 10 S2 9 1 I3 2 I2 3 I1 4 I0 5 Z 6 Z 7 E 8 GND LOADING (Note a) PIN NAMES S0 – S2 E I0 – I7 Z Z Select Inputs Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output Complementary Multiplexer Output HIGH 0.5 U. NOTES: a) 1 TTL Unit Load (U.com 103 .L.L.6 mA LOW. 0.L.L.L. 5 U. LOGIC SYMBOL 7 4 3 2 1 15 14 13 12 E I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2 Z Z 6 5 11 10 9 VCC = PIN 16 GND = PIN 8 http://onsemi.L. LOW 0. 10 U.25 U. b) The Output LOW drive factor is 5 U.L.L.5 U.L. 0.) = 40 mA HIGH/1.L.L. 0.L.25 U. for Commercial (74) Temperature Ranges. 0.5 U. 10 U.25 U. 5 U.

When it is not activated. to select from eight sources of data or control information. Both assertion and negation outputs are provided. 8-position switch with the switch position controlled by the state of three Select inputs. The logic function provided at the output is: Z = E ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + ⋅ I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ S2 + I3 ⋅ S0 ⋅ S1 ⋅ S2 + I4 ⋅ S0 ⋅ S1 ⋅ S2 + I5 ⋅ S0 ⋅ S1 ⋅ S2 + I6 ⋅ S0 ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2). S2. The Enable input (E) is active LOW. S1. By proper manipulation of the inputs. S0. in one package. The LS151 provides the ability.SN74LS151 LOGIC DIAGRAM I0 S2 S1 11 9 10 4 I1 3 I2 2 I3 1 I4 15 I5 14 I6 13 I7 12 S0 7 E VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 6 5 Z Z FUNCTIONAL DESCRIPTION The LS151 is a logical implementation of a single pole. the LS151 can provide any logic function of four variables and its negation.com 104 . the negation output is HIGH and the assertion output is LOW regardless of all other inputs. TRUTH TABLE E H L L L L L L L L L L L L L L L L S2 X L L L L L L L L H H H H H H H H S1 X L L L L H H H H L L L L H H H H S0 X L L H H L L H H L L H H L L H H I0 X L H X X X X X X X X X X X X X X I1 X X X L H X X X X X X X X X X X X I2 X X X X X L H X X X X X X X X X X I3 X X X X X X X L H X X X X X X X X I4 X X X X X X X X X L H X X X X X X I5 X X X X X X X X X X X L H X X X X I6 X X X X X X X X X X X X X L H X X I7 X X X X X X X X X X X X X X X L H Z H H L H L H L H L H L H L H L H L Z L L H L H L H L H L H L H L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care http://onsemi.

VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.3 V VOUT 1. VIN = 7.3 V VOUT 1.7 – 0.0 0.SN74LS151 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.5 0.0 mA VCC = VCC MIN. IOH = MAX. nor for more than 1 second.8 – 1. VIN = VIL or VIH per Truth Table VCC = MAX.25 VO OL Output LOW Voltage 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Select to Output Z Propagation Delay Select to Output Z Propagation Delay Enable to Output Z Propagation Delay Enable to Output Z Propagation Delay Data to Output Z Propagation Delay Data to Output Z Min Typ 27 18 14 20 26 20 15 18 20 16 13 12 Max 43 30 23 32 42 32 24 30 32 26 21 20 Unit ns ns ns ns ns ns Test Conditions VCC = 5.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.com 105 . IIN = – 18 mA VCC = MIN.3 V Figure 1.5 20 0. VIN = VIH or VIL per Truth Table IOL = 4.3 V tPHL 1.3 V VIN 1.0 V VCC = MAX.3 V tPLH 1.4 – 100 10 V µA mA mA mA mA 0.7 V VCC = MAX.4 Min 2. http://onsemi. VIN = 2. Figure 2.1 – 0.35 IIH IIL IOS ICC Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 0.65 3.0 mA IOL = 8.0 V CL = 15 pF AC WAVEFORMS VIN 1.3 V tPHL tPLH 1.3 V 1.

SN74LS153 Dual 4-Input Multiplexer The LSTTL / MSI SN74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section.0 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS153N SN74LS153D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. The LS153 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.75 0 Typ 5. 1999 106 December. http://onsemi. 6 Publication Order Number: SN74LS153/D . The two buffered outputs present data in the true (non-inverted) form.4 8. the LS153 can generate any two functions of three variables. LLC. 1999 – Rev.25 70 – 0.0 25 Max 5. It can select two bits of data from four sources. In addition to multiplexer operation.com • • • • Multifunction Capability Non-Inverting Outputs Separate Enable for Each Multiplexer Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.

5 U.5 U. LOGIC SYMBOL 1 6 5 4 3 10 11 12 13 15 I0b I1b I2b I3b Eb 14 2 Ea I0a I1a I2a I3a S0 Sa Za 7 Zb 9 VCC = PIN 16 GND = PIN 8 http://onsemi.L. LOW 0.L.25 U.com 107 . 0. 5 U.) = 40 mA HIGH/1.L. I1 Z Common Select Input Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output HIGH 0.L.SN74LS153 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.6 mA LOW.L.L. NOTES: a) 1 TTL Unit Load (U. 10 U. 0. 1 Ea 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND LOADING (Note a) PIN NAMES S0 E I0. 0.L.25 U.5 U. 0.25 U.L.L.

Zb) are forced LOW. The LS153 is the logic implementation of a 2-pole. It can select two bits of data from up to four sources under the control of the common Select Inputs (S0. where the position of the switch is determined by the logic levels supplied to the two Select Inputs. S1). Schottky barrier diode process for high speed. This is useful for implementing highly irregular random logic. the corresponding outputs (Za. The logic equations for the outputs are shown below.com 108 . A less obvious application is a function generator. Za = Ea ⋅ (I0a ⋅ S1 ⋅ S0 + I1a ⋅ S1 ⋅ S0 + I2a ⋅ S1 ⋅ S0 + I3a ⋅ S1 ⋅ S0) Zb = Eb ⋅ (I0b ⋅ S1 ⋅ S0 + I1b ⋅ S1 ⋅ S0 + I2b ⋅ S1 ⋅ S0 + I3b ⋅ S1 ⋅ S0) The LS153 can be used to move data from a group of registers to a common output bus. TRUTH TABLE SELECT INPUTS S0 X L L H H L L H H S1 X L L L L H H H H E H L L L L L L L L INPUTS (a or b) I0 X L H X X X X X X I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT Z L L H L H L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care http://onsemi. When the Enables (Ea. Eb) are HIGH. Eb) which can be used to strobe the outputs independently. The two 4-input multiplexer circuits have individual active LOW Enables (Ea. The LS153 can generate two functions of three variables. The particular register from which the data came would be determined by the state of the Select Inputs. 4-position switch.SN74LS153 LOGIC DIAGRAM Ea I0a 1 6 5 I1a 4 I2a 3 I3a 2 S1 14 S0 10 I0b 11 I1b 12 I2b 13 I3b Eb 15 7 Za VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 9 Zb FUNCTIONAL DESCRIPTION The LS153 is a Dual 4-input Multiplexer fabricated with Low Power.

SN74LS153 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.3 V tPHL 1.3 V VOUT 1.0 0. Figure 2. http://onsemi. VIN = VIH or VIL per Truth Table IOL = 4.3 V VIN 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.7 V VCC = MAX.25 VO OL Output LOW Voltage 0. VIN = 2.3 V Figure 1.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.3 V tPLH 1.0 mA VCC = VCC MIN. VIN = VIL or VIH per Truth Table VCC = MAX.3 V VOUT 1.4 Min 2.7 – 0.0 V VCC = MAX.3 V tPHL 1.35 IIH IIL IOS ICC Input HIGH Current 0.0 mA 0.com 109 .65 3.3 V tPLH 1.5 0.8 – 1. IIN = – 18 mA VCC = MIN. VIN = 7. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Data to Output Propagation Delay Select to Output Propagation Delay Enable to Output Min Typ 10 17 19 25 16 21 Max 15 26 29 38 24 32 Unit ns ns ns Figure 2 Figure 1 Figure 2 VCC = 5.4 – 100 10 0. nor for more than 1 second.0 V CL = 15 pF Test Conditions AC WAVEFORMS VIN 1. IOH = MAX.5 20 V µA mA mA mA mA IOL = 8.

The LS156 is fabricated with the Schottky barrier diode process for high speed and are completely compatible with all ON Semiconductor TTL families. The LS156 has open collector outputs for wired-OR (DOT-AND) decoding and function generator applications. If the Enable functions are satisfied. Decoder “b” has two active LOW Enable inputs. one output of each decoder will be LOW as selected by the address inputs.5 8. This device has two decoders with common 2-bit Address inputs and separate gated Enable inputs. 0 Publication Order Number: SN74LS156/D .SN74LS156 Dual 1-of-4 Decoder/ Demultiplexer The SN74LS156 is a high speed Dual 1-of-4 Decoder/ Demultiplexer. 1999 110 December.com LS156–OPEN–COLLECTOR LOW POWER SCHOTTKY • • • • • • Schottky Process for High Speed Multifunction Capability Common Address Inputs True or Complement Data Demultiplexing Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 16 1 PLASTIC N SUFFIX CASE 648 GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Voltage – High Output Current – Low Min 4.75 0 Typ 5.25 70 5.0 25 Max 5. LLC. 1999 – Rev.0 Unit V °C V mA 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS156N SN74LS156D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. Decoder “a” has an Enable gate with one active HIGH and one active LOW input. http://onsemi.

LOGIC SYMBOL 1 2 13 3 14 15 E DECODER a 0 1 2 3 A0 A1 A0 A1 0 1 E DECODER b 2 3 7 6 5 4 9 10 11 12 VCC = PIN 16 GND = PIN 8 http://onsemi. LOW 0.L.25 U.5 U.L.L. 0. 10 U.L. A1 Ea. 1 Ea 2 Ea 3 A1 4 O3a 5 O2a 6 O1a 7 O0a 8 GND LOADING (Note a) PIN NAMES A0. 0.L.L. 5 U.com 111 .25 U.L.SN74LS156 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 Eb 14 A0 13 O3b 12 O2b 11 O1b 10 O0b 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.5 U.6 mA LOW.) = 40 mA HIGH/1. 0.5 U.L. Eb Ea O0 – O3 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs HIGH 0.L. 0. NOTES: a) 1 TTL Unit Load (U.25 U.

E = Eb + Eb E A0 A1 E A0 A1 E A0 A1 E A0 A1 E O0 A0 A1 E O1 A0 A1 E O2 A0 A1 E O3 A0 A1 O0 O1 O2 O3 Figure a TRUTH TABLE ADDRESS A0 X X L H L H A1 X X L L H H ENABLE “a” Ea L X H H H H Ea X H L L L L O0 H H L H H H OUTPUT “a” O1 H H H L H H O2 H H H H L H O3 H H H H H L ENABLE “b” Eb H X L L L L Eb X H L L L L O0 H H L H H H OUTPUT “b” O1 H H H L H H O2 H H H H L H O3 H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care http://onsemi. all outputs of that decoder are HIGH. A1) and provides four mutually exclusive active LOW outputs (O0 – O3). The LS156 has the further advantage of being able to AND the minterm functions by tying outputs together. These four minterms are useful in some applications replacing multiple gate functions as shown in Fig. The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by tying Ea to Eb and relabeling the common connection as (A2). f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) where E = Ea + Ea.SN74LS156 LOGIC DIAGRAM Ea Ea 1 2 13 A0 A1 3 14 Eb Eb 15 7 6 5 4 9 10 11 12 O0a O1a O2a O3a O0b O1b O2b O3b VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with common Address inputs and separate gated Enable inputs. a. Decoder “a” can accept either true or complemented data by using the Ea or Ea inputs respectively. Each decoder section has a 2-input enable gate. If the Enable requirements of each decoder are not met.com 112 . each decoder section accepts the binary weighted Address inputs (A0. The enable gate for Decoder “a” requires one active HIGH input and one active LOW input (Ea•Ea). The other Eb and Ea are connected together to form the common enable. In demultiplexing applications. The enable gate for Decoder “b” requires two active LOW inputs (Eb•Eb). The LS156 can be used to generate all four minterms of two variables. When enabled. Any number of terms can be wired-AND as shown below.

IIN = – 18 mA VCC = MIN. VIN = VIL or VIH per Truth Table VCC = MAX.1 Input LOW Current Power Supply Current – 0.3 V tPHL 1.3 V VIN 1.0 mA VCC = VCC MIN.3 V VOUT 1. http://onsemi. VIN = 0.0 V CL = 15 pF RL = 2. Figure 2.7 V VCC = MAX.0 kΩ Test Conditions AC WAVEFORMS VIN 1.4 Typ Max Unit V V V µA V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.3 V tPHL 1. VIN = 7.0 0. Ea or Eb to Output Propagation Delay Address to Output Propagation Delay Ea to Output Min Typ 25 34 31 34 32 32 Max 40 51 46 51 48 48 Unit ns ns ns Figure 1 Figure 2 Figure 1 VCC = 5.65 Min 2.com 113 .3 V tPLH 1.35 IIH IIL ICC Input HIGH Current 0. VOH = MAX IOL = 4.25 Output LOW Voltage 0.4 10 0.8 – 1.3 V Figure 1.5 100 0.SN74LS156 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VO OL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0. VIN = 2.3 V VOUT 1.4 V VCC = MAX AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address.0 V VCC = MAX.3 V tPLH 1.0 mA – 0.5 20 V µA mA mA mA IOL = 8.

LLC. 1999 114 December.com • • • • • • Schottky Process for High Speed Multifunction Capability Non-Inverting Outputs Input Clamp Diodes Limit High Speed Termination Effects Special Circuitry Ensures Glitch Free Multiplexing ESD > 3500 Volts 16 LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. The LS157 can also be used to generate any four of the 16 different functions of two variables.0 25 Max 5. The four buffered outputs present the selected data in the true (non-inverted) form. 6 Publication Order Number: SN74LS157/D . Four bits of data from two sources can be selected using the common Select and Enable inputs.0 Unit V °C mA mA 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS157N SN74LS157D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. The LS157 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. 1999 – Rev.75 0 Typ 5.SN74LS157 Quad 2-Input Multiplexer The LSTTL / MSI SN74LS157 is a high speed Quad 2-Input Multiplexer.4 8. http://onsemi.25 70 – 0.

L.L.L. NOTES: a) 1 TTL Unit Load (U. 0.L.5 U.L.com 115 . 0.6 mA LOW.L.0 U.0 U. 0.L. 5 U.5 U. 1 S 2 I0a 3 I1d 4 Za 5 I0b 6 I1b 7 Zb 8 GND LOADING (Note a) PIN NAMES S E I0a – I0d I1a – I1d Za – Zd Common Select Input Enable (Active LOW) Input Data Inputs from Source 0 Data Inputs from Source 1 Multiplexer Outputs HIGH 1. 0. LOGIC SYMBOL 15 2 3 5 6 14 13 11 10 E I0a I1a I0b I1b I0c I1c I0d I1d 1 S Za Zb Zc Zd 4 7 12 9 VCC = PIN 16 GND = PIN 8 http://onsemi.25 U. 1.L.L.) = 40 mA HIGH/1.L.SN74LS157 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 0.5 U. LOW 0.25 U.L.5 U. 10 U.

2-position switch where the position of the switch is determined by the logic levels supplied to the Select Input. When E is HIGH. TRUTH TABLE ENABLE E H L L L L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care SELECT INPUT S X H H L L I0 X X X L H INPUTS I1 X L H X X OUTPUT Z L L H L H http://onsemi.com 116 . The LS157 can generate any four of the 16 different functions of two variables with one variable common. A less obvious use is as a function generator. This is useful for implementing highly irregular logic. The particular register from which the data comes is determined by the state of the Select Input. The logic equations for the outputs are: Za = E ⋅ (I1a ⋅ S + I0a ⋅ S) Zc = E ⋅ (I1c ⋅ S + I0c ⋅ S) Zb = E ⋅ (I1b ⋅ S + I0b ⋅ S) Zd = E ⋅ (I1d ⋅ S + I0d ⋅ S) A common use of the LS157 is the moving of data from two groups of registers to four common output busses. all of the outputs (Z) are forced LOW regardless of all other inputs. The LS157 is the logic implementation of a 4-pole.SN74LS157 LOGIC DIAGRAM I0a 2 3 I1a 5 I0b 6 I1b 14 I0c 13 I1c 11 I0d 10 I1d E S 15 1 4 7 12 9 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Zd Za Zb Zc FUNCTIONAL DESCRIPTION The LS157 is a Quad 2-Input Multiplexer fabricated with the Schottky barrier diode process for high speed. The Enable Input (E) is active LOW. It selects four bits of data from two sources under the control of a common Select Input (S).

7 V IIH mA VCC = MAX.5 20 40 0. Figure 2.3 V VOUT 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. http://onsemi. S IIL IOS ICC Input LOW Current I0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.25 VO OL Output LOW Voltage 0.8 – 100 16 V µA IOL = 8.0 9.4 Min 2. I1 E. IOH = MAX.com 117 .3 V tPHL 1.65 3. VIN = VIL or VIH per Truth Table VCC = MAX.3 V tPHL 1.SN74LS157 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. nor for more than 1 second.2 – 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Data to Output Propagation Delay Enable to Output Propagation Delay Select to Output Min Typ 9. S Short Circuit Current (Note 1) Power Supply Current – 20 0.3 V VIN 1.3 V VOUT 1.3 V tPLH 1.0 mA 0.7 – 0.3 V tPLH 1. VIN = VIH or VIL per Truth Table IOL = 4.3 V Figure 1. I1 E. I1 E.0 13 14 15 18 Max 14 14 20 21 23 27 Unit ns ns ns Figure 2 Figure 1 Figure 2 VCC = 5.0 mA VCC = VCC MIN.0 0.4 – 0. IIN = – 18 mA VCC = MIN. S I0.5 0. VIN = 0.8 – 1.0 V mA mA mA VCC = MAX.0 V CL = 15 pF Test Conditions AC WAVEFORMS VIN 1. VIN = 7.35 Input HIGH Current I0. VIN = 2.1 0.

synchronously presettable.75 0 Typ 5. Binary (Modulo 16) Asynchronous Reset Synchronous Reset LS161A LS163A http://onsemi. frequency division and other applications.SN74LS161A SN74LS163A BCD Decade Counters/ 4-Bit Binary Counters The LS161A / 163A are high-speed 4-bit synchronous counters. They are edge-triggered.0 Unit V °C mA mA 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS161AN SN74LS161AD SN74LS163AN SN74LS163AD Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. and is independent of. 1999 – Rev.com LOW POWER SCHOTTKY • • • • • • Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge-Triggered Operation Typical Count Rate of 35 MHz ESD > 3500 Volts 16 1 PLASTIC N SUFFIX CASE 648 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. the clock and all other control inputs. and cascadable MSI building blocks for counting. The LS163A has a Synchronous Reset (Clear) input that overrides all other control inputs.25 70 – 0. but is active only during the rising clock edge. 0 Publication Order Number: SN74LS161A/D . memory addressing.4 8. LLC. The LS161A and LS163A count modulo 16 (binary). 1999 118 December. The LS161A has an asynchronous Master Reset (Clear) input that overrides.0 25 Max 5.

SN74LS161A SN74LS163A
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. *MR for LS161A *SR for LS163A 1 *R 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP GND

LOADING (Note a) PIN NAMES PE P0 – P3 CEP CET CP MR SR Q0 – Q3 TC Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs Terminal Count Output HIGH 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 10 U.L. 10 U.L. LOW 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 5 U.L. 5 U.L.

NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL
9 3 4 5 6

7 10 2

PE P0 P1 P2 P3 CEP CET CP TC 15

*R Q0 Q1 Q2 Q3

1 14 13 12 11 VCC = PIN 16 GND = PIN 8 *MR for LS161A *SR for LS163A

http://onsemi.com
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SN74LS161A SN74LS163A
STATE DIAGRAM
LS161A • LS163A 0 1 2 3 LOGIC EQUATIONS 4 Count Enable = CEP • CET • PE TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3 Preset = PE • CP + (rising clock edge) Reset = MR (LS161A) Reset = SR • CP + (rising clock edge) Reset = (LS163A)

15

5

14

6

13

7

12

11

10

9

8

FUNCTIONAL DESCRIPTION

The LS161A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. Three control inputs — Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — select the mode of operation as shown in the tables below. The Count Mode is enabled when the CEP, CET, and PE inputs are HIGH. When the PE is LOW, the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET can be used to inhibit the count sequence. With the PE held HIGH, a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND feature of the two Count Enable inputs (CET • CEP) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits.

The Terminal Count (TC) output is HIGH when the Count Enable Trickle (CET) input is HIGH while the counter is in its maximum count state (HLLH for the BCD counters, HHHH for the Binary counters). Note that TC is fully decoded and will, therefore, be HIGH only for one count state. The LS161A and LS163A count modulo 16 following a binary sequence. They generate a TC when the CET input is HIGH while the counter is in state 15 (HHHH). From this state they increment to state 0 (LLLL). The Master Reset (MR) of the LS161A is asynchronous. When the MR is LOW, it overrides all other input conditions and sets the outputs LOW. The MR pin should never be left open. If not used, the MR pin should be tied through a resistor to VCC, or to a gate output which is permanently set to a HIGH logic level. The active LOW Synchronous Reset (SR) input of the LS163A acts as an edge-triggered control input, overriding CET, CEP and PE, and resetting the four counter flip-flops on the LOW to HIGH transition of the clock. This simplifies the design from race-free logic controlled reset circuits, e.g., to reset the counter synchronously after reaching a predetermined value.

MODE SELECT TABLE
*SR L H H H H PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge ( RESET (Clear) LOAD (Pn Qn ) COUNT (Increment) NO CHANGE (Hold) NO CHANGE (Hold) )

*For the LS163A only. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care

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SN74LS161A SN74LS163A
LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 – 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 Input HIGH Current MR, Data, CEP, Clock PE, CET MR, Data, CEP, Clock PE, CET IIL IOS ICC Input LOW Current MR, Data, CEP, Clock PE, CET Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH Total, Output LOW – 20 0.5 20 40 0.1 0.2 – 0.4 – 0.8 – 100 31 32 V µA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 – 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V

IIH

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 – 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 Input HIGH Current Data, CEP, Clock PE, CET, SR Data, CEP, Clock PE, CET, SR IIL IOS ICC Input LOW Current Data, CEP, Clock, PE, SR CET Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH Total, Output LOW – 20 0.5 20 40 0.1 0.2 – 0.4 – 0.8 – 100 31 32 V µA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 – 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V

IIH

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

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SN74LS161A SN74LS163A
AC CHARACTERISTICS (TA = 25°C)
Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Clock to TC Propagation Delay Clock to Q Propagation Delay CET to TC MR or SR to Q Min 25 Typ 32 20 18 13 18 9.0 9.0 20 35 35 24 27 14 14 28 Max Unit MHz ns ns ns ns VCC = 5.0 V CL = 15 pF Test Conditions

AC SETUP REQUIREMENTS (TA = 25°C)
Limits Symbol tWCP tW ts ts th th trec Parameter Clock Pulse Width Low MR or SR Pulse Width Setup Time, other* Setup Time PE or SR Hold Time, data Hold Time, other Recovery Time MR to CP Min 25 20 20 25 3 0 15 Typ Max Unit ns ns ns ns ns ns ns VCC = 5.0 V Test Conditions

*CEP, CET, or DATA

DEFINITION OF TERMS

SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.

AC WAVEFORMS

tW(H) CP 1.3 V tPHL Q 1.3 V

tW(L) 1.3 V tPLH 1.3 V OTHER CONDITIONS: PE = MR (SR) = H CEP = CET = H

MR

1.3 V

tW trec 1.3 V OTHER CONDITIONS: PE = L P0 = P1 = P2 = P3 = H

CP Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3

tPHL 1.3 V

Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width

Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time

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SN74LS161A SN74LS163A
AC WAVEFORMS (continued) COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS
The positive TC pulse occurs when the outputs are in the (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163. TC

CET

1.3 V tPLH 1.3 V

1.3 V tPHL 1.3 V

Figure 3.

OTHER CONDITIONS: CP = PE = CEP = MR = H

CLOCK TO TERMINAL COUNT DELAYS
CP The positive TC pulse is coincident with the output state (Q0 • Q1 • Q2 • Q3) for the LS161 and LS163. TC

1.3 V tPLH 1.3 V

1.3 V

1.3 V tPHL 1.3 V

Figure 4.

OTHER CONDITIONS: PE = CEP = CET = MR = H

CP

1.3 V th(H) = 0 1.3 V ts(L) 1.3 V

1.3 V th(L) = 0 1.3 V

SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS
The shaded areas indicate when the input is permitted to change for predictable output performance. P0 • P1 • P2 • P3

ts(H)

Q0 • Q1 • Q2 • Q3

Figure 5.

OTHER CONDITIONS: PE = L, MR = H

SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 V th (L) = 0 1.3 V PARALLEL LOAD (See Fig. 5) Q RESPONSE TO PE RESET Q RESPONSE TO SR COUNT OR LOAD Q OTHER CONDITIONS: PE = H, MR = H ts(H) 1.3 V CP th(H) = 0 1.3 V COUNT MODE (See Fig. 7) CEP ts(H) CET 1.3 V ts(H)

CP ts(L) SR or PE

1.3 V th(H) = 0 1.3 V th(H) = 0 1.3 V COUNT ts(L)

1.3 V th(L) = 0 1.3 V ts(L) 1.3 V HOLD

1.3 V

th(L) = 0 1.3 V HOLD

Figure 6.

Figure 7.

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1999 124 December.com • • • • • • Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 14 LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.4 8.0 25 Max 5. http://onsemi. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock.75 0 Typ 5.0 Unit V °C mA mA 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS164N SN74LS164D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.SN74LS164 Serial-In Parallel-Out Shift Register The SN74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. 6 Publication Order Number: SN74LS164/D . 1999 – Rev.25 70 – 0. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products. LLC.

0.6 mA LOW. LOGIC SYMBOL 1 2 8 A LS164 B 8-BIT SHIFT REGISTER CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 3 4 5 6 10 11 12 13 VCC = PIN 14 GND = PIN 7 http://onsemi.L.25 U.25 U.SN74LS164 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 Q7 13 Q6 12 Q5 11 Q4 10 MR 9 CP 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.) = 40 mA HIGH/1. B CP MR Q0 – Q7 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs HIGH 0. 10 U. 0.L. LOW 0.L.L. 5 U. 0. 1 A 2 B 3 Q0 4 Q1 5 Q2 6 Q3 7 GND LOADING (Note a) PIN NAMES A.L. NOTES: a) 1 TTL Unit Load (U.L.5 U.com 125 .5 U.25 U.L.L. 0.5 U.L.

either of these inputs can be used as an active HIGH Enable for data entry through the other input. or both inputs connected together. forcing all Q outputs LOW. Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A•B) that existed before the rising clock edge. An unused input must be tied HIGH.com 126 . MODE SELECT — TRUTH TABLE OPERATING MODE Reset (Clear) Shift INPUTS MR L H H H H A X I I h h B X I h I h OUTPUTS Q0 L L L L H Q1–Q7 L–L q0 – q6 q0 – q6 q0 – q6 q0 – q6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don’t Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously.SN74LS164 LOGIC DIAGRAM 1 2 A D B CD CD CD CD CD CD CD CD CP MR VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q0 3 Q D Q D Q D Q D Q D Q D Q D Q 8 9 Q1 4 Q2 5 Q3 6 Q4 10 Q5 11 Q6 12 Q7 13 FUNCTIONAL DESCRIPTION The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B). http://onsemi.

VIN = VIH or VIL per Truth Table VCC = MAX. IIN = – 18 mA VCC = MIN.SN74LS164 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 – 0.4 Min 2.65 3.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.25 VO OL Output LOW Voltage 0.com 127 .35 IIH IIL IOS ICC Input HIGH Current 0.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter CP.0 mA VCC = VCC MIN. nor for more than 1 second.0 V VCC = MAX.5 0. VIN = 7. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay MR to Output Q Propagation Delay Clock to Output Q Min 25 Typ 36 24 17 21 36 27 32 Max Unit MHz ns ns VCC = 5.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.0 mA 0.0 Test Conditions http://onsemi. VIN = 2.0 0. VIN = VIH or VIL per Truth Table IOL = 4.0 20 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.4 –100 27 0. VIN = 0. MR Pulse Width Data Setup Time Data Hold Time MR to Clock Recovery Time Min 20 15 5.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.8 – 1.5 20 V µA mA mA mA mA IOL = 8. IOH = MAX.7 V VCC = MAX.

3 V tPLH 1.3 V 1.3 V Figure 1.3 V Q 1. I/f max MR 1.3 V 1. Master Reset to Output Delay and Master Reset to Clock Recovery Time 1/fmax tW CP 1.3 V ts(H) D * 1.3 V th(L) 1.SN74LS164 AC WAVEFORMS *The shaded areas indicate when the input is permitted to change for predictable output performance.3 V Figure 3.3 V th(H) 1.3 V tPHL 1.3 V tW 1.3 V 1.3 V CP tW 1.3 V CONDITIONS: MR = H Q 1. Master Reset Pulse Width. Data Setup and Hold Times http://onsemi.3 V ts(L) 1. Clock to Output Delays and Clock Pulse Width Figure 2.3 V 1.com 128 .3 V CP tPHL Q 1.3 V trec 1.3 V 1.

GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. or one input can act as an active LOW clock enable. serial shifting occurs on the rising edge of the clock.0 25 Max 5.4 8.25 70 – 0.0 Unit V °C mA mA 16 1 http://onsemi. The 2-input OR clock can be used to combine two independent clock sources.75 0 Typ 5. 1999 129 December. With PL HIGH.SN74LS165 8-Bit Parallel-to-Serial Shift Register The SN74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. new data enters via the Serial Data (DS) input. LLC. 1999 – Rev. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW.com LOW POWER SCHOTTKY PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS165N SN74LS165D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 6 Publication Order Number: SN74LS165/D .

5 U. CP2 DS PL P0 – P7 Q7 Q7 Clock (LOW–to–HIGH Going Edge) Inputs Serial Data Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Serial Output from Last State Complementary Output HIGH 0.L.L. 1 PL 2 CP1 3 P4 4 P5 5 P6 6 P7 7 Q7 8 GND LOADING (Note a) PIN NAMES CP1.L.L. 5 U. 5 U.L. 10 U.L.L. 0.L.25 U.25 U.6 mA LOW.5 U. LOGIC SYMBOL 1 11 12 13 14 3 4 5 6 PL P0 P1 P2 P3 P4 P5 P6 P7 DS Q7 CP Q7 10 2 15 9 7 VCC = PIN 16 GND = PIN 8 http://onsemi.L. 0.L.5 U.L.5 U.75 U. 0. 0.L. NOTES: a) 1 TTL Unit Load (U. 10 U. 0. 1. LOW 0.L.) = 40 mA HIGH/1.com 130 .SN74LS165 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 CP2 15 P3 14 P2 13 P1 12 P0 11 DS 10 Q7 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.25 U.

The two clock inputs perform identically. one can be used as a clock inhibit by applying a HIGH signal. with respect to the rising edge of the clock. To avoid double clocking. provided that the recommended setup and hold times are observed. The parallel data can change while PL is LOW. For clock operation. Parallel data enters when the PL signal is LOW. TRUTH TABLE CP PL 1 L H H H H X L H 2 X Q0 P0 DS Q0 DS Q0 Q1 P1 Q0 Q1 Q0 Q1 Q2 P2 Q1 Q2 Q1 Q2 Q3 P3 Q2 Q3 Q2 Q3 Q4 P4 Q3 Q4 Q3 Q4 Q5 P5 Q4 Q5 Q4 Q5 Q6 P6 Q5 Q6 Q5 Q6 Q7 P7 Q6 Q7 Q6 Q7 Parallel Entry Right Shift No Change Right Shift No Change CONTENTS RESPONSE L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial http://onsemi. The serial input data can change at any time. the rising inhibit signal will cause the same response as a rising clock edge. Otherwise.com 131 . provided only that the recommended setup and hold times are observed. PL must be HIGH.SN74LS165 LOGIC DIAGRAM 11 12 13 14 3 4 5 6 P0 P1 P2 P3 P4 P5 P6 P7 10 DS 2 CP1 15 CP2 1 PL PRESET Q0 S CP R CLQ0 PRESET Q1 S CP R CL Q1 PRESET S Q2 CP R CLQ2 PRESET S Q3 CP R CLQ3 PRESET Q4 S CP R CLQ4 PRESET S Q5 CP R CLQ5 PRESET S Q6 CP R CLQ6 PRESET Q7 S CP R CL Q7 9 7 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The SN74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register. however. with auxiliary gating to provide overriding asynchronous parallel entry. the inhibit signal should only go HIGH while the clock is HIGH. The flip-flops are edge-triggered for serial operations.

IIN = – 18 mA VCC = MIN.4 – 1.7 – 0. VIN = 2.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. IOH = MAX. PL to CP Min 25 15 10 20 30 0 45 Typ Max Unit ns ns ns ns ns ns ns VCC = 5.0 V Test Conditions role of CP1 and CP2 in an application may be interchanged. VIN = 7.4 Min 2.0 V mA mA mA VCC = MAX.5 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay PL to Output Propagation Delay Clock to Output Propagation Delay P7 to Q7 Propagation Delay P7 to Q7 Min 25 Typ 35 22 22 27 28 14 21 21 16 35 35 40 40 25 30 30 25 Max Unit MHz ns ns ns ns VCC = 5.0 0.25 VO OL Output LOW Voltage 0.65 3.1 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA VCC = VCC MIN.8 – 1.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.3 – 0. VIN = VIH or VIL per Truth Table IOL = 4. http://onsemi. VIN = 0.35 Input HIGH Current Other Inputs PL Input Other Inputs PL Input IIL IOS ICC Input LOW Current Other Inputs PL Input Short Circuit Current (Note 1) Power Supply Current – 20 0.com 132 .0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW tW ts ts ts th trec 1 The Parameter CP Clock Pulse Width PL Pulse Width Parallel Data Setup Time Serial Data Setup Time CP1 to CP2 Setup Time1 Hold Time Recovery Time.2 – 100 36 V µA IOL = 8.7 V IIH mA VCC = MAX.SN74LS165 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.0 mA 0. nor for more than 1 second.5 20 60 0.

3 V 1.3 V PL 1.3 V 1.3 V th(L) 1.3 V ts(L) 1. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the PL pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer loaded Data to the Q outputs. Pn ts(H) PL OR CP 1. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition.3 V Q7 OR Q7 PL 1.com 133 . AC WAVEFORMS CP1 tW ts CP2 1.3 V tPHL Q7 OR Q7 1.3 V 1/fmax tW tPLH 1.3 V Figure 1.3 V CP Figure 3.3 V trec 1.SN74LS165 DEFINITION OF TERMS: SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.3 V tPLH 1. Figure 4.3 V tW 1.3 V tPHL 1.3 V th(H) 1. A negative hold time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. http://onsemi. Figure 2.3 V 1.

Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate. which permits one input to be used as a clock enable or clock inhibit function. including the clock. When high.75 0 Typ 5.SN74LS166 8-Bit Shift Registers The SN74LS166 is an 8-Bit Shift Register.25 70 – 0.4 8. By utilizing input clamping diodes. serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. 1999 134 December. LLC.0 25 Max 5. http://onsemi.com LOW POWER SCHOTTKY 16 1 • Synchronous Load • Direct Overriding Clear • Parallel to Serial Conversion GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. This will allow the system clock to be free running and the register stopped on command with the other clock input. The LS166 is a parallel-in or serial-in. the drive requirements are lowered to one 74LS standard load. The shift/load input establishes the parallel-in or serial-in mode. A buffered direct clear input overrides all other inputs. switching transients are minimized and system design simplified.0 Unit V °C mA mA 16 PLASTIC N SUFFIX CASE 648 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS166N SN74LS166D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. Clocking is inhibited when either of the clock inputs are held high. holding either input low enables the other clock input. and sets all flip-flops to zero. 6 Publication Order Number: SN74LS166/D . Designed with all inputs buffered. 1999 – Rev. this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Serial data flow is inhibited during parallel loading. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled.

.SN74LS166 PARALLEL PARALLEL INPUTS F 11 F E 10 E CLEAR 9 SHIFT/ INPUT OUTPUT G H QH VCC LOAD 16 15 SHIFT/ LOAD 14 H 13 QH 12 G SERIAL INPUT A 1 SERIAL INPUT 2 A B 3 B C 4 C D 5 D CLEAR CLOCK INHIBIT CK 8 6 7 CLOCK CLOCK GND INHIBIT PARALLEL INPUTS FUNCTION TABLE INPUTS CLEAR L H H H H H SHIFT/ LOAD X X L H H X CLOCK INHIBIT X L L L L H PARALLEL CLOCK X L ↑ ↑ ↑ ↑ SERIAL A..H X X X H L X X X a..h X X X QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 L QH0 h QGn QGn QH0 INTERNAL OUTPUTS OUTPUT QH http://onsemi.com 135 ..

Inhibit. Load.SN74LS166 Typical Clear. Shift. and Shift Sequences CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD A B C PARALLEL INPUTS D E F G H OUTPUT QH SERIAL SHIFT CLEAR (9) CLEAR (1) SERIAL INPUT (15) SHIFT/LOAD (2) A R CK S H L H L H L H H INHIBIT LOAD H H L H L H L SERIAL SHIFT H QA B (3) R S CK QB C (4) R S CK QC D (5) R S CK QD E (10) R S CK F (11) R QE CK S QF (12) G R CK S QG H CLOCK CLOCK INHIBIT (14) (7) (6) R S CK (13) Q H http://onsemi.com 136 .

0 mA 0.5 0. VIN = VIH or VIL per Truth Table IOL = 4. http://onsemi. IOH = MAX.0 mA VCC = VCC MIN.4 Min 2. VIN = 2.7 V VCC = MAX.8 – 1.25 VO OL Output LOW Voltage 0. nor for more than 1 second.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 V VCC = MAX.5 20 V µA mA mA mA mA IOL = 8. VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = VIL or VIH per Truth Table VCC = MAX.65 3.4 – 100 38 0.7 – 0.0 0.SN74LS166 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. IIN = – 18 mA VCC = MIN. VIN = 7.com 137 .35 IIH IIL IOS ICC Input HIGH Current 0.

LS166 Vref = 1. tn+8 = bit time after eight clocking transition NOTE 1. 3V 0V 3V tPLH (CLK-Q) OUTPUT Q Vref VOL AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Clear to Output Clock to Output Min 25 Typ 35 19 23 24 30 35 35 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts ts th Parameter Clock Clear Pulse Width Mode Control Setup Time Data Setup Time Hold Time.SN74LS166 TEST TABLE FOR SYNCHRONOUS INPUTS DATA INPUT FOR TEST H Serial Input SHIFT/LOAD 0V 4. Any Input Min 30 30 20 15 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.3 V. tn = bit time before clocking transition NOTE 1.com 138 .0 Test Conditions http://onsemi. tn+1 = bit time after one clocking transition NOTE 1.5 V OUTPUT TESTED QH at tn+1 QH at tn+8 AC WAVEFORMS tw(clear) CLEAR INPUT Vref Vref 0V tn CLOCK INPUT Vref tw(clock) DATA INPUT (SEE TEST TABLE) Vref Vref tsu tn + 1 (SEE NOTE 1) tn tn + 1 3V Vref th Vref tsu Vref th Vref 0V tPHL (clear-Q) Vref tPHL (CLK-Q) VOH Vref NOTE 1.

1999 – Rev. The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.25 70 – 0.75 0 Typ 5. 1999 139 December. The device has a Master Reset to simultaneously clear all flip-flops. The device is used primarily as a 6-bit edge-triggered storage register.0 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS174N SN74LS174D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. LLC. 6 Publication Order Number: SN74LS174/D .4 8. http://onsemi.SN74LS174 Hex D Flip-Flop The LSTTL / MSI SN74LS174 is a high speed Hex D Flip-Flop.com • • • • Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Asynchronous Common Reset Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.0 25 Max 5. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition.

) = 40 mA HIGH/1.L.25 U. NOTES: a) 1 TTL Unit Load (U. LOGIC SYMBOL 3 4 6 11 13 14 9 1 D0 D1 D2 D3 D4 D5 CP MR Q0 Q1 Q2 Q3 Q4 Q5 2 5 7 10 12 15 VCC = PIN 16 GND = PIN 8 LOGIC DIAGRAM MR CP D5 1 9 14 D4 13 D3 11 D2 6 D1 4 D0 3 D Q CP CD 15 D Q CP CD 12 D Q CP CD 10 D Q CP CD 7 D Q CP CD 5 D Q CP CD 2 Q5 Q4 VCC = PIN 16 GND = PIN 8 Q3 Q2 Q1 Q0 = PIN NUMBERS http://onsemi.L.com 140 . 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 D2 7 Q2 8 GND LOADING (Note a) PIN NAMES D0 – D5 CP MR Q0 – Q5 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs HIGH 0.L.5 U.SN74LS174 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q5 15 D5 14 D4 13 Q4 12 D3 11 Q3 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. LOW 0. 10 U.25 U.L. 0. 0.5 U. 0.5 U. 0. 5 U.L.L.25 U.L.L.L.6 mA LOW.

35 IIH IIL IOS ICC Input HIGH Current 0. VIN = VIL or VIH per Truth Table VCC = MAX.65 3. MR = H) D H L Note 1: t = n + 1 indicates conditions after next clock.25 VO OL Output LOW Voltage 0. VIN = 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.SN74LS174 FUNCTIONAL DESCRIPTION The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs.8 – 1.0 V VCC = MAX. TRUTH TABLE Inputs (t = n. IOH = MAX. VIN = 2. nor for more than 1 second.0 mA VCC = VCC MIN. IIN = – 18 mA VCC = MIN.4 Min 2. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. http://onsemi. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW to HIGH Clock (CP) transition.5 20 V µA mA mA mA mA IOL = 8.5 0.7 V VCC = MAX. The LS174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. VIN = VIH or VIL per Truth Table IOL = 4. VIN = 7.0 0. The Clock (CP) and Master Reset (MR) are common to all flip-flops.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. Outputs (t = n+1) Note 1 Q H L DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.4 – 100 26 0.com 141 .7 – 0.0 mA 0.

A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. and Master Reset Recovery Time DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter Clock or MR Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5. Setup and Hold Times Data to Clock Figure 2. Clock to Output Min 30 Typ 40 23 20 21 35 30 30 Max Unit MHz ns ns VCC = 5. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.3 V MR 1. http://onsemi.SN74LS174 AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay.com 142 .3 V tW 1. Clock Pulse Width.3 V tPLH 1.3 V tPHL 1.3 V 1.0 Test Conditions AC WAVEFORMS 1/fmax tw CP 1.3 V trec 1.3 V Q *The shaded areas indicate when the input is permitted to *change for predictable output performance.3 V ts(H) D * 1. Figure 1. Master Reset to Output Delay. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition.3 V 1.3 V CP Q tPHL 1. Clock to Output Delays. Frequency. MR to Output Propagation Delay.0 25 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.3 V th(L) 1.3 V th(H) ts(L) 1. Master Reset Pulse Width.

LLC.4 8.75 0 Typ 5.0 25 Max 5. The information on the D inputs is stored during the LOW to HIGH clock transition.25 70 – 0. The device is useful for general flip-flop requirements where clock and clear inputs are common.com • • • • • • LOW POWER SCHOTTKY Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp Diodes Limit High Speed Termination Effects 16 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 – Rev. 1999 143 December.0 Unit V °C mA mA PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS175N SN74LS175D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. Both true and complemented outputs of each flip-flop are provided. 6 Publication Order Number: SN74LS175/D . http://onsemi. independent of the Clock or D inputs. when LOW. A Master Reset input resets all flip-flops.SN74LS175 Quad D Flip-Flop The LSTTL / MSI SN74LS175 is a high speed Quad D Flip-Flop.

0.L. 10 U.L. NOTES: a) 1 TTL Unit Load (U. 0.25 U.6 mA LOW.L. LOW 0.com 144 .L. 0. 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND LOADING (Note a) PIN NAMES D0 – D3 CP MR Q0 – Q3 Q0 – Q3 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs Complemented Outputs HIGH 0.) = 40 mA HIGH/1.5 U.L.5 U. 10 U.5 U.L.25 U. 0. 5 U. LOGIC SYMBOL 4 5 12 13 9 CP D0 D1 D2 D3 1 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 3 2 6 7 11 10 14 15 VCC = PIN 16 GND = PIN 8 LOGIC DIAGRAM MR CP D3 1 9 13 D2 12 D1 5 D0 4 D Q CP Q CD 14 15 D Q CP Q CD 11 10 D Q CP Q CD 6 7 D Q CP Q CD 3 2 Q3 Q3 Q2 Q2 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q1 Q1 Q0 Q0 http://onsemi.25 U.L.SN74LS175 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L.L.L.L. 5 U.

http://onsemi. The Clock and Master Reset are common.0 V VCC = MAX.5 0. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition.7 V VCC = MAX. The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable. causing individual Q and Q outputs to follow.4 – 100 18 0.0 mA VCC = VCC MIN. IIN = – 18 mA VCC = MIN.0 0.0 mA 0.25 VO OL Output LOW Voltage 0. MR = H) D L H Outputs (t = n+1) Note 1 Q L H Q H L Note 1: t = n + 1 indicates conditions after next clock.65 3. VIN = 0. VIN = 2.4 Min 2. nor for more than 1 second.com 145 .1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = 7.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = VIL or VIH per Truth Table VCC = MAX. IOH = MAX.7 – 0. TRUTH TABLE Inputs (t = n. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. VIN = VIH or VIL per Truth Table IOL = 4. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.8 – 1.SN74LS175 FUNCTIONAL DESCRIPTION The LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.35 IIH IIL IOS ICC Input HIGH Current 0.5 20 V µA mA mA mA mA IOL = 8.

com 146 . Clock Pulse Width.3 V tPHL 1. MR to Output Propagation Delay.3 V th(L) 1. Master Reset to Output Delay. http://onsemi. Master Reset Pulse Width.0 Test Conditions AC WAVEFORMS 1/fmax CP 1.3 V MR 1.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter Clock or MR Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5. Clock to Output Min 30 Typ 40 20 20 13 16 30 30 25 25 Max Unit MHz ns ns VCC = 5.0 25 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.3 V Q CP Q tPLH 1. Setup and Hold Times Data to Clock Figure 2. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.3 V 1. and Master Reset Recovery Time DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.3 V trec 1.3 V 1.SN74LS175 AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay. Clock to Output Delays. Frequency.3 V tPHL 1. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. Figure 1.3 V 1.3 V tPLH 1.3 V ts(H) D * 1.3 V tPLH 1.3 V tPHL 1.3 V tW 1.3 V th(H) ts(L) tw 1.3 V Q Q *The shaded areas indicate when the input is permitted to *change for predictable output performance. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized.

LLC. 1999 147 December. 0 Publication Order Number: SN74LS193/D . thus simplifying multistage counter designs. 95 mW Typical Dissipation High Speed .75 0 Typ 5.25 70 – 0. .0 Unit V °C 16 PLASTIC N SUFFIX CASE 648 mA mA 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS193N SN74LS193D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.0 25 Max 5. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic.4 8. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Separate Count Up and Count Down Clocks are used and the circuits can operate synchronously. . .SN74LS193 Presettable 4-Bit Binary Up/Down Counter The SN74LS193 is an UP/DOWN MODULO-16 Binary Counter.com LOW POWER SCHOTTKY • • • • • • • Low Power . 1999 – Rev. http://onsemi. Individual preset inputs allow the circuits to be used as programmable counters. 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects 16 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. .

com 148 .L.5 U.L. 10 U.L.L.6 mA LOW. LOGIC SYMBOL 11 15 1 10 9 PL 5 4 CPU CPD P0 P1 P2 P3 TCU 12 MR Q0 Q1 Q2 Q3 14 3 2 6 7 TCD 13 VCC = PIN 16 GND = PIN 8 http://onsemi. NOTES: a) 1 TTL Unit Load (U.L. 0.25 U. 5 U.L.L.5 U.25 U.) = 40 mA HIGH/1. 0. 5 U.5 U.L. 10 U. 0.L. 0. 5 U.25 U.25 U.L. 0. 0.SN74LS193 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P0 15 MR 14 TCD 13 TCU 12 PL 11 P2 10 P3 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. 0. 1 P1 2 Q1 3 Q0 4 CPD 5 CPU 6 Q2 7 Q3 8 GND LOADING (Note a) PIN NAMES CPU CPD MR PL Pn Qn TCD TCU Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Flip–Flop Outputs Terminal Count Down (Borrow) Output Terminal Count Up (Carry) Output HIGH 0.25 U.L.5 U.L. 10 U.L.5 U.L.L. 0.L. LOW 0.

SN74LS193 STATE DIAGRAM 0 1 2 3 4 15 5 LOGIC EQUATIONS FOR TERMINAL COUNT TCU = Q0 ⋅ Q1⋅ Q2⋅ Q3 ⋅ CPU TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD 14 6 COUNT UP COUNT DOWN 13 7 12 11 10 9 8 LOGIC DIAGRAM P0 PL (LOAD) CPU (UP COUNT) 11 5 12 15 1 P1 10 P2 9 P3 TCU (CARRY OUTPUT) SD T Q T SD Q T SD Q T SD Q CD Q CD Q CD Q CD Q 13 CPD (DOWN COUNT) MR (CLEAR) 4 14 3 2 6 7 TCD (BORROW OUTPUT) Q0 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q1 Q2 Q3 http://onsemi.com 149 .

Since the TC outputs repeat the clock waveforms. If one of the Clock inputs is LOW during and after a reset or load operation. Similarly. information present on the Parallel Data inputs (P0. Otherwise. depending on the state of the first flip-flop. the next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW. Synchronous switching. Each circuit has an asynchronous parallel load capability permitting the counter to be preset. with internal gating and steering logic to provide master reset. thus effectively repeating the Count Up Clock. override both Clock inputs. P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. While counting with one clock input. the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. which cannot toggle as long as either Clock input is LOW. MODE SELECT TABLE MR H L L L L PL X L H H H CPU X X H H CPD X X H H MODE Reset (Asyn. but delayed by two gate delays. When a circuit has reached the maximum count state of 15. is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line. A HIGH signal on the Master Reset input will disable the preset gates. the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted. Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input causes the slave.com 150 . Each circuit contains four master/slave flip-flops. A LOW-to-HIGH transition on the Count Up input will advance the count by one. and latch each Q output in the LOW state. thereby causing all state changes to be initiated simultaneously. the circuit will either count by twos or not at all. as opposed to ripple counting. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. the other should be held HIGH.SN74LS193 FUNCTIONAL DESCRIPTION The LS193 is a 4-Bit Binary Synchronous UP / DOWN (Reversable) Counter. TCU will stay LOW until CPU goes HIGH again. a similar transition on the Count Down input will decrease the count by one. count up and count down operations.) Preset (Asyn. and thus the Q output to change state. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW. they can be used as the clock input signals to the next higher order circuit in a multistage counter. individual preset.) No Change Count Up Count Down L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = LOW-to-HIGH Clock Transition http://onsemi.

VIN = 7.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.5 20 V µA mA mA mA mA IOL = 8. nor for more than 1 second. VIN = VIH or VIL per Truth Table IOL = 4.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.7 V VCC = MAX.25 VO OL Output LOW Voltage 0.7 – 0.SN74LS193 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. IOH = MAX.0 Test Conditions DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the PL transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency CPU Input to TCU Output CPD Input to TCD Output Clock to Q PL to Q MR Input to Any Output Min 25 Typ 32 17 18 16 15 27 30 24 25 23 26 24 24 24 38 47 40 40 35 Max Unit MHz ns ns ns ns ns VCC = 5. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs.35 IIH IIL IOS ICC Input HIGH Current 0.4 Min 2.4 – 100 34 0. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter Any Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5.0 0. http://onsemi.0 mA 0. VIN = 2.0 40 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.65 3. A negative HOLD TIME indicates that the correct logic level may be released prior to the PL transition from LOW-to-HIGH and still be recognized. IIN = – 18 mA VCC = MIN.0 mA VCC = VCC MIN.com 151 .8 – 1. HOLD TIME (th) is defined as the minimum time following the PL transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition.0 V VCC = MAX.5 0.

Pn tw PL 1.3 V NOTE: PL = LOW Figure 2. Figure 5.SN74LS193 AC WAVEFORMS CPU or CPD 1.3 V Qn Q=P * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 6.3 V tPHL 1.com 152 .3 V Figure 1.3 V trec Figure 4.3 V tPLH 1.3 V PL tW tPHL 1. CPU or CPD tPHL TCU or TCD 1.3 V tPLH Qn 1.3 V 1. Figure 3.3 V tPHL tW tPLH 1.3 V 1. Figure 7. http://onsemi.3 V Q CPU or CPD tPHL 1.3 V Pn 1.3 V Q 1.3 V trec 1. Pn ts(H) PL 1.3 V th(H) ts(L) 1.3 V th(L) MR tW CPU or CPD Q=P Q 1.3 V tPHL tPLH Qn 1.3 V 1.3 V 1.

http://onsemi.4 8. with added features of shift left without external connections and hold (do nothing) modes of operation. shift left. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL families. parallel-serial. The LS194A is similar in operation to the LS195A Universal Shift Register.25 70 – 0. It may be used in serial-serial. shift right. LLC.SN74LS194A 4-Bit Bidirectional Universal Shift Register The SN74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. 6 Publication Order Number: SN74LS194A/D .75 0 Typ 5. it is useful in a wide variety of applications.0 25 Max 5.0 Unit V °C mA mA 16 PLASTIC N SUFFIX CASE 648 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS194AN SN74LS194AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.com LOW POWER SCHOTTKY • • • • • Typical Shift Frequency of 36 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects 16 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 – Rev. 1999 153 December. serial-parallel. As a high speed multifunctional sequential building block. and parallel-parallel data register transfers.

0. http://onsemi. 0.25 U.25 U. 0.25 U.L.25 U.5 U.25 U.L.L.L.L. 0.L.L.L. LOW 0.5 U.) = 40 mA HIGH/1.5 U. 0.L.L. 0.5 U. NOTES: a) 1 TTL Unit Load (U. 0.L. 0. S1 P0 – P3 DSR DSL CP MR Q0 – Q3 Mode Control Inputs Parallel Data Inputs Serial (Shift Right) Data Input Serial (Shift Left) Data Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs HIGH 0. 0. 5 U.L.com 154 . 10 U.L.5 U. 0.L.25 U.6 mA LOW.SN74LS194A CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 CP 11 S1 10 S0 9 1 MR 2 DSR 3 P0 4 P1 5 P2 6 P3 7 DSL 8 GND LOADING (Note a) PIN NAMES S0.5 U.L.

Q1. The asynchronous Master Reset (MR). Q3 Q2. The only timing restriction. P3) are D-type inputs. ! ! http://onsemi. The register is fully synchronous.com 155 . P1. therefore. or the memory buffer registers. Some of the common features of the two devices are described below: All data and mode control inputs are edge-triggered. DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation. etc. P1. Special logic features of the LS194A design which increase the range of application are described below: Two mode control inputs (S0. The LS194A is similar in operation to the ON Semiconductor LS195A Universal Shift Register when used in serial or parallel data register transfers. D-type serial data inputs (DSR. the data appearing on P0. or parallel data can be entered loading all four bits of the register simultaneously. P2. etc.) or right to left (shift left. and Q3 outputs respectively following the next LOW to HIGH transition of the clock. data can be entered and shifted from left to right (shift right. is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. P2. overrides all other input conditions and forces the Q outputs LOW. the existing data is retained in a “do nothing” mode without restricting the HIGH to LOW clock transition. As shown in the Mode Selection Table. and P3 inputs is transferred to the Q0. The four parallel data inputs (P0. responding only to the LOW to HIGH transition of the Clock (CP). with all operations taking place in less than 15 ns (typical) making the device especially useful for implementing very high speed CPUs.). S1) determine the synchronous operation of the device. When both S0 and S1. when LOW. Q2.are LOW. Q0 Q1. When both S0 and S1 are HIGH.SN74LS194A LOGIC DIAGRAM P0 10 P1 3 4 P2 5 P3 6 S1 9 S0 2 DSR 7 DSL VCC = PIN 16 GND = PIN 8 = PIN NUMBERS S CP Q0 S CP Q1 S CP Q2 S CP Q3 R CLEAR R CLEAR R CLEAR R CLEAR CP MR 11 1 15 14 13 12 Q0 Q1 Q2 Q3 FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS194A 4-Bit Bidirectional Shift Register.

0 V VCC = MAX.4 Min 2.0 0. VIN = 7.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. MR to Output Min 25 Typ 36 14 17 19 22 26 30 Max Unit MHz ns ns VCC = 5.8 – 1.25 VO OL Output LOW Voltage 0.SN74LS194A MODE SELECT — TRUTH TABLE OPERATING MODE Reset Hold Shift Left Shift Right Parallel Load INPUTS MR L H H H H H H S1 X I h h I I h S0 X I I I h h h DSR X X X X I h X DSL X X I h X X X Pn X X X X X X Pn Q0 L q0 q1 q1 L H P0 Q1 L q1 q2 q2 q0 q0 P1 OUTPUTS Q2 L q2 q3 q3 q1 q1 P2 Q3 L q3 L H q2 q2 P3 L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.4 – 100 23 0. IOH = MAX. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. VIN = VIH or VIL per Truth Table IOL = 4.7 V VCC = MAX.5 20 V µA mA mA mA mA IOL = 8. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VIN = VIL or VIH per Truth Table VCC = MAX.0 V CL = 15 pF F Test Conditions http://onsemi.65 3. VIN = 2.7 – 0.0 mA 0.com 156 .0 mA VCC = VCC MIN. Clock to Output Propagation Delay. VIN = 0.5 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. IIN = – 18 mA VCC = MIN. nor for more than 1 second.

3 V P0 P1 P2 P3 ts(L) th(L) = 0 CLOCK OUTPUT* 1. Clock to Output Delays Clock Pulse Width and fmax MR 1. Master Reset Pulse Width. Setup (ts) and Hold (th) Time for S Input http://onsemi. S1 = H OTHER CONDITIONS: PO = P1 = P2 = P3 = H Figure 2. Setup (ts) and Hold (th) Time for Serial Data (DSR. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. Any Input Recovery Time Min 20 30 20 0 25 Typ Max Unit ns ns ns ns ns VCC = 5. Master Reset to Output Delay and Master Reset to Clock Recovery Time Figure 4. P2.SN74LS194A AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts ts th trec Parameter Clock or MR Pulse Width Mode Control Setup Time Data Setup Time Hold time. S0 1/fmax 1. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition.3 V ts(H) th(H) = 0 1.3 V OTHER CONDITIONS: MR = H OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY CLOCK tPHL OUTPUT Figure 3.3 V ts(L) th(L) = 0 ts(H) th(H) = 0 (––– IS SHIFT LEFT) DSR DSL OTHER CONDITIONS: S1 = L. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs.3 V 1.3 V tW tPLH 1.3 V CLOCK tPHL OUTPUT 1.3 V OTHER CONDITIONS: MR = H ts th = 0 1. DSL) and Parallel Data (P0.3 V S1 1. P3) (STABLE TIME) 1. MR = H.3 V OTHER CONDITIONS: S0.com 157 .0 V Test Conditions DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.3 V ts th = 0 CLOCK 1.3 V tW trec 1. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. P1.3 V S0 S1 1. S0 = H Figure 1.

It is useful for a wide variety of register and counting applications.0 25 Max 5. K Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.4 8. 1999 158 December.25 70 – 0. 1999 – Rev. http://onsemi. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products.75 0 Typ 5. LLC.SN74LS195A Universal 4-Bit Shift Register The SN74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz.com • • • • • Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset J. 6 Publication Order Number: SN74LS195A/D .0 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS195AN SN74LS195AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.

0.L.SN74LS195A CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 Q3 11 CP 10 PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.25 U.L. 0.L. 5 U.5 U.5 U. 0.) = 40 mA HIGH/1. 0. 5 U.25 U.L.L.25 U.L.com 159 . LOGIC SYMBOL 9 4 5 6 7 2 10 3 J K PE P0 P1 P2 P3 Q3 11 CP MR Q0 Q1 Q2 Q3 1 15 14 13 12 VCC = PIN 16 GND = PIN 8 http://onsemi.L.L.L. 1 MR 2 J 3 K 4 P0 5 P1 6 P2 7 P3 8 GND LOADING (Note a) PIN NAMES PE P0 – P3 J K CP MR Q0 – Q3 Q3 Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage J (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs Complementary Last Stage Output HIGH 0.5 U.L.L.5 U.25 U. 0. NOTES: a) 1 TTL Unit Load (U.25 U.25 U. 0.6 mA LOW.L. 0.L. 10 U.5 U. 0. LOW 0. 10 U. 0.L.5 U.L.L.L. 0.

Q3 outputs following the LOW to HIGH clock transition. the LS195A appears as four common clocked D flip-flops. All serial and parallel data transfers are synchronous. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW.com 160 . pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. P3 is transferred to the respective Q0. Reset First Shift. independent of any other input condition. P1. K. It performs serial. Q2. When the PE input is HIGH. The JK inputs provide the flexibility of the JK type input for special applications. The device is useful in a wide variety of shifting. Toggle First Stage Shift. shift right (Q0 Q1) and parallel load which are controlled by the state of the Parallel Enable (PE) input. parallel. or parallel to serial data transfers at very high speeds. Retain First Stage Parallel Load L H H H H H PE X h h h h I J X h I h I X K X h I I h X Pn X X X X X pn Q0 L H L q0 q0 p0 Q1 L q0 q0 q0 q0 p1 Q2 L q1 q1 q1 q1 p2 Q3 L q2 q2 q2 q2 p3 Q3 H q2 q2 q2 q2 p3 OUTPUTS L = LOW voltage levels H = HIGH voltage levels X = Don’t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. occurring after each LOW to HIGH clock transition. The LS195A has two primary modes of operation. http://onsemi. counting and storage applications. Set First Stage Shift.SN74LS195A LOGIC DIAGRAM PE J 9 2 3 K 4 P0 5 P1 6 P2 7 P3 1 MR 10 CP R CD Q0 CP S VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q0 15 R CD CP S Q0 14 R CD CP S Q2 13 R CD Q3 CP S Q3 12 11 Q0 Q1 Q2 Q3 Q3 FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS195A 4-Bit Shift Register. serial to parallel. P2. The data on the parallel inputs P0. serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction Q0 Q1 Q2 Q3 following each LOW to HIGH clock transition. Since the LS195A utilizes edge-triggering. Shift left operations (Q3 Q2) can be achieved by tying the Qn Outputs to the Pn–1 inputs and holding the PE input LOW. When the PE ³ ³ ³ ³ input is LOW. Pn and PE inputs for logic operation — except for the set-up and release time requirements. there is no restriction on the activity of the J. ³ MODE SELECT — TRUTH TABLE INPUTS OPERATING MODES MR Asynchronous Reset Shift. and the simple D type input for general applications by tying the two pins together. Q1. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.

35 IIH IIL IOS ICC Input HIGH Current 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = 0.7 – 0. AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay. nor for more than 1 second. VIN = VIH or VIL per Truth Table IOL = 4. VIN = 7.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW tW ts ts trec trel th Parameter CP Clock Pulse Width MR Pulse Width PE Setup Time Data Setup Time Recovery Time PE Release Time Data Hold Time 0 Min 16 12 25 15 25 10 Typ Max Unit ns ns ns ns ns ns ns VCC = 5. VIN = VIL or VIH per Truth Table VCC = MAX.5 0.25 VO OL Output LOW Voltage 0.7 V VCC = MAX. VIN = 2.4 – 100 21 0.0 0. IIN = – 18 mA VCC = MIN. IOH = MAX.65 3.4 Min 2.0 V Test Conditions http://onsemi.0 mA 0. MR to Output Min 30 Typ 39 14 17 19 22 26 30 Max Unit MHz ns ns VCC = 5.8 – 1.SN74LS195A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.5 20 V µA mA mA mA mA IOL = 8.0 mA VCC = VCC MIN.0 V VCC = MAX. Clock to Output Propagation Delay.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.com 161 .

Master Reset Pulse Width.3 V LOAD SERIAL DATA SHIFT RIGHT CLOCK tPHL OUTPUT 1.3 V CONDITIONS: PE = L PO = P1 = P2 = P3 = H Figure 2. P3) MR tW 1. Master Reset to Output Delay and Master Reset to Clock Recovery Time CONDITIONS: MR = H *Q0 STATE WILL BE DETERMINED BY J AND K INPUTS. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized.com 162 .3 V tPLH 1. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. Clock to Output Delays and Clock Pulse Width Figure 3.3 V 1.3 V ts(H) th(H) = 0 J&K tW CONDITIONS: MR = H *J AND K SET–UP TIME AFFECTS Q0 ONLY Figure 1.3 V LOAD PARALLEL DATA 1.3 V CLOCK tPHL OUTPUT 1. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. Setup (ts) and Hold (th) Time for PE Input http://onsemi.3 V CONDITIONS: J = PE = MR = H K=L 1. P2. P1.3 V trec PE ts(L) CLOCK 1. Setup (ts) and Hold (th) Time for Serial Data (J & K) and Parallel Data (P0.3 V ts(L) th(L) = 0 P0 P1 P2 P3 1.3 V 1.3 V ts(H) trel 1. PE 1. Figure 4.SN74LS195A DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition.3 V th(L) = 0 CLOCK OUTPUT* ts(L) ts(H) th(H) = 0 1.3 V 1.3 V OUTPUT Qn = Pn Qn* = Qn–1 trel 1.

Once triggered.25 70 – 0. If pulse cutoff is not critical. 1999 – Rev.0 Unit V °C mA mA SN74LS221D 16 Pin 2500/Tape & Reel Device SN74LS221N Package 16 Pin DIP Shipping 2000 Units/Box © Semiconductor Components Industries.0 V and 25°C temperature. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF).com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B • SN74LS221 is a Dual Highly Stable One-Shot • Overriding Clear Terminates Output Pulse • Pin Out is Identical to SN74LS123 ORDERING INFORMATION GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. pulse stability will only be limited by the accuracy of external timing components. In most applications. where tW is in ns if Cext is in pF and Rext is in kΩ. the outputs are independent of further transitions of the inputs and are a function of the timing components. providing the circuit with excellent noise immunity. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. capacitance up to 1000 µF and resistance as low as 1.SN74LS221 Dual Monostable Multivibrators with Schmitt-Trigger Inputs Each multivibrator of the LS221 features a negative-transitiontriggered input and a positive-transition-triggered input either of which can be used as an inhibit input. 6 Publication Order Number: SN74LS221/D .4 kΩ may be used. a typical output pulse of 30 nanoseconds is achieved. The output pulses can be terminated by the overriding clear. Pulse width is defined by the relationship: tw(out) = CextRext ln 2. http://onsemi.4 8. With Rext = 2. LLC. Input pulse width may be of any duration relative to the output pulse width. 1999 163 December.75 0 Typ 5. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt / second.0 to 100 kΩ for the SN74LS221). A high immunity to VCC noise is also provided by internal latching circuitry.0 kΩ and Cext = 0. Output rise and fall times are independent of pulse length. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. The range of jitter-free pulse widths is extended if VCC is 5.0 25 Max 5.7 Cext Rext.0 ≈ 0. and greater than one decade of timing resistance (2. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse.

VCC Rext + Cext R/C FUNCTION TABLE (EACH MONOSTABLE) INPUTS CLEAR L X X H H *° OUTPUTS B X X L ° H H Q L L L Q H H H A X H X L ± L *See operational notes — Pulse Trigger Modes TYPE SN74LS221 TYPICAL POWER DISSIPATION 23 mW MAXIMUM OUTPUT PULSE LENGTH 70 s http://onsemi.com 164 .SN74LS221 (TOP VIEW) VCC 16 1 Rext/ 1 Cext Cext 15 14 Q Q CLR 1Q 13 2Q 12 2 CLR 11 2B 10 2A 9 CLR Q Q 4 1Q 5 2Q 6 2 Cext 8 7 2 Rext/ GND Cext 1 1A 2 1B 3 1 CLR Positive logic: Low input to clear resets Q low and Positive logic: Q high regardless of dc levels at A Positive logic: or B inputs.

rises above 50%. jitter is not appreciable until the duty cycle approaches 90%. Rext and Cext. This pulse width is essentially independent of VCC and temperature variations. (Jitter is independent of Cext). it may be forced low by bringing the clear input low. the output pulse width will become shorter. as long as the output remains high.0 µV/s). The LS123 is retriggerable so that the output is dependent upon the input transitions once it is high.SN74LS221 OPERATIONAL NOTES Once in the pulse trigger mode. Inputs should then be set up per the truth table (without triggering the output) to allow Clear to be used a trigger for the output pulse. it cannot be retriggered by other inputs. irregardless of the previous output state and other input states. it should be remembered that they are not functionally identical. t If the duty cycle. or jitter. Q will go low for a corresponding length of time. the Q output is low. The Clear input may also be used to trigger an output pulse. With Rext = 100K. Inhibit Mode: Pulse Trigger Mode: A transition of the A or B inputs as indicated in the functional truth table will trigger the Q output to go high for a duration determined by the tW equation described above. If the duty cycle varies between low and high valves. To reduce jitter to a minimum. Also note that it is recommended to externally ground the LS123 Cext pin. once the Q output goes low. The SN74LS221 is a dual. Output pulse widths varies typically no more than ±0. the A input must be set high OR the B input must be set low to allow Clear to be used as a trigger. If the Clear pin is routinely being used to trigger the output pulse. High immunity to VCC noise (typically 1. independent of the input slew rate.5 V) is achieved by internal latching circuitry. Rext should be as large as possible.5% from device to device. tW can be varied over 9 decades of timing by proper selection of the external timing components. The LS221 has four basic modes of operation. monolithic. but special logic preconditioning on the A or B inputs must be done as follows: Following any output triggering action using the A or B inputs. only the B input should be used for very long transition triggers (≥1. Once triggered. therefore. standard VCC bypassing is strongly recommended. Although all three inputs have this Schmitt-trigger effect.com 165 . Although the LS221 is pin-for-pin compatible with the LS123. Clear Mode: If the clear input is held low. However. http://onsemi. the output pulse width is determined by tW = RextCextIn2. as long as Rext and Cext are within their minimum and maximum valves and the duty cycle is less than 50%. defined as being 100 @ W where T is the T period of the input pulse. However. Overriding Clear Mode: If the Q output is high. high-stability one shot. If either the A input is high or the B input is low. non-retriggerable. The output pulse width. Pulse triggering occurs at a voltage level and is. the A or B inputs must be toggled as described above before and between each Clear trigger event. this cannot be done on the LS221. This is not the case for the LS221. this causes the output pulse width to vary in length. all input transitions (except overriding Clear) are ignored.

5 20 IIH 0.8 0.7 Min Typ 1. IIN = – 18 mA VCC = MIN.0 0.4 V IOS ICC mA VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time. IOH = MAX IOL = 8.4 0.7 3.8 – 100 11 27 2.0 V IIL mA VCC = MAX. VIN = 7.9 2.SN74LS221 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– Parameter Positive-Going Threshold Voltage at C Input Negative-Going Threshold Voltage at C Input Positive-Going Threshold Voltage at B Input Negative-Going Threshold Voltage at B Input Input HIGH Voltage Input LOW Voltage Input Clamp Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current 0.com 166 . VIN = 0.7 19 – 0. http://onsemi.8 – 0.8 – 1.7 V VCC = MAX.0 0.35 0. nor for more than 1 second. VIN = 2.0 V V VIH VIL VIK VOH VOL 2.4 – 0.5 V V V V V µA mA VCC = MAX.1 Input LOW Current Input A Input B Clear Short Circuit Current (Note 1) Power Supply Current Quiescent Triggered – 20 4.8 Max 2.0 mA VCC = MIN Test Conditions VT+ VT– 1.0 Unit V V VCC = MIN VCC = MIN VCC = MIN VCC = MIN Guaranteed Input HIGH Voltage for A Input Guaranteed Input LOW Voltage for A Input VCC = MIN.0 0.

0 V. B Logic Input.0 V/s V/µs Min Typ Max Unit http://onsemi.5 ms Limits Min Typ 45 35 50 40 35 44 120 47 Max 70 ns 55 80 ns 65 55 65 150 70 ns ns ns CL = 15 pF. 20 Unit Test Conditions AC SETUP REQUIREMENTS (VCC = 5. See Figure 1 Cext = 80 pF.0 kΩ Cext = 100 pF.0 1. TA = 25°C) Limits Symbol Parameter Rate of Rise or Fall of Input Pulse dv/dt Schmitt.9 750 7.0 670 6.4 0 100 1000 ns kΩ µF ns 1. Rext = 10 kΩ Cext = 1.0 kΩ RT = MAX Rext 50 90 % A or B. TA = 25°C) Symbol tPLH From (Input) A B A tPHL tPHL tPLH B Clear Clear To (Output) Q Q Q Q Q Q 70 20 tW(out) ( ) A or B Q or Q 600 6.com 167 .SN74LS221 AC CHARACTERISTICS (VCC = 5.0 V. Rext = 2.0 Ω pF. tW (clear) 40 40 15 1.0 µF. Rext = 2. Rext = 10 kΩ Cext = 80 pF Rext = 2.0 Ω Cext = 0. tW(in) Clear. A Input Pulse Width tW ts Rext Cext Clear-Inactive-State Setup Time External Timing Resistance External Timing Capacitance Output Duty Cycle RT = 2.

TRIGGER FROM B. http://onsemi.3 V 3V 0V 3V 0V Q OUTPUT A INPUT IS LOW. tW(out) ≥0 ts 3V 0V 3V 0V VOH VOL CLEAR OVERRIDING B.SN74LS221 AC WAVEFORMS tW(in) B INPUT ≥60 ns CLEAR tPLH Q OUTPUT tPHL Q OUTPUT A INPUT IS LOW.3 V 3V 0V VOH VOL B INPUT ≥ 50 ns CLEAR TRIGGERED Q OUTPUT NOT TRIGGERED A INPUT IS LOW.com 168 . THEN CLEAR — CONDITION 1 3V 1. THEN CLEAR — CONDITION 2 0V 1.3 V 0V 3V tPHL 0V VOH VOL VOH VOL tPLH 3V B INPUT ≥ 60 ns CLEAR Q OUTPUT A INPUT IS LOW. TRIGGERING FROM POSITIVE TRANSITION OF CLEAR VOH VOL Figure 1. TRIGGER FROM B. THEN TRIGGER FROM B B INPUT ≥ 50 ns CLEAR ≥ 50 ns 1.

1999 – Rev.75 0 Typ 5. clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.com • Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address • Input Clamp Diodes Limit High-Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC TA IOH Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Min 4. http://onsemi.0 25 Max 5. LLC. 6 Publication Order Number: SN74LS240/D .25 70 – 3.0 – 15 IOL Output Current – Low 24 Unit V °C 20 Registers LOW POWER SCHOTTKY mA mA mA 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS240N SN74LS240DW SN74LS244N SN74LS244DW Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.SN74LS240 SN74LS244 Octal Buffer/Line Driver with 3-State Outputs The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers. 1999 169 December.

2G L L H D L H X L H (Z) http://onsemi.com 170 .SN74LS240 SN74LS244 LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) SN74LS240 VCC 20 2G 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND SN74LS244 VCC 20 2G 19 1Y1 18 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 17 16 15 14 13 12 11 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND TRUTH TABLES SN74LS240 INPUTS OUTPUT 1G. 2G L L H D L H X H L (Z) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance SN74LS244 INPUTS OUTPUT 1G.

0 V VCC = MAX. VIN = 0.4 Output HIGH Voltage 2. VIN = 2.0 0. IOH = – 3.SN74LS240 SN74LS244 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VT+–VT– VIK VO OH Parameter Input HIGH Voltage Input LOW Voltage Hysteresis Input Clamp Diode Voltage 2. VIN = 7.7 V VCC = MAX.25 VO OL IOZH IOZL IIH IIL IOS Output LOW Voltage 0. IOH = MAX IOL = 12 mA VCC = VCC MIN.1 Input LOW Current Output Short Circuit Current (Note 1) Power Supply Current Total. VOUT = 2.5 Min 2. AC CHARACTERISTICS (TA = 25°C.0 mA VCC = MIN.8 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN VCC = MIN. IIN = – 18 mA VCC = MIN. Output LOW ICC Total at HIGH Z LS240 LS244 LS240 LS244 – 40 – 0. RL = 667 Ω CL = 45 pF.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay.0 0. Data to Output LS244 Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time from LOW Level Output Disable Time from HIGH Level Min Typ 9.7 V VCC = MAX.2 – 225 27 44 46 50 54 mA A VCC = MAX 0.4 V V 0. Data to Output LS240 Propagation Delay. RL = 667 Ω Test Conditions http://onsemi.65 3.2 0.0 12 12 12 15 20 15 10 Max 14 18 18 18 23 30 25 18 Unit ns ns ns ns ns ns CL = 5.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0. VOUT = 0.4 – 1.4 V VCC = MAX. nor for more than 1 second. VIN = VIL or VIH per Truth Table VCC = MAX.com 171 .0 pF.4 – 0. VCC = 5.5 20 – 20 20 V µA µA µA mA mA mA IOL = 24 mA 0. Output HIGH Total.

3 V VCC RL VOUT 1.3 V tPLH 1.3 V VE VOUT tPZH 1.3 V VOL 0. http://onsemi.3 V Figure 1.3 V tPLZ ≈ 1.3 V CL* 5 kΩ SW2 Figure 2.3 V tPHZ ≥VOH ≈ 1.3 V 1.3 V tPHL VOUT 1.5 V SWITCH POSITIONS SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed Figure 3. VE VE VOUT 1.SN74LS240 SN74LS244 AC WAVEFORMS VIN 1.3 V 0.3 V 1. SW1 TO OUTPUT UNDER TEST VIN 1.com 172 . VE 1.5 V Figure 4.3 V 1.3 V tPZL 1. Figure 5.3 V tPLH 1.3 V tPHL 1.

The Enable input (E) can be used to isolate the buses. 1999 173 December. http://onsemi.0 – 15 IOL Output Current – Low 24 Unit V °C mA mA mA Device SN74LS245N SN74LS245DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel ORDERING INFORMATION © Semiconductor Components Industries.0 25 Max 5.75 0 Typ 5.25 70 – 3.com • • • • Hysteresis Inputs to Improve Noise Immunity 2-Way Asynchronous Data Bus Communication Input Diodes Limit High-Speed Termination Effects ESD > 3500 Volts LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) VCC 20 E 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11 LOW POWER SCHOTTKY 20 1 1 DIR 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 GND PLASTIC N SUFFIX CASE 738 TRUTH TABLE INPUTS OUTPUT E L L H DIR L H X Bus B Data to Bus A Bus A Data to Bus B Isolation 20 1 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial SOIC DW SUFFIX CASE 751D GUARANTEED OPERATING RANGES Symbol VCC TA IOH Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Min 4. LLC.SN74LS245 Octal Bus Transceiver The SN74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. 6 Publication Order Number: SN74LS245/D . Direction Input (DR) controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. 1999 – Rev.

VIN = 7.0 V VCC = MAX. AC CHARACTERISTICS (TA = 25°C.0 25 27 15 15 Max 12 12 40 40 25 25 Unit ns ns ns ns ns CL = 5. VOUT = 2. Output LOW Total at HIGH Z – 40 0.0 ns) Limits Symbol tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay. VOUT = 0.65 3.4 V V 0.0 0.7 V VCC = MAX. RL = 667 Ω Test Conditions http://onsemi. VIN = VIL or VIH per Truth Table VCC = MAX.5 20 – 200 20 0.4 V VCC = MAX.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.1 – 0.1 0.35 Output Off Current HIGH Output Off Current LOW A or B.4 – 0. F.0 0. VCC = 5.SN74LS245 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VT+–VT– VIK VO OH Parameter Input HIGH Voltage Input LOW Voltage Hysteresis Input Clamp Diode Voltage 2.2 – 225 70 90 95 mA A VCC = MAX V µA µA µA mA mA mA mA IOL = 24 mA 0.25 VO OL IOZH IOZL Output LOW Voltage 0.4 – 1. DR or E IIH Input HIGH C I t Current t DR or E A or B IIL IOS Input LOW Current Output Short Circuit Current (Note 1) Power Supply Current Total. Output HIGH ICC Total.4 Output HIGH Voltage 2. VIN = 5.2 0.0 8.0 mA VCC = MIN. VIN = 0. IOH = – 3. IOH = MAX IOL = 12 mA VCC = VCC MIN.8 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN VCC = MIN. TRISE / TFALL ≤ 6. VIN = 2. nor for more than 1 second.0 V.5 Min 2. RL = 667 Ω CL = 45 pF.5 V VCC = MAX.com 174 . IIN = – 18 mA VCC = MIN.7 V VCC = MAX.0 pF. Data to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time from LOW Level Output Disable Time from HIGH Level Min Typ 8.

http://onsemi.25 70 – 50 3.com LOW POWER SCHOTTKY • Open-Collector Outputs Drive Indicators Directly • Lamp-Test Provision • Leading/ Trailing Zero Suppression GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL VO(off) IO(on) Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High BI/RBO Output Current – Low BI/RBO Off–State Output Voltage a–g On–State Output Current a–g Min 4.SN74LS247 BCD-to-Seven-Segment Decoders/Drivers The SN74LS247 is a BCD-to-Seven-Segment Decoder/Drivers. The LS247 composes the and with the tails. 1999 – Rev. 1999 175 December. The LS247 has active-low outputs for direct drive of indicators. Display pattern for BCD input counts above 9 are unique symbols to authenticate input conditions. The LS247 features a lamp test input and have full ripple-blanking input/output controls. LLC.75 0 Typ 5.2 15 24 Unit V °C 16 1 PLASTIC N SUFFIX CASE 648 mA 16 mA V mA 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS247N SN74LS247D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. Segment identification and resultant displays are shown below. 6 Publication Order Number: SN74LS247/D .0 25 Max 5. An automatic leading and/or trailing-edge zero-blanking control (RBI and RBO) is incorporated and an overriding blanking input (BI) is contained which may be used to control the lamp intensity by pulsing or to inhibit the output’s lamp test may be performed at any time when the BI/RBO node is at high level.

com 176 .SN74LS247 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS a f e d g b c SEGMENT IDENTIFICATION SN74LS247 (TOP VIEW) OUTPUTS VCC 16 f 15 g 14 f g a 13 b 12 c 11 d 10 e 9 a b c d e BI/ B C LT RBORBI D A 1 B 2 C INPUTS 3 4 LAMP RB TEST OUT PUT 5 RB IN PUT 6 D 7 A 8 GND INPUTS CIRCUIT FEATURES LAMP INTENSITY MODULATION CAPABILITY DRIVER OUTPUTS TYPE SN74LS247 ACTIVE LEVEL low OUTPUT CONFIGURATION open-collector SINK CURRENT 24 mA MAX VOLTAGE 15 V TYPICAL POWER DISSIPATION 35 mW http://onsemi.

SN74LS247 LOGIC DIAGRAM LS247 (13) INPUT (7) A INPUT (1) B INPUT (2) C INPUT (6) D BI/RBO BLANKING (4) INPUT OR RIPPLE-BLANKING OUTPUT (3) (14) (12) OUTPUT a OUTPUT b OUTPUT c OUTPUT d OUTPUT e OUTPUT f OUTPUT g (11) (10) (9) (15) LAMP TEST INPUT RBI (5) RIPPLE-BLANKING INPUT http://onsemi.com 177 .

and D are at a low level with the lamp test input high. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input. B. X = Irrelevant NOTES: 1. When ripple-blanking input (RBI) and inputs A. all segment outputs are on. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. L = LOW Level. C. 2. http://onsemi. 3. When a low logic level is applied directly to the blanking input (BI). all segment outputs are off regardless of the level of any other input. 4. BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.SN74LS247 LS247 FUNCTION TABLE DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT INPUTS LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X D L L L L L L L L H H H H H H H H X L X C L L L L H H H H L L L L H H H H X L X B L L H H L L H H L L H H L L H H X L X A L H L H L H L H L H L H L H L H X L X H H H H H H H H H H H H H H H H L L H BI/RBO a ON OFF ON ON OFF ON ON ON ON ON OFF OFF OFF ON OFF OFF OFF OFF ON b ON ON ON ON ON OFF OFF ON ON ON OFF OFF ON OFF OFF OFF OFF OFF ON c ON ON OFF ON ON ON ON ON ON ON OFF ON OFF OFF OFF OFF OFF OFF ON OUTPUTS d ON OFF ON ON OFF ON ON OFF ON ON ON ON OFF ON ON OFF OFF OFF ON e ON OFF ON OFF OFF OFF ON OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON f ON OFF OFF OFF ON ON ON OFF ON ON OFF OFF ON ON ON OFF OFF OFF ON g OFF OFF ON ON ON ON ON OFF ON ON ON ON ON ON ON OFF OFF OFF ON 2 3 4 NOTE 1 H = HIGH Level. all segment outputs go off and the ripple-blanking output (RBO) goes to a low level (response condition).com 178 .

nor for more than 1 second.25 0. VIL = MAX IO(on) = 12 mA IO(on) = 24 mA VCC = MIN.4 0.8 – 1.5 Typ Max Unit V V V V V V µA V V µA mA Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.com 179 . VIN = 2.0 V.2 – 2.0 0.35 2. VIN = 0.4 – 0.0 13 mA mA VCC = MAX VCC = MAX 0.2 0.1 Input LOW Current Any Input. VIH = 2. VIN = VIL or VIH per Truth Table VO OL IO(off) VO( ) O(on) VCC = MAX.65 4.4 0.6 mA IOL = 3. RL = 665 Ω Test Conditions http://onsemi. IIN = – 18 mA VCC = MIN.2 mA VCC = VCC MIN. VIH = 2. TA = 25°C) Limits Symbol tPLH tPHL tPHL tPLH Parameter Turn-Off Time from A Input Turn-On Time from A Input Turn-Off Time from RBI Input Turn-On Time from RBI Input Min Typ Max 100 100 100 100 Unit ns ns CL = 15 pF. VO(off) = 15 V. VIN = 7.0 V VCC = MAX.4 – 1. IOH = MAX.3 7. AC CHARACTERISTICS (VCC = 5. VIL per Truth Table VCC = MAX.25 0.5 250 0.7 V VCC = MAX. except BI / RBO BI / RBO IOS ICC Short Circuit Current BI / RBO (Note 1) Power Supply Current – 0.0 – 0.4 V IIL mA Note 1: Not more than one output should be shorted at a time.0 V. VIN = VIH or VIL per Truth Table IOL = 1.5 20 IIH Min 2.35 0.SN74LS247 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage BI / RBO Output LOW Voltage g BI / RBO Off-State Output Current a–g On-State Output Voltage g a–g Input HIGH Current 0.0 V.

6 Publication Order Number: SN74LS251/D . It provides.75 0 Typ 5. the ability to select one bit of data from up to eight sources. The LS251 can be used as a universal function generator to generate any logic function of four variables.25 70 – 2. Both assertion and negation outputs are provided. 1999 – Rev. in one package.6 24 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS251N SN74LS251D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.0 25 Max 5. LLC. http://onsemi.SN74LS251 8-Input Multiplexer with 3-State Outputs The TTL/MSI SN74LS251 is a high speed 8-Input Digital Multiplexer.com • • • • • Schottky Process for High Speed Multifunction Capability On-Chip Select Logic Decoding Inverting and Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 180 December.

5 U.25 U.com 181 .L.5 U. 15 U. LOW 0.SN74LS251 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 I4 15 I5 14 I6 13 I7 12 S0 11 S1 10 S2 9 1 I3 2 I2 3 I1 4 I0 5 Z 6 Z 7 E0 8 GND LOADING (Note a) PIN NAMES S0 – S2 E0 I0 – I7 Z Z Select Inputs Output Enable (Active LOW) Inputs Multiplexer Inputs Multiplexer Output Complementary Multiplexer Output HIGH 0. 0.25 U. 0. 0.L. 65 U. 0.L.L. NOTES: a) 1 TTL Unit Load (U. LOGIC DIAGRAM I0 S2 S1 S0 E1 9 10 11 7 4 I1 3 I2 2 I3 1 I4 15 I5 14 I6 13 I7 12 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Z 5 6 Z http://onsemi. 15 U. 65 U.L.L.) = 40 mA HIGH/1.L.25 U.5 U.L.L.L.6 mA LOW.L.

This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. the logic function provided at the output is: Z = EO ⋅ (I0 ⋅ S0 ⋅ S1 ⋅ S2 + I1 ⋅ S0 ⋅ S1 ⋅ S2 + I2 ⋅ S0 ⋅ S1 ⋅ Z = E O ⋅ S 2 + I 3 ⋅ S 0 ⋅ S 1 ⋅ S 2 + I4 ⋅ S 0 ⋅ S 1 ⋅ S 2 + I5 ⋅ S 0 ⋅ Z = EO ⋅ S1 ⋅ S2 + I6 ⋅ S0 ⋅ S1 ⋅ S2 + I7 ⋅ S0 ⋅ S1 ⋅ S2).com 182 . TRUTH TABLE E0 H L L L L L L L L L L L L L L L L S2 X L L L L L L L L H H H H H H H H S1 X L L L L H H H H L L L L H H H H S0 X L L H H L L H H L L H H L L H H I0 X L H X X X X X X X X X X X X X X I1 X X X L H X X X X X X X X X X X X I2 X X X X X L H X X X X X X X X X X I3 X X X X X X X L H X X X X X X X X I4 X X X X X X X X X L H X X X X X X I5 X X X X X X X X X X X L H X X X X I6 X X X X X X X X X X X X X L H X X I7 X X X X X X X X X X X X X X X L H Z (Z) H L H L H L H L H L H L H L H L Z (Z) L H L H L H L H L H L H L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care (Z) = High impedance (Off) http://onsemi. S2. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltage. 8-position switch with the switch position controlled by the state of three Select inputs. Both assertion and negation outputs are provided. When the Output Enable is HIGH. S1. When it is activated. The Output Enable input (EO) is active LOW. S0. both outputs are in the high impedance (high Z) state.SN74LS251 FUNCTIONAL DESCRIPTION The LS251 is a logical implementation of a single pole. When the outputs of the 3-state devices are tied together. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings.

65 3.0 V VCC = MAX. nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C. Select to Z Output Propagation Delay.8 – 1.7 V VCC = MAX.4 Min 2. VIN = 0.4 V VCC = MAX VCC = MAX.0 pF.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0. VIN = 7.7 V VCC = MAX.0 0. VE = 0 V VCC = MAX. VCC = 5. Data to Z Output Propagation Delay.4 – 130 10 0. RL = 667 kΩ CL = 15 pF.1 0. Data to Z Output Output Enable Time to Z Output Output Enable Time to Z Output Output Disable Time to Z Output Output Disable Time to Z Output Min Typ 20 21 29 28 10 9.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 12 mA – 30 – 0. 5 CL = 5. VE = 4.4 V VCC = MAX.5 20 – 20 20 V µA µA µA mA mA mA mA IOL = 24 mA 0.4 – 0. 5 Figures 3.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ Parameter Propagation Delay. IIN = – 18 mA VCC = MIN.0 kΩ Test Conditions http://onsemi.com 183 . 5 Figures 4. IOH = MAX. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN. VOUT = 0. VIN = 2.0 17 18 17 24 30 26 37 15 30 15 Max 33 33 45 45 15 15 28 28 27 40 45 40 55 25 45 25 Unit ns ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 1 Figures 2 Figures 4.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. RL = 2.25 VO OL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 0. VIN = VIL or VIH per Truth Table VCC = MAX.5 V Note 1: Not more than one output should be shorted at a time. Select to Z Output Propagation Delay. 5 Figures 3.SN74LS251 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. VOUT = 2.

3 V 1. AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed SW1 TO OUTPUT UNDER TEST 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance.3 V ≥ VOH ≈ 1.3 V VIN 1.3 V tPLH 1.3 V 0.3 V VOUT 1.3 V tPHZ 1.5 V 1. Figure 5.3 V 1.3 V VOUT 1.3 V tPLZ VE tPZH ≈ 1.SN74LS251 3-STATE AC WAVEFORMS VIN 1.3 V 0. 0.5 V Figure 3.com 184 . VE tPZL VOUT 1.3 V Figure 1.3 V tPHL 1. http://onsemi.3 V tPLH 1. Figure 2.5 V Figure 4.3 V VOL VOUT 1.3 V tPHL 1.

LLC. allowing the outputs to interface directly with bus oriented systems.25 70 – 2. http://onsemi.com • • • • Schottky Process for High Speed Multifunction Capability Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (E0) inputs. 6 Publication Order Number: SN74LS253/D .0 25 Max 5. It can select two bits of data from four sources using common select inputs.6 24 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS253N SN74LS253D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 1999 185 December. 1999 – Rev. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.75 0 Typ 5.SN74LS253 Dual 4-Input Multiplexer with 3-State Outputs The LSTTL / MSI SN74LS253 is a Dual 4-Input Multiplexer with 3-state outputs.

L. 0.L.L. 65 U.5 U.5 U.L. 0.L.25 U. 1 E0a 2 S1 3 I3a 4 I2a 5 I1a 6 I0a 7 Za 8 GND LOADING (Note a) PIN NAMES S0. 0.L.25 U. 0.6 mA LOW.L.) = 40 mA HIGH/1.L.5 U.L.25 U.L. S1 Multiplexer A E0a I0a – I3a Za Multiplexer B E0b I0b – I3b Zb Common Select Inputs Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output HIGH 0. LOGIC SYMBOL 1 6 5 4 3 10 11 12 13 15 14 2 E I I I I I I I I E S0 0a 0a 1a 2a 3a 0b 1b 2b 3b 0b S1 Za Zb 7 VCC = PIN 16 GND = PIN 8 9 http://onsemi.com 186 .L. 65 U. 0.25 U. NOTES: a) 1 TTL Unit Load (U.L.L.5 U.SN74LS253 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E0b 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 0. 0. 15 U. LOW 0. 0.25 U.L.L. 15 U.5 U.

http://onsemi. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The logic equations for the outputs are shown below: Za = E0a ⋅(I0a ⋅S1 ⋅S0 + I1a ⋅S1 ⋅S0 ⋅I2a ⋅S1 ⋅S0 + I3a ⋅ S1 ⋅S0) Zb = E0b⋅ (I0b S1 S0 + I1b⋅ S1⋅ S0 I2b⋅ S1⋅ S0 + I3b⋅ S1⋅ S0) If the outputs of 3-state devices are tied together. where the position of the switch is determined by the logic levels supplied to the two select inputs. The LS253 is the logic implementation of a 2-pole. E0b) inputs which when HIGH. The 4-input multiplexers have individual Output Enable (E0a. TRUTH TABLE SELECT INPUTS S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X DATA INPUTS I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT ENABLE E0 H L L L L L L L L OUTPUT Z (Z) L H L H L H L H H = HIGH Level L = LOW Level X = Irrelevant (Z) = High Impedance (off) Address inputs S0 and S1 are common to both sections. S1). forces the outputs to a high impedance (high Z) state.SN74LS253 LOGIC DIAGRAM E0b 15 I3b 13 I2b 12 I1b 11 I0b 10 S0 14 S1 2 I3a 3 I2a 4 I1a 5 I0a 6 E0a 1 Zb 9 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Za 7 FUNCTIONAL DESCRIPTION The LS253 contains two identical 4-Input Multiplexers with 3-state outputs. 4-position switch. They select two bits from four sources selected by common select inputs (S0.com 187 . Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap.

0 0. AC CHARACTERISTICS (TA = 25°C.4 – 130 12 0.1 0. RL = 667 Ω Test Conditions http://onsemi. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN.5 20 – 20 20 V µA µA µA mA mA mA mA IOL = 24 mA 0. VIN = 7. nor for more than 1 second.5 V Note 1: Not more than one output should be shorted at a time.4 – 0. VE = 0 V VCC = MAX.25 VO OL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 0.4 V VCC = MAX VCC = MAX.0 V VCC = MAX.8 – 1. 5 CL = 5.7 V VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX. VOUT = 2. IIN = – 18 mA VCC = MIN.0 V) See SN74LS251 for Waveforms Limits Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay.4 V VCC = MAX.SN74LS253 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. Select to Output Output Enable Time Output Disable Time Min Typ 17 13 30 21 15 15 27 18 Max 25 20 45 32 28 23 41 27 Unit ns ns ns ns Figure 1 Figure 1 Figures 4.com 188 .5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = 2.7 V VCC = MAX.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0. 5 Figures 3. IOH = MAX. VCC = 5. VIN = 0.0 pF. VE = 4.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 14 mA – 30 – 0. RL = 667 Ω CL = 45 pF. VOUT = 0. Data to Output Propagation Delay.4 Min 2.65 3.

The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (EO) Input.0 25 Max 5.SN74LS257B SN74LS258B Quad 2-Input Multiplexer with 3-State Outputs The LSTTL / MSI SN74LS257B and the SN74LS258B are Quad 2-Input Multiplexers with 3-state outputs.25 70 – 2. allowing the outputs to interface directly with bus oriented systems. 6 Publication Order Number: SN74LS257B/D . LLC.com LOW POWER SCHOTTKY • • • • • • Schottky Process For High Speed Multiplexer Expansion By Tying Outputs Together Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects Special Circuitry Ensures Glitch Free Multiplexing ESD > 3500 Volts 16 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 – Rev. http://onsemi. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. 1999 189 December. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non-inverted) form.75 0 Typ 5.6 24 Unit V °C mA mA 16 PLASTIC N SUFFIX CASE 648 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS257BN SN74LS257BD SN74LS258BN SN74LS258BD Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.

SN74LS257B SN74LS258B CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 E0 15 I0c 14 I1c 13 Zc 12 I0d 11 I1d 10 Zd 9 SN74LS257B VCC = PIN 16 GND = PIN 8 1 S VCC 16 2 I0a E0 15 3 I1a I0c 14 4 Za I1c 13 5 I0b Zc 12 6 I1b I0d 11 7 Zb I1d 10 8 GND Zd 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.com 190 . SN74LS258B 1 S 2 I0a 3 I1a 4 Za 5 I0b 6 I1b 7 Zb 8 GND http://onsemi.

com 191 .SN74LS257B SN74LS258B LOGIC DIAGRAMS SN74LS257B E0 15 I0a 2 I1a 3 I0b 5 I1b 6 I0c 14 I1c 13 I0d 11 I1d 10 S 1 4 7 12 9 Za Zb Zc Zd SN74LS258B E0 15 I0a 2 I1a 3 I0b 5 I1b 6 I0c 14 I1c 13 I0d 11 I1d 10 S 1 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 7 12 9 Za Zb Zc Zd http://onsemi.

When the Select Input is LOW. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. They select four bits of data from two sources each under control of a Common Data Select Input. The logic equations for the outputs are shown below: LS257B Za = E 0 • Zc = E0 • (I1a • S + I0a • S) Zb = E0 • (I1b • S + I0b • S) (I1c • S + I0c • S) Zd = E0 • (I1d • S + I0d • S) When the Output Enable Input (E0) is HIGH. the I0 inputs are selected and when Select is HIGH. The LS257B and LS258B are the logic implementation of a 4-pole. If the outputs are tied together. the I1 inputs are selected. LS258B Za = E 0 • Zc = E0 • (I1a • S + I0a • S) Zb = E0 • (I1c • S + I0c • S) Zd = E0 • (I1b • S + I0b • S) (I1d • S + I0d • S) TRUTH TABLE OUTPUT ENABLE EO H L L L L SELECT INPUT S X H H L L DATA INPUTS I0 X X X L H I1 X L H X X OUTPUTS LS257B Z (Z) L H L H OUTPUTS LS258B Z (Z) H L H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care (Z) = High Impedance (off) http://onsemi. 2-position switch where the position of the switch is determined by the logic levels supplied to the Select Input. The data on the selected inputs appears at the outputs in true (non-inverted) form for the LS257B and in the inverted form for the LS258B.com 192 .SN74LS257B SN74LS258B FUNCTIONAL DESCRIPTION The LS257B and LS258B are Quad 2-Input Multiplexers with 3-state outputs. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. the outputs are forced to a high impedance “off” state.

4 V VCC = MAX.com 193 .4 – 0. VOUT = 0.8 – 1. VCC = 5.65 3.0 V VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX.2 – 0.7 V IIH mA mA mA VCC = MAX. Output LOW Total. IIN = – 18 mA VCC = MIN. AC CHARACTERISTICS (TA = 25°C.4 – 130 V µA µA µA IOL = 24 mA 0. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN. VIN = 7.35 Output Off Current — HIGH Output Off Current — LOW Input HIGH Current Other Inputs S Inputs Other Inputs S Inputs IIL IOS Input LOW Current All Inputs Short Circuit Current (Note 1) Power Supply Current Total.7 V VCC = MAX. VIN = 0.0 16 14 19 16 mA VCC = MAX – 30 0. VOUT = 2. Data to Output Propagation Delay.1 0.4 Min 2.SN74LS257B SN74LS258B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. Output 3-State LS257B LS258B LS257B LS258B LS257B LS258B 10 9. VIN = 2.25 VO OL IOZH IOZL Output LOW Voltage 0. Select to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time to LOW Level Output Disable Time from HIGH Level Min Typ 10 12 14 14 20 20 16 18 Max 13 15 21 21 25 25 25 25 Unit ns ns ns ns ns ns Test Conditions Figures 1 & 2 CL = 45 pF Figures 1 & 2 Figures 4 & 5 Figures 3 & 5 Figures 3 & 5 Figures 4 & 5 CL = 45 pF RL = 667 Ω CL = 5.4 V VCC = MAX mA mA Note 1: Not more than one output should be shorted at a time. Output HIGH ICC Total.1 0.0 V) See SN74LS251 for Waveforms Limits Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 0. IOH = MAX. nor for more than 1 second.0 pF RL = 667 Ω http://onsemi.5 20 – 20 20 40 0.

http://onsemi.0 25 Max 5. 6 Publication Order Number: SN74LS259/D .0 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS259N SN74LS259D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. an active LOW Enable.SN74LS259 8-Bit Addressable Latch The SN74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. It is a multifunctional device capable of storing single line data in eight addressable latches. LLC.75 0 Typ 5.4 8. The device also incorporates an active LOW common Clear for resetting all latches. 1999 194 December.com • • • • • • Serial-to-Parallel Conversion Eight Bits of Storage With Output of Each Bit Available Random (Addressable) Data Entry Active High Demultiplexing or Decoding Capability Easily Expandable Common Clear LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 – Rev.25 70 – 0. as well as.

L.L.SN74LS259 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 C 15 E 14 D 13 Q7 12 Q6 11 Q5 10 Q4 9 1 Ao 2 A1 3 A2 4 Q0 5 Q1 6 Q2 7 Q3 8 GND LOADING (Note a) PIN NAMES A0. 1.L.25 U.L.L.25 U. 0. 5 U. 10 U.L.L. http://onsemi. NOTES: a) 1 TTL Unit Load (U.25 U.L.L. 0. 0.5 U.5 U. A1.) = 40 mA HIGH/1. 0.com 195 . 0.5 U.0 U. A2 D E C Q0 – Q7 Address Inputs Data Input Enable (Active LOW) Input Clear (Active LOW) Input Parallel Latch Outputs HIGH 0.L. LOW 0.6 mA LOW.L.5 U.

The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the one-of-eight decoding or demultiplexing mode. The truth table below summarizes the operations. In the clear mode all outputs are LOW and unaffected by the address and data inputs.com 196 . When operating the SN74LS259 as an addressable latch. this should only be done while in the memory mode.SN74LS259 LOGIC DIAGRAM E 14 D 13 1 A0 2 A1 A2 3 15 C VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FUNCTIONAL DESCRIPTION The SN74LS259 has four modes of operation as shown in the mode selection table. Therefore. TRUTH TABLE PRESENT OUTPUT STATES Q1 L L L L H Q2 L L L L L Q3 L L L L L • • • • • L Q4 L L L L L Q5 L L L L L Q6 L L L L L Q7 L L L L L MODE Clear Demultiplex H X L L H H H X L L L L L QN–1 L H QN–1 QN–1 L L L L L H Memory H H X H H H H • • • • • H H I L L L • • • • • L L I H L H • • • • • L H QN–1 QN–1 L H QN–1 QN–1 QN–1 QN–1 QN–1 Addressable Latch X = Don’t Care Condition L = LOW Voltage Level H = HIGH Voltage Level QN–1 = Previous Output State • • • • • QN–1 QN–1 L H H H H H QN–1 QN–1 http://onsemi. In the addressable latch mode. In the memory mode. data on the Data line (D) is written into the addressed latch. the addressed output will follow the state of the D input with all MODE SELECTION E L H L H C H H L L MODE Addressable Latch Memory Active HIGH Eight-Channel Demultiplexer Clear C E D A0 L L L L L • • • • • L H L L L L • • • • • L X L H L H • • • • • H X L L H H A1 X L L L L • • • • • H X L L L L • • • • • H H A2 X L L L L Q0 L L H L L other inputs in the LOW state. changing more then one bit of the address could impose a transient wrong address. all latches remain in their previous state and are unaffected by the Data or Address inputs.

VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN. VCC = 5. Data to Output Turn-Off Delay.com 197 . VIN = 2.0 20 Typ Max Unit ns ns ns ns http://onsemi. Data to Output Turn-On Delay.5 20 V µA mA mA mA mA IOL = 8.5 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current –20 – 0. Clear to Output Min Typ 22 15 20 13 24 18 17 Max 35 24 32 21 38 29 27 Unit ns ns ns ns ns ns ns Test Conditions CL = 15 pF AC SET-UP REQUIREMENTS (TA = 25°C. VIN = VIL or VIH per Truth Table VCC = MAX. Enable to Output Turn-Off Delay. Address Parameter Min 20 15 5.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. VCC = 5.0 0.7 V VCC = MAX. Enable to Output Turn-On Delay.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. Clear or Enable Hold Time.4 Min 2.35 IIH IIL IOS ICC Input HIGH Current 0. Address to Output Turn-On Delay. IIN = – 18 mA VCC = MIN. AC CHARACTERISTICS (TA = 25°C. nor for more than 1 second. IOH = MAX.7 – 0.0 mA 0. VIN = 0.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Turn-Off Delay.8 – 1.25 VO OL Output LOW Voltage 0.0 V) Limits Symbol ts tW th th Input Setup Time Pulse Width.0 V VCC = MAX.65 3.SN74LS259 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. Data Hold Time. VIN = 7. Address to Output Turn-On Delay.4 – 100 36 0.

Clear to Output OTHER CONDITIONS: C = H Figure 6. Setup Time.3 V OTHER CONDITIONS: E = L. Turn-on and Turn-off Delays.3 V 1. C = H. http://onsemi.SN74LS259 AC WAVEFORMS D D tw E tPHL Q OTHER CONDITIONS: C = H.3 V E Q Q=D Q=D OTHER CONDITIONS: E = L. Data to Output Figure 1. A = STABLE tw 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. Enable To Output and Enable Pulse Width A1 1. Turn-on and Turn-off Delays.3 V tPHL 1.3 V A1 Q1 1. Turn-on and Turn-off Delays. A = STABLE tPLH 1.3 V Q 1. Address to Output Figure 4. Turn-on Delay.3 V tPLH 1. Setup and Hold Time.3 V tPHL 1.3 V D ts(H) th(H) ts(L) th(L) 1.3 V 1.3 V 1.3 V tPHL A ts E STABLE ADDRESS Q OTHER CONDITIONS: E = H 1. Data to Enable C 1.com 198 . C = L. Address to Enable (See Notes 1 and 2) NOTES: 1. D = H OTHER CONDITIONS: C = H. The shaded areas indicate when the inputs are permitted to change for predictable output performance.3 V tPLH 1. A = STABLE Figure 3. 2.3 V Figure 2.3 V Figure 5.

4 8.SN74LS260 Dual 5-Input NOR Gate VCC 14 13 12 11 10 9 8 http://onsemi.25 70 – 0.0 Unit V °C mA mA 14 1 PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS260N SN74LS260D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 1999 – Rev. 1999 199 December. 6 Publication Order Number: SN74LS260/D .com 1 2 3 4 5 6 7 GND LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.0 25 Max 5. LLC.75 0 Typ 5.

VIN = 0.5 0.4 – 100 4. VIN = VIH or VIL per Truth Table IOL = 4.5 20 V µA mA mA mA IOL = 8. VIN = 7.0 Max 15 15 Unit ns ns Test Conditions VCC = 5. Input to Output Min Typ 5. Input to Output Turn-On Delay.35 IIH IIL IOS ICC Input HIGH Current 0.0 5.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 mA 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 6. Output HIGH Total.65 3. AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL Parameter Turn-Off Delay. Output LOW –20 – 0.SN74LS260 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.0 0.7 – 0. IOH = MAX.0 V CL = 15 pF http://onsemi.4 Min 2.com 200 . nor for more than 1 second.8 – 1. IIN = – 18 mA VCC = MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.7 V VCC = MAX.5 0.0 V VCC = MAX.25 VO OL Output LOW Voltage 0.0 mA VCC = VCC MIN.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time. VIN = 2.

com • • • • 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 201 December.0 25 Max 5. This device is supplied in a 20-pin package featuring 0. 1999 – Rev. http://onsemi. LLC.4 8. 6 Publication Order Number: SN74LS273/D .SN74LS273 Octal D Flip-Flop with Clear The SN74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset.0 Unit V °C 20 mA mA 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS273N SN74LS273DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.75 0 Typ 5.3 inch lead spacing.25 70 – 0.

5 U.L.L. 0. LOW 0.L.L.25 U.L.L.25 U.6 mA LOW.25 U. 0. TRUTH TABLE MR L H H CP X Dx X H L Qx L H L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM 3 11 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q 1 MR VCC = PIN 20 GND = PIN 10 = PIN NUMBERS Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 http://onsemi.SN74LS273 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND LOADING (Note a) PIN NAMES CP D0 – D7 MR Q0 – Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs HIGH 0. NOTES: a) 1 TTL Unit Load (U.5 U.5 U.L.L.5 U.L. 0. 10 U.com 202 .) = 40 mA HIGH/1. 0.

MR to Q Output Propagation Delay.7 – 0. the Q outputs are LOW.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.0 V) Limits Symbol tw ts th trec Parameter Pulse Width.35 IIH IIL IOS ICC Input HIGH Current 0.65 3. Clock to Output Min 30 Typ 40 18 17 18 27 27 27 Max Unit MHz ns ns Test Conditions Figure 1 Figure 2 Figure 1 AC SETUP REQUIREMENTS (TA = 25°C. When the MR input is LOW.5 20 V µA mA mA mA mA IOL = 8.0 mA 0.4 – 100 27 0. IOH = MAX.0 V VCC = MAX.4 Min 2. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input.0 V) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay. Clock or Clear Data Setup Time Hold Time Recovery Time Min 20 20 5. independent of the other inputs.25 VO OL Output LOW Voltage 0. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. VIN = VIH or VIL per Truth Table IOL = 4. VCC = 5.8 – 1. VIN = VIL or VIH per Truth Table VCC = MAX. VCC = 5.5 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. AC CHARACTERISTICS (TA = 25°C. VIN = 2.SN74LS273 FUNCTIONAL DESCRIPTION The SN74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset.0 25 Typ Max Unit ns ns ns ns Test Conditions Figure 1 Figure 1 Figure 1 Figure 2 http://onsemi. IIN = – 18 mA VCC = MIN. nor for more than 1 second.0 mA VCC = VCC MIN. VIN = 7.0 0. VIN = 0.7 V VCC = MAX.com 203 .

3 V ts(L) Qn Figure 1.3 V tPHL 1. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.SN74LS273 AC WAVEFORMS 1/f max tW CP 1.3 V ts(H) D * 1. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. and Master Reset Recovery Time SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.3 V tPLH Qn CP tW 1.3 V tPLH Qn 1.3 V trec 1. Clock to Output Delays. Master Reset Pulse Width. Clock Pulse Width.3 V 1. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs.com 204 . Frequency. MR 1. Setup and Hold Times Data to Clock DEFINITION OF TERMS Figure 2.3 V 1.3 V th(H) 1.3 V 1. http://onsemi. Master Reset to Output Delay.3 V 1.3 V tPHL 1.3 V th(L) 1.3 V tPHL *The shaded areas indicate when the input is permitted to *change for predictable output performance.3 V tPLH 1.

0 25 Max 5. 1999 – Rev. The LS280 is designed without the expander input implementation. 7. but the corresponding function is provided by an input at Pin 4 and the absence of any connection at Pin 3. 9 H = HIGH Level. 5. The LS280 has buffered inputs to lower the drive requirements to one LS unit load. 2. LLC. 1999 205 December. L = LOW Level OUTPUTS ∑EVEN H L ∑ODD L H ORDERING INFORMATION Device SN74LS280N Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. By cascading. This design permits the LS280 to be substituted for the LS180 which results in improved performance. the word length is easily expanded. 6 Publication Order Number: SN74LS280/D .com LOW POWER SCHOTTKY • • • • • Generates Either Odd or Even Parity for Nine Data Lines Typical Data-to-Output Delay of only 33 ns Cascadable for n-Bits Can Be Used To Upgrade Systems Using MSI Parity Circuits Typical Power Dissipation = 80 mW 14 1 INPUTS VCC 14 F 13 F G H 1 G 2 H 3 NC I E 12 E D 11 D C 10 C B 9 B A 8 PLASTIC N SUFFIX CASE 646 A ∑ ∑ EVEN ODD 14 1 4 5 6 7 I ∑ ∑ GND INPUT EVEN ODD OUTPUTS INPUTS SOIC D SUFFIX CASE 751A FUNCTION TABLE NUMBER OF INPUTS A THRU 1 THAT ARE HIGH 0. 6.25 70 – 0. 4.75 0 Typ 5.0 Unit V °C mA mA SN74LS280D © Semiconductor Components Industries. 3. It features odd / even outputs to facilitate either odd or even parity.4 8. http://onsemi. 8 1.SN74LS280 9-Bit Odd/Even Parity Generators/Checkers The SN74LS280 is a Universal 9-Bit Parity Generator / Checker.

IIN = – 18 mA VCC = MIN.5 0.65 3. Data to Output ΣODD Min Typ 33 29 23 31 Max 50 45 35 50 Unit ns CL = 15 pF ns Test Conditions http://onsemi. VIN = 7. VIN = 2.7 V VCC = MAX. VCC = 5.5 20 V µA mA mA mA mA IOL = 8. AC CHARACTERISTICS (TA = 25°C.com 206 . VIN = VIH or VIL per Truth Table IOL = 4.0 V VCC = MAX.25 VO OL Output LOW Voltage 0. Data to Output ΣEVEN Propagation Delay.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 mA 0.4 Min 2. IOH = MAX.35 IIH IIL IOS ICC Input HIGH Current 0.4 – 100 27 0. VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.0 0. nor for more than 1 second.SN74LS280 FUNCTIONAL BLOCK DIAGRAM A (8) B (9) (5) ∑ EVEN C (10) D E F (11) (12) (13) (6) ∑ ODD G H (1) (2) I (4) DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.0 mA VCC = VCC MIN.7 – 0.0 V) Limits Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.8 – 1.

B1 – B4) and a Carry Input (C0). GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.com LOW POWER SCHOTTKY PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS283N SN74LS283D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 1999 – Rev.SN74LS283 4-Bit Binary Full Adder with Fast Carry The SN74LS283 is a high-speed 4-Bit Binary Full Adder with internal carry lookahead. It generates the binary Sum outputs (∑1 – ∑4) and the Carry Output (C4) from the most significant bit. It accepts two 4-bit binary words (A1 – A4. The LS283 operates with either active HIGH or active LOW operands (positive or negative logic). LLC.25 70 – 0.0 25 Max 5. 6 Publication Order Number: SN74LS283/D .0 Unit V °C mA mA 16 1 http://onsemi. 1999 207 December.4 8.

5 U.SN74LS283 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 B3 15 A3 14 Σ3 13 A4 12 B4 11 Σ4 10 C4 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.0 U.L.6 mA LOW. 0. LOW 0.L.) = 40 mA HIGH/1. 0.L. 10 U. 0. 5 U. 10 U.0 U.L. 1 Σ2 2 B2 3 A2 4 Σ1 5 A1 6 B1 7 C0 8 GND LOADING (Note a) PIN NAMES A1 – A4 B1 – B4 C0 S1 – S4 C4 Operand A Inputs Operand B Inputs Carry Input Sum Outputs Carry Output HIGH 1. 5 U.L.L. NOTES: a) 1 TTL Unit Load (U.25 U.L.L.L.5 U.L. 1.L.com 208 . LOGIC SYMBOL 5 3 14 12 6 2 15 11 A1 A2 A3 A4 B1 B2 B3 B4 7 C0 ∑1 ∑2 ∑3 ∑4 4 1 13 10 C4 9 VCC = PIN 16 GND = PIN 8 http://onsemi.5 U.

http://onsemi. but must be held LOW when no carry in is intended. Carry Input can not be left open. thus C0. C0 + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = ∑1 + 2 ∑2 + 4 ∑3 + 8 ∑4 + 16C4 Where: (+) = plus Example: C0 logic levels Active HIGH Active LOW L 0 1 A1 L 0 1 A2 H 1 0 A3 L 0 1 A4 H 1 0 B1 H 1 0 Due to the symmetry of the binary add function the LS283 can be used with either all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). B2 L 0 1 B3 L 0 1 B4 H 1 0 ∑1 H 1 0 ∑2 H 1 0 ∑3 L 0 1 ∑4 L 0 1 C4 H 1 0 (10+9=19) (carry+5+6=12) Interchanging inputs of equal weight does not affect the operation. Note that with active HIGH inputs. B1. can be arbitrarily assigned to pins 7.com 209 . 5 or 3. A1.SN74LS283 LOGIC DIAGRAM C0 7 A1 5 B1 6 A2 3 B2 2 A3 14 B3 15 A4 12 B4 11 C1 C2 C3 4 ∑1 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS ∑2 1 ∑3 13 ∑4 10 9 C4 FUNCTIONAL DESCRIPTION The LS283 adds two 4-bit binary words (A plus B) plus the incoming carry. The binary sum appears on the sum outputs (∑1 – ∑4) and outgoing carry (C4) outputs.

65 3.8 – 100 34 39 0. VIN = VIL or VIH per Truth Table VCC = MAX. http://onsemi.4 VCC = MAX VCC = MAX VCC = MAX.1 0.7 mA Note 1: Not more than one output should be shorted at a time.25 VO OL Output LOW Voltage 0.0 0.0 mA VCC = VCC MIN.0 IOL = 8.7 – 0. IOH = MAX.com 210 .4 Min 2. IIN = – 18 mA VCC = MIN. Output LOW – 20 0.5 20 40 V µA µA mA mA mA mA mA VCC = MAX. nor for more than 1 second.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = 0 4 V MAX 0.5 0. VIN = 7 0 V MAX 7. VIN = 2 7 V MAX 2.35 C0 Any A or B IIH Input HIGH Current C0 Any A or B IIL IOS ICC Input LOW Current C0 Any A or B Short Circuit Current (Note 1) Power Supply Current Total.8 – 1.4 – 0. VIN = VIH or VIL per Truth Table IOL = 4. Output HIGH Total.SN74LS283 FUNCTIONAL TRUTH TABLE C (n – 1) L L L L H H H H An L L H H L L H H Bn L H L H L H L H ∑n L H H L H L L H Cn L L L H L H H H C1 – C3 are generated internally C0 is an external input C4 is an output generated internally DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.2 – 0.0 mA 0.

3 V tPLH VIN Figure 1.SN74LS283 AC CHARACTERISTICS (TA = 25°C.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay. Any A or B Input to C4 Output Min Typ 16 15 15 15 11 11 11 12 Max 24 24 24 24 17 22 17 17 Unit ns ns CL = 15 pF Figures 1 & 2 ns ns Test Conditions AC WAVEFORMS 1. Figure 2. http://onsemi. C0 Input to Any Σ Output Propagation Delay. Any A or B Input to Σ Outputs Propagation Delay.com 211 . C0 Input to C4 Output Propagation Delay.3 V VOUT tPHL VIN VOUT 1.3 V tPHL 1.3 V tPLH 1. VCC = 5.

4 8. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register.com LOW POWER SCHOTTKY • • • • Select From Two Data Sources Fully Edge-Triggered Operation Typical Power Dissipation of 65 mW Input Clamp Diodes Limit High Speed Termination Effects 16 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. The LS298 is fabricated with the Schottky barrier process for high speed and is completely compatible with all ON Semiconductor TTL families. LLC.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the Clock input.75 0 Typ 5. 1999 – Rev.25 70 – 0. 6 Publication Order Number: SN74LS298/D . http://onsemi.0 Unit V °C mA mA 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS298N SN74LS298D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.SN74LS298 Quad 2-Input Multiplexer with Storage The SN74LS298 is a Quad 2-Port Register.0 25 Max 5. 1999 212 December. A Common Select input selects between two 4-bit input ports (data sources.

L. 0. 0.6 mA LOW.5 U.5 U.25 U.L. NOTES: a) 1 TTL Unit Load (U.25 U.5 U.L. 0. 0.L.25 U.SN74LS298 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Qa 15 Qb 14 Qc 13 Qd 12 CP 11 S 10 I0c 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L. LOGIC SYMBOL 3 2 4 1 9 5 7 6 I0a I1a I0b I1b I0c I1c I0d I1d 10 11 S CP Qa 15 Qb 14 Qc 13 Qd 12 VCC = PIN 16 GND = PIN 8 http://onsemi.com 213 .L.25 U. 10 U.L.) = 40 mA HIGH/1.L.L. 0. 5 U. 0. LOW 0.L. 1 I1b 2 I1a 3 I0a 4 I0b 5 I1c 6 I1d 7 I0d 8 GND LOADING (Note a) PIN NAMES S CP I0a – I0d I1a – I1d Qa – Qd Common Select Input Clock (Active LOW Going Edge) Input Data Inputs from Source 0 Data Inputs from Source 1 Register Outputs HIGH 0.L.5 U.

It selects four bits of data from two sources (ports)under the control of a Common Select Input (S). h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition. The 4-bit output register is fully edge-triggered.SN74LS298 LOGIC OR BLOCK DIAGRAM I1a 2 I0a 3 I1b 1 I0b 4 I1c 5 I0c 9 I1d 6 I0d 7 S 10 CP 11 R CP S Qa 15 R CP S Qb 14 R CP S Qc 13 R CP S Qd 12 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Qa Qb Qc Qd FUNCTIONAL DESCRIPTION The LS298 is a high speed Quad 2-Port Register. The Data inputs (I) and Select input (S) must be stable only one setup time prior to the HIGH to LOW transition of the clock for predictable operation. The selected data is transferred to the 4-bit output register synchronous with the HIGH to LOW transition of the Clock input (CP). TRUTH TABLE INPUTS S I I h h I0 I h X X I1 X X I h OUTPUT Q L H L H L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition. http://onsemi.com 214 .

HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. VIN = 0. IOH = MAX. AC CHARACTERISTICS (TA = 25°C. VIN = 7.4 Min 2. VIN = 2.5 20 V µA mA mA mA mA IOL = 8.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. nor for more than 1 second. IIN = – 18 mA VCC = MIN.0 0 Typ Max Unit ns ns ns ns VCC = 5. http://onsemi.65 3. VCC = 5.25 VO OL Output LOW Voltage 0.8 – 1.0 mA 0. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. CL = 15 pF AC SET-UP REQUIREMENTS (TA = 25°C.0 V Test Conditions DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. VIN = VIH or VIL per Truth Table IOL = 4. g y Clock to Output Min Typ 18 21 Max 27 32 Unit ns ns Test Conditions VCC = 5.0 V.7 V VCC = MAX.4 – 100 21 0.0 V) Limits Symbol tW ts ts th th Parameter Clock Pulse Width Data Setup Time Select Setup Time Data Hold Time Select Hold Time Min 20 15 25 5.0 V) Limits Symbol tPLH tPHL Parameter Propagation Delay.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VCC = 5.0 mA VCC = VCC MIN.0 V VCC = MAX.7 – 0.0 0.35 IIH IIL IOS ICC Input HIGH Current 0.5 0. VIN = VIL or VIH per Truth Table VCC = MAX.SN74LS298 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.com 215 .

3 V 1. Figure 2.SN74LS298 AC WAVEFORMS I0 I1* ts(L) CP 1.3 V tW(H) tPLH 1.3 V th(H) = 0 ts(H) 1.com 216 .3 V tPHL Q 1.3 V *The shaded areas indicate when the input is permitted to *change for predictable output performance.3 V th(L) tW(L) ts(H) 1. Figure 1.3 V th(L) = 0 1.3 V Q Q = I0 Q = I1 1.3 V th(H) ts(L) CP 1. http://onsemi.3 V S* 1.

75 0 Typ 5. Q7 Output Current – Low Q 0 . shift left.0 – 2. 1999 217 December. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins.25 70 – 0.0 25 Max 5. 1999 – Rev.4 8. Q7 Output Current – High I/O0 – 1/O7 Output Current – Low I/O0 – 1/O7 Min 4. Shift Right. Load and Store • Separate Shift Right Serial Input and Shift Left Serial Input for Easy • • • Cascading 3-State Outputs for Bus Oriented Applications Input Clamp Diodes Limit High-Speed Termination Effects ESD > 3500 Volts 20 LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Q 0 . Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. Four modes of operation are possible: hold (store). shift right and load data. A separate active LOW Master Reset is used to reset the register. http://onsemi.6 24 Unit V °C mA mA mA mA 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS299N SN74LS299DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. LLC. 6 Publication Order Number: SN74LS299/D .SN74LS299 8-Bit Shift/Storage Register with 3-State Outputs The SN74LS299 is an 8-Bit Universal Shift / Storage Register with 3-state outputs.com • Common I/O for Reduced Pin Count • Four Operation Modes: Shift Left.

0.25 U.25 U. 0. 0. 65 U.5 U. LOW 0.5 U. S1 19 S0 1 LOGIC DIAGRAM 18 DS7 DS0 11 12 CLOCK Q0 MR OE1 OE2 8 9 2 3 D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q 17 Q7 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 7 13 6 14 5 15 4 16 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 http://onsemi.L.5 U.6 mA LOW.L.25 U.25 U. 0.L.L.L. 10 U.L. NOTES: a) 1 TTL Unit Load (U. 0.L.L.L.com 218 . 0. S1 Clock Pulse (Active Positive–Going Edge) Input Serial Data Input for Right Shift Serial Data Input for Left Shift Parallel Data Input or Parallel Output (3–State) 3–State Output Enable (Active LOW) Inputs Serial Outputs Asynchronous Master Reset (Active LOW) Input Mode Select Inputs HIGH 0. 1 S0 2 3 4 OE1 OE2 I/O6 8 5 6 7 I/O4 I/O2 I/O0 Q0 9 10 MR GND LOADING (Note a) PIN NAMES CP DS0 DS7 I/On OE1.L.L. Q7 MR S0.25 U.L.L.L.L.) = 40 mA HIGH/1.5 U. 0.L.L. 5 U. OE2 Q0.L.5 U.5 U.L.SN74LS299 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 20 S1 19 Ds7 18 Q7 17 I/O7 I/O5 I/O3 I/O1 16 15 14 13 CP 12 DS0 11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 U. 0.5 U. 0.25 U. 0. 15 U. 0.

Parallel Load. D³Q7.com 219 . Q7³Q6.SN74LS299 FUNCTION TABLE INPUTS MR L L L L L H H H H H H H H S1 X X H L X L L H H H L L L S0 X X H X L H H L L H L L L OE1 H X X L L X L X L X H X L OE2 X H X L L X L X L X X H L X X X CP X X X X X DS0 X X X X X D D X X X X X X DS7 X X X X X X X D D X X X X Asynchronous Reset. Q0 = Q7 = LOW I/O Voltage LOW RESPONSE ³ ³ ³ ³ Shift Left. D³Q7 & I/O7. D Q0. etc. Q0 = Q7 = LOW Reset I/O Voltage Undetermined Asynchronous Reset. etc. Q7³Q6 & I/O6. Q0 Q1. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial http://onsemi. etc. Q0 O1 & I/O1. Shift Left. I/On³Qn Hold: I/O Voltage undetermined Hold: I/On = Qn Shift Right. etc. D Q0 & I/O0. Shift Right.

VIN = VIL or VIH per Truth Table VO OL VO OL IOZH IOZL VCC = MAX. IOH = MAX VCC = MIN.SN74LS299 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage I/O0 – I/O7 Output HIGH Voltage Q 0 .1 3.4 0. VOUT = 0.4 0. VIN = VIL or VIH per Truth Table VCC = VCC MIN. VIN = 7 0 V MAX 7.5 Typ Max Unit V V V V V V V V V µA µA µA µA mA mA mA mA VCC = MAX. IOH = MAX IOL = 12 mA IOL = 24 mA IOL = 4.0 0.8 – 1.4 VCC = MAX VCC = MAX VCC = MAX VCC = MAX.4 V ICC Note 1: Not more than one output should be shorted at a time.7 V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. Q7 I/O0 – I/O7 – 20 – 30 – 0. S1.com 220 .4 0.25 0.4 2. nor for more than 1 second. VIN = 2.5 V VCC = MAX.8 –100 –130 53 mA mA mA mA 2.1 0.1 – 0.35 0.7 – 0.0 VCC = MAX. IIN = – 18 mA VCC = MIN.2 0. Q7 Output LOW Voltage g I/O0 – I/O7 Output LOW Voltage g I/O0 – I/O7 Output Off Current HIGH I/O0 – I/O7 Output Off Current LOW I/O0 – I/O7 Others S0.0 mA IOL = 8.4 Min 2.5 40 – 400 20 40 0. http://onsemi.65 3.0 mA VCC = VCC MIN. I/O0 – I/O7 IIH Input HIGH C I t Current t Others S0.5 0. S1 I/O0 – I/O7 Others IIL IOS Input LOW Current S0. S1 Short Circuit Current (Note 1) Power Supply Current Q 0 .7 V VCC = MAX. VOUT = 2. VIN = 5. VIN = 0 4 V MAX 0.

Clear to I/O0 – I/O7 Output Enable Time Output Disable Time Min 25 Typ 35 26 22 27 26 17 26 13 19 10 10 39 33 40 39 25 40 21 30 15 15 Max Unit MHz ns ns ns ns ns ns CL = 5. VCC = 5. Clock to I/O0 – I/O7 Propagation Delay.SN74LS299 AC CHARACTERISTICS (TA = 25°C.0 V) Limits Symbol fMAX tPHL tPLH tPHL tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay.0 Test Conditions http://onsemi.0 V) Limits Symbol tW tW tW ts ts th th trec Parameter Clock Pulse Width HIGH Clock Pulse Width LOW Clear Pulse Width LOW Data Setup Time Select Setup Time Data Hold Time Select Hold Time Recovery Time Min 25 13 20 20 35 0 10 20 Typ Max Unit ns ns ns ns ns ns ns ns VCC = 5 0 V 5.0 pF CL = 45 pF. VCC = 5. Clear to Q0 or Q7 Propagation Delay. RL = 667 Ω CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.com 221 . Clock to Q0 or Q7 Propagation Delay.

5 V VE VOUT tPZL 1. http://onsemi.5 V VOL VE 1.5 V VOUT tPHZ 1.5 V 0.SN74LS299 3-STATE WAVEFORMS VIN 1.5 V VE tPZH 1.3 V tPLH 1. AC LOAD CIRCUIT SWITCH POSITIONS VCC RL SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed SW1 TO OUTPUT UNDER TEST 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance.3 V VOUT 1.5 V ≥ VOH ≈ 1. Figure 2. Figure 4.3 V tPHL 1.com 222 .5 V Figure 3.3 V Figure 1.3 V tPHL 1.3 V tPLH 1. Figure 5.3 V VOUT 1.5 V 0.5 V tPLZ ≈ 1.3 V VIN 1. VE 1.5 V 1.

0 25 Max 5. If the outputs of the 3-state devices are tied together. 1999 – Rev. the outputs are forced to a high impedance “off” state. 6 Publication Order Number: SN74LS365A/D . 1999 223 December. They are organized as single 6-bit or 2-bit / 4-bit. with inverting or non-inverting data (D) paths. all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings.com LOW POWER SCHOTTKY PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS365AN SN74LS365AD SN74LS367AN SN74LS367AD SN74LS368AN SN74LS368AD Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries.SN74LS365A SN74LS367A SN74LS368A 3-State Hex Buffers These devices are high speed hex buffers with 3-state outputs.75 0 Typ 5. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power Schottky loads when the Enable (E) is LOW.6 24 Unit V °C mA mA 16 1 http://onsemi. When the Output Enable (E) is HIGH. LLC. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.25 70 – 2.

SN74LS365A SN74LS367A SN74LS368A SN74LS365A HEX 3-STATE BUFFER WITH COMMON 2-INPUT NOR ENABLE VCC 16 E2 15 14 13 12 11 10 9 1 E1 2 3 4 5 6 7 8 GND TRUTH TABLE INPUTS E1 L L H X E2 L L X H D L H X X L H (Z) (Z) OUTPUT SN74LS367A HEX 3-STATE BUFFER SEPARATE 2-BIT AND 4-BIT SECTIONS VCC 16 E 15 14 13 12 11 10 9 SN74LS368A HEX 3-STATE INVERTER BUFFER SEPARATE 2-BIT AND 4-BIT SECTIONS VCC 16 E 15 14 13 12 11 10 9 1 E 2 3 4 5 6 7 8 GND 1 E 2 3 4 5 6 7 8 GND TRUTH TABLE INPUTS E L L H D L H X L H (Z) OUTPUT TRUTH TABLE INPUTS E L L H D L H X H L (Z) OUTPUT http://onsemi.com 224 .

AC CHARACTERISTICS (TA = 25°C.0 V) Limits LS365A / LS367A Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Output Enable Time Output Disable Time Min Typ 10 9. VOUT = 0.com 225 . VIN = 2.1 0. nor for more than 1 second. VIN = 0.4 V Both E Inputs at 0. 367A LS368A – 40 – 225 24 21 0. VIN = 0. IIN = – 18 mA VCC = MIN.8 – 1.4 – 0.0 19 24 Max 16 22 35 40 30 35 LS366A / LS368A Min Typ 7.1 Input LOW Current E Inputs IIL D Inputs – 0.4 – 20 – 0. IOH = MAX.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.4 IOS ICC Short Circuit Current (Note 1) Power Supply Current LS365A.7 V VCC = MAX. RL = 667 Ω Test Conditions CL = 5.4 V VCC = MAX.65 3.0 V VCC = MAX. VIN = 7. VCC = 5. VIN = 0.4 Min 2.5 20 – 20 20 V µA µA µA mA mA µA mA mA IOL = 24 mA 0.0 0.25 VO OL IOZH IOZL IIH Output LOW Voltage 0.4 V VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time.SN74LS365A SN74LS367A SN74LS368A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN.0 pF http://onsemi. VOUT = 2.7 V VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX.4 V VCC = MAX.5 V Either E Input at 2.0 V VCC = MAX.0 12 18 28 Max 15 18 35 45 32 35 Unit ns ns ns CL = 45 pF.

The SN74LS374 is a high-speed.75 0 Typ 5. When OE is HIGH the bus output is in the high impedance state. 6 Publication Order Number: SN74LS373/D . When LE is LOW.0 25 Max 5.6 24 Unit V °C mA mA 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS373N SN74LS373DW SN74LS374N SN74LS374DW Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.25 70 – 2. Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. Data appears on the bus when the Output Enable (OE) is LOW. 1999 – Rev.SN74LS373 SN74LS374 Octal Transparent Latch with 3-State Outputs. http://onsemi. 1999 226 December. LLC.com LOW POWER SCHOTTKY • • • • • • • Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects 20 1 PLASTIC N SUFFIX CASE 738 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. the data that meets the setup times is latched.

25 U. 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND LOADING (Note a) PIN NAMES D0 – D7 LE CP OE O0 – O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH Going Edge) Input Output Enable (Active LOW) Input Outputs HIGH 0.L. http://onsemi.L.5 U.com 227 . LOW 0.5 U.25 U.5 U. 0. 65 U. NOTES: a) 1 TTL Unit Load (U.25 U.L.6 mA LOW. 15 U. 0. 0. TRUTH TABLE LS373 Dn H L X X LE H H L X OE L L L H On H L Q0 Z* Dn H L X X LS374 LE OE L L H On H L Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).L.L. 0.SN74LS373 SN74LS374 CONNECTION DIAGRAM DIP (TOP VIEW) SN74LS373 VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 VCC 20 O7 19 D7 18 D6 17 SN74LS374 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.25 U.L.) = 40 mA HIGH/1.5 U.L.L.L. 0. 0.L.L.

VIN = VIL or VIH per Truth Table VCC = MAX.4 – 0.0 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.5 20 – 20 20 0. VIN = 2. IIN = – 18 mA VCC = MIN.4 V VCC = MAX.25 VO OL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 0.1 – 0.SN74LS373 SN74LS374 LOGIC DIAGRAMS SN74LS373 3 4 7 8 13 14 17 18 D0 D LATCH ENABLE LE 11 OE Q G D1 D Q G D2 D Q G D3 D Q G D4 D Q G D5 D Q G D6 D Q G D7 D Q G VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 1 O0 2 5 O1 6 O2 9 O3 12 O4 15 O5 16 O6 19 O7 SN74LS374 3 11 4 7 8 13 14 17 18 D0 CP D Q Q CP D Q Q D1 CP D Q Q D2 CP D Q Q D3 CP D Q Q D4 CP D Q Q D5 CP D Q Q D6 CP D Q Q D7 CP OE 1 2 O0 5 O1 6 O2 9 O3 12 O4 15 O5 16 O6 19 O7 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. http://onsemi.7 V VCC = MAX. nor for more than 1 second. VIN = 7. VOUT = 2. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN.com 228 .4 – 130 40 V µA µA µA mA mA mA mA IOL = 24 mA 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time.1 0. VIN = 0. VOUT = 0. IOH = MAX.4 Min 2.0 V VCC = MAX.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 30 0.65 3.8 – 1.7 V VCC = MAX.

0 V) Limits LS373 Symbol tW ts th Clock Pulse Width Setup Time Hold Time Parameter Min 15 5.0 pF CL = 45 pF pF. Data to Output Clock or Enable to Output Output Enable Time Output Disable Time 12 12 20 18 15 25 12 15 18 18 30 30 28 36 20 25 15 19 20 21 12 15 28 28 28 28 20 25 Min Typ Max Min 35 LS374 Typ 50 Max Unit MHz ns ns ns ns CL = 5.0 20 Max Min 15 20 0 LS374 Max Unit ns ns ns DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.SN74LS373 SN74LS374 AC CHARACTERISTICS (TA = 25°C.0 V) Limits LS373 Symbol fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay. VCC = 5.com 229 . VCC = 5. http://onsemi. RL = 667 Ω Test Conditions AC SETUP REQUIREMENTS (TA = 25°C. HOLD TIME (th) — is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition.

SN74LS373 SN74LS374 SN74LS373 AC WAVEFORMS tW LE 1. Figure 4.3 V 0.5 V Figure 2. Figure 3.3 V VOL OE tPZH VOUT 1.3 V tPLZ 1.3 V 0. http://onsemi.3 V 1.3 V ts Dn tPLH OUTPUT tPHL th tW Figure 1.3 V tPHZ 1.com 230 . AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SYMBOL SW1 tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed 5.5 V 1.0 kΩ CL* SW2 * Includes Jig and Probe Capacitance.3 V 1. OE tPZL VOUT 1.3 V VOH 1.

http://onsemi. Figure 5. OE tPZH VOUT 1.3 V th OE tPZL VOUT 1.3 V tPHZ 1.0 kΩ CL* SW2 * Includes Jig and Probe Capacitance.3 V tWL 1.3 V 1.3 V 1.3 V 0.3 V ts Dn tPLH OUTPUT 1.3 V 1.3 V tPHL 1. AC LOAD CIRCUIT VCC RL SWITCH POSITIONS SYMBOL tPZH SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed SW1 tPZL tPLZ TO OUTPUT UNDER TEST tPHZ 5.3 V VOL Figure 6.com 231 .3 V 1.SN74LS373 SN74LS374 SN74LS374 AC WAVEFORMS tWH CP 1.3 V ≥ VOH ≈ 1. Figure 8.3 V tPLZ ≈ 1.5 V Figure 7.3 V 0.5 V 1.

0 Unit V °C mA mA 20 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS377N SN74LS377DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 6 Publication Order Number: SN74LS377/D . LLC.0 25 Max 5.com • • • • • 8-Bit High Speed Parallel Registers Positive Edge-Triggered D-Type Flip Flops Fully Buffered Common Clock and Enable Inputs True and Complement Outputs Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable.4 8. 1999 – Rev. http://onsemi. 1999 232 December.25 70 – 0.SN74LS377 Octal D Flip-Flop with Enable The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology.75 0 Typ 5.

L. 0.L.L.5 U. LOGIC DIAGRAM 3 4 7 8 13 14 17 18 D0 E ENABLE 1 D1 D2 D3 D4 D5 D6 D7 CP CLOCK 11 CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 http://onsemi. 0.L. 1 E 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND LOADING (Note a) PIN NAMES E D0 – D3 CP Q0 – Q3 Q0 – Q3 Enable (Active LOW) Input Data Inputs Clock (Active HIGH Going Edge) Input True Outputs Complemented Outputs HIGH 0. 5 U.5 U.com 233 .L.5 U.25 U.L. 10 U.L.SN74LS377 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.L.6 mA LOW.) = 40 mA HIGH/1.L. 10 U.L.L. NOTES: a) 1 TTL Unit Load (U. LOW 0. 5 U.25 U.25 U. 0. 0.

4 – 100 28 V µA mA mA mA mA 0.0 mA VCC = VCC MIN. VIN = VIL or VIH per Truth Table IIH IIL IOS ICC VCC = MAX. NOTE 1 NOTE: With all inputs open and GND applied to all data and enable inputs. IOH = MAX.0 V Test Conditions DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.8 – 1.25 VO OL Output LOW Voltage 0.35 Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 0.SN74LS377 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. nor for more than 1 second.7 V VCC = MAX. ICC is measured after a momentary GND.0 CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C. VCC = 5. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.5 0.5 V is applied to clock. VIN = VIH or VIL per Truth Table IOL = 4. then 4. http://onsemi.0 mA IOL = 8.0 Typ Max Unit ns ns ns ns ns VCC = 5. Note 1: Not more than one output should be shorted at a time. AC CHARACTERISTICS (TA = 25°C. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay.0 V) Limits Symbol tW ts ts th Parameter Any Pulse Width Data Setup Time Enable Setup Time Any Hold Time Inactive — State Active — State Min 20 20 10 25 5. IIN = – 18 mA VCC = MIN. VCC = 5.4 V VCC = MAX VCC = MAX.65 3. VIN = 2.com 234 . VIN = 7.4 Min 2.7 – 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 V VCC = MAX.1 – 0. VIN = 0.5 20 0.0 0. Clock to Output Min 30 Typ 40 17 18 27 27 Max Unit MHz ns Test Conditions VCC = 5 0 V 5.

3 V tPLH Q 1.SN74LS377 TRUTH TABLE E H L L L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial CP Dn X H L Qn No Change H L Qn No Change L H AC WAVEFORM 1/fmax CP 1. http://onsemi.com 235 .3 V *The shaded areas indicate when the input is permitted to change for predictable output performance.3 V tPHL 1.3 V th(H) ts(L) tW 1.3 V ts(H) D OR E * 1.3 V th(L) 1.

Each half of the LS393 operates as a Modulo-16 binary divider.25 70 – 0.SN74LS393 Dual 4-Stage Binary Counter The SN74LS393 contains a pair of high-speed 4-stage ripple counters. Each half of each circuit type has a Master Reset input which responds to a HIGH signal by forcing all four outputs to the LOW state.0 25 Max 5. 0 Publication Order Number: SN74LS393/D . • Dual Versions • Individual Asynchronous Clear for Each Counter • Typical Max Count Frequency of 50 MHz • Input Clamp Diodes Minimize High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. LLC. with the last three stages triggered in a ripple fashion.com LOW POWER SCHOTTKY PLASTIC N SUFFIX CASE 646 14 1 SOIC D SUFFIX CASE 751A ORDERING INFORMATION Device SN74LS393N SN74LS393D Package 14 Pin DIP 14 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 1999 – Rev.4 8. the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs.75 0 Typ 5.0 Unit V °C mA mA 14 1 http://onsemi. 1999 236 December. In the LS393.

L.L.L.L.5 U. 1.6 mA LOW. 0. LOW 1.5 U.5 U.L.L.0 U. 1. 0.L.L. NOTES: a) 1 TTL Unit Load (U. http://onsemi. 1 CP 2 MR 3 Q0 4 Q1 5 Q2 6 Q3 7 GND LOADING (Note a) PIN NAMES CP CP0 CP1 MR Q0 – Q3 Clock (Active LOW Going Edge) Input to +16 (LS393) Clock (Active LOW Going Edge) Input to ÷2 (LS390) Clock (Active LOW Going Edge) Input to ÷ 5 (LS390) Master Reset (Active HIGH) Input Flip–Flop Outputs HIGH 0. 10 U. 5 U.L. 0. 0.com 237 .25 U.L.) = 40 mA HIGH/1.5 U.SN74LS393 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 CP 13 MR 12 Q0 11 Q1 10 Q2 9 Q3 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.0 U.L.5 U.

therefore. should not be used as clocks for other counters. A HIGH signal on MR forces all outputs to the LOW state and prevents counting. registers or flip-flops. SN74LS393 LOGIC DIAGRAM (one half shown) CP K CP CD MR J Q CD K CP J Q CD K CP J Q CD K CP J Q Q0 Q1 Q2 Q3 TRUTH TABLE OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q3 L L L L L L L L H H H H H H H H Q2 L L L L H H H H L L L L H H H H Q1 L L H H L L H H L L H H L L H H Q0 L H L H L H L H L H L H L H L H H = HIGH Voltage Level L = LOW Voltage Level http://onsemi.SN74LS393 FUNCTIONAL DESCRIPTION Each half of the SN74LS393 operates in the Modulo 16 binary sequence. Each of the other flip-flops is triggered by a HIGH-to-LOW transition of the Q output of the preceding flip-flop.com 238 . as indicated in the ÷ 16 Truth Table. The first flip-flop is triggered by HIGH-to-LOW transitions of the CP input signal. This means that logic signals derived from combinations of these outputs will be subject to decoding spikes and. Thus state changes of the Q outputs do not occur simultaneously.

0 mA VCC = VCC MIN. AC CHARACTERISTICS (TA = 25°C.4 – 100 26 0.25 VO OL Output LOW Voltage 0.0 mA 0.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = VIH or VIL per Truth Table IOL = 4.com 239 .4 – 1.5 0.65 3. VIN = 2.4 Min 2.5 20 V µA mA mA mA mA mA mA VCC = MAX VCC = MAX VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX. IIN = – 18 mA VCC = MIN.8 – 1. CP0 CP1 IOS ICC Short Circuit Current (Note 1) Power Supply Current – 20 – 0.35 IIH Input HIGH Current 0.0 V) Limits Symbol tW tW trec Parameter Clock Pulse Width MR Pulse Width Recovery Time Min 20 20 25 Typ Max Unit ns ns ns VCC = 5.6 – 2.SN74LS393 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2. nor for more than 1 second. IOH = MAX.1 MR IIL Input LOW Current CP. CP to Q0 CP to Q3 MR to Any Output Min 25 20 12 13 40 40 24 20 20 60 60 39 Typ 35 Max Unit MHz MHz ns ns ns CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C.0 V Test Conditions http://onsemi.0 V) Limits Symbol fMAX fMAX tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency CP0 to Q0 Maximum Clock Frequency CP1 to Q1 Propagation Delay.0 V Note 1: Not more than one output should be shorted at a time.0 0. VCC = 5.4 V IOL = 8. VIN = 7. VCC = 5.7 – 0.7 V VCC = MAX. VIN = 0.

com 240 .3 V Q Figure 1.3 V 1.3 V tPHL Q 1. *The number of Clock Pulses required between tPHL and tPLH measurements can be determined from the appropriate Truth Table. MR & MS 1.SN74LS393 AC WAVEFORMS *CP 1.3 V tW CP 1.3 V trec Figure 2.3 V 1.3 V tPLH 1. http://onsemi.3 V tW tPHL 1.

0 25 Max 5. but with pinouts on the opposite side of the package. http://onsemi. 1999 – Rev. 1999 241 December. This device type is designed to be used as a memory address driver.25 70 – 15 24 Unit V °C mA mA SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS541N SN74LS541DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 0 Publication Order Number: SN74LS541/D .com • • • • • Hysteresis at Inputs to Improve Noise Margin PNP Inputs Reduce Loading 3-State Outputs Drive Bus Lines Inputs and Outputs Opposite Side of Package. allowing ease of layout and greater PC board density.75 0 Typ 5.SN74LS541 Octal Buffer/Line Driver with 3-State Outputs The SN74LS541 is an octal buffer and line driver with the same functions as the LS241. LLC. This device is especially useful as output ports for the microprocessors. Allowing Easier Interface to Microprocessors Input Clamp Diodes Limit High-Speed Termination Effects LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) VCC 20 19 18 17 16 15 14 13 12 11 20 LOW POWER SCHOTTKY 1 PLASTIC N SUFFIX CASE 738 1 2 3 4 5 6 7 8 9 10 GND 20 1 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. clock driver and bus-oriented transmitter / receiver.

7 V VCC = MAX.4 Min 2.2 – 225 32 52 55 0.5 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.5 V V µA µA µA mA mA mA mA mA mA VCC = MAX IOL = 24 mA VCC = MIN VCC = MAX.4 V VCC = MAX.4 V VCC = MAX 0. IOH = – 3.SN74LS541 BLOCK DIAGRAM E1 E2 (2) (18) (1) (19) INPUTS E1 Y1 L H X L E2 L X H L D H X X L OUTPUTS LS540 L Z Z H LS541 H Z Z L D1 D2 D3 D4 D5 D6 D7 D8 (3) (4) (5) (6) (7) (8) (9) (17) (16) (15) (14) (13) Y2 Y3 Y4 Y5 Y6 L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial Z = High Impedance (12) Y7 (11) Y8 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VO OH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 2. VIL = 0.0 mA VCC = MIN.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total.0 0. VIN = 2. nor for more than 1 second. Output LOW Total Output 3-State – 40 – 0.4 V V – 0.0 V VCC = MAX. IIN = – 18 mA VCC = MIN.65 3.2 0.4 Output HIGH Voltage 2. Output HIGH ICC Total. VIN = 0.5 V IOL = 12 mA VCC = VCC MIN.4 20 – 20 20 0.7 V VCC = MAX. VIN = 7. IOH = MAX. VIN = VIL or VIH per Truth Table Note 1: Not more than one output should be shorted at a time.0 0.8 – 1.25 VO OL VT+–VT– IOZH IOZL IIH IIL IOS Output LOW Voltage 0.com 242 . VOUT = 0. http://onsemi. VOUT = 2.35 Hysteresis Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.

5 V 1. http://onsemi.SN74LS541 AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay.3 V tPLH VOUT 1.3 V 1.5 V tPLZ ≈ 1.com 243 . VE VE VOUT 1.0 CL = 45 pF RL = 667 Ω Unit Test Conditions AC WAVEFORMS VCC VIN 1. TO OUTPUT UNDER TEST VIN 1.5 V 1.5 V tPZL 1. Figure 5. g y Data to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time to HIGH Level Output Disable Time to LOW Level Min Typ 12 12 15 20 10 15 Max 15 ns 18 32 38 18 29 ns ns ns CL = 5 0 pF 5.5 V SWITCH POSITIONS SYMBOL tPZH tPZL tPLZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed Figure 3.5 V VE VOUT tPZH 1.5 V VOL 0.3 V CL* 5 kΩ SW2 Figure 2.3 V tPLH VOUT 1.3 V SW1 RL Figure 1.5 V tPHZ Figure 4. VE 1.3 V tPHL 1.5 V tPHZ ≥VOH ≈ 1.3 V 1.3 V tPHL 1.0 ns VCC = 5 0 V 5.5 V 0.

1999 244 December.0 – 15 IOL Output Current – Low 24 Unit V °C mA mA mA 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS640N SN74LS640DW SN74LS641N Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel GUARANTEED OPERATING RANGES (SN74LS641. DEVICE LS640 LS641 LS642 LS645 OUTPUT 3-State Open-Collector Open-Collector 3-State LOGIC Inverting True Inverting True http://onsemi. 6 Publication Order Number: SN74LS640/D . 1999 – Rev.75 0 Typ 5.com LOW POWER SCHOTTKY FUNCTION TABLE CONTROL INPUTS G L L H DIR L H X LS640 LS642 B data to A bus A data to B bus Isolation OPERATION LS641 LS645 B data to A bus A data to B bus Isolation 20 1 PLASTIC N SUFFIX CASE 738 H = HIGH Level. LLC.25 70 5.75 0 Typ 5. L = LOW Level.0 25 Max 5. Enable input (G) can disable the device so that the buses are effectively isolated. SN74LS645) Symbol VCC TA IOH Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Min 4. Control function implementation minimizes external timing requirements.SN74LS640 SN74LS641 SN74LS642 SN74LS645 Octal Bus Transceivers These octal bus transceivers are designed for asynchronous two-way communication between data buses. X = Irrelevant 20 GUARANTEED OPERATING RANGES (SN74LS640.5 24 Unit V °C V mA SN74LS641DW SN74LS642N SN74LS642DW SN74LS645N SN74LS645DW © Semiconductor Components Industries. These circuits allow data transmission from the A bus to B or from the B bus to A bus depending upon the logic level of the direction control (DIR) input.25 70 – 3. SN74LS642) Symbol VCC TA VOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Voltage – High Output Current – Low Min 4.0 25 Max 5.

SN74LS640 SN74LS641 SN74LS642 SN74LS645 CONNECTION DIAGRAMS DIP (TOP VIEW) ENABLE B1 VCC G 20 19 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11 VCC 20 ENABLE B1 G 19 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11 1 DIR 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 GND 1 DIR 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 GND SN74LS640 SN74LS642 SN74LS641 SN74LS645 http://onsemi.com 245 .

VIN = 7.4 – 0. VIN = 5. DIR to A Output Disable Time G. Output LOW Total at HIGH Z – 40 DIR or G A or B 0. DIR or G Input HIGH Current Input LOW Current Output Short Circuit Current (Note 1) Power Supply Current Total Output HIGH ICC Total. RL = 667 Ω http://onsemi.7 V VCC = MAX.5 V VCC = MAX.0 11 8. DIR to A Output Enable Time G.0 0. VIN = VIL or VIH per Truth Table VCC = MAX.0 V VCC = MAX.0 11 31 26 31 26 15 15 15 15 Max 15 15 15 15 40 40 40 40 25 25 25 25 Unit ns ns ns ns ns CL = 5 0 pF 5. DIR to B Output Disable Time G.1 – 0.0 0.0 V) Limits LS640 Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPZL tPZH tPLZ tPHZ tPLZ tPHZ Parameter Propagation Delay A to B Propagation Delay B to A Output Enable Time G. VCC = 5.35 Output Off Current HIGH Output Off Current LOW A or B.4 Min 2.0 8. VIN = 0.0 ns Test Conditions CL = 45 pF.com 246 .7 V VCC = MAX. IIN = – 18 mA VCC = MIN.4 2. IOH = 3.5 20 – 400 20 0.0 8.4 V VCC = MAX Note 1: Not more than one output should be shorted at a time.0 mA VCC = MIN. VOUT = 2.25 VO OL IOZH IOZL IIH IIL IOS Output LOW Voltage 0.SN74LS640 SN74LS641 SN74LS642 SN74LS645 SN74LS640 • SN74LS645 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VO OH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.0 6.6 – 1.5 Typ Max Unit V V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.1 0.65 3. IOH = MAX IOL = 12 mA IOL = 24 mA VCC = VCC MIN.4 – 225 70 90 95 mA VCC = MAX V µA µA µA mA mA mA mA 0. DIR to B Min Typ 6. AC CHARACTERISTICS (TA = 25°C.0 31 23 31 23 15 15 15 15 Max 10 15 10 15 40 40 40 40 25 25 25 25 Min LS645 Typ 8. nor for more than 1 second. VIN = 2.4 V VCC = MAX. VOUT = 0.

65 Min 2. B to A Propagation Delay. DIR to A Propagation Delay.4 70 90 95 mA A VCC = MAX 0.7 V VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX. G. Output LOW Total at HIGH Z – 0. VOH = MAX IOL = 12 mA VCC = VCC MIN.5 100 0.0 V VCC = MAX.0 V) Limits LS641 Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay.4 V AC CHARACTERISTICS (TA = 25°C. VIN = 7.35 IIH IIL Input HIGH Current –0.0 0.4 Typ Max Unit V V V µA V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.5 20 V µA mA mA IOL = 24 mA – 0. RL = 667 Ω Test Conditions http://onsemi.1 Input LOW Current Power Supply Current Total.25 Output LOW Voltage 0. A to B Propagation Delay. VCC = 5.SN74LS640 SN74LS641 SN74LS642 SN74LS645 SN74LS641 • SN74LS642 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VO OL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0. G. DIR to B Min Typ 17 16 17 16 23 34 25 37 Max 25 25 25 25 40 50 40 50 Min LS642 Typ 19 14 19 14 26 43 28 39 Max 25 25 25 25 40 60 40 60 Unit ns ns ns ns CL = 45 pF. VIN = 0.com 247 . IIN = – 18 mA VCC = MIN. VIN = 2.6 – 1. Output HIGH ICC Total.

6 24 Unit V °C mA mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS670N SN74LS670D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. Any number of these devices can be operated in parallel to generate an n-bit length. low-power 4 x 4 Register File organized as four words by four bits. both address and enable.75 0 Typ 5. 1999 – Rev. allow simultaneous read and write operation.SN74LS670 4 x 4 Register File with 3-State Outputs The TTL / MSI SN74LS670 is a high-speed. LLC.0 25 Max 5. http://onsemi. The 3-state outputs make it possible to connect up to 128 outputs to increase the word capacity up to 512 words.25 70 – 2. Separate read and write inputs. 6 Publication Order Number: SN74LS670/D .com • • • • • Simultaneous Read / Write Operation Expandable to 512 Words by n-Bits Typical Access Time to 20 ns 3-State Outputs for Expansion Typical Power Dissipation of 125 mW LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4. 1999 248 December.

0. 0.5 U. RB ER Q1 – Q4 Data Inputs Write Address Inputs Write Enable (Active LOW) Input Read Address Inputs Read Enable (Active LOW) Input Outputs HIGH 0.L.com 249 .L. 0.L.L. LOW 0.) = 40 mA HIGH/1. 0.L.25 U.L.5 U.L. 65 U.5 U. 1 D2 2 D3 3 D4 4 RB 5 RA 6 Q4 7 Q3 8 GND LOADING (Note a) PIN NAMES D1 – D4 WA. LOGIC SYMBOL 12 14 13 5 4 WA EW WB RA RB ER 11 15 1 2 3 D1 D2 D3 D4 Q1 Q2 Q3 Q4 10 9 7 6 VCC = PIN 16 GND = PIN 8 http://onsemi. WB EW RA. 1.6 mA LOW. 1.L.0 U.L. 0.L.L. 0.5 U.L.L.25 U.SN74LS670 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 D1 15 WA 14 WB 13 EW 12 ER 11 Q1 10 Q2 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.25 U. NOTES: a) 1 TTL Unit Load (U. 15 U.5 U.75 U.

SN74LS670 LOGIC DIAGRAM D4 12 3 D3 2 D2 1 D1 15 EW 13 WB 14 WA WORD 0 G Q D G Q D G Q D G Q D G Q D G Q D G Q D G Q D WORD 1 WORD 2 G Q D G Q D G Q D G Q D WORD 3 G Q 4 D G Q D G Q D G Q D RB 11 ER 5 RA 6 7 9 10 Q4 Q3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Q2 Q1 http://onsemi.com 250 .

4 Min 2. R. IOH = MAX.0 0.4 – 0.2 – 130 50 V µA µA µA IOL = 24 mA 0.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current D.5 20 –20 20 40 60 0. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN. IIN = – 18 mA VCC = MIN.7 V IIH mA VCC = MAX. VO = 0. VIN = VIL or VIH per Truth Table VCC = MAX.7 V VCC = MAX.1 0.8 – 1.2 0. R. VIN = 2. W EW ER Short Circuit Current (Note 1) Power Supply Current – 30 0.4 V VCC = MAX.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN.0 V IIL mA VCC = MAX. VO = 2. nor for more than 1 second.com 251 . W EW ER Input LOW Current D. VIN = 7.25 VO OL IOZH IOZL Output LOW Voltage 0. VIN = 0.65 3. R.4 V IOS ICC mA mA VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time. W EW ER D.8 –1.3 – 0.4 – 0. http://onsemi.1 0.SN74LS670 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.

3 V Q Q Figure 1.3 V 1.SN74LS670 AC CHARACTERISTICS (TA = 25°C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter Propagation Delay. EW 1.0 pF VCC = 5.3 V 1.3 V tPHL 1. WB 1. RA or RB to Output Propagation Delay.3 V 1.com 252 . (D) Setup Time. (W) Recovery Time Min 25 10 15 15 5.3 V ts th 1.3 V D tW EW 1. WA.3 V Figure 3.3 V RA. Figure 2.3 V tPHL 1.0 V. CL = 45 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts ts th th trec Parameter Pulse Width Setup Time. RB 1. http://onsemi.3 V tPLH 1.3 V tPLH 1.3 V th 1. EW to Output Propagation Delay. (D) Hold Time. (W) Hold Time.0 Test Conditions AC WAVEFORMS D.3 V ts 1. Data to Output Output Enable Time Output Disable Time Min Typ 23 25 26 28 25 23 15 22 16 30 Max 40 45 45 50 45 40 35 40 35 50 Unit ns ns ns ns ns CL = 5.0 25 Typ Max Unit ns ns ns ns ns ns VCC = 5 0 V 5.

75 0 Typ 5. LLC.0 25 Max 5. All device types provide P = Q outputs and the LS682 and LS684 have P >Q outputs also. The LS682 has a 20 kΩ pullup resistor on the Q inputs for analog or switch data. 1999 – Rev. 684.com LOW POWER SCHOTTKY TYPE LS682 LS684 LS688 P=Q yes yes yes P>Q yes yes no PULLUP yes no no 20 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.4 24 Unit V °C mA mA 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS682N SN74LS682DW SN74LS684N SN74LS684DW SN74LS688N SN74LS688DW Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries. 688 are 8-bit magnitude comparators.SN74LS682 SN74LS684 SN74LS688 8-Bit Magnitude Comparators The SN74LS682. 1999 253 December.25 70 – 0. The LS682. These device types are designed to perform comparisons between two eight-bit binary or BCD words. LS684 and LS688 are totem pole devices. 6 Publication Order Number: SN74LS682/D . OUTPUT ENABLE no no yes OUTPUT CONFIGURATION totem-pole totem-pole totem-pole http://onsemi.

com 254 . L = LOW Level. Q P=Q P>Q P<Q X ENABLES G. GT L L L H G2 L L L H P=Q L H H H P>Q H L H H OUTPUTS H = HIGH Level. X = Irrelevant http://onsemi.SN74LS682 SN74LS684 SN74LS688 CONNECTION DIAGRAMS (TOP VIEW) VCC P=Q 20 19 Q7 18 P7 17 Q6 16 P6 15 Q5 14 P5 13 Q4 12 P4 11 SN74LS682/684 1 P>Q 2 P0 3 Q0 4 P1 5 Q1 6 P2 7 Q2 8 P3 9 Q3 10 GND VCC P=Q 20 19 Q7 18 P7 17 Q6 16 P6 15 Q5 14 P5 13 Q4 12 P4 11 SN74LS688 1 G 2 P0 3 Q0 4 P1 5 Q1 6 P2 7 Q2 8 P3 9 Q3 10 GND FUNCTION TABLE INPUTS DATA P.

4 VCC = MAX IOL = 24 mA 0.1 – 0. VIN = 7.0 0.com 255 .4 V µA mA mA mA VCC = MAX. VIN = VIL or VIH per Truth Table VCC = MAX. VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN. VIN = 2.35 0. IIN = – 18 mA VCC = MIN.SN74LS682 SN74LS684 SN74LS688 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.1 0.0 V Note 1: Not more than one output should be shorted at a time.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN. VIN = 5.7 V VCC = MAX.65 3.5 V VCC = MAX.7 – 0.2 – 130 70 65 65 mA mA mA mA mA VCC = MAX 0.8 – 1. http://onsemi. VIN = 0 4 V MAX 0. IOH = MAX.5 20 IIH Input HIGH Current LS682-Q Inputs Others LS682-Q Inputs IIL IOS Input LOW Current Others Short Circuit Current (Note 1) LS682 ICC Power S P Supply l Current LS684 LS688 – 30 – 0.5 0. nor for more than 1 second.25 VO OL Output LOW Voltage 0.4 Min 2.

SN74LS682 SN74LS684 SN74LS688 LOGIC DIAGRAMS P7 Q7 P6 Q6 P5 Q5 P4 Q4 P3 Q3 P2 Q2 P1 Q1 P0 Q0 (17) (18) (15) (16) (13) (14) (11) (12) (8) (9) (6) (7) (4) (5) (2) (3) (19) P7 Q7 P6 Q6 P5 Q5 P4 Q4 P3 Q3 P2 Q2 P1 (1) (17) (18) (15) (16) (13) (14) (11) (12) (8) (9) (6) (7) (4) (5) (2) (3) (19) P=Q P=Q Q1 P0 Q0 P>Q G (1) SN74LS682 and LS684 SN74LS688 http://onsemi.com 256 .

com 257 .0 V CL = 45 pF RL = 667 Ω http://onsemi. Q to P = Q Propagation Delay.SN74LS682 SN74LS684 SN74LS688 AC CHARACTERISTICS (TA = 25°C) SN74LS682 Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay. P to P = Q Propagation Delay. P to P = Q Propagation Delay. G . P to P > Q Propagation Delay.0 V F CL = 45 pF RL = 667 Ω SN74LS684 Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay.0 V F CL = 45 pF RL = 667 Ω SN74LS688 Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay. P to P > Q Propagation Delay. Q to P > Q Min Typ 15 17 16 15 22 17 24 20 Max 25 25 25 25 30 30 30 30 Unit ns ns ns ns Test Conditions VCC = 5. P to P = Q Propagation Delay. G1 to P = Q Min Typ 12 17 12 17 12 13 Max 18 23 18 23 18 20 Unit ns ns ns Test Conditions VCC = 5. Q to P = Q Propagation Delay. Q to P > Q Min Typ 13 15 14 15 20 15 21 19 Max 25 25 25 25 30 30 30 30 Unit ns ns ns ns Test Conditions VCC = 5. Q to P = Q Propagation Delay.

com 258 .http://onsemi.

CHAPTER 5 Reliability Data http://onsemi.com 259 .

com 260 .http://onsemi.

administration at offshore locations.com 261 .0 INTRODUCTION The Reliability Audit Program developed in March 1977 is the ON Semiconductor internal reliability audit which is designed to assess outgoing product performance under accelerated stress conditions. Frequency of testing is specified per internal document 12MRM15301A. including updating its requirements. and monthly reporting of results.“RAP” Reliability Audit Program for Logic Integrated Circuits 1. Logic Reliability Engineering has overall responsibility for RAP.0. http://onsemi. interpreting its results. These reports are available at all sales offices. Each sample receives the tests specified in section 2. RAP is a system of environmental and electrical tests performed periodically on randomly selected samples of standard products.

7. 16 hrs. 4.) and will include all assembly locations.com 262 . Method 1010. Device types sampled will be by generic type within each logic I/C product family (MECL. 6. All standard 25°C dc and functional parameters will be measured Go/No/Go at each readout. MG CMOS. OP LIFE — MIL-STD-883. 3. Additional sample reductions for high pin-count devices per TABLE II notes. – 65°C/+150°C. TTL. etc. Only moisture related failures (like corrosion) are criteria for failure on PTHB test. 45* 340 Initial Seal** PTHB 48 hrs PTH*** 48 hrs 100 Op Life 40 hours Temp Cycle 40 cycles interim test interim electrical Interim Electrical Add 460 cycles interim test Add 500 cycles final interim* test Temp Cycle# 1000 cycles (Additional) Op Life 210 hrs (Additional) Final Interim# Electrical PTH 48 hrs (Additional) Op Life# 750 hrs (Additional) Final Electrical (48 hrs) Final Electrical (96 hrs) Final Electrical & Seal** (2000 cycles) scrap Final# Electrical (1000 hrs) scrap # One sample per month for LS. 10K. PTHB is equivalent to approximately 800 hours of 85°C/85% RH THB for VCC ≤ 15 V. TEMP CYCLING — MIL-STD-883. scrap * PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs. NOTES: 1. Method 1005.2. 5. and HSL CMOS. Condition TEMP CYCLING — C. Sampling to include all package types routinely. TA = 145°C. 3. Special device specifications (48A’s) for logic products will reference 12MRM15301A as source of generic data for any customer required monthly audit reports. ** Seal (Fine & Gross Leak) required for hermetic products. *** PTH to be used when sockets for PTHB are not available. http://onsemi. Condition C OP LIFE — (Power plus Reverse Bias).0 TEST CONDITIONS AND COMMENTS PTHB — 15 psig/121°C/100% RH at rated VCC or VEE — PTHB — to be performed on plastic encapsulated devices PTHB — only.0 RAP TEST FLOW Pull 500* piece sample from lot following Group A acceptance. 2. Any indicated failure is first verified and then submitted to the Product Analysis Lab for detailed analysis. 10H.

CHAPTER 6 Package Information Including Surface Mount

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BIPOLAR LOGIC SURFACE MOUNT WHY SURFACE MOUNT?

Surface Mount Technology is now being utilized to offer answers to many problems that have been created in the use of insertion technology. Limitations have been reached with insertion packages and PC board technology. Surface Mount Technology offers the opportunity to continue to advance the State-of-the-Art designs that cannot be accomplished with Insertion Technology. Surface Mount Packages allow more optimum device performance with the smaller Surface Mount configuration. Internal lead lengths, parasitic capacitance and inductance that placed limitations on chip performance have been reduced. The lower profile of Surface Mount Packages allows more boards to be utilized in a given amount of space. They are stacked closer together and utilize less total volume than insertion populated PC boards. Printed circuit costs are lowered with the reduction of the number of board layers required. The elimination or reduction of the number of plated through holes in the board, contribute significantly to lower PC board prices. Surface Mount assembly does not require the preparation of components that are common on insertion technology lines. Surface Mount components are sent directly to the assembly line, eliminating an intermediate step.

Automatic placement equipment is available that can place Surface Mount components at the rate of a few thousand per hour to hundreds of thousands of components per hour. Surface Mount Technology is cost effective, allowing the manufacturer the opportunity to produce smaller units and/or offer increased functions with the same size product.
SURFACE MOUNT AVAILABILITY

Bipolar Logic is currently offering LS-TTL in production quantities in SOIC packages. Refer to the following Selector Guide (SG366/D) which indicate availability and package type for these families. These families may be ordered in rails or on Tape and Reel. Refer to Tape and Reel information for ordering details.
THERMAL DATA

The power dissipation of surface mount packages is dependent on many factors that must be taken into consideration in the initial board design. The board material, the board surface metal thickness, pad area and the proximity to other heat generating components all have a bearing on the device dissipation capability.

200

180

°C/W θJA

160

MIN DIE SIZE 2K MILS2

140

120 SEE FIG. 2 FOR HEAT SINK DETAIL SO-8 (.090″ x .110″) LEADFRAME METAL = COPPER

MAX DIE SIZE 8K MILS2

100

SO-14 (.090″ x .170″)

SO-16 (.090″ x .170″) NARROW

PACKAGE STYLE DATA TAKEN USING PHILIPS SO TEST BOARD # 7322-078, 80873

Figure 1. Thermal Resistance, Junction-To-Ambient (°C/W)

Measurement specimens are solder mounted on printed circuit card 19 mm × 28 mm × 1.5 mm in still air. No auxiliary thermal condition aids are used.

This data was collected using thermal test die in 20-pin PLCC packages on PLCC test boards (2.24″ x 2.24″ x .062″ glass epoxy, type FR-4, with solder coated 1 oz./sq. ft. copper).

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TAPE AND REEL STANDARD BIPOLAR LOGIC INTEGRATED CIRCUITS

ON Semiconductor has now added the convenience of Tape and Reel packaging for our growing family of standard Integrated Circuit products. The packaging fully conforms

to the latest EIA RS-481A specification. The antistatic embossed tape provides a secure cavity sealed with a peel-back cover tape.

MECHANICAL POLARIZATION SOIC DEVICES
Typical

View is from tape side Linear direction of travel

GENERAL INFORMATION

— Reel Size 13 inch (330 mm) Suffix R2 — Tape Width 12 mm to 24 mm (see table) — Units/Reel (see table) — No Partial Reel Counts Available and Minimum Lot Size is Per Table
ORDERING INFORMATION

To order devices which are to be delivered in Tape and Reel, add the suffix R2 to the device number being ordered.
Table 1 Tape and Reel Data
Device Type SO-8 SO-14 SO-16 SO-16 Wide SO-20 Wide Tape Width (mm) 12 16 16 16 24 Device/Reel 2,500 2,500 2,500 1,000 1,000 Reel Size (inch) 13 13 13 13 13 Min Lot Size Per Part No. Tape and Reel 5,000 5,000 5,000 5,000 5,000

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PACKAGE OUTLINES
SOIC
Case 751A-02 D Suffix 14-Pin Plastic SO-14
NOTES: 1. DIMENSIONS “A” AND “B” ARE DATUMS AND “T” IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. CONTROLLING DIMENSION: MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 6. 751A-01 IS OBSOLETE, NEW STANDARD 751A-02. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.25 0.19 0.10 0.25 0° 7° 6.20 5.80 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0° 7° 0.229 0.244 0.010 0.019

-A14 8

-B1 7

P
7 PL

0.25 (0.010)

M

B

M

G

C
SEATING PLANE

R X 45°

D 14 PL 0.25 (0.010)
M

K T B
S

M

F

J

A

S

-A-

Case 751B-03 D Suffix 16-Pin Plastic SO-16
9

16

-B1 8

P
8 PL

0.25 (0.010)

M

B

M

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B-01 IS OBSOLETE, NEW STANDARD 751B-03. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0° 7° 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0° 7° 0.229 0.244 0.010 0.019

R X 45° G -TD 16 PL 0.25 (0.010)
M

C
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K T B
S

M

F

J

A

S

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Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE)

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NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751D-01, AND -02 OBSOLETE, NEW STANDARD 751D-03. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.50 1.27 BSC 0.32 0.25 0.25 0.10 7° 0° 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 7° 0° 0.395 0.415 0.010 0.029

G R X 45° -TC K
M SEATING PLANE

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http://onsemi.com
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55 6.80 19.010) M J M T A M Case 738-03 N Suffix 20-Pin Plastic -A20 1 11 10 B C L NOTES: 1.01 0.020 0.175 0. 2.039 A F C N H G D SEATING PLANE NOTE 4 L J K M -A16 9 Case 648-08 N Suffix 16-Pin Plastic B 1 8 NOTES: 1.44 0.57 3.51 1.715 0.270 0.32 2.052 0.150 0.62 BSC 15° 0° 1. 738-02 OBSOLETE.54 BSC 1. ROUNDED CORNERS OPTIONAL. DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 25.01 INCHES MIN MAX 0. 646-05 OBSOLETE.92 3.095 0.62 BSC 0° 10° 0. DIMENSION “L” TO CENTER OF LEAD WHEN FORMED PARALLEL.145 0.008 0.070 0.015 0.56 6.015 0.5M. DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18. 5.39 0.55 2. CONTROLLING DIMENSION: INCH.78 2.050 BSC 0.740 0.300 BSC 0° 10° 0.015 0. NEW STANDARD 648-08.021 0.040 0.27 BSC 0.51 INCHES MIN MAX 1.38 0.070 0.38 2.PACKAGE OUTLINES PLASTIC Case 646-06 N Suffix 14-Pin Plastic 14 8 B 1 7 NOTES: 1.008 0.53 1. 3.55 0.39 1. 4.17 6.260 0.21 0.25 (0.010) M N M J 20 PL 0.100 BSC 0. ROUNDED CORNERS OPTIONAL. 5. 5.01 INCHES MIN MAX 0.040 F S C -TK SEATING PLANE L H G D 16 PL 0.02 1.81 0. 1982.27 BSC 1.50 7. NEW STANDARD 738-03.015 0.38 0.02 1. DIMENSIONING AND TOLERANCING PER ANSI Y14. 3.com 268 .295 0.110 0.110 0.77 1.80 3.070 0.015 0.20 0. NEW STANDARD 646-06.69 4.60 6.130 0. DIMENSION “B” DOES NOT INCLUDE MOLD FLASH.53 1.300 BSC 15° 0° 0.77 2.80 7.185 0. LEADS WITHIN 0.305 0° 10° 0.30 7.21 3.43 7.69 4.040 -TSEATING PLANE K E G F D 20 PL 0.770 0.010) T A M M T B M http://onsemi.115 0.050 0.240 0. DIMENSION “B” DOES NOT INCLUDE MOLD FLASH.25 (0. 648-01 THRU -07 OBSOLETE.260 0. 4.13 mm (0.070 0.100 BSC 0.69 0.38 2.015 0. 2. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 18.250 0.35 6.240 0.66 27.015 0. CONTROLLING DIMENSION: INCH.39 1.16 19. DIMENSIONING AND TOLERANCING PER ANSI Y14.770 0.022 0.74 0° 10° 0.54 BSC 0.180 0.41 0. 6.140 0. 4.008 0. DIMENSION “L” TO CENTER OF LEADS WHEN FORMED PARALLEL. DIMENSION “B” DOES NOT INCLUDE MOLD FLASH.85 3.10 6.10 4.25 (0. 1982.5M.040 0.27 2.010 1.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.54 BSC 1.135 0.100 BSC 0.021 0.145 0. DIMENSION “L” TO CENTER OF LEADS WHEN FORMED PARALLEL.60 3. 3.020 0. 2.050 BSC 0.

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com 271 .Notes http://onsemi.

com 272 .Notes http://onsemi.

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