Altera DE2-70 Board

Version 1.08

Copyright © 2009 Terasic Technologies

Altera DE2-70 Board

CONTENTS
Chapter 1 DE2-70 Package ...............................................................................................................1 1.1 1.2 1.3 Package Contents .................................................................................................................1 The DE2-70 Board Assembly ..............................................................................................2 Getting Help.........................................................................................................................3

Chapter 2 Altera DE2-70 Board .......................................................................................................4 2.1 2.2 2.3 Layout and Components ......................................................................................................4 Block Diagram of the DE2-70 Board ..................................................................................5 Power-up the DE2-70 Board................................................................................................9

Chapter 3 DE2-70 Control Panel.................................................................................................... 11 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Control Panel Setup ........................................................................................................... 11 Controlling the LEDs, 7-Segment Displays and LCD Display .........................................13 Switches and Buttons .........................................................................................................15 SDRAM/SSRAM/Flash Controller and Programmer........................................................16 USB Monitoring.................................................................................................................18 PS2 Device.........................................................................................................................19 SD CARD ..........................................................................................................................20 Audio Playing and Recording ............................................................................................21 Overall Structure of the DE2-70 Control Panel .................................................................23

Chapter 4 DE2-70 Video Utility ......................................................................................................25 4.1 4.2 4.3 4.4 Video Utility Setup.............................................................................................................25 VGA Display......................................................................................................................26 Video Capture ....................................................................................................................27 Overall Structure of the DE2-70 Video Utility ..................................................................28

Chapter 5 Using the DE2-70 Board................................................................................................30 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 Configuring the Cyclone II FPGA .....................................................................................30 Using the LEDs and Switches............................................................................................32 Using the 7-segment Displays............................................................................................36 Clock Circuitry...................................................................................................................38 Using the LCD Module......................................................................................................40 Using the Expansion Header..............................................................................................41 Using VGA ........................................................................................................................45 Using the 24-bit Audio CODEC ........................................................................................48 RS-232 Serial Port .............................................................................................................49 PS/2 Serial Port ..................................................................................................................49 Fast Ethernet Network Controller ......................................................................................50
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Altera DE2-70 Board 5.12 5.13 5.14 5.15 5.16 TV Decoder........................................................................................................................52 Implementing a TV Encoder..............................................................................................54 Using USB Host and Device..............................................................................................55 Using IrDA.........................................................................................................................57 Using SDRAM/SRAM/Flash.............................................................................................58

Chapter 6 Examples of Advanced Demonstrations ......................................................................66 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 DE2-70 Factory Configuration ..........................................................................................66 Quartus II 9.1 & Nios II EDS 9.1 Users ............................................................................67 TV Box Demonstration ......................................................................................................67 TV Box Picture in Picture (PIP) Demonstration................................................................70 USB Paintbrush..................................................................................................................73 USB Device........................................................................................................................75 A Karaoke Machine ...........................................................................................................77 Ethernet Packet Sending/Receiving ...................................................................................79 SD Card Music Player........................................................................................................81 Music Synthesizer Demonstration .....................................................................................84 Audio Recording and Playing ............................................................................................88

Chapter 7 Appendix .........................................................................................................................91 7.1 7.2 Revision History ................................................................................................................91 Copyright Statement ..........................................................................................................91

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1 shows a photograph of the DE2-70 package. 1. 1 . Figure 1.DE2-70 User Manual Chapter 1 DE2-70 Package The DE2-70 package contains all components needed to use the DE2-70 board in conjunction with a computer that runs the Microsoft Windows software.1.1 Package Contents Figure 1. The DE2-70 package contents.

2 • • The DE2-70 Board Assembly Assemble a rubber (silicon) cover. including the User Manual. tutorials. and is mounted over the top of the board by using additional stands and screws To assemble the included stands for the DE2-70 board: Figure 1.2. reference designs and demonstrations. The bag also contains some extender pins. The feet for the DE2-70 board. device datasheets. the Control Panel utility. 2 . for each of the six copper stands on the DE2-70 board The clear plastic cover provides extra protection. which can be used to facilitate easier probing with testing equipment of the board’s I/O expansion headers Clear plastic cover for the board 12V DC wall-mount power supply • • • • 1.2.DE2-70 User Manual The DE2-70 package includes: • • • The DE2-70 board USB Cable for FPGA programming and control DE2-70 System CD containing the DE2-70 documentation and supporting materials. and a set of laboratory exercises CD-ROMs containing Altera’s Quartus® II Web Edition and the Nios® II Embedded Design Suit Evaluation Edition software. as shown in Figure 1. Bag of six rubber (silicon) covers for the DE2-70 board stands.

302 Email: support@terasic.com Web: DE2-70.com • 3 . Rd. Taiwan.com Terasic Technologies No. Sec. 95134 USA Email: university@altera. 1. HsinChu County. Fusing E. 356.3 Getting Help Here are the addresses where you can get help if you encounter problems: • Altera Corporation 101 Innovation Drive San Jose. California.terasic.DE2-70 User Manual 1. Jhubei City.

EPCS16 USB Blaster (on board) for programming and user API control. The following hardware is provided on the DE2-70 board: • • • Altera Cyclone® II 2C70 FPGA device Altera Serial Configuration device . It depicts the layout of the board and indicates the location of the connectors and key components.DE2-70 User Manual Chapter 2 Altera DE2-70 Board This chapter presents the features and design characteristics of the DE2-70 board. The DE2-70 board. 2.1. Ethernet 10/100M Port USB Device Port USB Blaster Port Mic in Line In Line Out Video In 1 Video In 2 VGA Out RS-232 Port USB Host Port TV Decoder (NTSC/PAL) X2 12V DC Power Supply Connector Power ON/OFF Switch USB Host/Slave Controller Audio CODEC Altera USB Blaster Controller chipset Altera EPCS16 Configuration Device 50Mhz Oscillator Expansion Header 2 Expansion Header 1 PS2 Port VGA 10-bit DAC Ethernet 10/100M Controller RUN/PROG Switch for JTAG/AS Modes SD Card Slot (SD Card Not Included) Lock 16x2 LCD Module Altera Cyclone II FPGA with 70K LEs IrDA Transceiver 7-Segment Displays 8Mbyte Flash Memory 18 Red LEDs 18 Toggle Switches 8 Green LEDs SMA Extemal Clock 32Mbyte SDRAMx2 28Mhz Oscillator 2Mbyte SSRAM 4 Push-button Switches Figure 2.1 Layout and Components A photograph of the DE2-70 board is shown in Figure 2. from simple circuits to various multimedia projects.1. The DE2-70 board has many features that allow the user to implement a wide range of designed circuits. both JTAG and Active Serial 4 .

the user can configure the FPGA to implement any system design. the DE2-70 board has software support for standard I/O interfaces and a control panel facility for accessing various components. and microphone-in jacks VGA DAC (10-bit high-speed triple DACs) with VGA-out connector 2 TV Decoder (NTSC/PAL/SECAM) and TV-in connector 10/100 Ethernet Controller with a connector USB Host/Slave Controller with USB type A and type B connectors RS-232 transceiver and 9-pin connector PS/2 mouse/keyboard connector IrDA transceiver 1 SMA connector Two 40-pin Expansion Headers with diode protection In addition to these hardware features. 5 . software is provided for a number of demonstrations that illustrate the advanced capabilities of the DE2-70 board. In order to use the DE2-70 board. The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera’s DE2-70 Board and Quartus II Introduction (which exists in three versions based on the design entry method used. VHDL or schematic entry). namely Verilog.63-MHz oscillator for clock sources 24-bit CD-quality audio CODEC with line-in. To provide maximum flexibility for the user.DE2-70 User Manual (AS) programming modes are supported • • • • • • • • • • • • • • • • • • • 2-Mbyte SSRAM Two 32-Mbyte SDRAM 8-Mbyte Flash memory SD Card socket 4 pushbutton switches 18 toggle switches 18 red user LEDs 9 green user LEDs 50-MHz oscillator and 28. These tutorials are provided in the directory DE2_70_tutorials on the DE2-70 System CD-ROM that accompanies the DE2-70 board and can also be found on Altera’s DE2-70 web pages. 2. line-out. Also. all connections are made through the Cyclone II FPGA device. Thus. the user has to be familiar with the Quartus II software.2 gives the block diagram of the DE2-70 board.2 Block Diagram of the DE2-70 Board Figure 2.

416 LEs 250 M4K RAM blocks 1. Block diagram of the DE2-70 board. Following is more detailed information about the blocks in Figure 2.152.2: Cyclone II 2C70 FPGA • • • • • • • 68.000 total RAM bits 150 embedded multipliers 4 PLLs 622 user I/O pins FineLine BGA 896-pin package Serial Configuration device and USB Blaster circuit • • • Altera’s EPCS16 Serial Configuration device On-board USB Blaster for programming and user API control JTAG and AS programming modes are supported 6 .DE2-70 User Manual Figure 2.2.

DE2-70 User Manual SSRAM • • • 2-Mbyte standard synchronous SRAM Organized as 512K x 36 bits Accessible as memory for the Nios II processor and by the DE2-70 Control Panel SDRAM • • • Two 32-Mbyte Single Data Rate Synchronous Dynamic RAM memory chips Organized as 4M x 16 bits x 4 banks Accessible as memory for the Nios II processor and by the DE2-70 Control Panel Flash memory • • • 8-Mbyte NOR Flash memory Support both byte and word mode access Accessible as memory for the Nios II processor and by the DE2-70 Control Panel SD card socket • • Provides SPI and 1-bit SD mode for SD Card access Accessible as memory for the Nios II processor with the DE2-70 SD Card Driver Pushbutton switches • • • 4 pushbutton switches Debounced by a Schmitt trigger circuit Normally high. generates one active-low pulse when the switch is pressed Toggle switches • • 18 toggle switches for user inputs A switch causes logic 0 when in the DOWN (closest to the edge of the DE2-70 board) position and logic 1 when in the UP position Clock inputs • • • 50-MHz oscillator 28.63-MHz oscillator SMA external clock input 7 .

and microphone input jacks Sampling frequency: 8 to 96 KHz Applications for MP3 players and recorders.0 Supports data transfer at full-speed and low-speed Supports both USB host and device Two USB ports (one type A for a host and one type B for a device) Provides a high-speed parallel interface to most available processors. with auto-MDIX Fully compliant with the IEEE 802. voice recorders. supports Nios II with a Terasic driver Supports Programmed I/O (PIO) and Direct Memory Access (DMA) 8 . 4X over-sampling for CVBS Supports Composite Video (CVBS) RCA jack input Supports digital output formats : 8-bit ITU-R BT. Digital TV. Portable video devices. and FIELD Applications: DVD recorders. line-level output. etc. VS.DE2-70 User Manual Audio CODEC • • • • Wolfson WM8731 24-bit sigma-delta audio CODEC Line-level input.656 YCrCb 4:2:2 output + HS.3u Specification Supports IP/TCP/UDP checksum generation and checking Supports back-pressure mode for half-duplex mode flow control USB Host/Slave controller • • • • • • Complies fully with Universal Serial Bus Specification Rev. smart phones. VGA output • • • • Uses the ADV7123 140-MHz triple 10-bit high-speed video DAC With 15-pin high-density D-sub connector Supports up to 1600 x 1200 at 100-Hz refresh rate Can be used with the Cyclone II FPGA to implement a high-performance TV Encoder NTSC/PAL/ SECAM TV decoder circuit • • • • • • Uses two ADV7180 Multi-format SDTV Video Decoders Supports worldwide NTSC/PAL/SECAM color demodulation One 10-bit ADC. 2. 10/100 Ethernet controller • • • • • • Integrated MAC and PHY with a general processor interface Supports 100Base-T and 10Base-T applications Supports full-duplex operation at 10 Mb/s and 100 Mb/s. LCD TV. Set-top boxes. PDAs. and TV PIP (picture in picture) display.

Connect a VGA monitor to the VGA port on the DE2-70 board 4.2-kb/s infrared transceiver 32 mA LED drive current Integrated EMI shield IEC825-1 Class 1 eye safe Edge detection input Two 40-pin expansion headers • • • 72 Cyclone II I/O pins. as well as 8 power and ground lines. Turn the RUN/PROG switch on the left edge of the DE2-70 board to RUN position. it is necessary to install the Altera USB Blaster driver software.DE2-70 User Manual Serial ports • • • • One RS-232 port One PS/2 port DB-9 serial connector for the RS-232 port PS/2 connector for connecting a PS2 mouse or keyboard to the DE2-70 board IrDA transceiver • • • • • Contains a 115. Connect the 12V adapter to the DE2-70 board 3.3 Power-up the DE2-70 Board The DE2-70 board comes with a preloaded configuration bit stream to demonstrate some features of the board. If this driver is not already installed on the host computer. To power-up the board perform the following steps: 1. This bit stream also allows users to see quickly if the board is working properly. 2. Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2-70 board. the PROG position is used only for the AS Mode programming 6. Connect your headset to the Line-out audio port on the DE2-70 board 5. For communication between the host and the DE2-70 board. Turn the power on by pressing the ON/OFF switch on the DE2-70 board 9 . it can be installed as explained in the tutorial Getting Started with Altera's DE2-70 Board. are brought out to two 40-pin expansion connectors 40-pin header is designed to accept a standard 40-pin ribbon cable used for IDE hard drives Diode and resistor protection is provided 2. This tutorial is available in the directory DE2_70_tutorials on the DE2-70 System CD-ROM.

3. your voice will be mixed with the music played from the audio player • Figure 2.3. PC.DE2-70 User Manual At this point you should observe the following: • • • • • • All user LEDs are flashing All 7-segment displays are cycling through the numbers 0 to F The LCD display shows Welcome to the Altera DE2-70 The VGA monitor displays the image shown in Figure 2. you should hear a 1-kHz sound Set the toggle switch SW17 to the UP position and connect the output of an audio player to the Line-in connector on the DE2-70 board. Set the toggle switch SW17 to the DOWN position. or the like) You can also connect a microphone to the Microphone-in connector on the DE2-70 board. The default VGA output pattern. iPod. 10 . on your headset you should hear the music played from the audio player (MP3.

Launch the control panel by executing the “DE2_70_Control_Panel.1 Control Panel Setup The Control Panel Software Utility is located in the “DE2_70_control_panel” folder in the DE2-70 System CD-ROM. The . Set the RUN/PROG switch to the RUN position 4. connect the 12V power supply. The control codes include one . Click Download Code button. perform the following steps: 1. SDRAM-U2 or SSRAM. The facility can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code.sof file and one .1 will appear. and turn the power switch ON 3. . To activate the Control Panel. The program will call Quartus II and Nios II tools to download the control codes to the FPGA board through USB-Blaster[USB-0] connection. Specific control codes should be downloaded to your FPGA board before the control panel can request it to perform required tasks. just click the “Download Code” button on the program.exe on the host computer. 2. The host computer communicates with the board through an USB connection. To install it. Select the target memory. 6. 3. 5. Start the executable DE2_70_control_panel. Note. then describes its structure in block diagram form. The . the Control Panel will occupy the USB port until you 11 . Note. The . just copy the whole folder to your host computer. Make sure Quartus II and NIOS II are installed successfully on your PC.elf file is downloaded to either SDRAM-U2 or SSRAM. To download the codes.DE2-70 User Manual Chapter 3 DE2-70 Control Panel The DE2-70 board comes with a Control Panel facility that allows users to access various components on the board from a host computer.sof file is downloaded to FPGA.elf file will be downloaded to the target memory and the memory will be read-only in later memory access operation. Connect the supplied USB cable to the USB Blaster port. This chapter first presents some basic functions of the Control Panel. on the control panel. according to the user option.elf file.exe”. and finally describes its capabilities. The Control Panel user interface shown in Figure 3.

It communicates with the Control Panel window.2. The DE2-70 Control Panel. experiment by setting the value of some LEDs display and observing the result on the DE2-70 board. 12 . Figure 3. which is active on the host computer. The Control Panel is now ready for use.DE2-70 User Manual close that port. 7. It handles all requests and performs data transfers between the computer and the DE2-70 board. The concept of the DE2-70 Control Panel is illustrated in Figure 3. via the USB Blaster link.1. you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port. The graphical interface is used to issue commands to the control codes. The “Control Codes” that performs the control functions is implemented in the FPGA board.

3.2.2 Controlling the LEDs. monitor buttons/switches status. SSRAM and Flash Memory. Here. The feature of reading/writing a word or an entire file from/to the Flash Memory allows the user to develop multimedia applications (Flash Audio Player. The DE2-70 Control Panel can be used to light up LEDs. read data from a PS/2 keyboard. you can directly turn the individual LEDs on or off by selecting them or click “Light All” or “Unlight All”. 7-Segment Displays and LCD Display A simple function of the Control Panel is to allow setting the values displayed on LEDs. The DE2-70 Control Panel concept. Choosing the LED tab leads to the window in Figure 3. and the LCD character display. 3. monitor the status of an USB mouse. 7-segment displays.DE2-70 User Manual 7-SEG Display 16x2 LCD USB Blaster SDRAM Flash SSRAM Control Codes PS/2 USB Device SD Card Soket LEDs Figure 3. read/write the SDRAM. and read SD-CARD specification information. Flash Picture Viewer) without worrying about how to build a Memory Programmer. 13 . change the values displayed on 7-segment and LCD displays.

directly use the Up-Down control and Dot Check box to specified desired patterns. Controlling LEDs.3. In the tab sheet. Controlling 7-SEG display.4. Figure 3.DE2-70 User Manual Figure 3.4. Choosing the 7-SEG tab leads to the window in Figure 3. 14 . the 7-SEG patterns on the board will be updated immediately.

3. Press Stop to end the monitoring process. 15 . The function is designed to monitor the status of switches and buttons in real time and show the status in a graphical user interface. Press the Start button to start button/switch status monitoring process. and button caption is changed from Start to Stop. the status of buttons and switches on the board is shown in the GUI window and updated in real time. In the monitoring process.3 Switches and Buttons Choosing the Button tab leads to the window in Figure 3. It can be used to verify the functionality of the switches and buttons. Text can be written to the LCD display by typing it in the LCD box and pressing the Set button.5. Thus.6. The ability to set arbitrary values into simple display devices is not needed in typical design activities. However. Figure 3.5. it can be used for troubleshooting purposes. Controlling LEDs and the LCD display. it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected.DE2-70 User Manual Choosing the LCD tab leads to the window in Figure 3.

and FLASH. Also. the same approach is used to access the SDRAM-U2.4 SDRAM/SSRAM/Flash Controller and Programmer The Control Panel can be used to write/read data to/from the SDRAM. Thus. The ability to check the status of button and switch is not needed in typical design activities. please erase the flash before writing data to it. SRAM. SSRAM. Monitoring switches and buttons.DE2-70 User Manual Figure 3. Please note the target memory chosen for storing . We will describe how the SDRAM-U1 may be accessed.7. However. 3. it can be used for troubleshooting purposes. Click on the Memory tab and select “SDRAM-U1” to reach the window in Figure 3. it provides users a simple mechanism for verifying if the buttons and switches are functioning correctly. 16 .6.elf file is read-only. and FLASH chips on the DE2-70 board.

Contents of the location can be read by pressing the Read button.DE2-70 User Manual Figure 3. 67. 23. Accessing the SDRAM-U1. 3.7. and pressing the Write button. The Control Panel also supports loading files with a . a file containing the line 0123456789ABCDEF defines four 8-bit values: 01. CD. To initiate the writing of data. 4. specify the desired file in the usual manner. AB. 89. Figure 3. followed by reading the same location. then a checkmark may be placed in the File Length box instead of giving the number of bytes. EF. If the entire file is to be loaded. click on the Write a File to Memory button. These values will be loaded consecutively 17 . When the Control Panel responds with the standard Windows dialog box asking for the source file. Specify the number of bytes to be written in the Length box.hex extension. 2. For example. 45. The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows: 1.hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values. Specify the starting address in the Address box. Files with a .7 depicts the result of writing the hexadecimal value 06CA into location 200. A 16-bit word can be written into the SDRAM by entering the address of the desired location. specifying the data to be written.

Specify the number of bytes to be copied into the file in the Length box. 3. Users can use the similar way to access the SSRAM and Flash. When the Control Panel responds with the standard Windows dialog box asking for the destination file. Plug an USB mouse to the USB HOST port on the DE2-70 board. The Sequential Read function is used to read the contents of the SDRAM-U1 and place them into a file as follows: 1. 2. Please note that users need to erase the flash before writing data to it. then place a checkmark in the Entire Memory box. Press Load Memory Content to a File button. Press the Start button to start the USB mouse monitoring process.y) with range from (0. 3. specify the desired file in the usual manner. the status of the USB mouse is updated and shown in the Control Panel’s GUI window in real-time. and button caption is changed from Start to Stop. Follow the steps below to exercise the USB Mouse Monitoring tool: 1. The mouse movement is translated as a position (x. 18 . Choosing the USB tab leads to the window in Figure 3. This function can be used to verify the functionality of the USB Host. The movement of the mouse and the status of the three buttons will be shown in the graphical and text interface. 2.767). Press Stop to terminate the monitoring process. 3. In the monitoring process.5 USB Monitoring The Control Panel provides users a USB monitoring tool which monitors the real-time status of a USB mouse connected to the DE2-70 board. 4. If the entire contents of the SDRAM-U1 are to be copied (which involves all 32 Mbytes). Specify the starting address in the Address box.0)~(1023.DE2-70 User Manual into the memory.8.

6 PS2 Device The Control Panel provides users a tool to receive the inputs from a PS2 keyboard in real time. Press Stop to terminate the monitoring process. This function can be used to verify the functionality of the PS2 Interface. USB Mouse Monitoring Tool. For control key.9. Button caption is changed from Start to Stop. The input data will be displayed in the control window in real time. Plug a PS2 Keyboard to the FPGA board. Then. 3. 2. Press the Start button to start PS2Keyboard input receiving process. 19 . The received scan-codes are translated to ASCII code and displayed in the control window. Please follow the steps below to exercise the PS2 device: 1.DE2-70 User Manual Figure 3.8. Only visible ASCII codes are displayed. 3. only “Carriage Return/ENTER” key is implemented. Choosing the PS2 tab leads to the window in Figure 3. In the receiving process. users can start to press the attached keyboard. 4.

Reading the PS2 Keyboard.7 SD CARD The function is designed to read the identification and specification of the SD card. 3.9. 20 . Choosing the SD-CARD tab leads to the window in Figure 3. This function can be used to verify the functionality of SD-CARD Interface. then press the Read button to read the SD card. 2. First.DE2-70 User Manual Figure 3. Follow the steps below to exercise the SD card: 1.10. The SD card’s identification and specification will be displayed in the control window. Insert a SD card to the DE2-70 board. The 1-bit SD MODE is used to access the SD card.

3. It can play audio stored in a given WAVE file. 4. and 16-bits per channel. Follow the steps below to exercise this tool. 48K. and save the audio signal as a wave file. To stop the audio playing. simply click “Stop Play”. Click “Start Play” to start audio play. 3. Click “Open Wave” to select a WAVE file.DE2-70 User Manual Figure 3.11. 21 . Reading the SD card Identification and Specification. The program will download the waveform to SDRAM-U1. 32K. In the waveform window. or 8K.11. 2. stereo (2 channels per sample). The sampling rate of the wave file also is displayed in the Sample Rate Combo-Box. configure the audio chip for audio playing. The WAVE file must be uncompressed. Select the “Play Audio” item in the com-box. as shown in Figure 3. You can drag the scrollbar to browse the waveform. the blue line represents left-channel signal and green line represents right-channel signal. Its sample rate must be either 96K. 1.8 Audio Playing and Recording This interesting audio tool is designed to control the audio chip on the DE2-70 board for audio playing and recording. 44. 5. You will hear the audio sound from the headset or speaker. To play audio.1K.10. record audio. Choosing the Audio tab leads to the window in Figure 3. The waveform of the specified wave file will be displayed in the waveform window. and then start the audio playing process. plug a headset or speaker to the LINE-OUT port on the board.

DE2-70 User Manual Figure 3. 22 . 2. To stop recording. 3.11. Playing audio from a selected wave file To record sound using a microphone. 4. click “Stop Record”. Finally. Click “Save Wave” to save the waveform into a WAV file.12. as shown in Figure 3. audio signal saved in SDRAM-U1 will be uploaded to the host computer and displayed on the waveform window. The program will configure the audio chip for MIC recording. please follow the steps below: 1. Click “Start Record” to start the record process. and then save the audio signal into SDRAM-U1. Plug a microphone to the MIC port on the board. Select the “Record MIC” item in the com-box and select desired sampling rate. retrieve audio signal from the MIC port.

To run the Control Panel.DE2-70 User Manual Figure 3. The NIOS II interprets the commands sent from the PC and performs the corresponding actions. Figure 3.9 Overall Structure of the DE2-70 Control Panel The DE2-70 Control Panel is based on a NIOS II system running in the Cyclone II FPGA with the SDRAM-U2 or SSRAM. The code is located inside the DE2_70_demonstrations directory on the DE2 System CD-ROM.1. the hardware part is implemented in Verilog code with SOPC builder. Audio Recording and Saving as a WAV file. Each input/output device is controlled by the NIOS II Processor instantiated in the FPGA chip. 23 . users must first configure it as explained in Section 3. 3. To record audio sound from LINE-IN port. The software part is implemented in C code. The communication with the PC is done via the USB Blaster link. which makes it possible for a knowledgeable user to change the functionality of the Control Panel.12. please connect an audio source to the LINE-IN port on the board. The operation is as same as recording audio from MIC.13 depicts the structure of the Control Panel.

DE2-70 User Manual FPGA/ SOPC SEG7 Controller SDRAM Controller 7-SEG Display SDRAM U1 SDRAM U2 LCD USB Mouse PS2 Keyboard LED/Button/ Switch/ Seg7/ SD.MM Tris tate Bridge Avalon. 24 .Card Nios II Program NIOS II System Interconnect Fabric SDRAM Controller LCD Controller USB Controller PS2 Controller PIO Controller TIMER JTAG Blaster Hardware JTAG Avalon.MM Tri state Bridge Flash Controller SSRAM Controller Flash Nios II Program SSRAM Figure 3. The block diagram of the DE2-70 control panel.13.

exe on the host computer.elf file is downloaded to SDRAM-U1. Click the “Download Code” button. 25 . The Video Utility is now ready for use. capture the video sent from the video-in ports. This chapter first presents some basic functions of the Video Utility control panel. simply click the “Download Code” button on the program. 5. To activate the Video Utility. The . The configuration files include one .exe”. To download the codes. The facility can be used to verify the functionality of video components on the board. 4. or display desired pattern on the VGA port. perform the following steps: 1.1 Video Utility Setup The Video Utility is located in the “DE2_70_video_utility” folder in the DE2-70 System CD-ROM.1 will appear.DE2-70 User Manual Chapter 4 DE2-70 Video Utility The DE2-70 board comes with a video utility that allows users to access video components on the board from a host computer. connect the 12V power supply.sof file is downloaded to FPGA. you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port. and finally describes its capabilities. 2.sof file and one . The Video Utility user interface shown in Figure 4. The program will call Quartus II and Nios II tools to download the control codes to the FPGA board through USB-Blaseter[USB-0] connection. The Control Panel will occupy the USB port until you close that port. Make sure Quartus II and Nios II are installed successfully on your PC. Specific configuration files should be downloaded to your FPGA board before the Control Panel can request it to perform required tasks. Connect the supplied USB cable to the USB Blaster port. then describes its structure in block diagram form. and turn the power switch ON 3. 6. The . The host computer communicates with the board through the USB-Blaster link. Set the RUN/PROG switch to the RUN position 4. just copy the whole folder to your host computer.elf file. Start the executable DE2_70_VIDEO. Launch the Video Utility by executing the “DE2_70_VIDEO. To install it.

4. Click Load button and specify an image file for displaying. The selected image file will be displayed on the display window of the Video Utility. Click Display button to start downloading the image to the DE2-70 board.1. 3. Please follow the steps below to exercise the Video Utility: 1. It can be a bitmap or jpeg file. The DE2-70 Video Utility window. 2. you will see the desired image shown on the screen of the VGA monitor.2. 5.2 VGA Display Choosing the Display tab in the DE2-70 Video Utility leads to the window shown in Figure 4.DE2-70 User Manual Figure 4. 26 . Connect a VGA monitor to the VGA port of the board. The function is designed to download an image from the host computer to the FPGA board and output the image through the VGA interface with resolution 640x480. Select the desired Image Positioning method to fit the image to the VGA 640x480 display dimension. After finish downloading. 4.

4. such as a VCD/DVD player or NTSC/PAL camera.3 Video Capture Choosing the Capture tab leads to the window in Figure 4. Specify Video Source as VIDEO IN 1 or VIDEO IN 2. you will see the captured image shown in the display window of the Video Utility. 4. 27 . The input video source can be PAL or NTSC signals. Click Capture button to start capturing process.DE2-70 User Manual Figure 4. The image dimension of the captured image is also displayed. Displaying selected image file on VGA Monitor. 3.2.3. Users can click Save button to save the captured image as a bitmap or jpeg file. Then. and sent the image from the FPGA board to the host computer. The function is designed to capture an image from the video sources. Connect a video source. to VIDEO IN 1 or VIDEO IN 2 port on the board. 2. Please follow the steps below to capture an image from a video source: 1.

DE2-70 User Manual Figure 4. Each input/output device is controlled by the NIOS II Processor instantiated.3. the hardware part is implemented in Verilog code with SOPC builder. The code is located inside the DE2_70_demonstrations directory on the DE2-70 System CD-ROM. Video Capturing Tool. The software part is implemented in C code.4 depicts the block diagram of the Video Utility.4 Overall Structure of the DE2-70 Video Utility The DE2-70 Video Utility is based on a NIOS II system running in the Cyclone II FPGA with the SDRAM-U2 or SSRAM. 4. 28 . The communication between the DE2-70 board and the host PC is via the USB Blaster link. which makes it possible for a knowledgeable user to change the functionality of the Video Utility. Figure 4. The NIOS II processor interprets the commands sent from the PC and performs the appropriate actions.

Video Capture Block Diagram. 2. 4. Nios II processor interprets the command received and moves the raw image data from the SDRAM to SSRAM through the Multi-Port SSRAM controller. 2. Host computer issues a “capture” command to Nios II processor. 3. Nios II processor copies the raw image data from the SSRAM to SDRAM-U2. VGA Controller continuously reads the raw image data from the SSRAM and sends them to the VGA port. After capturing is done. 29 . The control flow for video capturing is described below: 1.DE2-70 User Manual FPGA SOPC NIOS II SDRAM Controller SDRAM Controller NIOS II Program SDRAM-U1 SDRAM-U2 VGA Controller VGA System Interconnect Fabric TIMER JTAG Blaster Hardware JTAG Multi . 3. 4.4. Host issues a “display” command to Nios II processor. Nios II processor interprets the command and controls Video-In controller to capture the raw image data into the SSRAM.Port SSRAM Controller Avalon MM Slave VIDEO-In Controller SSRAM VIDEO IN Figure 4. The control flow for video displaying is described below: 1. Host computer reads the raw image data from the SDRAM-U2 Host computer converts the raw image data to RGB color space and displays it. Host computer downloads the raw image data to SDRAM-U2.

JTAG programming: In this method of programming. Using this connection. the configuration is lost when the power is turned off. For both methods the DE2-70 board is connected to a host computer via a USB cable. called Active Serial programming. 1. This configuration data is automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board. When the board’s power is turned on. Using the Quartus II software. named after the IEEE standards Joint Test Action Group. AS programming: In this method. Both types of programming methods are described below. The user is encouraged to read the tutorial first. The FPGA will retain this configuration as long as power is applied to the board. This tutorial is available on the DE2-70 System CD-ROM. The DE2-70 board contains a serial EEPROM chip that stores configuration data for the Cyclone II FPGA. 5. the configuration bit stream is downloaded into the Altera EPCS16 serial EEPROM chip. The sections below describe the steps used to perform both JTAG and AS programming. This tutorial is found in the DE2_70_tutorials folder on the DE2-70 System CD-ROM. 2. and to treat the information below as a short reference. the board will be identified by the host computer as an Altera USB Blaster device. it is possible to reprogram the FPGA at any time. The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera’s DE2-70 Board. It provides non-volatile storage of the bit stream. the configuration bit stream is downloaded directly into the Cyclone II FPGA. the configuration data in the EPCS16 device is automatically loaded into the Cyclone II FPGA. so that the information is retained even when the power supply to the DE2-70 board is turned off. 30 .DE2-70 User Manual Chapter 5 Using the DE2-70 Board This chapter gives instructions for using the DE2-70 board and describes each of its I/O devices. and it is also possible to change the non-volatile data that is stored in the serial EEPROM chip.1 Configuring the Cyclone II FPGA The procedure for downloading a circuit from a host computer to the DE2-70 board is described in the tutorial Quartus II Introduction.

The JTAG configuration scheme. The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the .pof filename extension Once the programming operation is finished.1 illustrates the JTAG configuration setup. perform the following steps: • • • • Ensure that power is applied to the DE2-70 board Connect the supplied USB cable to the USB Blaster port on the DE2-70 board (see Figure 2.2 illustrates the AS configuration set up.DE2-70 User Manual Configuring the FPGA in JTAG Mode Figure 5. set the RUN/PROG switch back to the RUN 31 .1) Configure the JTAG programming circuit by setting the RUN/PROG switch (on the left side of the board) to the RUN position.sof filename extension USB Blaster Circuit Quartus II Programmer USB PROG/RUN MAX 3128 "RUN" JTAG Config Signals JTAG UART Auto Power-on Config JTAG Config Port EPCS16 Serial Configuration Device FPGA Figure 5. To download a configuration bit stream into the EPCS16 serial EEPROM device. Configuring the EPCS16 in AS Mode Figure 5. To download a configuration bit stream into the Cyclone II FPGA. perform the following steps: • • • • • Ensure that power is applied to the DE2-70 board Connect the supplied USB cable to the USB Blaster port on the DE2-70 board (see Figure 2.1) Configure the JTAG programming circuit by setting the RUN/PROG switch (on the left side of the board) to the PROG position.1. The EPCS16 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the .

3 volts) when it is not pressed. Since the pushbutton switches are debounced. they are appropriate for use as clock or reset inputs in a circuit. Each of these switches is debounced using a Schmitt Trigger circuit. this action causes the new configuration data in the EPCS16 device to be loaded into the FPGA chip. Each switch provides a high logic level (3. 5.3. the USB Blaster port on the DE2-70 board can also be used to control some of the board’s features remotely from a host computer. USB Blaster Circuit PROG/ RUN Quartus II Programmer AS Mode USB MAX 3128 "PROG" AS Mode Config Auto Power-on Config JTAG Config Port EPCS16 Serial Configuration Device Figure 5. Switch debouncing. The four outputs called KEY0. In addition to its use for JTAG and AS programming.DE2-70 User Manual position and then reset the board by turning the power switch off and back on. 32 . and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone II FPGA. Figure 5. KEY1.2. and provides a low logic level (0 volts) when depressed.3. The AS configuration scheme. as indicated in Figure 5.2 Using the LEDs and Switches The DE2-70 board provides four pushbutton switches. KEY2. Details that describe this method of using the USB Blaster port are given in Chapter 3.

When a switch is in the DOWN position (closest to the edge of the board) it provides a low logic level (0 volts) to the FPGA. A schematic diagram that shows the pushbutton and toggle switches is given in Figure 5.17] Figure 5.3 volts). Each LED is driven directly by a pin on the Cyclone II FPGA. and eight green LEDs are found above the pushbutton switches (the 9th green LED is in the middle of the 7-segment displays).4.DE2-70 User Manual There are also 18 toggle switches (sliders) on the DE2-70 board. the pins used to connect to the pushbutton switches and LEDs are displayed in Tables 5. Each switch is connected directly to a pin on the Cyclone II FPGA.5. Schematic diagram of the pushbutton and toggle switches. 33 .3. These switches are not debounced. A schematic diagram that shows the LED circuitry appears in Figure 5.2 and 5. Eighteen red LEDs are situated above the 18 toggle switches. driving its associated pin to a high logic level turns the LED on. and driving the pin low turns it off.1.. There are 27 user-controllable LEDs on the DE2-70 board. and are intended for use as level-sensitive data inputs to a circuit.3] SW17 SW16 SW15 SW14 SW[0. RN33 1 2 3 4 100K 8 7 6 5 VCC33 U8 GND OE KEYIN0 KEYIN1 KEYIN2 KEYIN3 BUTTON0 BUTTON1 BUTTON2 BUTTON3 10 19 11 12 13 14 15 16 17 18 RN34 8 7 6 5 120 1 2 3 4 KEY0 KEY1 KEY2 KEY3 4 1 TACT SW 3 2 4 1 TACT SW 3 2 4 1 TACT SW 3 2 4 1 TACT SW 3 2 C13 1u C14 1u C15 1u C16 1u VCC33 9 8 7 6 5 4 3 2 1 20 A8 A7 A6 A5 A4 A3 A2 A1 DIR VCC 74HC245 B8 B7 B6 B5 B4 B3 B2 B1 SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 4 1 2 3 5 SLIDE SW GND VCC33 SW0 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW1 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW2 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW3 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW4 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW5 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW6 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW7 GND GND SW8 SW9 SW10 SW11 SW12 SW13 4 1 2 3 5 SLIDE SW GND VCC33 SW8 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW9 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW10 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW11 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 SW12 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 R50 GND GND 120 SW13 SW14 SW15 SW16 SW17 4 1 2 3 5 SLIDE SW GND VCC33 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 GND GND 4 1 2 3 5 SLIDE SW GND VCC33 GND GND RN35 8 7 6 5 120 1 2 3 4 KEY[0.. Similarly. respectively.4. A list of the pin names on the Cyclone II FPGA that are connected to the toggle switches is given in Table 5. and when the switch is in the UP position it provides a high logic level (3.

PIN_AA23 PIN_AB26 PIN_AB25 PIN_AC27 PIN_AC26 PIN_AC24 PIN_AC23 PIN_AD25 PIN_AD24 PIN_AE27 PIN_W5 PIN_V10 PIN_U9 PIN_T9 PIN_L5 PIN_L4 PIN_L7 PIN_L8 Description Toggle Switch[0] Toggle Switch[1] Toggle Switch[2] Toggle Switch[3] Toggle Switch[4] Toggle Switch[5] Toggle Switch[6] Toggle Switch[7] Toggle Switch[8] Toggle Switch[9] Toggle Switch[10] Toggle Switch[11] Toggle Switch[12] Toggle Switch[13] Toggle Switch[14] Toggle Switch[15] Toggle Switch[16] Toggle Switch[17] Table 5. Schematic diagram of the LEDs. Signal Name SW[0] SW[1] SW[2] SW[3] SW[4] SW[5] SW[6] SW[7] SW[8] SW[9] SW[10] SW[11] SW[12] SW[13] SW[14] SW[15] SW[16] SW[17] FPGA Pin No.DE2-70 User Manual LED[0. Pin assignments for the toggle switches. 34 .1.26] LEDR0 LED0 LED1 LED2 LED3 RN10 1 2 3 4 330 8 7 6 5 LEDR1 LEDR2 LEDR3 LEDR LEDR LEDR LEDR LEDR4 LED4 LED5 LED6 LED7 RN11 1 2 3 4 330 8 7 6 5 LEDR5 LEDR6 LEDR7 LEDR LEDG0 LEDR LEDR LEDR LEDG3 LEDG LED19 LED20 LED21 LED22 RN15 1 2 3 4 330 8 7 6 5 LEDG1 LEDG2 LEDG LEDG LEDG LEDR8 LED8 LED9 LED18 RN12 1 2 3 4 330 8 7 6 5 LEDR9 LEDG8 LEDR LEDG4 LEDR LEDG LED23 LED24 LED25 LED26 RN16 1 2 3 4 330 8 7 6 5 LEDG5 LEDG6 LEDG7 LEDG LEDG LEDG LEDG LEDR10 LED10 LED11 LED12 LED13 RN13 1 2 3 4 330 8 7 6 5 LEDR11 LEDR12 LEDR13 LEDR LEDR LEDR LEDR LEDR14 LED14 LED15 LED16 LED17 RN14 1 2 3 4 330 8 7 6 5 LEDR15 LEDR16 LEDR17 LEDR LEDR LEDR LEDR Figure 5.5..

3.2. Signal Name LEDR[0] LEDR[1] LEDR[2] LEDR[3] LEDR[4] LEDR[5] LEDR[6] LEDR[7] LEDR[8] LEDR[9] LEDR[10] LEDR[11] LEDR[12] LEDR[13] LEDR[14] LEDR[15] LEDR[16] LEDR[17] LEDG[0] LEDG[1] LEDG[2] LEDG[3] LEDG[4] LEDG[5] LEDG[6] LEDG[7] LEDG[8] FPGA Pin No.DE2-70 User Manual Signal Name KEY[0] KEY[1] KEY[2] KEY[3] FPGA Pin No. PIN_AJ6 PIN_ AK5 PIN_AJ5 PIN_AJ4 PIN_AK3 PIN_AH4 PIN_AJ3 PIN_AJ2 PIN_AH3 PIN_AD14 PIN_AC13 PIN_AB13 PIN_AC12 PIN_AB12 PIN_AC11 PIN_AD9 PIN_AD8 PIN_AJ7 PIN_W27 PIN_ W25 PIN_ W23 PIN_ Y27 PIN_ Y24 PIN_ Y23 PIN_ AA27 PIN_ AA24 PIN_ AC14 Description LED Red[0] LED Red[1] LED Red[2] LED Red[3] LED Red[4] LED Red[5] LED Red[6] LED Red[7] LED Red[8] LED Red[9] LED Red[10] LED Red[11] LED Red[12] LED Red[13] LED Red[14] LED Red[15] LED Red[16] LED Red[17] LED Green[0] LED Green[1] LED Green[2] LED Green[3] LED Green[4] LED Green[5] LED Green[6] LED Green[7] LED Green[8] Table 5. PIN_T29 PIN_T28 PIN_U30 PIN_U29 Description Pushbutton[0] Pushbutton[1] Pushbutton[2] Pushbutton[3] Table 5. Pin assignments for the LEDs. 35 . Pin assignments for the pushbutton switches.

Table 5.6. with the intent of displaying numbers of various sizes. the decimal point is identified as DP. These displays are arranged into two pairs and a group of four.7.7. with the positions given in Figure 5.4 shows the assignments of FPGA pins to the 7-segment displays. 0 5 6 4 3 1 2 DP Figure 5. Schematic diagram of the 7-segment displays.DE2-70 User Manual 5. In addition. Applying a low logic level to a segment causes it to light up. PIN_AE8 PIN_AF9 PIN_AH9 PIN_AD10 PIN_AF10 PIN_AD11 PIN_AD12 Description Seven Segment Digit 0[0] Seven Segment Digit 0[1] Seven Segment Digit 0[2] Seven Segment Digit 0[3] Seven Segment Digit 0[4] Seven Segment Digit 0[5] Seven Segment Digit 0[6] 36 .. HEX0_D[0. Position and index of each segment in a 7-segment display. As indicated in the schematic in Figure 5.6. and applying a high logic level turns it off. Signal Name HEX0_D[0] HEX0_D[1] HEX0_D[2] HEX0_D[3] HEX0_D[4] HEX0_D[5] HEX0_D[6] FPGA Pin No. the seven segments are connected to pins on the Cyclone II FPGA.6] RN17 1 2 3 4 RN18 1 2 3 4 1K 8 7 6 5 1K 8 7 6 5 HEX0 A0 B0 C0 D0 10 9 8 5 4 2 3 7 a b c d e f g dp HEX0_D0 HEX0_D1 HEX0_D2 HEX0_D3 VCC33 C A1 C A2 1 6 HEX0_D4 HEX0_D5 HEX0_D6 HEX0_DP E0 F0 G0 DP0 7Segment Display Figure 5. Each segment in a display is identified by an index from 0 to 6.3 Using the 7-segment Displays The DE2-70 Board has eight 7-segment displays.

DE2-70 User Manual HEX0_DP HEX1_D[0] HEX1_D[1] HEX1_D[2] HEX1_D[3] HEX1_D[4] HEX1_D[5] HEX1_D[6] HEX1_DP HEX2_D[0] HEX2_D[1] HEX2_D[2] HEX2_D[3] HEX2_D[4] HEX2_D[5] HEX2_D[6] HEX2_DP HEX3_D[0] HEX3_D[1] HEX3_D[2] HEX3_D[3] HEX3_D[4] HEX3_D[5] HEX3_D[6] HEX3_DP HEX4_D[0] HEX4_D[1] HEX4_D[2] HEX4_D[3] HEX4_D[4] HEX4_D[5] HEX4_D[6] HEX4_DP HEX5_D[0] HEX5_D[1] HEX5_D[2] HEX5_D[3] PIN_AF12 PIN_ AG13 PIN_ AE16 PIN_ AF16 PIN_AG16 PIN_AE17 PIN_AF17 PIN_AD17 PIN_ AC17 PIN_AE7 PIN_AF7 PIN_AH5 PIN_AG4 PIN_AB18 PIN_AB19 PIN_AE19 PIN_AC19 PIN_P6 PIN_P4 PIN_N10 PIN_N7 PIN_M8 PIN_M7 PIN_M6 PIN_M4 PIN_P1 PIN_P2 PIN_P3 PIN_N2 PIN_N3 PIN_M1 PIN_M2 PIN_L6 PIN_M3 PIN_L1 PIN_L2 PIN_L3 Seven Segment Decimal Point 0 Seven Segment Digit 1[0] Seven Segment Digit 1[1] Seven Segment Digit 1[2] Seven Segment Digit 1[3] Seven Segment Digit 1[4] Seven Segment Digit 1[5] Seven Segment Digit 1[6] Seven Segment Decimal Point 1 Seven Segment Digit 2[0] Seven Segment Digit 2[1] Seven Segment Digit 2[2] Seven Segment Digit 2[3] Seven Segment Digit 2[4] Seven Segment Digit 2[5] Seven Segment Digit 2[6] Seven Segment Decimal Point 2 Seven Segment Digit 3[0] Seven Segment Digit 3[1] Seven Segment Digit 3[2] Seven Segment Digit 3[3] Seven Segment Digit 3[4] Seven Segment Digit 3[5] Seven Segment Digit 3[6] Seven Segment Decimal Point 3 Seven Segment Digit 4[0] Seven Segment Digit 4[1] Seven Segment Digit 4[2] Seven Segment Digit 4[3] Seven Segment Digit 4[4] Seven Segment Digit 4[5] Seven Segment Digit 4[6] Seven Segment Decimal Point 4 Seven Segment Digit 5[0] Seven Segment Digit 5[1] Seven Segment Digit 5[2] Seven Segment Digit 5[3] 37 .

5.4 Clock Circuitry The DE2-70 board includes two oscillators that produce 28.DE2-70 User Manual HEX5_D[4] HEX5_D[5] HEX5_D[6] HEX5_DP HEX6_D[0] HEX6_D[1] HEX6_D[2] HEX6_D[3] HEX6_D[4] HEX6_D[5] HEX6_D[6] HEX6_DP HEX7_D[0] HEX7_D[1] HEX7_D[2] HEX7_D[3] HEX7_D[4] HEX7_D[5] HEX7_D[6] HEX7_DP PIN_K1 PIN_K4 PIN_K5 PIN_K6 PIN_H6 PIN_H4 PIN_H7 PIN_H8 PIN_G4 PIN_F4 PIN_E4 PIN_K2 PIN_K3 PIN_J1 PIN_J2 PIN_H1 PIN_H2 PIN_H3 PIN_G1 PIN_G2 Seven Segment Digit 5[4] Seven Segment Digit 5[5] Seven Segment Digit 5[6] Seven Segment Decimal Point 5 Seven Segment Digit 6[0] Seven Segment Digit 6[1] Seven Segment Digit 6[2] Seven Segment Digit 6[3] Seven Segment Digit 6[4] Seven Segment Digit 6[5] Seven Segment Digit 6[6] Seven Segment Decimal Point 6 Seven Segment Digit 7[0] Seven Segment Digit 7[1] Seven Segment Digit 7[2] Seven Segment Digit 7[3] Seven Segment Digit 7[4] Seven Segment Digit 7[5] Seven Segment Digit 7[6] Seven Segment Decimal Point 7 Table 5. 38 .8. The clock distribution on the DE2-70 board is shown in Figure 5. The board also includes an SMA connector which can be used to connect an external clock source to the board.4. Both two clock signals are connected to the FPGA that are used for clocking the user logic. In addition.86 MHz oscillator is used to drive the two TV decoders. The associated pin assignments for clock inputs to FPGA I/O pins are listed in Table 5.86 MHz and 50 MHz clock signals. the 28. all these clock inputs are connected to the phase lock loops (PLL) clock input pin of the FPGA allowed users can use these clocks as a source clock for the PLL circuit. Pin assignments for the 7-segment displays. Also. 5.

8. PIN_E16 PIN_AD15 PIN_D16 PIN_R28 PIN_R3 PIN_R29 Description 28 MHz clock input 50 MHz clock input 50 MHz clock input 50 MHz clock input 50 MHz clock input External (SMA) clock input Table 5. Block diagram of the clock distribution. 39 . Pin assignments for the clock inputs.DE2-70 User Manual GPIO_0 2 GPIO_1 2 SD Card 2 2 SMA Connector 4 AUDIO CODEC 50-MHz Oscillator 4 Cyclone II FPGA 28-MHz Oscillator TV decoder 1 2 PS/2 Ethernet TV decoder 2 VGA DAC SDRAM 1 SDRAM 2 SSRAM FLASH Figure 5. Signal Name CLK_28 CLK_50 CLK_50_2 CLK_50_3 CLK_50_4 EXT_CLOCK FPGA Pin No.5.

which is called HD44780.DE2-70 User Manual 5. which can be found on the manufacturer’s web site. A schematic diagram of the LCD module showing connections to the Cyclone II FPGA is given in Figure 5..5 Using the LCD Module The LCD module has built-in fonts and can be used to display text by sending appropriate commands to the display controller.6.9. The associated pin assignments appear in Table 5. Schematic diagram of the LCD module.7] R36 680 LCD_BLON R37 680 Q5 8050 1u LCD_BL LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 LCD_EN LCD_RW LCD_RS LCD_CONT LCD_VCC R39 47 DIS1 2 X 16 DIGIT LCD LCD-2x16 Figure 5. Q1 8050 Q2 8550 C6 VCC5 VCC43 LCD_ON R35 680 R34 680 Q3 8050 VCC43 Q4 VCC43 8550 R38 1K LCD_D[0. and from the Datasheet/LCD folder on the DE2-70 System CD-ROM.9. 40 GND BL D7 D6 D5 D4 D3 D2 D1 D0 EN RW RS CONT VCC GND 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 . Detailed information for using the display is available in its datasheet.

1 = Read LCD Enable LCD Command/Data Select. Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages.3V. Table 5. 0 = Write.11 shows the related schematics.6. 5. but this circuitry is included for all 72 data pins.3V (VCC33).DE2-70 User Manual Signal Name LCD_DATA[0] LCD_DATA[1] LCD_DATA[2] LCD_DATA[3] LCD_DATA[4] LCD_DATA[5] LCD_DATA[6] LCD_DATA[7] LCD_RW LCD_EN LCD_RS LCD_ON LCD_BLON FPGA Pin No. Therefore the LCD_BLON signal should not be used in users’ design projects. 1 = Data LCD Power ON/OFF LCD Back Light ON/OFF Table 5. 0 = Command. The voltage level of the I/O pins on the expansion headers can be adjusted to 3.7 lists the jumper settings of the JP1. 41 . PIN_E1 PIN_E3 PIN_D2 PIN_D3 PIN_C1 PIN_C2 PIN_C3 PIN_B2 PIN_F3 PIN_E2 PIN_F2 PIN_F1 PIN_G3 Description LCD Data[0] LCD Data[1] LCD Data[2] LCD Data[3] LCD Data[4] LCD Data[5] LCD Data[6] LCD Data[7] LCD Read/Write Select.5V.3V. and also provides DC +5V (VCC5). or 1. Table 5.6 Using the Expansion Header The DE2-70 Board provides two 40-pin expansion headers. and two GND pins. Each header connects directly to 36 pins of the Cyclone II FPGA. 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA.8V using JP1. users can use a jumper to select the input voltage of VCCIO5 to 3. Pin assignments for the LCD module.10. Because the expansion I/Os are connected to the BANK 5 of the FPGA and the VCCIO voltage (VCCIO5) of this bank is controlled by the header JP1. Figure 5. The pin-outs of the JP1 appear in the Figure 5. 2. Note that the current LCD modules used on DE2/DE2-70 boards do not have backlight.8 gives the pin assignments. 2. The figure shows the protection circuitry for only two of the pins on each header.8V to control the voltage level of the I/O pins.5V. Finally. DC +3. and 1. Among these 36 I/O pins.

5V 3. 1.10. 42 .8V 2.DE2-70 User Manual IO Voltage of Expansion JP1 Jumper Settings Short Pins 1 and 2 Short Pins 3 and 4 Short Pins 5 and 6 Supplied Voltage to VCCIO5 Headers (J4/J5) 1. Schematic diagram of the expansion headers.5V 3. Voltage level setting of the expansion headers using JP1.3V Table 5.3V 1.5V 3. JP1 pin settings.11. VCCIO5 D12 1 3 2 BAT54S 1 VCCIO5 D14 (GPIO 0) J4 GPIO_D0 2 BAT54S 3 GPIO_D1 IO_CLKINn0 IO_CLKINp0 IO_A2 IO_A4 IO_A6 VCC5 GPIO_D0 GPIO_D1 R51 R52 47 47 IO_A0 IO_A1 (protection registors and diodes not shown for other ports) VCC33 1 3 5 7 9 11 IO_A8 13 IO_A10 15 IO_A12 17 IO_CLKOUTn019 IO_CLKOUTp021 IO_A16 23 IO_A18 25 IO_A20 27 29 IO_A22 31 IO_A24 33 IO_A26 35 IO_A28 37 IO_A30 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 IO_A0 IO_A1 IO_A3 IO_A5 IO_A7 IO_A9 IO_A11 IO_A13 IO_A14 IO_A15 IO_A17 IO_A19 IO_A21 IO_A23 IO_A25 IO_A27 IO_A29 IO_A31 BOX Header 2X20M VCCIO5 D48 1 2 BAT54S VCCIO5 D50 1 3GPIO_D32 2 BAT54S 3GPIO_D33 IO_CLKINn1 IO_CLKINp1 IO_B2 IO_B4 IO_B6 VCC5 1 3 5 7 9 11 IO_B8 13 IO_B10 15 IO_B12 17 IO_CLKOUTn119 IO_CLKOUTp121 IO_B16 23 IO_B18 25 IO_B20 27 29 IO_B22 31 IO_B24 33 IO_B26 35 IO_B28 37 IO_B30 39 (GPIO 1) J5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 IO_B0 IO_B1 IO_B3 IO_B5 IO_B7 IO_B9 IO_B11 IO_B13 IO_B14 IO_B15 IO_B17 IO_B19 IO_B21 IO_B23 IO_B25 IO_B27 IO_B29 IO_B31 GPIO_D32 GPIO_D33 R60 R61 47 47 IO_B0 IO_B1 (protection registors and diodes not shown for other ports) VCC33 BOX Header 2X20M Figure 5.3V 2 4 6 JP1 1 3 5 Figure 5.8V 2.7.8V 2.

DE2-70 User Manual Signal Name IO_A [0] IO_A [1] IO_A [2] IO_A [3] IO_A [4] IO_A [5] IO_A [6] IO_A [7] IO_A [8] IO_A [9] IO_A [10] IO_A [11] IO_A [12] IO_A [13] IO_A [14] IO_A [15] IO_A [16] IO_A [17] IO_A [18] IO_A [19] IO_A [20] IO_A [21] IO_A [22] IO_A [23] IO_A [24] IO_A [25] IO_A [26] IO_A [27] IO_A [28] IO_A [29] IO_A [30] IO_A [31] IO_CLKINN0 IO_CLKINP0 IO_CLKOUTN0 IO_CLKOUTP0 FPGA Pin No. PIN_C30 PIN_C29 PIN_E28 PIN_D29 PIN_E27 PIN_D28 PIN_E29 PIN_G25 PIN_E30 PIN_G26 PIN_F29 PIN_G29 PIN_F30 PIN_G30 PIN_H29 PIN_H30 PIN_J29 PIN_H25 PIN_J30 PIN_H24 PIN_J25 PIN_K24 PIN_J24 PIN_K25 PIN_L22 PIN_M21 PIN_L21 PIN_M22 PIN_N22 PIN_N25 PIN_N21 PIN_N24 PIN_T25 PIN_T24 PIN_H23 PIN_G24 Description GPIO Connection 0 IO[0] GPIO Connection 0 IO[1] GPIO Connection 0 IO[2] GPIO Connection 0 IO[3] GPIO Connection 0 IO[4] GPIO Connection 0 IO[5] GPIO Connection 0 IO[6] GPIO Connection 0 IO[7] GPIO Connection 0 IO[8] GPIO Connection 0 IO[9] GPIO Connection 0 IO[10] GPIO Connection 0 IO[11] GPIO Connection 0 IO[12] GPIO Connection 0 IO[13] GPIO Connection 0 IO[14] GPIO Connection 0 IO[15] GPIO Connection 0 IO[16] GPIO Connection 0 IO[17] GPIO Connection 0 IO[18] GPIO Connection 0 IO[19] GPIO Connection 0 IO[20] GPIO Connection 0 IO[21] GPIO Connection 0 IO[22] GPIO Connection 0 IO[23] GPIO Connection 0 IO[24] GPIO Connection 0 IO[25] GPIO Connection 0 IO[26] GPIO Connection 0 IO[27] GPIO Connection 0 IO[28] GPIO Connection 0 IO[29] GPIO Connection 0 IO[30] GPIO Connection 0 IO[31] GPIO Connection 0 PLL In GPIO Connection 0 PLL In GPIO Connection 0 PLL Out GPIO Connection 0 PLL Out 43 .

DE2-70 User Manual IO_B [0] IO_B [1] IO_B [2] IO_B [3] IO_B [4] IO_B [5] IO_B [6] IO_B [7] IO_B [8] IO_B [9] IO_B [10] IO_B [11] IO_B [12] IO_B [13] IO_B [14] IO_B [15] IO_B [16] IO_B [17] IO_B [18] IO_B [19] IO_B [20] IO_B [21] IO_B [22] IO_B [23] IO_B [24] IO_B [25] IO_B [26] IO_B [27] IO_B [28] IO_B [29] IO_B [30] IO_B [31] GPIO_CLKINN1 GPIO_CLKINP1 GPIO_CLKOUTN1 GPIO_CLKOUTP1 PIN_G27 PIN_G28 PIN_H27 PIN_L24 PIN_H28 PIN_L25 PIN_K27 PIN_L28 PIN_K28 PIN_L27 PIN_K29 PIN_M25 PIN_K30 PIN_M24 PIN_L29 PIN_L30 PIN_P26 PIN_P28 PIN_P25 PIN_P27 PIN_M29 PIN_R26 PIN_M30 PIN_R27 PIN_P24 PIN_N28 PIN_P23 PIN_N29 PIN_R23 PIN_P29 PIN_R22 PIN_P30 PIN_AH14 PIN_AG15 PIN_AF27 PIN_AF28 GPIO Connection 1 IO[0] GPIO Connection 1 IO[1] GPIO Connection 1 IO[2] GPIO Connection 1 IO[3] GPIO Connection 1 IO[4] GPIO Connection 1 IO[5] GPIO Connection 1 IO[6] GPIO Connection 1 IO[7] GPIO Connection 1 IO[8] GPIO Connection 1 IO[9] GPIO Connection 1 IO[10] GPIO Connection 1 IO[11] GPIO Connection 1 IO[12] GPIO Connection 1 IO[13] GPIO Connection 1 IO[14] GPIO Connection 1 IO[15] GPIO Connection 1 IO[16] GPIO Connection 1 IO[17] GPIO Connection 1 IO[18] GPIO Connection 1 IO[19] GPIO Connection 1 IO[20] GPIO Connection 1 IO[21] GPIO Connection 1 IO[22] GPIO Connection 1 IO[23] GPIO Connection 1 IO[24] GPIO Connection 1 IO[25] GPIO Connection 1 IO[26] GPIO Connection 1 IO[27] GPIO Connection 1 IO[28] GPIO Connection 1 IO[29] GPIO Connection 1 IO[30] GPIO Connection 1 IO[31] GPIO Connection 1 PLL In GPIO Connection 1 PLL In GPIO Connection 1 PLL Out GPIO Connection 1 PLL Out Table 5. 44 . Pin assignments for the expansion headers.8.

During the data display interval the RGB data drives each pixel in turn across the row being displayed. Table 5.13.9] U10 48 47 46 45 44 43 42 41 40 39 38 37 VAA B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 CLOCK G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 BLANK SYNC ADV7123 VREF COMP IOR IOR IOG IOG VAA VAA IOB IOB GND GND 36 35 34 33 32 31 30 29 28 27 26 25 J7 VGA_R VGA_G VGA_B VGA_VCC33 R82 75 R83 75 R84 75 VGA_HS VGA_VS R85 R86 47 47 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 1 11 10 5 15 VGA 16 BC49 0.10 show. blue) data can be found on various educational web sites (for example.1u VGA_G0 VGA_G1 VGA_G2 VGA_G3 VGA_G4 VGA_G5 VGA_G6 VGA_G7 VGA_G8 VGA_G9 VGA_BLANK_n VGA_SYNC_n 1 2 3 4 5 6 7 8 9 10 11 12 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 PSAV E RSET VGA_R[0. and the Analog Devices ADV7123 triple 10-bit high-speed video DAC is used to produce the analog data signals (red.1u BC48 0. The VGA synchronization signals are provided directly from the Cyclone II FPGA. The associated schematic is given in Figure 5. The timing of the vertical synchronization (vsync) is the same as shown in Figure 5. Finally.12 and can support resolutions of up to 1600 x 1200 pixels. Figure 5.1u VGA_VCC33 The timing specification for VGA synchronization and RGB (red. which is followed by the display interval (c). c.12. search for “VGA signal timing”). and blue). except that a vsync pulse signifies the end of one frame and the start of the next. VGA_B0 VGA_B1 VGA_B2 VGA_B3 VGA_B4 VGA_B5 VGA_B6 VGA_B7 VGA_B8 VGA_B9 VGA_CLOCK Figure 5. green. VGA_R9 VGA_R8 VGA_R7 VGA_R6 VGA_R5 VGA_R4 VGA_R3 VGA_R2 VGA_R1 VGA_R0 VGA_VCC33 R80 R81 RSET 4.9] VGA_G[0. green.13 illustrates the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor.7 Using VGA The DE2-70 board includes a 16-pin D-SUB connector for VGA output. b.9] VGA_B[0. and the data refers to the set of rows in the frame (horizontal timing). An active-low pulse of specific duration (time a in the figure) is applied to the horizontal synchronization (hsync) input of the monitor. VGA circuit schematic.7K 560 BC47 0... and d for both horizontal and vertical timing. the durations of time periods a.. The data (RGB) inputs on the monitor must be off (driven to 0 V) for a time period called the back porch (b) after the hsync pulse occurs. there is a time period called the front porch (d) where the RGB signals must again be off before the next hsync pulse can occur. for different resolutions.DE2-70 User Manual 5. which signifies the end of one row of data and the start of the next. 45 17 .9 and 5. at 100 MHz.

10.9 2.9 d(us) 0. VGA vertical timing specification. Figure 5. An example of code that drives a VGA display is described in Sections 6. VGA mode Configuration VGA(60Hz) VGA(85Hz) SVGA(60Hz) SVGA(75Hz) SVGA(85Hz) XGA(60Hz) XGA(70Hz) XGA(85Hz) 1280x1024(60Hz) Resolution (HxV) 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280x1024 a(lines) 2 3 4 3 3 6 6 3 3 Vertical Timing Spec b(lines) 33 25 23 21 27 29 29 36 38 c(lines) 480 480 600 600 600 768 768 768 1024 d(lines) 10 1 1 1 1 3 3 1 1 Table 5.6 0.11.6 1 0.2 2. or in the Datasheet/VGA DAC folder on the DE2-70 System CD-ROM.3 and 6.8 1.3 0.2 14.7 10.3 0.8 20 16.6 3. VGA mode Configuration VGA(60Hz) VGA(85Hz) SVGA(60Hz) SVGA(75Hz) SVGA(85Hz) XGA(60Hz) XGA(70Hz) XGA(85Hz) 1280x1024(60Hz) Resolution(HxV) 640x480 640x480 800x600 800x600 800x600 1024x768 1024x768 1024x768 1280x1024 a(us) 3.6 1.2 1.2. 6.4 0.1 2. 46 .0 Horizontal Timing Spec b(us) 1.5 0. which can be found on the manufacturer’s web site.9.7 2.2 2.6 1.4 Pixel clock(Mhz) 25 36 40 49 56 65 75 95 108 (640/c) (640/c) (800/c) (800/c) (800/c) (1024/c) (1024/c) (1024/c) (1280/c) Table 5.8 11.2 15.4.2 3.4 17. VGA horizontal timing specification.3 c(us) 25.5 1.DE2-70 User Manual Detailed information for using the ADV7123 video DAC is available in its datasheet.9 2. The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 5.2 2. VGA horizontal timing specification.0 1.1 1.8 13.8 1.13.

PIN_D23 PIN_E23 PIN_E22 PIN_D22 PIN_H21 PIN_G21 PIN_H20 PIN_F20 PIN_E20 PIN_G20 PIN_A10 PIN_B11 PIN_A11 PIN_C12 PIN_B12 PIN_A12 PIN_C13 PIN_B13 PIN_B14 PIN_A14 PIN_B16 PIN_C16 PIN_A17 PIN_B17 PIN_C18 PIN_B18 PIN_B19 PIN_A19 PIN_C19 PIN_D19 PIN_D24 PIN_C15 PIN_J19 PIN_H19 PIN_B15 Description VGA Red[0] VGA Red[1] VGA Red[2] VGA Red[3] VGA Red[4] VGA Red[5] VGA Red[6] VGA Red[7] VGA Red[8] VGA Red[9] VGA Green[0] VGA Green[1] VGA Green[2] VGA Green[3] VGA Green[4] VGA Green[5] VGA Green[6] VGA Green[7] VGA Green[8] VGA Green[9] VGA Blue[0] VGA Blue[1] VGA Blue[2] VGA Blue[3] VGA Blue[4] VGA Blue[5] VGA Blue[6] VGA Blue[7] VGA Blue[8] VGA Blue[9] VGA Clock VGA BLANK VGA H_SYNC VGA V_SYNC VGA SYNC Table 5.11. ADV7123 pin assignments. 47 .DE2-70 User Manual Signal Name VGA_R[0] VGA_R[1] VGA_R[2] VGA_R[3] VGA_R[4] VGA_R[5] VGA_R[6] VGA_R[7] VGA_R[8] VGA_R[9] VGA_G[0] VGA_G[1] VGA_G[2] VGA_G[3] VGA_G[4] VGA_G[5] VGA_G[6] VGA_G[7] VGA_G[8] VGA_G[9] VGA_B[0] VGA_B[1] VGA_B[2] VGA_B[3] VGA_B[4] VGA_B[5] VGA_B[6] VGA_B[7] VGA_B[8] VGA_B[9] VGA_CLK VGA_BLANK_N VGA_HS VGA_VS VGA_SYNC FPGA Pin No.

12.12. and line-out ports.7K R102 4.DE2-70 User Manual 5. Audio CODEC pin assignments. or in the Datasheet/Audio CODEC folder on the DE2-70 System CD-ROM.8 Using the 24-bit Audio CODEC The DE2-70 board provides high-quality 24-bit audio via the Wolfson WM8731 audio CODEC ( udio l/DECoder). line-in. PIN_F19 PIN_E19 PIN_G18 PIN_F18 PIN_D17 PIN_E17 PIN_J18 PIN_H18 Description Audio CODEC ADC LR Clock Audio CODEC ADC Data Audio CODEC DAC LR Clock Audio CODEC DAC Data Audio CODEC Chip Clock Audio CODEC Bit-Stream Clock I2C Data I2C Clock Table 5. Detailed information for using the WM8731 codec is available in its datasheet. The WM8731 is controlled by a serial I2C bus interface. Signal Name AUD_ADCLRCK AUD_ADCDAT AUD_DACLRCK AUD_DACDAT AUD_XCK AUD_BCLK I2C_SCLK I2C_SDAT FPGA Pin No.7K 4. A schematic diagram of the audio circuitry is shown in Figure 5.14.7K AGND R108 2K I2C_SDAT I2C_SCLK R109 2K AGND R103 330 AGND MIC IN I2C ADDRESS READ IS 0x34 I2C ADDRESS WRITE IS 0x35 A_VCC33 28 27 26 25 24 23 22 C40 1u NCL R NCR L GND J12 LINE OUT 5 2 4 1 3 NCL R NCR L GND 5 2 4 1 3 5 2 4 1 3 PHONE JACK B U13 PHONE JACK P SCLK SDIN CSB MODE LLINEIN RLINEIN MICIN AGND 1 2 3 4 5 6 7 EXPOSED DACDAT DACLRCK ADCD AT ADCLRCK HPVDD LHPOUT RHPOUT XTI/MCLK XTO DCVDD DGND DBVDD CLKOUT BCLK WM8731 MBIAS VMID AGND AVDD ROUT LOUT HPGND 21 20 19 18 17 16 15 R104 C41 10u AGND A_VCC33 680 C42 1n R105 AGND 47K AGND AGND AGND PHONE JACK G AUD_XCK AUD_BCLK AUD_DACDAT AUD_DACLRCK AUD_ADCD AT AUD_ADCLRCK AGND 29 8 9 10 11 12 13 14 C43 100u C44 100u A_VCC33 R106 47K R107 47K AGND AGND AGND Figure 5. and the FPGA pin assignments are listed in Table 5. 48 .7K NCL R NCR L GND J10 VCC33 VCC33 R101 4. with a sample rate adjustable from 8 kHz to 96 kHz. This chip supports microphone-in.14. Audio CODEC schematic. which is connected to pins on the Cyclone II FPGA. which can be found on the manufacturer’s web site. J11 LINE IN C38 1u C39 1u R99 R100 4.

or in the Datasheet/RS232 folder on the DE2-70 System CD-ROM. Instructions for using a PS/2 mouse or keyboard can be found by performing an appropriate search on various educational web sites. PIN_D21 PIN_E21 PIN_G22 PIN_F23 Description UART Receiver UART Transmitter UART Clear to Send UART Request to Send Table 5. users can use the PS/2 keyboard and mouse on the DE2-70 board simultaneously by an plug an extension PS/2 Y-Cable.15. RS-232 pin assignments.14.1u RS232 C10 VCC33 1u C+ ADM3202 C1C2+ VCC C2GND V+ V- 16 15 VCC33 BC33 0. Figure 5. MAX232 (RS-232) chip schematic.16 shows the schematic of the PS/2 circuit.DE2-70 User Manual 5. Figure 5.10 PS/2 Serial Port The DE2-70 board includes a standard PS/2 interface and a connector for a PS/2 keyboard or mouse. The pin assignments for the associated interface are shown in Table 5.13 lists the Cyclone II FPGA pin assignments.15 shows the related schematics. which is available on the manufacturer’s web site. 49 .1u C11 1u Figure 5. RXD R44 VCC33 R45 330 330 TXD LEDR UART_RXD J2 LEDG UART_TXD U7 UART_RXD UART_RTS UART_TXD UART_CTS C9 1u 12 9 11 10 1 3 4 5 2 6 C12 1u R1OUT R2OUT T1IN T2IN R1IN R2IN T1OUT T2OUT 13 8 14 7 RXD RTS TXD CTS 5 9 4 8 3 7 2 6 1 10 11 BC32 0. 5.13. In addition. and Table 5. For detailed information on how to use the transceiver refer to the datasheet. Signal Name UART_RXD UART_TXD UART_CTS UART_RTS FPGA Pin No.9 RS-232 Serial Port The DE2-70 board uses the ADM3202 transceiver chip and a 9-pin D-SUB connector for RS-232 communications.

PS/2 pin assignments.11 Fast Ethernet Network Controller The DE2-70 board provides Ethernet support via the Davicom DM9000A Fast Ethernet controller chip. Signal Name PS2_KBCLK PS2_KBDAT PS2_MSCLK PS2_MSDAT FPGA Pin No.1u Figure 5.DE2-70 User Manual VCC5 VCC5 VCC5 VCC5 R46 2K PS2_KBDAT PS2_KBCLK PS2_MSDAT PS2_MSCLK R48 R49 R174 R175 120 120 120 120 R47 2K R172 2K R173 2K KBDAT MSDAT KBCLK MSCLK J3 TOP VCC5 D96 BAT54S BC34 1 2 3 5 6 8 8 5 2 1 6 3 3 3 3 D9 BAT54S D10 BAT54S D95 BAT54S 3 BC35 VCC33 VCC33 VCC33 VCC33 0. 16 Kbytes SRAM. PS/2 schematic. Figure 5. For detailed information on how to use the DM9000A refer to its datasheet and application note. which are available on the manufacturer’s web site. The DM9000A includes a general processor interface.16.17 shows the schematic for the Fast Ethernet interface. a media access control (MAC) unit. 50 9 10 11 1 2 1 2 1 2 1 2 PS2 . or in the Datasheet/Ethernet folder on the DE2-70 System CD-ROM. PIN_F24 PIN_E24 PIN_D26 PIN_D25 Description PS/2 Clock PS/2 Data PS/2 Clock (reserved for second PS/2 device) PS/2 Data(reserved for second PS/2 device) Table 5. and a 10/100M PHY transceiver.1u 0.14. 5.15. and the associated pin assignments are listed in Table 5.

17. 1 = Data 51 13 14 15 16 17 18 19 20 21 22 23 24 SD4 SD3 GND SD2 SD1 SD0 EEDIO EEDCK EEDCS WAKE/SD15 VDD LED3/SD14 .9 R76 49.9 R75 49. PIN_A23 PIN_C22 PIN_B22 PIN_A22 PIN_B21 PIN_A21 PIN_B20 PIN_A20 PIN_B26 PIN_A26 PIN_B25 PIN_A25 PIN_C24 PIN_B24 PIN_A24 PIN_B23 PIN_D27 PIN_B27 Fast Ethernet schematic.9 R74 49.8K U9 48 47 46 45 44 43 42 41 40 39 38 37 BGGND RXGND SD GND X1 X2 VDD TEST PWRST# LED1 LED2 CS# N_VCC33 R71 4.9 GREEN 1 2 3 4 5 6 7 8 9 10 11 12 BGRES RXVDD25 RX+ RXRXGND TXGND TX+ TXTXVDD25 SD7 SD6 SD5 t DM9000A-8/16bi DM9000AE IOW# IOR# INT GND CMD GP1/SD8 VDD GP2/SD9 GP3/SD10 GP4/SD11 GP5/SD12 GP6/SD13 36 35 34 33 32 31 30 29 28 27 26 25 ENET_IOW_n ENET_IOR_n ENET_INT ENET_CMD ENET_D8 ENET_D9 ENET_D10 ENET_D11 ENET_D12 ENET_D13 N_VCC33 15 14 13 RJ45INTLED 16 CHSGND C18 0.1u BC37 0.1u R70 6.1u NGND R77 R78 120 120 SPEED ACT ENET_D14 ENET_D15 ENET_D0 ENET_D1 ENET_D2 ENET_D3 ENET_D4 ENET_D5 ENET_D6 ENET_D7 N_VCC33 Figure 5.15] 10u BC36 0. 0 = Command. Signal Name ENET_DATA[0] ENET_DATA[1] ENET_DATA[2] ENET_DATA[3] ENET_DATA[4] ENET_DATA[5] ENET_DATA[6] ENET_DATA[7] ENET_DATA[8] ENET_DATA[9] ENET_DATA[10] ENET_DATA[11] ENET_DATA[12] ENET_DATA[13] ENET_DATA[14] ENET_DATA[15] ENET_CLK ENET_CMD FPGA Pin No.7K J6 11 12 10 9 D3 D4 YELLOW D2 D1 N_VCC25 L2 MNT1 MNT0 N_VCC33 SMNT1 SMNT0 TD+ TDCTT CTR RD+ RDCHSG 1 2 4 5 3 6 8 CHSGND BEAD RX+ RXNGND TX+ TX- N_VCC25 N_VCC33 R73 49.DE2-70 User Manual N_VCC33 R72 N_VCC33 4.7K 25MHZ ENET_RESET_n SPEED ACT ENET_CS_n NGND L1 BEAD C17 ENET_D[0. Description DM9000A DATA[0] DM9000A DATA[1] DM9000A DATA[2] DM9000A DATA[3] DM9000A DATA[4] DM9000A DATA[5] DM9000A DATA[6] DM9000A DATA[7] DM9000A DATA[8] DM9000A DATA[9] DM9000A DATA[10] DM9000A DATA[11] DM9000A DATA[12] DM9000A DATA[13] DM9000A DATA[14] DM9000A DATA[15] DM9000A Clock 25 MHz DM9000A Command/Data Select.1u NGND C19 0..

and SECAM) into 4:2:2 component video data compatible with the 8-bit ITU-R BT. which is connected to the Cyclone II FPGA as indicated in Figure 5.18. broadcast sources. or in the Datasheet/TV Decoder folder on the DE2-70 System CD-ROM. including DVD players.15. 52 . The pin assignments are listed in Table 5. The ADV7180 is compatible with a broad range of video devices. Detailed information on the ADV7180 is available on the manufacturer’s web site. Fast Ethernet pin assignments.DE2-70 User Manual ENET_CS_N ENET_INT ENET_IOR_N ENET_IOW_N ENET_RESET_N PIN_C28 PIN_C27 PIN_A28 PIN_B28 PIN_B29 DM9000A Chip Select DM9000A Interrupt DM9000A Read DM9000A Write DM9000A Reset Table 5. 5.16.12 TV Decoder The DE2-70 board is equipped with two Analog Devices ADV7180 TV decoder chips. Note that the I2C address of the TV decoder 1(U11) and TV decoder 2(U12) are 0x40 and 0x42 respectively. The registers in both of the TV decoders can be programmed by a serial I2C bus. PAL. tape-based sources. The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal (NTSC.656 interface standard. and security/surveillance cameras.

18.DE2-70 User Manual V_VCC33 VGND 2 1 V_VCC33 V_VCC18 AV1_VCC18 D83 BAT54S PV1_VCC18 C31 14 36 27 20 1 4 U11 C26 0.74K 47 16 15 14 13 12 11 10 9 120 120 TD1_D0 TD1_D1 TD1_D2 TD1_D3 TD1_D4 TD1_D5 TD1_D6 TD1_D7 TD1_VS TD1_HS TD1_D[0.1u 0.1u 0. Signal Name TD1_D[0] TD1_D[1] TD1_D[2] TD1_D[3] TD1_D[4] TD1_D[5] TD1_D[6] TD1_D[7] TD1_HS TD1_VS FPGA Pin No.1u R96 1. Description TV Decoder 1 Data[0] TV Decoder 1 Data[1] TV Decoder 1 Data[2] TV Decoder 1 Data[3] TV Decoder 1 Data[4] TV Decoder 1 Data[5] TV Decoder 1 Data[6] TV Decoder 1 Data[7] TV Decoder 1 H_SYNC TV Decoder 1 V_SYNC 53 3 15 35 40 41 21 24 28 VGND .1u R91 1...7] DVDD DVDD J8 R89 R90 VGND 36 39 23 29 30 TD1_RESET_n C27 C29 0.7] DVDD DVDD R94 36 AIN1 AIN2 AIN3 RESET VREFN VREFP XTAL XTAL1 ALSB ADV7180 28MHZ I2C ADDRESS IS 0x42 V_VCC33 32 18 DVDDIO DVDDIO AVDD PVDD PWRDWN SCLK SDATA DGND DGND DGND DGND EXPOSED AGND AGND AGND TD2_CLK27 I2C_SCLK 34 I2C_SDAT 33 Figure 5.74K TD2_D[0.1u 23 29 30 31 26 27 20 1 4 C36 10n ELPF P0 P1 P2 P3 P4 P5 P6 P7 VS/FIELD HS SFL INTRQ LLC TEST_0 19 17 16 10 9 8 7 6 5 37 39 2 38 11 22 RN45 1 2 3 4 5 6 7 8 R97 R98 47 16 15 14 13 12 11 10 9 120 120 TD2_D0 TD2_D1 TD2_D2 TD2_D3 TD2_D4 TD2_D5 TD2_D6 TD2_D7 TD2_VS TD2_HS 0. PIN_A6 PIN_B6 PIN_A5 PIN_B5 PIN_B4 PIN_C4 PIN_A3 PIN_B3 PIN_E13 PIN_E14 TV Decoder schematic.1u C28 0.1u 25 13 12 AV2_VCC18 PV2_VCC18 C37 14 36 U12 C32 0.1u C34 0.1u 25 13 12 31 26 AIN1 AIN2 AIN3 RESET VREFN VREFP XTAL XTAL1 ALSB ADV7180 28MHZ I2C ADDRESS IS 0x40 V_VCC33 I2C_SCLK I2C_SDAT 32 18 34 33 DVDDIO DVDDIO AVDD PVDD 3 PWRDWN SCLK SDATA DGND DGND DGND DGND EXPOSED AGND AGND AGND TD1_CLK27 V_VCC33 VGND 2 1 3 15 35 40 41 21 24 28 VGND V_VCC33 V_VCC18 D84 BAT54S 3 J9 RCA JACK R95 VGND 39 TD2_RESET_n C33 C35 0.1u C30 10n ELPF P0 P1 P2 P3 P4 P5 P6 P7 VS/FIELD HS SFL INTRQ LLC TEST_0 19 17 16 10 9 8 7 6 5 37 39 2 38 11 22 RN44 1 2 3 4 5 6 7 8 R92 R93 0.

cos + V.DE2-70 User Manual TD1_CLK27 TD1_RESET_N TD2_D[0] TD2_D[1] TD2_D[2] TD2_D[3] TD2_D[4] TD2_D[5] TD2_D[6] TD2_D[7] TD2_HS TD2_VS TD2_CLK27 TD2_RESET_N I2C_SCLK I2C_SDAT PIN_G15 PIN_D14 PIN_C10 PIN_A9 PIN_B9 PIN_C9 PIN_A8 PIN_B8 PIN_A7 PIN_B7 PIN_E15 PIN_D15 PIN_H15 PIN_B10 PIN_J18 PIN_H18 TV Decoder 1 Clock Input.16. 54 . TV Encoder Block (Cyclone II 2C70) Clock Timing Y U V SIN COS Tables Sync Gen DSP Block (Calculate Composite) DSP Block S-Video (Y/C) 10-bit VGA DAC O (Composite) = Y + U. the ADV7123 (10-bit high-speed triple ADCs) can be used to implement a professional-quality TV encoder with the digital processing part implemented in the Cyclone II FPGA.sin DAC or Y (S-Video) 10-bit or RCA_Y C = U.cos + V. TV Decoder 1 Reset TV Decoder 2 Data[0] TV Decoder 2 Data[1] TV Decoder 2 Data[2] TV Decoder 2 Data[3] TV Decoder 2 Data[4] TV Decoder 2 Data[5] TV Decoder 2 Data[6] TV Decoder 2 Data[7] TV Decoder 2 H_SYNC TV Decoder 2 V_SYNC TV Decoder 2 Clock Input.sin (S-Video) DAC or RCA_Pb 10-bit RCA_Pr 10-bit DAC Figure 5. A TV Encoder that uses the Cyclone II FPGA and the ADV7123.19. Figure 5. TV Decoder pin assignments. 5.19 shows a block diagram of a TV encoder implemented in this manner.13 Implementing a TV Encoder Although the DE2-70 board does not include a TV encoder chip. TV Decoder 2 Reset I2C Data I2C Clock Table 5.

20. H_VCC5 U_VCC33 2 1 H_VCC5 2 D85 1 D86 BAT54S 3 J13 1 2 3 4 C48 47p C49 USB A-TYPE 6 BC66 0. 2.7K 4.1u 57 37 27 19 9 1 51 USB B-TYPE 6 5 12MHZ R126 22 C54 47p Figure 5.7K OTG_CS_n OTG_WE_n OTG_OE_n OTG_INT1 OTG_INT0 OTG_RESET_n OTG_DREQ1 OTG_DACK1_n OTG_DREQ0 OTG_DACK0_n 62 61 18 17 16 15 13 12 11 10 8 7 6 5 3 2 64 63 21 22 20 31 30 32 25 29 24 28 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CS WR RD INT2 INT1 RESET DREQ2 DACK2 DREQ1 DACK1 H_SUSPEND/H_SUSWKUP H_SUSPEND/D_SUSWKUP VDD_5V H_OC2 H_PSW2 H_DM2 H_DP2 H_OC1 H_PSW1 OTG_DM1 OTG_DP1 ISP1362 ID OTGMODE VBUS CP_CAP2 CP_CAP1 GL TEST2 TEST1 TEST0 CLKOUT X1 X2 DGND DGND DGND DGND DGND DGND AGND 47p R112 R113 22 22 R114 R115 15K R116 R117 22 22 15K U_VCC33 O_VCC5 2 1 O_VCC5 2 D87 BAT54S 1 D88 BAT54S 3 J14 3 2 43 44 OTG_FSPEED OTG_LSPEED R124 R125 1.1u 5 DD+ GND OTG_D[0.14 Using USB Host and Device The DE2-70 board provides both USB host and device interfaces using the Philips ISP1362 single-chip USB controller. Two complete examples of USB drivers.1u GOOD 330 10K 10K 100K LEDB U_VCC33 U_VCC33 U_VCC33 U_VCC5 BEAD H_VCC5 VCC VCC VCC VCC VCC VCC BAT54S 3 OTG_A1 OTG_A0 OTG_D15 OTG_D14 OTG_D13 OTG_D12 OTG_D11 OTG_D10 OTG_D9 OTG_D8 OTG_D7 OTG_D6 OTG_D5 OTG_D4 OTG_D3 OTG_D2 OTG_D1 OTG_D0 R111 4. or in the Datasheet/USB folder on the DE2-70 System CD-ROM. Detailed information for using the ISP1362 device is available in its datasheet and programming guide.15] U14 58 52 40 26 14 4 U_VCC5 L10 33 34 56 41 36 46 47 42 35 49 50 48 45 55 54 53 39 60 59 23 38 R118 R119 C50 R120 R121 R122 R123 4. can be found in Sections 6.5K L11 BEAD O_VCC5 3 1 4 VBUS C52 47p C53 47p BC68 0. for both host and device applications.7K 0. the pin assignments for the associated interface are listed in Table 5.DE2-70 User Manual 5. The most challenging part of a USB application is in the design of the software driver needed.5K 1.. 55 .5. Figure 5.5 Mbit/s). supporting data transfer at full-speed (12 Mbit/s) and low-speed (1. both documents can be found on the manufacturer’s web site. The host and device controllers are compliant with the Universal Serial Bus Specification Rev.17.20 shows the schematic diagram of the USB circuitry. USB (ISP1362) host and device schematic.4 and 6.0. These demonstrations provide examples of software drivers for the Nios II processor.

Z = Disable USB Low Speed. PIN_E9 PIN_D8 PIN_H10 PIN_G9 PIN_G11 PIN_F11 PIN_J12 PIN_H12 PIN_H13 PIN_G13 PIN_D4 PIN_D5 PIN_D6 PIN_E7 PIN_D7 PIN_E8 PIN_D9 PIN_G10 PIN_E10 PIN_D10 PIN_E11 PIN_H14 PIN_F13 PIN_J13 PIN_D12 PIN_E12 PIN_G12 PIN_F12 PIN_F7 PIN_F8 Description ISP1362 Address[0] ISP1362 Address[1] ISP1362 Data[0] ISP1362 Data[1] ISP1362 Data[2] ISP1362 Data[3] ISP1362 Data[4] ISP1362 Data[5] ISP1362 Data[6] ISP1362 Data[7] ISP1362 Data[8] ISP1362 Data[9] ISP1362 Data[10] ISP1362 Data[11] ISP1362 Data[12] ISP1362 Data[13] ISP1362 Data[14] ISP1362 Data[15] ISP1362 Chip Select ISP1362 Read ISP1362 Write ISP1362 Reset ISP1362 Interrupt 0 ISP1362 Interrupt 1 ISP1362 DMA Acknowledge 0 ISP1362 DMA Acknowledge 1 ISP1362 DMA Request 0 ISP1362 DMA Request 1 USB Full Speed. Z = Disable Table 5. USB (ISP1362) pin assignments. 0 = Enable. 0 = Enable.17.DE2-70 User Manual Signal Name OTG_A[0] OTG_A[1] OTG_D[0] OTG_D[1] OTG_D[2] OTG_D[3] OTG_D[4] OTG_D[5] OTG_D[6] OTG_D[7] OTG_D[8] OTG_D[9] OTG_D[10] OTG_D[11] OTG_D[12] OTG_D[13] OTG_D[14] OTG_D[15] OTG_CS_N OTG_OE_N OTG_WE_N OTG_RESET_N OTG_INT0 OTG_INT1 OTG_DACK0_N OTG_DACK1_N OTG_DREQ0 OTG_DREQ1 OTG_FSPEED OTG_LSPEED FPGA Pin No. 56 .

21 shows the schematic of the IrDA communication link.2 Kbit/s and both the TX and RX sides have to use the same transmission rate.18.18.com/webseminars/documents/IrDA_BW.21. Figure 5. PIN_W21 PIN_W22 Description IRDA Transmitter IRDA Receiver Table 5. U6 VCC33 IRDA_RXD IRDA_TXD VCC33 R41 R42 R43 120 120 47 1 2 3 4 5 6 7 8 9 GND NC VCC AGND SD RXD TXD LEDA SHIELD IrDA Figure 5. Signal Name IRDA_TXD IRDA_RXD FPGA Pin No. IrDA pin assignments.DE2-70 User Manual 5. IrDA schematic.pdf The pin assignments of the associated interface are listed in Table 5.15 Using IrDA The DE2-70 board provides a simple wireless communication media using the Agilent HSDL-3201 low power infrared transceiver. The datasheet for this device is provided in the Datasheet\IrDA folder on the DE2-70 System CD-ROM. Note that the highest transmission rate supported is 115.microchip. 57 . Please refer to the following website for detailed information on how to send and receive data using the IrDA link: http://techtrain.

5.7K DRAM1_CS_n 4.7K DRAM1_RAS_n 4. DRAM_D[0.20. SDRAM schematic.7K DRAM1_WE_n 4.16 Using SDRAM/SRAM/Flash The DE2-70 board provides a 2-Mbyte SSRAM.24 show the schematics of the memory chips.19. 5. and 5.12] DRAM1_A[0.7K DRAM0_RAS_n 4.7K DRAM0_CAS_n 4..31] DRAM0_A[0.21. 58 6 12 46 52 28 41 54 VSSQ VSSQ VSSQ VSSQ VSS VSS VSS . and two 32-Mbyte SDRAM chips.7K DRAM1_CKE R1 R2 R3 R4 R5 Figure 5.DE2-70 User Manual 5.23.7K DRAM0_CS_n 4.22..7K DRAM1_CAS_n 4.22. The datasheets for the memory chips are provided in the Datasheet/Memory folder on the DE2-70 System CD-ROM.7K DRAM0_CKE R7 R8 R9 R10 R11 SDRAM1 4. and 5. The pin assignments for each device are listed in Tables 5.7K DRAM0_WE_n 4. 8-Mbyte Flash memory. Figures 5..12] DR_VCC33 DR_VCC33 1 14 27 3 9 43 49 1 14 27 U1 U2 VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDD VDD VDD DRAM0_A0 DRAM0_A1 DRAM0_A2 DRAM0_A3 DRAM0_A4 DRAM0_A5 DRAM0_A6 DRAM0_A7 DRAM0_A8 DRAM0_A9 DRAM0_A10 DRAM0_A11 DRAM0_A12 DRAM0_CLK DRAM0_CKE DRAM0_LDQM0 DRAM0_UDQM1 DRAM0_WE_n DRAM0_CAS_n DRAM0_RAS_n DRAM0_CS_n DRAM0_BA0 DRAM0_BA1 23 24 25 26 29 30 31 32 33 34 22 35 36 38 37 15 39 16 17 18 19 20 21 A0 D0 D1 A1 A2 D2 A3 D3 A4 D4 A5 D5 A6 D6 A7 D7 A8 D8 A9 D9 A10 D10 A11 D11 SDRAM 16Mx16 A12 D12 CLK D13 CKE D14 LDQM D15 UDQM nW E nCAS nRAS nCS BA0 BA1 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 DRAM_D0 DRAM_D1 DRAM_D2 DRAM_D3 DRAM_D4 DRAM_D5 DRAM_D6 DRAM_D7 DRAM_D8 DRAM_D9 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D13 DRAM_D14 DRAM_D15 DRAM1_A0 DRAM1_A1 DRAM1_A2 DRAM1_A3 DRAM1_A4 DRAM1_A5 DRAM1_A6 DRAM1_A7 DRAM1_A8 DRAM1_A9 DRAM1_A10 DRAM1_A11 DRAM1_A12 DRAM1_CLK DRAM1_CKE DRAM1_LDQM0 DRAM1_UDQM1 DRAM1_WE_n DRAM1_CAS_n DRAM1_RAS_n DRAM1_CS_n DRAM1_BA0 DRAM1_BA1 VDDQ VDDQ VDDQ VDDQ 3 9 43 49 23 24 25 26 29 30 31 32 33 34 22 35 36 38 37 15 39 16 17 18 19 20 21 A0 D0 A1 D1 A2 D2 A3 D3 A4 D4 A5 D5 A6 D6 A7 D7 A8 D8 A9 D9 A10 D10 A11 D11 SDRAM 16Mx16 A12 D12 CLK D13 CKE D14 LDQM D15 UDQM nWE nCAS nRAS nCS BA0 BA1 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 DRAM_D16 DRAM_D17 DRAM_D18 DRAM_D19 DRAM_D20 DRAM_D21 DRAM_D22 DRAM_D23 DRAM_D24 DRAM_D25 DRAM_D26 DRAM_D27 DRAM_D28 DRAM_D29 DRAM_D30 DRAM_D31 VSSQ VSSQ VSSQ VSSQ VSS VSS VSS 6 12 46 52 28 41 54 SDRAM0 DR_VCC33 DR_VCC33 4.

7K FLASH_RY FLASH_CE_n WE# RESET# WP#ACC RY/BY# CE# OE# BYTE# RFU0 RFU1 RFU2 VSS VSS 27 28 30 33 52 Figure 5.3] SR_VCC33 SR_VCC33 15 41 65 91 VDD VDD VDD VDD U3 SRAM_addr0 SRAM_addr1 SRAM_addr2 SRAM_addr3 SRAM_addr4 SRAM_addr5 SRAM_addr6 SRAM_addr7 SRAM_addr8 SRAM_addr9 SRAM_addr10 SRAM_addr11 SRAM_addr12 SRAM_addr13 SRAM_addr14 SRAM_addr15 SRAM_addr16 SRAM_addr17 SRAM_addr18 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 4 11 20 27 54 61 70 77 37 36 35 34 33 32 44 45 46 47 48 49 50 81 82 99 100 43 42 39 38 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 NC/A19 NC/A20 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQPA DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQPB 52 53 56 57 58 59 62 63 51 68 69 72 73 74 75 78 79 80 2 3 6 7 8 9 12 13 1 18 19 22 23 24 25 28 29 30 SRAM_data0 SRAM_data1 SRAM_data2 SRAM_data3 SRAM_data4 SRAM_data5 SRAM_data6 SRAM_data7 SRAM_datapar0 SRAM_data8 SRAM_data9 SRAM_data10 SRAM_data11 SRAM_data12 SRAM_data13 SRAM_data14 SRAM_data15 SRAM_datapar1 SRAM_data16 SRAM_data17 SRAM_data18 SRAM_data19 SRAM_data20 SRAM_data21 SRAM_data22 SRAM_data23 SRAM_datapar2 SRAM_data24 SRAM_data25 SRAM_data26 SRAM_data27 SRAM_data28 SRAM_data29 SRAM_data30 SRAM_data31 SRAM_datapar3 SSRAM 512Kx36 IS61LPS51236A-200TQLI SRAM_MODE 31 SRAM_ZZ 64 SRAM_outen_n 86 SRAM_clock 89 SRAM_globalw_n 88 SRAM_writeen_n 87 SRAM_advance_n 83 SRAM_adsconttroler_n 85 SRAM_adsprocessor_n 84 SRAM_chipen1_n 98 SRAM_chipen2 97 SRAM_chipen3_n 92 SRAM_byteen_n0 93 SRAM_byteen_n1 94 SRAM_byteen_n2 95 SRAM_byteen_n3 96 MODE ZZ OE_n CLK GW_n BWE_n ADV_n ADSC_n ADSP_n CE1_n CE2 CE3_n BWA_n BWB_n BWC_n BWD_n DQC0 DQC1 DQC2 DQC3 DQC4 DQC5 DQC6 DQC7 DQPC DQD0 DQD1 DQD2 DQD3 DQD4 DQD5 DQD6 DQD7 DQPD 17 40 67 90 Figure 5.23. Flash schematic.18] SRAM_BE_n[0.7K 4.31] SRAM_DPA[0.14] FLASH_A[0.21] SSRAM schematic.24...... 59 .DE2-70 User Manual SRAM_DQ[0. FLASH_D[0.3] SRAM_A[0.. 5 10 21 26 55 60 71 76 F_VCC33 VIO VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 29 43 35 37 39 41 44 46 48 50 36 38 40 42 45 47 49 51 U5 FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 31 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 54 19 18 11 12 15 2 1 56 55 13 14 16 17 32 34 53 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15_A-1 FLASH 8Mx8 FLASH_WE_n FLASH_RESET_n FLASH_WP_n FLASH_RY FLASH_CE_n FLASH_OE_n FLASH_BYTE_n F_VCC33 R32 R33 4.

DE2-70 User Manual

Signal Name DRAM0_A[0] DRAM0_A[1] DRAM0_A[2] DRAM0_A[3] DRAM0_A[4] DRAM0_A[5] DRAM0_A[6] DRAM0_A[7] DRAM0_A[8] DRAM0_A[9] DRAM0_A[10] DRAM0_A[11] DRAM0_A[12] DRAM_D[0] DRAM0_D[1] DRAM_D[2] DRAM_D[3] DRAM_D[4] DRAM_D[5] DRAM_D[6] DRAM_D[7] DRAM_D[8] DRAM_D[9] DRAM_D[10] DRAM_D[11] DRAM_D[12] DRAM_D[13] DRAM_D[14] DRAM_D[15] DRAM0_BA_0 DRAM0_BA_1 DRAM0_LDQM0 DRAM0_UDQM1 DRAM0_RAS_N DRAM0_CAS_N

FPGA Pin No. PIN_AA4 PIN_AA5 PIN_AA6 PIN_AB5 PIN_AB7 PIN_AC4 PIN_AC5 PIN_AC6 PIN_AD4 PIN_AC7 PIN_Y8 PIN_AE4 PIN_AF4 PIN_AC1 PIN_AC2 PIN_AC3 PIN_AD1 PIN_AD2 PIN_AD3 PIN_AE1 PIN_AE2 PIN_AE3 PIN_AF1 PIN_AF2 PIN_AF3 PIN_AG2 PIN_AG3 PIN_AH1 PIN_AH2 PIN_AA9 PIN_AA10 PIN_V9 PIN_AB6 PIN_Y9 PIN_W10

Description SDRAM 1 Address[0] SDRAM 1 Address[1] SDRAM 1 Address[2] SDRAM 1 Address[3] SDRAM 1 Address[4] SDRAM 1 Address[5] SDRAM 1 Address[6] SDRAM 1 Address[7] SDRAM 1 Address[8] SDRAM 1 Address[9] SDRAM 1 Address[10] SDRAM 1 Address[11] SDRAM 1 Address[12] SDRAM 1 Data[0] SDRAM 1 Data[1] SDRAM 1 Data[2] SDRAM 1 Data[3] SDRAM 1 Data[4] SDRAM 1 Data[5] SDRAM 1 Data[6] SDRAM 1 Data[7] SDRAM 1 Data[8] SDRAM 1 Data[9] SDRAM 1 Data[10] SDRAM 1 Data[11] SDRAM 1 Data[12] SDRAM 1 Data[13] SDRAM 1 Data[14] SDRAM 1 Data[15] SDRAM 1 Bank Address[0] SDRAM 1 Bank Address[1] SDRAM 1 Low-byte Data Mask SDRAM 1 High-byte Data Mask SDRAM 1 Row Address Strobe SDRAM 1 Column Address Strobe

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DE2-70 User Manual

DRAM0_CKE DRAM0_CLK DRAM0_WE_N DRAM0_CS_N DRAM1_A[0] DRAM1_A[1] DRAM1_A[2] DRAM1_A[3] DRAM1_A[4] DRAM1_A[5] DRAM1_A[6] DRAM1_A[7] DRAM1_A[8] DRAM1_A[9] DRAM1_A[10] DRAM1_A[11] DRAM1_A[12] DRAM_D[16] DRAM_D[17] DRAM_D[18] DRAM_D[19] DRAM_D[20] DRAM_D[21] DRAM_D[22] DRAM_D[23] DRAM_D[24] DRAM_D[25] DRAM_D[26] DRAM_D[27] DRAM_D[28] DRAM_D[29] DRAM_D[30] DRAM_D[31] DRAM1_BA_0 DRAM1_BA_1 DRAM1_LDQM0 DRAM1_UDQM1

PIN_AA8 PIN_AD6 PIN_W9 PIN_Y10 PIN_T5 PIN_T6 PIN_U4 PIN_U6 PIN_U7 PIN_V7 PIN_V8 PIN_W4 PIN_W7 PIN_W8 PIN_T4 PIN_Y4 PIN_Y7 PIN_U1 PIN_U2 PIN_U3 PIN_V2 PIN_V3 PIN_W1 PIN_W2 PIN_W3 PIN_Y1 PIN_Y2 PIN_Y3 PIN_AA1 PIN_AA2 PIN_AA3 PIN_AB1 PIN_AB2 PIN_T7 PIN_T8 PIN_M10 PIN_U8

SDRAM 1 Clock Enable SDRAM 1 Clock SDRAM 1 Write Enable SDRAM 1 Chip Select SDRAM 2 Address[0] SDRAM 2 Address[1] SDRAM 2 Address[2] SDRAM 2 Address[3] SDRAM 2 Address[4] SDRAM 2 Address[5] SDRAM 2 Address[6] SDRAM 2 Address[7] SDRAM 2 Address[8] SDRAM 2 Address[9] SDRAM 2 Address[10] SDRAM 2 Address[11] SDRAM 2 Address[12] SDRAM 2 Data[0] SDRAM 2 Data[1] SDRAM 2 Data[2] SDRAM 2 Data[3] SDRAM 2 Data[4] SDRAM 2 Data[5] SDRAM 2 Data[6] SDRAM 2 Data[7] SDRAM 2 Data[8] SDRAM 2 Data[9] SDRAM 2 Data[10] SDRAM 2 Data[11] SDRAM 2 Data[12] SDRAM 2 Data[13] SDRAM 2 Data[14] SDRAM 2 Data[15] SDRAM 2 Bank Address[0] SDRAM 2 Bank Address[1] SDRAM 2 Low-byte Data Mask SDRAM 2 High-byte Data Mask

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DE2-70 User Manual

DRAM1_RAS_N DRAM1_CAS_N DRAM1_CKE DRAM1_CLK DRAM1_WE_N DRAM1_CS_N

PIN_N9 PIN_N8 PIN_L10 PIN_G5 PIN_M9 PIN_P9

SDRAM 2 Row Address Strobe SDRAM 2 Column Address Strobe SDRAM 2 Clock Enable SDRAM 2 Clock SDRAM 2 Write Enable SDRAM 2 Chip Select

Table 5.19. SDRAM pin assignments.

Signal Name SRAM_A[0] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_DQ[0] SRAM_DQ[1] SRAM_DQ[2] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8]

FPGA Pin No. PIN_AG8 PIN_AF8 PIN_AH7 PIN_AG7 PIN_AG6 PIN_AG5 PIN_AE12 PIN_AG12 PIN_AD13 PIN_AE13 PIN_AF14 PIN_AG14 PIN_AE15 PIN_AF15 PIN_AC16 PIN_AF20 PIN_AG20 PIN_AE11 PIN_AF11 PIN_AH10 PIN_AJ10 PIN_AK10 PIN_AJ11 PIN_AK11 PIN_AH12 PIN_AJ12 PIN_AH16 PIN_AK17

Description SRAM Address[0] SRAM Address[1] SRAM Address[2] SRAM Address[3] SRAM Address[4] SRAM Address[5] SRAM Address[6] SRAM Address[7] SRAM Address[8] SRAM Address[9] SRAM Address[10] SRAM Address[11] SRAM Address[12] SRAM Address[13] SRAM Address[14] SRAM Address[15] SRAM Address[16] SRAM Address[17] SRAM Address[18] SRAM Data[0] SRAM Data[1] SRAM Data[2] SRAM Data[3] SRAM Data[4] SRAM Data[5] SRAM Data[6] SRAM Data[7] SRAM Data[8]

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DE2-70 User Manual SRAM_DQ[9] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[30] SRAM_DQ[31] SRAM_ADSC_N SRAM_ADSP_N SRAM_ADV_N SRAM_BE_N0 SRAM_BE_N1 SRAM_BE_N2 SRAM_BE_N3 SRAM_CE1_N SRAM_CE2 SRAM_CE3_N SRAM_CLK SRAM_DPA0 SRAM_DPA1 SRAM_DPA2 PIN_AJ17 PIN_AH17 PIN_AJ18 PIN_AH18 PIN_AK19 PIN_AJ19 PIN_AK23 PIN_AJ20 PIN_AK21 PIN_AJ21 PIN_AK22 PIN_AJ22 PIN_AH15 PIN_AJ15 PIN_AJ16 PIN_AK14 PIN_AJ14 PIN_AJ13 PIN_AH13 PIN_AK12 PIN_AK7 PIN_AJ8 PIN_AK8 PIN_AG17 PIN_AC18 PIN_AD16 PIN_AC21 PIN_AC20 PIN_AD20 PIN_AH20 PIN_AH19 PIN_AG19 PIN_AD22 PIN_AD7 PIN_AK9 PIN_AJ23 PIN_AK20 SRAM Data[9] SRAM Data[10] SRAM Data[11] SRAM Data[12] SRAM Data[13] SRAM Data[14] SRAM Data[15] SRAM Data[16] SRAM Data[17] SRAM Data[18] SRAM Data[19] SRAM Data[20] SRAM Data[21] SRAM Data[22] SRAM Data[23] SRAM Data[24] SRAM Data[25] SRAM Data[26] SRAM Data[27] SRAM Data[28] SRAM Data[29] SRAM Data[30] SRAM Data[31] SRAM Controller Address Status SRAM Processor Address Status SRAM Burst Address Advance SRAM Byte Write Enable[0] SRAM Byte Write Enable[1] SRAM Byte Write Enable[2] SRAM Byte Write Enable[3] SRAM Chip Enable 1 SRAM Chip Enable 2 SRAM Chip Enable 3 SRAM Clock SRAM Parity Data[0] SRAM Parity Data[1] SRAM Parity Data[2] 63 .

20. Signal Name FLASH_A[0] FLASH_A[1] FLASH_A[2] FLASH_A[3] FLASH_A[4] FLASH_A[5] FLASH_A[6] FLASH_A[7] FLASH_A[8] FLASH_A[9] FLASH_A[10] FLASH_A[11] FLASH_A[12] FLASH_A[13] FLASH_A[14] FLASH_A[15] FLASH_A[16] FLASH_A[17] FLASH_A[18] FLASH_A[19] FLASH_A[20] FLASH_A[21] FLASH_DQ[0] FLASH_DQ[1] FLASH_DQ[2] FLASH_DQ[3] FLASH_DQ[4] FLASH_DQ[5] FLASH_DQ[6] FPGA Pin No. PIN_AF24 PIN_AG24 PIN_AE23 PIN_AG23 PIN_AF23 PIN_AG22 PIN_AH22 PIN_AF22 PIN_AH27 PIN_AJ27 PIN_AH26 PIN_AJ26 PIN_AK26 PIN_AJ25 PIN_AK25 PIN_AH24 PIN_AG25 PIN_AF21 PIN_AD21 PIN_AK28 PIN_AJ28 PIN_AE20 PIN_AF29 PIN_AE28 PIN_AE30 PIN_AD30 PIN_AC29 PIN_AB29 PIN_AA29 Description FLASH Address[0] FLASH Address[1] FLASH Address[2] FLASH Address[3] FLASH Address[4] FLASH Address[5] FLASH Address[6] FLASH Address[7] FLASH Address[8] FLASH Address[9] FLASH Address[10] FLASH Address[11] FLASH Address[12] FLASH Address[13] FLASH Address[14] FLASH Address[15] FLASH Address[16] FLASH Address[17] FLASH Address[18] FLASH Address[19] FLASH Address[20] FLASH Address[21] FLASH Data[0] FLASH Data[1] FLASH Data[2] FLASH Data[3] FLASH Data[4] FLASH Data[5] FLASH Data[6] 64 . SSRAM pin assignments.DE2-70 User Manual SRAM_DPA3 SRAM_GW_N SRAM_OE_N SRAM_WE_N PIN_AJ9 PIN_AG18 PIN_AD18 PIN_AF18 SRAM Parity Data[3] SRAM Global Write Enable SRAM Output Enable SRAM Write Enable Table 5.

21. Flash pin assignments.DE2-70 User Manual FLASH_DQ[7] FLASH_DQ[8] FLASH_DQ[9] FLASH_DQ[10] FLASH_DQ[11] FLASH_DQ[12] FLASH_DQ[13] FLASH_DQ[14] FLASH_DQ15_AM1 FLASH_BYTE_N FLASH_CE_N FLASH_OE_N FLASH_RESET_N FLASH_RY FLASH_WE_N FLASH_WP_N PIN_Y28 PIN_AF30 PIN_AE29 PIN_AD29 PIN_AC28 PIN_AC30 PIN_AB30 PIN_AA30 PIN_AE24 PIN_Y29 PIN_AG28 PIN_AG29 PIN_AH28 PIN_AH30 PIN_AJ29 PIN_AH29 FLASH Data[7] FLASH Data[8] FLASH Data[9] FLASH Data[10] FLASH Data[11] FLASH Data[12] FLASH Data[13] FLASH Data[14] FLASH Data[15] FLASH Byte/Word Mode Configuration FLASH Chip Enable FLASH Output Enable FLASH Reset LASH Ready/Busy output FLASH Write Enable FLASH Write Protect /Programming Acceleration Table 5. 65 .

and USB and Ethernet connectivity. perform the following 1. if the default factory configuration of the DE2-70 board is not currently stored in EPCS16 device). Copy the directory DE2_70_demonstrations into a local directory of your choice.sof or DE2_70_Default. For each demonstration the Cyclone II FPGA (or EPCS16 serial EEPROM) configuration file is provided. such as its audio and video capabilities. Demonstration Setup. and the red and green LEDs are flashing. with the USB cable connected to the USB Blaster port. These circuits provide demonstrations of the major features on the board. 6. It is important to ensure that the path to your local directory contains no spaces – otherwise. the Nios II software will not work. we give the name of the project directory for its files. as well as the full source code in Verilog HDL code.pof Power on the DE2-70 board. If necessary (that is. All of the associated files can be found in the DE2_70_demonstrations folder from the DE2-70 System CD-ROM. and the locations of its files are shown below. and Instructions • • • Project directory: DE2_70_Default Bit stream used: DE2_70_Default. download the bit stream to the board by using either JTAG or AS programming • You should now be able to observe that the 7-segment displays are displaying a sequence of characters.1 DE2-70 Factory Configuration The DE2-70 board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board. File Locations. Installing the Demonstrations To install the demonstrations on your computer. The setup required for this demonstration. For each of demonstrations described in the following sections. Welcome to the Altera DE2-70 is shown on the LCD display 66 . which are subdirectories of the DE2-70_demonstrations folder.DE2-70 User Manual Chapter 6 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2-70 board. Also.

Alternatively. the TV Decoder chip 67 . The TV_to_VGA block consists of the ITU-R 656 Decoder. Figure 6. As soon as the bit stream is downloaded into the FPGA.DE2-70 User Manual • • • Optionally connect a VGA display to the VGA D-SUB connector.v. The figure also shows the TV Decoder (ADV7180) and the VGA DAC (ADV7123) chips used. Figure 6. audio CODEC. When connected.1 & Nios II EDS 9. the VGA display should show a pattern of colors Optionally connect a powered speaker to the stereo audio-out jack Place toggle switch SW17 in the UP position to hear a 1 kHz humming sound from the audio-out port. and one TV decoder (U11) on the DE2-70 board.1. 6. which also includes the necessary files for the corresponding Quartus II project. The top-level Verilog file.1 IDE is used instead of the Nios II Software Build Tools for Eclipse as it is not supported. can be used as a template for other projects. or the line-in port can be used to play audio from an appropriate sound source The Verilog source code for this demonstration is provided in the DE2_70_Default folder. SDRAM Frame Buffer.2 Quartus II 9. the microphone-in port can be connected to a microphone to hear voice sounds. called I2C_AV_Config and TV_to_VGA.1 to run the DE2-70 demonstrations with Nios II processor must ensure that Nios II 9.3 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output. and VGA Controller.1 shows the directory of the correct Nios II software to run on the DE2-70 demonstrations.1 Users Users that are using the latest Quartus and Nios version 9. because it defines ports that correspond to all of the user-accessible pins on the Cyclone II FPGA. called DE2_70_Default. the register values of the TV Decoder chip are used to configure the TV decoder via the I2C_AV_Config block. YUV422 to YUV444. Following the power-on sequence. YcrCb to RGB. Figure 6. if switch SW17 is DOWN. 6. There are two major blocks in the circuit. which uses the I2C protocol to communicate with the TV Decoder chip.2 shows the block diagram of the design.

pof Connect a DVD player’s composite video output (yellow plug) to the Video-IN 1 RCA jack 68 .2. The VGA Controller block generates standard VGA sync signals VGA_HS and VGA_VS to enable the display on a VGA monitor. File Locations. The ITU-R 656 Decoder block extracts YcrCb 4:2:2 (YUV 4:2:2) video signals from the ITU-R 656 data stream sent from the TV Decoder. multiplexer(MUX) which is TD_DATA ITU-R 656 Decoder YUV 4:2:2 Data Valid SDRAM Frame Buffer Odd 4:2:2 Even 4:2:2 Odd Even Request TV Decoder 7180 TD_HS TD_VS Initiation Delay Timer DLY0 DLY1 DLY2 VGA Controller MUX YUV 4:2:2 VGA_Y 10-bit RGB RGB VGA_HS VGA_VS VGA DAC 7123 Locked Detector To Control the Initiation Sequence I2C_SCLK I2C_SDAT I2C_AV Config YUV 4:2:2 To YUV 4:4:4 YUV 4:2:2 YCbCr To RGB Figure 6. The YUV422 to YUV444 block converts the selected YcrCb 4:2:2 (YUV 4:2:2) video data to the YcrCb 4:4:4 (YUV 4:4:4) video data format. Demonstration Setup. the Lock Detector is responsible for detecting this instability. we need to perform de-interlacing on the data source. and Instructions • • • Project directory: DE2_70_TV Bit stream used: DE2_70_TV. Because the video signal from the TV Decoder is interlaced.sof or DE2_70_TV. the YcrCb_to_RGB block converts the YcrCb data into RGB output.DE2-70 User Manual will be unstable for a time period. Block diagram of the TV box demonstration. the VGA Controller generates data request and odd/even selected signals to the SDRAM Frame Buffer and filed selection multiplexer(MUX). Internally. We used the SDRAM Frame Buffer and a field selection udio lled by the VGA controller to perform the de-interlacing operation. It also generates a data valid control signal indicating the valid period of data output. Finally.

The DVD player has to be configured to provide o NTSC output o 60 Hz refresh rate o 4:3 aspect ratio o Non-progressive video • • Connect the VGA output of the DE2-70 board to a VGA monitor (both LCD and CRT type of monitors should work) Connect the audio output of the DVD player to the line-in port of the DE2-70 board and connect a speaker to the line-out port. Press KEY0 on the DE2-70 board to reset the circuit Figure 6. this is the same type of plug supported on most computers • Load the bit stream into FPGA. If the audio output jacks from the DVD player are of RCA type.3.3 illustrates the setup for this demonstration. Line Out Speaker Line In CVBS S-Video YPbPr Output Audio Output VGA(LCD/CRT)Monitor Video In VGA Out DVD Player ITU-R 656 YUV 4:2:2 Decoder DE-interlace Figure 6. then an adaptor will be needed to convert to the mini-stereo plug supported on the DE2-70 board. The setup for the TV box demonstration. 69 .DE2-70 User Manual (J8) of the DE2-70 board.

The Composite_to_VGA block takes the video signals from the TV decoders as input and generate VGA-interfaced signals as output. the output VGA data rate of the Composite_to_VGA block for the sub window must be two times as fast as the rate of the Composite_to_VGA block for the main window. called Composite_to_VGA. the output timing of the VGA interface signal from the Composite_to_VGA block is controlled by the pip_position_controller block that determines the stating poison of the sub window. The Composite_to_VGA block consists all of the function blocks in the TV box demonstration project described in the section 6. In addition. 70 . This demonstration will multiplex two different video source signals from the TV decoders and display both video signals on the LCD/CRT monitor using picture in picture mode (PIP mode : One picture is displayed on the full screen and the other picture is displayed in a small sub window).4 shows the basic block diagram of this demonstration. PIP_Position_Controller.4 TV Box Picture in Picture (PIP) Demonstration The DE2-70 board has two TV decoders and RCA jacks that allow users to process two video sources simultaneously using the 2C70 FPGA. Finally. Video in 1 or Video in 2 TV decoder (Sub window) TD data TD_clock Composite_to_ VGA (Sub window) VGA data PiP_position_ controller Control signal TD_clock_ PLL Video in 2 or Video in 1 TD_clock (27Mhz) TV decoder (Main window) TD data 54Mhz VGA data(Sub) VGA DAC Composite_to_ VGA (Main window) VGA data(Main) VGA data VGA multiplexer Figure 6. The circuit in the FPGA is equipped with two Composite_to_VGA blocks converting the video signals from the TV decoder 1 and TV decoder 2 respectively. Also. and VGA_Multiplexer. There are three major blocks in the circuit. both of the two VGA interfaced signals will be multiplexed and sent to the LCD/CRT monitor via the VGA_multiplexer block. Figure 6.4. Block diagram of the TV PIP demonstration. To display two video signals in PIP mode on the LCD/CRT monitor.3.DE2-70 User Manual 6. users can select which video is displayed in main/sub window via a toggle switch.

The detailed configuration for switching video source of main and sub window are listed in Table 6. 71 .pof Connect composite video output (yellow plug) of DVD player 1 and DVD player2 to the Video-in 1 and Video-in 2 RCA jack (J8 and J9) of the DE2-70 board respectively. • • Figure 6. If the audio output jacks from the DVD player are of RCA type. this is the same type of plug supported on most computers Load the bit stream into FPGA. File Locations.5 illustrates the setup for this demonstration.sof or DE2_70_TV_PIP. and Instructions • • • Project directory: DE2_70_TV_PIP Bit stream used: DE2_70_TV_PIP.DE2-70 User Manual Demonstration Setup.1. Both DVD players must be configured to provide o 60 Hz refresh rate o 4:3 aspect ratio o Non-progressive video • • Connect the VGA output of the DE2-70 board to a VGA monitor (both LCD and CRT type of monitors should work) Connect the one audio output of the DVD player to the line-in port of the DE2-70 board and connect a speaker to the line-out port. then an adaptor will be needed to convert to the mini-stereo plug supported on the DE2-70 board.

5.DE2-70 User Manual VGA(LCD/CRT)Monitor VGA Out To TV_to_VGA PIP_Control Figure 6. 72 . The setup for the TV box PIP demonstration.

we implement a Paintbrush application by using a USB mouse as the input device. The VGA Controller will overlap the data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display. PIP display mode SW[16] = OFF SW[17] = ON. the Nios II processor is able to keep track of the movement and record it in a frame buffer memory.DE2-70 User Manual Configuration SW[17] = OFF. VGA Display Mode Signal display mode Video source Video in 2 SW[16] = OFF SW[17] = OFF. it will detect the existence of the USB mouse connected to DE2-70 board.1. Once the program running on the Nios II processor is started. Signal display mode SW[16] = ON SW[17] = ON. We also implemented a video frame buffer with a VGA controller to perform the real-time image storage and display. The DE2-70 board provides a complete USB solution for both host and device applications.6 shows the block diagram of the circuit. 73 . Once the mouse is moved.5 USB Paintbrush USB is a popular communication method used in many multimedia products. PIP display mode SW[16] = ON Sub window : Video in 2 Sub window : Video in 1 Main window: Video in 1 Main window: Video in 2 Video in 1 Table 6. Figure 6. The setup for the TV box PIP demonstration 6. which allows the user to draw lines on the VGA display screen using the USB mouse. This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector. The VGA Controller block is integrated into the Altera Avalon bus so that it can be controlled by the Nios II processor. In this demonstration.

Demonstration Setup. 74 . Click on the Run button You should now be able to observe a blue background with an Altera logo on the VGA display Move the USB mouse and observe the corresponding movements of the cursor on the screen Left-click mouse to draw white dots/lines and right-click the mouse to draw blue dots/lines on the screen.6. and Instructions Project directory: DE2_70_NIOS_HOST_MOUSE_VGA Bit stream used: DE2_70_NIOS_HOST_MOUSE_VGA. File Locations.DE2-70 User Manual Philips ISP1362 Host Port Altera System Interconnect Fabric USB Mouse Nios II CPU VGA Controller ADV7123 Frame Buffer Figure 6. Block diagram of the USB paintbrush demonstration.sof Nios II Workspace: DE2_70_NIOS_HOST_MOUSE_VGA\Software • • • • • • • Connect a USB Mouse to the USB Host Connector (type A) of the DE2-70 board Connect the VGA output of the DE2-70 board to a VGA monitor (both LCD and CRT type of monitors should work) Load the bit stream into FPGA Run the Nios II and choose DE2_70_NIOS_HOST_MOUSE_VGA\Softwar as the workspace.

USB Driver VGA Monitor VGA Controller IP On-Chip Video Frame Buffer Figure 6. The setup for the USB paintbrush demonstration. the Nios II processor is used to communicate with the host computer via the host port on the DE2-70 board’s Philips ISP1362 device. the host computer will identify the new device in its USB device list and ask for the associated driver. a software program has to be executed on the Nios II processor to initialize the Philips ISP1362 chip. In the ISP1362DcUsb program. If 75 . After completion of the driver installation on the host computer. clicking on the Add button in the window panel of the software causes the host computer to send a particular USB packet to the DE2-70 board. the packet will be received by the Nios II processor and will increment the value of a hardware counter. In this demonstration. As indicated in the block diagram in Figure 6. Once the software program is successfully executed. After connecting the DE2-70 board to a USB port on the host computer.8.exe. we show how the DE2-70 board can operate as a USB device that can be connected to a host computer. rather than USB hosts. the device will be identified as a Philips PDIUSBD12 SMART Evaluation Board.7.DE2-70 User Manual Figure 6. 6.7 illustrates the setup for this demonstration. The value of the counter is displayed on one of the board’s 7-segment displays. this program communicates with the DE2-70 board. and also on the green LEDs.6 USB Device Most USB applications and products operate as USB devices. the next step is to run a software program on the host computer called ISP1362DcUsb.

File Locations. Specify the location of the driver as DE2_70_NIOS_DEVICE_LED\D12test.DE2-70 User Manual the user clicks on the Clear button in the window panel of the software driver. Figure 6.sof Nios II Workspace: DE2_70_NIOS_DEVICE_LED\HW\Software Borland BC++ Software Driver: DE2_70_NIOS_DEVICE_LED\SW Connect the USB Device connector of the DE2-70 board to the host computer using a USB cable (type A → B). Load the bit stream into FPGA Run Nios II IDE with DE2_70_NIOS_DEVICE_LED\HW\Software as the workspace. and Instructions • • • • • • • • Project directory: DE2_70_NIOS_DEVICE_LED\HW Bit stream used: DE2_70_NIOS_DEVICE_LED.inf (Philips PDIUSBD12 SMART Evaluation Board). Block diagram of the USB device demonstration. the host computer sends a different USB packet to the board. Demonstration Setup.exe on the host computer. which causes the Nios II processor to clear the hardware counter to zero. experiment with the software by clicking on the ADD and Clear buttons 76 .8. Click on Run A new USB hardware device will be detected. Then. Ignore any warning messages produced during installation • • The host computer should report that a Philips PDIUSBD12 SMART Evaluation Board is now installed Execute the software: DE2_70_NIOS_DEVICE_LED\SW\ISP1362DcUsb.

7 A Karaoke Machine This demonstration uses the microphone-in. 77 . The setup for the USB device demonstration. the I2C interface is used to configure the Audio CODEC.DE2-70 User Manual Figure 6. and the data input from the line-in port is then mixed with the microphone-in port and the result is sent to the line-out port. Pressing the pushbutton KEY0 reconfigures the gain of the audio CODEC via the I2C bus. line-in. cycling through one of the ten predefined gains (volume levels) provided by the device. The Wolfson WM8731 audio CODEC is configured in the master mode.9. where the audio CODEC generates AD/DA serial bit clock (BCK) and the left/right channel clock (LRCK) automatically. As indicated in Figure 6. PC USB Driver 7-SEG Control Accumulator Figure 6.10. and line-out ports on the DE2-70 board to create a Karaoke Machine application. 6. The sample rate and gain of the CODEC are set in this manner. For this demonstration the sample rate is set to 48 kHz.9 illustrates the setup for this demonstration.

File Locations. such as an MP3 player or computer. and Instructions • • • • • • • • Project directory: DE2-70_i2sound Bit stream used: DE2-70_i2sound.10. it cycles between volume levels 0 to 9 78 .pof Connect a microphone to the microphone-in port (pink color) on the DE2-70 board Connect the audio output of a music-player. Block diagram of the Karaoke Machine demonstration.DE2-70 User Manual Figure 6.sof or DE2-70_i2sound. to the line-in port (blue color) on the DE2-70 board Connect a headset/speaker to the line-out port (green color) on the DE2-70 board Load the bit stream into the FPGA You should be able to hear a mixture of the microphone sound and the sound from the music player Press KEY0 to adjust the volume. Demonstration Setup.

As illustrated in Figure 6.8 Ethernet Packet Sending/Receiving In this demonstration. the DM9000A appends a four-byte checksum to the packet 79 . On the transmitting side.DE2-70 User Manual Figure 6. the Nios II processor sends 64-byte packets every 0. The setup for the Karaoke Machine. we use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY/MAC Controller. MP3/Any Audio Output Speaker Microphone Clock/Data Frequency Generator Figure 6. we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2-70 board. 6.11 illustrates the setup for this demonstration. After receiving the packet.11.5 seconds to the DM9000A.12. or two DE2-70 boards connected together. The demonstration can be set up to use either a loop-back connection from one board to itself.

Demonstration Setup. File Locations. If the packet received does have the same MAC address or is a broadcast packet. and Instructions • • • • • • • • Project directory: DE2_70_NET Bit stream used: DE2_70_NET.DE2-70 User Manual and sends it to the Ethernet port. the DM9000A checks every packet received to see if the destination MAC address in the packet is identical to the MAC address of the DE2-70 board. On the receiving side. The processor will then display the packet contents in the Nios II IDE console window. the DM9000A will accept the packet and send an interrupt to the Nios II processor. Figure 6. Packet sending and receiving using the Nios II processor. 68-byte packets received because of the extra checksum bytes) 80 .12.sof Nios II Workspace: DE2_70_NET\Software Plug a CAT5 loop-back cable into the Ethernet connector of DE2-70 Load the bit stream into the FPGA Run the Nios II IDE under the workspace DE2_70_NET\Software Click on the Run button You should now be able to observe the contents of the packets received (64-byte packets sent.

We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM8731 audio CODEC to play the music.9 SD Card Music Player Many commercial media/audio players use a large external storage device.13.DE2-70 User Manual Figure 6. In this demonstration we show how to implement an SD Card Music Player on the DE2-70 board. The DE2-70 board provides the hardware and software needed for SD card access and professional audio performance so that it is possible to design advanced multimedia products using the DE2-70 board. such as an SD card or CF card. in which the music files are stored in an SD card and the board can play the music files via its CD-quality audio DAC circuits. The setup for the Ethernet demonstration.13 illustrates the setup for this demonstration. 81 . Such players may also include high-quality DAC devices so that good audio quality can be produced. to store music or video files. 6. 10/100Mbps CAT 5 Cable Loopback Device Ethernet Driver Figure 6.

14. The 7-segment display is controlled by the Seg-7 Controller which also is a user-defined SOPC component. The system requires a 50 MHZ clock provided from the board. Figure 6. Four PIO pins are connected to the SD CARD socket. This audio controller needs an input clock running at 18. The PLL generates a 100-MHZ clock for NIOS II processor and the other controllers except for the audio controller. 82 . only read function is implemented. The WAVE Lib block implements WAVE file decoding function for receiving audio signal from wave files. The I2C block implements I2C protocol for configuring audio chip. The audio chip is controlled by the Audio Controller which is a user-defined SOPC component. so the serial bit (BCK) and the left/right channel clock (LRCK) are provided by the audio chip. In this design. the clock is provided by the PLL block. The Audio block implements audio FIFO checking function and audio signal sending/receiving function. In this block. The audio controller requires the audio chip working in master mode. Two PIO pins are connected to the I2C bus. The FAT16 block implements FAT16 file system for reading wave files that stored in the SD card. SD 1-Bit Mode is used to access the SD card and is implemented by software. Figure 6.432 MHZ. SD 1-Bit Mod block implements the SD 1-bit mode protocol for reading raw data from the SD card. The SEG7 block implements displaying function for display elapsed playing time.15 shows the software stack of this demonstration. The I2C protocol is implemented by software. All of the other SOPC components in the block diagram are SOPC Builder built-in components. Block diagram of the SD music player demonstration.DE2-70 User Manual Figure 6.14 shows the hardware block diagram of this demonstration.

DE2-70 User Manual

Figure 6.15. Software Stack of the SD music player demonstration.

The audio chip should be configured before sending audio signal to the audio chip. The main program uses I2C protocol to configure the audio chip working in master mode, the audio interface as I2S with 16-bits per channel, and sampling rate according to the wave file content. In audio playing loop, the main program reads 512-byte audio data from the SD card, and then writes the data to DAC FIFO in the Audio Controller. Before writing the data to the FIFO, the program have to make sure the FIFO is not full. The design also mixes the audio signal from the microphone-in and line-in for the Karaoke-style effects by enabling the BYPASS and SITETONE functions in the audio chip. Finally, users can obtain the status of the SD music player from the 2x16-LCD module, the 7 segment display and the LEDs. The top and bottom row of the LCD module will display the file name of the music that is playing on the DE2-70 board and the value of music volume, respectively. The 7 segments display will show how long the music file has been played. The LED will indicate the audio signal strength.

Demonstration Setup, File Locations, and Instructions
• • • • • Project directory: DE2_70_SD_Card_Audio_Player Bit stream used: DE2_70_SD_Card_Audio_Player.sof Nios II Workspace: DE2_70_SD_Card_Audio_Player\Software Format your SD card into FAT16 format Put the played wave files to the root directory of the SD card. The provided wave files must have a sample rate of either 96K, 48K, 44.1K, 32K, or 8K. Besides, the wave files must be stereo and 16 bits per channel. Also, the file name must be short filename. Load the bitstream into the FPGA on the DE2-70 board. Run the Nios II IDE under the workspace DE2_70_SD_Card_Audio_Playe\Software Connect a headset or speaker to the DE2-70 board and you should be able to hear the music played from the SD Card
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DE2-70 User Manual

• Press KEY3 on the DE2-70 board can play the next music file stored in the SD card. • Press KEY2 and KEY1 will increase and decrease the output music volume respectively. . Figure 6.16 illustrates the setup for this demonstration.

Speaker

Lock

SD Card with music fils(wav)

SD Card Driver

Audio CODEC Controller On-Chip Audio PCM Buffer

Figure 6.16. The setup for the SD music player demonstration.

6.10 Music Synthesizer Demonstration
This demonstration shows how to implement a Multi-tone Electronic Keyboard using DE2-70 board with a PS/2 Keyboard and a speaker. PS/2 Keyboard is used as the piano keyboard for input. The Cyclone II FPGA on the DE2-70 board serves as the Music Synthesizer SOC to generate music and tones. The VGA connected to the DE2-70 board is used to show which key is pressed during the playing of the music.
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DE2-70 User Manual

Figure 6.15 shows the block diagram of the design of the Music Synthesizer. There are four major blocks in the circuit: DEMO_SOUND, PS2_KEYBOARD, STAFF, and TONE_GENERATOR. The DEMO_SOUND block stores a demo sound for user to play; PS2_KEYBOARD handles the users’ input from PS/2 keyboard; The STAFF block draws the corresponding keyboard diagram on VGA monitor when key(s) are pressed. The TONE_GENERATOR is the core of music synthesizer SOC. User can switch the music source either from PS2_KEYBOAD or the DEMO_SOUND block using SW9. To repeat the demo sound, users can press KEY1. The TONE_GENERATOR has two tones: (1) String. (2) Brass, which can be controlled by SW0. The audio codec used on the DE2-70 board has two channels, which can be turned ON/OFF using SW1 and SW2. Figure 6.17 illustrates the setup for this demonstration.

Figure 6.17.

Block diagram of the Music Synthesizer design

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pushbuttons (KEYs). pushbuttons (KEYs).3 illustrate the usage of the switches. Make sure all the switches (SW[9:0]) are set to 0 (Down Position) Press KEY1 on the DE2-70 board to start the music demo Press KEY0 on the DE2-70 board to reset the circuit Table 6.2 and 6. Switches and Pushbuttons Signal Name KEY[0] KEY[1] SW[0] SW[9] SW[1] SW[2] Reset Circuit Repeat the Demo Music OFF: BRASS. • PS/2 Keyboard Signal Name Q A W S E D F T G -#4 -5 -#5 -6 -#6 -7 1 #1 2 Description 86 . and Instructions • • • • • • • • • Project directory: DE2_70_Synthesizer Bit stream used: DE2_70_Synthesizer. Connect the VGA output of the DE2-70 board to a VGA monitor (both LCD and CRT type of monitors should work) Connect the Lineout of the DE2-70 board to a speaker. File Locations.pof Connect a PS/2 Keyboard to the DE2-70 board. PS/2 Keyboard.DE2-70 User Manual Demonstration Setup. Load the bit stream into FPGA.2. ON: STRING OFF: DEMO. Usage of the switches. ON: PS2 KEYBOARD Channel-1 ON / OFF Channel-2 ON / OFF Description Table 6.sof or DE2-70_Synthesizer.

DE2-70 User Manual Y H J I K O L P : “ #2 3 4 #4 5 #5 6 #6 7 +1 Table 6. 87 . C D E F G A B C D E F G A B C D E F G A B Line Out Speaker VGA(LCD/CRT)Monitor VGA Out Keyboard Input Keyboard Music Synthesizer Algorithms for Audio Processing Figure 6. The Setup of the Music Synthesizer Demonstration.16.3. Usage of the PS/2 Keyboard’s keys.

Record/Play Status Record/Play Duration Signal Strength Play Sample rate Record Audio Source MIC Boost Zero-Cross Detect Figure 6. 32K. or 8K. There are hardware part and software part in the block diagram. The seg7 is used to display Recording/Playing duration with time unit in 1/100 second. 44. The hardware part includes all the other blocks. This demonstration is developed based on SOPC Builder and NIOS II IDE. Man-Machine Interface of Audio Recorder and Player.11 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player using the DE2-70 board with the built-in Audio CODEC chip. The 16x2 LCD is used to indicate the Recording/Playing status. It is designed to send audio 88 . 48K. SW3. SW1 is to enable/disable MIC Boost when the recoding source is MIC-In. SW2 is used to enable/disable Zero-Cross Detection for audio playing. The “AUDIO Controller” is a user-defined SOPC component.19 shows the block diagram of the design of the Audio Recorder and Player. The software part is built by Nios II IDE in C programming language. Table 6. SW4 and SW5 are used to specify recording sample rate as 96K.1K.4 summarizes the usage of toggle switches for configuring the audio recorder and player. The hardware part is built by SOPC Builder under Quartus II. The LED is used to indicate the audio signal strength.18 shows the man-machine interface of this demonstration.DE2-70 User Manual 6. The software part means the Nios II program that stored in SSRAM. Two push buttons and six toggle switches are used for users to configure this audio system: SW0 is used to specify recording source to be Line-in or MIC-In. Figure 6. Figure 6.18.

The audio interface is configured as I2S and 16-bit mode. A 18.19. In this example. The audio chip is programmed through I2C protocol which is implemented in C code. The I2C pin from audio chip is connected to SOPC System Interconnect Fabric through PIO controllers.432MHz clock generated by the PLL is connected to the XTI/MCLK pin of the audio chip through the AUDIO Controller.sof Software Project directory: DE2_70_AUDIO\software\project_audio Software Execution File: DE2_70_AUDIO\software\project_auido\audio\debug\audio.elf Connect an Audio Source to the LINE-IN port of the DE2-70 board. Block diagram of the audio recorder and player. (note *1) Configure audio with the toggle switches. the audio chip is configured in Master Mode. Load the bit stream into FPGA. Connect a Microphone to MIC-IN port on the DE2-70 board. Connect a speaker or headset to LINE-OUT port on the DE2-70 board.DE2-70 User Manual data to the audio chip or receive audio data from the audio chip. Demonstration Setup. (note *1) Load the Software Execution File into FPGA. File Locations. and Instructions • • • • • • • • • • Hardware Project directory: DE2_70_AUDIO Bit stream used: DE2P_TOP. 89 . SOPC 50M Hz RESE_N NIOS II SDRAM Controller SRAM Controller PIO LCD Controller SEG7 Controller AUDIO Controller SDRAM Store Audio Data Nios II Program SRAM LED/KEY/SW/I2C LCD System Interconnect Fabric JTAG UART Clock to SDRAM SRAM PLL SEG7 AUDIO Figure 6.

(3).1K 32K 8K 96K Sample Rate Table 6.elf files. 1-UP) 0 1 0 1 0 96K 48K 44. 1. 90 . Playing process will stop if audio data is played completely.DE2-70 User Manual • • Press KEY3 on the DE2-70 board to start/stop audio recoding (note *2) Press KEY2 on the DE2-70 board to start/stop audio playing (note *3) Note: (1). (2). Recording process will stop if audio buffer is full.UP) 0 0 0 0 1 SW4 (0 – DOWN.bat will download . Toggle switch setting for audio recorder and player.4. Toggle Switches SW0 SW1 SW2 0 – DOWN Position Audio is from MIC Disable MIC Boost Disable Zero-cross Detection 1 – UP Position Audio is from LINE-IN Enable MIC Boost Enable Zero-cross Detection SW5 (0 – DOWN. Execute DE2_70_AUDIO\demo batch\audio.sof and . 1-UP) 0 0 1 1 0 Unlisted combination SW3 (0 – DOWN.

01 Revision History Change Log Initial Version (Preliminary) 1. 91 . All rights reserved.3.06 V1.04 V1.8 Modify clock frequency of the VGA DAC Modify Section 5.03 V1. Add appendix chapter.6.1 section 7.0 V1.2 Copyright Statement Copyright © 2009 Terasic Technologies. V1.2 V1.05 V1.08 Added Quartus II 9.5. 2.07 Modify Figure 6. Modify Chapter 2.1 Version V1.4.02 V1.4 Modify Chapter 1 Modify Nios II workspace Modify the location of the DE2-70 control panel and DE2-70 Video Utility for DE2-70 system CD v1.1 & Nios II EDS 9.DE2-70 User Manual Chapter 7 Appendix 7.

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