UNIT-5 INTRODUCTION DIGITAL SIGNAL PROCESSORS AND ITS APPLICATION

DSP/ISP division School of Electronics Engineering VIT University Vellore -632 014
DSP DIVISION DSP PROCESSOR 1

OBJECTIVE
• Understand the DSP Architecture, fixed and floating point processor differences • Able to understand how pipelining and parallelism supports in the DSP Architecture. • Know how to implement convolution, correlation, DFT & Filter design using Texas instruments DSP processor.

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DSP PROCESSOR

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Introduction
• DSP processors can be divided into two broad categories:
» General Purpose » Special Purpose

• Further DSP processors include
» Fixed point devices » Floating point devices

DSP DIVISION

DSP PROCESSOR

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Examples of Fixed and Floating
• Low End Fixed Point
– TMS320C2XX, ADSP21XX, Motorola (DSP56XXX)

• High End Fixed Point
– TMS320C55XX, DSP16XXX, – ADSP215XX, DSP56800

• Floating Point
– TMS320C3X, C67XX, ADSP210XX(SHARC processor), DSP96000, DSP32XX
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Fixed Point Vs Floating Point
– fixed point processor are :
• • • • cheaper smaller less power consuming Harder to program – Watch for errors: truncation, overflow, rounding • Limited dynamic range • Used in 95% of consumer products

– floating point processors
• have larger accuracy • are much easier to program • can access larger memory
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2.Fixed Point Vs Floating Point Floating Point Applications •Modems •Digital Subscriber Line (DSL) •Wireless Basestations Fixed Point Applications •Portable Products •2G.5G and 3G Cell Phones •Digital Audio Players •Digital Still Cameras •Electronic Books •Voice Recognition •GPS Receivers •Central Office Switches •Private Branch Exchange (PBX) •Digital Imaging •3D Graphics •Speech Recognition •Headsets •Biometrics •Fingerprint Recognition •Voice over IP DSP DIVISION DSP PROCESSOR 6 .

[ Algorithm-specific digital signal processor] • Hardware designed for specific application. FFT. or control applications.[ Application -specific digital signal processor] DSP DIVISION DSP PROCESSOR 7 . digital audio.Special purpose hardware • Hardware designed for efficient execution of specific DSP algorithms such as digital filter. for example telecommunications.

dedicated hardware multiplier/Accumulator Special instruction dedicated to DSP Replication On-chip memory/cache Extended parallelism.Computer Architecture for Signal Processing Techniques • • • • • • • Harvard Architecture Pipelining Fast.SIMD. VLIW and static superscalar processing DSP PROCESSOR 8 DSP DIVISION .

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Basic generic hardware architecture for signal processing ALU Multiplier Accumulator Memory units I/O devices Shifter X data memory Y data memory Program memory X data bus Y data bus DSP DIVISION DSP PROCESSOR Z data bus 10 .

Harvard Architecture DSP DIVISION DSP PROCESSOR 11 .

Hardware Multiply and accumulate DSP DIVISION DSP PROCESSOR 12 .

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Pipelining • A technique which allows two or more operations to overlap during execution. • It is used extensively in DSP to increase speed. • The simultaneous functions going on are: • instruction fetch • instruction decode • instruction execution DSP DIVISION DSP PROCESSOR 15 .

Stages of pipelining DSP DIVISION DSP PROCESSOR 16 .

• Each of the step is known as pipeline stage DSP DIVISION DSP PROCESSOR 17 .• In a Harvard architecture (DSP processor with pipelining) : • The program instructions and data lie in separate memory spaces. • Due to this the fetching of the next instruction can overlap the execution of the current instruction.

• Instruction register: holds the instruction to be executed. • Queue instruction register: stores the instruction to be executed if the current is still in process of execution. • Pre-fetch counter: holds the address of the next instruction to be fetched.REGISTERS • In TMS320 number of registers are used to achieve pipelining. • Program counter: contains the address of the next instruction to be executed DSP DIVISION DSP PROCESSOR 18 .

1990) time per instruction(non-pipeline) number of pipe stages Average instruction time (nonpipeline) •Speedup= DSP DIVISION AverageDSP PROCESSOR time (pipeline) instruction 19 . •In a perfect pipeline the average time per instruction is given by( Hennesy and Patterson.Parameters used in pipelining •Throughput is determined by the number of instructions through the pipe per unit time.

DISADVANTAGES The design is complex due to addition of extra flip flops. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs due to unstable instruction bandwidth. thus increasing instruction bandwidth in most cases.ADVANTAGES The cycle time of the processor is reduced. The manufacture cost is high. DSP DIVISION DSP PROCESSOR 20 .

Examples (pipelining) • Multiply and accumulate operations typified by the following equation • a0x(n)+a1x(n-1)+a2x(n-2)+….+AN-1x(N-1) • Non pipeline of the above equation DSP DIVISION DSP PROCESSOR 21 ..

MAC Pipeline operation DSP DIVISION DSP PROCESSOR 22 .

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Parallelism • To achieve increased computational performance • Three techniques used to achieve parallelism are • SIMD • VLIW • Superscalar processing DSP DIVISION DSP PROCESSOR 24 .

SIMD (Single instruction multiple data) • Used to increase number of operation performed per instruction • Multiple data path and multiple execution unit • Single instruction may be issued to multiple execution unit to process the block of data simultaneously and in this way number of operation performed in one cycle is increased DSP DIVISION DSP PROCESSOR 25 .

SIMD DSP DIVISION DSP PROCESSOR 26 .

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VLIW (Very Long Instruction Word) • Substantially increasing the number of instruction that are processed per cycle • Essentially a concatenation of several short instruction and require multiple execution units running in parallel to carry out the instructions in a single cycle DSP DIVISION DSP PROCESSOR 29 .

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organized in two sets –(L1.D1) and (L2.Features of VLIW • The cpu contain two data paths and eight independent execution units.S1.S2.M2. • VLIW architecture is clearly designed to support instruction level parallelism.D2) • Each short instruction is 32 bits wide and eight of these are linked together to form a very long instruction word packed which may be executed in parallel. together with fast clock speeds-200MHz DSP DIVISION DSP PROCESSOR 31 .M1.

• Super scalar. and Pentium processor • Best known super scalar processor is the Analog devices Tiger SHARC DSP DIVISION DSP PROCESSOR 32 .computer architecture that enable multiple instruction to be executed in one cycles • It is widely used in general purpose processor such as power PC.Super scalar processing • Increasing the instruction rate of a DSP processor (the number of instruction processed in a cycle) by exploiting instruction-level parallelism.

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pipelining and dedicated hardware. multiplication and so on DSP DIVISION DSP PROCESSOR 34 . Harvard architecture. scaling. shifting.General Purpose Digital Signal processor • It is a High speed microprocessor with hardware architecture • Instruction sets are optimized for DSP operations • Extensive use of parallelism.

Fixed point Digital Signal Processors DSP DIVISION DSP PROCESSOR 35 .

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Fixed point Digital Signal processors DSP DIVISION DSP PROCESSOR 45 .

Floating Point Processors DSP DIVISION DSP PROCESSOR 46 .

Selecting the Digital Signal Processor • Architectural features • Size of on chip memory • Special Instruction • I/O capability • Execution speed • Clock speed of the processor(MHz) • Number of instruction performed (MIPS) & (MFLOPS) DSP DIVISION DSP PROCESSOR 47 .

• Type of Arithmetic – Fixed point arithmetic – Floating point arithmetic • Word Length – 24 bit word length for audio processing – Longer data word length lower the error DSP DIVISION DSP PROCESSOR 48 .

Implementation of DSP algorithm on general purpose Digital Signal Processor • FIR Digital filtering DSP DIVISION DSP PROCESSOR 49 .

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Pearson Education. Lawrence R Rabiner and Bernard Gold. 2001. “ Digital Signal Processing A Practical Approach” 2 nd edition. 2.References: 1. Emmanuel C. PHI 1992 DSP DIVISION DSP PROCESSOR 51 . “Theory and Application of Digital Signal Processing” .Ifeachor.

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