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HY5DU284(8,16)22ET(Rev0.5)

HY5DU284(8,16)22ET(Rev0.5)

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HY5DU28422ET HY5DU28822ET HY5DU281622ET

128Mb DDR SDRAM
HY5DU28422ET HY5DU28822ET HY5DU281622ET

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 /Apr. 2006

HY5DU28422ET HY5DU28822ET HY5DU281622ET

Revision History
Revision No. 0.1 0.2 0.3 Define Preliminary Specification Insert CL3 in Speed Grade(-J) Editorial Changes 1) Changed Document Title from 128M to 128Mb 2) Changed Parameter name from Ambient Temperature to Operating Temperature in ABSOLUTE MAXIMUM RATINGS 3) Updated High, Low Current Level of Output Driver Strength in DC OPERATING CONDITIONS 4) Corrected 6th note and Added 7th note in DC OPERATING CONDITIONS 5) Editorial Changes State Diagram modified History Draft Date Sep. 2003 Oct. 2003 Jul. 2004 Remark

0.4

Aug. 2004

0.5

Apr. 2006

Rev. 0.5 /Apr. 2006

2

HY5DU28422ET HY5DU28822ET HY5DU281622ET

DESCRIPTION
The Hynix HY5DU28422ET, HY5DU28822ET and HY5DU281622ET are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

FEATURES
• • • • • • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe tRAS Lock-out function supported • • • • • • • • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency 2 / 2.5 / 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported 4096 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS

• • •

ORDERING INFORMATION
Part No. HY5DU28422ET-X* HY5DU28822ET-X* HY5DU281622ET-X* Configuration 32Mx4 16Mx8 8Mx16 PACKAGE 400mil 66pin TSOP-II

OPERATING FREQUENCY
Grade CL2 CL2.5 CL3 Remark (CL-tRCD-tRP)

-J -M -K -H -L

133MHz 133MHz 133MHz 100MHz 100MHz

166MHz 133MHz 133MHz 133MHz 125MHz

166MHz -

DDR333 (2.5-3-3) / 166MHz (3-3-3) DDR266 (2-2-2) DDR266A (2-3-3) DDR266B (2.5-3-3) DDR200 (2-2-2) 3

* X means speed grade

Rev. 0.5 / Apr. 2006

BA1 A10 4K 8Mx16 2M x 16 x 4banks A0 . BA1 A10 4K 16Mx8 4M x 8 x 4banks A0 .A11 A0-A9. BA1 A10 4K Rev.5 /Apr. 0.A11 A0-A8 BA0. A11 BA0.A11 A0-A9 BA0.65mm pin pitch ROW AND COLUMN ADDRESS TABLE ITEMS Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh 32Mx4 8M x 4 x 4banks A0 . 2006 4 .HY5DU28422ET HY5DU28822ET HY5DU281622ET PIN CONFIGURATION(TSOP) x4 VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD x16 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS 400mil X 875mil 66pin TSOP -II 0.

Reference voltage for inputs for SSTL interface. Address Inputs: Provide the row address for ACTIVE commands. Data Strobe: Output with read data. LDQS corresponds to the data on DQ0-Q7. Read. No connection. excluding CKE are disabled during SELF REFRESH. DQS and DM. BA1. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. /CK and CKE are disabled during POWER DOWN. CS is considered part of the command code.5 /Apr. 0. CKE must be maintained high throughout READ and WRITE accesses. but will detect an LVCMOS LOW level after VDD is applied. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). Chip Select: Enables or disables all inputs except CK. 2006 5 . Power supply for output buffers for noise immunity. UDM corresponds to the data on DQ8-Q15. CS provides for external bank selection on systems with multiple banks. Although DM pins are input only. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle). UDQS corresponds to the data on DQ8-Q15. Input buffers. and for SELF REFRESH entry. centered in write data. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE. BA1 Input A0 ~ A11 Input /RAS. or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is asynchronous for SELF REFRESH exit. DM is sampled on both edges of DQS. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). If only one bank is to be precharged. Data input / output pin: Data bus Power supply for internal circuits and input buffers. CKE Input /CS Input BA0. /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. Edge aligned with read data. the bank is selected by BA0. /CAS. input with write data. and CKE LOW deactivates internal clock signals. All commands are masked when CS is registered high. excluding CK. CKE. The address inputs also provide the op code during a MODE REGISTER SET command. Clock Enable: CKE HIGH activates. to select one location out of the memory array in the respective bank. Input buffers. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). For the x16. /CK. and for output disable. /CAS and /WE (along with /CS) define the command being entered. CKE is synchronous for POWER DOWN entry and exit. Write or PRECHARGE command is being applied. Used to capture write data. For the x16. the DM loading matches the DQ and DQS loading. /WE Input DM (LDM. LDM corresponds to the data on DQ0-Q7. and the column address and AUTO PRECHARGE bit for READ/WRITE commands. Command Inputs: /RAS.HY5DU28422ET HY5DU28822ET HY5DU281622ET PIN DESCRIPTION PIN CK. UDM) Input DQS (LDQS. UDQS) DQ VDD/VSS VDDQ/VSSQ VREF NC I/O I/O Supply Supply Supply NC Rev. and device input buffers and output drivers. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. CKE is an SSTL_2 input. Input Data Mask: DM is an input mask signal for write data.

HY5DU28422ET HY5DU28822ET HY5DU281622ET FUNCTIONAL BLOCK DIAGRAM (32Mx4) 4Banks x 8Mbit x 4 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 8 CLK /CLK CKE /CS /RAS /CAS /WE DM Bank Control Command Decoder 8Mx4/Bank0 Sense AMP 8Mx4/Bank1 8Mx4/Bank2 8Mx4/Bank3 Mode Register Row Decoder 8 4 Input Buffer Output Buffer 4 DS 2-bit Prefetch Unit DQ [0:3] Column Decoder ADD BA0. BA1 DQS Address Buffer Column Address Counter CLK_DLL DS CLK /CLK DLL Block Data Strobe Transmitter Data Strobe Receiver Mode Register Rev.5 /Apr. 2006 6 . 0.

HY5DU28422ET HY5DU28822ET HY5DU281622ET FUNCTIONAL BLOCK DIAGRAM (16Mx8) 4Banks x 4Mbit x 8 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 16 CLK /CLK CKE /CS /RAS /CAS /WE DM Bank Control Command Decoder 4Mx8/Bank0 Sense AMP 4Mx8/Bank1 4Mx8/Bank2 4Mx8/Bank3 Mode Register Row Decoder 16 8 Input Buffer Output Buffer 8 DS 2-bit Prefetch Unit DQ [0:7] Column Decoder ADD BA0. 0.5 /Apr.BA1 DQS Address Buffer Column Address Counter CLK_DLL DS CLK /CLK DLL Block Data Strobe Transmitter Data Strobe Receiver Mode Register Rev. 2006 7 .

BA1 Address Buffer Column Address Counter CLK_DLL LDQS UDQS CLK /CLK DLL Block Data Strobe Transmitter Data Strobe Receiver LDQS.HY5DU28422ET HY5DU28822ET HY5DU281622ET FUNCTIONAL BLOCK DIAGRAM (8Mx16) 4Banks x 2Mbit x 16 I/O Double Data Rate Synchronous DRAM Write Data Register 2-bit Prefetch Unit 32 CLK /CLK CKE /CS /RAS /CAS /WE LDM UDM Bank Control Command Decoder 2Mx16/Bank0 Sense AMP 2Mx16/Bank1 2Mx16/Bank2 2Mx16/Bank3 Mode Register Row Decoder 32 16 Input Buffer Output Buffer 16 DS 2-bit Prefetch Unit DQ[0:15] Column Decoder ADD BA0. 0. UDQS Mode Register Rev. 2006 8 .5 /Apr.

Last Data-In to Precharge delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 2.4 1. then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n). OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. LDM/UDM states are Don’t Care. Before entering Mode Register Set mode.2 1.3 1 1. If a Read with Autoprecharge command is detected by memory component in CK(n). If A10/AP is High when Precharge command being issued.5 1 1 1 1 X 1 1 X 1 1 1 1 X 1 1 H X L H L L CA V X V H H H H L X X H L H L L L L H L H L H L H L L H L L X H X H X H X V X H H L L X H X H X H X V L L H H X H X H X H X V X Entry Precharge Power Down Mode Exit H L L H Active Power Down Mode Entry Exit H L L H ( H=Logic High Level. X=Don’t Care.5 /Apr. BA0/BA1 are ignored and all banks are selected to be precharged. NOP=No Operation ) Note: 1.HY5DU28422ET HY5DU28822ET HY5DU281622ET SIMPLIFIED COMMAND TRUTH TABLE Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X ADDR A10/ AP OP code OP code X V V BA Note 1. V=Valid Data Input. Refer to below Write Mask Truth Table. then there will be no command presented to activated bank until CK(n+BL/2+tRP).2 1 1 1 1. 5. 2006 9 . 0. 3. OP Code=Operand Code. L=Logic Low Level. Rev. all banks must be in a precharge state and MRS command can be issued after tRP period from Precharge command.

/WE X X DM L H ADDR A10/AP X X BA Note 1 1 Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. /RAS.HY5DU28422ET HY5DU28822ET HY5DU281622ET WRITE MASK TRUTH TABLE Function Data Write Data-In Mask CKEn-1 H H CKEn X X /CS. /CAS.5 /Apr. 0. 2006 10 . Rev.

AP X OPCODE X X X BA. AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP Action NOP or power down3 NOP or power down3 ILLEGAL4 ILLEGAL4 ILLEGAL4 Row Activation NOP Auto Refresh or Self Refresh5 Mode Register Set NOP NOP ILLEGAL4 Begin read: optional AP6 Begin write: optional AP6 ILLEGAL4 Precharge7 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end Terminate burst Term burst. CA. AP BA. AP X OPCODE X X X BA. AP BA. RA BA. AP BA. CA. AP BA. precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL4 Term burst. new read:optional AP8 Term burst. CA. AP X OPCODE X X X BA. AP BA. CA. 0. RA BA. CA. AP BA. new write:optional AP 11 . CA. CA.5 /Apr. 2006 /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L Address X X X BA. RA BA. CA. new read:optional AP8 ILLEGAL ILLEGAL4 Term burst. AP BA.HY5DU28422ET HY5DU28822ET HY5DU281622ET OPERATION COMMAND TRUTH TABLE-I Current State /CS H L L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L WRITE L L L Rev.

AP BA.10 NOP-Enter IDLE after tRP ILLEGAL11 ILLEGAL11 Rev. AP BA.10 ILLEGAL4. AP X OPCODE X X X BA. AP BA.10 ILLEGAL4. CA. RA BA.10 ILLEGAL4. AP X OPCODE Command ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL4 Term burst. RA BA. AP X OPCODE X X X BA. RA BA. 0.5 /Apr.10 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4. RA BA. AP BA. AP X OPCODE X X X BA. precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4. AP BA.HY5DU28422ET HY5DU28822ET HY5DU281622ET OPERATION COMMAND TRUTH TABLE-II Current State /CS L WRITE L L L H L L READ WITH AUTOPRECHARGE L L L L L L H L L WRITE AUTOPRECHARGE L L L L L L H L L L PRECHARGE L L L L L /RAS L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /CAS H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L /WE H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address BA. CA. CA. CA. CA.10 ILLEGAL11 ILLEGAL11 NOP-Enter IDLE after tRP NOP-Enter IDLE after tRP ILLEGAL4 ILLEGAL4. CA. 2006 12 .10 ILLEGAL4. AP BA.

Enter precharge after tDPL NOP . 2006 13 .HY5DU28422ET HY5DU28822ET HY5DU281622ET OPERATION COMMAND TRUTH TABLE-III Current State /CS H L L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L H L L WRITE RECOVERING WITH AUTOPRECHARGE L L L L L L H L REFRESHING L L /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H Address X X X BA.5 /Apr.Enter ROW ACT after tWR ILLEGAL4 ILLEGAL ILLEGAL ILLEGAL4. CA. RA BA.11 ILLEGAL11 ILLEGAL11 NOP . AP X OPCODE X X X BA. AP BA. 0.Enter IDLE after tRC NOP . CA.10 ILLEGAL4. CA. AP BA. AP BA.10 ILLEGAL4.10 ILLEGAL4. CA.10 ILLEGAL4.Enter ROW ACT after tWR NOP . AP BA. CA.Enter precharge after tDPL ILLEGAL4 ILLEGAL4. AP X OPCODE X X X BA. AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP Action NOP . RA BA.10 ILLEGAL4.8.11 ILLEGAL11 ILLEGAL11 NOP . AP BA.10 ILLEGAL11 ILLEGAL11 NOP . AP BA. CA. AP X OPCODE X X X BA.10 ILLEGAL4.Enter IDLE after tRC ILLEGAL11 ILLEGAL11 Rev.10 ILLEGAL4.Enter ROW ACT after tRCD NOP .Enter ROW ACT after tRCD ILLEGAL4 ILLEGAL4.9. CA. RA BA.

AP BA. H . Rev. 2006 14 . CA. RA BA. bus turn around. 11.Bank Address.HY5DU28422ET HY5DU28822ET HY5DU281622ET OPERATION COMMAND TRUTH TABLE-IV Current State /CS L L WRITE L L L H L L L MODE REGISTER ACCESSING L L L L L /RAS H L L L L X H H H H L L L L /CAS L H H L L X H H L L H H L L /WE L H L H L X H L H L H L H L Address BA.Column Address.Enter IDLE after tMRD NOP . Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank. then in power down mode. RA BA. and/or write recovery requirements. 9. Illegal for single bank.AutoPrecharge Address. V .Logic Low Level. AP . but legal for other banks in multi-bank devices. X . CA . If both banks are idle and CKE is inactive(low level). BA . RA . 5. 8. Illegal to bank in specified state. then self refresh mode. 10. AP BA. Illegal if tRCD is not met.Valid Data Input. 0. Must satisfy bus contention.Row Address.NO Operation. CA. 6.5 /Apr. 7. Illegal if tRRD is not met. NOP . AP BA. 3. CA.Enter IDLE after tMRD ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 Note: 1. 2. L . All entries assume that CKE was active(high level) during the preceding clock cycle. Illegal for all banks. AP X OPCODE X X X BA. AP X OPCODE Command WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 NOP . 4.Don’t Care.Logic High Level. If both banks are idle and CKE is inactive(low level). Illegal if tRAS is not met.

1. all DQ and DQS must be in Hi-Z state. 0.HY5DU28422ET HY5DU28822ET HY5DU281622ET CKE FUNCTION TRUTH TABLE Current State CKEn1 H L SELF REFRESH1 L L L L L H L POWER DOWN2 L L L L L H H H ALL BANKS IDLE4 H H H H H L ANY STATE OTHER THAN ABOVE H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X L H L L L L L X X X X X /RAS X X H H H L X X X H H H L X X L X H H H L L X X X X X /CAS X X H H L X X X X H H L X X X L X H H L H L X X X X X /WE X X H L X X X X X H L X X X X H X H L X X L X X X X X /ADD X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit self refresh. enter idle Exit power down. Rev. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command. 3.5 /Apr. 4. continue self refresh INVALID Exit power down. Self refresh can be entered only from the all banks idle state. 2006 15 . Disabling CLK may cause malfunction of any bank which is in active state. continue power down mode See operation command truth table Enter self refresh Exit power down Exit power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP See operation command truth table ILLEGAL5 INVALID INVALID Note: When CKE=L. enter idle ILLEGAL ILLEGAL ILLEGAL NOP. Illegal if CLK is suspended or stopped during the power down mode. enter idle after tSREX Exit self refresh. enter idle after tSREX ILLEGAL ILLEGAL ILLEGAL NOP. 2. All command can be stored after 2 clocks from low to high transition of CKE. 5.

0.5 /Apr.HY5DU28422ET HY5DU28822ET HY5DU281622ET SIMPLIFIED STATE DIAGRAM Pow er A p p lie d Pow er On P re c h a rg e PREALL REFS REFSX MRS EM RS MRS S e lf R e fre s h Id le REFA A u to R e fre s h CKEL CKEH A c t iv e Power Down ACT P re c h a rg e Pow er Down CKEH CKEL B u rs t S to p Read Read W r ite A W r it e Read A Read Read Row A c t iv e W r it e W r it e W r it e A Read A W r it e A PRE PRE PRE Read A Read A PRE P re c h a rg e PR EALL A u t o m a t ic S e q u e n c e Com m and Sequence P R E A L L = P r e c h a r g e A ll B a n k s M R S = M o d e R e g is t e r S e t E M R S = E x t e n d e d M o d e R e g is t e r Set R E F S = E n t e r S e lf R e f r e s h R E F S X = E x it S e lf R e f r e s h R E F A = A u to R e f r e s h C K E L = E n te r P o w e r D o w n C K E H = E x it P o w e r D o w n A C T = A c tiv e W r ite A = W r it e w it h A u t o p r e c h a r g e R e a d A = R e a d w ith A u t o p r e c h a r g e P R E = P re c h a rg e Rev. 2006 16 .

VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable. Next a EXTENDED MODE REGISTER SET command should be issued for the Extended Mode Register. the DDR SDRAM is ready for normal operation. Following these cycles. VDDQ. and to program the operating parameters.5 /Apr.e. • VREF tracks VDDQ/2. Once the 200us delay has been satisfied. the DDR SDRAM requires a 200us delay prior to applying an executable command. Rev. Additionally.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation. Issue Extended Mode Register Set (EMRS) to enable DLL. 0. Except for CKE. VTT must be applied after VDDQ to avoid device latch-up. then to VDDQ. inputs are not recognized as valid until after VREF is applied. which may cause permanent damage to the device. 1. and the clock is stable. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state. Once in the idle state. VTT. apply NOP condition and take CKE high. Power must first be applied to VDD. 5. and CKE should be brought HIGH. Following the NOP command. to enable the DLL.3V < VDDQ + 0.) • VDD and VDDQ are driven from a single power converter output. VREF can be applied anytime after VDDQ.3V < VDDQ + 0. 3. Operational procedures other than those specified may result in undefined operation. two AUTO REFRESH cycles must be performed. to reset the DLL. Apply power . (All the other input pins may be undefined. After stable power and clock.VDD. Sequencing After or with VDD After or with VDDQ After or with VDDQ Voltage relationship to avoid latch-up < VDD + 0.5% tolerance) limits the input current from the VTT supply into any pin. a MODE REGISTER SET command for the Mode Register.HY5DU28422ET HY5DU28822ET HY5DU281622ET POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. but is expected to be nominally coincident with VTT. to program operating parameters without resetting the DLL) must be performed. • If the above criteria cannot be met by the system design. tXSRD(DLL locking time) should be satisfied for read command. • A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor . 6. 4. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. but will detect an LVCMOS LOW level after VDD is applied.3V Start clock and maintain stable clock for a minimum of 200usec. After the DLL reset. CKE is an SSTL_2 input. After the Mode Register set command. placing the device in the all banks idle state. • VTT is limited to 1. 2006 17 . (An additional 200 cycles(tXSRD) of clock are required for locking DLL) Issue Precharge commands for all banks of the device. then the following sequencing and voltage relationship must be adhered to during power up. and finally to VREF (and to the system VTT). with the reset DLL bit deactivated low (i. a PRECHARGE ALL command should be applied. a DESELECT or NOP command should be applied. then a MODE REGISTER SET command should be issued for the Mode Register. a PRECHARGE ALL command should be applied. Voltage description VDDQ VTT VREF 2.

Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS tIH CKE LVCMOS Low Level CMD NOP PRE EMRS MRS NOP PRE AREF MRS ACT RD DM ADDR CODE CODE CODE CODE CODE A10 CODE CODE CODE CODE CODE BA0.5 /Apr. 8.HY5DU28422ET HY5DU28822ET HY5DU281622ET 7. Issue 2 or more Auto Refresh commands. 2006 18 . 0. BA1 CODE CODE CODE CODE CODE DQS DQ'S T=200usec tRP tMRD tMRD tRP tRFC tXSRD* Power UP VDD and CK stable Precharge All EMRS Set MRS Set Reset DLL (with A8=H) Precharge All 2 or more Auto Refresh MRS Set (with A8=L) Non-Read Command READ tMRD * 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command Rev. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.

/CAS. /CS.5 2. During the MRS cycle. /WE and BA0. Two cycles are required to write the data in mode register. Once mode register field is determined. 0. DLL reset. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued.5 /Apr. 2006 19 . burst type. The mode register is programed via MRS command. test mode. BA1 0 BA0 0 A12 A11 A10 A9 A8 A7 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0 Operating Mode BA0 0 1 MRS Type MRS EMRS A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved 1. any command cannot be issued.HY5DU28422ET HY5DU28822ET HY5DU281622ET MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency. the information will be held until reset by another MRS command. This command is issued by the low signals of /RAS. burst length. addressing mode.5 Reserved A2 A1 A3 0 1 Burst Type Sequential Interleave Burst Length A0 Sequential 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved A12~A9 0 0 0 - A8 0 1 0 - A7 0 0 1 - A6~A0 Valid Valid VS Operating Mode Normal Operation Normal Operation/ Reset DLL 0 1 1 1 1 Vendor specific Test Mode All other states reserved Rev.

2. 2. 1. 2. 3. 6. 4. 7. 1. 2 2. 5. 7. 2006 20 . 2. 4. as unknown operation or incompatibility with future versions may result. 7. 3.5 /Apr. 0. 1. 1. 0. 0 0. 4. 6 0. 5. 0. 1. 0 2. When a Read or Write command is issued. 3. a block of columns equal to the burst length is effectively selected. 3. 5. 1. 3. 2 0. Accesses within a given burst may be programmed to be either sequential or interleaved. 0 Interleave BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented. 5. The block is uniquely selected by A1-Ai when the burst length is set to two. 5. 3 1. 0. 2. 1. 6. 5. 5. 6. 3 5. Reserved states should not be used. 2. 3. Burst lengths of 2. 2. this is referred to as the burst type and is selected via bit A3. 1 7. 1 1. 4. 0. 0. 6. the burst type and the starting column address. 7. 7 1. 7. 1. 0. 3. 5 3. 2. 7. 4. All accesses for that burst take place within this block. 3. 5. 2. 4. 0. The ordering of accesses within a burst is determined by the burst length. 0. 7. 1 3.HY5DU28422ET HY5DU28822ET HY5DU281622ET BURST DEFINITION Burst Length 2 Starting Address (A2. 3. 4 6. 1 1.A1. 0 0. 3. 6. 4. 1. 2 6. or 8 locations are available for both the sequential and the interleaved burst types. 6. 1 3. 3. 3. 4. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. 1. 2 4. 4 4. 6. 7. 4. 0. 0. 7. 2. 5. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. 6.A0) XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 Sequential 0. 4. 7 1. 2. 6. with the burst length being programmable. 3. 2. as shown in Burst Definitionon Table Rev. 7. 3. 1. 2. 6. meaning that the burst wraps within the block if a boundary is reached. 6. 1. 0 0. 5. 3 5. 2. 5 7. 1 3. 3. 0. 0. 0. 1. 0. 6 2. 5. 1. 7. 1. 4. 3 1. 2. 4. 2. by A 2 -Ai when the burst length is set to four and by A 3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). 5. 0. 3. The programmed burst length applies to both Read and Write bursts. 1. 4. 0. 0 2. 6. 7.

the data is available nominally coincident with clock edge n + m. I-V curves for both the full strength driver and the half strength driver are included in this document. DLL enable is required during power up initialization. Reserved states should not be used as unknown operation or incompatibility with future versions may result. and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. OUTPUT DRIVER IMPEDANCE CONTROL The normal drive strength for all outputs is specified to be SSTL_2. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation.HY5DU28422ET HY5DU28822ET HY5DU281622ET CAS LATENCY The Read latency. and the latency is m clocks. Rev. The latency can be programmed 2 / 2. Class II. intended for lighter load and/or point-to-point environments. between the registration of a Read command and the availability of the first burst of output data. or CAS latency. DLL RESET The DLL must be enabled for normal operation. is the delay. 0. Hynix also supports a half strength driver option. Selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. Any time the DLL is enabled. If a Read command is registered at clock edge n.5 /Apr.5 / 3 clocks. 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued. in clock cycles. 2006 21 .

2006 22 . output driver strength selection(optional). Rev. these additional functions include DLL enable/disable. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress.5 /Apr. BA1 0 BA0 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 0* A1 DS A0 DLL Operating Mode BA0 0 1 MRS Type MRS EMRS A0 0 1 DLL enable Enable Disable A1 0 1 Output Driver Impedance Control Full Strength Driver Half Strength Driver An~A3 0 _ A2~A0 Valid _ Operating Mode Normal Operation All other states reserved * This part do not support/QFC function. The Extended Mode Register is programmed via the Mode Register Set command (BA0=1 and BA1=0) and will retain the stored information until it is programmed again or the device loses power.HY5DU28422ET HY5DU28822ET HY5DU281622ET EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register. 0. Violating either of these requirements will result in unspecified operation. and the controller must wait the specified time before initiating any subsequent operation. A2 must be programmed to Zero. These functions are controlled via the bits shown below.

CK and CK inputs Input Differential Voltage. VREF is expected to be equal to 0. max VREF.5 ~ 3. CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input Leakage Current Output Leakage Current Normal Strength Output Driver (VOUT=VTT ± 0. VDDQ must not exceed the level of VDD.0.71 -2 -5 -16.3 VREF . 4.5*VDDQ of the transmitting device.15 -0.68) Output High Current (min VDDQ. 0. min VTT) Output Low Current (min VDDQ.04 0.3 0.0.HY5DU28422ET HY5DU28822ET HY5DU281622ET ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature ⋅ Time Symbol TA TSTG VIN.7 2. for device drain to source voltages from 0. max VREF. Voltage referenced to VSS = 0V) Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage Input Voltage Level. max VTT) Half Strength Output Driver (VOUT=VTT ± 0.36 0.3 VREF .6 -0. All other pins are not tested under VIN =0V. 6.5 2. 2. max VTT) Note: 1. Rev. min VTT) Output Low Current (min VDDQ.5*VDDQ - Max 2.8 -13. 3. VIL (min) is acceptable -1.6 -0.7 VDDQ + 0. VIN=0 to VDD.6 13. over the entire temperature and voltage range.5V AC pulse width with < 5ns of duration. 2.3 VREF + 0.2% of the dc value. For a given output. it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0. 5.5 /Apr.15 VREF + 0.6 50 1 260 ⋅ 10 o Unit o C oC V V V mA W C ⋅ sec Note: Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC.04 0. 2006 23 . min VREF. and to track variations in the dc level of the same.1 to 1.84) Symbol VDD VDDQ VIH VIL VTT VREF VIN(DC) VID(DC) VI(RATIO) ILI ILO IOH IOL IOH IOL Min 2. VID is the magnitude of the difference between the input level on CK and the input level on /CK.5 ~ 3. Peak to peak noise on VREF may not exceed +/.51*VDDQ VDDQ+0. min VREF.49*VDDQ -0.6 Typ.3 VDDQ+0.0.5 VREF 0.6 1.3 2. DQs are disabled.4 2 5 - Unit V V V V V V V V uA uA mA mA mA mA Note 1 2 3 4 5 6 7 Output High Current (min VDDQ.8 16. VOUT=0 to VDDQ. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage.5 ~ 3.0V.25V to 1. VOUT VDD VDDQ IOS PD TSOLDER Rating 0 ~ 70 -55 ~ 125 -0. 7.

address and control inputs changing once per clock cycle.8*tCK for DDR200 at 100Mhz. One bank active.Read . External clock on. 10*tCK for DDR266A & DDR266B at 133Mhz.DM and DQS inputs changing twice per clock cycle.Precharge. Reads. Power down mode. DM and DQS inputs changing twice per clock cycle.5 /Apr. Address and control inputs changing once per clock cycle. Burst=2. One bank active. address and control inputs changing once per clock cycle One bank. DQ. Continuous burst. CKE=High. tCK=tCK(min). ActivePrecharge.HY5DU28422ET HY5DU28822ET HY5DU281622ET IDD SPECIFICATION AND CONDITIONS 32Mx4 / 16Mx8 / 8Mx16 Parameter Symbol Test Condition (TA=0 to 70 oC. tCK=tCK(min). All banks idle. address and control inputs changing once per clock cycle All banks idle. CKE=Low.Precharge. DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) . Active . tCK=tCK(min) /CS=High. Address and control inputs changing once per clock cycle. DQ. CKE=Low. Active . Refer to the following page for detailed test condition 110 100 90 mA Operating Current IDD1 110 100 90 mA Precharge Power Down Standby Current IDD2P 20 15 15 mA Idle Standby Current IDD2F 50 45 40 mA Active Power Down Standby Current IDD3P 20 20 20 mA Active Standby Current IDD3N 60 50 40 mA Operating Current IDD4R 160 150 140 mA Operating Current IDD4W 160 150 140 mA Auto Refresh Current IDD5 180 170 160 mA Self Refresh Current Operating Current Four Bank Operation IDD6 IDD7 2 250 2 230 2 200 mA mA Rev. Voltage referenced to VSS = 0V) Speed -J -M -K -H -L Unit Note Operating Current IDD0 One bank. tRC=tRAS(max). tRC=tRC(min). VIN=VREF for DQ. Power down mode. DQ. CKE=HIGH. One bank. tCK=tCK(min).2V. 0. tCK=tCK(min). tCK=tCK(min) /CS=HIGH. tCK=tCK(min) Four bank interleaving with BL=4. 2006 24 . tCK=tCK(min). tRC=tRC(min). Writes. Continuous burst. distributed refresh CKE=<0. IOUT=0mA Burst=2. tCK=tCK(min). Address and other control inputs changing once per clock cycle Burst=2. DQS and DM One bank active.

5ns. tRAS = 7*tCK Read: A0 N N R0 N N N P0 N N A0 N . BL=2.5 /Apr. BL=4. BL=2.HY5DU28422ET HY5DU28822ET HY5DU281622ET DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1: Operating current: One bank operation 1. tRCD = 3*tCK Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 .DDR333(166Mhz. P=Precharge.DDR333(166Mhz. CL=2): tCK = 7. CL=2.5): tCK = 7. CL2=2.DDR266B(133Mhz.DDR266B(133Mhz. tRCD = 2*tCK. W=Write. CL=2. CL=2. lout = 0mA 2. CL=2. Timing patterns . tRCD = 3*tCK Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 .5. CL=2.5. BL=4. tRRD = 2*tCK. CL=2): tCK = 7. 2006 25 . tRC = 8*tCK. BL=2.5ns.repeat the same timing with random address changing 50% of data changing at every burst .repeat the same timing with random address changing 50% of data changing at every burst Legend: A=Activate. CL2.DDR200(100Mhz. CL=2): tCK = 10ns. tRAS = 6*tCK Read: A0 N N R0 N P0 N N N A0 N . 0. tRCD = 3*tCK.5ns. CL=2. tRCD= 3*tCK.5ns.repeat the same timing with random address changing 50% of data changing at every burst Legend: A=Activate. CL=2.DDR200(100Mhz. tRRD = 2*tCK. CL=2. tRCD = 2*tCK.repeat the same timing with random address changing 50% of data changing at every burst . R=Read. tRAS = 6*tCK Read: A0 N R0 N N N P0 N A0 N . Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 . lout = 0mA 2. tRRD = 2*tCK. tRRD = 2*tCK. Timing patterns . tRAS = 5*tCK Read: A0 N R0 N N P0 N A0 N . BL=2. CL=2. P=Precharge. Address and Control inputs on NOP edge are not changing.repeat the same timing with random address changing 50% of data changing at every burst . W=Write. BL=2.DDR266A (133Mhz. Address and Control inputs on NOP edge are changing once per clock cycle.5): tCK = 6ns. Only one bank is accessed with tRC(min).5): tCK = 7. BL=4. Burst Mode. Four banks are being interleaved with tRC(min).5. BL=4. tRC = 9*tCK.5): tCK = 6ns. tRAS = 6*tCK Read: A0 N N R0 N P0 N N N A0 N .DDR266A (133Mhz. tRCD = 3*tCK.DDR266(133Mhz. CL=2): tCK = 7. CL=2): tCK = 10ns. CL2.repeat the same timing with random address changing . Read with Autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 . N=NOP Rev. tRCD = 3*tCK.repeat the same timing with random address changing 50% of data changing at every burst . tRCD = 3*tCK.5ns.repeat the same timing with random address changing 50% of data changing at every burst . R=Read. N=NOP IDD7: Operating current: Four bank operation 1. CL=2. Burst Mode. tRC = 10*tCK.repeat the same timing with random address changing 50% of data changing at every burst . tRC = 9*tCK.

2 Max Unit V V V V 1 2 Note Note: 1. max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.6 0.31 VREF . 2006 26 .5 1 50 25 30 Unit V V V V V V V V/ns Ω Ω pF Rev. Voltage referenced to VSS = 0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH.0.31 VREF .7 0. 2.2 Min VREF + 0.5 VREF + 0.5*VDDQ+0. DQS and DM signals Input Low (Logic 0) Voltage. CK and /CK inputs Input Crossing Point Voltage.31 VDDQ + 0. The value of VIX is expected to equal 0.5 /Apr. Voltage referenced to VSS = 0V) Parameter Input High (Logic 1) Voltage. DQ.HY5DU28422ET HY5DU28822ET HY5DU281622ET AC OPERATING CONDITIONS (TA=0 to 70 oC. AC OPERATING TEST CONDITIONS (TA=0 to 70oC. DQ. CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.5 VDDQ x 0.0.31 VREF VTT 1.5*VDDQ-0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. min) AC Input Low Level Voltage (VIL. DQS and DM signals Input Differential Voltage. VID is the magnitude of the difference between the input level on CK and the input on /CK. 0.

4V-ns VDD GND Undershoot Time(ns) Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition Rev.ns 4.2V 2.HY5DU28422ET HY5DU28822ET HY5DU281622ET AC Overshoot/Undershoot Specification for Address and Control Pins This specification is intended for devices with no clamp protection and is guaranteed by design Parameter Maximum peak amplitude allowed for overshoot (See Figure 1): Maximum peak amplitude allowed for undershoot (See Figure 1): The area between the overshoot signal and VDD must be less than or equal to (See Figure 1): The area between the undershoot signal and GND must be less than or equal to (See Figure 1): 5 4 3 Max.4V . area = 2. amplitude = 1.2V 1.ns 2. 2006 27 .5V 1.ns 2. 0.4V .4V .5V . amplitude = 1.5 /Apr.5V-ns VDD GND Undershoot Time(ns) Figure 1: Address and Control AC Overshoot and Undershoot Definition Overshoot/Undershoot Specification for Data. and Mask Pins Parameter Maximum peak amplitude allowed for overshoot (See Figure 2): Maximum peak amplitude allowed for undershoot (See Figure 2): The area between the overshoot signal and VDD must be less than or equal to (See Figure 2): The area between the undershoot signal and GND must be less than or equal to (See Figure 2): 5 4 3 Max.2V 1.ns DDR200/266 1.5V .5V .5V 1.5V 4.2V Specification DDR333 1. area = 4.4V .ns 4. Strobe.5V .ns Overshoot Volts(V) 2 1 0 -1 -2 -3 0 1 2 3 4 5 6 Max.5V Specification DDR333 1.ns DDR200/266 1.ns Overshoot Volts(V) 2 1 0 -1 -2 -3 0 1 2 3 4 5 6 Max.2V 2.5V 4.

2006 28 .6 tHP -tQHS min (tCL.55 0.7 0.45 0.HY5DU28422ET HY5DU28822ET HY5DU281622ET AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time CL = 3 System Clock Cycle Time CL = 2.7 -0.6 2.3.45 -0.3. /CK Data-out low-impedance window from CK.75 -0.55 Max 120K 12 12 0.5 CL = 2 Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Valid Data Output Window Data-out high-impedance window from CK.55 0.55 0.75 0.75 -0.75 0.75 0.5 0.75 0.9 0.9 10 15 16 6 7. /CK Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tDV tHZ tLZ tIS tIH tCK Symbol tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL DDR333 Min 60 72 42 18 18 12 1 18 15 1 (tWR/tCK) + (tRP/tCK) 6 <DDR333.7 0.75 Unit Note ns ns ns ns ns ns CK ns ns CK CK ns ns ns CK CK ns ns ns ns ns ns ns ns ns ns ns 17 17 2.45 0.55 0.5 /Apr. DDR266(2-2-2)> DDR266(2-2-2) Min 60 75 45 15 15 15 1 15 15 1 (tWR/tCK) + (tRP/tCK) - Max 70K 12 12 12 0.tCH) - 7.45 -0.5.7 0.7 -0. 0.75 0.75 tHP -tQHS min (tCL.9 0.5 7.6 0.tCH) - tQH-tDQSQ -0.5 0.75 - Rev.7 - tQH-tDQSQ -0. 10 1.5.45 0.6 1.5 0.75 0.

6 0.9 0.0 1.9 0.35 0.35 0.8 0.72 0.25 0.4 2 200 1.6 Max - Parameter Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Symbol tIS tIH tIPW tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI Unit Note ns ns ns CK CK CK ns ns ns CK CK CK CK CK CK CK us 2.5.5.6 15.45 0.25 1. 2006 29 .4 2 200 1.8 2.45 1.75 0.1 0.1 0.6 15.7.2 0.75 0.6 2. 11~13 6.2 0.28 1.0 2.35 0.5 /Apr.6 6 6.7.35 0.75 0.4 0 0.4 0 0. 0.5 1.4.HY5DU28422ET HY5DU28822ET HY5DU281622ET DDR333 Min 0.4.6 Max DDR266(2-2-2) Min 1.25 0.5 0.6 0. 11~13 8 Rev.

2006 30 .5 0.55 0.45 -0.55 0.55 0.45 0.45 0.75 0.75 0.tCH) - tQH-tDQSQ -0.5 0.8 Rev. /CK CL = 2.75 tQH-tDQSQ -0.75 -0.5 /Apr.5 7.8 -0.5 CL = 2 Symbol tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL DDR266A Min 65 75 45 20 20 15 1 20 15 1 (tWR/tCK) + (tRP/tCK) <DDR266A/B. /CK Data-out low-impedance window from CK.8 0.tCH) - 7.45 -0.8 -0.9 10 15 16 tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tDV tHZ tLZ 7.75 Max 120K 12 12 0.8 tHP -tQHS min (tCL.HY5DU28422ET HY5DU28822ET HY5DU281622ET AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Valid Data Output Window Data-out high-impedance window from CK.55 0.55 0. DDR200> DDR266B Min 65 75 45 20 20 15 1 20 15 1 (tWR/tCK) + (tRP/tCK) DDR200 Min 70 80 50 20 20 15 1 20 15 1 (tWR/tCK) + (tRP/tCK) Max 120K 12 12 0.45 -0.75 Unit Note ns ns ns ns ns ns CK ns ns CK CK ns ns CK CK ns ns ns ns ns ns ns ns ns 17 17 1.75 tHP -tQHS min (tCL.5 10 0.75 0.6 0.tCH) - 8.75 -0.5 0.75 -0.75 0.45 0.55 0.75 -0.75 Max 120k 12 12 0. 0.75 tHP -tQHS min (tCL.75 tQH-tDQSQ -0.8 0.75 0.75 0.0 10 0.75 0.8 0.75 0. 10 1.8 0.

4.4 0 0.9 0.2 0.7.75 0.0 1.6 15.35 0.25 0.6 2.5 1.25 0.6 Max DDR200 Min 1.HY5DU28422ET HY5DU28822ET HY5DU281622ET -continuedDDR266A Min 0.4 2 200 1.35 0.9 1.4 2 200 Max 1.5.6 0.6 2 0.9 0.75 0.4.1 1.5 0.35 0.1 0.0 2. 11~13 8 Rev.5.25 1.6 Max DDR266B Min 0.75 0.6 6 6.5 0.6 15.9 0.0 2.1 2.35 0.5 1.1 1.6 2.3.75 0.5.1 0.5.5 0.4 2 200 1.4 0 0. 0.25 1.35 0.1 0.0 1.6 0.6 0.6 2.2 0.9 0.4 0 0.25 0.1 1. 2006 31 .9 0.9 1.35 0.5 /Apr.6 15.3.75 0.25 1.6 0.6 Parameter Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Symbol tIS tIH tIS tIH tIPW tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI Unit Note ns ns ns ns ns CK CK CK ns ns ns CK CK CK CK CK CK CK us 2.

CK.5V/ns.3 Delta tDS ps 0 +75 +150 Delta tDH ps 0 +75 +150 12. /CK slew rates are>=1. the pulse width distortion of on-chip circuit and jitter. 4. Input Setup / Hold Slew-rate Derating Table. 6. is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.4 0. /CAS. tQHS consists of tDQSQmax.5V/ns and <1. this value can be greater than the minimum specification limits for tCL and tCH).4V/n then the Delta Inverse Slew Rate=-0. 8. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS): DQ.25 +/. Input Setup / Hold Slew-rate Derating Table. 2006 32 .0. Input Setup / Hold Slew-rate V/ns 0. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.3 5. tCL). /CS. I/O Setup/Hold Plateau Derating.5 0. Input Setup / Hold Slew-rate V/ns 0. 11.5V/ns and Slew Rate2=0. This calculation accounts for tDQSQ(max). LDM/UDM. 7. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). but they are not necessarily tested on each device. I/O Setup/Hold Delta Inverse Slew Rate Derating. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command.5 Delta tDS ps 0 +50 +100 Delta tDH ps 0 +50 +100 Rev. For command/address input slew rate>=1. where CKE is held high.0V/ns This Derating Table is used to increase tIS/tIH in case where the input slew-rate is below 0. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level mV +280 Delta tDS ps +50 Delta tDH ps +50 13. tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i. 2. Delta tIS ps 0 +50 +100 Delta tIH ps 0 0 0 10.e.5ns/V. 3.0V/ns These parameters guarantee device timing. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH. /RAS.0V/ns For command/address input slew rate>=0.5V/ns.4 0.HY5DU28422ET HY5DU28822ET HY5DU281622ET Note: 1. and they may be guaranteed by design or tester correlation. Min (tCL.5 /Apr. For example. BA0~BA1. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. 9. 0. (1/SlewRate1)-(1/SlewRate2) ns/V 0 +/-0. the pulse width distortion of on-chip clock circuits. Data sampled at the rising edges of the clock: A0~A11. if slew rate 1= 0.5 0. CKE. /WE. data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers.

tCK is equal to the actual system clock cycle time.5 ns) + (20 ns / 7.67) Round up each non-integer to the next highest integer: = (2) + (3).00) + (2.5 ns) = (2. or begins driving (LZ).5 and tCK = 7. 15. Example: For DDR266B at CL=2. 17. Rev. DQS. Signal transitions through the DC region must be monotonic. tDAL = (tDPL / tCK) + (tRP / tCK). 0. For the parts which do not has internal RAS lockout circuit.5 ns.(BL/2) x tCK. round to the next highest integer. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ). tDAL = 5 clocks 16.HY5DU28422ET HY5DU28822ET HY5DU281622ET 14. tDAL = (15 ns / 7. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. Active to Read with Auto precharge delay should be tRAS . 2006 33 . For each of the terms above. if not already an integer.5 /Apr. DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.

HY5DU28422ET HY5DU28822ET HY5DU281622ET CAPACITANCE (TA=25oC. 2006 34 .25 3.0 2.5 5. DQS.. to max. VDDQ = 2. Pins not under test are tied to GND.0 0.2V 2. DM Pin Symbol CI1 Delta CI1 CI1 Delta CI2 CIO Delta CIO Min 2.0 0. /CK CK. OUTPUT LOAD CIRCUIT VTT RT=50Ω Output Zo=50Ω VREF CL=30pF Rev. 0. VDD = min.0 4. DM DQ. 3. DQS.5 /Apr.7V. VODC = VDDQ/2.5 Unit pF pF pF pF pF pF Note: 1. f=100MHz) Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitance Delta Input / Output Capacitance CK. These values are guaranteed by design and are tested on a sample basis only.0 Max 3.0 0. VOpeak-to-peak = 0. /CK All other input-only pins All other input-only pins DQ.3V to 2.

0059) 0.396) BASE PLANE 22.210 (0.25 (0.194 (0.65 (0.05 (0. Rev. 0.879) 22.0083) 0.120 (0.33 (0.79 (0. 2006 35 .871) 0 ~ 5 Deg. Allowable protrusion of both sides is 0.404) 10.05 (0.HY5DU28422ET HY5DU28822ET HY5DU281622ET PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package Unit : mm(Inch) 11.4mm.406 (0.0098) SEATING PLANE 0.470) 11.462) 10.12 (0.5 /Apr.0160) 0.0390) Note: Package do not mold protrusion.35 (0.0470) 0.26 (0. 0.0256) BSC 0.0138) 0.15 (0.94 (0.991 (0.597 (0.0020) 0.0047) 1.0235) 0.

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