Microprocessor Lab Manual - Final

Vidya Vikas College of Engineering and Technology
EXP. NO. 01 (A) Date: _________
TITLE: STUDY OF INTEL 8085 MICROPROCESSOR KIT
Aim : To study the working of Intel 8085 Microprocessor trainer kit.
Figure 1.1 Vimicro’s Micro-85 Microprocessor kit
1.1 INTRODUCTION
This section briefs the hardware and software facilities available in both the trainers
Micro-85 EBl and Micro-85 EB2. Micro-85 EBl is a powerful Microprocessor Trainer
with basic features such as 24 TTL lines using 8255, Hardware Single Stepping and
Software Single Stepping of user programs.
In addition to the above features, Micro-85 EB2 has RS232C compatible serial port,
Bus Expansion for interfacing VBMB series of add-on cards and 24 TTL I/O lines. A
separate switch is provided for learning more about hardware. interrupts. There is
also provision to add multi output power supply for interfacing experiment boards.
Most of the control signals are terminated .at test points for easy analysis on CRO or
logic probe.
EC1307 – Microprocessor & Application Lab - Manual 1

The differences in the specification of Micro-85 EBl and Micro-85 EB2 are highlighted
in this manual. The users are therefore requested to go through the Hardware
specification carefully.
1.2 SPECIFICATIONS
1.2.1 HARDWARE SPECIFICATIONS
1) PROCESSOR, CLOCK FREQUENCY: Intel 8085A at 6.144 MHz clock. .
2) MEMORY:
Monitor EPROM : 0000 - 1FFF
EPROM- Expansion : 2000 - 3FFF & COOO - FFFF
System RAM : 4000 - 5FFF
Monitor Data Area : 4000 - 40FF (Reserved)
User RAM Area : 4100 - 5FFF
RAM- Expansion : 6000 - BFFF
Note: The RAM area from 4000 - 40FF should not be accessed by the
user since it is used as scratch pad by the Monitor program.
3) INPUT/OUTPUT:
Parallel: 48 TTL :I/O lines using two number of 8255
(only 24 :I/O line. available in micro-85 EB1).
Serial : One number of RS232C compatible Serial interface
using 8251A - USART.
Timer : Three channel 16-bit Programmable Timer using 8253.
- Channel 0 is used as baud rate clock generator for 8251A USART.
- Channel 1 is used for in single stepping user programs.
- Channel 2 is used for Hardware Single Stepping user programs.
4) DISPLAY:
- 6 digit, 0.3", 7 Segment Red LED Display with filter.
- 4 digits for address display and 2 digits for data display.
5) KEYBOARD :
- 21 Keys soft keyboard including command keys and hexa-decimal keys.
6) AUDIO CASSETTE INTERFACE with file management.
7) BATTERY BACKUP:
- Onboard Battery backup facility is provided for the available RAM.

8) HARDWARE SINGLE STEP:

This facility allows the user to execute programs at machine cycle level
using a separate switch.
9) SYSTEM POWER CONSUMPTION:

Micro-85 EB2 Micro-85 EBl
+ 5 V @ 1 Amp +5V @ 500 mA
+ 12 V@ 200 mA
- 12 V @ l00 mA
10) POWER SUPPLY SPECIFICATIONS: [External ]

Micro-85 EB2 Micro-85 EB1
Input: 230 V AC @ 50, Hz 230V AC @ 50 Hz
Output: + 5 V @ 1.5 A + 5 V @ 600 mA
+ 12 V @ 150 mA
- 12 V @ 150 mA
+ 30 V @ 250 mA
(Unregulated)
11) PHYSICAL CHARACTERISTICS:

Micro-85 EB PCB : 230mm x 170mm [L x B] Weight : 1 Kg.
12) TEST POINTS: Test points provided

for MR*, MW*, INTA*, IO/M*, IOR*, IOW*, S0, S1, INTA.
This enables the user to study the hardware timing easily.

1.2.2 SOFTWARE SPECIFICATIONS
Micro-S5 EB contains a high performance 8K bytes monitor program. It is designed

to respond to user input, RS232C serial communications, tape interface etc. The
following is a simple description of the key functions. Out of the 21 keys in the
keyboard 16 are hexadecimal, command and register keys and the remaining are
stand-alone keys.
KEY FUNCTION SUMMARY
This RES key allows you to terminate any present activity and to return
your Micro-85 EB to an initialized state. When pressed, the µ..85 sign-
RES on message appears in the display for a few seconds and the monitor
will display command prompt “-“ in the left most digit.
Maskable interrupt connected to CPU's RST 7.5 interrupt.

INT
Decrement the address by one and display it contents

(or)
DEC Display the previous register contents.
Execute a particular program after selecting the address

through GO command.
EXEC
Increment address by one and display its contents

(or)
DEC Display the next register content.
The 16 Hexa decimal keys have either a dual or a triple role to play.
i) It functions as a Hex key entry when a address or data entry is required.
ii) It functions as the Register key entry during Register command.
iii) It functions as command key when pressed directly after command prompt.
NOTE: The Hex-key function summary below is in the order:

i) Hex key.
ii) Command key
iii) Register key.

KEY FUNCTION SUMMARY
i. Hex key entry "0"
0 ii. This key is for substituting memory contents When NEXT key is
E pressed immediate1y after this it takes the user to the start
SUB address for entering user programs, 4100 Hex (User RAM).
iii. Register key "E"
1 i. Hex key entry "1"

D ii. Examine the 8085A registers and modify the same.
REG
iii. Register key "D"
i. Hex key entry "2"

2
C ii. Writes data from memory on to audiotape.
TW
iii. Register key "C"
3 i. Hex key entry “3”

B ii. Retrieve data from an audiotape to memory.
TR
iii. Register key “B”
4 i. Hex key entry “4”.

F ii. Block search for a byte.
BLOC
iii. Register key “F”.
i. Hex key entry “5”.

5
A ii. Fill a block of RAM memory with desired data.
FILL
iii. Register key “A”.

L ii. Transmit/Receive data to/from the serial port.
SER
The TW/TR keys are used for sending/receiving respectively.
iii. Register key “L”.

H
ii. Register key "H"
F2


I
GO ii. Start running a particular program
iii. Register key "I"

PL ii. Single step a program instruction by instruction.
SNG
iii. Register key “PCL”.
i Hex key entry "A"

A
PH ii. Function key F3
F3 F3 [0] = Input a byte from a port
P3 [1] = Output a byte to a port
iii. Register key “PCH"
iv. Used with SNG key for hardware single stepping.
B i Hex key entry "B"

SL ii. Check a particular block for blank.
BC
iii. Register key "SPL"
C i. Hex key entry "C"

SH ii. Move block of memory to another block
MOV
iii. Register key “SPH”
D i. Hex key entry "D"
CMP ii. Compare two memory blocks.
E i. Hex key entry "E"

ii. Insert bytes into memory (RAM) .
INS
F i. Hex key entry "F"

DEL ii. Delete bytes from memory (RAM).

EXP. NO. 01 (B)
TITLE: STUDY OF INTEL 8086 MICROPROCESSOR
FEATURES:
1. 16-bit Data bus
2. Computes 16 bit / 32 bit data.
3. 20-bit address bus.
4. More memory addressing capability (220 = 1MB)
5. 16 bit Flag register with 9 Flags
6. Can be operated in Minimum mode and Maximum mode
7. Has two stage pipelined architecture
8. No internal clock generation
9. 40 pin DIP IC - HMOS technology
10. Operates on +5V supply voltage
11. Has more powerful instruction set
Memory:
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 1MB KB. As the most of the processor instructions use
16-bit pointers the processor can effectively address only 64 KB of memory. To
access memory outside of 64 KB the CPU uses special segment registers to specify
where the code, stack and data 64 KB segments are positioned within 1 MB of
memory (see the "Registers" section below).

16-bit pointers and data are stored as:

address : low-order byte
address+1 : high-order byte
32-bit addresses are stored in "segment:offset" format as:

address : low-order byte of segment
address+1 : high-order byte of segment
address+2 : low-order byte of offset
address+3 : high-order byte of offset
Physical memory address pointed by SEGMENT:OFFSET pair is calculated as:
Physical address = (<Segment Addr> * 16) + <Offset Addr>
Program memory - program can be located anywhere in memory. Jump and call
instructions can be used for short jumps within currently selected 64 KB code
segment, as well as for far jumps anywhere within 1 MB of memory. All conditional
jump instructions can be used to jump within approximately +127 - -127 bytes
from current instruction.
Data memory - the processor can access data in any one out of 4 available
segments, which limits the size of accessible memory to 256 KB (if all four
segments point to different 64 KB blocks). Accessing data from the Data, Code,
Stack or Extra segments can be usually done by prefixing instructions with the DS:,
CS:, SS: or ES: (some registers and instructions by default may use the ES or SS
segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading
word data from even byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at
odd memory addresses, but it is not recommended for performance reasons (see
"Data Memory" above).
Reserved locations:
• 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a
32-bit pointer in format SEGMENT:OFFSET.
• FFFF0h - FFFFFh - after RESET the processor always starts program execution
at the FFFF0h address.

Interrupts:
The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled

using STI/CLI instructions or using more complicated method of updating the
FLAGS register with the help of the POPF instruction. When an interrupt occurs, the
processor stores FLAGS register into stack, disables further interrupts, fetches from
the bus one byte representing interrupt type, and jumps to interrupt processing
routine address of which is stored in location 4 * <interrupt type>. Interrupt
processing routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the

INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI
processing routine is stored in location 0008h. This interrupt has higher priority
then the maskable interrupt.
Software interrupts can be caused by:
• INT instruction - breakpoint interrupt. This is a type 3 interrupt.

• INT <interrupt number> instruction - any one interrupt from available 256
interrupts.
• INTO instruction - interrupt on overflow
• Single-step interrupt - generated if the TF flag is set. This is a type 1
interrupt. When the CPU processes this interrupt it clears TF flag before calling
the interrupt processing routine.
• Processor exceptions: divide error (type 0), unused opcode (type 6) and
escape opcode (type 7).
Software interrupt processing is the same as for the hardware interrupts.
I/O ports:
8086 can interface maximum of 65536 nos of 8-bit I/O ports. These ports can be
also addressed as 32768 16-bit I/O ports.

Registers:
Most of the registers contain data/instruction offsets within 64 KB memory

segment. There are four different 64 KB segments for instructions, stack, data and
extra data. To specify where in 1 MB of processor memory these 4 segments are
located the processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with

processor instructions. The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP) register. CS register cannot be
changed directly. The CS register is automatically updated during far jump, far call
and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the
stack pointer (SP) and base pointer (BP) registers is located in the stack segment.
SS register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data
segment. DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment,

usually with program data. By default, the processor assumes that the DI register
references the ES segment in string manipulation instructions. ES register can be
changed directly using POP and LES instructions.
It is possible to change default segments used by general and index registers by

prefixing instructions with a CS, SS, DS or ES prefix.
All general registers of the 8086 microprocessor can be used for arithmetic and
logic operations. The general registers are:
Accumulator (AX) register consists of 2 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX. AL in this case contains the
low-order byte of the word, and AH contains the high-order byte. Accumulator can
be used for I/O operations and string manipulation.
Base (BX) register consists of 2 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX. BL in this case contains the low-order
byte of the word, and BH contains the high-order byte. BX register usually contains
a data pointer used for based, based indexed or register indirect addressing.

Count (CX) register consists of 2 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX. When combined, CL register
contains the low-order byte of the word, and CH contains the high-order byte.
Count register can be used as a counter in string manipulation and shift/rotate
instructions.
Data (DX) register consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the
low-order byte of the word, and DH contains the high-order byte. Data register can
be used as a port number in I/O operations. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the initial or resulting
number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP

register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in string manipulation
instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed
and register indirect addressing, as well as a destination data address in string
manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flag Register is a 16-bit register containing 9 nos of one bit flags:
• Overflow Flag (OF) - set if the result is too large positive number, or is too
small negative number to fit into destination operand.
• Direction Flag (DF) - if set then string manipulation instructions will auto-
decrement index registers. If cleared then the index registers will be auto-
incremented.
• Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
• Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
• Sign Flag (SF) - set if the most significant bit of the result is set.
• Zero Flag (ZF) - set if the result is zero.

• Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3
in the AL register.
• Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of
the result is even.
• Carry Flag (CF) - set if there was a carry from or borrow to the most
significant bit during last result calculation.
Instruction Set:
8086 instruction set consists of the following instructions:
• Data moving instructions.

• Arithmetic - add, subtract, increment, decrement, convert byte/word and
compare.
• Logic - AND, OR, exclusive OR, shift/rotate and test.
• String manipulation - load, store, move, compare and scan for byte/word.
• Control transfer - conditional, unconditional, call subroutine and return from
subroutine.
• Input/Output instructions.
• Other - setting/clearing flag bits, stack operations, software interrupts, etc.
Addressing modes:
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is
located.
Register indirect - instruction specifies a register containing an address, where

data is located. This addressing mode works with SI, DI, BX and BP registers.
Based - 8-bit or 16-bit instruction operand is added to the contents of a base

register (BX or BP), the resulting value is a pointer to location where data resides.
Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index

register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the
contents of an index register (SI or DI), the resulting value is a pointer to location
where data resides.
Based Indexed with displacement - 8-bit or 16-bit instruction operand is added

to the contents of a base register (BX or BP) and index register (SI or DI), the
resulting value is a pointer to location where data resides.
Result:
The features of the Intel 8085 & 8086 microprocessors were studied and operations
of the corresponding kits were understood.



Fig.2.1 – Flow chart for 8-bit Addition with carry

EXP. NO. 02 (A) Date: _________
TITLE: 8-BIT ARITHMETIC OPERATIONS (8-BIT ADDITION)
AIM: To write an assembly language program for the addition of two 8-bit numbers.
APPARATUS REQUIRED:
S.N o Item Description Qty
1 8085-microprocessor kit. 1
2 Power supply unit 1
THEORY:
The two operands (i.e., 8-bit numbers) are loaded into two registers A & B, using
immediate addressing mode instructions and then added using ADD instruction. The
result is stored in the desired memory location. The overflow in addition is checked
by verifying the status of Carry (Cy) flag and accordingly either “00” or “01” is stored
in the location next to the result.
ALGORITHM:
1. Start the program
2. Initialize the C register as 00H.
3. Move the data1 and data2 to Accumulator and B register respectively.
4. Add B register to the content of accumulator
5. If there is no carry, go to step 6, else increment C register.
6. Store the content of accumulator to the memory location 4500H.
7. Move the content of C register to accumulator.
8. Store the content of accumulator to the memory location 4501H.
9. Stop the program.

PROGRAM:
Opcode &
Address Label Mnemonics Comments
Operand
4100 0E, 00 MVI C, 00 Clear c register
Move data1 to
4102 3E, Data1 MVI A, Data1
accumulator
4104 06, Data2 MVI B, Data2 Move data2 to B Register
4106 80 ADD B Add B Reg to accumulator
Jump on No carry to
4107 D2, 0B,41 JNC GO
location GO
410A 0C INR C Increment C Register
410B 32,00,45 GO: STA 4500 Store the result
410E 79 MOV A,C Move carry to Acc

410F 32,01,45 STA 4501 Store the carry
4112 76 HLT Stop the program
MANUAL CALCULATION:

SAMPLE DATA:
Result of 8-bit addition without carry:
INPUT OUTPUT
Address Data Address Data
4500
4103 05H 0BH
(Result)
4501
4105 06H 00H
(Carry)
Result of 8-bit addition with carry:
INPUT OUTPUT
4500
4103 51H 3CH
(Result)
4501
4105 EBH 01H
(Carry)
EXERCISE:
Execute the program with your own data and observe the results. Check the result
with your manual calculation.
INPUT OUTPUT
4500
4103
(Result)
4501
4105
(Carry)
RESULT:
Thus the assembly language program for 8-bit addition is executed and the results
are verified.

Fig. 2.2 – Flow chart for 8-bit subtraction

EXP. NO. 02 (B) Date: _________
TITLE: 8-BIT ARITHMETIC OPERATION (8-BIT SUBTRACTION)
AIM: To write an assembly language program for the subtraction of two 8-bit
numbers, using 8085.
APPARATUS REQUIRED:
THEORY:
Out of the two operands for subtraction, the first operand is loaded into Accumulator
and the second operand is subtracted directly from memory, using register indirect
addressing mode instructions. The result is stored in desired memory location and
the borrow in subtraction is checked by verifying the status of Carry (Cy) flag and
accordingly either “00” or “01” is stored in the location next to result.
ALGORITHM:
1. Start the program.
2. Load the HL pair with 16-bit address of data location.
3. Move the content of memory address in HL to accumulator.
4. Increment the address in HL pair.
5. Subtract the content of memory from accumulator.
6. Jump on No-carry to step 8.
7. Increment the C-register.
8. Store the content of accumulator and C-register.

PROGRAM:
Opcode &
Operand
4100 21, 50, 41 LXI H,4150 Load data to HL Register
4103 7E MOV A, M Move Data1 to Acc
4104 0E, 00 MVI C, 00 Clear C-register.

4106 23 INX H Increment address.
4107 96 SUB M Subtract Data2 from Acc

Jump on No-carry
4108 D2, 0C, 41 JNC NEXT
to the location NEXT.
410B 0C INR C Increment C register
410C 32, 52, 41 NEXT: STA 4152 Store the result

410F 79 MOV A,C Move carry to acc
4110 32, 53, 41 STA 4153 Store the carry
MANUAL CALCULATION:

SAMPLE DATA:
Result of 8 bit subtraction without carry:
INPUT OUTPUT
4152
4150 68H 14H
(Result)
4153
4151 54H 00H
(Borrow)
Result of 8 bit subtraction with carry:
INPUT OUTPUT
4152
4150 57H F1H
(Result)
4153
4151 66H 01H
(Borrow)
EXERCISE:
INPUT OUTPUT
4152
4150
(Result)
4153
4151
(Borrow)
RESULT:
Thus the assembly language program for 8-bit subtraction is executed and the
results are verified.

Fig.2.3 – Flow chart for 8-bit Multiplication

EXP. NO. 02 (C) Date: _________
TITLE: 8-BIT ARITHMETIC OPERATION (8-BIT MULTIPLICATION)
AIM: To write an assembly language program for the multiplication of two 8-bit
APPARATUS REQUIRED:
THEORY:
Using the immediate addressing mode instructions, the two operands to be multiplied
are loaded into two registers say, B and C. By the method of repeated addition, the
multiplication operation is performed (i.e., first number is repeatedly added to
accumulator as per the second number Eg. 03 x 04 => Acc + 03 (04 times) ). The
overflow in multiplication is checked every time after each addition, by verifying the
status of Carry (Cy) flag and accordingly a register, say D is incremented. The result
in accumulator is stored in the desired memory location and the content of D register
is stored in the location next to result.
ALGORITHM:
2. Clear the Accumulator and D Register.
3. Load the Data1 to B register and Data2 to C register.
4. Add the content of B to accumulator until C becomes zero.
5. If No-carry, go to step 6.
6. Increment the D-register.
7. Decrement the C register.
8. If C register is Non-zero, Jump to step 4.
9. Store the content of accumulator to 5000H.
10. Move the content of D-register to Accumulator.
11. Store the content of accumulator to 5001H.

PROGRAM:
Opcode &
Operand
4500 3E, 00 MVI A,00 Move data to accumulator
Move multiplicand to b
4502 06, Data1 MVI B, Data1
register
Move the multiplier to c
4504 0E, Data2 MVI C, Data2
register
4506 16,00 MVI D, 00 Clear D-reg for carry
4508 80 LOOP2: ADD B repetitive addition
Jump on no carry to an
4509 D2, 0D, 45 JNC LOOP1
location LOOP1
Increment the D-register,
450C 14 INR D
if carry occurs.
450D 0D LOOP1: DCR C Decrement C-register
Jump on no zero to
450E C2, 08,45 JNZ LOOP2
Location LOOP2
4511 32,00,50 STA 5000 Store resultant product
Move carry to
4514 7A MOV A,D
accumulator
4515 32,01,50 STA 5001 Store the carry.
4518 76 HLT Stop the program.
MANUAL CALCULATION

SAMPLE DATA:
Result of 8 bit multiplication without carry:
INPUT OUTPUT
5000
4503 05H 19H
(Result)
5001
4505 05H 00H
(Carry)
Result of 8 bit multiplication with carry:
INPUT OUTPUT
5000
4503 41H 45H
(Result)
5001
4505 25H 01H
(Carry)
EXERCISE:
INPUT OUTPUT
5000
4503
(Result)
5001
4505
(Carry)
RESULT:
Thus the assembly language program for 8-bit multiplication is executed and the

Fig. 2.4 – Flow chart for 8-bit Division

EXP. NO. 02 (D) Date: _________
TITLE: 8-BIT ARITHMETIC OPERATION (8-BIT DIVISION)
AIM: To write an assembly language program for the division of two 8 – bit
APPARATUS REQUIRED:
THEORY:
Using the immediate addressing mode instructions, the Divisor and Dividend are
loaded directly into Accumulator and B register. By the method of successive
subtraction, the division is carried out (i.e., Divisor is repeatedly subtracted from
Dividend, until the dividend becomes smaller than divisor Eg. 09 / 02 => 09 – 02 (4
times) => Remainder=01 and Quotient=04). The C register is incremented every
time after each subtraction, to keep count of the quotient. The final content in
accumulator will be remainder of the division and it is stored in the desired memory
location and the content of C register containing the quotient is stored in the location
next to result.
ALGORITHM:
2. Clear C Register.
3. Load the Divisor to Accumulator.
4. Load the Dividend to B-register.
5. Compare the B-register value with the accumulator.
6. If Accumulator content is smaller to B reg., then Jump to step 10.
7. Subtract B-register value with accumulator.
8. Increment the C-register.
9. Jump to step 4.
10. Store the contents of accumulator and C-register into memory.

PROGRAM:
Opcode &
Operand
4500 3E, Divisor MVI A, Divisor Move Divisor to Acc
4502 06, Dividend MVI B, Dividend Move Dividend to B reg.
4504 0E, 00 MVI C, 00 Clear C register

4506 B8 LOOP2: CMP B Compare Acc and B reg.
Jump on Carry
4507 DA, 0F, 45 JC LOOP1
to location LOOP1
Repetitive subtraction
450A 90 SUB B
for division
450B 0C INR C Increment C register
450C C3, 06,45 JMP LOOP2 Jump to location LOOP2

450F 32,00,50 LOOP1: STA 5000 Store the Remainder
4512 79 MOV A,C Move C reg. to Acc

4513 32,01,50 STA 5001 Store the Quotient.
MANUAL CALCULATION:

SAMPLE DATA:
Result of 8-bit Division without remainder:
INPUT OUTPUT
4501 06H 5000 (R) 00H
4503 03H 5001 (Q) 02H
Result of 8 bit division with remainder:
INPUT OUTPUT
4501 25H 5000 (R) 02H
4503 05H 5001 (Q) 07H
EXERCISE:
INPUT OUTPUT
4501 5000 (R)
4503 5001 (Q)
RESULT:
Thus the assembly language program for 8-bit division is executed and the results
are verified.

Fig. 2.5 – Flow chart for 16-bit Addition

EXP. NO. 02 (E) Date: _________
TITLE: 8-BIT ARITHMETIC OPERATION (16-BIT ADDITION)
AIM: To write an assembly language program for the addition of two 16-bit
APPARATUS REQUIRED:
THEORY:
Using the direct addressing mode instructions, the two 16-bit numbers are loaded
into HL and DE register pairs from memory. Using the double addition instruction
(DAD rp), the contents of HL and DE are added together and the results are stored in
the HL register pair again. The B register is used to check the overflow of the above
addition, by verifying the carry flag. The result in the HL register pair is stored in the
desired memory location and the content of B register is stored in the location next
to result.
ALGORITHM:
2. Clear the B-register.
3. Load the Data1 to HL register pair.
4. Exchange the content of HL to the DE register pair.
5. Load the Data2 to HL pair register.
6. Add the content of HL and DE pair.
7. If no overflow in addition (no carry), go to step 9.
8. Increment the content of B-register.
9. Store the content of HL pair to the address 5504H.
10. Store the content of B-register to the address 5506H.

PROGRAM:
Opcode &
Operand
4500 06,00 MVI B,00 Clear B register
4502 2A, 00,55 LHLD 5500 Load Data1 to HL register

Shift the data in HL
4505 EB XCHG
to DE register
4506 2A, 02,55 LHLD 5502 Load the Data2 to HL pair
Add the content of the HL
4509 19 DAD D
and DE pair
Jump on no carry to an
450A D2, 0E, 45 JNC LOOP
address
450D 04 INR B Increment the B register
450E 22,04,55 LOOP SHLD 5504 Store the result

4511 78 MOV A,B Move carry to B register.
4512 32,06,55 STA 5506 Store the carry.
MANUAL CALCULATION:

SAMPLE DATA:
Result of 16-bit Addition without carry:
INPUT OUTPUT
5504, 05
5500, 01 7167H F7ECH
(Result)
5506
5502, 03 8685H 00H
(Carry)
Result of 16-bit Addition with carry:
INPUT OUTPUT
5504, 05
5500, 01 FF03H 06FEH
(Result)
5506
5502, 03 EF03H 01H
(Carry)
Exercise:
INPUT OUTPUT
5504, 05
5500, 01
(Result)
5506
5502, 03
(Carry)
RESULT:
Thus the assembly language program for 16-bit addition is executed and the results
are verified.

Fig. 2.6 – Flow chart for 16-bit Subtraction

EXP. NO. 02 (F) Date: _________
TITLE: 8-BIT ARITHMETIC OPERATION (16-BIT SUBTRACTION)
AIM: To write an assembly language program for the subtraction of two 16-bit
APPARATUS REQUIRED:
THEORY:
Using the direct addressing mode instructions, the two 16-bit numbers are loaded
into HL and DE register pairs. The lower bytes of the two numbers are subtracted
first using SUB instruction and the higher bytes of the same two numbers are
subtracted along with borrow using SBB instruction. The result in the accumulator
after each subtraction is stored in the two subsequent desired memory locations.
ALGORITHM:
3. Exchange the content of HL to the DE register pair.
5. Move the content of L register to Accumulator.
6. Subtract the content of E register from the Accumulator.
7. Store the result in accumulator to the memory location, 5100H.
8. Move the content of H register to Accumulator.
9. Subtract the content of D register from the Accumulator, along with borrow.
10. Store the result in Accumulator to the memory location, 5101H.

PROGRAM:
Opcode &
Operand
Load the Data2 to HL
4500 2A, 00,55 LHLD 5500
register.
Transfer the content
4503 EB XCHG
of HL to DE register pair.
Load the Data2
4504 2A, 02,55 LHLD 5002
to HL pair register.
Move the content of L
4507 7D MOV A,L
register to accumulator
Subtract E register and
4508 93 SUB E
accumulator
4509 32,00,51 STA 5100 Store the result
Move H register to
450C 7C MOV A,H
accumulator
Subtract D register and
450D 9A SBB D
accumulator
450E 32,01,51 STA 5101 Store the result.
MANUAL CALCULATION:

SAMPLE DATA:
Result of 16-bit Subtraction:
INPUT OUTPUT
5500, 01 5100
6677H 1111H
(Data2) (Result)
5502, 03
7788H - -
(Data1)
EXERCISE:
INPUT OUTPUT
5500, 01 5100
(Data2) (Result)
5502, 03
- -
(Data1)
RESULT:
Thus the assembly language program for 16-bit subtraction is executed and the

Fig. 3.1a – Flow chart for Sorting in Ascending order

EXP. NO. 03 (A) Date: _________
TITLE : SORTING AND SEARCHING USING 8085 - SORTING PROGRAM
AIM: To write an assembly language program for arrange an array of 8-bit numbers
in ascending and descending order, using 8085.
APPARATUS REQUIRED:
THEORY:
This program uses the register indirect addressing mode instructions, to access the
data during sorting. The Bubble-Sort technique is used to sort the numbers in either
ascending order or descending order. The numbers to be sorted is stored in the
memory as a array with the first location containing the count of the data in the
array. The sorted numbers are stored back again in the same source location of the
array.
(I) ALGORITHM : ASENDING ORDER:

2. Load the data address to HL register pair and Initialize B register with ‘00’
3. Move the array size count into C-register, then decrement the C-register
by 1 and increment HL register pair by 1.
4. Load the first data in the memory to Accumulator.
5. Compare the subsequent memory with Accumulator.
6. Jump on Carry, when M is greater A and go to Step 9.
7. Move the memory M to D register
8. Decrement the address of HL pair and move the D register content to M
and increment the value by HL by 1.
9. Move 01 to B register and decrement the C-register.
10. If C is Non-zero, Jump to comparison of next data.
11. If B becomes zero after decrement, go to step1.

PROGRAM:
Opcode &
Operand
4100 06,00 AHEAD: MVI B,00 Clear the counter
Load Data addr to HL
4102 21,50,41 LXI H, 4150
pair.
4105 4E MOV C,M Move Array size to C-reg
4106 0D DCR C Decrement C reg
4107 23 INX H Increment addr in HL

4108 7E LOOP2: MOV A,M Move data-I in HL to A

Compare data-II of
410A BE CMP M
Memory (HL) with A
410B DA, 15,41 JC LOOP1 Jump on cy to add
Move the data in HL to D
410E 56 MOV D,M
reg
Move content of acc to
410F 77 MOV M,A
HL.
Decrement address in HL
4110 2B DCX H
register.
Move content of D to M
4111 72 MOV M,D
reg
4112 Increment address of HL
23 INX H
register
4113 06,01 MVI B,01 Move data to B reg
4115 0D LOOP1: DCR C Decrement C reg
4116 C2, 08,41 JNZ LOOP2 Jump on no zero
4119 05 DCR B Decrement B reg
411A CA, 00,41 JZ AHEAD Jump on zero to ahead
411D 76 HLT Stop the program

SAMPLE DATA:
Result of the Sorting in Ascending Order
INPUT OUTPUT
4150 4150
05H 05H
(Array Size) (Array Size)
4151 78H 4151 25H
4152 A6H 4152 37H
4153 42H 4153 42H
4154 25H 4154 78H
4155 37H 4155 A6H
EXERCISE:
INPUT OUTPUT
4150 4150
4151 4151
4152 4152
4153 4153
4154 4154
4155 4155
4156 4156
4157 4157

Fig. 3.1b – Flow chart for Sorting in Descending order

(II) ALGORITHM: DESENDING ORDER:

2. Load the data address to HL and initialize B register with ‘00’
3. Move the Array size count into C-register then decrement the C-register by
1 and increment HL by 1.
4. Load the data-I in the memory to A.
5. Compare the subsequent memory content with A.
6. Jump on No-carry (when M is greater A), go to Step 9.
7. Move the memory M to D register
8. Decrement the value of HL pair and move the D register content to M and
increment the value by HL by 1.
9. Move B register and decrement the C-register.
10. Jump on Non-Zero to the next comparison. If zero, then decrement B and
go to step1.

PROGRAM:
Opcode &
Operand
4100 06, 00 AHEAD: MVI B,00 Clear the counter
4102 21, 50, 41 LXI H,4150 Load Data addr to HL pair.
4105 4E MOV C,M Move Array size to C-reg


4108 7E LOOP2: MOV A,M Move data-I in HL to A

Compare data-II of Memory
410A BE CMP M
(HL) with A
410B D2, 15, 41 JNC LOOP1 Jump on No-Carry to Loop1
410E 56 MOV D,M Move the data in M to D reg

410F 77 MOV M,A Move content of A to M.
4110 2B DCX H Decrement address in HL reg.
4111 72 MOV M,D Move content of D reg. to M
4112
23 INX H Increment Addr in HL reg
4113 06, 01 MVI B,01 Move data to B reg

4115 0D LOOP1: DCR C Decrement C reg
4116 C2, 08, 41 JNZ LOOP2 Jump on Non-zero to LOOP2
4119 05 DCR B Decrement B reg
411A CA, 00,41 JZ AHEAD Jump on Zero to AHEAD
411D 76 HLT Stop the program

SAMPLE DATA:
Result of the Sorting in Descending order:
INPUT OUTPUT
4150 4150
05H 05H
4151 78H 4151 A6H
4152 A6H 4152 78H
4153 42H 4153 42H
4154 25H 4154 37H
4155 37H 4155 25H
EXERCISE:
INPUT OUTPUT
4150 4150
4151 4151
4152 4152
4153 4153
4154 4154
4155 4155
4156 4156
4157 4157
RESULT:
Thus the assembly language program for sorting Ascending & Descending order is
executed and the results are verified.

Fig. 3.2 – Flow Chart for Searching

EXP. NO. 03 (B) Date: __________
TITLE : SORTING AND SEARCHING USING 8085 - SEARCHING PROGRAM
AIM: To write an assembly language program to search the given data in an array.
APPARATUS REQUIRED:

THEORY:
This program uses the register indirect addressing mode instructions, to access the
data for searching a number from the array stored in the memory. The numbers to
be searched is loaded into the Accumulator and compared with the numbers of the
given array. Here again, the array has the data count stored in its first location. At
the end of searching, this program provides the information about the number of
times the given number is found in the array. The result is stored in the desired
memory location.
ALGORITHM:
2. Load the data address to the HL register pair.
3. Load the data to be searched in Accumulator.
4. Load the data count of array in the C register.
5. Initialize the B register with ‘00’.
6. Compare the memory content addressed by HL pair with Accumulator.
7. If not equal (zero flag is set); go to step 9.
8. Increment the B register.
9. Increment the HL register pair.
10. Decrement the C register by 1 and if not zero, go to step 6.
11. Store the content of B register in memory.

PROGRAM:
Opcode &
Operand
Load data to be searched
4100 3A, 50, 42 LDA 4250H
into Acc from memory
4103 21, 51, 42 LXI H, 4251H Set pointer for data array
4106 06, 00 MVI B,00H Clear B register
4108 4E MOV C, M Load data count to C reg.

4109 23 LOOP: INX H Increment HL reg. pair
410A BE CMP M Compare Acc & memory
If Not equal, go to location
410B C2, 0F, 41 JNZ NEXT
NEXT
410E 04 INR B Increment B register
410F 0D NEXT: DCR C Decrement C register
If not zero,
4110 C2, 09, 41 JNZ LOOP
go to location LOOP
4113 78 MOV A, B Move the data from B to Acc
4114 32, 00, 42 STA 4200 Store the result

SAMPLE DATA:
Result of the Searching:
INPUT OUTPUT
4250 4200
75H 02H
(Data to be searched) (Result)
4251
06H
(Array size)
4252 23H
4253 75H The result shows the number of times,
4254 C1H the given number that was found in
the array.
4255 A7H
4256 75H
4257 12H
EXERCISE:
INPUT OUTPUT
4250 4200
(Data to be searched) (Result)
4251
(Array size)
4252
The result shows the number of times,
4253
the given number that was found in
4254 the array.
4255
4256
RESULT:
Thus the assembly language program for searching the given data from an array is
executed and the result is verified.

Fig. 3.3a – Flow chart for Sorting in Ascending order on 8086.

EXP. NO. 03 (C) Date: _________
TITLE: SORTING AND SEARCHING USING 8086 - SORTING PROGRAM
AIM: To write an assembly language program for the sorting in ascending and
Descending order, using 8086.
APPARATUS REQUIRED:
THEORY:
The Bubble-Sort technique is used to sort the numbers in either ascending order or
descending order. The numbers to be sorted is stored in the memory as a array with
the first location containing the count of the data in the array. The sorted numbers
are stored back again in the same source location of the array.
(I) ALGORITHM: ASCENDING ORDER:

2. Move data to CX register and move CX data to DI register
3. Move 1200 to the BX register and move the content of 1200 to memory of AX
4. Compare the content of AX with 1202
5. Jump on borrow to rep
6. Move the data in memory to AX and move Data from AX to AI
7. Add Data to BX register and go to loop2
8. Perform no operation and move data & DI to CX
9. Go to the loop
10. Stop the program

PROGRAM:
Opcode &
Operand
1000 B9, 07, 00 MOV CX,07 Move data to CX reg
1003 89 CF LOOP1: MOV DI,CX Move CX data to DI
1005 BB, 00, 12 MOV BX,1200 Move 1200 to the BX reg

Move the content of 1200 to
1008 8B, 07 LOOP2: MOV AX,AI[BX]
memory of AX
CMP Compare the content of AX
100A 3B, 47, 02
AX,AI[BX+2] with 1202H
100D 72, 05 JB REP Jump on borrow to rep
XCHG Move the data in memory to
100F 87, 47, 02
AX,AI[BX+2] AX
1012 89, 07 MOV AI[BX],AX Move data from AX to AI
101A 83, C3, 02 REP: ADD BX,02 Add data to BX register
1017 F2, EF LOOP LOOP2 Go to loop2

1019 90 NOP No operation
101A 89, F9 MOV CX,DI Move data of DI to CX
101C E2, E5 LOOP LOOP1 Go to loop1
101E F4 HLT Stop the process

SAMPLE DATA:
Result of Sorting in Ascending order:
INPUT OUTPUT
1100 00FFH 1100 00CCH
1102 0100H 1102 00FEH
1104 1101H 1104 00FFH
1106 00FEH 1106 0100H
1108 00CCH 1108 1101H
110A CDEFH 110A 1234H
110C ABCDH 110C ABCDH
110E 1234H 110E CDEFH
EXERCISE:
INPUT OUTPUT
1100 1100
1102 1102
1104 1104
1106 1106
1108 1108
110A 110A
110C 110C
110E 110E

Fig. 3.3b – Flow chart for Sorting in Descending order on 8086.

(II) ALGORITHM : DESCENDING ORDER

2. Move the data to CX register and move CX content to D1 register.
3. Move the address to BX register and move the count of 1200 to AX.
4. Compare the content of AX with 1202.
5. Jump on no borrow to REP.
6. Exchange AX and A1 register and move AX register to BX.
7. Add BX register to 2 and continue the loop up to CX is zero.
8. Perform no operation and move D1 register to CX register and continue
the loop up to CX is zero.

PROGRAM:
Opcode &
Operand
1000 B9, 07, 00 MOV CX,07 Move data to CX reg
1003 89 CF LOOP1: MOV DI,CX Move CX data to DI
1005 BB, 00, 12 MOV BX,1200 Move 1200 to the BX reg

Move the content of 1200 to
1008 8B, 07 LOOP2: MOV AX,AI[BX]
memory of AX
CMP Compare the content of AX
100A 3B, 47, 02
AX,AI[BX+2] with 1202H
100D 72, 05 JNB REP Jump on No-borrow to REP
XCHG Move the data in memory to
100F 87, 47, 02
AX,AI[BX+2] AX
1012 89, 07 MOV AI[BX],AX Move data from AX to AI
101A 83, C3, 02 REP: ADD BX,02 Add data to BX register
1017 F2, EF LOOP LOOP2 Go to LOOP2

1019 90 NOP No operation
101A 89, F9 MOV CX,DI Move data of DI to CX
101C E2, E5 LOOP LOOP1 Go to LOOP1
101E F4 HLT Stop the process

SAMPLE DATA:
Result of Sorting in Descending order:
INPUT OUTPUT
1100 00FFH 1100 CDEFH
1102 0100H 1102 ABCDH
1104 1101H 1104 1234H
1106 00FEH 1106 1101H
1108 00CCH 1108 0100H
110A CDEFH 110A 00FFH
110C ABCDH 110C 00FEH
110E 1234H 110E 00CCH
EXERCISE:
INPUT OUTPUT
1100 1100
1102 1102
1104 1104
1106 1106
1108 1108
110A 110A
110C 110C
110E 110E
RESULT:
Thus the assembly language programs for sorting- ascending & descending order was
executed are verified.

Fig. 4 – Flow chart for String Manipulation

EXP. NO. 04 Date: _________
TITLE: STRING MANIPULATION USING 8086
AIM: To write an assembly language program to move a byte of string of length FF

from a source to a destination.
APPARATUS REQUIRED:
THEORY:
A group of similar data stored in consecutive memory locations, representing a
variable can be celled as a String. Various operations can be performed on the string
data like, string copy, string compare, string store, string load, etc. The following
program helps to copy a string data from a source location to a destination location.
ALGORITHM:
2. Set the SI to point the source array and DI at destination location.
3. Move the string size to CX register.
4. Direction Flag is cleared so that SI & DI will auto increment after each loop.
5. Move the bytes of the string using MOVSB instruction.

PROGRAM:
Opcode &
Operand
Load offset address of
1000 BE, 00, 11 MOV SI, Source
Source to SI register
Load offset address of
1003 BF, 00, 12 MOV DI, Destination
destination to DI register
Number of array elements
1006 B9, FF, 00 MOV CX, 00FFH
in CX register
1009 FC CLD Clear Direction Flag (D)
100A A4 NEXT: MOV SB Move string byte
Decrement CX and Check
100B E2, FD LOOP NEXT for Zero. If not zero,
go to location NEXT
100D F4 HLT Stop the program

SAMPLE DATA:
Result of String manipulation:
INPUT (Source) OUTPUT (Destination)

1100 xx 1200 xx
To xx To xx
11FF xx 12FF xx
As CX Register is loaded with string size ‘FF’
256 bytes of data at source location
(starting from 1100H)
will be copied to destination location
(at address 1200H)
EXERCISE:
Result of String manipulation:
INPUT (Source) OUTPUT (Destination)

1100 1200
1101 1201
1102 1202
1103 1203
1104 1204
1105 1205
1106 1206
1107 1207
1108 1208
Execute the program with following modifications.

a) Move smaller sized string data, by changing the string size stored in CX
register.
b) Change the auto-increment of SI & DI registers to auto-decrement by setting
the direction flag to ‘1’. Also store the last address of the string in SI & DI
register instead of starting address of the string.
RESULT:
Thus the string was moved from source to destination using the assembly language
of 8086.

Fig. 5.1 – Block diagram of ADC conversion

EXP. NO. 05 Date: _________
TITLE: INTERFACING ADC AND DAC USING 8085
AIM: To write an assembly language program to interface ADC and DAC with 8085
microprocessor kit.
APPARATUS REQUIRED:
2 CRO 1
3 ADC & DAC interface board 1
4 Flat ribbon Cable 1
THEORY:
In a real time applications, processing of input data, conversion of data from digital
to analog and vice versa, are indispensable. The following program initiates the
analog to digital conversion process, checks the EOC pin of ADC 0809 as to whether
the conversion is over and then inputs the data to the processor. It also instructs the
processor to store the converted digital data in the memory.
ADC:
HARDWARE DETAILS:
ADC 0809 is a monolithic CMOS device, with an 8-bit analog-to-digital converter, 8
channel multiplexer and microprocessor compatible control logic.
Selected Address Lines in the Multiplexer of ADC 0809
Analog Channel Addr C Addr B Addr A
IN0 0 0 0
IN1 0 0 1
IN2 0 1 0
IN3 0 1 1
IN4 1 0 0
IN5 1 0 1
IN6 1 1 0
IN7 1 1 1
A particular input channel is selected by using address decoding. The conversion

begins at the falling edge of the SOC pulse. The conversion will complete before 8th
clock pulse from the rising edge of SOC pulse.

PROGRAM FOR ADC:

Opcode &
Operand
4100 3E, 10 START: MVI A,10H
4102 D3, C8 OUT C8H

Select the input channel
4104 3E, 18 MVI A, 18H
4106 D3, C8 OUT C8H
4108 3E, 01 MVI A, 01H Send HIGH in SOC signal of

410A D3, D0 OUT D0H ADC
410C AF XRA A
Waste time to make A/D
410D AF XRA A
conversion to complete
410E AF XRA A
410F 3E, 00 MVI A, 00H Send LOW in SOC signal of

ADC
4111 D3, D0 OUT D0H
4113 DB, D8 LOOP: IN D8H
4115 E6, 01 ANI 01H

Check for EOC signal
4117 FE, 01 CPI 01H
4119 C2, 13, 41 JNZ LOOP

Input the digital data from
411C DB, C0 IN C0H
ADC interface
411E 32, 50, 41 STA 4150 Store the data in memory

ALGORITHM:

2. Give start of conversion pulse and set the data.
3. Check for the end of the pulse.
4. Store the digital data in the memory.
OBSERVATION:
Execute this program and compare the data displayed at the LEDs with that of the
stored data at location 4150H.
Vin – Analog Voltage Digital Output Digital Output Stored in

Set at input of ADC seen in LED memory location 4150

Fig. 5.2 – Block diagram of the DAC interface with 8085 Kit.

DAC:
HARDWARE DETAILS:
Digital to analog converter can be classified as current output, voltage output,

multiplexing type. The electronic circuit that translates a digital to analog signal is
called as DAC. VBMB 002 contains two D/A converter using DAC 0800.
The basic microprocessor board VBMB 002 incorporates two 8-bit DAC0800.
DAC0800 is a monolithic high-speed current output type. Its unique features are
1. Typical setting of time loop

2. Complementary current o/p
3. Differential o/p voltage of 20 vpp with simple resistor loads
4. Two quadrant diode range multiplexing data
5. To decoding
6. D/A conversion circuit
SOFTWARE DETAILS:
ALGORITHM FOR GENERATION OF SQUARE WAVEFORM:
1. Load the data 00h to Acc and send it to DAC to produce analog output of -5v.
2. Call time delay routine
3. Load the data FFh to Acc and send it to DAC to produce analog output of +5v.
4. Time delay routine is called again
5. A square wave of amplitude 10v (p-p) is produced, when steps 1 to 4 is
repeated continuously.

PROGRAM FOR DAC:

Opcode &
Operand
4100 3E, 00 START: MVI A,00H
Output the data to DAC to
4102 D3, C8 OUT C8H produce -5v
4104 CD, 11, 41 CALL DELAY Time delay is introduced

4107 3E, FF MVI A,FFH
Output of DAC to produce 5v
4109 D3, C8 OUT C8H
410B CD, 11, 41 CALL DELAY Time delay is introduced
410E C3, 00, 41 JMP START Repeat from START again
Delay Program
4111 06, 01 DELAY: MVI B,05H
4113 0E, FF L1: MVI C,FFH
4115 0D L2: DCR C
4116 C2, 15, 41 JNZ L2
4119 05 DCR B
411A C2, 13, 41 JNZ L1
410D C9 RET Return to Main program

SAMPLE DATA:
Result observed in CRO for DAC

The amplitude and time period of Square wave form generated using DAC are
DESCRIPTION OBSERVED OUTPUT

Amplitude (VP-P) 10
Time Period (ms) 17
EXERCISE:
Execute the program with different time delay and different input to DAC and
observe the results. Check the result with your manual calculation.
The amplitude and time period of Square wave form generated using DAC are
DESCRIPTION OBSERVED OUTPUT

Amplitude (VP-P)
Time Period (ms)
RESULT:
Thus the interfacing of ADC and DAC are performed using 8085 microprocessor kit.

Fig. 6 – Flow chart for Digital clock

EXP. NO. 06 Date: _________
TITLE: DIGITAL CLOCK USING 8085
AIM: To write an assembly language program to simulate digital clock using 8085.
APPARATUS REQUIRED:
THEORY:
The hours, minutes and seconds are entered at the memory location 4250, 4251 and
4252 in decimal form. The entered data is converted into Hex format from decimal
using a sub-routine. A delay of exactly 1 Sec is generated and after each delay, the
seconds, minutes and hours information is updated. The processing of data is done in
hex form and converted back into decimal before displaying.
ALGORITHM:

2. Load seconds, minutes and hours info in the memory
3. Display hours, minutes and seconds
4. Convert time information into Hex format from decimal
5. Call delay routine (1Sec)
6. Increment seconds
7. if seconds is greater than 60, reset seconds to ‘00’ and increment minutes
8. if minutes is greater than 60, reset minutes to ‘00’ and increment hours
9. if hours is greater than 24, reset seconds, minutes and hours to ‘00’
10. Convert time information back into Decimal format
11. Go to step 3
12. Stop the program

PROGRAM:
Opcode &
Operand
Main Program
4100 06, 03 MVI B, 03
4102 21, 50, 42 LXI H, 4250
4105 7E L2: MOV A, M
4106 32, 00, 43 STA 4300
4109 0E, 0A MVI C, 0A
410B E6, F0 ANI F0
410D 07 RLC
410E 07 RLC
410F 07 RLC
4110 07 RLC
4111 57 MOV D, A
4112 97 SUB A
4113 82 L1: ADD D
4114 0D DCR C
4115 C2, 13, 41 JNZ L1
4118 57 MOV D, A
4119 3A, 00, 43 LDA 4300
411C E6, 0F ANI 0F
411E 82 ADD D
411F 77 MOV M, A
4120 23 INX H
4121 05 DCR B
4122 C2, 05, 41 JNZ L2
4125 3E, 90 START: MVI A, 90
4127 D3, 01 OUT 01
4129 21, 50, 42 LXI H, 4250
412C 06, 03 MVI B, 03
412E 0E, 18 MVI C, 18
4130 7E L3: MOV A, M
4131 CD, 47, 41 CALL C1

Opcode &
Operand
4134 CD, 4C, 41 CALL CONVERT
4137 CD, 67, 41 CALL DISPLAY
413A 23 INX H
413B 3E, 18 MVI A, 18
413D C6, 24 ADI 24
413F 4F MOV C, A
4140 05 DCR B
4141 C2, 30, 41 JNZ L3
4144 C3, 85, 41 JMP DELAY
Compare Hours, Minutes and Seconds
4147 B9 C1: CMP C
4148 C0 RNZ
4149 91 SUB C
414A 77 MOV M, A
414B C9 RET
Routine to convert data for Display
414C 16, 00 CONVERT: MVI D, 00
414E D6, 0A L01: SUI 0A
4150 DA, 57, 41 JC LO2
4153 14 INR D
4154 C3, 4E, 41 JMP LO1
4157 C6, 0A L02: ADI 0A
4159 32, 00, 43 STA 4300
415C 7A MOV A, D
415D 0F RRC
415E 0F RRC
415F 0F RRC
4160 0F RRC
4161 57 MOV D, A
4162 3A, 00, 43 LDA 4300
4165 82 ADD D
4166 C9 RET

Opcode &
Operand
Display Routine
4167 32, 00, 43 DISPLAY: STA 4300
416A E6, F0 ANI F0
416C 07 RLC
416D 07 RLC
416E 07 RLC
416F 07 RLC
4170 CD, 7C, 41 CALL D1
4173 3A, 00, 43 LDA 4300
4176 E6, 0F ANI 0F
4178 CD, 7C, 41 CALL D1
417B C9 RET
417C 11, C8, 41 D1: LX1 D, 41C8
417F 83 ADD E
4180 5F MOV E, A
4181 1A LDAX D
4182 D3, 00 OUT 00
4184 C9 RET
Delay Routine (1Sec)
4185 0E, 02 DELAY: MVI C, 02
4187 3E, 30 MVI, 30
4189 D3, 0B OUT 0B
418B 3E, 90 L04: MVI A, 90
418D D3, 08 OUT 08
418F 3E, 80 MVI A, 80
4191 D3, 08 OUT 08
4193 3E, 00 L03: MVI A, 00
4195 D3, 0B OUT 0B
4197 DB, 08 IN 08
4199 5F MOV E, A
419A DB, 08 IN 08
419C B3 ORA E

Opcode &
Operand
419D C2, 93, 41 JNZ L03
41A0 0D DCR C
41A1 C2, 8B, 41 JNZ L04
Check for Seconds
41A4 2B DCX H
41A5 34 INR M
41A6 7E MOV A, M
41A7 FE, 3C CPI 3C
41A9 C2, 25, 41 JNZ START
41AC D6, 3C SUI 3C
41AE 77 MOV M, A
Check for Minutes
41AF 2B DCX H
41B0 34 INR M
41B1 7E MOV A, M
41B2 FE, 3C CPI 3C
41B4 C2, 25, 41 JNZ START
41B7 D6, 3C SUI 3C
41B9 77 MOV M, A
Check for Hours
41BA 2B DCX H
41BB 34 INR M
41BC 7E MOV A, M
41BD FE, 18 CPI 18
41BF C2, 25, 41 JNZ START
41C2 D6, 18 SUI 18
41C4 77 MOV M, A
41C5 C3, 25, 41 JMP START

Opcode &
Operand
Look Table (Codes) for display from ‘0’ to ‘F’
41C8 0A, 9F, 49, 0D DB
41CC 9C, 2C, 28, 8F DB
41D0 08, 8C, 88, 38 DB
41D4 6A, 19, 68, E8 DB

OUTPUT:
Enter the Time information (hours, minutes and seconds) at 4250, 4251 and 4252
respectively. Execute the program and look for digital clock being displayed at the 7-
segment display of the microprocessor kit.
RESULT:
Thus, the program for simulating digital clock in the 8085 microprocessor kit is
executed and the display was verified.

PIN DIAGRAM (8279):
CIRCUIT DIAGRAM (Keyboard and Display Interface)

EXP. NO. 07 Date: _________
TITLE : KEYBOARD AND DISPLAY INTERFACE – 8279
AIM: To write a program to study 8279 Keyboard and display controller and also
initialize 8279 for rolling message in the display.
APPARATUS REQUIRED:
2 8279 – Keyboard and display controller board 1
THEORY:
Intel 8279 is responsible for key debouncing, coding of the keyboard matrix and
refreshing of the display elements in the microprocessor based system. Its main
functions are:
• Simultaneous Keyboard and Display operation.

• 3 Input modes (Scanned Keyboard mode, Scanned sensor mode and Strobed
input entry mode.)
• 2 Output modes (8 character or 16 character display with left / right entry)
• Clock Pre-scaler
• Programmable scan timing
• 2-Key Lockout / N-Key Rollover mode selection
• Auto increment facility for easy programming.
DESCRIPTION:
In the 8279 Keyboard and display interfacing, we adopt the mode in which we
want to operate the keyboard and display by initializing it. The clear display
command is executed to clear all the rows of the display RAM. The data to be
displayed is fetched from Display RAM and displayed at first digit of display. A
counter is initialized and its value is decremented until all the values are displayed. A
delay is set such that the display is made for a period. The write display RAM
Command word is used it set the auto increment flag.
The various command words of 8279 are:

KEYBOARD AND DISPLAY MODE SET:
0 0 0 D D K K K
Where, DD is the display mode and KKK is the keyboard mode.
DD:
0 0 8 character display-left entry.
1 0 8 character display-right entry.
KKK:
0 0 0 Encoded scan keyboard-2 key lockout.
0 0 1 Decoded scan keyboard-2 key lockout.
0 1 0 Encoded scan keyboard-N key lockout.
0 1 1 Decoded scan keyboard-N key lockout.
1 0 0 Encoded scan sensor matrix.
1 0 1 Decoded scan sensor matrix.
1 1 0 Strobed input encoded scan display.
1 1 1 Strobed output decoded scan display.
CLEAR HISTORY:
1 1 0 CD CD CD CF CA
CD CD CD
0 x A0-3 B0-3 = 00 (0000 0000)
0 0 A0-3 B0-3 = 00 (0000 0000)
1 0 A0-3 B0-3 = 20 (0010 0000)
1 1 A0-3 B0-3 = FF (1111 1111)
Enables clear display when CD=1, the rows of display are cleared by the code set by
lower two CD bits
CF-> If CF=1, FIFO status is cleared, interrupt O/P line is reset sensor RAM
pointer is set to row 0.
CA-> Clear all bits has the combined effect of CD and CF. If uses the CD clearing
mode on display RAM and clears FIFO status. It also resynchronizes the
internal timing chain.

WRITE DISPLAY RAM:
1 0 0 AI A A A A
AI-> Auto Increment flag,

If the AI is ‘1’; then row address selected will be incremented after each
read and write to the display RAM.
AAAA-> To select, 1 of the 16 rows of display RAM.
READ FIFO STATUS
DU S/E O U F N N N
NNN -> Number of characters in the FIFO.

F -> FIFO full.
U -> Error under run (occurs when CPU read empty FIFO).
O -> Error overrun (occurs when char try to enter the full FIFO).
S/E -> Sensor closure/Error flag for multiple closures
DU -> Display unavailable.
READ FIFO/SENSOR RAM:
0 1 0 AI X A A A
X -> don’t care.

AI -> Auto increment flag irrelevant 16 scanned key mode. For the sensor matrix
mode. If AI=1 then each successive read will be from subsequent row of
sensor.
AAA->In the scanned Keyboard mode irrelevant in sensor matrix mode if select
one of the rows of sensor RAM.

SCANNED KEYBOARD SPECIAL ERROR MODE:
1 1 1 E X X X X
X=don’t ‘care
If during a single debounced cycle, two keys are found pressed, this is considered as
simultaneous multiple depression and sets error flag. This flag prevent any further
writing into FIFO and set interrupt. This error flag is rest by sending the normal clear
command CF=1.
PROGRAM CLOCK:
0 0 1 P P P P P
All timing and multiplexing signals for the 8279 are generated by an internal
Prescaler. This Prescaler divides the external clock (pin 3) by a programmable
integer. Bits PPPPP determine the value of this integer which ranges from 2 to 31.
Choosing a divisor that yield 100KHZ will give the specified scan and debounce times.
For instance if pin 3 of the 8279 is being cluched by 2MHZ signal, PPPPP should be
set to 10100 to divide the clock by 20 to yield the proper 100KHZ operating
frequency.
READ DISPLAY RAM:
0 1 1 AI A A A A
The CPU sets up the 8279 for a read of the display RAM by the first writing this
command. The address bits AAAA select one the 16 rows of the display RAM. If the
AI flag is set this row address will be incremented after each of the following read
and write operation of display RAM. Since the same counter is used for both reading
and writing this command sets the next read or write address and the sense of the
auto increment mode for both operations.
DISPLAY WRITE INHIBIT/BLANKING:
1 0 1 X 1W 1W BL BL
The 1W bits can be used to mask nibble A and nibble B in applications requiring
separate 4-bit display.

Segment Definition for 7-Segment Display:
8279 Output A3 A2 A1 A0 B3 B2 B1 B0
Data Bus D7 D6 D5 D4 D3 D2 D1 D0
Segments d c b a dp g f e
Note:
It must be noted that, ‘0’ in segment makes it glow and ‘1’ makes it blank.
PROGRAM: TO ACCEPT A KEY AND DISPLAY IT:

The below program accepts the key pressed in the interface board which is connected
to the kit and displays the same in the display in the interface board.
ALGORITHM:
1. Initialize 8279 by selecting display & keyboard mode

2. Send the command word for clearing display
3. Send command word to select row of display ram
4. Clear display
5. Check for key pressing
6. Send read FIFO ram command
7. Input the data from FIFO ram
8. Get display code from lookup table
9. Display character on LED display
10. Go to step 5

PROGRAM:
Opcode &
Operand
4100 06, 08 MVI B, 08H Load count for no. of char.
4102 3E, 00 MVI A, 00H

Mode and display set
4104 D3, C2 OUT C2
4106 3E, CC MVI A, CC
Clear display RAM
4108 D3, C2 OUT C2
410A 3E, 90 MVI A, 90 Write display
410C D3, C2 OUT C2 (select a row in display RAM)
410E 3E, FF MVI A,FF Load data to clear display
4110 D3, C0 BACK: OUT C0

Clears 8 Characters
4112 05 DCR B
of the Display
4113 C2, 10, 41 JNZ BACK
4116 DB, C2 LOOP: IN C2
4118 E6, 07 ANI 07 Look for pressing of a key
411A CA, 16, 41 JZ LOOP
411D 3E, 40 MVI A, 40

Set to send FIFO RAM
411F D3, C2 OUT C2
4121 DB, C0 IN C0 Read FIFO RAM
4123 E6, 0F ANI 0F
4125 6F MOV L, A Frame memory pointer by

joining ‘42’ and Key no., from
4126 26, 42 MVI H,42 FIFO RAM
Retrieve data from lookup
4128 7E MOV A, M
table in memory
Display data
4129 D3, C0 OUT C0
in 8279 Interface
412B C3, 16, 41 JMP LOOP Repeat same for next key
0C, 9F, 4A, 0B, LOOK UP – TABLE

4200
99, 29, 28, 8F, for the 7-segment display code
to
08, 09, 88, 38, corresponding to each number
420F
6C, 1A, 68, E8. starting from 0 to F in HEX.

RESULT:
Thus the Program of Interfacing 8279 Keyboard and Display is executed and verified.

Fig. 8 – Pin Diagram & Architecture of 8259 (PIC)

EXP. NO: 08 Date: _________
TITLE : 8259 - PROGRAMMABLE INTERRUPT CONTROLLER
AIM: To write an assembly program to study the Characteristics of 8259

Programmable Interrupt Controller.
APPARATUS REQUIRED:
1 8085-Microprocessor kit. 1
2 8259–Programmable interrupt controller board 1
HARDWARE DESCRIPTION:
The 8259 interface board comprises of the programmable Interrupt Controller, Intel
8259. The 8259 serves as an interface between interrupt request sent from multiple
I/O devices and the 8085 processor which is connected to INTR interrupt pin. Thus, it
functions as a overall manager in an interrupt driven system environment.
The special features of 8259 are
• Eight level priority controller, expandable to 64 levels and

programmable Interrupt modes. Individual request mask capability is
there.
• The 8259 are designed to minimize the software and real time
overhead in handling multilevel priority interrupts. It has several
modes permitting optimization for a variety of S/M requirements.
• The 8259 consist of the following parts

- Interrupt Mask Register (IMR), Interrupt Request Register (IRR)
- Interrupt Service Register (ISR)
- Priority Resolver (PR)
- Data Bus Buffer
- R/W Control Logic
• The 8259 can be easily interconnected in a system of one master with

up to eight slaves to handle up to 64 priority levels.

ICW1 (Initialization Command Word One)
D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 1 LTIM ADI SNGL IC4
D0: IC4: 0=no ICW4, 1=ICW4 required
D1: SNGL: 1=Single PIC, 0=Cascaded PIC
D2: ADI: Address interval. Used only in 8085, not 8086.

1=ISR's are 4 bytes apart (0200, 0204, etc)
0=ISR's are 8 bytes apart (0200, 0208, etc)
D3: LTIM: level triggered interrupt mode:

1=All IR lines level triggered.
0=edge triggered
D4-D7: A5-A7: 8085 only. ISR address lower byte segment.
The lower byte is A7 A6 A5 A4 A3 A2 A1 A0
ICW2 (Initialization Command Word Two)

Higher byte of ISR address (8085), or 8 bit vector address (8086).
D7 D6 D5 D4 D3 D2 D1 D0
A15 A14 A13 A12 A11 A10 A9 A8
ICW3 (Initialization Command Word Three)
D7 D6 D5 D4 D3 D2 D1 D0
Master S7 S6 S5 S4 S3 S2 S1 S0
Slave 0 0 0 0 0 ID3 ID2 ID1
• Master mode:
1 indicates slave is present on that interrupt, 0 indicates direct interrupt
• Slave mode:
ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000
0100)

ICW4 (Initialization Command Word Four)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 SFNM BUF M/S AEOI Mode
• SFNM: 1=Special Fully Nested Mode, 0=FNM

• M/S: 1=Master, 0=Slave
• AEOI: 1=Auto End of Interrupt, 0=Normal
• Mode: 0=8085, 1=8086
OCW1 (Operational Command Word One)
D7 D6 D5 D4 D3 D2 D1 D0
M7 M6 M5 M4 M3 M2 M1 M0
IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)
OCW2 (Operational Command Word Two)

D7 D6 D5 D4 D3 D2 D1 D0
R SL EOI 0 0 L3 L2 L1
Details R SL EOI Action
0 0 1 Non specific EOI (L3L2L1=000)

EOI Specific EOI command (Interrupt to
0 1 1
clear given by L3L2L1)
1 0 1 Rotate priorities on non-specific EOI
Auto rotation of priorities Rotate priorities in auto EOI mode

1 0 0
(L3L2L1=000) set
Rotate priorities in auto EOI mode
0 0 0
clear
Rotate priority on specific EOI
1 1 1
command (resets current ISR bit)
Specific rotation of priorities
(Lowest priority ISR=L3L2L1) Set priority
1 1 0
(does not reset current ISR bit)
0 1 0 No operation

OCW3 (Operational Command Word Three)
D7 D6 D5 D4 D3 D2 D1 D0
D7 ESMM SMM 0 1 MODE RIR RIS
ESMM SMM Effect

0 X No effect
1 0 Reset special mask
1 1 Set special mask

THEORY:
When one or more the Interrupt requests are received from I/O devices through the
interrupt Request lines (IR0-IR7), the corresponding (IRR bits) are set in IRR
register. The 8259 evaluates these requests and send an Interrupt signal to the CPU
through INTR. The CPU upon receiving the Interrupt request from 8259, it responds
back with an Interrupt Acknowledge signal through INTA. Upon receiving an INTA
from the CPU, the highest priority bit is set in Interrupt Service Register (ISR) and
the corresponding IRR bit is reset and 8259 also releases a CALL Instruction code
(1100 1101) onto the 8 bit data bus through its D7-D0 pins. On receiving the opcode
for CALL instruction from 8259, the processor (8085) initiates two more INTA signals
to the 8259. These two INTA signals allow the 8259 to release its preprogrammed
interrupt subroutine (ISR) address on to the data bus. The lower 8-bit address is
released at the first INTA signal and the higher 8-bit address is released at the
second INTR signal. In the AEOI (Automatic End of Interrupt) mode, the ISR bit is
reset of the end of the third INTA signal otherwise the ISR bit remains set until an
appropriate EOI command is issued at the end of interrupt sequence.
ALGORITHM:

2. Initialize 8259 with the following specifications
a) ICW4 needed
b) Single 8259
c) Address Interval of 4 bytes
d) Edge triggered mode
e) A7, A6, A5 = 0 0 0
f) Set Interrupt Service Address for selected as 5000H
g) 8085 mode
h) Normal End of Interrupt (EOI)
i) Non-buffered Mode (since we don’t use buffers)
j) No special fully nested mode
k) Mask all interrupts except desired interrupt (say IR0)
3. Press the selected interrupt in interface board
4. Execute ISR corresponding to selected interrupt at 5000H
5. stop the program

PROGRAM:
Opcode &
Operand
4100 3E, 17 MVI A, 17H
4102 D3, C0 OUT C0H
4104 3E, 50 MVI A, 50H Initialize 8259

as per the
4106 D3, C2 OUT C2H set configuration
4108 3E, 00 MVI A, 00
410A D3, C2 OUT C2H
410C 3E, FE MVI A, FE Load value in Acc for

selecting one of the eight
410E D3, C2 OUT C2H interrupts in 8259 interface
Program for ISR at 5000H
5000 3E, 20 MV1 A, 20H
5002 D3, C0 OUT C0H
5004 CF RST1

OBSERVATION:
If you press the switch IR0 (when Acc is loaded with data ‘FE’), the CPU jumps to the
location 5000H. The 8259 will not accept any more interrupt at IR0, since AEOI is not
set. The end of interrupt (EOI) should be given through OCW2 in ISR program at
5000H.
Upon pressing the IR0 switch in the 8259 interface board, the ISR program at 5000H
automatically makes the 8085 trainer kit to get resetted.
The value loaded into Acc for selecting the interrupt request switch in 8259 interface
board can be changed. Upon executing of the main program again, we can see the
kit getting resetted on pressing of selected interrupt switch at the 8259 interface
board.
RESULT:
Thus the 8259 Interface board is connected with 8085 and its operation is
understood.

CONTROL FORMAT:
SC1 SC0 RL1 RL0 M2 M1 M0 BCD

EX NO: 09 Date: _________

TITLE: PROGRAMMABLE INTERVAL TIMER - 8253
AIM: To write a program to study 8253 Timer and verify its modes of operation.
APPARATUS REQUIRED:

1 8085–Microprocessor kit. 1
2 8253–Programmable interval timer interface board 1
4 CRO
Hardware Description:
The 8253 is a Programmable interval timer/counter. The 8253 includes three

identical 16-bit counters that can operate independently in any of the six modes. It
is PQC based in a 24 pin o/p and required a single +5v Power Supply. The 8254 is an
upgraded version of the 8253 and the pins are compatible.
The six different modes are:
MODE 0 - Interrupt on Terminal Count

When this mode is set, the output will be low. Loading the count register with a value
will cause the output to remain low and the counter will start counting down. When
the counter reaches 0 the output will go high and remain high until the counter is
reprogrammed. The counter will continue to count down after terminal count is
reached. Writing a value to the count register during counting will stop the counter,
writing a second byte starts the new count.
MODE 1 - Programmable One-Shot

The output will go low, once the counter has been loaded, and will go high once
terminal count has been reached. Once terminal count has been reached it can be
triggered again.

MODE 2 - Rate Generator

It is a standard divide-by-N counter. The output will be low for one period of the
input clock then it will remain high for the time in the counter. This cycle will keep
repeating.
MODE 3 - Square Wave Rate Generator

Similar to mode 2, except the output will remain high until one half of the count has
been completed and then low for the other half.
MODE 4 - Software Triggered Strobe

After the mode is set the output will be high. Once the count is loaded it will start
counting, and will go low once terminal count is reached.
MODE 5 - Hardware Triggered Strobe

Hardware triggered strobe. Similar to mode 5, but it waits for a hardware trigger
signal before starting to count. Modes 1 and 5 require the 8253 gate pin to go ‘high’
in order to start counting.
-----------------------------------------------------------------------------------------------
MODE 0 - Interrupt on Terminal Count
Set the Channel 0 in Mode 0. Connect ‘CLK0’ to the debounce circuit and execute the
following program.
Opcode &
Operand
4100 3E, 30 MVI A,30H
Set Channel-0 in Mode-0
4102 D3, CE OUT CEH
4104 3E, 05 MVI A,05H Load Lower byte of COUNT

4106 D3, C8 OUT C8H to Counter
4108 3E, 00 MVI A,00H Load Higher byte of COUNT

410A D3, C8 OUT C8H to Counter
410C 76 HLT Stop the Program
Using a CRO, observe the output of Channel 0 is initially low. After giving six clock
pulses, we may notice that the output goes high.

Mode-1 Programmable One Shot:
After loading the counter, the output will remain low following the rising edge of the
gate input. The output would go high on the terminal count. It is retriggered hence
the output will remain low for the full count after any rising edge of gate input.
Initialize channels of 8253 in mode 1 and also initiates triggering of gate-0 and 0
goes low clock pulse after triggering the gate and goes back to high level after file
clock pulses.
Opcode &
Operand
4100 3E, 32 START MVI A, 32H
4102 D3, CE OUT CEH
4104 3E, 05 MVI A, 05H Load LSB of Count

4106 D3, C8 OUT C8H into Counter
4108 3E, 00 MVI A, 00H Load MSB of Count

410A D3, C8 OUT C8H into Counter
41OC D3, D0 OUT D0H Triggers gate0
410E 76 HLT Stop the program
Execute the grogram, give clock pulses through the denounce logic and verify using a
CRO.

Mode-2: Rate Generator:
It is a simple divide by N counter. The output will be low for one period of the input
clock. The period from one output pulse to the next, equals the number of input
counts in the count register. If the count register is reloaded between output pulses,
the present period will not be affected, but subsequent period will reflect the new
value.
Using mode 2, let us divide the clock pulse of the channel 1 by 10. Connect the CLK1
to PCLK.
Opcode &
Operand
4100 3E, 36 START MVI A, 36H
4102 D3, CE OUT CEH
4104 3E, 0A MVI A, 0AH Load Lower Byte of Count

4106 D3, CA OUT CAH To Counter
4108 3E, 00 MVI A, 00H Load Higher byte of Count

410A D3, CA OUT CAH To Counter
410C 76 HLT Stop the program
In a CRO, observe continuously the Input clock to Channel-1 and output at OUT-1

OUTPUT:
Mode 0: Input: 05 Clock pulse

Output: Goes HIGH, after 5 clock pulses.
Mode 1: Input: 05 Clock pulse

Output: Shifted after 5 clock pulse and again shifted after 5 counts.
Mode 2: Input: 05 Clock pulse, Clock 4th Pin, grounded – 10th Pin.
Output: Toggled after 5th clock pulse and this is repeated.
INPUT CLOCK TIMER OUTPUT
Amplitude Amplitude
Time Period Time Period
RESULT:
Thus the program for interface of programmable timer was executed and the outputs
were verified.

Fig. 10 – Pin Diagram & Internal Block diagram of 8251

EXP. NO: 10 Date: _________
TITLE: 8251 USART– INTERFACE WITH 8085 FOR SERIAL COMM.
AIM: To establish the communication between two microprocessor systems using

RS232C.
APPARATUS REQUIRED:
2 8251–USART Interface board 2
4 RS-232C Cable 1
IC 8251 – USART (Universal Synchronous / Asynchronous Receiver Transmitter)
The 8251 provides an interface between a microprocessor and a serial

communication device. The 8251 converts the parallel data from the processor into
serial before serial transmission to external device and it converts the serially
received data into parallel before sending them to the processor. The 8251 receives
and transmits data in a variety of configurations including 7- or 8-bit data words,
with odd, even, or no parity, and 1 or 2 stop bits. The transmitter and receiver can
be designed for synchronous or asynchronous operation.
Main Features of 8251 are
1) Both Synchronous and Asynchronous operation

2) False start bit detection
3) Automatic break detect and handling
4) Clock rate 1, 16, or 64 time band rate
4) Error detection - parity, overrun and framing errors.
5) Break characters generation
The control pins with which the 8251 A communicates with the CPU are the RESET,
CLK WR, RD, CS, and D0-D7

MODE WORD FORMAT:
COMMAND WORD FORMAT:
EH IR RTS ER SBRK RXE DTR TXEN
EH -> Enable hunt mode 1-enable

IR -> Internal reset 1-Reset
RTS -> Request to send 1-enable RTS.
ER -> Error reset 1-Reset error flag.
SBRK -> Send break character 1-Force Txd “low” & 0-Normal operation.
RE -> Receive enables 1-Enable & 0-Disable.
DTR -> Data transmit ready 1-Enable
TXEN -> Transmit enable 1-Enable

STATUS WORD FORMAT:

TXEN
DST SYNDET FE OE PE RXRDY TXRRDY
RDY
DSR -> It indicates that DSR is Zero.

FE -> Framing Error sets when a valid stop bit is not detected and reset by ER
Command.
OE -> Overrun error reads the character before it is available. It is reset by ER bit
in
Command word.
PE -> Parity error, 1-Enable parity error reset by ER bit of command word.
RS 232 C STANDARD DEFINITION:

The RS 232 C specifies 9 signal pins and it specifies that DTE connecter should be a
male and the demodulator should be a female the signal is divided into 4 groups.
Data signals, control signals, timing signals and ground. For data lines, the voltage
level +3 to –15V is defined as logic 1 and –12V corresponds to logic 0.
CONTROL SIGNAL 8251A:

Obviously a USART such as the 8251 A is not directory compatible with RS 232C
signal levels we can interface TTL signals of the 8251A to RS 232C signals If the
Jumper in this interface and removed and the jumpers in the jumper table under CRT
are inserted then this circuit will produce and accept RS232C signals.
The 8251A is used as the serial port on SDIC-86 boards. It is also used on the IBM
PC synchronous communication board and on many other boards. The D0-D7 act as
data bus the chip select is input is connected to an address decoder so the device is
enabled when addressed.
C/D means control or data is to be write read. RD read data command. WR write
data or Control command. The TXC is the transmit shift register clock input RXC is
the receive shift register input when connected with another system for several
communication the signals. With connect with CTS, RTS, TXD and RXD signals of that
system
CTS: Clear to send: Enable 8251 to transmit several data
RTS: Request to send: When low, indicates that 8251 can receive serial data
TXD: Transmit serial data
RXD: Receive serial data.

MASTER PROGRAM:
Opcode &
Operand
4100 3E, 36 START MVI A, 36
Mode set from 8253
4102 D3, CE OUT CEH
4104 3E, 0A MVI A, 0A

4106 D3, C8 OUT C8H
Timer initialization
4108 3E, 00 MVI A, 00
410A D3, C8 OUT C8H
410C 3E, 4E MVI A, 4EH

Mode set for 8251
410E D3, C2 OUT C2H
4110 3E, 37 MVI A, 37H

Command word to 8251
4112 D3, C2 OUT C2H
4114 DB, C2 LOOP IN C2H

Check for
4116 E6, 04 ANI 04
Transmitter Empty
4118 CA, 14, 41 JZ LOOP
Load the data to be
411B 3E, 41 MVI A, 41H
transmitted serially
411D D3, C0 OUT C0H Data is transmitted.
411F CF RST 1

The two microprocessor trainer kits are connected serially via RS232 standard cable.
The Master program is stored in memory location 4100H of first trainer kit (Tx-
Transmitter End) and Slave program is stored in the memory location 4200H of
second trainer kit (Rx-Receiver End).
Here Polling technique is used to send and receive the serial data.
MASTER PROGRAM
ALGORITHM:

2. Initialize the 8253 for clock signal generation.
3. Initialize the 8251 for mode of serial communication
4. Get the status to check whether transmitter is empty.
5. if not, Jump to step 3.
6. Transmit the loaded data & Stop the program
SLAVE PROGRAM
ALGORITHM:

2. Initialize the 8253 for clock signal generation.
3. Initialize the 8251 for mode of serial communication
4. Get the status word of 8251.
5. Check whether the receiver is ready.
6. if not, Jump to step 4.
7. Receive the data in Acc and stored it in memory location 4150H.

SLAVE PROGRAM:
Opcode &
Operand
4200 3E, 36 START MVI A, 36
Mode set for 8253
4202 D3, CE OUT CEH
4204 3E, 0A MVI A, 0A

4206 D3, C8 OUT C8H
Timer initialization
4208 3E, 00 MVI A, 00
420A D3, C8 OUT C8H
420C 3E, 4E MVI A, 4E

Mode word to 8251
420E D3, C2 OUT C2H
4210 3E, 37 MVI A, 37

Command word to 8251.
4212 D3, C2 OUT C2H
4214 DB, C2 LOOP1 IN C2H
4216 E6, 02 ANI 02H Check receiver is ready
4219 CA, 14, 42 JZ LOOP1
421B DB, C0 IN C0H

Store received DATA (at Acc)
421D 32, 50, 41 STA 4150H
in the Memory
4220 CF RST 1
Remember to first make the receiver program is executed and receiver end is kept
ready for reception of the serially transmitted data.

OUTPUT:
MICROPROCESSOR KITS DATA
Master (Tx) Transmitted data 41H
Slave (Rx) Received data stored at location 4150H 41H
RESULT:
Thus the serial interface program for communication between two microprocessor
kits using RS-232C was executed and the results are verified.


EXP. NO: 11 Date: _________
TITLE: 8255 PPI– INTERFACE WITH 8085 FOR PARALLEL COMM.
AIM: To establish the parallel communication between two microprocessor kits using
8255 PPI interface.
APPARATUS REQUIRED:
S.No. Item Description Qty
2 8255–PPI Interface board 2
The Intel 8255A is a general purpose programmable I/O device which is designed for
parallel communication between microprocessors and peripheral devices. It provides
24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3
major modes of operation.
The 8255 allows the following three operating modes (Modes 0, 1 and 2):
• Mode 0 - Simple I/O mode: Ports A and B operate as either inputs or

outputs and Port C is divided into two 4-bit groups either of which can be
operated as inputs or outputs.
• Mode 1 – Handshake I/O Mode: Same as Mode 0 but Port C is used for
handshaking and control.
• Mode 2 – Bidirectional I/O: Port A is bidirectional (both input and output)

and Port C is used for handshaking. Port B is not used.
In the given program, Port A is used for transmission and reception of parallel data
between the two microprocessor kits. Port A of 8255 interface in Tx end is selected in
Mode 0 – Output mode and Port A of 8255 interface in Rx end is selected in Mode 0 –
Input mode.

CONTROL WORD
for I/O MODE:
BSR MODE:

The two microprocessor trainer kits are connected parallel through 8255 interface.
The Master program is stored in memory location 4100H of first trainer kit (Tx-
Transmitter End) and Slave program is stored in the memory location 4100H of
second trainer kit (Rx-Receiver End).
Here Polling technique is used to send and receive the parallel data.
MASTER PROGRAM
ALGORITHM:

2. Initialize the mode format of 8255
3. Get the status to check whether transmitter is empty.
4. if not, Jump to step 3
5. Transmit the data stored in memory
6. Call delay routine
7. Check whether all data is transmitted. If not, jump to step 5
8. Stop the program
SLAVE PROGRAM
ALGORITHM:

2. Set the mode for 8255
3. Check whether the receiver is ready
4. Receive the data and store it in memory
5. Call delay routine
6. Check whether all data is received. If not, jump to step 4.

MASTER PROGRAM (Tx):

Opcode &
Operand
4100 3E, 82 MVI A, 82H
4102 D3, 0F OUT 0FH
4104 3E, 3F MVI A, 3FH

4106 D3, 0C OUT 0CH
4108 DB, 0D LOOP: IN 0DH

410A D6, 3F SUI 3FH
410C C2, 08, 41 JNZ LOOP
410F 0E, 08 MVI C, 08H
4111 21, 00, 45 LXI H, 4500H
4114 7E TRANS: MOV A, M
4115 D3, 0C OUT 0CH
4117 CD, 50, 41 CALL DELAY
411A 23 INX H
411B 0D DCR C
411C C2, 14, 41 JNZ TRANS
411F CF RST1
DELAY Routine
4150 06, 05 MVI B, 05H
4152 1E, FF LOOP2: MVI E, FFH
4154 1D LOOP1: DCR E
4155 C2, 54, 41 JNZ LOOP1
4158 05 DCR B
4159 C2, 52, 41 JNZ LOOP2
415C C9 RET

PROCEDURE:
1. Load the master program in the transmitting end microprocessor kit.
2. Load the slave program in the receiver end microprocessor kit.
3. Load the block of data at memory location 4500H in the transmitting end kit.
4. Execute the slave program in the receiving end kit first.
5. Execute the master program in the transmitting end kit.
6. Check for the transfer of parallel data from Tx kit to Rx kit, by verifying the
data at location 4400H in the Rx kit.
OUTPUT:
MICROPROCESSOR KITS
Transmitter End (Tx) Receiver End (Rx)
4500 4400
4501 4401
4502 4402
4503 4403
4504 4404
4505 4405
4506 4406
4507 4407

SLAVE PROGRAM (Rx):

Opcode &
Operand
4100 3E, 90 MVI A, 90H
4102 D3, 0F OUT 0FH
4104 DB, 0C CHECK: IN 0CH

4106 D6, 3F SUI 3FH
4108 C2, 04, 41 JNZ CHECK

410A 3E, 3F MVI A, 3FH
410C D3, 0D OUT 0DH
410F 0E, 08 MVI C, 08H
4111 CD, 50, 41 CALL DELAY
4114 21, 00, 44 LXI H, 4400H
4117 DB, 0C RECV: IN 0CH
4119 77 MOV M, A
411A CD, 50, 41 CALL DELAY
411D 23 INX H
411E 0D DCR C
411F C2, 17, 41 JNZ RECV
4122 CF RST1
DELAY Routine:
4150 06, 05 MVI B, 05H
4152 1E, FF LOOP2: MVI E, FFH
4154 1D LOOP1: DCR E
4155 C2, 54, 41 JNZ LOOP1
4158 05 DCR B
4159 C2, 52, 41 JNZ LOOP2
415C C9 RET
Note:
Remember to make the program in Rx end to get executed first and receiver end is
kept ready for reception of the parallel transmitted data.

RESULT:
Thus the program for parallel communication between two microprocessor kits using
8055 was executed and the results were verified.

Fig. 12.1 – movement of rotor for current in different windings
Fig. 12.2 – Bock diagram for stepper motor interface with 8085 kit

EXP. NO: 12 Date: __________
TITLE: INTERFACING AND PROGRAMMING OF STEPPER MOTOR (8085)
AIM: To write a program to interface and program of stepper motor with 805.
APPARATUS REQUIRED:

2 Stepper Motor 1
THEORY:
Stepper Motor:
A DC motor, in which the rotor makes only discrete angular movements in steps, is
called a Stepper Motor. The Stepper motor controlled by a microprocessor has variety
of applications in control system area and in process automations like, machine tools,
robotics, CNC lathes, etc.
Construction of stepper motor:
There are four windings in the Stator, named as A1, B1, A2, B2 and the Rotor has
three permanent magnets in it. The arrangement of stator and rotor can be seen in
figure 12.1. The movement occurs in the rotor in a stepwise manner, from one
equilibrium to the next.
Step size = 360°__

Nr x Ns
Where, ‘Nr’ is no. of pairs of poles in rotor and ‘Ns’ is the no. of poles in stator
Note: With Ns=4 and Nr=3; Step size in the stepper motor will be 30°

To make stepwise movement in the rotor of stepper motor, the coil windings in the
stator have to be energized appropriately.
The three different schemes for step movements in rotor of a stepper motor are,
a) Wave scheme
b) 2-phase scheme
c) Half or Mixed scheme
A. Wave Scheme:
In this scheme, the coil windings (A1, B2, A2, B1) of the stator of stepper motor are
cyclically excited with a DC current, to make clockwise movement in steps and in
reverse order for anti-clockwise movements.
Anti Clockwise Clockwise

Step A1 A2 B1 B2 Step A1 A2 B1 B2
1 1 0 0 0 1 0 0 1 0
2 0 0 0 1 2 0 1 0 0
3 0 1 0 0 3 0 0 0 1
4 0 0 1 0 4 1 0 0 0
B. 2-Phase Scheme:
In this scheme, the two adjacent coil windings (A1-B2, B2-A2, A2-B1, B1-A1) of the
stator of stepper motor are cyclically excited with a DC current, to make clockwise
movement in steps and in reverse order for anti-clockwise movements.
Anti Clockwise Clockwise

Step A1 A2 B1 B2 Step A1 A2 B1 B2
1 1 0 0 1 1 1 0 1 0
2 0 1 0 1 2 0 1 1 0
3 0 1 1 0 3 0 1 0 1
4 1 0 1 0 4 1 0 0 1
C. Half Scheme:
In this scheme, we obtain the movement of rotor in half of the original step size, by
interleaving these two schemes.
Note: ‘1’ in the table indicates the supply of DC current to the stator coil winding.

Format of Data storage (in Lookup table) for DC current to the stator coil windings,
are as follows.
D7 D6 D5 D4 D3 D2 D2 D1
0 0 0 0 A1 A2 B1 B2
Example:
Data for step-1 in the 2-phase scheme (clockwise rotation) is ‘ 09 ’
ALGORITHM:

2. Load the data (no. of steps) into B register
3. Load the address of the LOOKUP table memory to HL pair.
4. Load the data (containing current info in step-1) to Acc.
5. Send the data to Stepper motor interface.
6. Call a Delay routine.
7. Increment pointer to LOOKUP table (Address in HL pair).
8. Check whether all data have been taken from LOOKUP table
9. If not, Jump to step 4. Otherwise, Jump to step 2.

PROGRAM:
Opcode &
Operand
4100 21, 50, 41 START: LXI H, 4150 Load Lookup table addr to HL
4103 06, 04 MVI B, 04H Move no. of steps data to B
4105 7E REPEAT: MOV A, M Move data-I from Memory to

4106 D3, C0 OUT C0H Acc and send it out
4108 11, 03, 03 LXI D, 0303H

410B 00 DELAY: NOP
410C 1B DCX D
Delay Program
410D 7B MOV A, E
410E B2 ORA D
410F C2, 0B, 41 JNZ DELAY
4112 23 INX H Increment Data pointer
4113 05 DCR B Check whether all 4 steps in

Lookup table is taken. If not,
4114 C2, 05, 41 JNZ REPEAT Jump to Repeat.
4117 C3, 00, 41 JMP START If Yes, Jump to Start.
LOOKUP Table
4150 09, 05, 06, 0A -

OUTPUT:
Execute the program and observe the movement of stepper motor.
Note:
1. To reverse the direction of rotation in stepper motor, Change the order of

stored data in LOOKUP table in reverse order.
2. To vary the speed of rotation, change the delay time in the program.
RESULT:
Thus the stepper motor is interfaced with 8085 processor and program for the control
of stepper motor is executed to verify the direction of rotation in both forward and
reverse direction and change in speed of rotation.

Fig. 13 – Block diagram of DC motor control

EXP. NO: 13 Date: _________
TITLE: DC MOTOR SPEED CONTROL USING 8085.
AIM: To write an assembly program to control the speed of DC motor using 8085 kit.
APPARATUS REQUIRED:

2 DC Motor interface card with DC motor 1
THEORY:
The measurement of speed plays a vital role in an instrumentation process control

system.
Principal of Operation:
The speed of the motor varies with input supply power. Hence, by varying the input
voltage to the motor, the speed of DC motor can be varied. The speed measurement
is based on the principle that the motor rotation is converted into pulses using optical
pickup sensor and the pulses are used to decrement a counter for a known time. This
count value can be calibrated to RPM, which is the standard unit for speed
measurement.
This program illustrates the concept of setting the speed of DC motor and read the
count value from channel-0 of the counter. To make up this functions, the following
procedures to be adapted.
1. Set the DC motor speed.

2. Set the control word and initialize counter.
3. Enable the counter gate.
4. Apply 1 sec delay. (RPS)
5. Disable the counter
6. Read the counter.

PROGRAM:
Opcode &
Operand
4100 3E, FF MVI A, 0FFH Move data FFH to C reg
4102 D3, C0 OUT C0H DAC OUT port
4104 3E, 00 MVI A, 00H Clear acc
4106 D3, D8 OUT D8H Initialize gates as low
4108 CD, 2B, 41 CALL DELAY Call delay for stable running
Initialize mode as
410B 3E, 30 MVI A, 30H
interruption terminal count
410D D3, CE OUT CEH Time control port
410F 3E, FF MVI A, FFH Maximum data
Initialize Timer port CH0
4111 D3, C8 OUT C8H
(LSB)
Initialize Timer port CH0
4113 D3, C8 OUT C8H
(MSB)
4117 D3, D0 OUT D0H Make gate high
4119 CD, 2B, 41 CALL DELAY Call delay for 1 sec
411C 3E, 00 MVI A, 00H Clear acc
411E D3, D8 OUT D8H Make gate low
4120 DB, C8 IN C8H Data in from CH0
4122 32, 00, 45 STA 4500H Store data in memory
4127 32, 01, 45 STA 4501H Clear buffer
412A 76 HLT Stop the program
1 Second DELAY Routine
412B 0E, 03 DELAY MVI C, 03H Move 03H to C reg
412D 21, C3, A3 LOOP1 LXI H, A3C3H Load data in HL pair
4130 2B LOOP DCX H Decrement HL pair addr
4131 7D MOV A, L Move L reg content to acc
OR Acc content with H reg
4132 B4 ORA H
content
4133 C2, 30, 41 JNZ LOOP Jump on no zero to LOOP
4137 C2, 2D, 41 JNZ LOOP1 Jump on no zero
413A C9 RET Return to main program

OUTPUT:
The determined counter value representing the speed is stored in memory location as
shown below.
OUTPUT
Determined counter
Memory Location
Value
4500
4501
RESULT:
Thus the speed of DC motor was controlled with 1 sec time delay using 8085
microprocessor kit.



Flow Chart:
PROGRAM (16-bit Addition):

Opcode &
Operand
4100 C3 CLR C Clear carry
4101 74, Data1L MOV A, #DATA1 Move Data1L to Acc
4103 24, Data2L ADD A, #DATA2 Add Data2L with Acc

MOV DPTR, Move content in 4500 to
4105 90, 41, 50
#4150h DPTR.
4108 F0 MOVX @DPTR, A Move data to DPTR location
4109 A3 INC DPTR Increment DPTR
410A 74, Data1H MOV A, #DATA1 Move Data1H to Acc

ADDC A,
410C 34, Data2H Add Acc with Data2H & Carry
#DATA2
Move from Acc
410E F0 MOVX @DPTR, A
to DPTR location
410F 80, FE HERE: SJMP HERE End

EXP. NO: 14 Date: _________
TITLE: PROGRAMMING ARITHMETIC, LOGICAL AND BIT

MANIPULATION USING 8051
AIM: To write an assembly language program for the arithmetic, logical and bit
manipulation using 8051.
APPARATUS REQUIRED:
1 8051–Micro Controller kit. 1
2 Power Supply unit 1
(A) ARITHMETIC OPERATION:
(I) 16 BIT ADDITION:
ALGORITHM:
2. Get the LSB of 1st and 2nd operands.
3. Add the LSB of the two operands and store it in memory.
4. Get the MSB of 1st and 2nd operands.
5. Add the MSB and store the result in memory
OUTPUT OF 16-BIT ADDITION:
INPUT OUTPUT
4102 4500
4104 4501
410B - -
410D - -

Flow Chart:
PROGRAM (8-bit Subtraction):

Opcode &
Operand
4100 C3 CLR C Clear carry
4101 74, Data1 MOV A, #DATA1 Move data1 to acc
4103 94, Data2 SUBB A, #DATA2 Add data2 with acc

MOV DPTR,
4105 90, 45, 00 Move 4500 to DPTR.
#4500h
Move Acc value to DPTR
4108 FO MOVX @DPTR, A
location
4109 80, FE HERE: SJMP HERE End

(II) 8- BIT SUBTRACTION:
ALGORITHM:
2. Clear the carry flag and load the first operand in accumulator.
3. Get the 2nd operand and subtract it from accumulator.
4. Store the result in memory.
OUTPUT OF 8-BIT Subtraction without Carry:
INPUT OUTPUT
4102 4500
4104 - -

Flow Chart:
PROGRAM (8-bit Multiplication):

Opcode &
Operand
4100 74, Data1 MOV A, #DATA1 Move Data1 to Acc
4102 75, F0, Data2 MOV B, #DATA2 Move Data2 to Acc
4105 A4 MUL AB Multiply Acc and B

MOV DPTR,
4106 90, 45, 00 Move 4500 to DPTR.
#4500h
location
410A A3 INC DPTR INC DPTR
Move B register value to
410B E5, F0 MOV A, B
Acc
410D FO MOVX @DPTR, A
location
410E 80, FE HERE: SJMP HERE End

(III) 8-BIT MULTIPLICATION:
ALGORITHM:
2. Load the 1st operand in A and 2nd operand in B.
3. Multiply A and B contents using MUL instruction.
OUTPUT OF 8-BIT Multiplication:
INPUT OUTPUT
4101 4500
4104 4501

Flow Chart:
PROGRAM (8-Bit Division):
Opcode &
Operand
4100 74, Data1 MOV A, #DATA1 Move Dividend to Acc
4102 75, F0, Data2 MOV B, #DATA1 Move Divisor to B
4105 84 DIV AB Divide A by B

MOV DPTR,
4106 90, 45, 00 Move 4500 to DPTR.
#4500h
location
410A A3 INC DPTR Increment DPTR
410B E5, F0 MOV A, B Move B-reg. value to Acc
410D FO MOVX @DPTR, A Store the result
410E 80, FE HERE: SJMP HERE End

(IV) 8 BIT DIVISION:
ALGORITHM:
2. Get 1st operand in A and 2nd in B.
3. Divide A by B contents using division instruction.
OUTPUT OF 8-BIT Division:
INPUT OUTPUT
4500
4101
(Quotient)
4501
4104
(Remainder)

Flow Chart:
PROGRAM (OR):
Opcode &
Operand
4102 44, Data2 ORL A, #DATA2 OR Acc and Data2

MOV DPTR,
4104 90, 45, 00 Move 4500 to DPTR.
#4500H
4107 FO MOVX @DPTR, A Store the result
4108 80, FE HERE SJMP HERE End

(B) LOGICAL OPERATION:
(I) ‘OR’ OPERATION:
ALGORITHM:
2. Load 1st operand in Accumulator.
3. Get 2nd operand and perform OR between Acc and 2nd Operand.
OUTPUT OF OR Operation:
INPUT OUTPUT
4101 4500
4103 - -

Flow Chart:
PROGRAM (AND):
Opcode &
Operand
4102 54, Data2 ADL A, #DATA2 AND Acc and Data2

MOV DPTR,
4104 90, 45, 00 Move 4500 to DPTR.
#4500H
4107 FO MOVX @DPTR, A Store the result
4108 80, FE HERE: SJMP HERE End

(II) ‘AND’ OPERATION:

ALGORITHM:
2. Get 1st operand in Accumulator.
3. Get 2nd operand and perform AND accumulator content & 2nd operand
OUTPUT OF AND Operation:
INPUT OUTPUT
4101 4500
4103 - -
RESULT:
Thus the programs involving arithmetic, logical and bit manipulation using 8051 are
executed and its results are verified.


EXP NO: 15 Date: _________
TITLE: COMMUNICATION BETWEEN 8051 MICROCONTROLLER KIT AND PC
Aim: To communicate microcontroller kit and PC using the stepper motor in both
forward and reverse direction with delay program.
APPARATUS REQUIRED:
1 8051–Micro Controller kit. 1
2 Stepper Motor 1
3 PC with Cross assembler software 1
4 Flat Ribbon Cable & RS232C Cable 1 Each
Theory:
The software which is used to compile (convert) the assembly language program into
a machine suitable for a particular processor, is called Cross Assembler. This
converted machine code is sent to the trainer kit through the serial cable (RS232)
and executed in the trainer kit.
CROSS ASSEMBLER:
You may use any text editor such as Notepad in Windows to edit your 8051 program.
Then you can assemble and link your program so as to make it loadable to the 8051
trainer kit for its execution.
ASSEMBLING:
Suppose your program is ready and is now stored in the working directory where the
8051 cross assembler and the 8051 linker are in, Run X8051.exe to activate the
cross assembler.

Figure C1 shows the user interface of the cross-assembler. In the interface, the cross
assembler will prompt for inputting listing destination, input filename and output
filename. You have to specify the input filename. As for others, you can skip them by
just entering ENTER key. If no error is detected by the cross-assembler, an object file
with extension ‘.obj’ will be generated.
LINKING:
Run Link.exe to activate the linker. Figure C2 shows the user interface of the linker.
The linker will prompt for inputting parameters. All you need to do is to specify the
input filename. It should be an object file with extension ‘.obj’. As an example, Figure
C2 shows the case that the input file is “Stepper.obj”. You can skip all other prompts
by just entering ENTER key. If no error is detected, a binary file with extension ‘.hex’
will be generated.
The assembled program will be loaded into external memory of the 8051 trainer kit
through serial communication interface with PC and the same can be executed from
the trainer kit.

Algorithm:
1. Activate the assembler program.

2. Select the COM port for serial connection and Set the baud rate.
3. Open the “stepper.asm” program.
4. Assemble and link the opened assembly language program.
5. Initiate the transfer of generated Hex file to the trainer kit.
6. Execute the loaded program from trainer kit.
7. Observe the movement of stepper motor in desired direction & speed.

PROGRAM (To be typed in TEXT editor for Assembling):

Opcode &
Operand
4100 ORG 4100H
4100 90, 45, 00 START: MOV DPTR, #4500H Load address to DPTR
4103 78, 04 MOV R0, #04H Move 04 to Ro reg

Move Data
4105 E0 REPEAT: MOVX A, @DPTR
from DPTR location to Acc
4106 C0, 83 PUSH DPH
4108 C0, 82 PUSH DPL
410A 90, FF, C0 MOV DPTR, #FFC0H
410D 7A, 01 MOV R1,#04H
410F 79, 22 DLY1: MOV R2, #FFH
4111 7B, FF DLY2: MOV R3, #FFH
Delay Program
4113 DB, FE DLY3: DJNZ R3, DLY3
4115 D9, FC DJNZ R2, DLY2
4117 DA, FA DJNZ R1, DLY1
411A DO, 82 POP DPL
411C D0, 83 POP DPH
411E A3 INC DPTR Increment the DPTR
Decrement R0 and Jump to
411F D8, E4 DJNZ R0, REPEAT
REPEAT, until R0 = ‘00’
4121 80, DD SJMP START Jump to Start
4123 END
DB 09, 05,
4500 TABLE Look up table
06, 0A

Result:
Thus the program for stepper mot or interface with 8051-microcontroller kit through
PC was executed and its parameters like speed, direction was observed.


APPENDIX A
8085 OPCODE SHEET


8086 OPCODE SHEET
DATA TRANSFER:
MOV AX, [a16] A1, ___, ___
MOV [a16], AX A3, ___, ___
MOV AX, DX 8B, C2
MOV AL, d8 B0, ___
MOV AH, d8 B4, ___
MOV [a16], AL A2, ___, ___
MOV [a16], AH 88, 26, ___, ___
MOV AL, AH 8A, C4
MOV AH, AL 88, C4
MOV BP, AX 8B, E8
MOV BX, d16 BB, ___, ___

MOV BL, d8 B3, ___
MOV BH, d8 B7, ___
MOV [BX], DX 89, 17
MOV CX, d16 B9, ___, ___

MOV CL, d8 B1, ___
MOV CH, d8 B5, ___
MOV CX, DI 8B, CF
MOV [a16], DX 87, 16, ___, ___

MOV DX, [a16] 8B, 16, ___, ___
MOV DX, d16 BA, ___, ___
MOV SI, AX 8B, F0

MOV SI, d16 BE, ___, ___
MOV DI, d16 BF, ___, ___
I/O:
OUT a8, AL E6, a8
IN AL, a8 E4, a8
ARITHMETIC:
ADD AL, d8 04, ___
ADD AX, [a16] 03, 06, ___, ___
ADC AX, [a16] 13, 06, ___, ___
SUB AX, [a16] 2B, 06, ___, ___

SBB AX, [a16] 1B, 06, ___, ___
SUB AL, d8 2C, ___
MUL [a16] F7, 26, ___, ___

DIV [a16] F7, 36, ___, ___
DAA 27

INC BX 43
INC AL FE, C0
INC SI 46
INC DI 47
DEC BL FE, CB
DEC CH FE, CD
DEC CX 49
LOGICAL:
AND AL, d8 24, ___
AND AX, d16 25, ___, ___
AND AH, BL 22, E3
OR AX, d16 0D, ___, ___

OR BL, BH 0A, DF
OR AL, AH 0A, C4
XOR AL, AL 30, C0
NOT AX F7, A0
CMP AH, AL 38, C4
STRING MANIPULATION
MOVSB A4
STOSB AA
CLD FC
STD FD
CLI FA
STI FB
ITERATION CONTROL
LOOP rel E2, rel_
EXT H/W SYNCHRONIZATION:

NOP 90
HLT F4
BRANCHING:
JMP rel EB, rel_
JNC rel 73, rel_
JNZ rel 75, rel_
JZ rel 74, rel_
CALL [a16] E8, ___, ___

RET C3

8051 OPCODE SHEET


Note:
Data Addr refers to 8-bit (direct) address of Internal RAM memory location / SFR
Code Addr refers to 8-bit relative addressing from the current location


APPENDIX B
PROGRAMMING STEPS in Microprocessor Kit:
A. To Store program / Data:

<Res>
<Sub>
<...16-bit address...> Starting address of memory where data /
Program is to be stored
<Next>
<...Enter the 8-bit data / opcode...>
<Next>
Keep repeating the last two steps until entire data / Program is stored.
B. To Execute the stored program:

<Res>
<Go>
<...16-bit address...> Starting address of memory where data /
Program is stored
<Exec>
A display of letter ‘ E ’ in the trainer kit indicates the successful execution of

the program in the kit.
C. To view the Opcode / Data / Result:

<Res>
<Sub>
<...16-bit address...> Address of memory where data is stored
<Next>
Keep pressing <Next> key to view data in subsequent locations.

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Vidya Vikas College of Engineering and Technology

EXP. NO. 01 (A) Date: _________

TITLE: STUDY OF INTEL 8085 MICROPROCESSOR KIT

Aim : To study the working of Intel 8085 Microprocessor trainer kit.

Figure 1.1 Vimicro’s Micro-85 Microprocessor kit

EC1307 – Microprocessor & Application Lab - Manual 1

1.2.1 HARDWARE SPECIFICATIONS

1) PROCESSOR, CLOCK FREQUENCY: Intel 8085A at 6.144 MHz clock. .

6) AUDIO CASSETTE INTERFACE with file management.

EC1307 – Microprocessor & Application Lab - Manual 2

8) HARDWARE SINGLE STEP:

9) SYSTEM POWER CONSUMPTION:

10) POWER SUPPLY SPECIFICATIONS: [External ]

11) PHYSICAL CHARACTERISTICS:

12) TEST POINTS: Test points provided

EC1307 – Microprocessor & Application Lab - Manual 3

1.2.2 SOFTWARE SPECIFICATIONS

Micro-S5 EB contains a high performance 8K bytes monitor program. It is designed

KEY FUNCTION SUMMARY

Maskable interrupt connected to CPU's RST 7.5 interrupt.

Decrement the address by one and display it contents

Execute a particular program after selecting the address

Increment address by one and display its contents

NOTE: The Hex-key function summary below is in the order:

EC1307 – Microprocessor & Application Lab - Manual 4

KEY FUNCTION SUMMARY

i. Hex key entry "0"

1 i. Hex key entry "1"

i. Hex key entry "2"

3 i. Hex key entry “3”

4 i. Hex key entry “4”.

i. Hex key entry “5”.

6 i. Hex key entry "6"

7 i. Hex key entry "7"

EC1307 – Microprocessor & Application Lab - Manual 5

8 i. Hex key entry "8"

9 i. Hex key entry "9"

i Hex key entry "A"

B i Hex key entry "B"

C i. Hex key entry "C"

D i. Hex key entry "D"

CMP ii. Compare two memory blocks.

E i. Hex key entry "E"

F i. Hex key entry "F"

EC1307 – Microprocessor & Application Lab - Manual 6

EXP. NO. 01 (B)

TITLE: STUDY OF INTEL 8086 MICROPROCESSOR

EC1307 – Microprocessor & Application Lab - Manual 7

16-bit pointers and data are stored as:

32-bit addresses are stored in "segment:offset" format as:

Physical memory address pointed by SEGMENT:OFFSET pair is calculated as:

Physical address = (<Segment Addr> * 16) + <Offset Addr>

EC1307 – Microprocessor & Application Lab - Manual 8

The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the

Software interrupts can be caused by:

• INT instruction - breakpoint interrupt. This is a type 3 interrupt.

Software interrupt processing is the same as for the hardware interrupts.

EC1307 – Microprocessor & Application Lab - Manual 9

Most of the registers contain data/instruction offsets within 64 KB memory

Code segment (CS) is a 16-bit register containing address of 64 KB segment with

Extra segment (ES) is a 16-bit register containing address of 64KB segment,

It is possible to change default segments used by general and index registers by