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Wakerly, Copyright 2000, and are used by permission. NO permission is given to re-use or publish these figures, in either original or modified form, in printed, electronic or any other format.
Slide Set 9 Latches Flip-flops Sequential PLAs
Output depends on current input and past history of inputs. ´Stateµ embodies all the information about the past needed to predict current output based on current input.
² State variables, one or more information bits.
Describing Sequential Circuits
² For each current-state, specify next-states as function of inputs ² For each current-state, specify outputs as function of inputs ² Like a separate combinational problem for each state
² Graphical version of state table
1/1 0/0 0/0
Very important with most sequential circuits
² State variables change state at clock edge.
Bistable element HIGH LOW LOW HIGH LOW HIGH HIGH LOW .
5 V . 5V rail Theoretical threshold center is 2.Analog analysis Assume pure CMOS thresholds.
5 V 0.0 2.0 4.5 V 5.5 V 0. 5V rail Theoretical threshold center is 2.0 2.0 2.8 V .0 4.51V 2.5 V 2.Analog analysis Assume pure CMOS thresholds.5 V 5.0 2.8 V 2.
one metastable point .Metastability Metastability is inherent in any bistable circuit Two stable points.
Another look at metastability .
Many digital designers. ´metastability resolution timeµ can be longer than one clock period.Why all the harping on metastability? All real systems are subject to it ² Problems are caused by ´asynchronous inputsµ that do not meet flip-flop setup and hold times. Especially severe in high-speed systems ² since clock periods are so short. and companies have been burned by this phenomenon. products. .
Digital Design Principles and Practices.Back to the bistable element cross-coupled inverter maintains a zero or one. 3/e . Inc. but has no provision for forcing a change enter the set-reset (S-R) latch cross-coupled NOR gates (control = 0) ==> inverter (control = 1) ==> zero out R Q S R 0 0 0 1 1 0 Q QN last Q last QN 0 1 0 1 0 0 (a) S QN (b) 1 1 Copyright © 2000 by Prentice Hall.
.S-R latch operation Metastability is possible if S and R are negated simultaneously.
S-R latch timing parameters Propagation delay Minimum pulse width .
S-R latch symbols .
S-R latch using NAND gates also called S R latch (control = 1) ==> inverter (control = 0) ==> one output Differs from NOR implementation: controls are active-low set control drives Q gate .
S-R latch with enable .
D latch .
D-latch operation latch acts like a wire while its control is active flip-flop (later) grabs data when control changes .
D-latch timing parameters Propagation delay (from C or D) Setup time (D before C edge) Hold time (D after C edge) .
Construct edge-triggered D flip-flop two D latches in series driven by opposite clock phases first stage is the master second stage is the slave master-slave D flip-flop note edge-trigger clock symbol .
Edge-triggered D flip-flop behavior .
D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK) .
Inc.Edge-triggered D flip-flop with asynchronous preset and clear (b) PR_L D Q (a) PR D Q CLK Q CLR QN CLK CLR_L Copyright © 2000 by Prentice Hall. Digital Design Principles and Practices. 3/e master slave .
but no further effect tracks D' when clock is low one when clock is high. Inc. master tracks D release during high clock ==> master reverts to cross-coupled inverters. regardless of data and assuming clear remains unasserted . but no further effect (b) PR_L D (a) PR D Q 1 assert preset forces one 1 1 Q CLK Q CLR 1 0 0 QN CLK CLR_L Copyright © 2000 by Prentice Hall. circuit exhibits pattern above. which is already cross-coupled inverters release during low-to-high at master ==> master captures D. slave tracks master (stable 1) release during low-to-high at slave ==> slave captures master. release during low clock ==> slave reverts to cross-coupled inverters. 3/e clock. Digital Design Principles and Practices. but slave isolates with stable one tracks clock'.
TTL edge-triggered D circuit Preset and clear inputs ² like S-R latch 3 feedback loops ² interesting analysis .
reverts to 1 (captured D = 1) tracking D 0 (captured D = 0) so. captured D· also stable sets Q=D stable D· 1 0 1 1 0 D 1 in either case captured D is stable tracks D· (captured D = 1) trackingor D· reverts to 1 (captured D = 0) .
multiplexes input D or output Q to flip-flop (a) D EN D Q (b) D EN CLK 0 Q QN 1 x x x CLK Q (c) Q 0 1 QN 1 0 D EN CLK Q Q 1 1 0 x x 0 1 last Q last QN last Q last QN last Q last QN CLK .Variant: edge-triggered D flip-flop --.
CMOS edge-triggered D circuit Two feedback loops (master and slave latches) Uses transmission gates in feedback loops .
Other D flip-flop variations Negative-edge triggered Clock enable Scan .
Scan flip-flops -. ² Load up (´scan inµ) a test pattern. do one normal operation.for testing TE = 0 ==> normal operation TE = 1 ==> test operation ² All of the flip-flops are hooked together in a daisy chain from external test input TI. shift out (´scan outµ) result on TO. .
J-K flip-flops .
3/e (a) S R C S C R Q Q (b) S QM QM_L S C R Q Q (c) R x 0 1 0 1 C 0 Q QN S C R Q Q Q QN x 0 0 1 1 last Q last QN last Q last QN 0 1 1 0 undef. note pulse catching S has positive glitch (of sufficient duration) during high clock ==> master sets ==> slave sets on falling clock transition . Digital Design Principles and Practices. Inc.SR master-slave Copyright © 2000 by Prentice Hall. undef.
llaH ecitnerP yb 0002 © thgirypoC e/3 . Digital Design Principles and Practices. Ignored until C is 1.secitcarP dna selpicnirP ngiseD latigiD )a( MQ L_MQ Q Q S C R S R . 3/e . Inc.fednu SR master-slave timing QM_L QM QN Q C R S Ignored since C is 0. Copyright © 2000 by Prentice Hall.)c( NQ Q Q S C R )b( Q C 0 R x 0 1 0 1 S x 0 0 1 1 C Q NQ Q Q S C R NQ tsal Q tsal NQ tsal Q tsal 1 0 0 1 .fednu . Ignored until C is 1.cnI .
JK master-slave Copyright © 2000 by Prentice Hall. Inc. Digital Design Principles and Practices. positive glitch on J during high clock sets master slave follows after clock goes low . 3/e (a) (b) J K x 0 1 0 1 C 0 Q QN (c) J C K Q Q J K C S C R Q Q QM QM_L S C R Q Q Q QN x 0 0 1 1 last Q last QN last Q last QN 0 1 1 0 last QN last Q note pulse catching still a problem if Q is zero.
llaH ecitnerP yb 0002 © thgirypoC e/3 .cnI . Inc. Ignored since QN is 0.secitcarP dna selpicnirP ngiseD latigiD R C S )a( K J C Ignored since C is 0.JK master-slave timing Q Q C K J J K C QM QM_L Q QN )c( NQ tsal Q tsal NQ tsal Q tsal Q tsal NQ tsal NQ 0 1 Q 1 0 C 0 K 1 0 0 1 x 0 1 1 0 J x )b( NQ Q Q Q S R C L_MQ MQ Q Q . Copyright © 2000 by Prentice Hall. Ignored since C is now 0. Ignored since Q is 0. 3/e . Digital Design Principles and Practices. Ignored since QN is 0.
3/e . Inc. Inc. 3/e (a) (b) J J D Q Q (c) K CLK x x 0 1 0 1 0 1 Q QN J CLK K Q Q x Q QN x 0 0 last Q last QN last Q last QN last Q last QN 0 1 1 0 K CLK CLK 1 1 last QN last Q J K CLK Q Copyright © 2000 by Prentice Hall.Edge-triggered JK flip-flop removes pulse catching Copyright © 2000 by Prentice Hall. Digital Design Principles and Practices. Digital Design Principles and Practices.
cnI .llaH ecitnerP yb 0002 © thgirypoC e/3 .secitcarP dna selpicnirP ngiseD latigiD L_K .L_RP Q L_RLC NQ KLC J Commercial edge-triggered JK flip-flop similar to edge-triggered D flip-flop .
set Q) PR_L tracking: 1 if set (J = 1.NOR requires all zeros on inputs to achieve one out transitions to zero for: set..NAND requires all ones on inputs to achieve zero out --. 3/e 1 if reset (J = 0. K = 0) CLR_L two input ones acts like inverter for remaining input 1 1 0 1 stable output Q CLK 0 1 QN J JQ· K·Q J·K + J·Q· + KQ transitions to zero for: reset. hold a zero (i. K = 0) two input ones acts like inverter for remaining input . K = 1) Q if toggle (J = 1. toggle a zero. K = 0) 0 if reset (J = 0. K = 0) tracking: 0 if set (J =© 2000 by Prentice Hall.e. K = 1) Q if hold (J = 0.e.Analysis: as before --. toggle a one. reset Q) K_L Copyright 1. Digital Design Principles and Practices. K = 1) Q· if hold (J = 0. hold a one (i. Inc. K = 1) Q· if toggle (J = 1..
3/e . K J·K + J·Q· + KQ K_L Copyright © 2000 by Prentice Hall. Digital Design Principles and Practices. K inputs 0 1 0 1 stable output Q CLK 1 0 QN J JQ· K·Q stable zero now forces stable one here while clock is high. Inc. K 1 CLR_L PR_L transitions to one no longer tracking J. independent of input changes to J.Suppose this signal transitions to zero forces stable zero while clock is high. regardless of inputs J.
T flip-flops Important for counters .
Sequential PALs 16R8 .
common clock for all Q output is fed back into AND array ² needed for state machines and other applications Common 3-state enable for all output pins .One output of 16R8 8 product terms to D input of flip-flop ² positive edge triggered.
PAL16R6 Six registered outputs Two combinational outputs (like the 16L8·s) .
GAL16V8 Finally got it right Each output is programmable as combinational or registered (diagram shows only registered outputs) Also has programmable output polarity .
GAL16V8 output logic macrocell .
GAL22V10 More inputs More product terms More flexibility .
GAL22V10 output logic macrocell .
Sequential PLD timing parameters First PLD feeding a second with same clock output from first must arrive at second at least setup time before clock edge ==> stable output time plus setup time must not exceed a clock period .
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