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‫ريزپردازنده ها‬ Microprocessors

Spring 2005

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-1

Books
 The Z80 Microprocessor , Hardware , Software programming & interfacing

 Author: Burry B. Brey  Translator: Hossein Nia  Publisher: Astane Ghodse Razavi(Beh Nashr

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-2

Books
 Microcompiuter and Microprocessor : the 8080 , 8085 , Z-80 Programming , interfacing and trubleshooting  Publisher: Nass Pub.Date: 1381 Edition Turn: 3 ISBN: 964-6264-43-4-3 Pages: 719 Author: John E . UffenbeckTranslator: Mahmmod Dayani

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-3

Books
 The 80x86 IBM PC and compatible computers (Design and interfacing of the IBM PC PS and compatible) Publisher: Baghani Pub.Date: 1379 Edition Turn: 2 ISBN: 964-91532-3-3 Pages: 760 Author: Mohammad Ali . Mazidi Janice Gillispie . MazidiTranslator: Dr. Sepidnam
hsabaghianb @ kashanu.ac.ir Microprocessors 1-4

Books
 Microcontroller 8051 Publisher: Baghani Pub.Date: 1380 ISBN: 964-7343-00-0 Pages: 380 Author: Mohammad ali Mazidi Jonis Glispi MazidiTranslator: Dr. Sepidnam

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-5

Books
 The 8051 Microcontroller Publisher: Baghani Pub.Date: 1380 Publishing Turn: 5 Edition Turn: 3 ISBN: 964-91532-2-5 Pages: 383 Author: Iscott Makenzi Translator: Rezaei Nia ,Darbandi Azar
hsabaghianb @ kashanu.ac.ir Microprocessors 1-6

ac. small computer uP + peripheral I/O + memory specifically for data acquisition and control applications  u-Computer on a single chip of silicon Microprocessors 1-7  Micro-computer (u-Computer)  Microcontroller (uC) hsabaghianb @ kashanu. instruction decoder. bus control circuit.ir . Components of CPU ALU. registers.Intruduction  Microprocessor (uP)(MPU) A uP is a CPU on a single chip. etc.

ROM . num of port is seletable RAM is larger than ROM (usually) contains a CPU and RAM. uC  A uP     only is a single-chip CPU bus is available RAM capacity.ac. I/O port in a single IC internal hardware is fixed Communicate by port ROM is larger than RAM (usually) Small power consumption Single chip. small board Implementation is easy Low cost  A uC         hsabaghianb @ kashanu.ir Microprocessors 1-8 .uP vs.Prepherals.

ac. uC – cont.uP vs.ir Microprocessors 1-9 .  Applications uCs are suitable to control of I/O devices in designs requiring a minimum component uPs are suitable to processing information in computer systems. hsabaghianb @ kashanu.

 Only single chip can be a complete system  interfacing to other devices. motors. and communicate with PC. I/O .uP vs.  uC is easy to use and design.  for example.ac. sensors. similar system that builds from uP would require a lot of additional units. UART. displays. uC – cont. TIMER and etc.  In contrast. hsabaghianb @ kashanu.ir Microprocessors 1-10 .  such as RAM.

In order to change circuit’s functionality. input to output or digital to analog on the fly. hsabaghianb @ kashanu.uC is a Reusable Hardware  Logic circuit provides limited function for one single design.ir Microprocessors 1-11 .  uC can reprogram and change functionality of every port.ac. we need to redesign the circuits.

68HC11.  8051. and etc.  We may widely divide it with how it is designed  RISC/CISC architecture.ir Microprocessors 1-12 .  What is the main difference between RISC/CISC?  Does it make any difference to our application? hsabaghianb @ kashanu.ac.uCs  Many uCs are existing right now. MSP430. ARM series.

hsabaghianb @ kashanu.ac. and Execute the instruction  The internal architecture of the microprocessor is complex. Decode .The Microprocessor (MPU)  The uP is the ‘brain of the microcomputer’  Is a single chip which is capable of  processing data  controlling all of the components which make up the microcomputer system  µP used to sequence executions of instructions that is in memory  uP Fetch .ir Microprocessors 1-13 .

 The Arithmetic Logic unit (ALU): This part of the MPU performs both arithmetic and logical operations  Timing and Control Circuits: that keep all of the other parts of system (Regs.ir Microprocessors 1-14 .ac. memory & I/O) working together in the right time sequence hsabaghianb @ kashanu.The Microprocessor (MPU)  microprocessor (MPU) typically contains  Registers: Temporary storage locations for program instruction or data. ALU.

ir Microprocessors 1-15 .ac.Microcomputers  All Microcomputers consist of (at least) :       1. Microprocessor Unit (MPU) 2. Input / Output ports 5. Bus System (and Software)  MPU is the brain of microcomputer hsabaghianb @ kashanu. Data Memory (RAM) 4. Program Memory (ROM) 3.

ac.ir Microprocessors 1-16 .Microcomputers hsabaghianb @ kashanu.

 I/O ports connect both digital and analogue devices by DAC and ADC hsabaghianb @ kashanu.  An input port is a circuit through which an external device can send signals (data?) to the MPU.ac.ir Microprocessors 1-17 .The Input/Output (I/O) System  I/O is the link between the MPU and the outside world.  An output port is a circuit that allows the MPU to send signals (data?) to external devices.

Bus  A Bus is a common communications pathway used to carry information between the various elements of a computer system  The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another  The individual subsystems of the digital computer are connected through an interconnecting BUS system. hsabaghianb @ kashanu.ac.ir Microprocessors 1-18 .

Bus There are three main bus groups  ADDRESS BUS  DATA BUS  CONTROL BUS hsabaghianb @ kashanu.ir Microprocessors 1-19 .ac.

Data Bus  The Data Bus carries the data which is transferred throughout the system.  Data being sent from MPU to I/O port  Data being read from I/O port going to MPU  Results from MPU sent to Memory  These are called read and write operations hsabaghianb @ kashanu.ac.ir Microprocessors 1-20 . ( bi-directional)  Examples of data transfers  Program instructions being read from memory into MPU.

 The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.ir Microprocessors 1-21 .ac. hsabaghianb @ kashanu.Address Bus  An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer  The Address Bus is used to transmit the address of the location to the memory or the I/O port.

ac.Control Bus  The Control Bus: is another group of signals whose functions are to provide synchronization ( timing control ) between the MPU and the other system components.  Example Control signals  RD: read signal asserted to read data into MPU  WR: write signal asserted to write data from MPU hsabaghianb @ kashanu.ir Microprocessors 1-22 . and are mainly outputs from the MPU.  Control signals are unidirectional.

Contains program (Firmware). When power up will contain random data values Microprocessors 1-23  Main memory Types hsabaghianb @ kashanu.ir . does not lose its contents when power is removed (Non-volatile)  RAM: random access memory (read/write memory) used as variable data.Main memory  The duties of the memory are :  To store programs  To provide data to the MPU on request  To accept result from the MPU for storage  ROM : read only memory. loses contents when power is removed volatile.ac.

the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap ) hsabaghianb @ kashanu. when the power is turned on.Read-Only Memory  uP can read instructions from ROM quickly  Cannot write new data to the ROM  ROM remembers the data.ac.ir Microprocessors 1-24 . even after power cycled  Typically.

fast reading)  EEPROM (electrically erasable read-only memory.ir Microprocessors 1-25 . usually must write a whole block not just 1 byte or 2 bytes.Available ROMs  Masked ROM or just ROM  PROM or programmable ROM(once only)  EPROM (erasable via ultraviolet light)  Flash (can be erased and re-written about 10000 times. slow writing.ac. hsabaghianb @ kashanu. also known as EEROM—both reading and writing are very slow but can program millions of times… useless for storing a program but good for say configuration information.

ac.ROM m+1 bit Address A0 A1 A2 Am D0 D1 D2 Capacity : 2 m +1 2m+1 × ( n + 1) ROM PROM EEPROM n+1 bit Data Dn OE : Output Enable connect to RD of uP : Chip Enable to Address decoder CE (CS ) CE OE hsabaghianb @ kashanu.ir Microprocessors 1-26 .

ir Microprocessors 1-27 .ac.Timing Diagram for a Typical ROM A0-Am D0-Dn CE OE OE falls to data valid Addr valid to data valid hsabaghianb @ kashanu.

ac.27XX EPROM U 1 8 7 6 5 4 3 2 1 23 22 19 20 18 21 A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 O O O O O O O O 0 1 2 3 4 5 6 7 9 10 11 13 14 15 16 17 U 3 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 1 A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 O O O O O O O O 0 1 2 3 4 5 6 7 11 12 13 15 16 17 18 19 U2 8 7 6 5 4 3 2 1 23 22 19 21 20 18 A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 O O O O O O O O 0 1 2 3 4 5 6 7 9 10 11 13 14 15 16 17 OE C E V P P O E /V P P CE OE P GM C E V P P 16 kbit 2 kbyte 2716 2732 32 kbit 4 kbyte 2764 64 kbit 8 kbyte PGM and VPP are used to programming hsabaghianb @ kashanu.ir Microprocessors 1-28 .

27XXX EPROM U 7 U4 10 9 8 7 6 5 4 3 25 24 21 23 2 26 22 27 20 1 A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 D D D D D D D D 0 1 2 3 4 5 6 7 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 22 20 1 U 5 A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D D D D D D D D 0 1 2 3 4 5 6 7 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 22 20 28 U 6 A A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 O O O O O O O O 0 1 2 3 4 5 6 7 11 12 13 15 16 17 18 19 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 1 A A A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D D D D D D D D 0 1 2 3 4 5 6 7 13 14 15 17 18 19 20 21 OE P GM CE V P P OE C E V P P O E /V P P C E V CC OE P GM C E V P P 27128 27256 27512 27010 128 kbit 16 kbyte hsabaghianb @ kashanu.ac.ir 256 kbit 32 kbyte 512 kbit 64 kbyte 1024 kbit 128 kbyte Microprocessors 1-29 .

ir Microprocessors 1-30 .28XX E2PROM 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 24 31 22 32 A A A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D D D D D D D D 0 1 2 3 4 5 6 7 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 24 31 22 32 A A A A A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D D D D D D D D 0 1 2 3 4 5 6 7 13 14 15 17 18 19 20 21 8 7 6 5 4 3 2 1 23 22 19 20 21 18 24 A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 9 10 11 13 14 15 16 17 10 9 8 7 6 5 4 3 25 24 21 23 2 22 27 20 28 A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 R D Y /B 10 11 12 I/ O I/ O I/ O I/ O I/ O I/ O I/ O I/ O 0 1 2 3 4 5 6 7 11 12 13 15 16 17 18 19 1 U S Y 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 22 27 20 28 A A A A A A A A A A A A A A A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D D D D D D D D 0 1 2 3 4 5 6 7 11 12 13 15 16 17 18 19 OE W E CE V C C OE W E C E V CC OE W E C E V CC OE W E C E V CC OE W E CE V C C 2816 16 kbit 2 kbyte 2864 64 kbit 8 kbyte 28256 256 kbit 32 kbyte 28010 1026 kbit 128 kbyte 28040 4096 kbit 512 kbyte hsabaghianb @ kashanu.ac.

hsabaghianb @ kashanu. applied for cache . no refresh Dynamic RAM (DRAM): cap base.RAM (Random Access Memory)  The uP can read the data from RAM quickly. low cap/vol.ac. applied for main memory(pc) need refresh. slow . low cost high capacity/volume .ir Microprocessors 1-31 . fast. expensive.  The uP can write new data quickly to RAM  RAM forgets its data if power is turned off  Two type of is available : Static RAM(SRAM): ff base.

ir Data bus is Bidirectional CS WR RD Microprocessors 1-32 .ac.RAM(Static) m+1 bit Address A0 A1 A2 Am D0 D1 D2 Capacity : 2 m +1 2m+1 × ( n + 1) RAM n+1 bit Data Dn RD : Read signal connect to MemRD of uP WR : Write signal connect to MemWR of uP CS : Chip Select to Address decoder hsabaghianb @ kashanu.

Session 2  Microprocessors  History  Data width  8086 vs 8088  8086 pin description  Z80 Pin description hsabaghianb @ kashanu.ir Microprocessors 1-33 .ac.

Microprocessors  Microprocessors come in all kinds of varieties from the very simple to the very complex  Depend on data bus and register and ALU width uP could be 4-bit .ir Microprocessors 1-34 . 64-bit  We will discuss two sample of it  Z80 as an 8-bit uP  and 8086/88 as an 16-bit uP  All uPs have  the address bus  the data bus  RD. INT.ac. 32-bit . 16-bit. . CLK . hsabaghianb @ kashanu. RST. . . WR. 8-bit .

ac.ir .History Company 4 bit 8 bit 16 bit 32 bit 64 bit intel 4004 4040 8008 8080 8085 Z80 8088/6 80186 80286 Z8000 Z8001 Z8002 68006 68008 68010 80386 80486 80860 pentium zilog Motorola 6800 6802 6809 68020 68030 68040 Microprocessors 1-35 hsabaghianb @ kashanu.

Internal and External Bus  Internal bus is a pathway for data transfer between registers and ALU in the uPs  External bus is available externally to connect to RAM. Bus width may be different  For example In 8088 Int. bus is 8-bit In 8086 Int. Ext. Bus is 16-bit . Ext. bus is 16-bit hsabaghianb @ kashanu. ROM and I/O  Int.ir Microprocessors 1-36 . and Ext. Bus is 16-bit .ac.

ac.8086 vs 8088 Only external bus of 8088 is 8_bit U? 33 22 19 21 18 MN REA DY C LK RES ET IN T R 16 A D 0 15 A D 1 14 A D 2 13 A D 3 12 A D 4 11 A D 5 10 A D6 9 A D7 8 A D8 7 A D9 6 A D 1 05 A D 1 14 A D 1 23 A D 1 32 A D 1 439 A D 1 538 A 1 6 / S 33 7 A 1 7 / S 43 6 A 1 8 / S 53 5 A 1 9 /S 6 34 B H E /S 7 26 D E N 27 D T /R 2 8 M /IO 32 R D 29 W R 25 A LE 24 IN T A 33 22 19 21 18 U? MN REA DY C LK RES ET IN T R A A A A A A A A D0 D1 D2 D3 D4 D5 D6 D7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 1 6 /S 1 7 /S 1 8 /S 1 9 /S 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 39 38 33 7 43 6 53 5 6 34 8_bit Data Bus 20_bit Address 16_bit Data Bus 20_bit Address A A A A SSO 30 31 17 23 H LD A H O LD NMI TE S T 8 0 8 6 M IN 30 31 17 23 H LD A H O LD NMI TE S T 8 0 8 8 M IN 26 D E N 27 D T /R 2 8 IO /M 32 R D 29 W R 25 A LE 24 IN T A 8086 8088 Microprocessors 1-37 hsabaghianb @ kashanu.ir .

8086 Pin Assignment hsabaghianb @ kashanu.ac.ir Microprocessors 1-38 .

A17/S4. A18/S5. A19/S6. Active High) : take uP to wait state CLK (input) : Provides basic timing for the processor RESET (input. A8.ac. Active High) : Hold Ack INTR (input . A16/S3 : 20 -bit Address Bus MN/MX’ (input) : Indicates Operating mode READY (input . Active High) : At least 4 clock cycles Causes the uP immediately terminate its present activity..AD7 . Active High) : Interrupt request INTA’ (output .A15 . Active High) : Connect this to LOW HLDA (output .ir Microprocessors 1-39 .8086 Pin Description Vcc (pin 40) : Power Gnd (pin 1 and 20) : Ground AD0. Active Low) : Interrupt Acknowledge NMI (input . Active Low) : Connect this to HIGH HOLD (input .. TEST’ (input . Active High) : Non-maskable interrupt hsabaghianb @ kashanu.

A16/S3 as address lines hsabaghianb @ kashanu. A17/S4. uP is performing a read operation WR’ (output) : When Low.ac.8086 Pin Description DEN’ (output) : Data Enable. Active High Provided by uP to latch address When HIGH. A18/S5. A19/S6. When High. data is from memory to uP (to74245 dir) IO/M’ (output) : If High uP access I/O Device. If Low uP access memory RD’ (output) : When Low. data from uP to memory When Low.ir Microprocessors 1-40 . uP is using AD0. uP is performing a write operation ALE (output) : Address Latch Enable . It is LOW when processor wants to receive data or processor is giving out data (to74245) DT/R’ (output) : Data Transmit/Receive..AD7.

ac.ir Microprocessors 1-41 .Z80 CPU Pin Assignment M1 27 19 20 21 22 28 18 24 16 17 26 25 23 14 15 12 8 7 6 11 29 9 10 13 30 31 32 33 34 35 36 37 38 39 40 System Control Lines M REQ IOR Q RD WR RFSH H ALT - CPU Control Lines W AIT IN T NM I RESET - Z .80 CPU 1 2 3 4 5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 Address Bus Bus Control Lines BU SR Q B U SA K  + 5V GND Data Bus hsabaghianb @ kashanu.

I/O and interrupts.Z80 Pin Description A15-A0 : Address bus (output. 3-state). 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.ac. D7-D0 : Data Bus (input/output. Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus. active high. active high. active Low. hsabaghianb @ kashanu. Used for data exchanges with memory. active Low. RD: Read (output. 3-state). 3-state) indicates that the CPU wants to read data from memory or I/O WR: Write (output.ir Microprocessors 1-42 .

Together with MREQ indicates refresh cycle. active Low). See M1 Machine Cycle One (output. Lower 7-bits address is refresh address to DRAM hsabaghianb @ kashanu.3-state) Indicates I/O read/write operation. active Low.ac. active Low).ir Microprocessors 1-43 . Indicates memory read/write operation.active Low. Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle RFSH Refresh (output. See M1 Input/Output Request(output. 3-state).Z80 Pin Description MREQ IORQ M1 Memory Request (output.

Recognized at the end of the current Instruction Independent of the status of IFF Forces the CPU to restart at location 0066H.Z80 Pin Description INT Interrupt Request (input. Interrupt Request is generated by I/O devices. hsabaghianb @ kashanu. negative edge-triggered).ir Microprocessors 1-44 . active Low). Higher priority than INT. Checked at the end of the current instruction If flip-flop (IFF) is enabled.ac. NMI Non-Maskable Interrupt (Input.

and control signals MREQ. RD.ir Microprocessors 1-45 .ac. and WR to high-imp. BUSACK Bus Acknowledge (output. IORQ. hsabaghianb @ kashanu.Low) indicates to the requesting device that address. IORQ.Z80 Pin Description BUSREQ Bus Request (input. higher priority than NMI recognized at the end of the current machine cycle. active. data bus. and WR have entered their high-impedance states. RD. active Low). forces the CPU address bus. and MREQ. data.

RESET initializes the CPU as follows: Resets the IFF Clears the PC and registers I and R Sets the interrupt status to Mode 0. active Low).ac. During reset time.ir Microprocessors 1-46 . must be active for a minimum of three full clock cycles before the reset operation is complete. the address and data bus go to a high-impedance state And all control output signals go to the inactive state.Z80 Pin Description RESET Reset (input. hsabaghianb @ kashanu.

ac.Z80 CPU 8 IN T E R N A L D A T A B U S (8 B IT ) B U F F E R F F' MUX IN S T R U C T IO N R E G IS T E R W' Z' W MUX A Z D ATA BU S I R TM P A' B' D' H' C' E' L' IX IY SP B D H C E L ACT DECODER CO NTRO LLER SEQUENCER ALU PC ±k ±k 16 IN T E R N A L A D D R E S S B U S (1 6 B IT ) CONTROL S E C T IO N B U F F E R ADDRESS BUS 13 IN T E R N A L C O N T R O L B U S B U F F E R C O NTRO L BUS hsabaghianb @ kashanu.ir Microprocessors 1-47 .

ac.ir Microprocessors 1-48 .Z80 Programming Model hsabaghianb @ kashanu.

ir (BC)<->(BC') . AF ’ what is this instruction useful for? hsabaghianb @ kashanu.ac. (HL)<->(HL') (AF)<->(AF') Microprocessors 1-49 . (DE)<->(DE') .Register Set  A : Accumulator Register  F : Flag register  Two sets of six general-purpose registers D’ E’ H’ L’) may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’ or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’)  The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’) not visible to the programmer but can access via: EXX EX AF.

Register Set(cont)  4 16-bit registers hold memory address (pointers)  index registers (IX) and (IY) are 16-bit memory pointers  16 bit stack pointer (SP)  Program counter (PC)  Program counter (PC)  PC points to the next opcode to be fetched from ROM  when the µP places an address on the address bus to fetch the byte from memory.  R : memory Refresh register hsabaghianb @ kashanu. it then increments the program counter by one to the next location  Special purpose registers  I : Interrupt vector register.ac.ir Microprocessors 1-50 .

Flag Register
7 6 5 4 3 2 1 0

S Z X H X
S Z H P V N C

P V

N C

Sign Flag (1:negativ)* Zero Flag (1:Zero) Half Carry Flag (1: Carry from Bit 3 to Bit 4)** Parity Flag (1: Even) Overflow Flag (1:Overflow)* Operation Flag (1:previous Operation wassubtraction)** Carry Flag (1: Carry from Bit n-1 to Bit n, with n length of operand)

*: 2-complement number representation **: used in DAA-operation for BCD-arithmetic
hsabaghianb @ kashanu.ac.ir Microprocessors 1-51

DAA - Decimal Adjust Accumulator
Adjusts the content of the Accumulator A for BCD addition and subtraction operations such as ADD, ADC, SUB, SBC, and NEG according to the table:
before DAA Op ADD ADC N 0 0 0 0 0 0 0 0 0 1 1 1 1 C 0 0 0 0 0 0 1 1 1 0 0 1 1 Bits 4-7 0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3 0-9 0-8 7-F 6-F H 0 0 1 0 0 1 0 0 1 0 1 0 1 Bits 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3 0-9 6-F 0-9 6-F after DAA A=A+.. 00 06 06 60 66 66 60 66 66 00 FA A0 9A C 0 0 0 1 1 1 1 1 1 0 0 1 1
Microprocessors 1-52

SUB SBC NEG

hsabaghianb @ kashanu.ac.ir

Instruction cycles, machine cycles and “T-states”
 Instruction cycle is the time taken to complete the execution of an instruction  Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc.  T-state = 1/f (f:Z80 Clock Frequency)
f= 4MHZ  T-state=0.25 uS

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-53

Basic CPU Timing Example hsabaghianb @ kashanu.ac.ir Microprocessors 1-54 .

ir Microprocessors 1-55 .Opcode Fetch Bus Timings (M1 Cycle) hsabaghianb @ kashanu.ac.

So bit 7 stays the same  Bit 7 can be changed using the LD R.  Bit 7 of it is never changed by this.The R register  Is increased at every first machine cycle (M1).A access the R register after it is increased  R is often used in programs for a random value.A instruction.R and LD R. hsabaghianb @ kashanu.  LD A. only the lower 7 bits are included in the addition. so the instructions are re-executed.ac.ir Microprocessors 1-56 . which is good but of course not truly random.  the block instructions decrease the PC with two.

Memory read/write cycle hsabaghianb @ kashanu.ac.ir Microprocessors 1-57 .

ir Microprocessors 1-58 .Adding One Wait State to an M1 Cycle hsabaghianb @ kashanu.ac.

ir Microprocessors 1-59 .Adding One Wait State to Any Memory Cycle hsabaghianb @ kashanu.ac.

ir Microprocessors 1-60 .IO read/write cycle During I/O operations a single wait state is automatically inserted hsabaghianb @ kashanu.ac.

ir Microprocessors 1-61 .ac.Bus Request/Acknowledge Cycle hsabaghianb @ kashanu.

Interrupt Request/Acknowledge Cycle Two wait states are automatically added to this cycle hsabaghianb @ kashanu.ir Microprocessors 1-62 .ac.

ir Microprocessors 1-63 .Non-Maskable Interrupt Request Operation hsabaghianb @ kashanu.ac.

each cell needs to be periodically refreshed  During T3 and T4 (when Z80 is performing internal ops).ac. the low order address is used to supply a 7-bit address for refresh hsabaghianb @ kashanu. which store Information as capacitive charges.M1 Refresh Cycle  Takes 4T to 6Ts  Z80 includes built in circuitry for refreshing DRAM  This simplifies the external interfacing hardware  DRAM consists of MOS transistors.ir Microprocessors 1-64 .

ir Microprocessors 1-65 .ac.Wait Signal  the Z80 samples the wait signal during T2 if low then Z80 adds wait  states to extend the machine cycle  used to interface memories with slow response time  Slow memory is low cost hsabaghianb @ kashanu.

ir Microprocessors 1-66 .Interrupts There are two types of interrupts:  non mask-able (NMI) Could not be masked Jump to 0066H of memory  mask-able(INT) Has 3 mode Can be set with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets Interrupt mode 2 hsabaghianb @ kashanu.ac.

ir Microprocessors 1-67 .Interrupt Modes  Mode 0:  An 8 bit opcode is Fetched from Data BUS and executed  The source interrupt device must put 8 bit opcode at data bus  8 bit opcode usually is RST p instructions  Mode 1:  A jump is made to address 0038h  No value is required at data bus  Mode 2:  A jump is made to address (register I × 256 + value from interrupting device that puts at bus)  I is high 8 bit of interrupt vector  Value is low 8 bit of interrupt vector hsabaghianb @ kashanu.ac.

ir Microprocessors 1-68 .hsabaghianb @ kashanu.ac.

 Instruction groups  Load and Exchange  Block Transfer and Search  Arithmetic and Logical  Rotate and Shift  Bit Manipulation (Set. Test)  Jump.ac.ir Microprocessors 1-69 . and Return  Input/Output  Basic CPU Control hsabaghianb @ kashanu. Call. Reset.Z80 CPU Instruction Description  158 different instruction types  Including all 78 of the 8080A CPU.

ir Microprocessors 1-70 .ac.Addressing Modes  Immediate  Immediate Extended  Modified Page Zero Addressing (rst p)  Relative Addressing  Jump Relative (2 byte)  One Byte Op Code  8-Bit Two’s Complement Displacement (A+2)  Extended Addressing  Absolute jump  One byte opcode  2 byte address  Indexed Addressing  (Index Register + Displacement) (IX+d)  2 byte opcode  1 byte displacement hsabaghianb @ kashanu.

and test instructions.)  Register Addressing LD C.ir Microprocessors 1-71 . SET 3.B hsabaghianb @ kashanu.B  Implied Addressing Op Code implies other operand(s) ADD E  Register Indirect Addressing 16-bit CPU register pair as pointer (such as HL) ADD (HL)  Bit Addressing set.A RES 7.ac. reset.Addressing Modes(cont.

80 CPU Data Bus Control Bus Input Output (I/O) Out In hsabaghianb @ kashanu.ac. RAM) Power Supply Address Bus Z .ir Microprocessors 1-72 .Minimal Configuration of a Z80 Microcomputer Clock Generator Memory (ROM.

ir Microprocessors 1-73 .ac.Z80 Memory connection  CPU 16 bit address bus  64 k memory(max)  CPU 8 bit data bus  8 bit data width  Generally should be connected Data to data Address to address Wr to wr Rd to rd Mreq to cs hsabaghianb @ kashanu.

Memory connection (cont.ir Microprocessors 1-74 .ac.)  If only one RAM chip Full size (64 kb capacity) D7~D0 D7~D0 RAM 64 kb A15~A0 A15~A0 Z80 CPU RD WR RD WR CS MREQ hsabaghianb @ kashanu.

Memory connection (cont.ac.ir Microprocessors 1-75 .)  If RAM capacity was 32 kb  A15 composed with MREQ  RAM area is from 0000h to 7FFFh D7~D0 D7~D0 RAM 32 kb A14~A0 A14~A0 Z80 CPU RD WR RD WR CS A15 MREQ hsabaghianb @ kashanu.

ac. Microprocessors 1-76 hsabaghianb @ kashanu. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.ir . The two memory chips will provide data at the same time when microprocessor performs a memory read.  Solution: Use address line A15 as an “arbiter”.)  There is two 32 kb RAM  Problem: Bus Conflict.Memory connection (cont.

 There is two 32 kb RAM  A15 applied to select one RAM chip  Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1) D7~D0 D7~D0 RAM 32 kb D7~D0 A14~A0 RD WR CS Memory connection (cont.) RAM 32 kb A14~A0 A14~A0 RD WR CS Z80 CPU RD WR A15 MREQ hsabaghianb @ kashanu.ac.ir Microprocessors 1-77 .

ir Microprocessors 1-78 .ac.Memory connection (cont.)  32 kb ROM and 32 kb RAM  ROM doesn’t have wr signal D7~D0 D7~D0 ROM 32 kb D7~D0 A14~A0 RAM 32 kb A14~A0 A14~A0 OE CS Z80 CPU RD WR RD WR CS A15 MREQ hsabaghianb @ kashanu.

ac.Memory connection (cont.ir A14 A15 MREQ En S0 S1 Microprocessors 1-79 .) There is 4 memory chip A14 and A15 applied to chip selection D7~D0 A13~A0 Z80 CPU D7~D0 ROM 16 kb A13~A0 OE CS RAM RAM RAM 16 kb 16 kb 16 kb A13~A0 A13~A0 A13~A0 RD WR CS D7~D0 D7~D0 D7~D0 RD WR CS RD WR CS RD WR hsabaghianb @ kashanu.

ir .Address Bit Map Selects chip A15 to A0 (HEX) 0000h 3FFFh 4000h 7FFFh 8000h BFFFh C000h FFFFh Selects location within chips AAAA 1198 10 0000 1111 0000 1111 0000 1111 0000 1111 AAAA 7654 0000 1111 0000 1111 0000 1111 0000 1111 AAAA 3210 0000 1111 0000 1111 0000 1111 0000 1111 RAM3 Microprocessors 1-80 AA AA 11 11 54 32 00 00 00 11 01 00 01 11 10 00 10 11 11 00 11 11 Memory Chip ROM RAM1 RAM2 hsabaghianb @ kashanu.ac.

ac.ir A14 A15 .Memory Map  Represents the memory type  Address area of each memory chip  Empty area D7~D0 D7~D0 ROM 16 kb A13~A0 A13~A0 A13~A0 CS 0000h 3FFFh 4000h 7FFFh 8000h BFFFh C000h FFFFh ROM 16k RAM1 16k D7~D0 RAM 16 kb D7~D0 RAM 16 kb A13~A0 D7~D0 RAM 16 kb A13~A0 OE RD WR CS RD WR CS RD WR CS RAM2 16k RD WR MREQ En S0 S1 RAM3 16k Microprocessors 1-81 hsabaghianb @ kashanu.

ir A14 A15 MREQ En S0 S1 RAM3 FFFFh Microprocessors 1-82 .ac.Memory Map  Empty Area cann’t write and read  Read op. cann’t store any value on it 3FFFh 4000h Empty D7~D0 D7~D0 ROM 16 kb A13~A0 A13~A0 A13~A0 CS 0000h ROM D7~D0 RAM 16 kb D7~D0 RAM 16 kb A13~A0 7FFFh 8000h OE RD WR CS RD WR CS RAM2 BFFFh C000h RD WR hsabaghianb @ kashanu. returns FFh value (usualy)  Write op.

Memory Map  Empty Area cann’t write and read  Read op. returns FFh value (usualy)  Write op.ac.ir A14 A15 MREQ En S0 S1 FFFFh Microprocessors 1-83 . cann’t store any value on it 3FFFh 4000h Empty D7~D0 D7~D0 ROM 16 kb A13~A0 A13~A0 A13~A0 CS 0000h ROM D7~D0 RAM 16 kb 7FFFh 8000h OE RD WR CS RAM BFFFh C000h Empty RD WR hsabaghianb @ kashanu.

ir Microprocessors 1-84 .Full and Partial Decoding  Full (exhaust) Decoding  All of the address lines are connected to any memory/device to perform selection  Absolute address : any memory location has one address  Partial Decoding  When some of the address lines are connected the memory/device to perform selection  Using this type of decoding results into roll-over addresses (fold back or shading).ac.  roll-over address : any memory location has more than one address hsabaghianb @ kashanu.

ac.Partial Decoding  A15~A12 has no connection  Then doesn’t play any role in addressing  What is the Memory and Address Bit map? D7~D0 D7~D0 RAM 4 kb A11~A0 A15~A12 X A11~A0 RD WR CS Z80 CPU RD WR MREQ hsabaghianb @ kashanu.ir Microprocessors 1-85 .

0000h 0FFFh 1000h 1FFFh 2000h 2FFFh 3000h 3FFFh RAM RAM’ RAM’ RAM’ F000h FFFFh RAM’ F000h D7~D0 D7~D0 A15 to A0 (HEX) X000h XFFFh AAAA 1111 5432 xxxx xxxx AAAA 1198 10 0000 1111 AAAA 7654 0000 1111 AAAA 3210 0000 1111 Memory Chip A11~A0 A15~A12 A11~A0 RAM 4 kb X RD WR CS RAM Z80 CPU RD WR MREQ hsabaghianb @ kashanu.ac. …………….ir Microprocessors 1-86 .Partial Decoding  Every memory location has more than one address  For example first RAM location has addresses: 0000h 1000h 2000h 3000h Roll-over Address …………….

Partial Decoding  A12 only connected to RAM  A13 has no connection  What is the memory map? D7~D0 D7~D0 ROM 4 kb D7~D0 A12~A0 RAM 8 kb A12~A0 A13 A11~A0 X OE CS RD WR CS Z80 CPU A15 A14 hsabaghianb @ kashanu.ac.ir RD WR MREQ Microprocessors 1-87 .

Partial Decoding  8 roll-over address for ROM  4 roll-over address for RAM D7~D0 D7~D0 D7~D0 ROM 4 kb A12~A0 A11~A0 A12~A0 RAM 8 kb AAAA 1111 5432 0xxx 0xxx X0x0 X0x1 AAAA 1198 10 0000 1111 0000 1111 AAAA 7654 0000 1111 0000 1111 AAAA 3210 0000 1111 0000 1111 Memory Chip Z80 CPU A13 X OE CS RD W R CS ROM RD WR MREQ RAM hsabaghianb @ kashanu.ir A15 A14 Microprocessors 1-88 .ac.

ir A15 A14 MREQ 5FFFh 6000h 5FFFh 6000h 6FFFh AAAA 1198 10 0000 1111 0000 1111 AAAA 7654 0000 1111 0000 1111 AAAA 3210 0000 1111 0000 1111 Memory Chip 4k 7000h 7FFFh 8000h 7FFFh F000h RAM ROM 8k 9FFFh A000h RAM RAM’ BFFFh C000h Microprocessors 1-89 .ac.Partial Decoding D7~D0 D7~D0 D7~D0 0000h 0000h RAM’ 1FFFh 0FFFh 1000h 1FFFh ROM Conflict ROM’ 2000h 2FFFh 3000h 3FFFh 4000h 4FFFh 5000h ROM 4 kb A12~A0 A11~A0 A12~A0 RAM 8 kb 2000h ROM’ ROM’ ROM’ ROM’ ROM’ ROM’ RAM’ 3FFFh 4000h Z80 CPU A13 X OE CS RD W R C S RD WR AAAA 1111 5432 0xxx 0xxx X0x0 X0x1 hsabaghianb @ kashanu.

Partial Decoding D7~D0 D7~D0 D7~D0 0000h 0000h 0FFFh 1000h ROM ROM’ 1FFFh 1FFFh ROM 4 kb A12~A0 A11~A0 A12~A0 RAM 8 kb 2000h 2000h 2FFFh 3000h ROM’ ROM’ ROM’ ROM’ ROM’ ROM’ Z80 CPU A13 X OE CS RD W R C S 3FFFh 4000h RD WR Conflict RAM’ 4000h 4FFFh 5000h 5FFFh 6000h 3FFFh AAAA 1111 5432 0xxx 0xxx X1x0 X1x1 hsabaghianb @ kashanu.ac.ir A15 A14 MREQ 5FFFh 6000h AAAA 1198 10 0000 1111 0000 1111 AAAA 7654 0000 1111 0000 1111 AAAA 3210 0000 1111 0000 1111 RAM’ Memory Chip 4k 7FFFh 8000h 6FFFh 7000h 7FFFh F000h ROM 8k 9FFFh A000h RAM BFFFh C000h RAM Microprocessors 1-90 .

Full (exhaustive) decoding AAAA 1111 5432 0000 0001 0010 0010 AAAA 1198 10 0000 1111 0000 0111 AAAA 7654 0000 1111 0000 1111 AAAA 3210 0000 1111 0000 1111 RAM ROM Memory Chip A12~A0 A12~A0 D7~D0 2764 EPROM 8k× 8 OE RD CE D7~D0 A13 A12 A11 C B A Y0 0000h-07FFh Y1 0800h-0FFFh Y2 1000h-17FFh Y3 Y4 Y5 Y6 Y7 1800h-1FFFh 2000h-27FFh 7421 A10~A0 74138 A15 A14 MREQ A10~A0 D7~D0 6116 RWM 2k× 8 G2A G2B G1 RD WR CS RD WR hsabaghianb @ kashanu.ir Microprocessors 1-91 .ac.

ir Microprocessors 1-92 .Partial decoding AAAA 1111 5432 0000 0001 001x 001x AAAA 1198 10 0000 1111 x000 x111 AAAA 7654 0000 1111 0000 1111 AAAA 3210 0000 1111 0000 1111 RAM ROM Memory Chip A12~A0 A12~A0 D7~D0 2764 EPROM 8k× 8 OE RD CE D7~D0 A15 A14 A13 C B A Y0 Y2 0000h-1FFFh Y1 2000h-3FFFh Y3 Y4 Y5 Y6 Y7 RD WR A10~A0 74138 MREQ GND VCC A10~A0 D7~D0 6116 RWM 2k× 8 G2A G2B G1 RD WR CS hsabaghianb @ kashanu.ac.

ir Microprocessors 1-93 .1 Bit Memory With Separated I/O D7-D0 D7 D1 D0 Din A11-A0 A11~A0 2147 RWM 4k× 1 Din A11-A0 A11~A0 2147 RWM 4k× 1 Din A11~A0 A11-A0 2147 RWM 4k× 1 Dout Dout Dout WR/ RD CS WR/ RD CS WR/ RD CS WR / RD CS hsabaghianb @ kashanu.ac.

bit) map A12~A0 D7~D0 2764 EPROM 8k× 8 OE RD D7-D0 CE A15 A14 A13 C B A Y0 Y1 Y2 Y3 Y4 0000h-1FFFh 2000h-3FFFh D7 D1 D0 74138 MREQ GND VCC Din A11-A0 A11~A0 Dout 2147 RWM 4k× 1 Din A11-A0 A11~A0 Dout 2147 RWM 4k× 1 Din A11~A0 Dout A11-A0 2147 RWM 4k× 1 G2A G2B G1 WR Y5 Y6 Y7 WR W R/ R D C S W R/ R D C S W R/ R D C S RD hsabaghianb @ kashanu.ir Microprocessors 1-94 .ac.What is the memory(addr.

ac.ir Microprocessors 1-95 .Adding RAM & ROM hsabaghianb @ kashanu.

ir Microprocessors 1-96 .ac.Minimum Z80 Computer System hsabaghianb @ kashanu.

Control) INT - INT - INT IEO IEI IEO W/RDYB - Z80 CPU +5V IEI CTC ZC/TO1 ZC/TO2 SIO TxCA TxCB RxCA RxCB - hsabaghianb @ kashanu.Z80-µP-Family (Typical Environment) PIO INT - +5V INT - DMA IEI RDY System Buses (Address. Data.ac.ir Microprocessors 1-97 .

r  Content of C is a port address  IN A. A  n is 8 bit port address  OUT (C). (n)  n is 8 bit port address  IN r (C)  Content of Reg C is a port address  Data is transfered to A  r is a data register  Content of A is data  Input data is hsabaghianb @ kashanu.irtransfered to r (data reg) Microprocessors 1-98 .Z80 Input Output  Z80 at most could have 256 input port and 256 output  8 bit port address is placed on A7–A0 pin to select the I/O device  OUT (n).ac.

ac.Remember IO read/write cycle hsabaghianb @ kashanu.ir Microprocessors 1-99 .

A D0 D1 D2 D3 D4 74LS373 D5 D6 D7 LE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE Z80 CPU hsabaghianb @ kashanu.ac.Z80 and simple output port A15 A14 : A0 D7 D6 D5 D4 D3 D2 D1 D0 OUT (03).ir WR IORQ IOWR AAAAAAAA 76543210 Microprocessors 1-100 .

ir RD IORQ IORD AAAAAAAA 76543210 Microprocessors 1-101 . (02) Y0 A0 Y1 A1 Y2 A2 Y3 A3 Y4 74LS244 A4 Y5 A5 Y6 A6 Y7 A7 G1 G2 5V Z80 CPU hsabaghianb @ kashanu.Z80 and simple input port A15 A14 : A0 D7 D6 D5 D4 D3 D2 D1 D0 IN A.ac.

ac.ir Microprocessors 1-102 .8088 and simple output port A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 74LS373 D5 D6 D7 LE IOR IOW Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE 8088 Minimum Mode AAAAAAAAAAAAAAAAIOW 1111119876543210 5 4 32 10 hsabaghianb @ kashanu.

8088 and simple input port A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 Y0 A0 Y1 A1 Y2 A2 Y3 A3 Y4 74LS244 A4 Y5 A5 Y6 A6 Y7 A7 G1 G2 IOR IOW 5V What is this? 8088 Minimum Mode AAAAAAAAAAAAAAAAIOW 1111119876543210 5 4 32 10 hsabaghianb @ kashanu.ac.ir Microprocessors 1-103 .

Simplified Drawing of 8088 Minimum Mode A7 .Q0 D7 .Q0 A15 .A16/ S3 74LS373 Q7 .ir Microprocessors 1-104 .D0 OE LE A7-A0 74LS373 Q7 .A0 DEN DT / R AD7 .B0 D7-D0 74LS245 Q7 .D4 D3 .ac.A8 D7 .D0 GND OE LE A15-A8 8088 A19/S6 .AD0 GND E DIR B7 .Q0 D7 .D0 GND OE LE A19-A16 ALE RD IO / M WR 74LS373 MEMR MEMW IOR IOW hsabaghianb @ kashanu.Q4 Q3 .

Minimum Mode 220 bytes or 1MB memory D7 .A0 Simplified Drawing of 8088 Minimum Mode MEMR MEMW RD 1 MB Memory WR CS hsabaghianb @ kashanu.D0 A19 .ac.ir Microprocessors 1-105 .D0 D7 .A0 A19 .

ir Microprocessors 1-106 .What are the memory locations of a 1MB (220 bytes) Memory? A19 to A0 (HEX) 00000 FFFFF AAAA 1111 9876 0000 1111 AAAA 1111 5432 0000 1111 AAAA 1198 10 0000 1111 AAAA 7654 0000 1111 AAAA 3210 0000 1111 Example: 34FD0 0011 0100 11111 1101 0000 hsabaghianb @ kashanu.ac.

D0 A19 D7 .ac.D0 What do we do with A19? Don’t connect it Connect to cs A18 .A0 1) Simplified 2) Drawing of 8088 Minimum What is the difference? Mode MEMR MEMW RD 512 kB Memory WR CS hsabaghianb @ kashanu.A0 A18 .ir Microprocessors 1-107 .Minimum Mode 512 kB memory D7 .

512 kB Memory Map  Don’t connect it  00000h 7FFFFh 80000h FFFFFh  A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”.the memory cannot “see” it. A19=0 is the same as A19=1 for Memory 512k Mem 512k Mem’  Connect to cs  00000h 7FFFFh 80000h FFFFFh If A19=0 Memory chip act normal fanction 512k Mem Empty hsabaghianb @ kashanu.ir Microprocessors 1-108 .ac.

2 × 512 kB memory D7 .A0 MEMR MEMW RD WR CS hsabaghianb @ kashanu.A0 MEMR D7 .ac.D0 512 kB RAM1 A18 .D0 A19 A18 .A0 RD WR MEMR MEMW MEMW CS D7 .D0 Simplified Drawing of 8088 Minimum Mode 512 kB RAM2 A18 .ir Microprocessors 1-109 .

2 × 512 kB memory What are the memory locations of two consecutive 512KB (219 bytes) Memory? AAAA 1111 9876 0000 0111 1000 1111 AAAA 1111 5432 0000 1111 0000 1111 AAAA 1198 10 0000 1111 0000 1111 AAAA 7654 0000 1111 0000 1111 AAAA 3210 0000 1111 0000 1111 Memory Chip 7FFFFh 00000h 512k RAM1 ROM RAM 80000h 512k RAM2 FFFFFh hsabaghianb @ kashanu.ac.ir Microprocessors 1-110 .

ir Microprocessors 1-111 .ac.Interfacing four 256K Memory Chips to the 8088 Microprocessor A19 A18 A17 : A17 : A0 D7 : D0 RD WR CS A17 : 256KB #4 A0 D7 : A0 D7 : D0 MEMR MEMW D0 RD WR CS A17 : 256KB #3 8088 Minimum Mode A0 D7 : D0 RD WR CS A17 : 256KB #2 A0 D7 : D0 RD WR CS 256KB #1 hsabaghianb @ kashanu.

ir Microprocessors 1-112 .Interfacing four 256K Memory Chips to the 8088 Microprocessor A19 A18 A17 : A17 : A0 D7 : D0 RD WR CS A17 : 256KB #4 A0 D7 : A0 D7 : D0 MEMR MEMW D0 RD WR CS A17 : 256KB #3 8088 Minimum Mode A0 D7 : D0 RD WR CS A17 : 256KB #2 A0 D7 : D0 RD WR CS 256KB #1 hsabaghianb @ kashanu.ac.

Memory chip#__ is mapped to: AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip RAM#1 RAM#2 RAM#3 RAM#4 hsabaghianb @ kashanu.ir Microprocessors 1-113 .ac.

A12 : Interfacing several 8K Memory Chips to the 8088 µ P A19 A18 A17 A16 A15 A14 A13 A12 : A0 D7 : D0 RD WR CS 8KB #? A0 D7 : 8088 Minimum Mode D0 MEMR MEMW : : A12 : A0 D7 : D0 RD WR CS A12 : 8KB #2 A0 D7 : D0 RD WR CS 8KB #1 hsabaghianb @ kashanu.ir Microprocessors 1-114 .ac.

ir Microprocessors 1-115 .ac.Interfacing 128 8K Memory Chips to the 8088 µ P 8088 Minimum Mode A12 : A19 A18 A17 A16 A15 A14 A13 A12 : A0 D7 : D0 RD WR CS 8KB #128 A0 D7 : D0 MEMR MEMW : : A12 : A0 D7 : D0 RD WR CS A12 : 8KB #2 A0 D7 : D0 RD WR CS 8KB #1 hsabaghianb @ kashanu.

ir Microprocessors 1-116 .A12 : Interfacing 128 8K Memory Chips to the 8088 µ P A19 A18 A17 A16 A15 A14 A13 A12 : A0 D7 : D0 RD WR CS 8KB #128 A0 D7 : 8088 Minimum Mode D0 MEMR MEMW : : A12 : A0 D7 : D0 RD WR CS A12 : 8KB #2 A0 D7 : D0 RD WR CS 8KB #1 hsabaghianb @ kashanu.ac.

Memory chip#__ is mapped to: AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 10 AAAA 7654 AAAA 3210 Memory Chip RAM#1 RAM#2 RAM#126 RAM#127 RAM#128 hsabaghianb @ kashanu.ir Microprocessors 1-117 .ac.

What is the Memory and Address Bit map? A12~A0 A12~A0 D7~D0 2764 EPROM 8k× 8 OE CE D7~D0 A14 A13 A12 C B A 7408 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A10~A0 RD 74138 MREQ A10~A0 D7~D0 6116 RWM 2k× 8 74244 input G1G 2 G2A G2B G1 A15 VCC RD WR CS RD WR hsabaghianb @ kashanu.ir Microprocessors 1-118 .ac.

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