A finite state machine (FSM) or simply a state machine, is a model of behavior composed of a finite number of states, transitions between

those states, and actions.It is like a "flow graph" where we can see how the logic runs when certain conditions are met. In this aricle I have implemented a Mealy type state machine in VHDL.The state machine bubble diagram in the below figure shows the operation of a four-state machine that reacts to a single input "input" as well as previous-state conditions.

The code is given below:

library ieee; use IEEE.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end mealy; architecture behavioral of mealy is type state_type is (s0,s1,s2,s3); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process.

process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then output <= '0'; next_s <= s1; else output <= '1'; next_s <= s2; end if; when s1 if(input output next_s else output next_s end if; =>; --when current state is "s1" ='0') then <= '0'; <= s3; <= '0'; <= s1;

when s2 => --when current state is "s2" if(input ='0') then output <= '1'; next_s <= s2; else output <= '0'; next_s <= s3; end if;

when s3 => if(input output next_s else output next_s end if; end case; end process;

--when current state is "s3" ='0') then <= '1'; <= s3; <= '1'; <= s0;

end behavioral;

Sign up to vote on this title
UsefulNot useful