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To Angelina and Jahan, for their love and patience

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**About the Author
**

Behzad Razavi received the BSEE degree from Sharif University of Technology in 1985 and the MSEE and PhDEE degrees from Stanford University in 1988 and 1992, respectively. He was with AT&T Bell Laboratories and Hewlett-Packard Laboratories until 1996. Since 1996, he has been Associate Professor and subsequently Professor of electrical engineering at University of California, Los Angeles. His current research includes wireless transceivers, frequency synthesizers, phase-locking and clock recovery for high-speed data communications, and data converters. Professor Razavi was an Adjunct Professor at Princeton University from 1992 to 1994, and at Stanford University in 1995. He served on the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC) from 1993 to 2002 and VLSI Circuits Symposium from 1998 to 2002. He has also served as Guest Editor and Associate Editor of the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems, and International Journal of High Speed Electronics. Professor Razavi received the Beatrice Winner Award for Editorial Excellence at the 1994 ISSCC, the best paper award at the 1994 European Solid-State Circuits Conference, the best panel award at the 1995 and 1997 ISSCC, the TRW Innovative Teaching Award in 1997, and the best paper award at the IEEE Custom Integrated Circuits Conference in 1998. He was the co-recipient of both the Jack Kilby Outstanding Student Paper Award and the Beatrice Winner Award for Editorial Excellence at the 2001 ISSCC. He was also recognized as one of the top 10 authors in the 50-year history of ISSCC. Professor Razavi is an IEEE Distinguished Lecturer, a Fellow of IEEE, and the author of Principles of Data Conversion System Design (IEEE Press, 1995), RF Microelectronics (Prentice Hall, 1998) (translated to Chinese), Design of Analog CMOS Integrated Circuits (McGraw-Hill, 2001) (translated to Chinese and Japanese), and Design of Integrated Circuits for Optical Communications (McGraw-Hill, 2003), and the editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits (IEEE Press, 1996), and Phase-Locking in High-Performance Systems (IEEE Press, 2003).

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Preface

With the advances in the semiconductor and communication industries, it has become increasingly important for electrical engineers to develop a good understanding of microelectronics. This book addresses the need for a text that teaches microelectronics from a modern and intuitive perspective. Guided by my industrial, research, and academic experience, I have chosen the topics, the order, and the depth and breadth so as to efﬁciently impart analysis and design principles that the students will ﬁnd useful as they enter the industry or graduate school. One salient feature of this book is its synthesis- or design-oriented approach. Rather than pulling a circuit out of a bag and trying to analyze it, I set the stage by stating a problem that we face in real life (e.g., how to design a cellphone charger). I then attempt to arrive at a solution using basic principles, thus presenting both failures and successes in the process. When we do arrive at the ﬁnal solution, the student has seen the exact role of each device as well as the logical thought sequence behind synthesizing the circuit. Another essential component of this book is “analysis by inspection.” This “mentality” is created in two steps. First, the behavior of elementary building blocks is formulated using a “verbal” description of each analytical result (e.g., “looking into the emitter, we see 1=g m .”). Second, larger circuits are decomposed and “mapped” to the elementary blocks to avoid the need for writing KVLs and KCLs. This approach both imparts a great deal of intuition and simpliﬁes the analysis of large circuits. The two articles following this preface provide helpful suggestions for students and instructors. I hope these suggestions make the task of learning or teaching microelectronics more enjoyable. This “preview edition” is introduced as a test vehicle so as to collect feedback from students and instructors and polish the book for the ﬁrst edition. A set of Powerpoint slides and a solutions manual are available for instructors. Behzad Razavi April 2006

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Acknowledgments

This book has taken three years to write and beneﬁted from contributions of many individuals. I wish to thank the following for their input at various stages of this book’s development: David Allstot (University of Washington), Joel Berlinghieri, Sr. (The Citadel), Bernhard Boser (University of California, Berkeley), Charles Bray (University of Memphis), Marc Cahay (University of Cincinnati), Norman Cox (University of Missouri, Rolla), Tranjan Farid (University of North Carolina at Charlotte), Paul Furth (New Mexico State University), Roman Genov (University of Toronto), Maysam Ghovanloo (North Carolina State University), Gennady Gildenblat (Pennsylvania State University), Ashok Goel (Michigan Technological University), Michael Gouzman (SUNY, Stony Brook), Michael Green (University of California, Irvine), Sotoudeh Hamedi-Hagh (San Jose State University), Reid Harrison (University of Utah), Payam Heidari (University of California, Irvine), Feng Hua (Clarkson University), Marian Kazmierchuk (Wright State University), Roger King (University of Toledo), Edward Kolesar (Texas Christian University), Ying-Cheng Lai (Arizona State University), Daniel Lau (University of Kentucky, Lexington), Stanislaw Legowski (University of Wyoming), Philip Lopresti (University of Pennsylvania), Mani Mina (Iowa State University), James Morris (Portland State University), Khalil Najaﬁ (University of Michigan), Homer Nazeran (University of Texas, El Paso), Tamara Papalias (San Jose State University), Matthew Radmanesh (California State University, Northridge), Angela Rasmussen (University of Utah), Sal R. Riggio, Jr. (Pennsylvania State University), Ali Sheikholeslami (University of Toronto), Yannis Tsividis (Columbia University), Thomas Wu (University of Central Florida), Darrin Young (Case Western Reserve University). I am grateful to Naresh Shanbhag (University of Illinois, Urbana-Champaign) for test driving a draft of the book in a course and providing valuable feedback. I also thank my publishers, Catherine Schultz and Bill Zobrist, for their dedication and exuberance. My wife, Angelina, typed the entire book and kept her humor as this project dragged on. My deepest thanks go to her. Behzad Razavi April 2006

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**Suggestions for Students
**

You are about to embark upon a journey through the fascinating world of microelectronics. Fortunately, microelectronics appears in so many facets of our lives that we can readily gather enough motivation to study it. The reading, however, is not as easy as that of a story book; we must deal with analysis and design, applying mathematical rigor as well as engineering intuition every step of the way. This article provides some suggestions that students may ﬁnd helpful in studying microelectronics. Rigor and Intuition Before reading this book, you have taken one or two courses on basic circuit theory, mastering Kirchoff’s Laws and the analysis of RLC circuits. While quite abstract and bearing no apparent connection with real life, the concepts studied in these courses form the foundation for microelectronics—just as calculus does for engineering. Our treatment of microelectronics also requires rigor but entails two additional components. First, we identify many applications for the concepts that we study. Second, we must develop intuition, i.e., a “feel” for the operation of microelectronic devices and circuits. Without an intuitive understanding, the analysis of circuits becomes increasingly more difﬁcult as we add more devices to perform more complex functions. Analysis by Inspection We will expend a considerable effort toward establishing the mentality and the skills necessary for “analysis by inspection.” That is, looking at a complex circuit, we wish to decompose or “map” it to simpler topologies, thus formulating the behavior with a few lines of algebra. As a simple example, suppose we have encountered the resistive divider shown in Fig. (a) and derived its Thevenin equivalent. Now, if given the circuit in Fig. (b), we can

R1 V in (a) R2 Vout V in R1 C1 (b) R2 L1 Vout

readily replace Vin , R1 , and R2 with a Thevenin equivalent, thereby simplifying the calculations. 40 Pages per Week While taking courses on microelectronics, you will need to read about 40 pages of this book every week, with each page containing many new concepts, derivations, and examples. The lectures given by the instructor create a “skeleton” of each chapter, but it rests upon you to “connect the dots” by reading the book carefully and understanding each paragraph before proceeding to the next. Reading and understanding 40 pages of the book each week requires concentration and discipline. You will face new material and detailed derivations on each page and should set aside two- or three-hour distraction-free blocks of time (no phone calls, TV, email, etc.) so that you

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can follow the evolution of the concepts while honing your analytical skills. I also suggest that you attempt each example before reading its solution. 40 Problems per Week After reading each section and going through its examples, you are encouraged to evaluate and improve your understanding by trying the corresponding endof-chapter problems. The problems begin at a relatively easy level and gradually become more challenging. Some problems may require that you return to the section and study the subtle points more carefully. The educational value provided by each problem depends on your persistence. The initial glance at the problem may be discouraging. But, as you think about it from different angles and, more importantly, re-examine the concepts in the chapter, you begin to form a path in your mind that may lead to the solution. In fact, if you have thought about a problem extensively and still have not solved it, you need but a brief hint from the instructor or the teaching assistant. Also, the more you struggle with a problem, the more appealing and memorable the answer will be. Attending the lecture and reading the book are examples of “passive learning:” you simply receive (and, hopefully, absorb) a stream of information provided by the instructor and the text. While necessary, passive learning does not exercise your understanding, thus lacking depth. You may highlight many lines of the text as important. You may even summarize the important concepts on a separate sheet of paper (and you are encouraged to do so). But, to master the material, you need practice (“active learning”). The problem sets at the end of each chapter serve this purpose. Homeworks and Exams Solving the problems at the end of each chapter also prepares you for homeworks and exams. Homeworks, too, demand distraction-free periods during which you put your knowledge to work and polish your understanding. An important piece of advice that I can offer here is that doing homeworks with your fellow students is a bad idea! Unlike other subject matters that beneﬁt from discussions, arguments, and rebuttals, learning microelectronics requires quiet concentration. (After all, you will be on your own during the exam!) To gain more conﬁdence in your answers, you can discuss the results with your fellow students, the instructor, or the teaching assistants after you have completed the homework by yourself. Time Management Reading the text, going through the problem sets, and doing the homeworks require a time commitment of at least 10 hours per week. Due to the fast pace of the course, the material accumulates rapidly, making it difﬁcult to keep up with the lectures if you do not spend the required time from the very ﬁrst week. In fact, the more you fall behind, the less interesting and useful the lectures become, thus forcing you to simply write down everything that the instructor says while not understanding much. With your other courses demanding similar time commitments, you can soon become overwhelmed if you do not manage your time carefully. Time management consists of two steps: (1) partitioning your waking hours into solid blocks, and (2) using each block efﬁciently. To improve the efﬁciency, you can take the following measures: (a) work in a quiet environment to minimize distractions; (b) spread the work on a given subject over the week, e.g., 3 hours every other day, to avoid saturation and to allow your subconscious to process the concepts in the meantime. Prerequisites Many of the concepts that you have learned in the circuit theory courses prove essential to the study of microelectronics. Chapter 1 gives a brief overview to refresh your memory. With the limited lecture time, the instructor may not cover this material in the class, leaving it for you to read at home. You can ﬁrst glance through the chapter and see which concepts “bother” you before sitting down to concentrate.

**Suggestions for Instructors
**

Teaching undergraduate courses proves quite challenging—especially if the emphasis is on thinking and deduction rather than on memorization. With today’s young minds used to playing fast-paced video games and “clicking” on the Internet toward their destination, it has become increasingly more difﬁcult to encourage them to concentrate for long periods of time and deal with abstract concepts. Based on one decade of teaching, this article provides suggestions that instructors of microelectronics may ﬁnd helpful. Therapy The students taking the ﬁrst microelectronics course have typically completed one or two courses on basic circuit theory. To many, that experience has not been particularly memorable. After all, the circuit theory textbook is most likely written by a person not in the ﬁeld of circuits. Similarly, the courses are most likely taught by an instructor having little involvement in circuit design. For example, the students are rarely told that node analysis is much more frequently used in hand calculations than mesh analysis is. Or, they are given little intuition with respect to Thevenin and Norton theorems. With the foregoing issues in mind, I begin the ﬁrst course with a ﬁve-minute “therapy session.” I ask how many came out of the circuit theory courses with a “practical” understanding. Very few raise their hands. I then ask, “But how about your calculus courses? How many of you came out of these courses with a “practical” understanding?” Subsequently, I explain that circuit theory builds the foundation for microelectronics just as calculus does for engineering. I further point out that some abstractness should also be expected in microelectronics as we complete the foundation for more advanced topics in circuit analysis and design. I then point out that (1) microelectronics is very heavily based on intuitive understanding, requiring that we go beyond simply writing KVLs and KCLs and interpret the mathematical expressions intuitively, and (2) this course offers many applications of microelectronic devices and circuits in our daily lives. In other words, microelectronics is not as dry as arbitrary RLC circuits consisting of 1- resistors, 1-H inductors, and 1-F capacitors. First Quiz Since different students enter each course with different levels of preparation, I have found it useful to give a 10-minute quiz in the very ﬁrst lecture. Pointing out that the quiz does not count towards their grade but serves as a gauge of their understanding, I emphasize that the objective is to test their knowledge rather than their intelligence. After collecting the quizzes, I ask one of the teaching assistants to assign a binary grade to each: those who would receive less than 50% are marked with a red star. At the end of the lecture, I return the quizzes and mention that those with a red star need to work harder and interact with the teaching assistants and myself more extensively. The Big Picture A powerful motivational tool in teaching is the “big picture,” i.e., the “practical” application of the concept under study. The two examples of microelectronic systems described in Chapter 1 serve as the ﬁrst step toward creating the context for the material covered

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in the book. But, the big picture cannot stop here. Each new concept may merit an application— however brief the mention of the application may be—and most of this burden falls on the lecture rather than on the book. The choice of the application must be carefully considered. If the description is too long or the result too abstract, the students miss the connection between the concept and the application. My general approach is as follows. Suppose we are to begin Chapter 2 (Basic Semiconductor Physics). I ask either “What would our world look like without semiconductors?” or “Is there a semiconductor device in your watch? In your cellphone? In your laptop? In your digital camera?” In the ensuing discussion, I quickly go over examples of semiconductor devices and where they are used. Following the big picture, I provide additional motivation by asking, ”Well, but isn’t this stuff old? Why do we need to learn these things?” I then brieﬂy talk about the challenges in today’s designs and the competition among manufacturers to lower both the power consumption and the cost of portable devices. Analysis versus Synthesis Let us consider the background of the students entering a microelectronics course. They can write KVLs and KCLs efﬁciently. They have also seen numerous “random” RLC circuits; i.e., to these students, all RLC circuits look the same, and it is unclear how they came about. On the other hand, an essential objective in teaching microelectronics is to develop speciﬁc circuit topologies that provide certain characteristics. We must therefore change the students’ mentality from “Here’s a circuit that you may never see again in your life. Analyze it!” to “We face the following problem and we must create (synthesize) a circuit that solves the problem.” We can then begin with the simplest topology, identify its shortcomings, and continue to modify it until we arrive at an acceptable solution. This step-by-step synthesis approach (a) illustrates the role of each device in the circuit, (b) establishes a “design-oriented” mentality, and (c) engages the students’ intellect and interest. Analysis by Inspection In their journey through microelectronics, students face increasingly more complex circuits, eventually reaching a point where blindly writing KVLs and KCLs becomes extremely inefﬁcient and even prohibitive. In one of my ﬁrst few lectures, I show the internal circuit of a complex op amp and ask, “Can we analyze the behavior of this circuit by simply writing node or mesh equations?” It is therefore important to instill in them the concept of “analysis by inspection.” My approach consists of two steps. (1) For each simple circuit, formulate the properties in an intuitive language; e.g., “the voltage gain of a common-source stage is given by the load resistance divided by 1=g m plus the resistance tied from the source to ground.” (2) Map complex circuits to one or more topologies studied in step (1). In addition to efﬁciency, analysis by inspection also provides great intuition. As we cover various examples, I emphasize to the students that the results thus obtained reveal the circuit’s dependencies much more clearly than if we simply write KVLs and KCLs without mapping. “What If?” Adventures An interesting method of reinforcing a circuit’s properties is to ask a question like, “What if we tie this device between nodes C and D rather than between nodes A and B ?” In fact, students themselves often raise similar questions. My answer to them is “Don’t be afraid! The circuit doesn’t bite if you change it like this. So go ahead and analyze it in its new form.” For simple circuits, the students can be encouraged to consider several possible modiﬁcations and determine the resulting behavior. Consequently, the students feel much more comfortable with the original topology and understand why it is the only acceptable solution (if that is the case). Numeric versus Symbolic Calculations In the design of examples, homeworks, and exams, the instructor must decide between numeric and symbolic calculations. The students may,

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of course, prefer the former type as it simply requires ﬁnding the corresponding equation and plugging in the numbers. What is the value in numeric calculations? In my opinion, they may serve one of two purposes: (1) make the students comfortable with the results recently obtained, or (2) give the students a feel for the typical values encountered in practice. As such, numeric calculations play a limited role in teaching and reinforcing concepts. Symbolic calculations, on the other hand, can offer insight into the behavior of the circuit by revealing dependencies, trends, and limits. Also, the results thus obtained can be utilized in more complex examples. Blackboard versus Powerpoint This book comes with a complete set of Powerpoint slides. However, I suggest that the instructors carefully consider the pros and cons of blackboard and Powerpoint presentations. I can offer the following observations. (1) Many students fall asleep (at least mentally) in the classroom if they are not writing. (2) Many others feel they are missing something if they are not writing. (3) For most people, the act of writing something on paper helps “carve” it in their mind. (4) The use of slides leads to a fast pace (“if we are not writing, we should move on!”), leaving little time for the students to digest the concepts. For these reasons, even if the students have a hardcopy of the slides, this type of presentation proves quite ineffective. To improve the situation, one can leave blank spaces in each slide and ﬁll them with critical and interesting results in real time. I have tried this method using transparencies and, more recently, tablet laptops. The approach works well for graduate courses but leaves undergraduate students bored or bewildered. My conclusion is that the good old blackboard is still the best medium for teaching undergraduate microelectronics. The instructor may nonetheless utilize a hardcopy of the Powerpoint slides as his/her own guide for the ﬂow of the lecture. Discrete versus Integrated How much emphasis should a microelectronics course place on discrete circuits and integrated circuits? To most of us, the term “microelectronics” remains synonymous with “integrated circuits,” and, in fact, some university curricula have gradually reduced the discrete design ﬂavor of the course to nearly zero. However, only a small fraction of the students taking such courses eventually become active in IC products, while many go into board-level design. My approach in this book is to begin with general concepts that apply to both paradigms and gradually concentrate on integrated circuits. I also believe that even board-level designers must have a basic understanding of the integrated circuits that they use. Bipolar Transistor versus MOSFET At present, some controversy surrounds the inclusion of bipolar transistors and circuits in undergraduate microelectronics. With the MOSFET dominating the semiconductor market, it appears that bipolar devices are of little value. While this view may apply to graduate courses to some extent, it should be borne in mind that (1) as mentioned above, many undergraduate students go into board-level and discrete design and are likely to encounter bipolar devices, and (2) the contrasts and similarities between bipolar and MOS devices prove extremely useful in understanding the properties of each. The order in which the two species are presented is also debatable. (Extensive surveys conducted by Wiley indicate a 50-50 split between instructors on this matter.) Some instructors begin with MOS devices to ensure enough time is spent on their coverage. On the other hand, the natural ﬂow of the course calls for bipolar devices as an extension of pn junctions. In fact, if diodes are immediately followed by MOS devices, the students see little relevance between the two. (The pn junctions in MOSFETs do not come into the picture until the device capacitances are introduced.)

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My approach in this book is to ﬁrst cover bipolar devices and circuits while building the foundation such that the MOS counterparts are subsequently taught with greater ease. As explained below, the material can comfortably be taught even in one quarter with no sacriﬁce of details of either device type. Course Syllabi This book can be used in a two-quarter or two-semester sequence. Depending on the instructor’s preference, the courses can follow various combinations of the chapters. Figure 0.1 illustrates some possibilities. I have followed Syllabus I for the quarter system at UCLA for a number of years. 1 Syllabus II sacriﬁces op amp circuits for an introductory treatment of digital CMOS circuits. In a semester system, Syllabus I extends the ﬁrst course to current mirrors and cascode stages and the second course to output stages and analog ﬁlters. Syllabus II, on the other hand, includes digital circuits in the ﬁrst course, moving current mirrors and cascodes to the second course and sacriﬁcing the chapter on output stages. Figure 0.2 shows the approximate length of time spent on the chapters as practiced at UCLA. In a semester system, the allotted times are more ﬂexible. Coverage of Chapters The material in each chapter can be decomposed into three categories: (1) essential concepts that the instructor should cover in the lecture, (2) essential skills that the students must develop but cannot be covered in the lecture due to the limited time, and (3) topics that prove useful but may be skipped according to the instructor’s preference. 2 Summarized below are overviews of the chapters showing which topics should be covered in the classroom. Chapter 1: Introduction to Microelectronics The objective of this chapter is to provide the “big picture” and make the students comfortable with analog and digital signals. I spend about 30 to 45 minutes on Sections 1.1 and 1.2 , leaving the remainder of the chapter (Basic Concepts) for the teaching assistants to cover in a special evening session in the ﬁrst week. Chapter 2: Basic Semiconductor Physics Providing the basics of semiconductor device physics, this chapter deliberately proceeds at a slow pace, examining concepts from different angles and allowing the students to digest the material as they read on. A terse language would shorten the chapter but require that the students reread the material multiple times in their attempt to decipher the prose. It is important to note, however, that the instructor’s pace in the classroom need not be as slow as that of the chapter. The students are expected to read the details and the examples on their own so as to strengthen their grasp of the material. The principal point in this chapter is that we must study the physics of devices so as to construct circuit models for them. In a quarter system, I cover the following concepts in the lecture: electrons and holes; doping; drift and diffusion; pn junction in equilibrium and under forward and reverse bias. Chapter 3: Diode Models and Circuits This chapter serves four purposes: (1) make the students comfortable with the pn junction as a nonlinear device; (2) introduce the concept of linearizing a nonlinear model to simplify the analysis; (3) cover basic circuits with which any electrical engineer must be familiar, e.g., rectiﬁers and limiters; and (4) develop the skills necessary to analyze heavily-nonlinear circuits, e.g., where it is difﬁcult to predict which diode turns on at what input voltage. Of these, the ﬁrst three are essential and should be covered in the lecture, whereas the last depends on the instructor’s preference. (I cover it in my lectures.) In the

1 We offer a separate undergraduate course on digital circuit design, which the students can take only after our ﬁrst

microelectronics course. 2 Such topics are identiﬁed in the book by a footnote.

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Quarter System, Syllabus I First Quarter: Introduction to Microelectronics (Chapter 1) MOS Devices (Chapter 6) Physics of Semiconductors (Chapter 2) MOS Circuits (Chapter 7) Diode Models and Circuits (Chapter 3) Op Amp as Black Box (Chapter 8) Differential Pairs (Chapter 10) Frequency Response (Chapter 11) Feedback and Stability (Chapter 12) Bipolar Transistors (Chapter 4) Bipolar Circuits (Chapter 5)

Second Quarter: Current Mirrors and Cascodes (Chapter 9)

Quarter System, Syllabus II First Quarter: Introduction to Microelectronics (Chapter 1) MOS Devices (Chapter 6) Physics of Semiconductors (Chapter 2) MOS Circuits (Chapter 7) Diode Models and Circuits (Chapter 3) Bipolar Transistors (Chapter 4) Bipolar Circuits (Chapter 5)

Digital CMOS Circuits (Chapter 15) Differential Pairs (Chapter 10) Frequency Response (Chapter 11) Feedback and Stability (Chapter 12)

Second Quarter: Current Mirrors and Cascodes (Chapter 9)

Semester System, Syllabus I First Semester: Introduction to Microelectronics (Chapter 1) MOS Devices (Chapter 6) Second Semester: Differential Pairs (Chapter 10) Physics of Semiconductors (Chapter 2) MOS Circuits (Chapter 7) Frequency Response (Chapter 11) Diode Models and Circuits (Chapter 3) Op Amp as Black Box (Chapter 8) Bipolar Transistors (Chapter 4) Bipolar Circuits (Chapter 5)

Current Mirrors and Cascodes (Chapter 9) Output Stages (Chapter 13) Analog Filters (Chapter 14)

Feedback and Stability (Chapter 12)

Semester System, Syllabus II First Semester: Introduction to Microelectronics (Chapter 1) MOS Devices (Chapter 6) Second Semester: Current Mirrors and Cascodes (Chapter 9) Physics of Semiconductors (Chapter 2) MOS Circuits (Chapter 7) Differential Pairs (Chapter 10) Diode Models and Circuits (Chapter 3) Op Amp as Black Box (Chapter 8) Frequency Response (Chapter 11) Bipolar Transistors (Chapter 4) Bipolar Circuits (Chapter 5)

Digital CMOS Circuits (Chapter 15) Feedback and Stability (Chapter 12) Analog Filters (Chapter 14)

Figure 0.1 Different course structures for quarter and semester systems.

interest of time, I skip a number of sections in a quarter system, e.g., voltage doublers and level shifters. Chapter 4: Physics of Bipolar Transistors Beginning with the use of a voltagecontrolled current source in an ampliﬁer, this chapter introduces the bipolar transistor as an extension of pn junctions and derives its small-signal model. As with Chapter 2, the pace is rela-

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Quarter System, Syllabus I First Quarter: 1.5 Weeks Introduction to Microelectronics (Chapter 1) 1 Week MOS Devices (Chapter 6) Second Quarter: 2 Weeks Current Mirrors and Cascodes (Chapter 9) 3 Weeks Differential Pairs (Chapter 10) 2 Weeks Frequency Response (Chapter 11) 3 Weeks Feedback and Stability (Chapter 12) Physics of Semiconductors (Chapter 2) 2 Weeks MOS Circuits (Chapter 7) 1.5 Weeks Diode Models and Circuits (Chapter 3) 1 Week Op Amp as Black Box (Chapter 8) 1 Week Bipolar Transistors (Chapter 4) 2 Weeks Bipolar Circuits (Chapter 5)

Figure 0.2 Timetable for the two courses.

tively slow, but the lectures need not be. I cover structure and operation of the bipolar transistor, a very simpliﬁed derivation of the exponential characteristic, and transistor models, mentioning only brieﬂy that saturation is undesirable. Since the T-model of limited use in analysis and carries little intuition (especially for MOS devices), I have excluded it in this book. Chapter 5: Bipolar Circuits This is the longest chapter in the book, building the foundation necessary for all subsequent work in electronics. Following a bottom-up approach, this chapter establishes critical concepts such as input and output impedances, biasing, and small-signal analysis. While writing the book, I contemplated decomposing Chapter 5 into two chapters, one on the above concepts and another on bipolar ampliﬁer topologies, so that the latter could be skipped by instructors who prefer to continue with MOS circuits instead. However, teaching the general concepts does require the use of transistors, making such a decomposition difﬁcult. Chapter 5 proceeds slowly, reinforcing, step-by-step, the concept of synthesis and exploring circuit topologies with the aid of “What if?” examples. As with Chapters 2 and 4, the instructor can move at a faster pace and leave much of the text for the students to read on their own. In a quarter system, I cover all of the chapter, frequently emphasizing the concepts illustrated in Figure 5.7 (the impedance seen looking into the base, emitter, or collector). With about two (perhaps two and half) weeks allotted to this chapter, the lectures must be precisely designed to ensure the main concepts are imparted in the classroom. Chapter 6: Physics of MOS Devices This chapter parallels Chapter 4, introducing the MOSFET as a voltage-controlled current source and deriving its characteristics. Given the limited time that we generally face in covering topics, I have included only a brief discussion of the body effect and velocity saturation and neglected these phenomena for the remainder of the book. I cover all of this chapter in our ﬁrst course. Chapter 7: MOS Circuits Drawing extensively upon the foundation established in Chapter 5, this chapter deals with MOS ampliﬁers but at a faster pace. I cover all of this chapter in our ﬁrst course. Chapter 8: Operational Ampliﬁer as a Black Box Dealing with op-amp-based circuits, this chapter is written such that it can be taught in almost any order with respect to other chapters. My own preference is to cover this chapter after ampliﬁer topologies have been studied, so that the students have some bare understanding of the internal circuitry of op amps and its gain limitations. Teaching this chapter near the end of the ﬁrst course also places op amps closer

each chapter offers a relatively large problem set at the end. I have made great effort to create a step-by-step procedure for analyzing feedback circuits. For this reason. so I explain that the differential pair is a versatile circuit and is utilized in both regimes. this chapter proceeds at a deliberately slow pace. Chapter 10: Differential Ampliﬁers This chapter deals with large-signal and small-signal behavior of differential ampliﬁers. allowing the students to become comfortable with each concept and appreciate the points taught by each example. The study of cascodes and current mirrors here also provides the necessary background for constructing differential pairs with active loads or cascodes in Chapter 10. I have excluded TTL and ECL circuits here. As with Chapters 2 and 5. Chapter 9: Cascodes and Current Mirrors This chapter serves as an important step toward integrated circuit design. especially where input and output loading effects must be taken into account. I cover all of this chapter in our second course. Problem Sets In addition to numerous examples. This chapter can be comfortably covered in a semester system. . Given the time constraints in quarter and semester systems. Chapter 14: Analog Filters This chapter provides a basic understanding of passive and active ﬁlters. Chapter 11: Frequency Response Beginning with a review of basic concepts such as Bode’s rules. I cover all of this chapter in our second course. I cover all of this chapter in our second course. I begin with simple. I cover all of this chapter in our ﬁrst course. I cover all of the topics in this chapter in approximately two weeks. Due to the limited lecture time. I ask the teaching assistants to cover SPICE in a special evening session around the middle of the quarter—just before I begin to assign SPICE problems. Except for the device physics chapters. but it is in the ﬁrst microelectronics course that the students can appreciate the importance of simulation tools. conﬁdencebuilding problems and gradually raise the level of difﬁculty. Chapter 15: Digital CMOS Circuits This chapter is written for microelectronics courses that include an introduction to digital circuits as a preparation for subsequent courses on the subject. The students may wonder why we did not study the largesignal behavior of various ampliﬁers in Chapters 5 and 7. In our second microelectronics course. For each concept covered in the chapter. this chapter introduces the high-frequency model of transistors and analyzes the frequency response of basic ampliﬁers. This chapter can also be comfortably covered in a semester system. Chapter 13: Output Stages and Power Ampliﬁers This chapter studies circuits that deliver higher power levels than those considered in previous chapters. thus allowing the students to appreciate the relevance of each. Appendix A of this book introduces SPICE and teaches circuit simulation with the aid of numerous examples. Topologies such as pushpull stages and their limitations are analyzed. SPICE Some basic circuit theory courses may provide exposure to SPICE. The objective is to master only a subset of SPICE commands that allow simulation of most circuits at this level. Chapter 12: Feedback and Stability Most instructors agree that the students ﬁnd feedback to be the most difﬁcult topic in undergraduate microelectronics. all chapters also provide a set of design problems that encourage students to work “in reverse” and select the bias and/or component values to satisfy certain requirements. From this chapter on. preparing the student for more advanced texts on the subject.xxi to differential ampliﬁers (Chapter 10). bipolar and MOS circuits are covered together and various similarities and contrasts between them are pointed out.

the homeworks contain moderate to difﬁcult problems. I tell them that one of the problems in the book is given in the exam verbatim.. The exams are open-book. 5-10). Mostly based on the problem sets in the book. Homeworks and Exams In a quarter system.e. I assign four homeworks before the midterm and four after..xxii Most chapters contain SPICE problems. To encourage the students to solve all of the problems at the end of each chapter. This is for two reasons: (1) the students must ﬁrst develop their basic understanding and analytical skills. but I prefer to introduce SPICE only in the second half of the ﬁrst course (toward the end of Chapter 5). the homeworks must exercise the fundamental concepts. i. . The exam questions are typically “twisted” version of the problems in the book. but I suggest to the students to summarize the important equations on one sheet of paper. thereby requiring that the students ﬁrst go over the easier problems in the book on their own. and (2) the students appreciate the utility of SPICE much better if the circuit contains a relatively large number of devices (e.g.

. . . . . . 1. . . . . . . . . . . . . . . . . . . .1 Half-Wave and Full-Wave Rectiﬁers . . 3. . . . .2 PN Junction . . . . . . . . . . .5. . . . . .3. . . . . . 2. 2. .3 Digital Circuits . . . . . . . . . . . . . 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. . . . . . .1 Initial Thoughts .3. . . . . . . . . 1. . . . . .3 Limiting Circuits . . . . . . . . . . . . 6 . . . . . 2 . . . . . . 2.4 Basic Circuit Theorems . . .3 Reverse Breakdown .2 Digital Camera . . . . . . . . . . . . . . .1. . . . . . . . . . . 2. . . . . . . . . . . . . . .2 PN Junction as a Diode . . . . . . . . . . . . . . .1.3. .4 I/V Characteristics . . . . . 3 Diode Models and Circuits 3. .5. . . . . . . . . . . . . . . . . . . . . . . . . . 3.2. .3. . . . . .1 Electronics versus Microelectronics 1. . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . 7 . . . . .5. .1. . . . . . . . . . . 3. . . . . . . . . . . . . 3. .1 Analog and Digital Signals . . . . . . . . . . . . . 1. . 3.1 Ideal Diode . . . . . . . . . . . .3 Transport of Carriers . . . . . . . .4 Voltage Doublers . . . . . . .2 Avalanche Breakdown . . . . 3. . . . . . . . . . . . . . . . 2. . . . . . . . . . . . . . . 3. . . . . . . . . . . . . . . . . . . . 1 . . . . . . . . . . . . . . . . . . . . . . .2. .Contents 1 Introduction to Microelectronics 1. . . . . 4 . 2. . . . . . . .3 Additional Examples . . . . . . . . . . . . .2 Ideal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . 11 19 19 20 22 25 32 33 38 42 45 49 49 50 56 56 56 57 62 65 67 73 81 82 93 96 98 103 116 xxiii 2 Basic Physics of Semiconductors 2. . . . 7 . . . . . . . . . . . . . . . . . . 2. . . . . . . . . . . . . . . 3. . . . . . . . . . . . .2. . . . . . .2. . . . . . . . . . . . . . . . . . . .3 PN Junction Under Forward Bias . .1 PN Junction in Equilibrium . . . . . . . . . . . . . . . . . .2 Analog Circuits . . . . . . . . . . . . . . . . . . . . . . .1 Cellular Telephone . . . . 2 . . . . . . . . . . . . . . . . . . . . . . .5 Diodes as Level Shifters and Switches 4 Physics of Bipolar Transistors . . . . 9 . . .1 Charge Carriers in Solids . . . . . . . . . . . .3. . . . . . . . 3. . . . . . . . . . . 1 . . . . .4 Large-Signal and Small-Signal Operation . . . . . . . . .2 Examples of Electronic Systems . . . . . . 3. . . . . . . . . . . . . . . . . . . .3 Analog versus Digital .5 Applications of Diodes . . . .3. .2 PN Junction Under Reverse Bias . . . .5. . . . . .2. . . . . . . . . .2 Modiﬁcation of Carrier Densities . . . . 2. . 1. . .2. . . 1. . . . . . . . . . . .2 Voltage Regulation . . . . . . . . . . . . . . . . . . . . . .3 Basic Concepts . . . . . . . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . . . . . . 2. . . . . . . . . . . . 2. . . . . . . . . . . . . .5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. . . . . . . . . . . . . . . . . .1 Semiconductor Materials and Their Properties 2. . . . . . .1. . . . . . . . . . . . .1. . . . . . 3. . . . .1. . . . . . .1 Zener Breakdown . . . . . . . . .3 Application Examples .

. . . . . . . .2 Biasing . . . . . . .6 Comparison of Bipolar and MOS Devices 7 CMOS Ampliﬁers . . . .1 Input and Output Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. . . 5. . . 5. . . . . 4. . . . . .5 Early Effect . . . . . . . . .3. . . . . Bipolar Transistor Models and Characteristics . .1 Structure of MOSFET . . . . . . . .3 DC and Small-Signal Analysis . . . . . . . . . . . Operation of Bipolar Transistor in Saturation Mode The PNP Transistor . .2. . . . . . .3. . . . . . . . .4. . . . . . . . . . . . . .6. . . . . . . . . . . . 4. . . . . . 5. . . . . . . . . . . . . . . . .4. . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. . . . . . . . . . . . . . . .1 General Considerations . . . . . . . .4. . . . 6. . . . . . . . . . . . . . . . . . . . . . .3. .3 Biasing with Emitter Degeneration . . . 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . .4 4. . 4. . . . . . . . . . . . . . . . 4. . . . . . . . . . . . . . . . . . . . . . .2 4. 5. . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Derivation of I/V Characteristics . . . . . . . . 6. . . . . . . . . . . . . . .4 Self-Biased Stage . . . . . . . . . .4 PMOS Transistor . . . . . . . . . . . . . . .2 Small-Signal Model . . . . . . . . . . . . . 6. . . .2 I/V Characteristics .6. . .5 4. . . . Structure of Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Emitter Follower . . . . 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. . . .3 4. .3 MOS Device Models . . . . . . . . . . . . . 4. . . . .2 Large-Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Velocity Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Common-Emitter Topology . . .2 Operation of MOSFET . . . . . .4. . . . . . . . . . . . . . .2. . . . .2.3 Small-Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Operating Point Analysis and Design .3 Channel-Length Modulation . . . . .1 Large-Signal Model . . . . . . . . . . . . . . .2 Common-Base Topology . . . . . . . . . . . . . .1 Structure and Operation . . . . . .4 MOS Transconductance . . . 4. . . . . . . . .2. . . 5. 5. .6 Other Second-Order Effects . 6. .xxiv 4. . . . .2. . . . . .3. . . . . . . .2. . . . .4 Summary and Additional Examples . .2. 6. . . .1. . . . . . . . . . . . . . . . . . . 5. . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . .5 Biasing of PNP Transistors . . . . . . . . . . . . . . Operation of Bipolar Transistor in Active Mode . . . . . . . . . . . . . . . 5. . . . . . . . . . . . . . . 4. 5. . . . . . . . . . 4. . . . . . . . . . . . . .2 Base and Emitter Currents . . . . . . . . . . . . . . . . 4. . .2. . . . . . . .2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. . . . 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 CMOS Technology . . . . .3. . . . . . .6. . . . . . . . . . . . . . .1 Qualitative Analysis . . .4 Small-Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Bipolar Ampliﬁer Topologies . . .2 Resistive Divider Biasing . . . . . . . . . . . . . . . . . . 116 118 119 121 125 127 127 129 131 133 137 142 145 145 146 149 165 165 166 170 170 172 173 175 179 182 185 189 189 215 230 238 266 266 268 269 274 283 284 286 286 287 288 289 290 292 293 304 5 Bipolar Ampliﬁers 5. . 6. . . . . . . . 6 Physics of MOS Transistors 6. . . 5. . . . . . .3 Concept of Transconductance . . . . . . . . . . . . . . . . . . 6. . . . . . . . . . . . . . . . . . . .1 Large-Signal Model . .1 4. . . . . . . .2. . . . . . . .6 General Considerations . .1 Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. . . .2. . . . . . 6. . . . . . . . . . . . . . . . . . .1. . . . . . . .1 Simple Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. 5. . . . . . . 6. .

. .4. . . . . . . . . . 7. . . . . . .1. . . . . . . .3 Integrator and Differentiator . .3 Differential Pair .4. . . .1 Precision Rectiﬁer . . .4. . . . . . .4 Voltage Adder . . . . . .2 Source Follower With Biasing . . . . . 8. . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . . . . .4 7. . .3. . . . .3 MOS Current Mirror . . . . . . . . . 8. . . . . . . . . . . . . . .1. . . .2. . . . . . . . . . . . . . 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. .1 Initial Thoughts . . . . . . 10 Differential Ampliﬁers 10. . . .1 CS Core . . . . .2 Input Bias Current .1 General Considerations . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1. . . . . . . . . . . 7. . . . . . . . . Common-Gate Stage . . . . . . . . . . . . . . . . . . . . . . . . . Source Follower .2. . . . .2. . 304 304 304 308 309 309 312 313 314 318 320 324 326 326 328 330 353 353 355 355 358 360 366 368 368 369 370 370 370 373 377 381 382 394 394 394 401 408 408 410 418 438 438 438 440 442 443 443 8 Operational Ampliﬁer As A Black Box 8. . . .1 CG Stage With Biasing . . . . . . . 8. . . . . . . . . . . . 7. . . . . . . . . . . . . . .1 Noninverting Ampliﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 7. . . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . .4 Op Amp Nonidealities .1. . .4 Finite Input and Output Impedances 8. . . . . . . . . . . .2 CS stage With Current-Source Load . . . . . . . . . . .3 Speed Limitations . . . . . . . . . . . . .3. . . . . . . . . . 8. . . . . . . . . . . . 10. . . . . . . . . . . . . . . . . . . . . . 10. . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7. . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . .4. . 8. . . . . .1 MOS Ampliﬁer Topologies . . . . . . .1 Qualitative Analysis . . . . . .3. . . . . . .2 Op-Amp-Based Circuits . . . . . . . . . . . . . . . . . . . . . .3 CS stage With Diode-Connected Load 7. . .2 Logarithmic Ampliﬁer . . . . 9 Cascode Stages and Current Mirrors 9. . . . .1. . . . . . . . . . . . .2 Bipolar Current Mirror . . . . . . . 7. . . . . . . . . . .1 Cascode Stage . . . . . . . . . . . . 8. . . . 8.2 Inverting Ampliﬁer .2 Cascode as an Ampliﬁer . . . . . . .4 CS Stage With Degeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . . . . . 7. .3 Square-Root Ampliﬁer .2. . . . . . . . . . . . . . .2. . . . . . . 9. . .2. . . .1 Source Follower Core . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . . . 10. . . . . . . . 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 General Considerations . . . . . . . . . .2. . . . . . . . . . . . . . . . . . . . . . . . 9. . . . . . . .2 Current Mirrors . . . . Summary and Additional Examples . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . .2 Bipolar Differential Pair . . . . . . . . . . . . . . . . . . . . . . 9. . . . . . . . . . . . .1 Initial Thoughts . . . . . . . . . . . . . . . . .4. . . . . . . . . . . . . . . . . .5 Design Examples . . . . . . .xxv 7. . .2 Differential Signals . . . . . . . . . . . . . . .1 DC Offsets . . . . . . . . 10. . . . . . . . . . . . .1 7. . . . 7. . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. . . . . . .3 Realization of Current Sources . . . . 7. . . . . . .1 General Considerations . . . . 9. 8. . 8. . . . Common-Source Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. .2 Biasing . . . . . . . . . 10. .3 Nonlinear Functions . . 8. . . . . . . . . . 7. . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . .5 CS Core With Biasing . . . . . . . . . . . . . .1 Cascode as a Current Source 9. . . 8. .

. . . . . 12. . . . . . . . . .1 Gain Desensitization . .1 Qualitative Analysis . . . . . . . .2 High-Frequency Models of Transistors . . . .2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Frequency Response of CE and CS Stages . . . .2 Voltage-Current Feedback . . . . . . .1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . .3 Input Impedance .3 Modiﬁcation of I/O Impedances 12. . . . . . . . . . . . . . . . . . . . . . . . . .2. . . 12 Feedback 12. .3. . . . . . . . 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cascode Differential Ampliﬁers . . . .3.1. . . . . . . . . . . . . . . . . . . . . . . . . . 10. 11. . . . . . . 11. . . . . 11. . . . . . . . . . . . . . . . . . . . . . . .3 Types of Ampliﬁers . . . . . . . .1 Simple Ampliﬁer Models . . . . . . . . . . . . . . . . . . . . . . . . . 11. . . . . . . . .6 Frequency Response of Cascode Stage . . . . . . . . . . . . .1. 12. 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Direct Analysis . . . . .1 Qualitative Analysis . . .6. . . . . . . . . . . . .6. . . . . . . .6. . . .5. . 12. . . . . . . . . 11. . . . . .2 Large-Signal Analysis . . . . . .1 Voltage-Voltage Feedback . . . . . . . . . . . . . . .3. . . . . . . . . . . . .2. . . . . . . . . . . . . . . . . . . . . .1 High-Frequency Model of Bipolar Transistor .1 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Current-Current Feedback . . . . . . . . . . . . 11. . . 10. . . . . . . . . . . .5 Polarity of Feedback . .2 Examples of Ampliﬁer Types . . . . . . . . .2 Quantitative Analysis . . . . . . . . . . .1 Input and Output Impedances . . . . . . . . . . . 12. . . . .1 Relationship Between Transfer Function and Frequency Response 11. . . . . . . . . . . . . 11. . . .2 High-Frequency Model of MOSFET . 10.6 Feedback Topologies . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . .4 Frequency Response of CB and CG Stages . . . . . . . . . . . . . . . . . . . . . . . . . .2 Large-Signal Analysis . . . . . . . . . . . . . . . . . . .4 Linearity Improvement . . . . . . . MOS Differential Pair . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . .xxvi 10. . . . .2. . . . . . . . . . . . . . 12. . . . . . 12. . .2 Bandwidth Extension . . . . . Differential Pair with Active Load 10. 11. . . . . . . . . . . .3 10. . . . . . . 10.2. . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Small-Signal Analysis . . 11. . . . . . . . . . . . . . . . . . . . . . . . . . . 11. 11.6. . . . . . . . . . . . . . 12.4 Miller’s Theorem . . . . .4 10. . 449 453 459 459 463 468 471 475 479 479 481 504 504 506 507 508 509 512 512 514 516 516 517 519 521 521 523 525 529 532 532 547 547 550 551 551 553 554 558 558 559 560 562 565 567 567 571 574 578 11 Frequency Response 11. . . . . . . . . . . . . .5 Frequency Response of Followers . . . . . . . . . .4 Sense and Return Techniques . . . . . . . .1. . . 11. . . .3 Current-Voltage Feedback . . . . . . . . . . 11. . . . . . . . . . . . . . . . 12.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Considerations . . . . . . . . . . 11. . . . . . . . . . . . 12. . . . 12. . . . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . .1 Input and Output Impedances . . . . . . . . . . . . . . . . . . . . .2 Properties of Negative Feedback . . . . .6. . . . . . . . . . . . . . . . . Common-Mode Rejection . . . . . .6. . . . . . . . . . . . . . . . 11. 12. . . . . . . . . . .1 Use of Miller’s Theorem . . . . . . .2 Bode Rules . .5 10. . . . . 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . 12. . . . . . . . . . . . . . . . . . . . . .1. . . .6 10. . . . . . . .6. . .3 Transit Frequency . . . . . .3 Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . .7 Frequency Response of Differential Pairs . . . 12. . . . . . . . . . . . . . . . . . .2. . .3 Association of Poles with Nodes .3. . .

. . . . . .8 Efﬁciency . . . . . . . . . . . . . . . . . . . . . . .9 Power Ampliﬁer Classes . . 13. . . . . . . . . . . . . . . . .2 Classiﬁcation of Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 High-Fidelity Design . . 12. . . . .5. . . . . .3 Filter Transfer Function . . 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14. . . . . . . .5 Large-Signal Considerations .8 Stability in Feedback Systems . . . . . . . . . . .1.5. . . . . . . . . . . . . . . . . . 12. . . . . . . . . . . . .1 Emitter Follower Power Rating . . . . . . 13. . . . . . . . . . . . . . . . . . . . . . . . . . 13. . . . . .4 Phase Margin . . .xxvii 12. . . . . . . 13. . . . . .2 Addition of CE Stage . . . . . . . . .1.1 Filter Characteristics . . . . . . . . . . . . . . . . . . . . 14. . . . . . . . . . . . . .4. . . .7. . . . . . . . . . . . . . . . . . . . .1 Butterworth Response . . . . . . . 14.2 Chebyshev Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8. 14. . . . . . . . . . . . . . . . . . . . .8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Emitter Follower as Power Ampliﬁer . . . 13. . . . . . . . . . . . . . . . . . . . .3 Thermal Runaway . . . . . . 13. . . . . . . .1 Reduction of Crossover Distortion . . . . . .1 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . .2 Omission of PNP Power Transistor 13. 14. 14. . . . . . . .2 Problem of Instability .6 Short-Circuit Protection . . . . . . . . . . . . . . . . . . .8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8. . . . . . . . . . . . . . . . . . .1 Biasing Issues . . .4 Problem of Sensitivity . . .4. . . . . . . . . .1 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8. . . .4. . . . . . . 13. . . . . . . . . . . . . . . . . .1 Review of Bode’s Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Stability Condition . . . . . . . 14. . . . . . 13. .5 Frequency Compensation . . . . . . . . . . . . . . . . . . .8. . . . . . .2 Push-Pull Stage Power Rating . . . . . . .4. . . . . .5. . 15 Digital CMOS Circuits 707 15. . . . . . . . . . . . . .5. . . . . . . . . . . . . . . . 12. . 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 . . . . . . . . . . .1 Inclusion of I/O Effects . . 14. . . . . . . 14. 13. . . . . .2 RLC Realizations . . . . .1 General Considerations . . . . . . .5. . 14. . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Effect of Finite I/O Impedances . . . . . . . . . .1. . . . . . . . . . . . .2 Efﬁciency of Push-Pull Stage . . . . . . . . . . . . . . . .7. . . . . . . . . .2 Integrator-Based Biquads . . . 14. . . . . . . . 13. . .8. . . . . . . . . 14. . . . . . 12. . .4 Active Filters . . . . . .7. . . . . . . .3 Push-Pull Stage . . . . . . . . . . . . . . . . . . 12. . . . . . 12. . 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Approximation of Filter Response . . . . . 13. . . 14 Analog Filters 14. . . . . . . . . . . . . . 12. . . . . . . . . . . . . . . .6 Miller Compensation . . . . . . . . . . . . . . . . .1 Sallen and Key Filter . . . . . . . . . . . .7 Heat Dissipation . . . 13. . . . . . . . . . . . . . 13.1. . . . . . . . . . . 14. . . 581 582 593 593 595 598 601 602 606 623 623 624 626 629 629 632 636 636 637 640 640 641 641 642 644 645 645 646 647 656 656 657 658 661 664 665 667 668 671 676 676 681 685 690 690 695 13 Output Stages and Power Ampliﬁers 13. . . . . . . . . .3 Second-Order Filters . . . .3 Biquads Using Simulated Inductors 14. . . . . 13. . . . . . . . . . .1 Efﬁciency of Emitter Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8. . . . .2 First-Order Filters . 13. . . . . . . 12.7. . . . . . . . . . . . . .1 General Considerations . . . .3. . . . . . . . . . . . .4 Improved Push-Pull Stage . . . . . . .4. . . .

. . . . . . . . . . . . . A. . . . . . . . . . . . . . 15. . . . . . .1. . . . . . . . . . . . . . . . . . . . . .2 CMOS Inverter . . . .1 Static Characterization of Gates . . . . . 15. . . . A. 15. . . . .3 Bipolar Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 714 717 719 719 721 726 731 734 734 737 746 746 748 749 749 752 753 753 754 756 758 761 761 762 .2. . . . . . . . . . . . . . . . . . . . . . . . . . .1 Current Sources .4 Power Dissipation . . . . . . . . . . . . . . . .3. . . . . . . A Introduction to SPICE A. . . . . . . A. . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Element Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . A. . . . . . . . . . . 15. . . . . . . . . . . . . . . . . .1 Simulation Procedure . . . . .1 Dependent Sources . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . A. . . . . .2 Transient Analysis . . . . . . . .3 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Operating Point Analysis A. . . . A. . 15. . . . . . . . . . . . . . . .2 Diodes . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . .3 DC Analysis . . . .2. . . . . . 15. A. . . . . . . . .3 Power-Speed Trade-Off . . . .2 Types of Analysis .3. . . . . .3 CMOS NOR and NAND Gates . . . . . . . . . . . . . . . .1 Initial Thoughts . .2 Dynamic Characterization of Gates 15. . . . . . . . . . .3. .2. . .2. . . . . A. . . . . . . . . . . . . . . .2 Initial Conditions . . . . . . . . . . . . . . . .2. . . . . . . . . . . 15. . . . .2. A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . . . A. . . .4 Other Elements and Commands A. . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . .xxviii 15. .4. . .2 NAND Gate . . . . . . . .1 NOR Gate . . . . . . . . . . . . . .3. . . . . . . . 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1. . . . . . .4 MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Voltage Transfer Characteristic . . . . . . . . . . . . . . . .

e. While beyond the realm of possibility a few decades ago. What other issues would arise in such an implementation? The minimum volume is given by 27 mm3 108 . less than 1 cm3 in packaged form) than vacuum tubes did. The ﬁrst transistor was invented in the 1940s and rapidly displaced vacuum tubes. We also provide a review of basic circuit theory to refresh the reader’s memory.. We introduce examples of microelectronic systems and identify important circuit “functions” that they employ. 2006] June 30. cellphones. laptop computers. Early “integrated circuits” (ICs) contained only a handful of devices. Learning microelectronics can be fun. a cube 1. determine the minimum volume for the processor. how devices comprise circuits that perform interesting and useful functions. i.1 Electronics versus Microelectronics The general area of electronics began about a century ago and proved instrumental in the radio and radar communications used during the two world wars. As we learn how each device operates. If each device occupies a volume of 3 mm 3 mm 3 mm... we begin to see the beauty of microelectronics and appreciate the reasons for its explosive growth. It exhibited a very long (in principle.e. Early systems incorporated “vacuum tubes. 1.4 m on each side! Of course. began.1 Today’s microprocessors contain about 100 million transistors in a chip area of approximately 3 cm 3 cm.” amplifying devices that operated with the ﬂow of electrons between plates in a vacuum chamber. i.) Suppose integrated circuits were not invented and we attempted to build a processor using 100 million “discrete” transistors.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the 1 Solution . but advances in the technology soon made it possible to dramatically increase the complexity of “microchips. However.g. microelectronics has revolutionized our lives. But it was not until 1960s that the ﬁeld of microelectronics. and how circuits form sophisticated systems. the ﬁnite lifetime and the large size of vacuum tubes motivated researchers to seek an electronic device with better properties. inﬁnite) lifetime and occupied a much smaller volume (e.cls v. (The chip is a few hundred microns thick. digital cameras. This chapter gives an overview of microelectronics so as to provide a context for the material presented in this book. 2007 at 13:42 1 (1) 1 Introduction to Microelectronics Over the past ﬁve decades.” Example 1. the science of integrating many transistors on one chip. and many other electronic products have now become an integral part of our daily affairs.

. What goes on in these black boxes? Why are they needed? Transmitter (TX) Microphone ? ? (a) (b) Figure 1. the signals would need to travel on wires as long as 1.2 Examples of Electronic Systems At this point.. 1. to convert most of the electrical signal to electromagnetic radiation.cls v. this discrete processor would be extremely slow. How well does this system work? We make two observations. Second. 1. i. e. if each discrete transistor costs 1 cent and weighs 1 g.. after some processing. In addition to occupying a large volume. to obtain a reasonable antenna length. 1.g. But our objective here is to see how the concepts described in this book prove relevant to the operation of a cellphone. 5 cm. applied to the speaker [Fig. the wavelength must be around 20 cm and the frequency around 1.1 (a) Simpliﬁed view of a cellphone. a frequency range of 20 Hz to 20 kHz translates to a wavelength1 of 1:5 107 m to 1:5 104 m. requiring gigantic antennas for each cellphone.5 GHz. 2006] June 30. each processor unit would be priced at one million dollars and weigh 100 tons! Exercise How much power would such a system consume if each transistor dissipates 10 W? This book deals with mostly microelectronics while providing sufﬁcient foundation for general (perhaps discrete) electronic systems as well. (b) further simpliﬁcation of transmit and receive paths.e. its dimension must be a signiﬁcant fraction (e. 25) of the wavelength. we introduce two examples of microelectronic systems and identify some of the important building blocks that we should study in basic electronics. 1 Recall that the wavelength is equal to the (light) velocity divided by the frequency. The signal produced by your antenna is picked up by the your friend’s receiver and.4 m! Furthermore. Unfortunately. transmitted by the antenna. for an antenna to operate efﬁciently.. our voice contains frequencies from 20 Hz to 20 kHz (called the “voice band”). 1. Your voice is converted to an electric signal by a microphone and.1(a)].1 Cellular Telephone Cellular telephones were developed in the 1980s and rapidly became popular in the 1990s. 1 Introduction to Microelectronics wires connecting the transistors would increase the volume substantially.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Today’s cellphones contain a great deal of sophisticated analog and digital electronics that lie well beyond the scope of this book.g. after some processing. Conversely. First. 2007 at 13:42 2 (1) 2 Chap.2.1(b). Suppose you are speaking with a friend on your cellphone. Receiver (RX) Speaker Let us attempt to omit the black boxes and construct the simple system shown in Fig.

1. the sinusoid. and since the spectrum x (t ) Voice Signal A cos( 2 π f C t ) Output Waveform t (a) t t X (f ) Voice Spectrum −20 kHz +20 kHz 0 Spectrum of Cosine Output Spectrum f −fC 0 +fC f −fC 0 +fC f (b) Figure 1.2(b)].2 (a) Multiplication of a voice signal by a sinusoid. a relatively large voltage swing (e. 1. .3(a).3 as depicted in Fig. 20 Vpp ) to the antenna so that the radiated power can reach across distances of several kilometers.1(a) contains a multiplier. 2006] June 30. 3 Also called a “mixer” in high-frequency electronics. This topology fails to operate with the principle of modulation: if the signal received by the antenna resides around a gigahertz center frequency. 1.cls v. Let us now turn our attention to the receive path of the cellphone.”2 We therefore postulate that the black box in the transmitter of Fig. 1.. This operation is an example of “amplitude modulation. beginning with the simple realization illustrated in Fig. a means of 2 Cellphones in fact use other types of modulation to translate the voice band to higher frequencies. the cellphone must deliver Power Amplifier A cos( 2 π f C t ) (a) Oscillator (b) Figure 1. (b) equivalent operation in the frequency domain. A cos2fc t [Fig. Unfortunately. by a sinusoid. Thus. xt. the audio speaker cannot produce meaningful information. of the sinusoid consists of two impulses at fc . In other words.2 Examples of Electronic Systems 3 How do we “convert” the voice band to a gigahertz center frequency? One possible approach is to multiply the voice signal.3 (a) Simple transmitter. Second. 1. Since multiplication in the time domain corresponds to convolution in the frequency domain.” We thus arrive at the transmitter architecture shown in Fig.g. 2007 at 13:42 3 (1) Sec. must be produced by an “oscillator.3(b). (b) more complete transmitter. A cos 2fc t. the output occupies a bandwidth of 40 kHz centered at 1 GHz. 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. First.2(a)].1(b). the voice spectrum is simply shifted (translated) to fc [Fig. thereby requiring a “power ampliﬁer” between the multiplier and the antenna. But two other issues arise. 1. if fc = 1 GHz.

power dissipation (i.2.. 1. This is because the design entails critical trade-offs between speed (gigahertz center frequencies). price of a cellphone). 1. and ﬁlters.2 Digital Camera Another consumer product that. e.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and multipliers in both transmit and receive paths of a cellphone. For example. weight. by virtue of “going electronic. and many other parameters. we received no immediate .g. oscillators. noise. The signal received by the antenna can be as low as a few tens of microvolts whereas the speaker may require swings of several tens or hundreds of millivolts. 1.4(c). 2007 at 13:42 4 (1) 4 Chap.cls v. as depicted in Fig. Nonetheless. since multipliers typically suffer from a high “noise” and hence corrupt the received signal. ampliﬁers. these building blocks still remain among the most challenging circuits in communication systems. The newly-generated components at 2fc can be removed by a low-pass ﬁlter.. With traditional cameras.. The overall architecture is depicted in Fig. A cos2fc t. (b) simple receiver. the reader may wonder if “this is old stuff” and rather trivial compared to the state of the art. a given design is never “good enough” and the engineers are forced to further push the above trade-offs in each new generation of the product. We therefore devote a great deal of effort to the analysis and design of ampliﬁers. a “low-noise ampliﬁer” must precede the multiplier. the receiver must provide a great deal of ampliﬁcation (“gain”) between the antenna and the speaker.4(b). 2006] June 30. the voice signal in the transmitter and the receiver is applied to a digital signal processor (DSP) to improve the quality and efﬁciency of the communication. our study reveals some of the fundamental building blocks of cellphones. In the competitive world of cellphone manufacturing. (b) more complete receiver. fc . with the last two also utilizing ampliﬁcation. translates the spectrum to left and right by Output Spectrum Received Spectrum Spectrum of Cosine −fC 0 +fC f −fC 0 +fC f (a) −2 f C 0 +2 f C f Low−Noise Amplifier Low−Pass Filter Low−Pass Filter Amplifier oscillator (b) oscillator (c) Figure 1. Furthermore. For example. restoring the original voice band.e. We thus arrive at the receiver topology shown in Fig. oscillators.” has dramatically changed our habits and routines is the digital camera. That is. 1 Introduction to Microelectronics translating the spectrum back to zero center frequency is necessary. 1.4 (a) Translation of modulated signal to zero center frequency. Interestingly. battery lifetime).e.4(a). Today’s cellphones are much more sophisticated than the topologies developed above. cost (i. Our receiver design is still incomplete. multiplication by a sinusoid. Having seen the necessity of ampliﬁers.

The “front end” of the camera must convert light to electricity. thereby developing a 25 Amplifier 00 C ol um ns Light I Diode CL Photodiode (a) (b) V out 2500 Rows Signal Processing (c) Figure 1.5(a).2 A digital camera is focused on a chess board. CL . proportional voltage across it. say. 1. How is the output voltage of each pixel sensed and processed? If each pixel contains its own electronic circuitry. In this section. we connect a wire to the outputs of all 2500 pixels in a “column. for a certain period of time.cls v.5(a) with a simple. Now consider a camera with. 1. 6. transmission of pictures through cellphones or ability to retouch or alter pictures by computers.25-million pixels arranged in a 2500 2500 array [Fig. on the other hand. we have resolved these issues and enjoy many other features that only electronic processing can provide.. The overall array consists of 2500 of such columns.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. With digital cameras. 4 The term “pixel” is an abbreviation of “picture cell. To this end. Now.5 (a) Operation of a photodiode. compact ampliﬁer and a switch (within the pixel) [Fig. we needed to carry bulky rolls of ﬁlm. We must therefore “time-share” the signal processing circuits among pixels. 2006] June 30. raising the cost and the power dissipation considerably. Sketch the voltage produced by one column as a function of time. e.”4 Each pixel consists of an electronic device (a “photodiode” that produces a current proportional to the intensity of the light that it receives. (b) array of pixels in a digital camera. with each column employing a dedicated signal processing block. 1.g. we follow the circuit of Fig. the overall array occupies a very large area. we were very careful in selecting and shooting scenes to avoid wasting frames. Each pixel thus provides a voltage proportional to the “local” light density. this current ﬂows through a capacitance. As illustrated in Fig.5(b)]. a task performed by an array (matrix) of “pixels. 1. (c) one column of the array. 1. Example 1.2 Examples of Electronic Systems 5 feedback on the quality of the picture that was taken. 2007 at 13:42 5 (1) Sec.” .5(c)]. and apply the corresponding voltage to the “signal processing” block outside the column.” turn on only one switch at a time. and we would obtain the ﬁnal result only in printed form. we study the operation of the digital camera.

In practice.7). The resulting waveform is shown in Fig. the V column V column t (a) (b) (c) Figure 1. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 Sharing one ADC between two columns of a pixel array. 1. very fast ADC for all 2500 columns. Once in the digital domain. (b) voltage waveform of one column. to “zoom in. we must ﬁrst “digitize” it by means of an “analog-to-digital converter” (ADC). For example. What does each signal processing block do? Since the voltage produced by each pixel is an analog signal and can assume all values within a range.6(a)]. In the extreme case.6 (a) Chess board captured by a digital camera. 1.6(b). the optimum choice lies between these two extremes. we may time-share one ADC between every two columns (Fig. the “video” signal collected by the camera can be manipulated extensively. we may employ a single.” the digital signal processor (DSP) simply considers only . Exercise Plot the voltage if the ﬁrst and second squares in each row have the same color. but requiring that the ADC operate twice as fast (why?).cls v. 1 Introduction to Microelectronics Solution The pixels in each column receive light only from the white squares [Fig. A 6. 1. Since ADCs are relatively complex circuits. 2007 at 13:42 6 (1) 6 Chap.25 megapixel array must thus incorporate 2500 ADCs. column voltage alternates between a maximum for such pixels and zero for those receiving no light. 2006] June 30. ADC Figure 1.

video. 1. 2007 at 13:42 7 (1) Sec. and music This section serves as a review and can be skipped in classroom teaching. contain no analog functions. and the digital functions consist of subsequent signal processing and storage. . Second. “I have no intention of working for a cellphone or camera manufacturer and.3 Basic Concepts 7 a section of the array. The ﬁnite risetime and falltime of the latter raises many issues in the operation of gates.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1. and other digital circuits. Called “analog. and analog-to-digital conversion. digital signal processors. circuits that must process each point on a waveform (e.4 must employ low-noise and power ampliﬁers. Signals that occur in nature can assume all values in a given range. 10 ns x 1 (t ) 1 ns t x 2 (t ) t Figure 1. 1. ﬂipﬂops.2. seismic. therefore.3 and 1.” such signals include voice. a voice signal) with great care to avoid effects such as noise and “distortion. one at 100 Mb/s and another at 1 Gb/s. Also.g. For example.8 exempliﬁes this point by illustrating two binary data waveforms. 1. The reader may then say. Similarly. Figure 1. the processor “compresses” the video signal. oscillators. necessitating great attention to each point on the waveform.” By contrast.3 Basic Concepts Analysis of microelectronic circuits draws upon many concepts that are taught in basic courses on signals and systems and circuit theory. The architectures of Figs.” In fact. This section provides a brief review of these concepts so as to refresh the reader’s memory and establish the terminology used throughout this book. First. “digital” circuits deal with binary levels (ONEs and ZEROs) and. the video signal collectively captured by the pixels in a digital camera must be processed with low noise and distortion before it appears in the digital domain. 1.3 Analog versus Digital Ampliﬁers and ADCs are examples of “analog” functions. with digital communications. a 20-V signal (analog or digital) received by the antenna cannot be directly applied to a digital gate. to reduce the required memory size.8 Data waveforms at 100 Mb/s and 1 Gb/s.1 Analog and Digital Signals An electric signal is a waveform that carries information. need not learn about analog circuits. discarding the information from the remaining pixels. not every function can be realized digitally.. is there any future for analog design? Well. 2006] June 30. The analog functions include ampliﬁcation. switching operations. and multipliers regardless of whether the actual communication is in analog or digital form. evidently.3. and every other function becoming digital. The reader may ﬁrst glance through this section to determine which topics need a review or simply return to this material as it becomes necessary later. The digital camera exempliﬁes the extensive use of both analog and digital microelectronics. digital circuits require analog expertise as the speed increases. some of the assumptions in the above statements are incorrect.cls v.

which remains at only one of two levels for V (t ( ZERO ONE V ( t ( + Noise T T (a) t (b) t Figure 1. While occurring all around us. 1. The storage of binary signals (in a digital memory) is also much simpler. 1. “analog-to-digital conversion.” and digital processing (Fig. an analog voltage waveform swings through a “continuum” of V (t ( V ( t ( + Noise t t (a) (b) Figure 1. Depicted in Fig.g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The foregoing observations favor processing of signals in the digital domain. Consider.11). complex microelectronic systems such as digital cameras. 2006] June 30. Upon retrieval. and compact disk (CD) recorders perform some analog processing. values and provides information at each instant of time. T .. capacitors). It is worth noting that many digital binary signals must be viewed and processed as analog waveforms. Indeed.”5 As an example. Digital Processing and Storage Analog Signal Analog Processing Analog−to−Digital Conversion Figure 1. 1 Introduction to Microelectronics waveforms.9(a). the “digital” data appears as a distorted waveform with only a few millivolts of amplitude 5 Distortion arises if the output is not a linear function of input.10(b)].10(a) is a “binary” waveform. for example. camcorders. a digital signal assumes only a ﬁnite number of values at only certain points in time. 1.9 (a) Analog signal . So long as the two voltages corresponding to ONEs and ZEROs differ sufﬁciently. 1. (b) effect of noise on digital signal. the information stored on a hard disk in a computer. Figure 1.10 (a) Digital signal. with the ﬁrst two functions playing a critical role in the quality of the signal. each period. analog signals are difﬁcult to “process” due to sensitivities to such circuit imperfections as “noise” and “distortion. Shown in Fig.11 Signal processing in a typical system.9(b) illustrates the effect of noise. analog signals are difﬁcult to “store” because they require “analog memories” (e. We therefore consider digital signals more “robust” than their analog counterparts.cls v. 2007 at 13:42 8 (1) 8 Chap. (b) effect of noise on analog signal. logical circuits sensing such a signal process it correctly—even if noise or distortion create some corruption [Fig. . By contrast. suggesting that inherently analog information must be converted to digital form as early as possible. Furthermore.

Calculate the required voltage gain in decibels.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.12). The voltage gain.2 Analog Circuits Today’s microelectronic systems incorporate many analog functions. 2006] June 30. we prefer to express the gain in decibels (dB): Av jdB = 20 log vvout : in (1. e.3) (1.cls v. The signal received by a cellphone or picked up by a microphone proves too small to be processed further.3 Solution We have Av = 20 log 50 mV 20 V 68 dB: (1.4) Exercise What is the output swing if the gain is 50 dB? . As exempliﬁed by the cellphone and the digital camera studied above. 1. Example 1. is to drive a logical gate.. and power dissipation. a voltage gain of 10 translates to 20 dB.3. Such a small separation between ONEs and ZEROs proves inadequate if this signal ~3 mV Hard Disk t Figure 1. An ampliﬁer is therefore necessary to raise the signal swing to acceptable levels. demanding a great deal of ampliﬁcation and other analog processing before the data reaches a robust digital form. A voltage ampliﬁer produces an output swing greater than the input swing. gain. The most commonly-used analog function is ampliﬁcation. but it must deliver a swing of 50 mV to the speaker that reproduces the voice. analog circuits often limit the performance of the overall system.12 Signal picked up from a hard disk in a computer. The gain of typical ampliﬁers falls in the range of 101 to 105 . is deﬁned as Av = vvout : in (1.1) In some cases. A cellphone receives a signal level of 20 V.2) For example.3 Basic Concepts 9 (Fig. The performance of an ampliﬁer is characterized by a number of parameters. 1. 1.g. but it is instructive to brieﬂy review some of these concepts here. 2007 at 13:42 9 (1) Sec. speed. We study these aspects of ampliﬁcation in great detail later in this book. Av .

g. Ampliﬁers (and other analog circuits) suffer from trade-offs between gain. with the understanding that they are present. 2007 at 13:42 10 (1) 10 Chap. an electrocardiograph measuring a patient’s heart activities also picks up the 60-Hz (or 50-Hz) electrical line voltage because the patient’s body acts as an antenna.” For example. static and dynamic memories. Called the “power supply.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 Digital Circuits More than 80 of the microelectronics industry deals with digital circuits. and other components.14 Roll-off an ampliﬁer’s gain at high frequencies. ﬂipﬂops. we study the design of the internal circuits of gates. and power dissipation of these building blocks play a central role in the overall system performance. limiting the (usable) “bandwidth” Amplifier Gain High−Frequency Roll−off Frequency Figure 1. we may simplify the notation to that shown in Amplifier VCC V in Vout V CC V in Vout Ground (a) (b) (c) Figure 1. For example. of the circuit.13(b). speed and power dissipation. 1 Introduction to Microelectronics In order to operate properly and provide gain.3. Thus. V in Vout Fig. Typical ampliﬁers operate with supply voltages in the range of 1 V to 10 V. What other analog functions are frequently used? A critical operation is “ﬁltering. (b) ampliﬁer with supply rails omitted. In digital microelectronics. thereby lowering the gain. 1. and digital signal processors. Examples include microprocessors.. Today’s microelectronic ampliﬁers achieve bandwidths as large as tens of gigahertz. 1.” this source is typically denoted by VCC or VDD [Fig. e. an ampliﬁer must draw power from a voltage source.13(a)]. we construct a circuit using devices such as transistors to . as depicted in Fig. a ﬁlter must suppress this “interferer” to allow meaningful measurement of the heart.13 (a) General ampliﬁer symbol along with its power supply.14.13(c)]. (b) simpliﬁed diagram of (a). In complex circuits. the gain rolls off at sufﬁciently high frequencies. and latches and ﬂipﬂops constitute “sequential” machines. 1. What limits the speed of ampliﬁers? We expect that various capacitances in the circuit begin to manifest themselves at high frequencies. a battery or a charger. speed. Recall from basic logic design that gates form “combinational” circuits. 2006] June 30. The complexity. If the ampliﬁer is simply denoted by a triangle. 1.cls v. In other words. we may even omit the supply terminals [Fig. 1. where the “ground” terminal signiﬁes a reference point with zero potential.

If A is high. where switch S1 is controlled by the digital input. the output is high.4 Figure 1.e. i. forcing Vout to zero.. the output assumes the opposite state. S1 remains off. some prove particularly important to our study of microelectronics. 1. Based on these implementations.16)? ? Figure 1. 1. On the other hand.17 is. Consider the circuit shown in Fig. if A is high. early digital circuits did employ mechanical switches (relays). Prove that the circuit provides the NOT function.17. 1. 1. As a result.15 NOT and NOR gates. This section provides a review of such concepts. if A is low. S1 is on and vice versa. For example.3 Basic Concepts 11 realize the NOT and NOR functions shown in Fig.4 Basic Circuit Theorems Of the numerous analysis techniques taught in circuit theory courses. but suffered from a very limited speed (a few kilohertz). 2007 at 13:42 11 (1) Sec.cls v. we NOT Gate NOR Gate A Y =A A B Y =A +B Figure 1. . 2006] June 30.16 Response of a gate to a noisy input. We thus observe that. Solution Exercise Determine the logical function if S1 and RL are swapped and Vout is sensed across RL . drawing no current from RL . That RL A S1 V DD Vout Example 1. In fact. It was only after “transistors” were invented and their ability to act as switches was recognized that digital circuits consisting of millions of gates and operating at high speeds (several gigahertz) became possible.15. then determine various properties of each circuit. 1.3. what limits the speed of a gate? How much power does a gate consume while running at a certain speed? How robustly does a gate operate in the presence of nonidealities such as noise (Fig. S1 is on.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the voltage drop across RL is zero and hence Vout = VDD . for both logical states at the input. The above example indicates that switches can perform logical operations.

we may not know a priori the correct polarities of the currents and voltages.19(a). we may sum the voltages in the loop to zero: V1 + V2 + V3 + V4 = 0. write KCLs and KVLs.18 Illustration of KCL. . 1 Introduction to Microelectronics I1 I2 In Ij Figure 1.19(a)]: 2 V2 1 V2 V3 3 1 2 3 V1 V1 V3 V4 4 V4 4 (a) (b) Figure 1. 1. 2007 at 13:42 12 (1) 12 Chap. The Kirchoff Voltage Law (KVL) states that the sum of voltage drops around any closed loop in a circuit is zero [Fig.” In the example illustrated in Fig. KVL arises from the conservation of the “electromotive force. 1. X j Vj = 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In solving circuits. V3 . Kirchoff’s Laws The Kirchoff Current Law (KCL) states that the sum of all currents ﬂowing into a node is zero (Fig. Alternatively. adopting the modiﬁed view shown in Fig. Nonetheless. 2006] June 30.cls v. (b) slightly different view of the circuit . 1. we can simply assign arbitrary polarities.18): X j Ij = 0: (1. (1. 1. Note that the polarities assigned to V2 .6) where Vj denotes the voltage drop across element number j .5) KCL in fact results from conservation of charge: a nonzero sum would mean that either some of the charge ﬂowing into node X vanishes or this node produces charge.19(a).19(b). and solve the equations to obtain the actual polarities and values. and 4: V1 = V2 + V3 + V4 . 3.19 (a) Illustration of KVL. 1. we can say V1 is equal to the sum of the voltages across elements 2. and V4 in Fig.19(b) are different from those in Fig. 1.

rπ vπ i 1 g vπ R L m v out v in Figure 1.6 multiplied by the voltage drop across v in v out RL rπ vπ i 1 g vπ R L m v out Figure 1. we must eliminate v from the equations. 1. Writing a KVL in the “input loop. Compute the gain.7) = gmvin .8) vout = . Determine the voltage gain of the ampliﬁer.e. A KCL at the output node yields gm v + vout = 0: R L It follows that (1.20 r .21 shows another ampliﬁer topology.9) 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. gm . 2006] June 30. and hence gm v (1. 2007 at 13:42 13 (1) Sec. Example 1.” we have Solution vin = v . We must compute vout in terms of vin .21 6 What is the dimension of gm ? . vout =vin .6 Figure 1. (1.cls v. Unimportant in most cases.5 The topology depicted in Fig. i. the negative Exercise Repeat the above example if r ! infty. The dependent current source i1 is equal to a constant.3 Basic Concepts 13 Example 1.g R : m L vin Note that the circuit ampliﬁes the input if gm RL sign simply means the circuit “inverts” the signal..20 represents the equivalent circuit of an ampliﬁer. 1.

12) That is.v : The KCL at the output node is similar to (1.7 A third ampliﬁer topology is shown in Fig.11) Exercise Repeat the above example if r ! infty. vout for v gives vin r + gm = vout R1 + r1 + gm . Example 1. (1. r . vout . and the current vout =RE ﬂows out of it. 1 Introduction to Microelectronics Noting that r in fact appears in parallel with vin .cls v. we write a KVL across these two components: Solution vin = . rπ vπ i 1 g vπ m v in RE v out Figure 1. 2006] June 30.13) Substituting vin .22. Thus. 1. and RE : Solution vin = v + vout : v + g v = vout : r m RE (1. (1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. E and hence . 2007 at 13:42 14 (1) 14 Chap. Next. we write a KCL: (1.8). noting that the currents v =r and gm v ﬂow into the output node. v = vin . Determine the voltage gain.22 We ﬁrst write a KVL around the loop consisting of vin .10) vout = g R : vin m L Interestingly. this type of ampliﬁer does not invert the signal.

1 .

(1.14) 1 vout = r + gm 1 1 vin RE + r + gm (1.15) .

(b) computation of equivalent impedance. 2007 at 13:42 15 (1) Sec. vThev .8 Suppose the input voltage source and the ampliﬁer shown in Fig. ZThev .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.23(a). is determined by setting all independent voltage and current sources in the circuit to zero and calculating the impedance between the two nodes. We also call ZThev the impedance “seen” when “looking” into the output port [Fig.20 are placed in a box and only the output port is of interest [Fig. 1. is obtained by leaving the port open and computing the voltage created by the actual circuit at this port. Determine the Thevenin equivalent of the circuit. Would such an ampliﬁer prove useful at all? In fact. 1.23(b)].23 (a) Thevenin equivalent circuit. 1. voltage. provide additional insight into the operation of a circuit. Solution We must compute the open-circuit output voltage and the impedance seen when looking into the .cls v. Example 1. 1. A few examples illustrate these principles. more importantly. this topology exhibits some important properties that make it a versatile building block. Exercise Repeat the above example if r ! infty. Illustrated in Fig. the term “port” refers to any two nodes whose voltage difference is of interest. The above three examples relate to three ampliﬁer topologies that are studied extensively in Chapter 5. The impedance is computed by applying a voltage source across the port and obtaining the resulting current. Thevenin’s theorem states that a (linear) one-port network can be replaced with an equivalent circuit consisting of one voltage source in series with one impedance. 1. The equivalent impedance. 2006] June 30.16) Note that the voltage gain always remains below unity.3 Basic Concepts 15 r E = r 1 + gmg rRR : + 1 + m E (1. the Thevenin and Norton theorems can both simplify the algebra and. Thevenin and Norton Equivalents While Kirchoff’s laws can always be utilized to solve any circuit.24(a)]. The equivalent Vj i X v Port j ZT v he X ZT v he v Th ev (a) (b) Figure 1.

24 output port. since both terminals of r are tied to ground.17) (1. v = 0 and gm v = 0.25(b)]. Fortunately. 1. (1. we can readily analyze its behavior in the presence of a subsequent stage or “load. The circuit thus reduces to RL and v iX = RX : L That is.24(a) and Eq.21) (1. 1. apply a voltage source. setting vin to zero means replacing it with a short circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.9 The ampliﬁer of Fig. and write sp vout = .24(b)? We must again eliminate v .24(c) depicts the Thevenin equivalent of the input voltage source and the ampliﬁer. Determine the Solution Shown in Fig. vX . 1 Introduction to Microelectronics iX RL vX − g m R Lv in v in rπ vπ i 1 g vπ m R L v out v in = 0 r π vπ i 1 g vπ m RL (a) (b) (c) Figure 1.gmRL vin R R+ R sp L = . across the output port. 1. As shown in Fig. Replacing the section in the dashed box with its Thevenin equivalent from Fig. Also.19) RThev = RL : (1. How do we solve the circuit of Fig.22) .gm RLvin : (1.18) To calculate ZThev . (1. 2007 at 13:42 16 (1) 16 Chap. whose value is not known a priori.20 must drive a speaker having an impedance of voltage delivered to the speaker.9): vThev = vout = . With the Thevenin equivalent of a circuit available. we set vin to zero. and determine the current drawn from the voltage source. In this case.25(a) is the overall circuit arrangement that must solve. we call RThev (= RL ) the “output impedance” of the circuit. 1.24(c). note that the current source gm v remains in the circuit because it depends on the voltage across r . Exercise Repeat the above example if r ! 1.24(b). 2006] June 30. The Thevenin voltage is obtained from Fig. 1.” Example 1. Rsp . iX . 1. we greatly simplify the circuit [Fig.cls v.gmvin RL jjRsp : (1. 1.20) Figure 1.

1.vX : v + g v + i = vX . and iX ﬂow into this node and the current vX =RL ﬂows out of it. Example 1.24) We now write a KCL at the output node.10 Determine the Thevenin equivalent of the circuit shown in Fig. 1.cls v. 2007 at 13:42 17 (1) Sec. Consequently.16): + r L vThev = r 1 1 gmg rRR vin : (1. (1.25) or . The currents v =r . To eliminate v . 2006] June 30. we recognize that the two terminals of r rπ vπ i 1 g vπ m iX RL v X vX RL Figure 1.22 if the output port is of interest.3 Basic Concepts RL 17 v in rπ vπ i 1 g vπ R L m v out R sp − g m R Lv in v out R sp Figure 1.26 are tied to those of vX and hence v = .23) + + m L To calculate the Thevenin impedance. r m X RL (1. 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we set vin to zero and apply a voltage source across the output port as depicted in Fig.26.25 (a) (b) Exercise Repeat the above example if r ! 1. gm v . Solution The open-circuit output voltage is simply obtained from (1.

1 vX r + gm .vX + iX = RL : (1.26) .

28) = r + 1r+RL r R : gm L Exercise What happens if RL = 1? Norton’s theorem states that a (linear) one-port network can be represented by one current source in parallel with one impedance (Fig.20 if the output port is of interest.28(a). iNor . Of course.27). Example 1.11 Determine the Norton equivalent of the circuit shown in Fig.28 across RL is now forced to zero. ZNor . 2007 at 13:42 18 (1) 18 Chap. 1 Introduction to Microelectronics That is. The equivalent impedance. shorting the port of interest and computing the current that ﬂows through it. this resistor carries no current.27) (1. ZNor = ZThev .27 Norton’s theorem.gmv (1. we short the output port and seek the value of iNor .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. is obtained by Port j Z No r No r i Figure 1. A KCL at the output node thus yields iNor = . is determined by setting all independent voltage and current sources in the circuit to zero and calculating the impedance seen at the port. 1. RThev = vX i X (1. 1. 1. Since the voltage i Nor v in rπ vπ i 1 g vπ R L m (a) Short Circuit Solution g v m in RL (b) Figure 1. 2006] June 30. As depicted in Fig.29) .cls v. The equivalent current.

2007 at 13:42 19 (1) Sec. 1. the same as the output voltage of the original circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. RNor (= RThev = RL . from Example 1.gm RL vin . vin = v (why?). yielding iNor = v + gmv : r (1. we observe that the ﬂow of iNor through RL produces a voltage of . we note that RL carries no current. Exercise Repeat the above example if a resistor of value R1 is added between the top terminal of vin and the output node. . Shorting the output port as illustrated in Fig.30) Also.31) iNor = r + gm vin : With the aid of Fig.22 if the output port is interest.gmvin : (1. Thus. 1.8.12 Determine the Norton equivalent of the circuit shown in Fig. 1. The Norton equivalent therefore emerges as shown in Fig. 2006] June 30.28(b). To check the validity of this model.29(a). 1.29 Also. 1.29(b). v in rπ vπ i 1 g vπ m ( 1 + g m ) vin rπ Solution r π RL r π + (1+ g mr π ) R L RL i Nor (a) (b) Figure 1.4 Chapter Summary 19 = . Example 1.cls v.

we construct the Norton equivalent depicted in Exercise What happens if r = infty? 1. laptop computers.1 (1.10. including cellphones. . etc. digital cameras.4 Chapter Summary Electronic functions appear in many devices.32) RThev found in Example 1.

By contrast. The voltage gain of an ampliﬁer is deﬁned as vout =vin and sometimes expressed in decibels (dB) as 20 logvout =vin . 2006] June 30. Similarly.” analog circuits ﬁnd wide application in most of today’s electronic systems.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Analog circuits process signals that can assume various values at any time. Kirchoff’s current law (KCL) states that the sum of all currents ﬂowing into any node is zero. digital circuits deal with signals having only two levels and switching between these values at known points in time.cls v. Kirchoff’s voltage law (KVL) states that the sum of all voltages around any loop is zero. 2007 at 13:42 20 (1) 20 Chap. 1 Introduction to Microelectronics Ampliﬁcation is an essential operation in many analog and digital systems. Despite the “digital revolution. . Thevenin’s theorem reduces a one-port circuit to a voltage source in series with an impedance. Norton’s theorem allows simplifying a one-port circuit to a current source in parallel with an impedance.

Next. we must develop a basic understanding of “semiconductor” materials and their current conduction mechanisms before attacking diodes.g. just as we need to eat our broccoli before having desert.” However. but must also be sufﬁciently brief to allow quick entry into circuits. we do face a dilemma. “If you do not push the devices and circuits to their limit but your competitor does.. so that a circuit using such a device can be analyzed easily. capacitors. Our treatment of device physics must contain enough depth to provide adequate understanding. Nonetheless. Semiconductors Charge Carriers Doping Transport of Carriers PN Junction Structure Reverse and Forward Bias Conditions I/V Characteristics Circuit Models It is important to note that the task of developing accurate models proves critical for all microelectronic devices. 2006] June 30. e. calling for aggressive designs that push semiconductor devices to their limits. a good understanding of the internal operation of devices is necessary. and formulate its behavior. voltage or current sources.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. This chapter accomplishes this task. In this chapter. The situation is similar to many other engineering problems.). While this book deals with the analysis and design of circuits. then you lose to your competitor. the ﬂow of current) in them.” which also serves as diode.” 21 . one cannot design a high-performance automobile without a detailed knowledge of the engine and its limitations. we should emphasize at the outset that a good understanding of devices is essential to our work.1 1 As design managers often say.e. The electronics industry continues to place greater demands on circuits.cls v.. The outline is shown below. we begin with the concept of semiconductors and study the movement of charge (i. we deal with the the “pn junction. Thus. Our ultimate goal is to represent the device by a circuit model (consisting of resistors. etc. Our ultimate objective in this chapter is to study a fundamentally-important and versatile device called the “diode. 2007 at 13:42 21 (1) 2 Basic Physics of Semiconductors Microelectronic circuits are based on complex semiconductor structures that have been under active research for the past six decades.

The above principles suggest that atoms having approximately four valence electrons fall somewhere between inert gases and highly volatile elements.2 2 Silicon is obtained from sand after a great deal of processing.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. neon exhibits a complete outermost shell (with eight electrons) and hence no tendency for chemical reactions. sodium has only one valence electron. ready to relinquish it.1 Outline of this section. called “valence” electrons. This outline represents a logical thought process: (a) we identify charge carriers in solids and formulate their role in current ﬂow. it is useful to bear a general outline in mind: Charge Carriers in Solids Crystal Structure Bandgap Energy Holes Modification of Carrier Densities Intrinsic Semiconductors Extrinsic Semiconductors Doping Transport of Carriers Diffusion Drift Figure 2.1.” The atom’s chemical activity is determined by the electrons in the outermost shell.2 Section of the periodic table. 2 Basic Physics of Semiconductors 2. possibly displaying interesting chemical and physical properties. eager to receive one more. 2. silicon merits a detailed analysis.1 Semiconductor Materials and Their Properties Since this section introduces a multitude of concepts. Shown in Fig. 2007 at 13:42 22 (1) 22 Chap. (b) we examine means of modifying the density of charge carriers to create desired current ﬂow properties.1 Charge Carriers in Solids Recall from basic chemistry that the electrons in an atom orbit the nucleus in different “shells. As the most popular material in microelectronics.2 is a section of the periodic table containIII IV V Boron (B) Aluminum (Al) Galium (Ga) Carbon (C) Silicon (Si) Germanium (Ge) Phosphorous (P) Arsenic (As) Figure 2. and how complete this shell is. 2006] June 30. These steps naturally lead to the computation of the current/voltage (I/V) characteristics of actual diodes in the next section. ing a number of elements with three to ﬁve valence electrons.cls v. and chloride has seven valence electrons. On the other hand. For example. 2. Both elements are therefore highly reactive. . (c) we determine current ﬂow mechanisms.

4 Movement of electron through crystal. 2. the silicon crystal behaves as an insulator for T ! 0K . at higher temperatures. Bandgap Energy We must now answer two important questions. Called a “hole.” such a void can readily absorb a free electron if one becomes available. 2. But. each atom shares one valence electron with its neighbors. or. requiring another four to complete its outermost shell.4. Suppose covalent bond number 1 contains a hole after losing an electron some time t = t1 1 Si Si Hole Si Si Si Si Si Si Si Si Si 2 Si t = t2 Si Si Si Si Si t = t3 Si 3 Si Si Si Figure 2. an electron leaves bond number 3 and falls into the hole in bond number 2. 2007 at 13:42 23 (1) Sec. 2. As a result.3(b) plays a crucial role in semiconductor devices. The uniform crystal depicted in Fig. before t = t1 . does it carry current in response to a voltage? At temperatures near absolute zero.cls v. consider the time evolution illustrated in Fig. thereby completing its own shell and those of the neighbors. at t = t3 .” we can say one electron has traveled from right to left. we say an “electron-hole pair” is generated when an electron is freed. an electron breaks away from bond number 2 and recombines with the hole in bond number 1. it is the free electron that actually moves in the crystal. refusing to move freely. (b) covalent bonds between atoms. alternatively. However. one hole has moved from left to right.3(a)]. the siliCovalent Bond Si Si Si Si Si Si Si Si Si Si Si Si Si e Si Si Free Electron (a) (b) (c) Figure 2. 2006] June 30. Similarly. occasionally breaking away from the bonds and acting as free charge carriers [Fig.3(b)]. (c) free electron released by thermal energy.3 (a) Silicon atom. con material can form a “crystal” wherein each atom is surrounded by exactly four others [Fig. This view of current ﬂow by holes proves extremely useful in the analysis of semiconductor devices.1 Semiconductor Materials and Their Properties 23 Covalent Bonds A silicon atom residing in isolation contains four valence electrons [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. At t = t2 . an electron leaves a “void” behind because the bond is now incomplete. electrons gain thermal energy. 2. does any thermal energy create free electrons (and holes) in silicon? No. the valence electrons are conﬁned to their respective covalent bonds. If processed properly. First.3(c)] until they fall into another incomplete bond. Looking at the three “snapshots. Thus. We will hereafter use the term “electrons” to refer to free electrons. and an “electron-hole recombination” occurs when an electron “falls” into a hole. Holes When freed from a covalent bond. To appreciate the usefulness of holes. The “bond” thus formed between atoms is called a “covalent bond” to emphasize the sharing of valence electrons. 2. in fact. 2. In other words. a minimum energy is required to . Why do we bother with the concept of the hole? After all.

a hole is left behind. thereby bringing ni toward zero. = 1:12 eV= 1:792 10. The ni values obtained in the above example may appear quite high. . But. we postulate that the number of electrons depends on both Eg and T : a greater Eg translates to fewer electrons. To simplify future derivations. The derivation can be found in books on semiconductor physics. but a higher T yields more electrons. it is possible to modify the resistivity of silicon by replacing some of the atoms in the crystal with atoms of another material. Eg = 1:12 eV.2) and (2. as T ! 0.2) (2.kTg electrons=cm3 2 (2. the electron density.23 J/K is called the Boltzmann constant. [1]. Eg = 2:5 eV for diamond. we recognize that only one in 5 1012 atoms beneﬁt from a free electron at room temperature.e. Determine the density of electrons in silicon at T Since Eg Example 2. 2006] June 30. Conductors. ni . noting that silicon has 5 1022 atoms=cm3 . Note that 1 eV= 1:6 10. Called the “bandgap energy” and denoted by Eg . for example. typically ranging from 1 eV to 1. so do T 3=2 and exp .5 eV. silicon still seems a very poor conductor. Fortunately. Also. 2007 at 13:42 24 (1) 24 Chap..3) Since for each free electron. Finally.19 J. For silicon. As expected.3 The second question relates to the conductivity of the material and is as follows. 2. How many free electrons are created at a given temperature? From our observations thus far. Insulators display a high Eg .5 eV. In other words.1 Solution = 300 K (room temperature) and T = 600 K. the number of electrons per unit volume. In an intrinsic semiconductor. e. semiconductors exhibit a moderate Eg .1) where k = 1:38 10.” suffering from a very high resistance.3).. but. have a small bandgap.19 J. we have ni T = 300 K = 1:08 1010 electrons=cm3 ni T = 600 K = 1:54 1015 electrons=cm3 : (2. is equal 3 The unit eV (electron volt) represents the energy necessary to move one electron across a potential difference of 1 V. i. materials having a larger Eg exhibit a smaller ni .cls v. the density of holes is also given by (2.2 Modiﬁcation of Carrier Densities Intrinsic and Extrinsic Semiconductors The “pure” type of silicon studied thus far is an example of “intrinsic semiconductors. 2 Basic Physics of Semiconductors dislodge an electron from a covalent bond.1. this minimum is a fundamental property of the material. The exponential dependence of ni upon Eg reveals the effect of the bandgap energy on the conductivity of the material. on the other hand. do not despair! We next introduce a means of making silicon more useful. and write for silicon: E ni = 5:2 1015T 3=2 exp .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g. n= ni . Exercise Repeat the above exercise for a material having a bandgap of 1. we consider the density (or concentration) of electrons.Eg =2kT .

four electrons with the neighboring silicon atoms. What happens if some P atoms are introduced in a silicon crystal? As illustrated in Fig. p. 2. i (2. How can atoms and increase n? np remain constant while we add more donor Equation (2.. then the density of free electrons rises by the same amount. np = n2 . Example 2. Thus. leaving the ﬁfth electron “unattached.” Providing many more free electrons than in the intrinsic state. np = n2 : i (2. The controlled addition of an “impurity” such as phosphorus to an intrinsic semiconductor is called “doping.5) where n and p respectively denote the electron and hole densities in the extrinsic semiconductor. The doping density is .2 The above result seems quite strange.2 that phosphorus (P) contains ﬁve valence electrons.” more speciﬁcally. As remarked earlier. if N phosphorus atoms are uniformly introduced in each cubic centimeter of a silicon crystal. the doped silicon crystal is now called “extrinsic. how about these densities in a doped material? It can be proved that even in this case.3 A piece of crystalline silicon is doped uniformly with phosphorus atoms. This occurs because many of the new electrons donated by the dopant “recombine” with the holes that were created in the intrinsic material.” and phosphorus itself a “dopant. Recall from Fig.5) reveals that p must fall below its intrinsic level as more n-type dopants are added to the crystal. 2. The quantity ni represents the densities in the intrinsic semiconductor (hence the subscript i) and is therefore independent of the doping level [e.g. Solution Exercise Why can we not say that n + p should remain constant? Example 2. 2007 at 13:42 25 (1) Sec. an “n-type” semiconductor to emphasize the abundance of free electrons.5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. But.1 Semiconductor Materials and Their Properties 25 to the hole density. 2006] June 30.cls v. serving as a charge carrier. Thus. each P atom shares Si Si Si Si P e Si Si Figure 2. 2. (2.1) for silicon].” This electron is free to move. the electron and hole densities in an intrinsic semiconductor are equal. Eq.4) We return to this equation later.5 Loosely-attached electon with phosphorus doping.

the fourth bond contains a hole. ready to absorb Si Si Si B Si Si Si Figure 2. if a voltage is applied across this piece of silicon. providing holes as majority carriers.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. then we may obtain many incomplete covalent bonds. As a result. N boron atoms contribute N boron holes to the conduction of current in silicon. we can assume Solution n = 1016 electrons=cm3 It follows from (2.5) that (2. 2. Indeed. 2007 at 13:42 26 (1) 26 Chap. If an intrinsic semiconductor is doped with a density of ND ( ni ) donor atoms per cubic centimeter. Determine the electron and hole densities in this material at the room temperature. 2. thereby exchanging the roles of electrons and holes.6 Available hole with boron doping. The addition of 1016 P atoms introduces the same number of free electrons per cubic centimeter. 2 Basic Physics of Semiconductors 1016 atoms/cm3 .10) . if we can dope silicon with an atom that provides an insufﬁcient number of electrons.2) and (2.6). 2. Since this electron density exceeds that calculated in Example 2. The structure in Fig.8) Note that the hole density has dropped below the intrinsic level by six orders of magnitude.7) (2. Thus.cls v.6) p = ni n = 1:17 104 holes=cm3 2 (2.9) (2. Let us formulate our results thus far. In other words. the resulting current predominantly consists of electrons. a free electron.2 suggests that a boron (B) atom—with three valence electrons—can form only three complete covalent bonds in a silicon crystal (Fig.1 by six orders of magnitude. We may naturally wonder if it is possible to construct a “p-type” semiconductor. Exercise At what doping level does the hole density drop by three orders of magnitude? This example justiﬁes the reason for calling electrons the “majority carriers” and holes the “minority carriers” in an n-type semiconductor. the table in Fig. 2006] June 30. For example.6 therefore exempliﬁes a p-type semiconductor. then the mobile charge densities are given by Majority Carriers : n ND Minority Carriers : p Ni : D n2 (2. The boron atom is called an “acceptor” dopant.

3 Transport of Carriers Having studied charge carriers and the concept of doping. illustrating the types of charge carriers and their densities in semiconductors.1.12) Since typical doping densities fall in the range of 1015 to 1018 atoms=cm3 . the mechanisms leading to the ﬂow of current. 2.1 Semiconductor Materials and Their Properties 27 Similarly. i.7 summarizes the concepts introduced in this section. for a density of NA ( ni ) acceptor atoms per cubic centimeter: Majority Carriers : p NA Minority Carriers : n Ni : A n2 (2.11) (2.4 Is it possible to use other elements of Fig. 2006] June 30. arsenic (As) is another common dopant.e.7 Summary of charge carriers in silicon. Exercise Can carbon be used for this purpose? Figure 2. the above expressions are quite accurate. . Intrinsic Semiconductor Si Si Covalent Bond Si Valence Electron Extrinsic Semiconductor Silicon Crystal Silicon Crystal N D Donors/cm Si Si Si n−Type Dopant (Donor) Si P e Si 3 N A Acceptors/cm Si Si B Si Free Majority Carrier Si 3 Si Si Si p−Type Dopant (Acceptor) Free Majority Carrier Figure 2. we are ready to examine the movement of charge in semiconductors. 2007 at 13:42 27 (1) Sec. Also.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 2.2 as semiconductors and dopants? Solution Yes. some early diodes and transistors were based on germanium (Ge) rather than silicon. for example.. 2. 2.

p = 480 cm2 =V s. the current is considered to have a direction from B to A.13) v = E. where L is the length. eventually reaching the other end and ﬂowing into the battery.14) where is called the “mobility” and usually expressed in cm2 =V s. to be proportional to the electric ﬁeld strength. accelerated by the ﬁeld and accidentally collide with the atoms in the crystal. since electrons move in a direction opposite to the electric ﬁeld. on the other hand. and hence (2. 2 Basic Physics of Semiconductors Drift We know from basic physics and Ohm’s law that a material can conduct current in response to a potential difference and hence an electric ﬁeld. 6 This phenomenon is analogous to the “terminal velocity” that a sky diver with a parachute (hopefully. Solution 5 The convention for direction of current assumes ﬂow of positive charge from a positive voltage to a negative voltage.4 The ﬁeld accelerates the charge carriers in the material.cls v.16) A uniform piece of n-type of silicon that is 1 m long senses a voltage of 1 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6 We expect the velocity. we must express the velocity vector as ! ve = . R = . Movement of charge carriers due to an electric ﬁeld is called “drift. open) experiences. Of course. forcing some to ﬂow from one end to the other. the charge carriers are E Figure 2. leading to a constant velocity for the carriers.5 ! (2.n E : For holes.”5 Semiconductors behave in a similar manner. 2007 at 13:42 28 (1) 28 Chap. The acceleration due to the ﬁeld and the collision with the crystal counteract. 2006] June 30. the mobility of electrons. ba Edx. is equal to the negative integral of the electric ﬁeld. 000 V/cm and hence v = n E = 1:35 107 cm/s. electrons take 1 m=1:35 107 cm=s = 7:4 ps to cross the 1-m length. if electrons ﬂow from point A to point B . to distance: Vab 4 Recall that the potential (voltage) difference. E . 2.15) ! vh = p E : Example 2. In other words. v .8 Drift in a semiconductor. we have E = V=L. ! (2. V . (2.8. As shown in Fig. Determine the velocity of the electrons. with respect . n = 1350 cm2 =V s. E : v E. Since the material is uniform. E = 10. Thus. and that of holes. Thus. For example in silicon.

. (2.” with the understanding that “current” in fact refers to current density. a hole carries a positive charge of the same value. We may loosely say. Equivalently.9). we write Jn = n E n q. (2. 2007 at 13:42 29 (1) Sec. Since the bar has a width of W . v m/s.18) where Jn denotes the “current density. Let us now reduce Eq. and since W h is the cross section area of the bar.17) where v W h represents the volume.v W h n q. the current passing through a unit cross section area.cls v.9 Current ﬂow in terms of charge density. Since for electrons. considering a cross section of the bar at x = x1 and taking two “snapshots” at t = t1 and t = t1 + 1 second. Eq.e. and negative or positive signs are taken into account properly. 2. 2. (2.18) is modiﬁed to Jtot = n E n q + p E p q = qn n + p pE: (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and is expressed in A=cm2 . we note that the total charge in v meters passes the cross section in 1 second. Now suppose a voltage V1 is applied across a uniform semiconductor bar having a free electron density of n (Fig. v = .n E . and the negative sign accounts for the fact that electrons carry negative charge. “the current is equal to the charge velocity times the charge density. 2006] June 30. we have: I = . In the presence of both electrons and holes. n q denotes the charge density in coulombs. how is the current calculated? We ﬁrst note that an electron carries a negative charge equal to q = 1:6 10. the current is equal to the total charge enclosed in v meters of the bar’s length. Assuming the electrons move with a velocity of v meters W t = t1 L h t = t1 + 1 s x1 V1 x x1 V1 x Figure 2. (2.1 Semiconductor Materials and Their Properties 29 Exercise What happens if the mobility is halved? With the velocity of carriers known.19) (2.19 C.20) This equation gives the drift current density in response to an electric ﬁeld E in a semiconductor having uniform electron and hole densities.17) to a more convenient form.” i.. In other words.

and hence (2.6 In an experiment. as a ﬁeld-dependent parameter.10).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we must modify v = E accordingly. . i (2.cls v. eventually reaching a saturated level. 2 Basic Physics of Semiconductors Example 2. Exercise How should the carrier densities be chosen so that the electron drift current is twice the hole drift current? Velocity Saturation We have thus far assumed that the mobility of carriers in semiconductors is independent of the electric ﬁeld and the velocity rises linearly with E according to v = E . 2006] June 30. 2. n =p = 1350=480 = 2:81. In order to represent velocity saturation.21) n = p : p n We also recall that np = n2 . it is desired to obtain equal electron and hole drift currents. if the electric ﬁeld approaches sufﬁciently high levels. This conﬁrms our earlier notion of majority carriers in 3 semiconductors having typical doping levels of 1015 -1018 atoms=cm . . The expression for must This section can be skipped in a ﬁrst reading.23) (2. As a result. v varies “sublinearly” at high electric ﬁelds.” this effect manifests itself in some modern transistors. Thus. limiting the performance of circuits. v no longer follows E linearly. Called “velocity saturation. In reality.22) r p = n ni p r p n = ni : n p = 1:68ni n = 0:596ni: (2. How should the carrier densities be chosen? Solution We must impose n n = p p. equal electron and hole drift currents can occur for only a very lightly doped material. in silicon. A simple approach is to view the slope. This is because the carriers collide with the lattice so frequently and the time between the collisions is so short that they cannot accelerate much.25) (2.26) Since p and n are of the same order as ni . vsat (Fig.24) For example. 2007 at 13:42 30 (1) 30 Chap. yielding (2.

(2. determine the effective mobility. v ! vsat . In other words. Solution We have E=V L It follows that (2. (2.7 0 E: 1 + 0 E vsat (2. 2007 at 13:42 31 (1) Sec.10 Velocity saturation. we have vsat = b0 .35) . calculate the maximum allowable voltage such that the effective mobility is only 10% lower than 0 . 2006] June 30. If the low-ﬁeld mobility is equal to 1350 cm2 =V s and the saturation velocity of the carriers 107 cm/s..32) = 50 kV=cm: = 0 1 + 0 E vsat 0 = 7:75 = 174 cm2 =V s: (2. where 0 is the “low-ﬁeld” mobility and b a proportionality factor. = 1 +0bE . therefore gradually fall toward zero as E rises. i. v= Example 2. We may consider “effective” mobility at an electric ﬁeld E .34) (2. 2. Also.e.29) and hence b = 0 =vsat .31) (2. but approach a constant value for small E .33) (2.30) A uniform piece of semiconductor 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. Thus.1 Semiconductor Materials and Their Properties Velocity 31 vsat µ2 µ1 E Figure 2.28) v = 1 + 0bE E: Since for E ! 1.27) as the (2.2 m long sustains a voltage of 1 V.

patience is a virtue and we will answer these questions in the next section. the ink molecules tend to ﬂow from a region of high concentration to regions of low concentration. Suppose a drop of ink falls into a glass of water.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. What serves as the source of carriers in Fig.11? Where do the charge carriers go after they roll down to the end of the proﬁle at the far right? And.12. the drop begins to “diffuse. This mechanism is called “diffusion. another mechanism can lead to current ﬂow.36) sat E = 1 v 9 (2.8 A source injects charge carriers into a semiconductor bar as shown in Fig.5 mV. 2006] June 30. 2 Basic Physics of Semiconductors If the mobility must remain within 10% of its low-ﬁeld value. the carriers move toward regions of low concentration. . thereby carrying an electric current so long as the nonuniformity is sustained.38) = 823 V=cm: 10. why should we care?! Well. Explain how the current ﬂows. 2007 at 13:42 32 (1) 32 Chap. 1 + 0 E vsat 0 (2. Figure 2.” that is.” A similar phenomenon occurs if charge carriers are “dropped” (injected) into a semiconductor so as to create a nonuniform density.11 Diffusion in a semiconductor.4 cm = 16:5 mV.11 conceptually illustrates the process of diffusion. Exercise At what voltage does the mobility fall by 20%? Diffusion In addition to drift.cls v. a nonuniform charge proﬁle is created along the x-axis. A source on the left continues to inject charge carriers into the semiconductor. 2. 2. and the carriers continue to “roll down” the proﬁle. then 0:90 = and hence 0 .2 m experiences such a ﬁeld if it sustains a voltage of 823 V=cm 0:2 This example suggests that modern (submicron) devices incur substantial velocity saturation because they operate with voltages much greater than 16. Semiconductor Material Injection of Carriers Nonuniform Concentration Figure 2. A device of length 0. Even in the absence of an electric ﬁeld. Introducing a high local concentration of ink molecules. The reader may raise several questions at this point.37) (2. Diffusion is therefore distinctly different from drift. most importantly. Example 2.

We call dn=dx the concentration “gradient” with respect to x.43) . we can write: I dn .39) where n denotes the carrier concentration at a given point along the x-axis. we normalize the diffusion current to the cross section area.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exercise Is KCL still satisﬁed at the point of injection? Our qualitative study of diffusion suggests that the more nonuniform the concentration. leading to current ﬂow from the source toward the two ends of the bar.cls v. obtaining the current density as Jn = qDn dn : dx Similarly.41) where Dn is a proportionality factor called the “diffusion constant” and expressed in cm2 =s. assuming current ﬂow only in the x direction. For example.39) can be written as I Aq dn : dx Thus. If each carrier has a charge equal to q . Eq.42) dp Jp = . 2007 at 13:42 33 (1) Sec. a gradient in hole concentration yields: (2. in intrinsic silicon.qDp dx : (2. More speciﬁcally. the larger the current.12 Injection of carriers into a semiconductor. dx (2. (2.1 Semiconductor Materials and Their Properties Injection of Carriers 33 0 x Figure 2. dx (2. Solution In this case.40) I = AqDn dn . As with the convention used for the drift current. (2. two symmetric proﬁles may develop in both positive and negative directions along the x-axis. 2006] June 30. and the semiconductor has a cross section area of A. and Dp = 12 cm2 =s (for holes). 2. Dn = 34 cm2 =s (for electrons).

2 Basic Physics of Semiconductors With both electron and hole concentration gradients present. 2007 at 13:42 34 (1) 34 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. Dp dx : dx Example 2. the total current density is given by dp Jtot = q Dn dn .9 .cls v.

13).11 again. Example 2.10 Repeat the above example but assume an exponential gradient (Fig. Exercise Repeat the above example for holes.46) = . Suppose the electron concentration is equal to N at x = 0 and falls linearly to zero at x = L (Fig.47) .44) Consider the scenario depicted in Fig.qDn N : L The current is constant along the x-axis.45) (2.14): N Injection 0 L x Figure 2. 2. N Injection 0 L x Figure 2. all of the electrons entering the material at x = 0 successfully reach the point at x = L.14 Current resulting from an exponential diffusion proﬁle. this observation prepares us for the next example. Solution We have Jn = qDn dn dx (2. Determine the diffusion current. 2..x . nx = N exp . While obvious.13 Current resulting from a linear diffusion proﬁle. i. L d (2. (2. 2.e.

(1) The device ﬁnds application in many electronic systems.7 Solution We have Jn = qDn dn (2.2 PN Junction 35 where Ld is a constant. It can be proved that and D are related as: D = kT : q (2.48) dx = . some electrons vanish while traveling from x = 0 to the right.2 We begin our study of semiconductor devices with the pn junction for three reasons. (2) The pn junction is among the simplest semiconductor devices. That is. What happens to these electrons? Does this example violate the law of conservation of charge? These are important questions and will be answered in the next section. .50) Called the “Einstein Relation. Exercise At what value of x does the current density drop to 1% its maximum value? Einstein Relation Our study of drift and diffusion has introduced a factor for each: n (or p ) and Dn (or Dp ).. 2006] June 30.qDn N exp . respectively. [1].x : (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2.49) Ld Ld Interestingly.cls v.15 Summary of drift and diffusion mechanisms. 2. in adapters that charge the batteries of cellphones.” this result is proved in semiconductor physics texts. e.15 summarizes the charge transport mechanisms studied in this section. the current is not constant along the x-axis.g.g. Drift Current Diffusion Current E Jn = q n µn E Jp = q p µp E dn dx dp Jp = − q Dp dx Jn = q Dn Figure 2. e. Note that kT=q 26 mV at T = 300 K. thus providing a 7 The factor PN Junction Ld is necessary to convert the exponent to a dimensionless quantity. 2007 at 13:42 35 (1) Sec.. Figure 2.

16 and called a “pn junction. 2 Basic Physics of Semiconductors good entry point into the study of the operation of such complex structures as transistors. The sharp concentration gradient for both electrons and holes across the junction leads to two large diffusion currents: electrons ﬂow from the n side to the p side. We have thus far seen that doping produces free electrons or holes in a semiconductor. We also use the term “diode” to refer to pn junctions. The following outline shows our thought process. the ”cathode.18. i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 2. PN Junction in Equilibrium Let us ﬁrst study the pn junction with no external connections. we express the concentrations of holes and electrons on the p side Solution .12). An interesting situation arises if we introduce n-type and p-type dopants into two adjacent sections of a piece of semiconductor. indicating that our objective is to develop circuit models that can be used in analysis and design. a large excess of electrons. the terminals are open and 2. 2007 at 13:42 36 (1) 36 Chap. recognizing that one side contains a large excess of holes and the other.11 = 51015 cm. From Eqs.11) and (2.17 Outline of concepts to be studied. Since we must deal with both electron and hole concentrations on each side of the junction. Depicted in Fig. A pn junction employs the following doping levels: NA = 1016 cm. We begin by examining the interface between the n and p sections.” respectively.3 .2.” While seemingly of no practical value. we study the properties and I/V characteristics of pn junctions.” this structure plays a fundamental role in many semiconductor devices.e.1 no voltage is applied across the device.. The p and n sides are called the “anode” and n p Cathode Anode Si Si P e Si B Si (a) Si Si Si Si (b) Figure 2. and holes ﬂow in the opposite direction. We say the junction is in “equilibrium. In this section. 2.cls v. 2.3 and ND Determine the hole and electron concentrations on the two sides. (2. this condition provides insights that prove useful in understanding the operation under nonequilibrium as well. we introduce the notations shown in Fig. (3) The pn junction also serves as part of transistors. PN Junction in Equilibrium Depletion Region Built−in Potential PN Junction Under Reverse Bias Junction Capacitance PN Junction Under Forward Bias I/V Characteristics Figure 2. and an electric ﬁeld or a concentration gradient leads to the movement of these charge carriers. 2006] June 30.16 PN junction.

However.51) (2. but they must eventually decay to zero.3 (2. . nn : Concentration of electrons on n side pn : Concentration of holes on n side pp : Concentration of holes on p side np : Concentration of electrons on p side respectively as: pp NA np Ni n2 = 1016 cm.3 (2.3 : A Similarly.58) (2. This is because.3 2 = 1:081016 cmcm .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We must now answer an important question: what stops the diffusion currents? We may postulate that the currents stop after enough free carriers have moved across the junction so as to equalize the concentrations on the two sides.3 1:1 104 cm. another effect dominates the situation and stops the diffusion currents well before this point is reached. if the terminals are left open (equilibrium condition).59) (2. 2006] June 30. the concentrations on the n side are given by nn ND pn N i n2 = 5 1015 cm.18 .55) 1010 .53) (2.3 2 = 1:08 1015 cm. the device cannot carry a net current indeﬁnitely.2 PN Junction n Majority Carriers 37 p pp np Majority Carriers nn pn Minority Carriers Minority Carriers Figure 2.56) (2.3 5 = 2:3 104 cm.52) (2.60) 1010 cm.cls v.57) (2.54) (2. 2007 at 13:42 37 (1) Sec.3 : D Note that the majority carrier concentration on each side is many orders of magnitude higher than the minority carrier concentration on either side. 2. The diffusion currents transport a great deal of charge from each side to the other. Exercise Repeat the above example if ND drops by a factor of four.

the junction is suddenly formed at t = 0. we can say. 2. Alternatively. Thus.8 Interestingly.cls v.21. the magnitude of E rises as x approaches zero.19 Evolution of charge concentrations in a pn junction. in equilibrium.12 Solution 8 The direction of the electric ﬁeld is determined by placing a small positive test charge in the region and watching how it moves: away from positive charge and toward negative charge.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. an electric ﬁeld emerges as shown in Fig. we note that the absence of net charge yields E = 0.19.e.20 Electric ﬁeld in a pn junction. Example 2. 2. with the formation of the depletion region. each positive donor ion contributes to the electric ﬁeld. the negative and positive charge exactly cancel each other and E = 0. In the junction shown in Fig. Now recall from basic physics that a particle or object carrying a net (nonzero) charge creates an electric ﬁeld around it. Sketch the electric ﬁeld as a function of x. 2. and the diffusion currents continue to expose more ions as time progresses. At x . the negative acceptor atoms begin to contribute negatively to the ﬁeld.. left to right whereas the concentration gradients necessitate the ﬂow of holes from right to left (and electrons from left to right). 2 Basic Physics of Semiconductors To understand this effect.b. .e.. E falls.e. the depletion region has a width of b on the n side and a on the p side. 2006] June 30. In this illustration. i.20. Consequently.” t=0 n − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − t = t1 p n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − t= p + + + + + + + + + + + + + + + + + + + + + + + + + + + + n − − − − − − + − − −+ − − − + − − − − − − + − − − − − − + + + + + + − − − − − − − − − − + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p + + + + + + + + + + + + + + + + + + + + + + + + Free Free Electrons Holes Positive Negative Donor Acceptor Ions Ions Depletion Region Figure 2. 2007 at 13:42 38 (1) 38 Chap. a positive ion is left behind. the drift currents resulting from the electric ﬁeld exactly cancel the diffusion currents due to the gradients. We therefore surmise that the junction reaches equilibrium once the electric ﬁeld is strong enough to completely stop the diffusion currents. the immediate vicinity of the junction is depleted of free carriers and hence called the “depletion region. the junction evolves with time as conceptually shown in Fig. As we pass x = 0.. Beginning at x . i. At x = a. the ﬁeld tends to force positive charge ﬂow from n − − − − − − − − − − − − − − − − − − − − − − − − E + + + + + + + + + + − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + Figure 2.b. i. we recognize that for every electron that departs from the n side.

we can compute this potential. we may be tempted to write: jIdrift. (2.2 PN Junction n − − − − − − − − − − N − − D − − − − − − − − − − E + + + + + + + + + + 0 − − − − − − − − − − 39 p + + + + + + + + + + + NA + + + + + + + + + + a x −b E −b 0 a x Figure 2. 2007 at 13:42 39 (1) Sec.63) Built-in Potential The existence of an electric ﬁeld within the depletion region suggests that the junction may exhibit a “built-in potential.62) can be written as dp qp pE = qDp dx . respectively.66) .p p dV = Dp dx : dx Dividing both sides by p and taking the integral.21 Electric ﬁeld proﬁle in a pn junction.61) where the subscripts p and n refer to holes and electrons. however. and since (2.65) . allows an unrealistic phenomenon: if the number of the electrons ﬂowing from the n side to the p side is equal to that of the holes going from the p side to the n side.64) dp . plot the potential as a function of x.” In fact.p Zx x1 2 dV = Dp Z pp dp pn p.cls v.p j = jIdi . From our observation regarding the drift and diffusion currents under equilibrium. Since the electric ﬁeld E = . then each side of this equation is zero while electrons continue to accumulate on the p side and holes on the n side. using (2.dV=dx. 2006] June 30. we have (2. This condition.n j = jIdi .p + Idi . we obtain (2.63).p + Idrift.n j = jIdi .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.n j.62) (2. Exercise Noting that potential voltage is negative integral of electric ﬁeld with respect to distance.n j: (2. and each current term contains the proper polarity.62) or (2. We must therefore impose the equilibrium condition on each carrier: jIdrift. 2.p j jIdrift. (2.

(2.22 Carrier proﬁles in a pn junction.1 that ni T Example 2. 2 p Basic Physics of Semiconductors pp np x1 x2 x Figure 2. this equation plays a central role in many semiconductor devices.3 .68) Exercise Writing Eq. 2. (2.10) for pp and pn yields V0 = kT ln NA ND : q n2 i (2. Recall from Example 2.64) for electron drift and diffusion currents. Finally. we can replace Dp =p with kT=q : p jV0 j = kT ln pp : q n (2. using (2.71) 1016 4 16 V0 26 mV ln 2 1:08 1010 210 768 mV: Exercise By what factor should ND be changed to lower V0 by 20 mV? . Eq.70) (2.50). Determine the Solution = 300 K = 1:08 1010 cm. (2.69) Expressing the built-in potential in terms of junction parameters. Also. from Einstein’s relation.3 and ND built-in potential at room temperature (T = 300 K). (2. 2006] June 30. respectively (Fig. and carrying out the integration. p V x2 .3 .11) and (2. Dp ln pp : p n where pn and pp are the hole concentrations at x1 and x2 .22). V x1 = .cls v. derive an equation for V0 in terms of nn and np . A silicon pn junction employs NA = 2 1016 cm.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 40 (1) 40 n nn pn Chap. Thus.67) The right side represents the voltage difference developed across the depletion region and will be denoted by V0 . Thus.13 = 4 1016 cm.

9 As explained in Section 2. more positive charge appears on the n side and more negative charge on the p side.2 PN Junction 41 Equation (2. which exhibits no tendency for diffusion and hence no need to create a built-in voltage. we can now study its behavior under more 2.23. We wish to reexamine the results obtained in equilibrium for the case of reverse bias. Let us ﬁrst determine whether the external voltage enhances the built-in electric ﬁeld or opposes it. PN Junction Under Reverse Bias Having analyzed the pn junction in equilibrium.”).72) (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 2. E is directed from the n side to the p side. in fact.cls v.9 With no current conduction. How is that possible? We observe that the builtin potential is developed to oppose the ﬂow of diffusion currents (and is. How much does V0 change if NA or ND is increased by one order of magnitude? Example 2.2. sometimes called the “potential barrier.14 Solution We can write V0 = VT ln 10NA2 ND . The junction carries no net current (because its terminals remain open).74) Exercise How much does V0 change if NA or ND is increased by a factor of three? An interesting question may arise at this point. . We will study the concept of biasing extensively in this and following chapters.2. a reverse-biased pn junction does not seem particularly useful. a higher electric ﬁeld can be sustained only if a larger amount of ﬁxed charge is provided.23. thus prohibiting the ﬂow of current. the junction carries a negligible current under reverse bias. as VB increases.69) reveals that V0 is a weak function of the doping levels. the barrier rises even higher than that in equilibrium. VT ln NAn2ND n = VT ln 10 60 mV at T = 300 K: i i (2. In other words. We note that in Fig. where the voltage source makes the n side more positive than the p side. but it sustains a voltage. requiring that more acceptor and donor ions be exposed and. However. 2007 at 13:42 41 (1) Sec. VR enhances the ﬁeld. Used as a noun or a verb. What happens to the diffusion and drift currents? Since the external voltage has strengthened the ﬁeld. the current is not exactly zero. 2.73) (2. We say the junction is under “reverse bias” to emphasize the connection of the positive voltage to the n terminal. 2. But.2 interesting and useful conditions. the depletion region be widened. therefore. This phenomenon is in contrast to the behavior of a uniform conducting material. ! Since under equilibrium. the term “bias” indicates operation under some “desirable” conditions. an important observation will prove otherwise.3. Let us begin by applying an external voltage across the device as shown in Fig.

75) . 2. 2.24 Reduction of junction capacitance with reverse bias. The reader may still not ﬁnd the device interesting.24(a)]. 2.24(a) can be drawn as in Fig. we can view the conductive n and p sections as the two plates of the capacitor.24(b) for increasing values of VR . as VR increases. Returning to Fig. we recognize that. 2 Basic Physics of Semiconductors + + + + + + + + + + − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + p + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + − − − − − − − − − − − − − − − VR Figure 2. revealing that the capacitance of the structure decreases as the two plates move away from each other. The junction therefore displays a voltage-dependent capacitance. In essence. VR V0 . After all. It can be proved that the capacitance of the junction per unit area is equal to Cj = r Cj0 1 .cls v. since any two parallel plates can form a capacitor. V R2 + + + + + + + + + + + + + + + − − − − − − − − − − − − − − − n − − − − − − − − − − − − − − − − − − − − − − − − − − − − V R1 + + + + + + + + + + − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + + + + + n − − − − − − − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + − − − − − V R1 (a) V R2 (more negative than V R1 ) (b) Figure 2. so does the width of the depletion region. the use of a pn junction for this purpose is not justiﬁed. But.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Thus. the device operates as a capacitor [Fig. 2006] June 30.23 PN junction under reverse bias. 2. reverse-biased pn junctions exhibit a unique property that becomes useful in circuit design. (2. 2007 at 13:42 42 (1) 42 n − − − − − − − − − − − − − − − − − − − − − − − − n − − − − − − − − − − − − − − − − Chap. the conceptual diagram of Fig. We also assume the charge in the depletion region equivalently resides on each plate.23. That is.

For VR (2. we have r q NN 1 D Cj0 = si N A N V 2 A+ D 0 = 2:65 10. (2. and 0 the dielectric constant of vacuum (8:85 10. we deal with very small devices and may rewrite this result as Cj0 = 0:265 fF=m2 .19 C.14 F/cm).2 PN Junction 43 where Cj 0 denotes the capacitance corresponding to zero bias (VR = 0) and V0 is the built-in potential [Eq. A pn junction is doped with NA = 2 1016 cm.) The value of Cj 0 is in turn given by r q NN Cj0 = si A D 2 NA + ND V0 1. 2. for VR (2.8 F=cm2 : (2.. 2. (2.15 = 9 1015 cm.76) where si represents the dielectric constant of silicon and is equal to 11:7 8:85 10. 2006] June 30.3. Cj indeed decreases as VR increases.3 and ND capacitance of the device with (a) VR = 0 and VR = 1 V.25 Junction capacitance under reverse bias.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. where r is the “relative” dielectric constant and a dimensionless factor (e.69)].81) = 1 V.14 F/cm.77) (2.7). 2007 at 13:42 43 (1) Sec. 1 + VR V 0 (2.80) In microelectronics.15 F. Cj 0 VR Figure 2.25. Determine the Solution We ﬁrst obtain the built-in potential: V0 = VT ln NA ND n2 = 0:73 V: i Thus.78) = 0 and q = 1:6 10. Example 2. 11.83) 10 The dielectric constant of materials is usually written in the form r 0 .10 Plotted in Fig.79) (2.g.cls v. . where 1 fF (femtofarad) = 10.82) Cj = r Cj 0 = 0:172 fF=m2 : (2. (This equation assumes VR is negative for reverse bias.

85) (2. and the junction area is 2000 m2 . Thus. yielding a total device capacitance of Cj. 2007 at 13:42 44 (1) 44 Chap.15.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.1 . 2 Basic Physics of Semiconductors Exercise Repeat the above example if the donor concentration on the results in the two cases. Oscillator C VR L Figure 2. N side is doubled. Nonetheless. as demonstrated by the following example.16 A cellphone incorporates a 2-GHz oscillator whose frequency is deﬁned by the resonance frequency of an LC tank (Fig. a voltage-dependent capacitor leads to interesting circuit topologies. the resonance frequency is equal to fres = 21 p 1 : LC At VR (2. Solution Recall from basic circuit theory that the tank “resonates” if the impedances of the inductor and the capacitor are equal and opposite: jL!res = . If the tank capacitance is realized as the pn junction of Example 2. 2.26).84) = 0.87) Cj.jC!res . Compare the The variation of the capacitance with the applied voltage makes the device a “nonlinear” capacitor because it does not satisfy Q = CV . Example 2. we obtain (2.tot VR = 2 V = r Cj0 1 + 0:2 73 = 274 fF: 2000 m2 (2. Assume the circuit operates at 2 GHz at a reverse voltage of 0 V. (2.86) L = 11:9 nH: If VR goes to 2 V.88) (2.26 Variable capacitor used to tune an oscillator. Cj = 0:265 fF/m2 .tot VR = 0 = 0:265 fF=m2 2000 m2 = 530 fF: Setting fres to 2 GHz.cls v. calculate the change in the oscillation frequency while the reverse voltage goes from 0 to 2 V.89) .

tends to create a ﬁeld directed from the p side toward the n side—opposite to the built-in ﬁeld that was developed to stop the diffusion currents. we note that the potential barrier developed in the depletion region determines the device’s desire to conduct. the external voltage. n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − PN Junction Under Forward Bias p + + + + + + + + + + + + + + + + + + + + + + + + + + + + VF Figure 2. From our study of the device in equilibrium and reverse bias. 2.75). Exercise Some wireless systems operate at 5. We therefore surmise that VF in fact lowers the potential barrier by weakening the ﬁeld.cls v.” We also wish to compute the resulting current in terms of the applied voltage and the junction parameters.84). In forward bias. a reverse-biased pn junction carries a negligible current but exhibits a voltagedependent capacitance.27 PN junction under forward bias. 2006] June 30. This condition is called “forward bias.3 Our objective in this section is to show that the pn junction carries a current if the p side is raised to a more positive voltage than the n side (Fig. a current ﬂows through the diode that is proportional to the light intensity. the electrons are attracted to the positive battery terminal and the holes to the negative battery terminal. VF . electrons are dislodged from their covalent bonds and hence electron-hole pairs are created.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Note that we have tacitly developed a circuit model for the device under this condition: a simple capacitance whose value is given by Eq. we have fres VR = 2 V = 2:79 GHz: (2.” 2. (2. ultimately arriving at a circuit model. 2. etc. We say the pn junction operates as a “photodiode. (2.90) An oscillator whose frequency can be varied by an external voltage (VR in this case) is called a “voltage-controlled oscillator” and used extensively in cellphones.2 GHz. personal computers. In summary. 2007 at 13:42 45 (1) Sec. assuming the junction area is still 2000 m2 but the inductor value is scaled to reach 5. With a reverse bias. thus allowing greater diffusion currents.2. Repeat the above example for this frequency. As a result.2 PN Junction 45 Using this value along with L = 11:9 nH in Eq.27).2 GHz. . microprocessors. Another interesting application of reverse-biased diodes is in digital cameras (Chapter 1). If light of sufﬁcient energy is applied to a pn junction.

f pn. for the electron concentration on the p side: np ND exp VF . 2007 at 13:42 46 (1) 46 Chap.f np.e pp. 1: VT exp V VT (2.e pn. As the junction goes from equilibrium to forward bias. (b) the “thermal voltage” ( 26 mV at T = 300 K).f to be much higher than pn. leading to a proportional change in the diffusion currents.94) NA 0 exp VF . (2.96) .f n p pp.91) = kT=q is called VF (a) Figure 2. 2006] June 30.f = where the subscript f denotes forward bias. VF . we begin with Eq.92) pn = pn.e nn.f pn.f V0 . 2 Basic Physics of Semiconductors To derive the I/V characteristic in forward bias.e np.e (it can be proved that pp.f pp. the minority carrier concentration on the p side rises rapidly with the forward bias voltage while the majority carrier concentration remains relatively constant. (2. we expect pn.28(b) illustrates the results of our analysis thus far. Since the exponential denominator drops considerably. 2.f .e = V0 .95) Similarly. np and pn increase dramatically.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.68) for the built-in voltage and rewrite it as pn.e = pp.e 0 . Figure 2.11 We can express the change in the hole concentration on the n side as: pp.28(a)] and VT n nn.f (2. pn.28 Carrier proﬁles (a) in equilibrium and (b) under forward bias.cls v. VF : exp V T (2.e NA ). This statement applies to the n side as well.e p pp. exp V0 exp V VT T (2.93) (2.e np. V exp V T where the subscript e emphasizes equilibrium conditions [Fig. In forward bias. In other words. 1: V VT exp V 0 T 11 The width of the depletion region actually decreases in forward bias but we neglect this effect here.f pp. the potential barrier is lowered by an amount equal to the applied voltage: pn.

Using q Example 2. it can be proved that [1] (2. Determine IS for the junction of Example 2.15 A.2)]. implying that the charge carriers do not ﬂow deep into the p and n sides and hence no net current results! Thus. Exercise What junction area is necessary to raise IS to 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.17 = 300K if A = 100 m2 . such a scenario would suggest that electrons continue to ﬂow from the n side to the p side. V T (2. A similar situation exists for holes. 1: V V VT VT exp V 0 exp V 0 T T Itot = IS exp VF . A is the cross section area of the device. Dn = 34 cm2 =s. This observation reminds us of Example 2.. 2. .” respectively. 2007 at 13:42 47 (1) Sec. what happens to the carriers and how can the current remain constant along the x-axis? Interestingly.17 A: (2. 1 mA) for Itot . Ln = 20 m.69) indicates that expV0 =VT = NA ND =n2 .g. An interesting question that arises here is: are the minority carrier concentrations constant along the x-axis? Depicted in Fig.19 C. 2. but exhibit no tendency to go beyond x = x2 because of the lack of a gradient. the minority carrier concentrations must vary as shown in Fig. 2. 1.99) In this equation. Itot NA exp VF .98) must assume very large values so as to yield a useful amount (e. (2. = 1:6 10.2 PN Junction 47 Note that Eq. which are abundant in this region.13 at T and Lp = 30 m.29(a). as the electrons enter the p side and roll down the gradient. the exponential term in Eq.100) Since IS is extremely small. ni = 1:08 1010 electrons=cm3 [Eq. Diffusion lengths are typically in the range of tens of micrometers. (2. we have Solution IS = 1:77 10. and Dp = 12 cm2 =s. respectively. Note that the ﬁrst and second terms in the parentheses correspond to the ﬂow of electrons and holes.97) Indeed.29(b) so that diffusion can occur.. i. 2006] June 30.10 and the question raised in conjunction with it: if the minority carrier concentration falls with x. they gradually recombine with the holes.e. i The increase in the minority carrier concentration suggests that the diffusion currents must rise by a proportional amount above their equilibrium value. (2.98) where IS is called the “reverse saturation current” and given by n IS = Aqn2 NDL + NDp : i A n D Lp (2. and Ln and Lp are electron and hole “diffusion lengths. 1 + ND exp VF .cls v.

At each point along the x-axis.f x + + + + pp. V T (2. then expVD =VT 1 and ID . on the other hand.30 Minority and majority carrier currents. 2.29 (a) Constant and (b) variable majority carrier proﬁles ioutside the depletion region. It can be proved that Eq. i. 2006] June 30. In reverse bias. (Why is this expected?) As VD becomes positive and exceeds several VT .4 I/V Characteristics Let us summarize our thoughts thus far. 1. the holes entering the n side recombine with the electrons. prohibiting current ﬂow. We hereafter assume expVD =VT 1 in the forward bias region.f pn.30). 2 Basic Physics of Semiconductors n Electron Flow − ++ − + −− + Hole Flow p n Electron Flow − ++ − + − Hole Flow p nn.f nn.f pp. 2007 at 13:42 48 (1) 48 Chap.f − x1 x2 VF (a) x1 x2 VF (b) x Figure 2.101) where ID and VD denote the diode current and voltage.2. the external voltage opposes the built-in potential. it is primarily comprised of majority carriers (Fig.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.101) also holds in reverse bias.. the exponential term grows rapidly and ID IS expVD =VT .IS : (2. If VD 0 and jVD j reaches several VT . the applied voltage enhances the ﬁeld. VD = 0 yields ID = 0. respectively.f pn.e. 2. for negative VD . (2. but towards the far contacts. Similarly. We hereafter write the junction equation as: ID = IS exp VD .f np. raising the diffusion currents substantially.102) . the two components add up to Itot . the current consists of mostly minority carriers. As expected. In forward bias.f − − − np. Thus. in the immediate vicinity of the depletion region. n −− − − −− − − −− ++ + + + + ++ ++ p −− − − − − −− −− + ++ + ++ + + ++ x VF Figure 2.

” Example 2.tot VD = 800 mV = 82 A: (2.2 PN Junction 49 Figure 2.” Note that IS and hence the junction current are proportional to the device cross section area [Eq.103) (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. view the current under reverse bias as “leakage. A n p 2A n n A VF VF p p Figure 2. 2006] June 30. Example 2.17 A for each junction.104) = 800 mV: ID. From Example 2. Determine the forward bias current of the composite device for VD = 300 mV and 800 mV at T = 300 K. We therefore Reverse Bias Forward Bias ID VD VT VD I S exp −IS Figure 2. IS Solution = 1:77 10.31 I-V characteristic of a pn junction.17. (2.105) Exercise How many of these diodes must be placed in parallel to obtain a current of 100 A with a . 2.31 plots the overall I/V characteristic of the junction.32 employs the doping levels described in Example 2.13.18 Each junction in Fig. 1 VT = 3:63 pA: Similarly. two identical devices placed in parallel (Fig.99)].32 Equivalence of parallel devices to a larger device. For example.17 indicates that IS is typically very small. the total current is equal to ID. 2.cls v.tot VD = 300 mV = 2IS exp VD . 2007 at 13:42 49 (1) Sec.32) behave as a single junction with twice the IS . Thus. 2. for VD (2. revealing why IS is called the “reverse saturation current.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.e. (a) Determine the change in ID if VD is maintained constant.111) (b) From the above example. VT ln 10: IS (2.20 The cross section area of a diode operating in the forward bias region is increased by a factor of 10..108) (2. 2006] June 30. More generally.113) .cls v. Suppose we wish to increase the current by a factor of 10.112) (2. meaning VD changes by 60 mV for a decade (tenfold) change in ID .107) (2. 2007 at 13:42 50 (1) 50 Chap. VD1 : V = V ln 10ID D1 T VD = VT ln ID : I S (2. (a) Since IS Solution A. How much change in VD is required? Solution Let us ﬁrst express the diode voltage as a function of its current: We deﬁne I1 = 10ID and seek the corresponding voltage. the new current is given by ID1 = 10IS exp VD VT = 10ID : I VD1 = VT ln 10D IS = VT ln ID .106) = VT ln ID + VT ln 10 IS = VD + VT ln 10: IS (2.109) Thus. ID IS expVD =VT ]. Example 2. Assume ID IS expVD =VT . the diode voltage must rise by VT ln 10 60 mV (at T = 300 K) to accommodate a tenfold increase in the current. Exercise By what factor does the current change if the voltages changes by 120 mV? Example 2.110) (2. (2. We say the device exhibits a 60-mV/decade characteristic. (b) Determine the change in VD if ID is maintained constant. 2 Basic Physics of Semiconductors voltage of 750 mV. an n-fold change in ID translates to a change of VT ln n in VD .19 A diode operates in the forward bias region with a typical current level [i.

Exercise A diode in forward bias with ID IS expVD =VT undergoes two simultaneous changes: the current is raised by a factor of m and the area is increased by a factor of n. Reverse Bias ID V D. the above examples imply that the diode voltage is a relatively weak function of the device current and cross section area. Simple models allow a quick. Consider the circuit of Fig. a tenfold increase in the device area lowers the voltage by 60 mV if ID remains constant. considering the device fully off if VD 800 mV. 2006] June 30.34.on because we assume the forward-biased diode operates as an ideal voltage source.16 A and (b) a constant-voltage model with VD. we construct a “physics-based” circuit model. different levels of accuracy) prove essential to the analysis and design of circuits. Note that the current goes to inﬁnity as VD tends to exceed VD.on Forward Bias V D. thus arriving at progressively simpler representations.cls v. we often approximate the forward bias voltage by a constant value of 800 mV (like an ideal battery).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.21 . The resulting characteristic is illustrated in Fig. We say the junction operates as an open circuit if VD VD. and we seek to approximate the resulting model. VD falls in the range of 700 .800 mV. only the switch turns on and the battery always resides in series with the switch.33(b). the voltage source placed in series with the switch in the off condition helps simplify the analysis of circuits: we can say that in the transition from off to on. Device models having different levels of complexity (and. Determine the change in the device voltage. Fortunately.on (a) VD (b) V D.on . 2007 at 13:42 51 (1) Sec. while more accurate models reveal the true performance. why did we study the physics of semiconductors and pn junctions in such detail? The developments in this chapter are representative of our treatment of all semiconductor devices: we carefully analyze the structure and physics of the device to understand its operation. Example 2. 2.on and as a constant voltage source if we attempt to increase VD beyond VD. With typical current levels and areas.2 PN Junction 51 Thus. Calculate IX for VX = 3 V and VX = 1 V using (a) an exponential model with IS = 10. A number of questions may cross the reader’s mind at this point. intuitive understanding of the operation of a complex circuit. Constant-Voltage Model The exponential I/V characteristic of the diode results in nonlinear equations. For this reason. why do we subject the diode to such a seemingly inaccurate approximation? Second.on Figure 2. making the analysis of circuits quite difﬁcult. 2.33 Constant-voltage diode model. Neglecting the leakage current in reverse bias. inevitably.on . we derive the circuit model shown in Fig. First. 2. 2.on = 800 mV.33(a) with the turn-on voltage denoted by VD. if we indeed intend to use this simple approximation. While not essential.

(b) A constant-voltage model readily IX = 2:2 mA for VX = 3 V IX = 0:2 mA for VX = 1 V: (2.122) We note that the value of IX rapidly converges.117) (2. 2 Basic Physics of Semiconductors VX D1 R 1 = 1 kΩ VD Figure 2. determine the new value of VD from VD = VT lnIX =IS and iterate.34 Simple circuit using a diode.cls v. VD . Following the same procedure for VX have = 1 V.116) (2. 0:75 V = 1k = 2:25 mA: Thus.120) IX = 3 V .125) (2.115) This equation must be solved by iteration: we guess a value for VD .k :75 V 1 = 0:25 mA. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.121) (2. we (2. we can obtain a more accurate value for IX : (2.114) (2. IX = VX R VD 1 3 V .118) VD = VT ln IX IS = 799 mV: With this new value of VD . compute the corresponding IX from IX R1 = VX . 0:799 V 1k = 2:201 mA: 0 IX = 1 V . (2. (2.123) (2. 2007 at 13:42 52 (1) 52 IX Chap.119) (2. we have VX = IX R 1 + VD VD = VT ln IIX : S (2.124) which yields VD gives = 0:742 V and hence IX = 0:258 mA.126) . Let us guess VD = 750 mV and hence . (a) Noting that ID Solution = IX .

provide no loosely-connected carriers. enormous current is observed. but it is obtained with much less computational effort than that in part (a). This section can be skipped in a ﬁrst reading. Figure 2. the electrons are accelerated by the ﬁeld and swept to the n side of the junction. thus lowering the resistance of the air and creating a tremendous current. Called the “Zener effect. . a high electric ﬁeld in this region may impart enough energy to the remaining covalent electrons to tear them from their bonds [Fig. 2. A common example is lightning.35 plots the device I/V characteristic.76) translates to high doping levels on both sides of the junction (why?).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.36(a)]. 2. relatively constant current in reverse bias.” 2. In order to create such high ﬁelds with reasonable voltages. Once freed. 2. 2007 at 13:42 53 (1) Sec. This effect occurs at a ﬁeld strength of about 106 V/cm (1 V/m). The breakdown resulting from a high voltage (and hence a high electric ﬁeld) can occur in any material.35 Reverse breakdown characteristic. which from Eq. 2006] June 30. 2. ID V BD VD Breakdown Figure 2. (2.3 Reverse Breakdown 53 The value of IX incurs some error. as the reverse voltage across the device increases. The breakdown phenomenon in pn junctions occurs by one of two possible mechanisms: “Zener effect” and “avalanche effect.” this type of breakdown appears for reverse bias voltages on the order of 3-8 V.31 that the pn junction carries only a small. displaying this effect.3. eventually “breakdown” occurs and a sudden.1 Zener Breakdown The depletion region in a pn junction contains atoms that have lost an electron or a hole and. Exercise Repeat the above example if the cross section area of the diode is increased by a factor of 10.3 Reverse Breakdown Recall from Fig. a narrow depletion region is required. therefore. However. in which case the electric ﬁeld in the air reaches such a high level as to ionize the oxygen molecules. However.

For example. in an n-type material. The Zener and avalanche breakdown effects do not damage the diodes if the resulting current remains below a certain limit given by the doping levels and the geometry of the junction. An interesting contrast between Zener and avalanche phenomena is that they display opposite temperature coefﬁcients (TCs): VBD has a negative TC for Zener effect and positive TC for avalanche effect. 2. i Charge carriers move in semiconductors via two mechanisms: drift and diffusion. a “hole” is left behind. Both the breakdown voltage and the maximum allowable reverse current are speciﬁed by diode manufacturers. i n ND and hence p n2 =ND . .5-V rating ﬁnd application in some voltage regulators. semiconductors are “doped” with certain impurities. Even though the leakage current is very small. (b) avalanche effect.4 Chapter Summary Silicon contains four atoms in its last orbital. The two TCs cancel each other for VBD 3:5 V.2 Avalanche Breakdown Junctions with moderate or low doping levels ( 1015 cm3 ) generally exhibit no Zener breakdown. 2 Basic Physics of Semiconductors n Si E Si Si e Si Si Si e Si p n e e e e e E p e e e e Si e e Si Si VR (a) VR (b) Figure 2. For this reason. Called “impact ionization. each carrier entering the depletion region experiences a very high electric ﬁeld and hence a large acceleration. For example. Zener diodes with 3. 2.” this phenomenon can lead to avalanche: each electron freed by the impact may itself speed up so much in the ﬁeld as to collide with another atom with sufﬁcient energy. addition of phosphorous to silicon increases the number of free electrons because phosphorous contains ﬁve electrons in its last orbital. The bandgap energy is the minimum energy required to dislodge an electron from its covalent bond. 2006] June 30. rapidly raising the number of free carriers. as the reverse bias voltage across such devices increases.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For doped or undoped semiconductors. Now. thereby freeing one more covalent-bond electron.3.cls v. np = n2 . 2007 at 13:42 54 (1) 54 Chap. When an electron is freed from a covalent bond. these two electrons may again acquire energy and cause more ionizing collisions. But. It also contains a small number of free electrons at room temperature. thus gaining enough energy to break the electrons from their covalent bonds.36 (a) Release of electrons due to high electric ﬁeld. an avalanche effect takes place. To increase the number of free carriers.

(b) Repeat (a) for T = 400 K assuming for simplicity that mobility does not change with temperature.3 . and a “depletion resgion” is formed.3 . Depending on the structure and doping levels of the device. The intrinsic carrier concentration of germanium (GE) is expressed as where Eg = 0:66 eV.127) . reverse bias. they leave ionized atoms behind. 2006] June 30. typically in the range of 700 to 800 mV. 2 (2.) Eg ni = 1:66 1015 T 3=2 exp . (This is not a good assumption. the junction carries a current that is an exponential function of the applie voltage: IS expVF =VT . Upon formation of the pn junction. Dp dp=dx. A n-type piece of silicon with a length of 0:1 m and a cross section area of 0:05 m0:05 m sustains a voltage difference of 1 V.cls v. 2. 3.3 . Problems 1. The pn junction can be considered in three modes: equilibrium. (a) Calculate ni at 300 K and 600 K and compare the results with those obtained in Example 2.kT cm. calculate the total current ﬂowing through the device at T = 300 K. The capacitance itself is a function of the voltage applied across the device. 2007 at 13:42 55 (1) Sec. “Zener” or “avalanche” breakdown may occur. (b) Determine the electron and hole concentrations if Ge is doped with P at a density of 5 1016 cm. The electric ﬁeld in the depletion results in a built-in potential across the region equal to kT=q lnNA ND =n2 . The diffusion current density is proportional to the gradient of the carrier concentration and given by Jtot = q Dn dn=dx . sharp gradients of carrier densities across the junction result in a high current of electrons and holes. Since the exponential model often makes the analysis of circuits difﬁcult. An n-type piece of silicon experiences an electric ﬁeld equal to 0. As the carriers cross.1 for Si. A pn junction is a piece of semiconductor that receives n-type doping in one section and p-type doping in an adjacent section. The electric ﬁeld created in the depletion region eventually stops the current ﬂow. Under forward bias. This condition is called equilibrium. pn junctions break down. 1 . the junction carries negligible current and operates as a capacitor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and forward bias.4 Chapter Summary 55 The drift current density is proportional to the electric ﬁeld and the mobility of the carriers and is given by Jtot = q n n + p pE . 2. Under a high reverse bias voltage. conducting a very high current. (a) If the doping level is 1017 cm. i Under reverse bias. (b) What doping level is necessary to provide a current density of 1 mA/m2 under these conditions? Assume the hole current is negligible. (a) Calculate the velocity of electrons and holes in this material. a constantvoltage model may be used in some cases to estimate the circuit’s response with less mathematical labor.1 V/m.

Repeat Problem 6 for Example 2.. Figure 2. 5 x 10 Electrons 16 2 x 10 16 Holes Figure 2.38). Compare the results for linear and exponential proﬁles. what voltage yields a current of 1 mA? 15. Explain the trend.10 but for x = 0 to x = 1. Assume the cross section area of the bar is equal to a.cls v. compute the total number of electrons “stored” in the material from x = 0 to x = L. 300 K. Determine the required ND if NA = 1017 /cm2 .3 experiences a reverse bias voltage of 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 12. Determine the total current ﬂowing through the device if the cross section area is equal to 1 m 1 m. 2006] June 30. . (a) Prove that the parallel combination operates as an exponential device. 7. repeat Problem 3 for Ge.37 shows a p-type bar of silicon that is subjected to electron injection from the left 5 x 10 Electrons 16 2 x 10 16 Holes Figure 2. How do you explain the phenomenon of drift to a high school student? 10.37 0 2 µm x and hole injection from the right.38 0 2 µm x 9. (b) Calculate the built-in potential at T = 250 K. 2007 at 13:42 56 (1) 56 Chap. 2. 6.3 .e.9. (a) Determine the junction capacitance per unit area. how should IS be chosen? (b) If the diode cross section area is now doubled. the p-side of a pn junction has not been doped. (a) To obtain a current of 1 mA with a voltage of 750 mV. they fall to negligible values at x = 2 m and x = 0.39. (b) By what factor should NA be increased to double the junction capacitance? 13. Assume n = 3900 cm2 =V s and p = 1900 cm2 =V s. 8. 5.3 and NA = 2 1015 cm.6 V. In Example 2. If ND = 3 1016 cm.3 . Consider a pn junction in forward bias. From the data in Problem 1.40 shows two diodes with reverse saturation currents of IS 1 and IS 2 placed in parallel. A junction employs ND = 5 1017 cm. calculate the built-in potential at T = 300 K. An oscillator application requires a variable capacitance with the characteristic shown in Fig. i. Figure 2. respectively (Fig. Repeat Problem 7 if the electron and hole proﬁles are “sharp” exponentials.3 and NA = 4 1016 cm. 2. 2 Basic Physics of Semiconductors 4. and 350 K. A pn junction with ND = 3 1016 cm. Due to a manufacturing error. 11. 14. (a) Determine the majority and minority carrier concentrations on both sides.

Calculate VD1 and IX for IX R1 2 kΩ VX D1 Figure 2.42. What is the required change in VB ? 19. (a) Prove that this combination can be viewed as a single two-terminal device having an exponential characteristic. Figure 2. how much voltage change does such a device require? 17.cls v. Determine VD1 and IX for VX = 0:8 V and 1. (b) For a tenfold change in the current. and VD2 in terms of VB . and 1. IS 1 .5 −0. 2. the cross section area of D1 is increased by a factor of 10. VD1 . In the circuit of Fig.3 −1. .42 20. Compare the results with those obtained in Problem 19.41 shows two diodes with reverse saturation currents of IS 1 and IS 2 placed in series.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. where IS = 2 10.4 Chapter Summary C j (fF/ µ m 2 ) 57 2. 2. Consider the circuit shown in Fig.2 1. 0.2 V. 18.5 0 V R (V) Figure 2. D1 IB V D1 D1 V D2 VB Figure 2. VX = 0:5 V. 2006] June 30. Note that VD1 changes little for VX 0:8 V. In the circuit of Problem 17. 2007 at 13:42 57 (1) Sec. 2. Two identical pn junctions are placed in series.41 Calculate IB .39 I tot VB D1 D2 Figure 2. and IS 2 .15 A.2 V.42. we wish to increase IB by a factor of 10. 1 V.40 (b) If the total current is Itot .8 V. 16. determine the current carried by each diode.

We note IX R1 D1 VX Figure 2. does R1 sustain a voltage equal to VX =2? Assume IS = 2 10. 2007 at 13:42 58 (1) 58 Chap.cls v. We have received the circuit shown in Fig. 2. 2006] June 30. 2. Calculate R1 and IS . 22. Determine the required IS . determine the value of R1 such that this resistor carries 0. 29.44 25. does R1 carry a current equal to IX =2? Assume IS = 3 10. 2. . In the circuit of Fig. For what value of IX in Fig.42. 2.5 mA for IX = 1:3 mA. 28. 2. 26.5 mA.45 and wish to determine R1 and IS . Suppose D1 in Fig.44.47.16 A. Calculate the required IS . 2.46 employs two identical diodes with IS = 5 10.43 that VX = 1 V ! IX = 0:2 mA and VX = 2 V ! IX = 0:5 mA. 24. 23.43 and wish to determine R1 and IS . 2 mA.42 must sustain a voltage of 850 mV for VX = 2 V. and 4 mA. 2. If IS = 3 10. D1 D2 IX R1 2 kΩ Figure 2. For what value of VX in Fig. we wish D1 to carry a current of 0.16 A. 1 kΩ IX R1 D1 Figure 2. 2 Basic Physics of Semiconductors 21. 2.45 ments indicate that IX = 1 mA ! VX = 1:2 V and IX = 2 mA ! VX = 1:8 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.44 depicts a parallel resistor-diode combination.46 Calculate the voltage across R1 for IX = 2 mA. 27. We have received the circuit shown in Fig. Calculate R1 and IS . In the circuit of Fig. calculate VD1 for IX = 1 mA. The circuit illustrated in Fig. Measure- IX VX R1 D1 Figure 2.44. Figure 2.16 A.16 A.

47 Assume IS = 5 10. 30. 2.50 such that D1 carries 1 mA if Iin = 2 mA. Assume Iin varies from 0 to 2mA. 2. At what value of I in D1 R1 Vout Figure 2. 2. 2. 2. (b) an exponential model.49 32.48 SPICE Problems In the following problems.2 V to +2 V.51. IX VX R1 D1 Figure 2. Using SPICE. assume IS = 5 10. R1 = 500 . Repeat Problem 31 for the circuit depicted in Fig. At what value of Vin are the voltage drops across R1 and D1 equal? R1 Vout V in D1 Figure 2. Assume (a) a constantvoltage model.49. In the circuit of Fig.16 A. 34.4 Chapter Summary 59 D1 IX 1 mA R 1 D2 Figure 2. Sketch VX as a function of IX for the circuit shown in Fig. 2006] June 30. 31.48. determine the value of R1 in Fig.16 A for each diode.cls v. plot Vout as a function of Iin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2. Plot Vout as a function of Vin if Vin varies from . where R1 Iin are the currents ﬂowing through D1 and R1 equal? =1k . For the circuit shown in Fig.51 . I in D1 Vout Figure 2.50 33.50. 2007 at 13:42 59 (1) Sec.

2 Basic Physics of Semiconductors 35. 2006] June 30. R1 such that Vout 0:7 V for References 1. use SPICE to select the value of Vin 2 V. 2007 at 13:42 60 (1) 60 Chap.cls v. In the circuit of Fig. Streetman and S. Solid-State Electronic Device. B.51. 2. ﬁfth edition.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Prentice-Hall. Banerjee. We say the circuit “limits” the output. . 1999.

A simple resistor cannot serve in this role because it is linear.1 Initial Thoughts In order to appreciate the need for diodes.1(b) points to the need for a device that discriminates between positive and negative voltages. this is accomplished by ﬁrst stepping down the ac voltage by means of a transformer to about 4 V and subsequently converting the ac voltage to a dc quantity. That is. 3.1(a).1(b). How does the black box in Fig.3 The same principle applies to adaptors that power other electronic devices. 2006] June 30. 110 2. 3. ultimately arriving at interesting and real-life applications. This chapter also prepares us for understanding transistors as circuit elements in subsequent chapters. We must 1 This value refers to the root-mean-square (rms) voltage. The result displays a positive average and some ac components. so does the current through it. Ohm’s law. V = IR. which can be removed by a low-pass ﬁlter (Section 3.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. let us brieﬂy study the design of a cellphone charger.1(a) perform this conversion? As depicted in Fig.1.5 V. 3. 2007 at 13:42 61 (1) 3 Diode Models and Circuits Having studied the physics of diodes in Chapter 2. 3. Now suppose this waveform is applied to a mysterious device that passes the positive half cycles but blocks the negative ones. leading to a zero average. The waveform conversion in Fig. We proceed as follows: Diodes as Circuit Elements Ideal Diode Circuit Characteristics Actual Diode Applications Regulators Rectifiers Limiting and Clamping Circuits 3. implies that if the voltage across a resistor goes from positive to negative. As shown in Fig. we now rise to the next level of abstraction and deal with diodes as circuit elements.1 Ideal Diode 3. p 61 . passing only one and blocking the other.5. The peak value is therefore equal to 2 The line ac voltage in most countries is at 220 V and 50 Hz. 3 The actual operation of adaptors is somewhat different. The charger converts the line ac voltage at 110 V1 and 60 Hz2 to a dc voltage of 3.1). the output of the transformer exhibits a zero dc content because the negative and positive half cycles enclose equal areas.

3. (b) elimination of negative half cycles.” Shown in Fig. y (t ) t x (t ) t Figure 3. 2007 at 13:42 62 (1) 62 V1 4 2 Chap.1. 3. if x ! . Note that the device is nonlinear because it does not satisfy y = x.3(a).x.1 (a) Charger circuit. 2006] June 30. The mysterious device generates an output equal to the input for positive half cycles and equal to zero for negative half cycles.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3(a). The corresponding terminals are called the “anode” and the “cathode.2 Ideal Diode The mysterious device mentioned above is called an “ideal diode. Forward and Reverse Bias To serve as the mysterious device in the charger example of Fig. . 3. the diode must turn “on” if Vanode Vcathode and “off” if Vanode Vcathode [Fig. Figure 3. 3 60 Hz Diode Models and Circuits t V line 110 2 60 Hz 3.cls v.5 V V1 t Block Box Vout t (a) V1 4 2 ? t Equal Positive and Negative Areas (b) Positive Areas t Figure 3.2 Conceptual operation of a diode.” respectively.2 summarizes the result of our thought process thus far.y . y 6! . with the triangular head denoting the allowable direction of current ﬂow and the vertical bar representing the blocking behavior for currents in the opposite direction. therefore seek a device that behaves as a short for positive voltages and as an open for negative voltages. the diode is a two-terminal device.

3. from B to C . we say the diode is “forward-biased” if VD tends to exceed zero and “reverse-biased” if VD 0. 3. the anodes of D1 and D2 point to the same direction.3(c).3 (a) Diode symbol. If water pressure is applied from the left. D1 A B (a) D2 C A D1 B (b) D2 C A D1 B (c) D2 C Figure 3. 3.1 Ideal Diode 63 D1 Anode Cathode Forward Bias Reverse Bias IX (a) Hinge Forward Bias (b) Reverse Bias Pipe Valve Stopper (c) Figure 3. the topology of Fig.3(b) are drawn according to this convention. Solution Exercise Determine all possible series combinations of three diodes and study their conduction properties.4(b).4(c) behaves as an open for any voltage. 4 In our drawings. In Fig. Consider the pipe shown in Fig. we sometimes place more positive nodes higher to provide a visual picture of the circuit’s operation. 3. none of these circuits appears particularly useful at this point. D1 stops current ﬂow from B to A.4 A water pipe analogy proves useful here. allowing a current. . Determine which one of the conﬁgurations in Fig. 3. The diodes in Fig. the valve rises. 3.1 As with other two-terminal devices. 3. but they help us become comfortable with diodes. On the other hand. and D2 . 2007 at 13:42 63 (1) Sec. diodes can be placed in series (or in parallel).4 Series combinations of diodes.4 can conduct current. Thus. Vcathode = VD .cls v. By the same token. allowing the ﬂow of current from A to B to C but not in the reverse direction. 3. Deﬁning Vanode .3(b)]. Of course. 2006] June 30. Example 3. where a valve (a plate) is hinged on the top and faces a stopper on the bottom.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if water pressure is applied from the right. (c) water pipe analogy. (b) equivalent circuit. no current can ﬂow in either direction. the stopper keeps the valve shut. In Fig.4(a).

cls v.6(a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the current that ﬂows through the device as a function of the voltage across it.. If VA 0. Solution Exercise How is the characteristic modiﬁed if we place a 1. D1 is off. i. and ID is deﬁned as the current ﬂowing into the anode and out of the cathode.3). How do we interpret this plot? This characteristic indicates that as VD exceeds zero by a very small amount. Since an ideal diode behaves as a short or an open. The result is illustrated in Fig. Seemingly a useless circuit. If VA 0.5.5 I/V characteristics of (a) zero and inﬁnite resistors.3 Plot the I/V characteristic for the “antiparallel” diodes shown in Fig.e. The antiparallel combination therefore acts as a short for all voltages. 3. we ﬁrst construct the I/V characteristics for two special cases of Ohm’s law: R=0 I = V =1 R V = 0: R=1 I = R (3. but D2 is on.5(b) does not appear to show any ID values for VD 0. a forward-biased ideal diode sustains a zero voltage—similar to a short circuit. we combine the positive-voltage region of the ﬁrst with the negative-voltage region of the second. 3. in circuits containing only ﬁnite currents. A common type of plot is that of the current/voltage (I/V) characteristic. this topology becomes much more interesting with actual diodes (Section 3. Vcathode .2 We said that an ideal diode turns on for positive anode-cathode voltages. (b) Example 3.2) The results are illustrated in Fig.5(a).5(b). arriving at the ID =VD characteristic in Fig. yielding IA = 1. (b) ideal diode. Thus.resistor in series with the diode? Example 3. again leading to IA = 1.6(b). Solution . D1 is on and D2 is off. 2007 at 13:42 64 (1) 64 Chap. For an ideal diode. 2006] June 30. 3.1) (3. VD = Vanode . 3 Diode Models and Circuits I/V Characteristics In studying electronic devices. ID I R=0 V I R= Reverse Bias Forward Bias V VD (a) Figure 3. 3. then the diode turns on and conducts inﬁnite current if the circuit surrounding the diode can provide such a current. it is often helpful to accompany equations with graphical visualizations. 3. But the characteristic in Fig. Here.

. 3. 2007 at 13:42 65 (1) Sec. (b) Exercise Repeat the above example if a 1-V battery is placed is series with the parallel combination of the diodes. Suppose for some Solution . 3. let us assume D1 is on and see if we reach a conﬂicting result. IA IA D1 R1 (b) VA D1 R1 (a) IA R1 D1 R1 R1 (c) IA 1 R1 IA D1 R1 (e) VA VA (d) Figure 3. if VA 0. As VA rises above zero. We begin with VA 0. Example 3. Figure 3.cls v. Let us study the circuit more rigorously. (b) equivalent circuit under forward bias. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 (a) Diode-resistor series combination. Thus. (c) equivalent circuit under reverse bias. 3. D We surmise that. postulating that the diode is off. But this implies that D1 carries a current from its cathode to its anode.6 (a) Antiparallel diodes. (e) equivalent circuit if 1 is on.e. On the other hand. D1 is probably off [Fig. for VA 0. If D1 is on. the circuit is reduced to that in Fig. Does D1 turn on for any VA 0 or does R1 shift the turn-on point? We again invoke proof by contradiction.4 Plot the I/V characteristic for the diode-resistor combination of Fig.7(c)] and ID = 0. and if VA is negative. 2006] June 30.7(a). To conﬁrm the validity of this guess. 3. violating the deﬁnition of the diode. i. the actual current ﬂows from right to left.7(d) plots the resulting I/V characteristic. if VA 0. it tends to forward bias the diode.1 Ideal Diode 65 IA VA D1 D2 IA VA (a) Figure 3. (b) resulting I/V characteristic. (d) I/V characteristic. the diode is on [Fig. The above observations are based on guesswork.7(b)] and IA = VA =R1 because VD1 = 0 for an ideal diode. so is IA .7(e). D1 remains off and IA = 0.

the “effect. we can assume both D1 and D2 are forward-biased. This assumption is therefore incorrect.” This is because in typical circuits. the ﬁnal result contradicts the original assumptions. Exercise Repeat the above analysis if the terminals of the diode are swapped. D1 is still off.8 OR gate realized by diodes. then we surmise that D1 is forward-biased and D2 . Of course.6 Figure 3. 2007 at 13:42 66 (1) 66 Chap. Vout = VA = +3 V. If VA = +3 V. 3 Diode Models and Circuits VA 0. The above example leads to two important points. each input can assume a value of either zero or +3 V. In other words. Also. Exercise Plot the V/I characteristic of an ideal diode. D1 VA VB D2 RL Vout Example 3. Thus. Example 3. voltage polarities can be predicted more readily and intuitively than current polarities. behaving as an open circuit and yielding IA = 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Determine the response observed at the output. the series combination of D1 and R1 acts as an open for negative voltages and as a resistor of value R1 for positive voltages. and VB = 0.5 Why are we interested in I/V characteristics rather than V/I characteristics? Solution In the analysis of circuits. it is helpful to ﬁrst examine the circuit carefully and make an intuitive guess. The voltage drop across R1 is therefore equal to zero. if the assumptions are incorrect. we often prefer to consider the voltage to be the “cause” and the current. 2006] June 30. D1 turns on for any VA 0. Second. 3. suggesting that VD1 = VA and hence ID1 = 1 and contradicting the original assumption.cls v. In the circuit of Fig. First. Solution . in the analysis of circuits. If uncertain. we can assume an arbitrary state (on or off) for each diode and proceed with the computation of voltages and currents. reverse-biased. immediately facing a conﬂict: D1 enforces a voltage of +3 V at the output whereas D2 shorts Vout to VB = 0.8. devices such as transistors fundamentally produce current in response to voltage.

10(a).9(b). where the output is deﬁned as the voltage across D1 .10(b) and analyze its response to a sinusoidal input [Fig. We therefore modify the circuit as depicted in Fig. However. After all.10(b) is called a “rectiﬁer. shorting the output to the input. Since no current ﬂows through R1 . and the state of the diode is ambiguous.cls v. 3. When Vin falls below zero. 3. 3. 2007 at 13:42 67 (1) Sec.” the output current is always equal to zero. Since R1 has a tendency to maintain the cathode of D1 near zero. 3. Exercise Repeat the above example if a 1. If Vin 0. If Vin 0. then D1 is forward biased. It is therefore instructive to construct the input/output characteristics of a circuit by varying the input across an allowable range and plotting the resulting output. Noting that if Vin 0. Exercise Construct a three-input OR gate.10(c)]. 3. shorting the output and forcing Vout = 0 [Fig. The circuit operates as a logical OR gate and was in fact used in early digital computers. D1 is forward biased. D1 is off and Vout = 0. 2006] June 30. Thus. as Vin rises. 3. D1 turns off and R1 ensures that Vout = 0 because ID R1 = 0. Let us now design a circuit that performs this function. An example.9(d) illustrates the overall input/output characteristic.resistor is placed in series with the diode. consider the circuit depicted in Fig. Is an ideal diode on or off if VD Example 3. D1 is on and Vout = Vin . reducing the circuit to that in Fig. Input/Output Characteristics Electronic circuits process an input and generate a corresponding output. we consider slightly positive or negative voltages to determine the response of a diode circuit.3 Application Examples Recall from Fig.9(a). a piece of wire experiencing a zero voltage behaves similarly. however. the state of an ideal diode with VD = 0 is somewhat arbitrary and ambiguous. 3. the output voltage is not deﬁned because a ﬂoating node can assume any potential. and if Vin 0. D1 is reverse biased.1. 3.5 The circuit of Fig. This state holds for the positive half cycle.2 that we arrived at the concept of the ideal diode as a means of converting xt to y t.9(c)]. this does not mean it acts as an open circuit. the cathode of the diode is “ﬂoating.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . Figure 3. We may naturally construct the circuit as shown in Fig. 3. we have Vout = Vin .” It is instructive to plot the input/output characteristic of the circuit as well. In practice.1 Ideal Diode 67 The symmetry of the circuit with respect to VA and VB suggests that Vout = VB = +3 V if VA = 0 and VB = +3 V. we obtain the 5 Note that without R1 .7 Solution = 0? An ideal diode experiencing a zero voltage must carry a zero current (why?). 3. Unfortunately.

! .Vin then Example 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6) . 2007 at 13:42 68 (1) 68 V in < 0 R1 V in D1 Vout V in R1 Chap. Then.8 Is it a coincidence that the characteristics in Figs.5) (3. the two plots differ by only a scaling factor equal to R1 .10(c) to arrive at another interesting application. (c) equivalent circuit for positive input. 3. we recognize that the output voltage in Fig. 3. in the ﬁrst cycle after t = 0. Solution Exercise Construct the characteristic if the terminals of D1 are swapped.9 (a) Resistor-diode circuit. The rectiﬁer is a nonlinear circuit because if Vin Vout 6! .7(d) and 3. 3.Vout .avg = T out 0 0 (3.3) (3. 3. We now determine the time average (dc value) of the output waveform in Fig. (b) equivalent circuit for negative input. where ! = 2=T denotes the frequency in radians per second and T the period. (d) input/output characteristic. 3 Diode Models and Circuits V in > 0 R1 Vout V in Vout (a) (b) (c) Vout V in 1 (d) Figure 3. 2006] June 30. Thus. we have Vout = Vp sin !t for 0 t T 2 T tT = 0 for 2 1 Z T V tdt Vout.cls v.10(b) is simply equal to IA R1 in Fig. 3. behavior shown in Fig.10(d) look similar? No. Suppose Vin = Vp sin !t. we obtain the area under Vout and normalize the result to the period: 1 Z T=2 V sin !tdt =T p (3.10(d).4) To compute the average.7(a).

cls v.resistor is placed in series with the diode? . (b) complete rectiﬁer.10 (a) A diode operating as a rectiﬁer. If the signal is applied to a rectiﬁer.9 Solution The rectiﬁed output exhibits an average value ranging from 2 mV/ = 3:18 mV. 2007 at 13:42 69 (1) Sec. A cellphone receives a 1.8-GHz signal with a peak amplitude ranging from 2 V to 10 mV. since cellphones receive varying levels of signal depending on the user’s location and environment.7) (3. The above observation reveals that the average value of a rectiﬁed output can serve as a measure of the “strength” (amplitude) of the input.1 Ideal Diode D1 V in Vout V in D1 R1 Vout 69 (a) (b) V in t Vout 1 V in R1 V in R1 Rectified Half Cycles V in Vout 0 T 2 T (c) 3T 2 2T t (d) Figure 3. 1 = T Vp .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. cos !t T=2 0 ! = Vp : (3. a rectiﬁer can operate as a “signal strength indicator. 2006] June 30. That is.8) Thus. an expected result because a larger input amplitude yields a greater area under the rectiﬁed half cycles. (d) input/output characteristic.” For example. what is the corresponding range of the output average? Example 3. they require an indicator to determine how much the signal must be ampliﬁed. V= = 0:637 V to 10 Exercise Do the above results change if a 1. (c) input and output waveforms. the average is proportional to Vp . 3.

11(b). VB .11(c) for a sinusoidal input as the battery voltage. Depicted in Fig. we examine another circuit that will eventually (in Section 3. 3 Diode Models and Circuits In our effort toward understanding the role of diodes. yielding Vout = Vin . Here.3.11(a).cls v. How should the circuit of Fig. 3. but shifted to the right by 1 V.11(a). We say the circuit “clips” or “limits” at +1 V.5. the anode is not positive enough to forward bias D1 . Now. placing D1 in reverse behave? If V1 bias. Thus. 3. Shown in Fig. 3. 2006] June 30. Sketch the time average of Vout in Fig. D1 acts a short. let us examine the circuit in Fig. D1 remains off. 3. consider the topology in Fig. (c) addition of series battery to (b).. as illustrated in the output waveform and the input/output characteristic. For Vin 0. 3. e. D1 must turn on only when Vout approaches +1 V. the modiﬁcation indeed guarantees Vout +1 V for any input level. I1 I1 V1 D1 VB 1V +1 V (a) V1 Vout R1 V in D1 Vout V in t Vout 1 V in t (b) R1 D1 VB 1V V in + Vp V in Vout Vout t − Vp +1V Vout +1 V +1 V 1 V in t − Vp (c) Figure 3. where a 1-V battery is placed in series with an ideal diode. the I/V characteristic of the diode-battery combination resembles that of a diode.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g. the cathode voltage is higher than the anode voltage. and Vout = 0. 3. equal to 0.11(c). How does this circuit 0. First. 2007 at 13:42 70 (1) 70 Chap. (b) resistor-diode circuit. The circuit therefore does not allow the Example 3. But suppose we seek a circuit that must not allow the output to exceed +1 V (rather than zero).11 (a) Diode-battery circuit. V1 must approach +1 V for D1 to turn on.10 . output to exceed zero. for Vin 0. implying that a 1-V battery must be inserted in series with the diode.3) lead to some important applications. Even if V1 is slightly greater than zero.9 V. “Limiters” prove useful in many applications and are described in Section 3.5.11(b) be modiﬁed? In this case.

12 . 2007 at 13:42 71 (1) Sec. for VB Vp . 3. D1 turns off at some point in the negative half cycle and remains off in the positive half cycle. yielding an average greater than .Vp VB 0. D1 is always on because Vin .11 Is the circuit of Fig. indeed. 3. In this case.Vp = .Vp . 2006] June 30. Exercise Repeat the above example if the terminals of the diode are swapped. the output average is equal to VB [Fig. producing a negative average.1 to +1. VB < − Vp V in t VB − Vp − Vp < VB Solution V in VB Vout − Vp t Vout = VB VB = 0 + Vp < VB + Vp VB V in VB Vout − Vp (a) t Vout t Vout − Vp + Vp − Vp − Vp 1 (b) π VB Figure 3. The circuit passes only negative cycles to the output. . Finally. Figure 3. no limiting occurs and the average is equal to zero.1 Ideal Diode 71 varies from .11(b) be modiﬁed to pass only positive cycles to the output. For VB = 0. Example 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3.12(a)]. the average reaches . Exercise How should the circuit of Fig. If VB is very negative. For .cls v.11(b) a rectiﬁer? Solution Yes.Vp but less than VB .12(b) sketches this behavior. 3.

Thus. the voltage drop across R1 is zero and Vout = Vin .cls v. 3. In fact. Figures 3. we may discover that this idealization is inadequate and hence employ the constant-voltage model. This model sufﬁces in most cases. ID Ij VD (a) (b) Vj ID V D. rough understanding of the circuit’s operation. operating as a short and reducing the circuit to a voltage Solution . for Vin 0.14(a) using (a) the ideal model and (b) the constant-voltage model. 2007 at 13:42 72 (1) 72 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (c) constant-voltage model. providing a simple approximation of the exponential function and also resembling the characteristic plotted in Fig. Given a circuit topology.13 Diode characteristics: (a) ideal model. how do we choose one of the above models for the diodes? We may utilize the ideal model so as to develop a quick.11(a). 3 Diode Models and Circuits 3.12 Plot the input/output characteristic of the circuit shown in Fig. Example 3.2 PN Junction as a Diode The operation of the ideal diode is somewhat reminiscent of the current conduction in pn junctions.on (c) Figure 3. As Vin exceeds zero. respectively. (a) We begin with Vin = . D1 turns on. The following examples illustrate these points.on V D.13 is the constant-voltage model developed in Chapter 2. 3. The latter can serve as an approximation of the former by providing “unilateral” current conduction. Shown in Fig. (b) exponential model.13(a) and (b) plot the I/V characteristics of the ideal diode and the pn junction. but we may need to resort to the exponential model for some circuits. In fact.on VD V D. recognizing that D1 is reverse biased.3(b) are quite similar to those studied for pn junctions in Chapter 2. the diode remains off and no current ﬂows through the circuit. 3. the forward and reverse bias conditions depicted in Fig.1. 3. Upon performing this exercise. 2006] June 30.

Figure 3.on Vout = R1 (3. (c) input/output characteristic with constant-voltage diode model . yielding Vout = Vin . Vout = Vout . . D1 turns on.on [as illustrated in Fig.2 PN Junction as a Diode 73 V in R1 Vout R2 D1 Vout R2 R2 + R1 V in 1 (a) (b) V in R1 Vout R2 V D.on . 3.11) : 1 + R2 R1 As expected. we apply Kirchoff’s current law to the output node: Vout = R R2 R Vin for Vin 0: 1+ 2 (3. (b) In this case.on : R1 R2 It follows that (3. displaying the same shape as that in Fig. the circuit operates as a voltage divider once the diode turns on and loads the output node with R2 . D1 is reverse biased for Vin VD.on Vout R2 R2 + R1 V D. 3. 3.14(c).14(d) plots the resulting characteristic.on 1 (c) (d) V D.cls v. Vout = VD.on if Vin = VD.on V in Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.14 (a) Diode circuit.14(b) plots the overall characteristic. (b) input/output characteristic with ideal diode model. Reducing the circuit to that in Fig. VD.9) Vin .14(b) but with a shift in the break point. In other words. divider.on . 2007 at 13:42 73 (1) Sec. plot the current through R1 as a function of Vin . operating as a constant voltage source with a value VD. As Vin exceeds VD. That is. revealing a slope equal to unity for Vin 0 and R2 =R2 + R1 for Vin 0.10) R2 V + V in D.on .13(c)]. Figure 3. 3. 2006] June 30. Exercise In the above example.

15 Diode circuit. Determine the current ﬂowing through each diode. ID1 = Exercise For the circuit of Fig. We have Iin = ID1 + ID2 : We also equate the voltages across D1 and D2 : (3.3 Additional Examples Example 3.14) Iin I 1 + IS 2 S1 Iin : ID2 = I 1 + IS 1 S2 As expected.13) ID1 = ID2 : IS1 IS2 Solving (3.13 In the circuit of Fig. ID1 = ID2 = Iin =2 if IS 1 = IS 2 . I I S1 S2 that is. D1 and D2 have different cross section areas but are otherwise identical. (3. 3 Diode Models and Circuits 3. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (3. 3.15.16) This section can be skipped in a ﬁrst reading .15) (3.15.14) together yields (3. 2006] June 30.12) and (3. IS 1 . 2007 at 13:42 74 (1) 74 Chap. calculate VD is terms of Iin . and IS 2 .12) VT ln ID1 = VT ln ID2 . Solution In this case. I in R 1 V1 D1 D2 Figure 3. we must resort to the exponential equation because the ideal and constant-voltage models do not include the device area.cls v.

17) At what point does D1 turn on? The diode voltage must reach VD. vout = R R2 R Vin : 1+ 2 R2 V = V . 3. R1 Vout R2 D1 R1 Vout R2 V in V in (a) (b) Vout V D. R1 + R2 in D.16(a). 2007 at 13:42 75 (1) Sec.1.3 Additional Examples 75 Example 3. the voltage across the diode happens to be equal to the output voltage. D1 is reverse biased and the circuit reduces to that in Fig.on R1 ) V D.on 2 . We note that if Vin = .14 Using the constant-voltage model plot the input/output characteristics of the circuit depicted in Fig.16 (a) Diode circuit.16(b).on R2 V in R2 R2 + R1 (1 + (c) Figure 3. 3.cls v.18) R1 V : Vin = 1 + R D. (b) equivalent circuit when D1 is off.on . 3. 2006] June 30. (c) input/output characteristic.on and hence (3. Solution In this case.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.on . requiring an input voltage given by: (3. Note that a diode about to turn on carries zero current but sustains VD. Consequently.

18)? To determine the break point. So why did we express the diode voltage as such in Eq.g. (3. but the voltage across it and hence the input voltage are almost sufﬁcient to turn it on. The diode therefore still draws no current. . it draws current and the diode voltage is no longer equal to R2 =R1 + R2 Vin .19) The reader may question the validity of this result: if the diode is indeed on. (3. e. it creates Vout 799 mV.. we assume Vin gradually increases so that it places the diode at the edge of the turn-on.

D1 remains forward-biased.16(c) plots the overall characteristic.17(a). Thus. D1 V in R2 X R1 Vout V D. and redraw the circuit as depicted in Fig. placing the more negative voltages on the bottom and the more positive voltages on the top.e. This diagram suggests that the diode operates in forward bias.. 3 Diode Models and Circuits For Vin 1 + R1 =R2 VD. the anode is tied to ground and the cathode the output node.20) .on .on . plot the current through R1 as a function of Vin .on X D1 R2 R1 Vout V in = − (a) (b) Vout V in R2 Vout R1 R ( 1 + 1 ) V D.cls v. Note that in this regime. Example 3. i. we have Solution Vout = Vin + VD. so long as D1 is on.on . 2006] June 30. (c) equivalent circuit when off. (d) input/output characteristic. 3. (b) illustration for very negative inputs.on R2 R1 R1 + R2 V in 1 (c) (d) Figure 3.15 Plot the input/output characteristic for the circuit shown in Fig. 2007 at 13:42 76 (1) 76 Chap. Assume a constantvoltage model for the diode. Exercise For the above example. VX is independent of R2 because D1 acts as a battery.1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Figure Exercise Repeat the above example but assume the terminals of D1 are swapped. 3. D1 is We begin with Vin = . establishing a voltage at node X equal to Vin + VD.17 (a) Diode circuit.17(b). yielding Vout 3. = VD.on : (3.

In other words. at some point IR2 = IR1 . it may be difﬁcult to correctly predict the region of operation of each diode by inspection. At what point does D1 turn off? Interestingly. predicting intuitively that D1 is on. The reader may ﬁnd it interesting to recognize that the circuits of Figs.23) 1 Thus.e. the circuit reduces to that shown in Fig. we may simply make a guess.1.on = .. in more complex circuits. in this case it is simpler to seek the condition that results in a zero current through the diode rather than insufﬁcient voltage across it. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. proceed with the analysis.16 Plot the input/output characteristic of the circuit shown in Fig. Vin + VD.22) R1 + = . In such cases. 3.21) and (3. As mentioned in Example 3.3 Additional Examples 77 We also compute the current ﬂowing through R2 and R1 : IR2 = VD. We also (blindly) assume that D2 . Exercise Repeat the above example if the terminals of the diode are swapped.24) R Vin = . We begin with Vin Solution = . From (3.21) R2 IR1 = 0 . 3.on : 2 As Vin exceeds this value. The observation that at some point. IR2 = IR1 proves useful here as this condition also implies that D1 carries no current (KCL at node X ).on R2 R1 and hence (3.cls v.on : (3. the output is sensed across the diode whereas in the latter it is sensed across the series resistor. VX (3. as Vin increases from . VD.16(a) and 3.25) Vout = R R1 R Vin : 1+ 2 (3.17(c) and (3. 2007 at 13:42 77 (1) Sec. The following example illustrates this approach.1 + R1 VD. 3.18(a) using the constant-voltage diode model.17(d).Vin R VD. IR2 remains constant but jIR1 j decreases.23). Example 3. i.26) The overall characteristic is shown in Fig. Of course. 2006] June 30. 3.17(a) are identical: in the former. and eventually determine if the ﬁnal result agrees or conﬂicts with the original guess.1. we still apply intuition to minimize the guesswork. D1 turns off if Vin is chosen to yield IR2 = IR1 .on (3.4.

Vout = Vin . IR1 is independent of Vin . (e) equivalent circuit for in D.V is on. We must now analyze these results to determine whether they agree with our assumptions regarding the state of D1 and D2 .on .VB . 3 Diode Models and Circuits I R2 = D1 V in D2 Y V B= 2 V R1 X R1 Vout V D. (b) possible equivalent circuit for very negative inputs.e. VR 2 (3. (d) equivalent circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.18 (a) Diode circuit.VB + VD.on D1 X R1 Vout Y VB R1 D2 Y V B= 2 V (e) R1 (d) Vout D1 − V D. 2007 at 13:42 78 (1) 78 Chap. 2006] June 30.on V in D 1 turns off. thus reducing the circuit to that in Fig. (f) complete input/output characteristic.on + VB between Vin and Vout .on R2 Vout VB Y I1= V D. Consider the current ﬂowing through R2 : out IR2 = .18(b). (f) section of input/output characteristic. 3. (g) equivalent circuit. i. yielding R1 IR1 + VD. The path through VD.on : R 1 (3.on V D.on R2 Vout R1 X Y VB I R1 R1 X V in = − (a) (b) V in = − (c) D1 V in D2 X R1 Vout V in = − V D. VD.cls v..on = .on .on . V in V in (f) (g) (h) Figure 3.28) That is.on + VB . 2VD. This voltage difference also appears across the branch consisting of R1 and VD. (c) simpliﬁed circuit. V = .29) . and hence (3.27) IR1 = .on and VB creates a difference of VD.on Vout X R1 Vout D2 Y V B= 2 V R1 − V D.

which is not possible. In other words. 3. and hence D1 . However. The ideal and constant-voltage diode models resolve the issues to some extent. Thus. D2 must conduct current from its cathode to it anode.31) We now raise Vin and determine the ﬁrst break point. the voltage at node Y is equal to +VB whereas the cathode of D2 is at . yielding a zero current through R1 .4 Large-Signal and Small-Signal Operation 79 which approaches +1 for Vin = .1. At what point does D2 turn on? The input voltage must exceed VY by VD. Vin .on . Vin must reach VB + VD. 3.on . (3. and VY = VB .18(f) plots the input-output characteristic to the extent computed thus far. Since at this break point.on approaches zero. The following example illustrates the general difﬁculty. The large value of IR2 and the constant value of IR1 indicate that the branch consisting of VB and D2 carries a large current with the direction shown.VD. we have D. this model often complicates the analysis.VD.cls v. 3.18(g). The diode therefore turns off at Vin = . i. assume D2 turns on before D1 turns off and show that the results conﬂict with the assumption. VR . VB : Figure 3. 2006] June 30.30) Vout = Vin + VD..1. 3. “manual” analysis eventually becomes impractical. VX = Vin + VD. In summary. after which the circuit is conﬁgured as shown in Fig. we have observed that the forward bias assumption for D2 translates to a current in a prohibited direction. Which one occurs ﬁrst? Let us assume D1 turns off ﬁrst and obtain the corresponding value of Vin .e.18(d).on = . summarizing the regions of operation. D2 operates in reverse bias for Vin = .on R R2 R : 1+ 2 (3.32) Exercise In the above example.on .18(c) and noting that VX = Vin + VD. thereby requiring a “general” model such as the exponential I/V characteristic. 2007 at 13:42 79 (1) Sec. Vout = 0.on . as the number of nonlinear devices in the circuit increases.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We call this regime “largesignal operation” and the exponential characteristic the “large-signal model” to emphasize that the model can accommodate arbitrary signal levels. Consequently. Redrawing the circuit as in Fig. revealing that Vout = 0 after the ﬁrst break point because the current ﬂowing through R1 and R2 is equal to zero.18(h) plots the overall result. making it difﬁcult to develop an intuitive understanding of the circuit’s operation. 3..on . Assuming that D1 is still slightly on. 3.4 Large-Signal and Small-Signal Operation Our treatment of diodes thus far has allowed arbitrarily large voltage and current changes.on . Since D2 is assumed off. we draw the circuit as shown in Fig. as seen in previous examples. VX = Vout = 0. VD. Before D2 turns on.on [Fig. That is. 3. Vout = Vin . Furthermore. but the sharp nonlinearity at the turn-on point still proves problematic.e. .18(e)]. we recognize that at Vin . Fig. i. 2 (3. We must now verify the assumption that D2 remains off. R2 .VD. the point at which D1 turns off or D2 turns on. D2 is indeed off. VB .

IX = Vad R Vout 1 = 6 mA: We note that each diode carries IX and hence (3.16 A: (3.1 V must drop across R1 . raising IX to 7 mA. where three identical diodes in forward bias produce a total voltage of Vout = 3VD 2:4 V and resistor R1 sustains the remaining 600 mV. we begin with IX = 7 mA and iterate: Vout = 3VD (3.38) 6 Made for the sake of simplicity here. 2006] June 30.33) (3. IS 1 so that Vout 3. Then.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 To examine the circuit quantitatively.cls v. He then decides to put his knowledge of electronics to work and constructs the circuit shown in Fig. Neglect the current drawn by the cellphone.36) IS = 2:602 10.6 (a) Determine the reverse IX 600 mV R 1 = 100 Ω Vad = 3 V Adaptor Vout Cellphone Figure 3. 3. an electrical engineering student tries several stores but does not ﬁnd adaptors with outputs less than 3 V.34) IX = IS exp VD : V T It follows that (3. (a) With Vout = 2:4 V. Since the voltage across each diode has a logarithmic dependence upon the current. (b) Compute Vout if the adaptor voltage is in fact Solution = 2:4 V.1 V.37) (b) If Vad increases to 3. this assumption may not be valid.19.4 V.17 Having lost his 2. the change from 6 mA to 7 mA indeed yields a small change in Vout . we expect that Vout increases only slightly. To understand why.35) mV 6 mA = IS exp 800mV 26 and (3. .19 Adaptor feeding a cellphone.1 V. ﬁrst suppose Vout remains constant and equal to 2. 3 Diode Models and Circuits Example 3. 7 Recall from Eq. 2007 at 13:42 80 (1) 80 Chap. the current ﬂowing through R1 is equal to . the additional 0. saturation current.4-V cellphone charger.109) that a tenfold change in a diode’s current translates to a 60-mV change in its voltage. (2.

Now suppose a perturbation in the circuit changes the diode voltage by a small amount VD [point B in Fig. These thoughts lead us to the extremely important concept of “small-signal operation. 2006] June 30.1 V results in a small change in the circuit’s voltages and currents. The constant-voltage diode model would not be useful in this case. 3. But.46) (3. the reader may wonder if a simpler approach is really necessary.45) (3. allowing standard circuit analysis and obviating the need for iteration. 3. motivating The situation described above is an example of small “perturbations” in circuits.20(c)].39) (3. 2007 at 13:42 81 (1) Sec. Exercise Repeat the above example if an output voltage of 2. 3.cls v.20(a). The deﬁnition of “small” will become clear later. let us consider diode D1 in Fig.43) (3. which sustains a voltage VD1 and carries a current ID1 [point A in Fig. us to seek a simpler analysis method that can replace the nonlinear equations and the inevitable iterative procedure. we conclude that Vout = 2:411 V with good accuracy. To develop our understanding of small-signal operation. 3. ID ? We can begin with the nonlinear characteristic: Vad from 3 V to 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. since the above example does not present an overwhelmingly difﬁcult problem. Of course.35 is desired.44).40) and (3.41) (3. IX = Vad R Vout 1 = 6:88 mA.40) . then expV=VT 1 + V=VT and ID2 = IS exp VD1 + V IS exp VD1 VT VT VT (3. circuits containing complex devices such as transistors may indeed become impossible to analyze if the nonlinear equations are retained.44) Noting the very small difference between (3.” whereby the circuit experiences only small changes in voltages and currents and can therefore be simpliﬁed through the use of “small-signal models” for nonlinear devices.20(b)]. as seen in subsequent chapters. The change in If V + ID2 = IS exp VD1V V T VD1 exp V : = IS exp V VT T VT . How do we predict the change in the diode current. which translates to a new Vout : (3.42) Vout = 3VD = 2:411 V: (3.4 Large-Signal and Small-Signal Operation 81 = 3VT ln IX I = 2:412 V: This value of Vout gives a new value for IX : S (3. The simplicity arises because such models are linear.47) .

(3.8 8 This is also to be expected.45) to obtain the change in equivalent to taking the derivative. (3.cls v. Writing Eq. (c) change in ID as a result (3. with a slope equal to the local slope of the characteristic.21). I D2 ID I D2 I D1 A V D1 V D2 VD B I D1 A ∆V D B ∆I D Figure 3. V D1 .) The above result should not come as a surprise: if the change in VD is small.20(c) between points A and B can be approximated by a straight line (Fig.49). ID for a small change in VD is in fact . the section of the characteristic in Fig. 2006] June 30. 3. (b) operating point of of change in D . with a proportionality factor equal to ID1 =VT .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. ID = V ID1 : V T (3.49) The key observation here is that ID is a linear function of V . The signiﬁcance of this trend becomes clear later.51) (3. In other words. T which yields the same result as that in Eq.21 Approximation of characteristic by a straight line. 2007 at 13:42 82 (1) 82 Chap. ID dID VD = dVD jV D=V D1 (3. 3.50) (3.48) = ID1 + V ID1 : V T That is.20 (a) General circuit containing a diode.52) I = VS exp VD1 VT T D = IV 1 . 3 Diode Models and Circuits ID V D1 D1 I D1 I D1 A V D1 (a) (b) ID I D2 I D1 VD ? B A V D1 V D2 (c) ∆V D VD Figure 3. (Note that larger values of ID1 lead to a greater ID for a given VD .

53) (3.cls v. Example 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.49). it moves on a straight line to point B with a slope equal to the local slope of the characteristic (i.54) = 38:4 A: VD = VT ID I = 1 mA 0:1 mA = 2:6 mV: .18 Solution (a) We have I ID = VD VD T (b) Using the same equation yields (3. 3.e. for small-signal analysis. dID =dVD calculated at VD = VD1 or ID = ID1 ). Equivalently.4 Large-Signal and Small-Signal Operation 83 Let us summarize our results thus far. (a) Determine the current change if VD changes by 1 mV. If the voltage across a diode changes by a small amount (much less than VT ). (3.9 A diode is biased at a current of 1 mA. 3. we can assume the operation is at a point such as A in Fig. (b) Determine the voltage change if ID changes by 10%. Point A is called the “bias” point or the “operating” point. then the change in the current is given by Eq.21 and. due to a small perturbation. 2006] June 30. 2007 at 13:42 83 (1) Sec..

. the device behaves as a linear resistor. rd = 26 . For bias calculations. the diode is replaced with an ideal voltage source of value VD.22(b) is transformed to that in Fig.57) Exercise In response to a current change of 1 mA.D mV 26 (3. In the above example.58) This quantity is also called the “incremental” resistance to emphasize its validity for small changes.55) in the above example reveals an interesting aspect of small-signal operation: as far as (small) changes in the diode current and voltage are concerned.56) (3. In analogy with Ohm’s Law. and for small changes.55) (3. Figure 3.22(a) summarizes the results of our derivations for a forward-biased diode. 3. 3. a diode exhibits a voltage change of 3 mV. we deﬁne the “small-signal resistance” of the diode as: rd = VT : I D (3. For example.on . Calculate the bias current of the diode. Equation (3. the circuit of Fig. Note that v1 and vout in 9 Also called the “quiescent” point. with a resistance equal to rd .22(c) if only small changes in V1 and Vout are of interest.

It follows that. we can view V0 and the corresponding current. determine the resulting diode current. (b) response of a diode to the sinusoid. 2007 at 13:42 84 (1) 84 Chap. as the bias point of the diode and Vp as a small perturbation. With a signal swing much less than VT . In general. 2006] June 30.on Bias Model (a) R1 D1 Vout v1 rd v out rd Small−Signal Model V1 (b) (c) Figure 3. If this signal is applied across a diode and Vp VT .23(b). As shown in Fig. 3. 3. T and (3. Example 3.59) rd = VT : I 0 (3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.23(a). (b) circuit example. 3 Diode Models and Circuits Fig.19 Solution The signal waveform is illustrated in Fig. (c) smallsignal model. we rotate this diagram by 90 so that its vertical axis is aligned with the voltage axis of the diode characteristic. ID ID Ip V (t ) V0 I0 Vp VD t t V0 t (a) (b) Figure 3.22 Summary of diode models for bias and signal calculations. R1 VD.cls v. we denote small-signal voltages and currents by lower-case letters. I0 .60) . 3. A sinusoidal signal having a peak amplitude of Vp and a dc value of V0 can be expressed as V t = V0 + Vp cos !t.22(c) represent changes in voltage and are called small-signal quantities. V I0 = IS exp V 0 .23 (a) Sinusoidal input along with a dc level.

62) ID t = I0 + Ip cos !t V I = IS exp V 0 + V0 Vp cos !t: T T (3. ID changes by a small amount and we wish to compute the change in VD .4 Large-Signal and Small-Signal Operation 85 Thus. 2006] June 30. Calculate IS .. i. V T a task much more difﬁcult than the above linear calculations.64) The diode in the above example produces a peak current of 0. Beginning with VD = VT lnID =Is .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.65) In the derivation leading to Eq. T yielding (3. the peak current is simply equal to Ip = Vp =rd I = V0 Vp .cls v.e.20 Solution VD1 + VD = VT ln ID1 + ID I = VT ln IID1 1 + ID I S S .63) (3.1 mA in response to V0 and Vp = 1:5 mV. Denoting the change in VD by VD . 2007 at 13:42 85 (1) Sec. we assumed a small change in VD and obtained the resulting change in ID .49).10 (3. 3. If Vp were large.61) (3. investigate the reverse case. we would need to solve the following equation ID t = IS exp V0 + Vp cos !t . (3. we have Example 3. Exercise = 800 mV The above example demonstrates the utility of small-signal analysis.

66) (3.67) (3. we assume ID .68) if = VT ln IID1 + VT ln 1 + ID : I S For small-signal operation. D1 (3.

(3. Figure 3.69) which is the same as Eq. distinguishing between the cause and the effect. . (3. Thus.49). ID1 1. D1 ID1 and note that ln1 + VD = VT ID . 10 The function expa sin bt can be approximated by a Taylor expansion or Bessel functions.24 illustrates the two cases.

we can construct the small-signal model shown in Fig. In Example 3. solution of nonlinear diode equations predicted an 11-mV change in Vout .71) That is. The small-signal analysis therefore offers reasonable accuracy while requiring much less computational effort.70) (3. Exercise Repeat Examples (3.17. With our understanding of small-signal operation.5-mV change in Vout . we now revisit Example 3. 3. (As mentioned earlier. where vad = 100 mV and rd = 26 mV=6 mA = 4:33 .17. . Example 3.21) if the value of R1 in Fig. the voltages shown in this model denote small changes. Since each diode carries ID1 = 6 mA with an adaptor voltage of 3 V and VD1 = 800 mV.25.) We can thus write: R1 Solution v ad rd rd rd v out Figure 3. Exercise Repeat the above example by taking the derivative of the diode voltage equation with respect to ID . 2007 at 13:42 86 (1) 86 Chap. 2006] June 30.cls v.17) and (3. a 100-mV change in Vad yields an 11.21 Repeat part (b) of Example 3.24 Change in diode current (voltage) due to a change in voltage (current).17 with the aid of a small-signal model for the diodes. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. r vout = R 3+d3r vad 1 d = 11:5 mV: (3.25 Small-signal model of adaptor. 3 Diode Models and Circuits ∆ID ∆V D D1 (a) ∆ID = = ∆V D rd ∆ID I D1 VT D1 ∆V D (b) ∆V D = ∆ I D r d = ∆V D ∆I D VT I D1 Figure 3.19 is changed to 200 .

the reader may wonder if the smallsignal model is really necessary.4 Large-Signal and Small-Signal Operation 87 Considering the power of today’s computer software tools. ~6 mA R 1 = 100 Ω 0. (2) develop the small-signal model for each diode (i. Indeed. Example 3.cls v. In summary. as shown in Fig.72) (3.73) (3.21.22 In Examples 3. Solution Since the current ﬂowing through the diodes decreases by 0. 2006] June 30.e. 2007 at 13:42 87 (1) Sec. A bad circuit designer. we write the change in the output voltage as: Vout = ID 3rd = 0:5 mA3 4:33 = 6:5 mV: (3. allows the computer to think for him/her. the current drawn by the cellphone is neglected. . 11 A cellphone in reality draws a much higher current..74) Exercise Repeat the above example if R1 is reduced to 80 .26 Adaptor feeding a cellphone. we utilize sophisticated simulation tools in the design of integrated circuits today.5 mA11 and determine Vout . but the intuition gained by hand analysis of a circuit proves invaluable in understanding fundamental limitations and various trade-offs that eventually lead to a compromise in the design. on the other hand. Now suppose. calculate rd ).5 mA V ad Vout Cellphone Figure 3. the analysis of circuits containing diodes (and other nonlinear devices such as transistors) proceeds in three steps: (1) determine—perhaps with the aid of the constant-voltage model— the initial values of voltages and currents (before an input change is applied). A good circuit designer analyzes and understands the circuit before giving it to the computer for a more accurate analysis. 3.5 mA and since this change is much less than the bias current (6 mA).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the load pulls a current of 0. 3.17 and 3. (3) replace each diode with its small-signal model and compute the effect of the input change.26.

1 Half-Wave and Full-Wave Rectiﬁers Half-Wave Rectiﬁer Let us return to the rectiﬁer circuit of Fig.23 Prove that the circuit shown in Fig. Depicted in Fig. D1 is off12 and Vout = 0.29 Rectiﬁcation of positive cycles. 2007 at 13:42 88 (1) 88 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5. Half−Wave and Full−Wave rectifiers Limiting Circuits Voltage Doublers Level Shifters and Switches Figure 3.on V in R1 Vout t V D. 3.on . allowing R2 to maintain Vout = 0. 3.5 Applications of Diodes The remainder of this chapter deals with circuit applications of diodes. at which point D1 turns on and Vout = Vin . 12 If Vin 0. 3.on .VD. but it blocks the positive cycles. In this case.29(a) is also a rectiﬁer. In particular.on V in V out Figure 3. we no longer assume D1 is ideal. D1 turns off. 3 Diode Models and Circuits 3. VD.cls v.VD. D1 V in R1 Vout V out (a) (b) V in t Figure 3. For Vin VD.27 Applications of diodes. 2006] June 30.on . D1 remains on for negative values of Vin . 3. D1 V D. Solution Exercise Plot the output if D1 is an ideal diode. D1 carries a small leakage current. A brief outline is shown below. Thus. the resulting output reveals that this circuit is also a rectiﬁer.28. but the effect is negligible.10(b) and study it more closely. Example 3. for Vin . the circuit still operates as a rectiﬁer but produces a slightly lower dc level.28 Simple rectiﬁer.on . but use a constant-voltage model. 3. Vout remains equal to zero until Vin exceeds VD.on . speciﬁcally. . As Vin exceeds . As illustrated in Fig.29.

VD. Vin = .31(a) shows the input and output waveforms. which is impossible.28 does not produce a useful output.Vp .on t1 t2 t3 t4 t5 t Continuing our analysis.. the rectiﬁer generates an output that varies considerably with time and cannot supply power to electronic devices.on . V out V D.on indeﬁnitely. 2006] June 30.31(a).e. D1 is off until Vin VD. Assuming a constant-voltage model for D1 in forward bias. Assuming an ideal diode model. we note that at t = t3 . Thus. (b) Plot the voltage across D1 . Vout remains equal to Vp .on . At t = t2 .on = Vout .31(b). We must therefore attempt to create a constant output.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. At t t2 . 3.on . diodes used in rectiﬁers must withstand a reverse voltage of approximately 2Vp with no breakdown. As depicted in Fig.” the circuit of Fig.on V in D1 V in C1 Vout Maximum Reverse Voltage (a) (b) Figure 3.3(c) proves useful here. VD1 . VD. VD. Vout . Fortunately. Vin falls below Vout . we have Vin = Vp and Vout = Vp . As Vin begins to fall. D1 turns on as Vin exceeds zero and Vout = Vin . 3.5 Applications of Diodes 89 Called a “half-wave rectiﬁer. 3. This is because if Vout were to fall. Figure 3.30 (a) Diode-capacitor circuit. VD1 is similar to Vin but with the 13 The water pipe analogy in Fig. The operation of this circuit is quite different from that of the above rectiﬁer. then C1 would need to be discharged by a current ﬂowing from its top plate through the cathode of D1 . 3. 3. At t = t5 . As Vin rises from zero. we begin with a zero initial condition across C1 and study the behavior of the circuit [Fig. Vin just exceeds Vout but still cannot turn D1 on. at which point D1 begins to act as a battery and Vout = Vin . a simple modiﬁcation solves the problem. and D1 is on. Vout must remain constant.on .30(a). but Vout exhibits no tendency to change because the situation is identical to that at t = t1 .24 Solution .on. Interestingly. (b) input and output waveforms. (a) With a zero initial condition across C1 .on across the diode. What happens as Vin passes its peak value? At t = t1 . Does Vout change after t = t1 ? Let us consider t = t4 as a potentially interesting point. Vin = 2Vp . After t = t1 . Here. In other words. applying a maximum reverse bias of Vout . (b) The voltage across the diode is VD1 = Vin . turning D1 off. VD. Vin = Vp . i. (a) Repeat the above analysis. 3. as a function of time. Unlike a battery. Vin Vout and the diode experiences a negative voltage. 3. VD. VD. Vp V p − V D.30(b)]. For this reason. Vin = Vp = Vout + VD. Using the plots in Fig. we readily arrive at the waveform in Fig. Vout reaches a peak value of Vp . Example 3.13 The diode therefore turns off after t1 . the diode sustains a zero voltage difference.cls v. the resistor is replaced with a capacitor. 2007 at 13:42 89 (1) Sec.

2006] June 30. If the laptop is modeled by a resistor.14 But how is the value of C1 chosen? To answer this question.cls v. Since P = V I .” .3 V.30 with an ideal diode. then RL = V=I = 0:436 .30(a) achieves the properties required of an “ac-dc converter. RL .4). The circuit of Fig.Vp .” generating a constant output equal to the peak value of the input sinusoid. .25 A laptop computer consumes an average power of 25 W with a supply voltage of 3. 3.load represent for such a supply voltage? 14 This circuit is also called a “peak detector. we have I 7:58 A.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 3. We will exploit this result in the design of voltage Exercise Repeat the above example if the terminals of the diode are swapped. Solution Exercise What power dissipation does a 1.5. 3.31 (a) Input and output waveforms of the circuit in Fig. (b) voltage across the diode. 2007 at 13:42 90 (1) 90 V out Chap. Determine the average current drawn from the batteries or the adapter. we consider a more realistic application where this circuit must provide a current to a load. 3 Diode Models and Circuits t1 V in (a) t t1 t V D1 −2 V p (b) Figure 3. average value shifted from zero to doublers (Section 3.

at t = t3 . C1 is called the “smoothing” or “ﬁlter” capacitor. the circuit behaves as in the ﬁrst cycle. C1 must be so large that the current drawn by RL does not reduce Vout signiﬁcantly. 3. if C1 is very small. as Vin begins to fall after t = t1 . Vout falls slowly and D1 remains reverse biased. If V in V out Very Small C 1 Large C1 Small C1 Solution t Figure 3. Figure 3.32 as values.32(a)].cls v. .33 Output waveform of rectiﬁer for different values of smoothing capacitor. With such a choice of C1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VD. Conversely. Hereafter.26 Sketch the output waveform of Fig. exhibiting large variations in Vout . VD. Vin exceeds Vout by VD.5 Applications of Diodes 91 As suggested by the above example. C1 varies from very large values to very small C1 is very large. the current drawn by RL when D1 is off creates only a small change in Vout .on . The resulting variation in Vout is called the “ripple.33 illustrates several cases.32 (a) Rectiﬁer driving a resistive load. 3.on . Vp V p − V D. Vin and Vout become equal and slightly later. so does Vout because RL provides a discharge path for C1 . From the waveforms in Fig. the circuit approaches that in Fig. However. 2007 at 13:42 91 (1) Sec. (b) input and output waveforms. 2006] June 30. 3. Of course. 3. t = t2 .” Also. VD. 3.on V in D1 V in t1 C1 RL Vout t3 t2 t V out VR (a) (b) Figure 3. still exhibiting a value of Vin . the load can be represented by a simple resistor in some cases [Fig.on = Vp . since changes in Vout are undesirable. The output voltage continues to decrease while Vin goes through a negative excursion and returns to positive values. Exercise Repeat the above example for different values of RL with C1 constant.32(b). thereby turning D1 on and forcing Vout = Vin . At some point.28. Example 3. we recognize that Vout behaves as before until t = t1 .on if the diode voltage is assumed relatively constant. We must therefore repeat our analysis with RL present.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.on at t = t1 .75) RL C1 must be much (3.34). the (peak-to-peak) amplitude of the ripple. VR .on exp R.34 Ripple at output of a rectiﬁer. (b) t Vout t = Vp . for 1. 3.76) (3. Since Vout = Vp .on . t1 .C 0 t t3 . VD. thus.on C : RL 1 . 3.on 1 . VD.on D1 V in C1 RL Vout Vp V in t1 t3 t4 t2 t V out VR (a) Figure 3.32(b) must remain below 5 to 10% of the input peak voltage. VD.cls v. To ensure a small ripple. To this end. L 1 where we have chosen t1 = 0 for simplicity. greater than t3 . the value of C1 is chosen large enough to yield an acceptable ripple. noting that exp. the discharge of C1 through RL can be expressed as: V p − V D. R tC L 1 t Vp . 2007 at 13:42 92 (1) 92 Chap. VD. 3 Diode Models and Circuits Ripple Amplitude In typical applications. If the maximum current drawn by the load is known. (3. VD.77) Vout t Vp . 1 . we must compute VR analytically (Fig. Vp . 2006] June 30. in Fig.

VD.15 This result should not come as a surprise because the nearly constant voltage across RL results in a relatively constant current equal to Vp .CVD. a falling ramp—as if a constant current equal to Vp . where T = t4 . t1 = Tin . Thus.80) This section can be skipped in a ﬁrst reading. .on =RL discharges C1 .on Tin RL C1 p VR . VR = Vp . I = CdV=dt and hence dV = I=C dt.79) (3. VD. The ﬁrst term on the right hand side represents the initial condition across C1 and the second term. t3 is equal to the input period. T .on Tin C T : R L 1 (3. then the diode turns on for only a brief period. Since t4 . VD. The peak-to-peak amplitude of the ripple is equal to the amount of discharge at t = t3 . L 1 fin 15 Recall that (3. we write t3 . .on .78) Recognizing that if C1 discharges by a small amount. t3 denotes the time during which D1 is on. VD.on =RL . Tin . we can assume T Tin and hence VR Vp .

RL = 0:436 . thereby demanding that the circuit following the rectiﬁer tolerate such a large.80) as the load current. (3. that the diode current in forward bias consists of two components: (1) the transient current drawn by C1 . 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. A halfwave rectiﬁer follows the transformer to supply the power to the laptop computer of Example 3. Vp sin !in t1 = Vp . Which mains frequency gives a more desirable choice of C1 ? In many cases. weight. Repeating the above analysis with the load represented by a constant current source or simply viewing Vp . We recognize from Fig.25.on =RL in Eq. 2006] June 30.1 V.84) . Exercise Repeat the above example for 220-V. periodic variation.on = 0:8 V. IL . (3.82) C1 = Vp . the power dissipated in the diode (= VD ID ) may raise the junction temperature so much as to damage the device. limitations on size. assuming the transformer still produces a peak-to-peak swing of 9 V. For a given junction doping proﬁle and geometry.81) (3.5 Applications of Diodes 93 where fin .5 V. = Tin1. The peak diode current therefore occurs when the ﬁrst component reaches a maximum. approximately equal to Vp .35. i. Thus. e.. and Tin = 16:7 ms. we note that the point at which D1 turns on is given by Vin t1 = Vp . and (2) the current supplied to RL .30(b) that the diode must exhibit a reverse breakdown voltage of at least 2 Vp .83) Diode Peak Current We noted in Fig. 3. VR . 0. VD. the current drawn by the load is known..cls v. This section can be skipped in a ﬁrst reading. weight. we can write VR = CIL : f 1 in (3.on Vp for simplicity.g.on =RL . VD. and cost of the capacitor. In fact. 2007 at 13:42 93 (1) Sec. (3. 60-Hz line voltage to a peak-to-peak swing of 9 V. 50-Hz line voltage. VR . for Vin t = Vp sin !in t. The designer must trade the ripple amplitude with the size. 3.e. Thus.on Tin VR RL = 1:417 F: This is a very large value. C1 dVout =dt. at the point D1 turns on because the slope of the output waveform is maximum. We have Vp Solution = 4:5 V. Example 3. and cost of the adaptor may dictate a much greater ripple. Determine the minimum value of the ﬁlter capacitor that maintains the ripple below 0. VD. if the current exceeds a certain limit. Another important parameter of the diode is the maximum forward bias current that it must tolerate. Assuming VD.27 A transformer converts the 110-V. Assume VD.

and hence sin !in t1 = 1 .cls v.88) 2 V Ip = C1 !in Vp 1 . 3 Diode Models and Circuits D1 V in C1 RL V out Vp − VR V in Vout Vp t1 t Figure 3. L which. reduces to (3.on neglected. 2007 at 13:42 94 (1) 94 Chap. 1 .85) V ID1 t = C1 dVout + Rp dt This current reaches a peak at t = t1 : V = C1 !in Vp cos !in t + Rp : L L (3.35 Rectiﬁer circuit for calculation of ID .86) (3.85).87) V Ip = C1 !in Vp cos !in t1 + Rp . 2006] June 30. VR : V p With VD. VR + Rp Vp L s 2 V V = C1 !in Vp 2V R . from (3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VR + Rp : Vp2 p L Since VR s . we also have Vout t Vin t. obtaining the diode current as (3.

28 Solution 0 and C1 = 1:417 F.91) V V Rp RLC1 !in 2V R + 1 : L p Determine the peak diode current in Example 3.27 assuming VD. !in = 260 Hz. RL = 0:436 .90) Vp . = 4:5 V. (3. Thus. we neglect the second term under the square root: V V Ip C1 !in Vp 2V R + Rp p L s (3. Ip = 517 A: (3.89) (3.92) Example 3.93) . and VR = 0:1 V.on We have Vp s ! (3.

Can we combine these circuits to realize a full-wave rectiﬁer? We may attempt the circuit in Fig. We ﬁrst implement a circuit that performs this function [called a “full-wave rectiﬁer” (FWR)] and next prove that it indeed exhibits a smaller ripple. 3. 3.36 (a) Input and output waveforms and (b) input/output characteristic of a full-wave rectiﬁer. no rectiﬁcation is performed because the negative half cycles are not inverted. if Vin 0.37(c): we must ﬁrst design a half-wave rectiﬁer that inverts. Thus.1).37(f)]. the idea is to pass both positive and negative half cycles to the output.37(d) and (f) to form a full-wave rectiﬁer. yielding a zero current through RL and hence Vout = 0.cls v. we also compose that in Fig. We begin with the assumption that the diodes are ideal to simplify the task of circuit synthesis. positive half cycles. 3. Conversely. unfortunately. where one blocks negative half cycles and the other. both D2 and D1 are on and Vout = . 2006] June 30. i.37(f). 3. 3. 3.. if Vin 0. which can also be redrawn as in Fig. 3.Vin .. Note that the current drawn by C1 is much greater than that ﬂowing through RL . In analogy with this circuit. allowing the ﬁlter capacitor to be discharged by the load for almost the entire period.36(b) depicts the desired input/output characteristic of the full-wave rectiﬁer.37(d)] and the positive half cycles through D3 and D4 with no sign reversal [as in Fig. 3.” Let us summarize our thoughts with the aid of the circuit shown in Fig. Consider the two half-wave rectiﬁers shown in Fig. 3. Full-Wave Rectiﬁer The half-wave rectiﬁer studied above blocks the negative half cycles of the input. Depicted in Fig.38(b).37(e) for simplicity. The circuit therefore suffers from a large ripple in the presence of a heavy load (a high current). we can now combine the topologies of Figs. Figure 3. but with the negative half cycles inverted (i. D2 and D1 are on and D3 and D4 are off. both diodes are off.e. reducing the circuit to that shown in Fig. 3. Here.37(b). 3. i. the resulting circuit passes the negative half cycles through D1 and D2 with a sign reversal [as in Fig. This conﬁguration is usually drawn as in Fig. the output contains both positive and negative half cycles. but. Shown in Fig.e. 3. 3. which simply blocks the negative input half cycles.37(a). It is possible to reduce the ripple voltage by a factor of two through a simple modiﬁcation.5 Applications of Diodes 95 This value is extremely large. the problem is reduced to that illustrated in Fig. 3. multiplied by .38(b) and called a “bridge rectiﬁer. Exercise Repeat the above example if C1 = 1000 F.38(a). y (t ) t V in t (a) Vout Vout t x (t ) t (b) Figure 3. 2007 at 13:42 95 (1) Sec..BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Illustrated in Fig.38(c) and . If Vin 0. Vout = 0 for Vin 0 and Vout = Vin for Vin 0. 3.e.36(a). Note the polarity of Vout in the two diagrams. With the foregoing developments.37(d) is such a topology.

(b) no rectiﬁcation. the bridge is simpliﬁed as shown in Fig.on may pose difﬁculty if Vp is relatively small and the output voltage must be close to Vp . 3. VD. (d) realization of (c). and Vout = Vin .on for Vin 0. 3 Diode Models and Circuits RL (a) (b) D2 D2 ? D3 Vout Vin RL D4 Vout RL Vin D1 RL Vout Vin RL D1 (c) (d) (e) (f) Figure 3. Example 3.38 (a) Full-wave rectiﬁer.Vin .on . 2007 at 13:42 96 (1) 96 D1 RL D2 RL Chap. 3.on and “tracks” the input for jVin j VD. (b) simpliﬁed diagram.37 (a) Rectiﬁcation of each half cycle.28 produces Vout = Vin . (c) current path for negative input. yielding Vout = . (f) path for positive half cycles. the half-wave rectiﬁer in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.38(c) and (d) reveal that the circuit introduces two forward-biased diodes in series with RL . On the other hand. plot the input/output characteristic of a full-wave rectiﬁer. 2VD.Vin . How do these results change if the diodes are not ideal? Figures 3. 2006] June 30.cls v. The drop of 2VD. yielding Vout = . (d) current path for positive input.29 Assuming a constant-voltage model for the diodes.38(d). The output remains equal to zero for jVin j Solution 2VD. if Vin 0.on . (c) rectiﬁcation and inversion. By contrast. D2 Vin RL Vout Vin D4 (a) (b) Vout RL D3 D1 D2 Vin D4 (c) D3 Vin D1 D2 D3 D4 D1 (d) Figure 3. (e) path for negative half cycles.

(3. 3.CVf .on ? We now redraw the bridge once more and add the smoothing capacitor to arrive at the complete design [Fig.on +2V D.5 Applications of Diodes 97 with a slope of unity. 3. (b) equivalent circuit.40(a)].cls v. Since the capacitor discharge occurs for about half of the input cycle.on VR 2 Vp .39 plots the result.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.40 (a) Ripple in full-wave rectiﬁer.on t Figure 3. 2007 at 13:42 97 (1) Sec. (3. Figure 3.80): V in t D4 D1 RL C 1 Vout V out t (a) D2 Vin D3 A D2 Vin B D4 V D. R L 1 in where the numerator reﬂects the drop of 2VD.94) . 2006] June 30.on due to the bridge. 1 2 D. Exercise What is the slope of the characteristic for jVin j 2VD. Vout Vout V in t −2 V D.39 Input/output characteristic of full-wave rectiﬁer with nonideal diodes.on D1 RL C 1 Vout D3 (b) Figure 3. the ripple is approximately equal to half of that in Eq.

A similar argument applies to the other diodes.on for Vin +2VD. 2007 at 13:42 98 (1) 98 Chap. the diode currents appear as shown in Fig. The results of our study are summarized in Fig.on and Vout = Vin .on RL Figure 3. Assume no smoothing capacitor is connected to the output. In Problem 38. 3. Exercise Sketch the power consumed in each diode as a function of time.on I D1 = I D2 RL t I D3 = I D4 t − Vp − 2V D. Another point of contrast between half-wave and full-wave rectiﬁers is that the former has a common terminal between the input and output ports (node G in Fig. VD.2VD. While using two more diodes.on + Vout = Vp .Vin + 2VD. the full-wave rectiﬁer offers another important advantage: the maximum reverse bias voltage across each diode is approximately equal to Vp rather than 2Vp .16 16 The four diodes are typically manufactured in a single package having four terminals.42. we study the effect of shorting the input and output grounds of a fullwave rectiﬁer and conclude that it disrupts the operation of the circuit. As illustrated in Fig. is simply equal to VD. well justifying their use in adaptors and chargers. 3.on for Vin . full-wave rectiﬁers exhibit a lower ripple and require only half the diode breakdown voltage. 3. two of the diodes carry a current equal to Vout =RL and the other two remain off. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we have Vout = . 3. when Vin is near Vp and D3 is on. Example 3. From Figs. 3 Diode Models and Circuits In addition to a lower ripple. Thus.28).on.40(b). 3.cls v.30 Plot the currents carried by each diode in a bridge rectiﬁer as a function of time for a sinusoidal input. In each half cycle. whereas the latter does not.38(c) and (d).41.41 Currents carried by diodes in a full-wave rectiﬁer.on . . VAB . the voltage across D2 . Solution V in t Vp − 2V D. 2VD.

p = 3:6 V + 2VD.31 Design a full-wave rectiﬁer to deliver an average power of 2 W to a cellphone with a voltage of 3. 2007 at 13:42 99 (1) Sec.on Vout V in t V in V out t Reverse Bias (a) 2 Vp Reverse Bias (b) Vp Figure 3.99) Exercise If cost and size limitations impose a maximum value of 1000 F on the smoothing capacitor. we determine the minimum value of the smoothing capacitor that ensures VR 0:2 V. Example 3. 2006] June 30.on .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 V. Since the output voltage is approximately equal to Vp .on Vin D2 D3 D4 D1 RL C1 Vp − 2V D.97) (3.83) for a full-wave rectiﬁer gives VR = 2CILf For VR W = 32:6 V 2C1f : 1 in 1 in (3.98) = 0:2 V and fin = 60 Hz. Rewriting Eq.95) (3.42 Summary of rectiﬁer circuits.on 5 :2 V : (3.2 V. Next. 2VD. C1 = 23. the transformer preceding the rectiﬁer must step the line voltage (110 Vrms or 220 Vrms ) down to a peak value of 5.6 V and a ripple of 0. Solution We begin with the required input swing. (3.5 Applications of Diodes 99 D1 V in C1 RL V p − V D. what is the maximum allowable power drain in the above example? .cls v. 000 F: The diodes must withstand a reverse bias voltage of 5.96) Thus. 3. (3.2 V. we have Vin.

the ﬁnite output impedance of the transformer leads to changes in Vout if the current drawn by the load varies. Operating in the reverse breakdown region. Unfortunately.40(a) is often followed by a “voltage regulator” so as to provide a constant output. possibly exceeding the maximum level that can be tolerated by the load (e. 2006] June 30. For these reasons.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.43 as a more versatile adaptor having a nominal output of 3VD.8)]. the signal cannot turn actual diodes on and off. Is it possible to use the half-wave or full-wave rectiﬁers studied above? Solution No. a cellphone). resulting in a zero output..5. We have already encountered a voltage regulator without calling it such: the circuit studied in Example 3. 3. (3. . D1 exhibits a small-signal resistance. the circuit of Fig. rD . 3. For such signal levels. a subject studied in Chapter 8. We wish to generate a dc voltage representing the signal amplitude [Eq. 2007 at 13:42 100 (1) 100 Chap. the peak amplitude produced by the transformer and hence the dc output vary considerably.4 V.g. the ripple may become seriously objectionable in many applications. We may therefore arrive at the circuit shown in Fig. if the adaptor supplies power to a stereo. 3. Moreover. it is not. thus providing a relatively constant output despite input variations if rD R1 . the output voltage varies with the load current.44(a) shows another regulator circuit employing a Zener diode.on 2:4 V. Owing to its small amplitude.43 Voltage regulator block diagram. Figure 3. incurring only an 11-mV change in the output for a 100-mV variation in the input.8 V is added to the desired signal? 3. Diode Bridge R1 Vin C1 Load Figure 3.22. as studied in Example 3. Furthermore. the 120-Hz ripple can be heard from the speakers. in the range of 1 to 10 . Exercise What if a constant voltage of 0.cls v. “precision rectiﬁcation” is necessary.44(b): This section can be skipped in a ﬁrst reading.17 provides a voltage of 2. For example.32 A radio frequency signal received and ampliﬁed by a cellphone exhibits a peak swing of 10 mV.2 Voltage Regulation The adaptor circuit studied above generally proves inadequate. Due to the signiﬁcant variation of the line voltage. This can be seen from the small-signal model of Fig. 3 Diode Models and Circuits Example 3.

In the circuit of Fig. 2006] June 30. R1 = 100 . 3.100) For example.cls v. 3. (c) load regulation. poor stability if the load current varies signiﬁcantly. Our brief study of regulators thus far reveals two important aspects of their design: the stability of the output with respect to input variations.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.33 Constant (a) (b) (c) Figure 3. 2007 at 13:42 101 (1) Sec. The former is quantiﬁed by “line regulation. VD.101) (3.103) (3. if rD = 5 and R1 = 1 k . (3. Vin has a nominal value of 5 V. We ﬁrst determine the bias current of D1 and hence its small-signal resistance: Solution ID1 = Vin .7 V and a small-signal resistance of 5 . V in R1 Vout D1 D2 VD. VD2 R1 = 15 mA: Thus. then changes in Vin are attenuated by approximately a factor of 200 as they appear in Vout . and D2 has a reverse breakdown of 2.102) rD1 = IVT D1 = 1:73 : (3. Assuming VD.104) .” deﬁned as Vout =IL .” deﬁned as Vout =Vin . (b) small-signal equivalent of (a). determine the line and load regulation of the circuit.on VDz v in R1 v out r d1 r d2 v in R1 r d1 r d2 v out iL Example 3.45(a).on 0:8 V for D1 .44 (a) Regulator using a Zener diode. The Zener regulator nonetheless shares the same issue with the circuit of Fig.5 Applications of Diodes R1 Vout D1 R1 v out rd 101 V in v in (a) (b) Figure 3. D vout = r r+ R vin : D 1 (3. and the stability of the output with respect to load current variations.45 Circuit using two diodes. namely.43.on . 3. (b) small-signal equivalent. and the latter by “load regulation.

107) vout = r + r jjR D1 D2 1 iL = 6:31 : (3.48(a).31-mV change in the output voltage. 3. and as the input level exceeds a “threshold” or “limit. The nonlinear input-output characteristic suggests that one or more diodes must turn on or off as Vin approaches VL .3 Limiting Circuits Consider the signal received by a cellphone as the user comes closer to a base station (Fig. translating to the input/output characteristic shown in Fig.cls v.5.109) This value indicates that a 1-mA change in the load current results in a 6. we have vout rD1 + rD2 jjR1 = .45(c) (where vin = 0 to represent a constant input). we assume the input is constant and study the effect of load current variations. It is therefore desirable to “limit” the signal amplitude at a suitable point in the receiver. Vout = Vin . 2007 at 13:42 102 (1) 102 Chap. In .48(b). (3. 3. a signal applied to the input emerges at the output with its peak values “clipped” at VL . We now implement a circuit that exhibits the above behavior.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the circuit must simply pass the input to the output. As the distance decreases from kilometers to hundreds of meters.44(b).46 summarizes the results of our study in this section. This behavior must hold for both positive and negative inputs.47). Figure 3.” the output must remain constant. 3.105) (3. e. 3. How should a limiting circuit behave? For small input levels. Exercise Repeat the above example for R1 = 50 and compare the results.iL: That is.106) For load regulation. D1 Vin C1 Load Vin Load Vin Load Figure 3.46 Summary of regulators. Using the small-signal circuit shown in Fig.g. 2006] June 30. As illustrated in Fig..108) (3. we compute the line regulation as vout = rD1 + rD2 vin rD1 + rD2 + R1 = 0:063: (3. 3. 3 Diode Models and Circuits From the small-signal model of Fig. the signal level may become large enough to “saturate” the circuits as it travels through the receiver chain. 3.

34 = 800 mV. where the positive half cycles of the input are clipped at 0 V and +1 V.49(a). Note that VB 1 can be positive or negative to shift VL to higher or lower values. . we postulate that a constant voltage source in series with D1 shifts the limiting point. 3. First. accomplishing this objective. the resulting circuit limits at VL = VB 1 + VD.. (b) response to a sinusoid. the negative values of Vin must also experience limiting. then the circuit limits at Vin = . Figure 3.11(b) and (c). To serve as a more general limiting circuit. the source in series with D2 must be positive and equal to 700 mV. we have already seen simple examples in Figs. Since the positive limiting point must shift to the left. 3. Similarly.5 Applications of Diodes 103 Base Station Receiver Base Station Receiver (a) Figure 3. 3.11(c).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3.52(b) shows the result. Second.48 (a) Input/output characteristic of a limiting circuit. Thus. we recognize that if the anode and cathode of D1 are swapped.on thereafter.VD. e.51). 2006] June 30. A signal must be limited at 100 mV. 3. VL . the limiting level.on . respectively.g.47 Signals received (a) far from or (b) near a base station.50(b). the above topology must satisfy two other conditions. Beginning with the circuit of Fig. As illustrated in Fig.cls v. as shown in Fig. We reexamine the former assuming a more realistic diode. 2007 at 13:42 103 (1) Sec.on . design the required limiting Solution Figure 3.on circuit. 3. (b) Vout Vout + VL − VL + VL − VL Vout + VL − VL + VL V in V in − VL t t (a) (b) Figure 3.49(b). Vout is equal to Vin for Vin VD.52(a) illustrates how the voltage sources must shift the break points. must be an arbitrary voltage and not necessarily equal to VD. inserting constant voltage sources in series with the diodes shifts the limiting points to arbitrary levels (Fig. 3.on and equal to VD. 3. the voltage source in series with D1 must be negative and equal to 700 mV. two “antiparallel” diodes can create a characteristic that limits at VD.on [Fig.on .50(a)]. Inspired by the circuit of Fig. Example 3. respectively. Finally. Assuming VD.49(a). the constant-voltage model. Depicted in Fig. 3. fact.

3 Diode Models and Circuits Vout R1 V in D1 Vout V D.on V in Vout V D. so does the current through the diode that is forward biased and hence the diode voltage.. 3. e. First. in the circuit of Fig. Exercise Before concluding this section.on + V B1 t V in t (b) Figure 3.on t t (a) Vout R1 D1 VB1 V D. e.Q. 3.53). However.. “Voltage doublers” may serve this purpose. as Vin increases. we have thus far assumed Vout = Vin for . Second. Vout = Vin . to charge one plate of a capacitor to +Q. This is because. the voltage across C1 cannot change even if Vin changes because the right plate 17 Recall that VD = VT lnID =IS . the circuits studied above actually display a nonzero slope in the limiting region (Fig. Thus. Repeat the above example if the positive values of the signal must be limited at +200 mV and the negative values at .4 Voltage Doublers Electronic systems typically employ a “global” supply voltage.18 Before studying doublers. 18 Voltage doublers are an example of “dc-dc converters. 6 V. First.VL Vin +VL. requiring that the discrete and integrated circuits operate with such a value. but it is possible to realize a non-unity slope in the region. 2007 at 13:42 104 (1) 104 Chap. the design of some circuits in the system is greatly simpliﬁed if they run from a higher supply voltage.54(a). the other plate must be charged to . (2.17 Nonetheless. we make two observations. (b) limiter with level shift.49 (a) Simple limiter. 2006] June 30.on V D.cls v. This section can be skipped in a ﬁrst reading.g.5.1:1 V.g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the 60-mV/decade rule expressed by Eq. 3.on + V B1 V in Vout V D. it is helpful to review some basic properties of capacitors. 3 V.109) implies that this effect is typically negligible.on + V B1 Vout V D.” .

To determine the change in Vout .on − V D. Note that all four plates receive or release equal amounts of charge because C1 and C2 are in series.on − V B2 V D.5 Applications of Diodes R1 Vout − V D.on Vout + V D. we write the change in the charge on C2 as Q2 = C2 Vout . Second. Vout R1 − V D.on − V B2 t Figure 3. a capacitive voltage divider such as that in Fig.on + V B1 V in Vout t V in D1 VB1 D2 VB2 Vout − V D. 2006] June 30. of C1 cannot receive or release charge (Q = CV ).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the left plate of C1 receives positive charge from Vin . Vout .on + V D. the voltage change across C1 is equal to C2 Vout =C1 . This is an important observation.on Vout V in t D1 D2 Vout t (b) Figure 3. (b) limiter for both half cycles. an input change Vin directly appears at the output.on 105 Vout V in t V in D1 Vout t (a) R1 V in − V D.on − V D. 3.54(b) operates as follows.110) .cls v.51 General limiter and its characteristic. Since VC 1 remains constant. resulting from Vin . Adding these two voltage changes and equating the result to Vin . Having lost negative charge.50 (a) Negative-cycle limiter. we have Vin = C2 Vout + Vout : C 1 (3.on + V B1 V D. which also holds for C1 : Q2 = Q1 . 2007 at 13:42 105 (1) Sec. If Vin becomes more positive. thus requiring that the right plate absorb negative charge of the same magnitude from the top plate of C2 . Thus. and hence the bottom plate absorbs negative charge from ground. the top plate of C2 equivalently holds more positive charge. 3.

cls v. 3.31: the voltage across the diode in the peak detector exhibits an average value of .on −100 mV + V D.52 (a) Example of a limiting circuit.53 Effect of nonideal diodes on limiting characteristic. we derive the output waveform from a different perspective so as to gain more insight. For further investigation. 3. we note that as Vin exceeds zero. we redraw the circuit as shown in Fig. 2007 at 13:42 106 (1) 106 Chap.55. 3. Assuming an ideal diode and a zero initial condition across C1 . the circuit of Fig.2Vp (with respect to zero). 3 Diode Models and Circuits Vout + V D. (b) input/output characteristic. As our ﬁrst step toward realizing a voltage doubler.Vp and. except that C1 (rather than C2 ) appears in the numerator. That is. recall the result illustrated in Fig. a peak value of . While Vout in this circuit behaves exactly the same as VD1 in Fig.54 (a) Voltage change at one plate of a capacitor.30(a).on +100 mV (a) R1 D1 D2 V in V in Vout 700 mV (b) Figure 3.111) This result is similar to the voltage division expression for resistive dividers. where the diode and the capacitors are exchanged and the voltage across D1 is labeled Vout . Vout = C C1 C Vin : 1+ 2 (3.54(a) is a special case of the capacitive divider with C2 = 0 and hence Vout = Vin . 2006] June 30. Interestingly.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3. V C1 ∆V in V in C1 Vout ∆V in V in C1 C 2 Vout (a) (b) Figure 3. the input tends to place positive charge on the left plate of C1 and hence draw negative . more importantly. Vout V in Figure 3. (b) voltage division.

Consequently.19 As the input rises toward Vp . 2006] June 30.54(a). reducing the circuit to that in Fig.35 V out V in C1 t D1 Vout V in t2 V in V in V in (a) (b) t4 t Vp t1 Figure 3. the output simply tracks the changes in the input while C1 sustains a constant voltage equal to Vp . the voltage across C1 remains equal to Vin because its right plate is “pinned” at zero by D1 . . Vin begins to fall and tends to discharge C1 .2Vp .Vp . 2007 at 13:42 107 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.e. D1 turns on. +2 V p Example 3. 3. charge from D1 .5 Applications of Diodes t1 V out V in −Vp 107 0 t V in C1 D1 Vout V in V in t1 t −2 V p −Vp (b) (a) Figure 3. 3. The diode therefore turns off. Plot the output waveform of the circuit shown in Fig.cls v. forcing Vout = 0. requiring that V out rise and D1 1 turn on. After t = t1 .. the output goes from zero to .55 (a) Capacitor-diode circuit and (b) its waveforms.56 if the initial condition across C1 is zero. 19 If we assume D does not turn on.54(a). From this time. i.31(b). 3. then the circuit resembles that in Fig. and the cycle repeats indeﬁnitely. 3. In particular. The output waveform is thus identical to that obtained in Fig. draw positive charge from the left plate and hence from D1 .56 Capacitor-diode circuit and (b) its waveforms. as Vin varies from +Vp to . 3.

3.56 with the peak detector of Fig.. C1 is 1 V more positive than its left plate at We have thus far developed circuits that generate a periodic output with a peak value of . at which point the direction of the current through C1 and D1 must change. since the peak detector “loads” the ﬁrst stage when D2 turns on. We surmise that if these circuits are followed by a peak detector [e. . combining the circuit of Fig. Thus. 3. As Vin falls below zero. In this case. attempting to place positive charge on the left plate of C1 and hence draw negative charge from D1 . Now. we must still analyze this circuit carefully and determine whether it indeed operates as a voltage doubler.57(a) exempliﬁes this concept.Vp and +Vp .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.57 Voltage doubler circuit and its waveforms. We assume ideal diodes. turning D1 off. C1 carries a voltage equal to Vp and transfers the input change to the output. 2007 at 13:42 108 (1) 108 Chap. C1 V in X D1 D2 C 2 Vout V out Vp t V in Vp 2 t1 C1 V in C2 C1 V in C1 V in C2 t2 t3 t4 t5 t V in C2 C1 C 2 Vp V in C2 C1 Figure 3. turning D1 on and forcing Vout = 0. After t = t1 .. reaching a peak value of +2Vp . the output tracks the input but with a level shift of +Vp . C1 directly transfers the input change to the output for the entire positive half cycle.2Vp or +2Vp for an input sinusoid varying between .30(a). the diode turns off.2Vp or +2Vp may be produced. Solution Exercise Repeat the above example if the right plate of t = 0. Of course. and C1 = C2 . Fig. then a constant output equal to . Figure 3. D1 turns on. As a result. zero initial conditions across C1 and C2 . the voltage across C1 remains equal to Vin until t = t2 . the input tends to push negative charge into C1 . 3. 3 Diode Models and Circuits As Vin rises from zero.30(a)].cls v.e. i. the analysis is simpliﬁed if we begin with a negative cycle. 2006] June 30.g.

D2 turns off. both D1 and D2 are off. approaching a ﬁnal value of Vout = 1 Vin . and each capacitor holds a constant voltage. our objective was to generate an output equal to 2Vp rather than Vp .Vp to 0.Vp at t = t4 . falling to zero at t = t3 . the circuit reduces to a simple capacitive divider that follows Eq. Vout increases from +Vp to +Vp + Vp =2 as Vin goes from 0 to +Vp . As Vin begins to rise again. For t t1 . the voltage across C1 reaches . D2 turns on at t = t5 . and vary sinusoidally but with an amplitude equal to Vp =2.111): because C1 = C2 . 2 = 2Vp : .) As a result. The output has now reached 3Vp =2. 3.112) 1 Vout = Vp 1 + 1 + 4 + 2 = Vp 1 1.cls v. i. with the right plate of C1 ﬂoating. In other words.. But patience is a virtue and we must continue the transient analysis.20 Thus. D1 turns off and D2 remains off because VX = 0 and Vout = +Vp .e. The reader may wonder if something is wrong here. forming a capacitive divider again. What happens after t = t2 ? Since Vin begins to fall and tends to draw charge from C1 . allowing C1 to charge to . 3. in each input cycle. Vp =4. raising VX and hence turning D2 on. As is evident from the foregoing analysis. a change of 2Vp in Vin appears as a change equal to Vp in VX and Vout . the voltage across C1 is zero because both Vin and Vout are equal to +Vp .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Thus. the output continues to rise by Vp . How does D2 behave in this regime? Since Vin is now rising. At this point. turning D2 on.. Since the voltage across C1 is zero. Note at t = t2 .Vp . reaching +Vp as Vin goes from . (If D2 remains off.5 Applications of Diodes 109 pinning node X to zero.57. Vp =2. etc. For t t2 . Thus. At t = t1 . from t1 to t2 . turning D1 off and yielding the circuit shown in Fig. Now. D2 remains off and Vout = 0. 2007 at 13:42 109 (1) Sec. VX tracks the change at the input. 2 (3. (3. VX and Vout begin from zero. maintaining Vout at +Vp . 2006] June 30. After this time. the output change is equal to half of the input change. for t t1 . then C1 simply transfers the change in Vin to node X . VX = Vin . D1 turns on again. remain equal. the input begins to rise and tends to deposit positive charge on the left plate of C1 . we postulate that VX also tends to increase (from zero).

we construct the plot shown in Fig. (3.36 Solution 20 As always. From t = t1 to t = t3 . and writing the current as ID1 = .. repeating the same behavior in subsequent cycles. 3.e. 1 remains off) and arrive at a conﬂicting result. immediately after t = 0.113) (3.115) The reader is encouraged to continue the analysis for a few more cycles and verify this trend. Sketch the current through D1 in the doubler circuit as function of time. the reader is encouraged to assume otherwise (i.e.58(b). noting that D1 and C1 carry equal currents when D1 is forward biased. i. D1 conducts and the peak current corresponds to the maximum slope of Vin .C1 dVin =dt. I D . Using the diagram in Fig. 3.114) (3. Example 3. 21 As usual.21 For 0 t t1 .. the diode remains off. D1 denotes the current ﬂowing from the anode to the cathode.58(a).

an ampliﬁer) may not operate properly with the present dc level. 22 The diode is drawn vertically to emphasize that Vout is lower than Vin . we This section can be skipped in a ﬁrst reading. Also..on . to obtain a shift of place two diodes in series. Sustaining a relatively constant voltage in forward bias.58 Diode current in a voltage doubler. a diode can be viewed as a battery and hence a device capable of shifting the signal level. we consider the circuit shown in Fig.22 If the current pulled by the next stage is negligible (or at least constant). Exercise Plot the current through D2 in the above example as a function of time. we apply the input to the cathode. Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. establishing VD. 2VD. 2007 at 13:42 110 (1) 110 V in t1 C1 V in C2 C1 V in C1 V in C2 Chap.cls v. 3.g. In our ﬁrst attempt. where I1 draws a constant current.on across D1 . 3 Diode Models and Circuits t4 t5 t2 t3 t V in C2 C1 C 2 Vp V in C2 C1 I D1 t1 t2 t3 t4 t Figure 3. However. Vout is simply lower than Vin by a constant amount. Example 3.5 Diodes as Level Shifters and Switches In the design of electronic circuits. . 3. 3.59(a) as a candidate for shifting the level down by VD. the diode current remains unknown and dependent on the next stage. we may need to shift the average level of a signal up or down because the subsequent stage (e.37 Solution To shift the level up. To alleviate this issue we modify the circuit as depicted in Fig. Design a circuit that shifts up the dc level of a signal by 2VD.60 shows the result.on .5. 2006] June 30. VD.59(b).on .on .

many applications employ the topology shown in Fig. To resolve this issue.on Vout I1 Vin Vout V D. the circuit is modiﬁed as shown in Fig.61(b)]. Exercise What happens if I1 is extremely small? The level shift circuit of Fig. the diode is forward-biased again.5 Applications of Diodes 111 Vin D1 Vin Vout D1 V D. the circuit reduces to that in Fig. so does D1 . If I1 is on. 2007 at 13:42 111 (1) Sec. With both I1 and I2 on.59 (a) Use of a diode for level shift. where the back-to-back diodes fail to conduct for any value of Vin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Let us replace S1 with the level shift circuit and allow I1 to be turned on and off [Fig.on Vout 2 V D. VD1 . evidently disconnecting C1 from the input and freezing the voltage across C1 . The assumption that D1 turns off holds only if C1 draws no current from D1 . 3. allowing C1 to store a value equal to Vin1 . Now consider the case illustrated in Fig. 3. We used the term “evidently” in the last sentence because the circuit’s true behavior somewhat differs from the above description. D1 turns on for part of the cycle. charging C1 with the input (in a manner similar to a peak detector). where I1 turns off at t = t1 . Vout tracks Vin with no level shift.on Vin Vin t Figure 3. 3. thereby isolating C1 from the input. VD. Thus. the two diodes and the two current sources form an electronic switch.60 Positive voltage shift by two diodes. . VCC I1 Vout 2 V D. 2006] June 30.61(e). even though I1 is off.61(d). the diodes operate in forward bias. only if Vin .Vout remains less than VD.cls v. For example.on . When I1 turns off. and I2 provides a bias current for D2 . As the input waveform completes a negative excursion and exceeds Vin1 at t = t2 . Vout .on . That is.59(b) can be transformed to an electronic switch. where D2 is inserted between D1 and C1 . 3.on (a) (b) t Figure 3.e. i. In other words.61(a) to “sample” Vin across C1 and “freeze” the value when S1 turns off. VX = Vin . (b) practical implementation. 3. 3. 3. When I1 and I2 turn off.on .61(c). Vout tracks Vin except for a level shift equal to VD. and Vout = VX + VD2 = Vin if VD1 = VD2 ..

C Vout = C =2j =2C Vin : j + 1 To ensure this “feedthrough” is small. 2006] June 30.62 shows the equivalent circuit for the case where the diodes are off. Study the effect of this capacitance on the operation of the above circuit. Speciﬁcally. (3.cls v. I I Example 3.61 (a) Switched-capacitor circuit. 2007 at 13:42 112 (1) 112 Chap.38 Recall from Chapter 2 that diodes exhibit a junction capacitance in reverse bias.62 Feedthrough in the diode switch. we have Vin C j1 C j2 C1 Vout Figure 3. C1 must be sufﬁciently large.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.116) Exercise Calculate the change in the voltage at the left plate of Cj 1 (with respect to ground) in terms of . (c) problem of diode conduction. D 1 turns off. suggesting that the conduction of the input through the junction capacitances disturbs the output. 3. invoking the capacitive divider of Fig. (b) realization of (a) using a diode as a switch. (e) equivalent circuit when 1 and 2 are off.54(b) and assuming Cj 1 = Cj 2 = Cj . Solution Figure 3. (a) (b) (c) t1 t2 t VCC CK Vin C1 CK I1 I1 Vout Vin C1 Vout (d) (e) Figure 3. (d) more complete circuit. 3 Diode Models and Circuits Vin Vin V in Vout C1 CK I1 D1 Vout C1 Vin D1 Vout I1 C1 CK Vout D 1 turns on.

When an electron is freed from a covalent bond. and a “depletion region” is formed.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3. A pn junction is a piece of semiconductor that receives n-type doping in one section and p-type doping in an adjacent section. Dp dp=dx. n ND i and hence p n2 =ND .6 Chapter Summary 113 Vin . assume VD. 1 . . conducting a very high current. Problems In the following problems. 3. i Charge carriers move in semiconductors via two mechanisms: drift and diffusion. The drift current density is proportional to the electric ﬁeld and the mobility of the carriers and is given by Jtot = q n n + p pE .63. The pn junction can be considered in three modes: equilibrium. typically in the range of 700 to 800 mV. reverse bias. 1. semiconductors are “doped” with certain impurities.on = 800 mV for the constant-voltage diode model. To increase the number of free carriers. the junction carries negligible current and operates as a capacitor. The bandgap energy is the minimum energy required to dislodge an electron from its covalent bond. addition of phosphorus to silicon increases the number of free electrons because phosphorus contains ﬁve electrons in its last orbital. For example. a constant-voltage model may be used in some cases to estimate the circuit’s response with less mathematical labor. The capacitance itself is a function of the voltage applied across the device. “Zener” or “avalanche” breakdown may occur.cls v. 2006] June 30. in an n-type material. Plot the I/V characteristic of the circuit shown in Fig. 2007 at 13:42 113 (1) Sec. The electric ﬁeld created in the depletion region eventually stops the current ﬂow. As the carriers cross. The electric ﬁeld in the depletion results in a built-in potential across the region equal to kT=q lnNA ND =n2 . The diffusion current density is proportional to the gradient of the carrier concentration and given by Jtot = q Dn dn=dx . they leave ionized atoms behind. np = n2 . 3. a “hole” is left behind. pn junctions break down. This condition is called equilibrium. sharp gradients of carrier densities across the junction result in a high current of electrons and holes. Under forward bias. Depending on the structure and doping levels of the device. the junction carries a current that is an exponential function of the applied voltage: IS expVF =VT . It also contains a small number of free electrons at room temperature. Upon formation of the pn junction. For doped or undoped semiconductors. i Under reverse bias.6 Chapter Summary Silicon contains four atoms in its last orbital. Under a high reverse bias voltage. and forward bias. For example. Since the exponential model often makes the analysis of circuits difﬁcult.

Assume VB IX R1 VX VB D1 Ideal 0. VX = V0 cos !t. R1 VB Figure 3. 2006] June 30.63 is expressed as VX = V0 cos !t.65. 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.64.1 V and VB = +1 V. In the circuit of Fig. plot IX as a function of VX for two cases: VB = . Assume VB = 2 V.66. plot IX and IR1 as a function of VX for two cases: VB = . 3.1 V and VB = +1 V. For the circuit depicted in Fig.69 using an ideal model for the diodes.68.64 for two cases: VB = . Plot IX and ID1 as a function of VX for the circuit shown in Fig. Plot IX as a function of VX for the circuit shown in Fig. 3 IX R1 D1 Ideal Diode Models and Circuits VX Figure 3. 3.1 V IX VX D1 Ideal VB = +1 V. For the circuit depicted in Fig. 8. 3. If the input in Fig. 3.65 and VB = +1 V. 3. 3. Plot the input/output characteristics of the circuits depicted in Fig. .63 2. 3. 3. 6. If in Fig.1 V and VB = +1 V. I D1 Figure 3.64 4. plot IX as a function of time for two cases: VB = . plot IX and IR1 as a function of VX for two cases: VB = .1 V and IX R1 VX D1 Ideal VB Figure 3.66 7. 2007 at 13:42 114 (1) 114 Chap. 3.67. plot the current ﬂowing through the circuit as a function of time. 5.

3. 2006] June 30. Assume a constant-voltage diode model. In the circuits of Fig.71. Repeat Problem 9 with a constant-voltage diode model. 3.71. 16. 13. 3. plot the output of each circuit in Fig. Plot Vout as a function of Iin for the circuits shown in Fig. 2007 at 13:42 115 (1) Sec.67 IX R2 I R1 VX R1 D1 VB Ideal Figure 3. Assuming the input is expressed as Vin = V0 cos !t. plot the current ﬂowing through R1 as a function of Vin .69 10.70 using an ideal model for the diodes. Repeat Problem 12 with a constant-voltage diode model. 17. Assuming a constant-voltage diode model. 18. Plot the input/output characteristics of the circuits shown in Fig.70 as a function of time.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume an ideal diode model. 3. plot the output of each circuit in Fig. 3. 3. plot Vout as a function of Iin for the circuits shown in Fig. 9 as function of time.72. 11. 12. Assume a constant-voltage model and a relatively large I0 . . plot Vout as a function of time if Iin = I0 cos !t.6 Chapter Summary IX R2 VX I R1 R1 D1 VB Ideal 115 Figure 3. If the input is given by Vin = V0 cos !t.68 R1 D1 VB (a) (b) D1 Vout V in VB V in VB R1 D1 (c) V in R1 Vout Vout D1 R1 VB (d) R1 Vout V in VB V in D1 Vout (e) Figure 3.71. 3.cls v. Assume a constant-voltage diode model. 15. Use an ideal diode model. 14. For the circuits illustrated in Fig.

70 I in R1 D1 Vout I in R1 D1 VB (b) Vout (a) I in D1 R1 VB Vout I in D1 (d VB Vout R1 (c) Figure 3.74 assuming a constantvoltage model. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . 3. assume Iin = I0 cos !t. Assume a constant-voltage diode model. Plot Vout as a function of time using a constant-voltage diode model. 3 Diode Models and Circuits D1 VB D1 Vout V in Vout V in R1 Vout (c) VB R1 D1 (d) D1 R1 VB (e) V in Vout V in Vout Figure 3. 20. For the circuits shown in Fig. where I0 is relatively large.73. plot Vout as a function of Iin assuming a constant-voltage model for the diodes. 21. 22. Plot the current ﬂowing through R1 as a function of Iin for the circuits of Fig. 2006] June 30. 23. Plot the input/output characteristic of the circuits illustrated in Fig.cls v.73. In the circuits depicted in Fig. 2007 at 13:42 116 (1) 116 R1 V in VB R1 D1 VB (a) (b) Chap.71 I in R1 D1 VB (a) Vout I in D1 R1 VB (b) Vout I in D1 VB Vout R1 (c) Figure 3. Assume a constant-voltage diode model. Plot the current ﬂowing through R1 in the circuits of Fig.72 as a function of Iin . 3. 3.72. 3.72 19.

27. Assume constant-voltage diode model. Plot the input/output characteristic of the circuits illustrated in Fig.6 Chapter Summary 117 D1 I in R1 D2 (a) Vout I in R1 D1 (b) D2 Vout I in R1 D1 (c) D2 Vout I in R1 D1 D2 Vout I in R1 D1 D2 D1 Vout I in D2 R1 (f) Vout (d) (e) D1 I in D2 R1 (g) D1 Vout I in D2 R1 (h) Vout Figure 3.76. 3. Assume constant-voltage diode model. 3.75 assuming a constantvoltage model. Assume constant-voltage diode model. 28.74. 3. . 29.76 assuming a constantvoltage model. Plot the input/output characteristic of the circuits illustrated in Fig. Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.75. 25. 3. 3. 3.77 assuming a constantvoltage model and VB = 2 V.74 24. Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig. Plot the input/output characteristic of the circuits illustrated in Fig. 2006] June 30. 3. Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig.73 D1 R1 R2 D1 R1 Vout V in R2 Vout V in (a) (b) Figure 3. 26.cls v. 2007 at 13:42 117 (1) Sec.

plot the output waveform of the circuit depicted in Fig. 3. 2006] June 30.cls v. Repeat Problem 34 for the circuit shown in Fig.80 for an initial condition of +0:5 V across C1 .on 800 mV for each diode. determine the change in Vout if Vin changes from +2:4 V to +2:5 V for the circuits shown in Fig. 34. 3.78. 3 D 1 VB Vout V in R1 Diode Models and Circuits Vout R2 (b) D1 V in R1 VB Vout R2 (c) R1 V in D1 VB Vout R2 (d) Figure 3.77.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. calculate the ripple amplitude if the frequency is 60 Hz. 3. 3. . For a 1000-F smoothing capacitor. 31. 3.on 800 mV for each diode. Assume Vp = 5 V. 35. Beginning with VD. 32. 3. Assume constant-voltage diode model. Assuming Vin = Vp sin !t. Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig.32 drives a 100.81. In Problem 32.79.1 mA in the circuits of Fig. 36. calculate the change in Vout if Iin changes from 3 mA to 3.76 30. 33. determine the change in the current ﬂowing through the 1-k resistor in each circuit.5 V. Suppose the rectiﬁer of Fig. 2007 at 13:42 118 (1) 118 D1 V in R1 R2 VB (a) Chap. Beginning with VD.load with a peak voltage of 3.75 V in D1 R1 Vout D2 R2 V in D1 R1 Vout D2 R2 (a) (b) D1 V in R1 D2 R2 Vout V in D1 D2 R1 Vout R2 (d) D1 V in R1 D2 Vout R2 (e) (c) Figure 3.

39. where V0 = 3 V and ! = 2 60 Hz. Plot the input-output characteristic assuming an ideal diode model and explaining why the circuit does not operate as a full-wave rectiﬁer. A full-wave rectiﬁer is driven by a sinusoidal input Vin = V0 cos !t. 3. a student mistakenly has swapped the terminals of D3 as depicted in Fig. 38. A 3-V adaptor using a half-wave rectiﬁer must supply a current of 0.5 A with a maximum ripple of 300 mV. Assume a constant-voltage diode model and VD VD. . 40. 42.78 37. determine the ripple amplitude with a 1000-F smoothing capacitor and a load resistance of 30 .on . Assume the input and output grounds in a full-wave rectiﬁer are shorted together.77 V in D1 Vout R 1 = 1 kΩ V in D1 Vout R 1 = 1 kΩ D2 (a) (b) V in D1 R1 1 kΩ Vout D2 V in R1 1 kΩ R2 (d) Vout 2kΩ D2 (c) Figure 3.cls v. 41. 3. 2006] June 30. Explain what happens.82. 2007 at 13:42 119 (1) Sec. Plot the voltage across each diode in Fig.on = 800 mV. Draw the output waveform with and without the load capacitor and explain why the circuit does not operate as a rectiﬁer. 3.38(b) as a function of time if Vin = V0 cos !t.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For a frequency of 60 Hz. While constructing a full-wave rectiﬁer. Assuming VD. Suppose the negative terminals of Vin and Vout in Fig.6 Chapter Summary R1 V in D1 VB D2 R2 (a) (b) 119 D1 Vout V in D1 VB R2 R1 Vout R1 V in D1 R2 D2 VB (c) (d) Vout V in D1 R1 Vout D2 VB R2 Figure 3. 3.38(b) are shorted together. compute the minimum required smoothing capacitor.

fin = 60 Hz.cls v.43. . the diodes carry a current of 5 mA and the load. 3.82 43. Suppose in Fig. and the peak voltage produced by the transformer is equal to 5 V. R1 = 1000 .79 V in D1 Vout C1 0. 2007 at 13:42 120 (1) 120 D1 Vout I in R 1 = 1 kΩ Chap. neglect the load. determine the ripple amplitude across the load.on 800 mV. (a) Assuming R1 carries a relatively constant current and VD. Also. 3. 3 Diode Models and Circuits D1 Vout I in R 1 = 1 kΩ D2 (a) (b) D1 I in R1 1 kΩ R1 Vout D2 I in 1 kΩ R2 (d) Vout 2kΩ D2 (c) Figure 3. C1 = 100 F. If the load current increases to 21 mA.5 V V in Figure 3. we estimate the ripple seen by the load in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For simplicity. (b) Using the small-signal model of the diodes.5 V Figure 3. 44.81 D2 Vin D4 Vout RL D3 D1 Figure 3.43 so as to appreciate the regulation provided by the diodes. estimate the ripple amplitude across C1 . a current of 20 mA. what is the change in the total voltage across the three diodes? Assume R1 is much greater than 3rd . In this problem. 2006] June 30.80 D1 Vout C1 0.

ideal diodes. 2006] June 30. How should the input-output characteristic be modiﬁed so that the output becomes a better approximation of a sinusoid? SPICE Problems In the following problems. 3. R1 = 500 and R2 = 1 k .5 0. 46. the maximum allowable current through each diode is 2 mA. Using ideal diodes and other components. VB 2 . . Using the transient analysis in SPICE.83 48. 3.5 +4V 0. Also.86 must deliver a current of 5 mA to R1 for a peak input level of 2 V. In the limiting circuit of Fig. Using 1-k resistors.VD. Plot the output waveform and note that it is a rough approximation of a sinusoid.85. Assume the input peak voltage is equal to 5 V. (The value of resistors is not unique. plot the currents ﬂowing through D1 and D2 as a function of time if the input is given by V0 cos !t and V0 VD. and other components. 2007 at 13:42 121 (1) Sec. (b) Verify the result by SPICE. 3. The half-wave rectiﬁer of Fig. The rectiﬁer shown in Fig.5 V in Figure 3.on + VB 1 and .87.51 for a negative threshold of .84 49. (a) Using hand calculations. 3. 3. Use SPICE to construct the input/output characteristic for .83.cls v. 52. construct the circuit.5 V in Figure 3. Vout +2V −2V +2V −2V 0. determine the required value of R1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.51. plot the current ﬂowing through R1 as a function of Vin . and VD.88 is driven by a 60-Hz sinusoid input with a peak amplitude of 5 V.) Suppose a triangular waveform is applied to the characteristic of Fig. “Wave-shaping” applications require the input/output characteristic illustrated in Fig. assume IS = 5 10.84 as shown in Fig.2 V Vin +2 V.V0 . 3.6 Chapter Summary 121 45.84. 47. In the circuit of Fig. 3.on 800 mV. construct a circuit that provides such a characterVout +2V −4 V −2V +2V −2V 0. 50. 3. Design the limiting circuit of Fig. 3.1:9 V and a positive threshold of +2:2 V.16 A. 3. istic.on . We wish to design a circuit that exhibits the input/output characteristic shown in Fig. 51.

(c) Compute the heaviest load (smallest RL ) that the circuit can drive while maintaining a ripple less than 200 mVpp . 53.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 54.2 V Vin +2 V and determine the maximum input range across which jVin .cls v. determine the values of VB 1 and VB 2 such that . Using the dc analysis in SPICE to plot the input/output characteristic for 0 Vin 4 V. 3. The circuit of Fig. 3 Diode Models and Circuits Vout +2V −4 V −2V +2V −2V 0.Vout j 5 mV.90 can provide an approximation of a sinusoid at the output in response to a triangular input waveform.5 V in V in t Figure 3.88 (a) Determine the peak-to-peak ripple at the output.87 D1 Vout V in 1 µF 100 Ω Figure 3. Plot the input/output characteristic for .5 +4V 0. 2007 at 13:42 122 (1) 122 Chap.89 is used in some analog circuits.86 R1 D2 D1 R2 in Vout Figure 3. The circuit shown in Fig. 3.85 D1 Vout V in R1 Figure 3. 2006] June 30. (b) Determine the peak current ﬂowing through D1 .

5 V 1 kΩ 123 D2 V in D4 D3 Vout D1 1 kΩ VEE = −2.89 the characteristic closely resembles a sinusoid. 2007 at 13:42 123 (1) Sec.90 . 2006] June 30.cls v.5 V Figure 3. 2 kΩ Vout D2 V B2 Vout 4V V in (a) (b) V in D1 V B1 Figure 3. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6 Chapter Summary VCC = +2.

with K = 0:001 . and develop an equivalent model that can be used in circuit analysis and design.. preparing ourselves for the study of circuits employing such devices. we analyze the structure and operation of bipolar transistors. where a voltage source Vin controls I1 and the output current ﬂows through a load resistor RL . Consider the voltage-dependent current source depicted in Fig. we aim to understand the physics of the transistor. 4. 2007 at 13:42 124 (1) 4 Physics of Bipolar Transistors The bipolar transistor was invented in 1945 by Shockley. and Bardeen at Bell Laboratories.1) Interestingly. Following the same thought process as in Chapter 2 for pn junctions.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Our objective is to demonstrate that this circuit can operate as an ampliﬁer.e. Vout is an ampliﬁed replica of Vin .1(b). producing Vout . Since V1 = Vin and Vout = . where I1 is proportional to V1 : I1 = KV1 . Figure 4 illustrates the sequence of concepts introduced in this chapter.1 . AV .1 .2) (4. The ampliﬁcation factor or “voltage gain” of the circuit. 2006] June 30. the bipolar transistor can be viewed as a voltage-dependent current source.1(a).KRL. i. then the circuit ampliﬁes the input. For example. Voltage−Controlled Device as Amplifying Element Structure of Bipolar Transistor Operation of Bipolar Transistor Large−Signal Model Small−Signal Model 4. The negative sign indicates that the output is an “inverted” replica of the input circuit [Fig.3) .cls v. Note that K has a dimension of resistance. we have Vout = . is deﬁned as AV = Vout Vin = . In this chapter. subsequently replacing vacuum tubes in electronic systems and paving the way for integrated circuits.1 General Considerations In its simplest form. an input voltage of 1 V yields an output current of 1 mA. if KRL 1.RL I1 . 4.1(b)]. We ﬁrst show how such a current source can form an ampliﬁer and hence why bipolar devices are useful and interesting. 4. derive equations that represent its I/V characteristics. 124 (4. Brattain.KRLVin : (4. Let us now construct the circuit shown in Fig.

Note that K signiﬁes how strongly V1 controls I1 . on the other hand.cls v. bipolar transistors make the analysis of circuits more difﬁcult. the voltage gain remains unchanged.4 that under certain conditions. we are accustomed to a oneto-one correspondence between the current through and the voltage across each device. Solution Exercise Repeat the above example if rin = 1.4. As three-terminal devices.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Having dealt with two-terminal components such as resistors. With three-terminal elements.1 (a) Voltage-dependent current source.2 Voltage-dependent current source with an internal resistance rin . 4. Example 4. 2007 at 13:42 125 (1) Sec. Bipolar transistors are an example of such current sources and can ideally be modeled as shown in Fig. V in r in V1 I1 KV1 RL Vout Figure 4. inductors. and depends on both the characteristics of the controlled current source and the load resistor. and diodes in elementary circuit analysis and the previous chapters of this book. Since V1 is equal to Vin regardless of the value of rin .1 General Considerations V in Vp t 125 V1 I1 KV1 V in V1 I1 KV1 R L Vout V out K R L Vp t (a) (b) Figure 4. The foregoing study reveals that a voltage-controlled current source can indeed provide signal ampliﬁcation. Determine the voltage gain of the circuit. Note that the device contains three terminals and its output current is an exponential function of V1 . thus obtaining a relatively simple model. one may consider the current and voltage between every two terminals. 4. 4. Fortunately. we discard some of these current and voltage combinations as irrelevant.3. This point proves useful in our analyses later.2. thus directly affecting the gain. arriving at a complex set of equations. 4. as we develop our understanding of the transistor’s operation. (b) simple ampliﬁer. . this model can be approximated by that in Fig. where the voltage-controlled current source exhibits an “internal” resistance of rin . We will see in Section 4.1(a). capacitors. 2006] June 30.1 Consider the circuit shown in Fig.

2 Structure of Bipolar Transistor The bipolar transistor consists of three doped regions forming a sandwich. about 100 A in modern integrated bipolar transistors. in reality.” As explained later.” the “emitter.5(a) and recall from Chapter 2 that the depletion region sustains a strong electric ﬁeld. 4 Physics of Bipolar Transistors 1 3 V1 I S exp V1 VT 2 Figure 4.. if the base is more positive than the emitter. Before continuing with the bipolar transistor. Shown in Fig. The circuit symbol for the npn transistor is shown in Fig.4 (a) Structure and (b) circuit symbol of bipolar transistor. What happens to this electron? Serving as a minority carrier on the p side. VCB . and VCE can assume positive or negative values. 4. 4. Now suppose an electron is somehow “injected” from outside into the right side of the depletion region. VB .4(a). and VC . VBE 0. E and C cannot be interchanged.g.cls v. and VCE . it is instructive to study an interesting effect in pn junctions.3 Exponential voltage-dependent current source. leading to 23 possibilities for the terminal voltages of the transistor. only one of these eight combinations ﬁnds practical value and comes into our focus here. then this junction is forward-biased.4(a) is an example comprising of a p layer sandwiched between two n regions and called an “npn” transistor. and the voltage differences by VBE . We will also see that proper operation requires a thin base region. the emitter “emits” charge carriers and the collector “collects” them while the base controls the number of carriers that make this journey. VBC . As mentioned in the previous section. 2007 at 13:42 126 (1) 126 Chap. 2006] June 30. 4. For the device in Fig. The transistor is labeled Q1 here. 4. Fortunately. the possible combinations of voltages and currents for a three-terminal device can prove overwhelming. In other words. We denote the terminal voltages by VE . VBE . For example.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the dimensions and doping levels of these two regions are quite different. the electron experiences the electric ﬁeld and is rapidly . Consider the reverse-biased junction depicted in Fig.” and the “collector. While this simple diagram may suggest that the device is symmetric with respect to the emitter and the collector. e. Collector Collector (C) n Base VCB Base (B) p n Q 1 VCE VBE Emitter (E) (b) Emitter (a) Figure 4. 4.4(b). 4.4(a) that the device contains two pn junction diodes: one between the base and the emitter and another between the base and the collector. The three terminals are called the “base. We readily note from Fig.

4. we say the device is biased in the “forward active region” or simply in the “active mode. we intend to show that (a) the current ﬂow from the emitter to the collector can be viewed as a current source tied between these two terminals.. under certain conditions. aiming to prove that.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. with the emitter connected to ground. This view implies that D1 carries a current and D2 does not. it appears that the bipolar transistor simply consists of two diodes sharing their anodes at the base terminal. bearing in mind that the base region is very .” For example. I2 V CE = +1 V V BE = +0.8 V and the collector voltage to a higher value. We begin our study with the assumption that the base-emitter junction is forward-biased (VBE 0) and the base-collector junction is reverse-biased (VBC 0). The base-collector junction therefore experiences a reverse bias of 0. The ability of a reverse-biased pn junction to efﬁciently “collect” externally-injected electrons proves essential to the operation of the bipolar transistor. To understand why the transistor cannot be modeled as merely two back-to-back diodes. 1 V [Fig.6(b). we should anticipate current ﬂow from the base to the emitter but no current through the collector terminal. we must examine the ﬂow of charge inside the device. VBE .5 Injection of electrons into depletion region.g.e. 4.3 Operation of Bipolar Transistor in Active Mode 127 swept away into the n side.2 V.6(a)].6 (a) Bipolar transistor with base and collector bias voltages. Electron injected e n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + + + + + E VR Figure 4. it indeed acts as a voltage-controlled current source. e.8 V (a) D2 V CE = +1 V I1 (b) D1 Figure 4. Were this true.6(a) to the equivalent circuit shown in Fig. More speciﬁcally. and (b) this current is controlled by the voltage difference between the base and the emitter. (b) simplistic view of bipolar transistor. 2007 at 13:42 127 (1) Sec. After all. 2006] June 30.3 Operation of Bipolar Transistor in Active Mode In this section. 4. 4.cls v. We may be tempted to simplify the example of Fig. 4. Let us now consider the operation of the transistor in the active mode.8 V V BE = +0. the transistor would not operate as a voltage-controlled current source and would prove of little value. we analyze the operation of the transistor. Under these conditions. the base voltage is set to about 0.. i.

For proper transistor operation.” We therefore observe that the reverse-biased collectorbase junction carries a current because minority carriers are “injected” into its depletion region. i. (c) electrons passing through collector junction. how does the resulting current depend on the terminal voltages? Third. through the base. how large is the base current? Operating as a moderate conductor.cls v. most of the electrons reach the edge of the collector-base depletion region. how do electrons travel through the base: by drift or diffusion? Second.8 V (a) (b) Depletion Region n − e p + h + V CE = +1 V V BE = +0. 4.7(a) summarizes our observations thus far. We must now answer several questions. as illustrated in Fig. it allows most of the ﬁeld to drop across the base-emitter depletion layer. n V CE = +1 V p V BE = +0. (2) 1 This assumption simpliﬁes the analysis here but may not hold in the general case.5) and absorbed by the positive battery terminal. Thus. to the collector while drawing a small current of holes through the base terminal. we recognize that the density of electrons at x = x1 is very high. . Thus. electrons ﬂow from the emitter to the base and holes from the base to the emitter. the drift current in the base is negligible.7 (a) Flow of electrons and holes through base-emitter junction.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) electrons approaching collector junction. 2007 at 13:42 128 (1) 128 Chap. In fact.7(b) and (c) illustrate this effect in “slow motion.8 V n (c) Figure 4. 2. 2006] June 30. beginning to experience the built-in electric ﬁeld. Figure 4. Let us summarize our thoughts.29 for the emitterbase junction [Fig. Since the base-emitter junction is forward-biased.5.8 V + h − e n + Depletion Region n V CE = +1 V p + h − e n + V BE = +0. What happens to electrons as they enter the base? Since the base region is thin. where the superscript emphasizes the high doping level. we denote the emitter region with n+ .1 leaving diffusion as the principal mechanism for the ﬂow of electrons injected by the emitter. an npn bipolar transistor carries a large number of electrons from the emitter. as explained for pn junctions in Chapter 2. Consequently.e. Figures 4. two observations directly lead to the necessity of diffusion: (1) redrawing the diagram of Fig. 4. 4 Physics of Bipolar Transistors thin. indicating that the emitter injects a large number of electrons into the base while receiving a small number of holes from it. 4.. the base region sustains but a small electric ﬁeld. In the active mode. the former current component must be much greater than the latter. the electrons are swept into the collector region (as in Fig. requiring that the emitter doping level be much greater than that of the base (Chapter 2). First.8(a)].

1 Collector Current We now address the second question raised above and compute the current ﬂowing from the collector to the emitter. the density of electrons falls to zero at this point. the electron density in the base assumes the proﬁle depicted in Fig. As a result. 2006] June 30. 4.8(c). (b) zero electron density near collector. (c) electron proﬁle in base.2 As a forward-biased diode. 2007 at 13:42 129 (1) Sec.8 (a) Hole and electron proﬁles at base-emitter junction. 1 : n2 T i . (2. 1 V0 T exp V BE = NB exp VV . 4.3 Operation of Bipolar Transistor in Active Mode 129 since any electron arriving at x = x2 in Fig.3.8(c) given by Eq.cls v. 4. the base-emitter junction exhibits a high concentration of electrons at x = x1 in Fig. 4. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8(b) is swept away. n x V CE Reverse Biased n p x x2 V CE e V BE p x1 e V BE n + h Forward Biased (a) n + (b) n x x2 x1 V CE e V BE p + n Electron Density (c) Figure 4. providing a gradient for the diffusion of electrons.96): BE nx1 = NE exp VV .

(4.4) .

Wnx1 . Thus. we determine the ﬂow of electrons into the collector as Jn = qDn dn dx (4. In this chapter. (2. NE and NB denote the doping levels in the emitter and the base. we assume VT = 26 mV.42)]. and we have utilized the relationship expV0 =VT = NE NB =n2 .7) 2 In an npn transistor. respectively. B (4. electrons go from the emitter to the collector. i Applying the law of diffusion [Eq.5) Here.T (4. . the conventional direction of the current is from the collector to the emitter.6) = qDn 0 .

2006] June 30.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. AE . Multipling this quantity by the emitter cross section area. and changing the sign to obtain the conventional current. substituting for nx1 from (4.5). 4 Physics of Bipolar Transistors where WB is the width of the base region. 2007 at 13:42 130 (1) 130 Chap. we obtain 2 E BE IC = ANqDn ni exp VV . 1 : B WB T In analogy with the diode current equation and assuming expVBE =VT .

VC . (b) equivalence to a single transistor . 4.” Determine the current IX in Fig.9(a) if Q1 and Q2 are identical and operate in the active mode and V1 = V2 . proving a good candidate for ampliﬁcation. We may alternatively say the transistor performs “voltage-to-current conversion.9 (a) Two identical transistors drawing current from having twice the area. we write (4.9) implies that the bipolar transistor indeed operates as a voltage-controlled current source.2 I C2 Q2 V3 IX I C1 Q1 V1 C IX I C2 Q2 V3 V1 Q eq C 2A E V3 B B 2A E E AE E AE (b) Figure 4.8) 1.10) Equation (4.9) BE IC = IS exp VV . T where E IS = ANqDn ni : W B B 2 (4. IX I C1 Q1 V1 V2 (a) Example 4. (4.

14) (4.e.3 Operation of Bipolar Transistor in Active Mode 131 Since IX Solution = IC 1 + IC 2 . Determine V1 .9(a).cls v. we have V1 IC 1 = IS exp VT .9(b) and noting that Q1 and Q2 experience identical voltages at their respective terminals. In fact. 4. Q1 and Q2 are identical and operate in the active mode.9). We therefore consider the baseemitter voltage of the transistor relatively constant and approximately equal to 0.3 Solution From Eq. exp V1 V V2 = 10: T That is.11) This result can also be viewed as the collector current of a single transistor having an emitter area of 2AE . 2007 at 13:42 131 (1) Sec.12) . Exercise Repeat the above example if Q1 and Q2 have different emitter areas. V2 such that IC 1 = 10IC 2. AE 1 = nAE2 .15) 60 mV at T = 300 K: Identical to Eq. Q1 has an emitter area of AE and Q2 an emitter area of In the circuit of Fig. V2 = VT ln 10 (4. (4..BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (2. 2006] June 30. Example 4. (4. we say the two transistors are “in parallel. of course. expected because the exponential dependence of IC upon VBE indicates a behavior similar to that of diodes.8 V for typical collector current levels. this result is. Exercise Repeat the above example if 8AE . 4.109). i.” operating as a single transistor with twice the emitter area of each. 4.13) V1 . IC 2 IS exp V2 V T and hence (4. . we have 2 V E IX 2 ANqDn ni exp V 1 : WB B T (4. redrawing the circuit as shown in Fig.

10 if IS RL IC 750 mV Example 4. This current ﬂows through RL .g. however. VBEdis = VT ln AE2 : E1 For this example. 2006] June 30. determine the difference between the base-emitter voltage of two such transistors for equal collector currents. Exercise Repeat the above comparison for a very small integrated device with an emitter area of 0:15 m 0:15 Since many applications deal with voltage quantities. generating a voltage . The key point here is that VBE = 800 mV is a reasonable approximation for integrated transistors and should be lowered to about 700 mV for discrete devices.5 = 5 10. VBEint .18) In practice..10 Simple stage with biasing. we write IC Solution = 1:69 mA. 500 m 500 m. we have VBE Example 4. e. Determine the output voltage in Fig. 1 kΩ 3V Q1 Vout Figure 4. Since IS AE . respectively.9). Using Eq. Assuming other device parameters are identical. From Eq. (4. 4. S2 (4. VBEdis falls in the range of 100 to 150 mV because of differences in the base width and other parameters. A VBEint . VBEdis = 383 mV: (4.16) where VBEint = VT lnIC 2 =IS 2 and VBEdis = VT lnIC 1 =IS 1 denote the base-emitter voltages of the integrated and discrete devices. (4. whereas modern integrated devices may have an area as small as 0:5 m 0:2 m.17) = 2:5 106.16 A.4 Solution = VT lnIC =IS and hence I VBEint .cls v. 4 Physics of Bipolar Transistors Typical discrete bipolar transistors have a large area. AE 2 =AE 1 (4. VBEdis = VT ln IS1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the collector current generated by a bipolar transistor typically ﬂows through a resistor to produce a voltage.9). 2007 at 13:42 132 (1) 132 Chap. yielding VBEint .

out of every 200 electrons injected by the emitter. As an example. the base current must supply holes for both reverse injection into the emitter and recombination with the electrons traveling toward the collector. calculation of the base current readily yields the emitter current as well.11(b) is the current as a function of the collector-emitter voltage. As the electrons injected by the emitter travel through the base. (2. IC RL. acting as a current source [Fig.11 (a) Bipolar transistor as a current source. Equation (4.12(b)]. the base current. one hole must be supplied by the base. we obtain Vout = 1:31 V: (4. results from the ﬂow of holes.12(a).3.3 Operation of Bipolar Transistor in Active Mode 133 drop of 1 k 1:69 mA = 1:69 V. Since VCE = 3V . Plotted in Fig. on the average. the device draws a constant current. In Section 4. some electrons and holes are “wasted” as a result of recombination. Thus. IC Q1 V1 I S exp V1 VT V1 (a) (b) Forward Active Region V CE Figure 4.99) that the hole and electron currents in a forward-biased pn junction bear a constant ratio given by the doping levels and other parameters. Recall from Eq.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the base current contains an additional component of holes. 4. 4.2 Base and Emitter Currents Having determined the collector current. 2006] June 30. 4. one recombines with a hole. 4. 4. IB .5. in essence. Since the bipolar transistor must satisfy Kirchoff’s current law.19) Exercise What happens if the load resistor is halved. for every 200 electrons injected by the emitter. Thus. We can therefore view IB as a 3 Recall that VCE V1 is necessary to ensure the collector-base junction remains reverse biased. for a ﬁxed base-emitter voltage. In practice.11(a)]. 4.cls v. we now turn our attention to the base and emitter currents and their dependence on the terminal voltages.9) reveals an interesting property of the bipolar transistor: the collector current does not depend on the collector voltage (so long as the device remains in the active mode). In summary. 2007 at 13:42 133 (1) Sec.3 Constant current sources ﬁnd application in many electronic circuits and we will see numerous examples of their usage in this book. For example. exhibiting a constant value for VCE V1 . the number of holes entering from the base to the emitter is a constant fraction of the number of electrons traveling from the emitter to the base. some may “recombine” with the holes [Fig. In the npn transistor of Fig. . we study the behavior of the transistor for VCE VBE . (b) I/V characteristic.

(4. constant fraction of IE or a constant fraction of IC .12 Base current resulting from holes (a) crossing to emitter and (b) recombining with electrons. In order to determine the emitter current. 2006] June 30. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 134 (1) 134 IC n IB V BE + h − e p + Chap. It is common to write IC = IB .cls v. the of npn transistors typically ranges from 50 to 200.20) where is called the “current gain” of the transistor because it shows how much the base current is “ampliﬁed. 4 Physics of Bipolar Transistors n V CE V BE + h − e p − e n + V CE n IE (a) (b) Figure 4. we apply the KCL to the transistor with the current directions depicted in Fig.” Depending on the device structure.12(a): IE = IC + IB = IC 1 + We can summarize our ﬁndings as follows: .

In this book.25) It is sometimes useful to write IC = = + 1 IE and denote = + 1 by .23) (4. the collector current remains independent of : Example 4.24) (4.16 A is biased in the forward active region with VBE = 750 mV.21) : (4. = 0:99. For = 100.22) BE IC = IS exp VV T 1 I exp VBE IB = S VT + 1 I exp VBE : IE = S V T (4. 1 (4. calculate the minimum and maximum terminal currents of the device.6 Solution BE IC = IS exp VV T (4. A bipolar transistor having IS = 5 10. suggesting that 1 and IC IE are reasonable approximations. we assume that the collector and emitter currents are approximately equal. If the current gain varies from 50 to 200 due to manufacturing variations. For a given VBE .26) .

which requires a proportional base current. 4.27) 8:43 A IB 33:7 A: (4. we add a voltage-controlled current source between the collector and the emitter.14(a). 4. the emitter current experiences only a small variation because near unity for large : + 1= is 1:005IC IE 1:693 mA IE Exercise 1:02IC 1:719 mA: (4.e. But how do we ensure that the current ﬂowing through the diode is equal to 1= times the collector current? Equation (4. the base-emitter voltage generates a collector current. the base-emitter junction is modeled by a diode whose cross section area is 1= times that of the actual emitter area. 4.28) On the other hand. Since the base-emitter junction is forward-biased in the active mode. and the sum of the two ﬂows through the emitter.7 = 5 10. B C VBE IS I S exp V BE VT β exp V BE VT E Figure 4. Moreover.4 Bipolar Transistor Models and Characteristics 4.cls v.4. We view the chain of dependencies as VBE ! IC ! IB ! IE . (4.11. 4. 2006] June 30.29) (4. arriving at the model shown in Fig. we can place a diode between the base and emitter terminals. this current remains independent of the collector-emitter voltage. Consider the circuit shown in Fig.23)-(4. the reader may wonder about the cause and effect relationships.17 A and VBE = 800 mV. As illustrated in Fig.13 Large-signal model of bipolar transistor in active region. 4. we can now construct a model that proves useful in the analysis and design of circuits—in a manner similar to the developments in Chapter 2 for the pn junction. ..13.1 Large-Signal Model With our understanding of the transistor operation in the forward active region and the derivation of Eqs.24) suggests that the base current is equal to that of a diode having a reverse saturation current of IS = . where IS. With the interdependencies of currents and voltages in a bipolar transistor.30) Repeat the above example if the area of the transistor is doubled. i.4 Bipolar Transistor Models and Characteristics 135 = 1:685 mA: The base current varies from IC =200 to IC =50: (4. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 135 (1) Sec.25). since the current drawn from the collector and ﬂowing into the emitter depends on only the base-emitter voltage.Q1 Example 4.

(b) Determine the maximum value of RC that permits operation in the active mode.0 X Q1 VCC 2V 1.36) = +800 mV. We must now calculate the collector voltage. respectively. the voltage at node X drops. The device approaches the “edge” of the forward active region if the base-collector voltage falls to zero.35) Since the collector voltage is more positive than the base voltage. 4 Physics of Bipolar Transistors VX (V) RC IC V BE 500 Ω 2. (b) variation of collector voltage as a function of collector resistance.34) yields: RC = VCCI. increases while VCC is constant. for VX (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.31) (4.34) VX = 1:424 V: (4. i. reduces to RC = 1041 : Figure 4. (4. as VX ! +800 mV. C which. Solution (a) Using Eq. this junction is reverse-biased and the transistor operates in the active mode. VX . 2006] June 30.424 0. (4.. RC IC .e.23)-(4. VX . Rewriting Eq.14 (a) Simple stage with biasing.25). we obtain VCC = RC IC + VX : That is. (4. (b)What happens to the circuit as RC increases? Since the voltage drop across the resistor. we have IC = 1:153 mA IB = 11:53 A IE = 1:165 mA: (4. Writing a KVL from the 2-V power supply and across RC and Q1 .33) The base and emitter voltages are equal to +800 mV and zero.37) .cls v.32) (4. Assume = 100. 2007 at 13:42 136 (1) 136 Chap.14(b) plots VX as a function of RC . (a) Determine the transistor terminal currents and voltages and verify that the device indeed operates in the active mode.800 500 1041 R C (Ω ) (a) (b) Figure 4. (4.

However. we may envision plotting different currents as a function of the potential difference between every two terminals—an elaborate task. the characteristic moves up or down. thus. as explained below.13 is called the “large-signal model.11. As shown in Fig. and hence the collector current by many orders of magnitude.15(b). 4 A 500-mV change in VBE leads to 500 mV=60 mV = 8:3 decades of change in IC . if the base-emitter voltage varies from 800 mV to 300 mV. different values of VCE do not alter the characteristic. 2006] June 30.4. IC Q1 V BE V CE V BE IC Q1 V CE IC I S exp I S exp V BE (a) IC V BE2 VT V BE1 VT V BE = V B2 V BE = V B1 V CE (b) Figure 4. 4. This example implies that there exists a maximum allowable value of the collector resistance.4. 2007 at 13:42 137 (1) Sec. the above example apparently contains no signals! This terminology emphasizes that the model can be used for arbitrarily large voltage and current changes in the transistor (so long as the device operates in the active mode). 4. the characteristic is a horizontal line because IC is constant if the device remains in the active mode (VCE VBE ). Figure 4. this limits the voltage gain that the circuit can provide.4.2 I/V Characteristics The large-signal model naturally leads to the I/V characteristics of the transistor.4 Bipolar Transistor Models and Characteristics 137 RC . Exercise In the above example. IC is independent of VCE .15 Collector current as a function of (a) base-emitter voltage and (b) collector-emitter voltage. what is the minimum allowable value of VCC for transistor operation in the active mode? Assume RC = 500 . in the circuit of Fig.14(a). the exponential relationship inherent in the device. we examine IC for a given VBE but with VCE varying. The reader may wonder why the equivalent circuit of Fig. 4. For example.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Illustrated in Fig. The ﬁrst characteristic to study is. 4. 4. if different values are chosen for VBE . studied in Section 4. of course. On the other hand. This is in contrast to the small-signal model. With three terminal currents and voltages. Next.4 the model still applies. only a few of such characteristics prove useful. 4. As we will see in Chapter 5.cls v.15(a) plots IC versus VBE with the assumption that the collector voltage is constant and no lower than the base voltage.” After all. .

4. we simply divide the IC values by 100 [Figs.4.3..169 µ A 0. (c) Using the values obtained above.g.g.5 µ A 0. 169 A if its base-emitter voltage is held at 750 mV.153 mA 169 µ A 24. 4 Physics of Bipolar Transistors The two plots of Fig.025 µ A V BE = 800 mV V BE = 750 mV V BE = 700 mV V CE (d) V BE (mV) (c) Figure 4. For a bipolar transistor. IC jumps by increasingly greater steps: 24. . 2007 at 13:42 138 (1) 138 Chap.cls v. for equal increments in VBE . 4.40) IC 1.8 = 100. (b) collector current as a function of base current as a function of BE . We determine a few points along the IC -VBE characteristics. For IB characteristics. e. Equations (4.5 µ A 0.17 A and IB -VBE .24) and (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.16 (a) Collector current as a function of BE .16(c) and (d)].15 constitute the principal characteristics of interest in most analysis and design tasks. 4.16(a). 2006] June 30.6 µ A V BE = 800 mV V BE = 750 mV V BE = 700 mV V CE (b) V BE (mV) (a) IB 11. (b) base current as a function of CE .025 µ A 700 750 800 IB 11. 4. We return to this property in Section 4.. Example 4. V V V VCE . and IB -VCE characteristics. e. concluding that the transistor operates as a constant current source of.25) suggest that the base and emitter currents follow the same behavior.6 A to 169 A to 1.6 µ A 700 750 800 (4. We also remark that. Solution VBE1 = 700 mV IC 1 = 24:6 A VBE2 = 750 mV IC 2 = 169 A VBE3 = 800 mV IC 3 = 1:153 mA: The characteristic is depicted in Fig.16(b).38) (4.153 mA.153 mA 169 µ A 24. we can also plot the IC -VCE characteristic as shown in Fig.39) (4. IC 1. IC -VCE . Construct the IC -VBE .169 µ A 0. IS = 5 10.

(4. another type of transistor described in Chapter 6). 2006] June 30. 4.1 mA in one transistor and 0. we recognize that the “strength” of the device can be represented by IC =VBE . we can view the latter as a better voltage-dependent current source or “voltage-to-current converter.5 mA in another. compared to Eqs. (4.4 Bipolar Transistor Models and Characteristics 139 Exercise What change in VBE doubles the base current? The reader may wonder what exactly we learn from the I/V characteristics. what is the measure of the “goodness” of a voltage-dependent current source? The example depicted in Fig. if a signal changes the base-emitter voltage of a transistor by a small amount (Fig.4.17).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g. We must therefore concentrate on the voltage-to-current conversion property of the transistor. For a bipolar transistor. The ratio IC =VBE approaches dIC =dVBE for very small changes and. 4. how much change is produced in the collector current? Denoting the change in IC by IC .25). More speciﬁcally. we ask. the visualization of equations by means of such plots greatly enhances our understanding of the devices and the circuits employing them. However.1 suggests that the device becomes “stronger” as K increases because a given input voltage yields a larger output current. particularly as it relates to ampliﬁcation of signals. if a base-emitter voltage change of 1 mV results in a IC of 0. For example. 2007 at 13:42 139 (1) Sec.41) BE Note that this deﬁnition applies to any device that approximates a voltage-dependent current source (e.9) gives gm = dVd .17 Test circuit for measurement of Q1 V CE gm . is called the “transconductance.cls v. 4. the plots impart no additional information.. An important question that arises here is. as we will see throughout this book.” gm : dI gm = dV C : (4. 4. Eq. how is the performance of such a device quantiﬁed? In other words.23)-(4.” IC ∆V BE Figure 4. in the limit. After all.3 Concept of Transconductance Our study thus far shows that the bipolar transistor acts as a voltage-dependent current source (when operating in the forward active region).

58)] is no coincidence and will become clearer in the next chapter.44) I = VC : T The close resemblance between this result and the small-signal resistance of diodes [Eq. BE = V1 IS exp VV T T BE BE IS exp VV T (4. (3.42) (4.43) (4. .

we have gm = 0:0385 . 4.g. and the corresponding base-emitter voltage. Consider the circuit shown in Fig. VBE 0 .45) (4. we use the term “bias current” to refer to the collector bias current. 2006] June 30. IC 0 .1 or “siemens.19(a). where gm = IC 0 =VT . The transconductance may be expressed in .cls v. . for IC = 1 mA. as we will see throughout this book. ultimately. then the collector current displays a change of gm V around IC 0 .. the required gain. it is often helpful to view gm as the inverse of a resistance. 2007 at 13:42 140 (1) 140 Chap.48) The concept of transconductance can be visualized with the aid of the transistor I/V characteristics. 4 Physics of Bipolar Transistors Equation (4.9 I C0 V CE V BE0 I C0 I C0 V CE n transistors providing transconductance. (b) 5 Unless otherwise stated. the transistor becomes a better amplifying device by producing larger collector current excursions in response to a given signal level applied between the base and the emitter. In other words.46) (4.19 (a) One transistor and (b) Example 4.18. meaning the device carries a bias (or “quiescent”) current of IC 0 in the absence of signals. Thus.5 IC I C0 V BE0 V BE g m ∆V ∆V Figure 4. if IC = 1 mA.44) reveals that.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As shown in Fig. we may write gm = 261 : (4.18 Illustration of transconductance. e. as IC increases. if VBE experiences a small perturbation V around VBE 0 . For example.47) However. the value of IC 0 must be chosen according to the required gm and. We say the transistor is “biased” at a collector current of IC 0 . 4.1 = 0:0385 S = 38:5 mS: (4. gm = dIC =dVBE simply represents the slope of IC -VBE characteristic at a given collector current. then with VT = 26 mV. What happens to the transconductance of Q1 if the area of the device is increased by a factor of n? n I C0 I C0 Q1 V BE0 (a) Figure 4.” S.

the current produced by the transistor may ﬂow through a resistor to generate a proportional voltage. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Figure 4. For this reason.42)-(4. Thus. e.10. 4.20 for two different bias currents IC 1 and IC 2 . determine the changes in the currents ﬂowing through all terminals.20 Transconductance for different collector bias currents. Recall from Chapter 3 that diodes can be reduced to linear devices through the use of the small-signal model. and represent the results by proper circuit elements such as controlled current sources or resistors. We perturb the voltage difference between every two terminals (while the third terminal remains at a constant potential). The derivation of the small-signal model from the large-signal counterpart is relatively straightforward. and IE are examined. IB . may incorporate a large number of transistors. 2007 at 13:42 141 (1) Sec. then the composite device exhibits a transconductance equal to n times that of each. IS is multiplied by the same factor. (4. On the other hand. if IC remains constant but varies. then so does the transconductance. ampliﬁers. 4. As shown in Fig. Solution Exercise Repeat the above example if VBE 0 is reduced by VT ln n. As a result.19(b)]. IC = IS expVBE =VT also rises by a factor of n because VBE is constant. The derivation of gm in Eqs. the plots reveal that a change of V in VBE results in a greater change in IC for operation around IC 2 than around IC 1 because gm2 gm1 . with the base current viewed as secondary. [Fig.g. 2006] June 30. Illustrated in Fig.4 Small-Signal Model Electronic circuits. the collector bias current plays a central role in the analysis and design. if the total collector current remains unchanged.44) suggests that the transconductance is fundamentally a function of the collector current rather than the base current. . 4. often undesirable effect. if n identical transistors. IC g m2 ∆V V BE = V B2 + ∆V V BE = V B2 V BE = V B1 + ∆V V BE = V B1 I C2 I C1 g m1 ∆V V CE Figure 4. From another perspective.4 Bipolar Transistor Models and Characteristics 141 Since IS AE .21 depicts two conceptual examples where VBE or VCE is changed by V and the changes in IC . A similar beneﬁt accrues if a smallsignal model can be developed for transistors. For example. then gm does not change but IB does. the transconductance increases by a factor of n. thus posing great difﬁculties in the analysis and design.4. We exploit this concept in Chapter 5 to design ampliﬁers. It is also possible to study the transconductance in the context of the IC -VCE characteristics of the transistor with VBE as a parameter. each carrying a collector current of IC 0 are placed in parallel..cls v. 4.

by a resistor placed between the base and emitter having a value: r = VIBE B (4.51) = gm VBE : That is. IC = gm VBE . We know from the deﬁnition of transconductance that ∆ I C = g m ∆V BE ∆V BE Q1 V CE ∆I B VBE I S exp ∆I C V BE + ∆V BE VT V CE ∆V BE ∆I E B C B vπ g vπ m C B rπ vπ g vπ m C ∆V BE g ∆V BE m E E E Figure 4. Let us begin with a change in VBE while the collector voltage is constant (Fig..49) concluding that a voltage-controlled current source must be connected between the collector and the emitter with a value equal to gm V .50) (4.22 Development of small-signal model.cls v. 2007 at 13:42 142 (1) 142 Chap. i. if the base-emitter voltage changes by VBE . 4. Since the voltage and current correspond to the same two terminals. the current ﬂowing between these two terminals changes by gm = VBE . 2006] June 30. The change in VBE creates another change as well: IB = IC (4. For simplicity. they can be related by Ohm’s Law.52) .21 Excitation of bipolar transistor with small changes in (a) base-emitter and (b) collectoremitter voltage. (4.e.22). we denote VBE by v and the change in the collector current by gm v .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4 Physics of Bipolar Transistors ∆I C ∆I B ∆V ∆I B V BE (b) ∆I C ∆V Q1 Q1 V CE ∆I E (a) ∆I E Figure 4.

We should remark that both parameters of the model.92 mA for VBE = I gm = VC T (4. The simple small-signal model developed in Fig.22 serves as a powerful. 4. 2007 at 13:42 143 (1) Sec.24 (a) Transistor with bias and small-signal excitation.23). We now turn our attention to the collector and apply a voltage change with respect to the emitter (Fig. and Q1 operates in the active mode. how much change is observed in the collector and base currents? (a) Writing IC 800 mV. the model developed in Fig. versatile tool in the analysis and design of bipolar circuits. (3. (b) If the microphone generates a 1-mV signal. This result is expected because the diode carries a bias current equal to IC = and. for a constant VBE . Studied in Chapter 5. 4. As illustrated in Fig. IS = 3 10. Thus.8 V v1 rπ vπ iC g vπ m (a) (b) Figure 4. Since VCE leads to no change in any of the terminal currents.11. determine the small-signal parameters of Q1 .cls v.53) Thus.24(a). With a high collector bias current. IC Q1 v1 800 mV Example 4. 4.4 Bipolar Transistor Models and Characteristics 143 =g : m (4. exhibits a small-signal resistance of VT =IC = = VT =IC = =gm . (a) If v1 = 0. = 100. such a change also results in a zero change in the terminal currents. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. gm and r . How about a change in the collector-base voltage? As studied in Problem 18.54) . where v1 represents the signal generated by a microphone. we obtain a collector bias current of 6. the collector voltage has no effect on IC or IB because IC = IS expVBE =VT and IB = IC = .58). from Eq. (b) small-signal equivalent circuit. Solution = IS expVBE =VT . ∆I C ∆V CE Q1 V BE V BE VBE I S exp V BE VT ∆V CE Figure 4. depend on the bias current of the device. 4. Consider the circuit shown in Fig. this trade-off proves undesirable in some cases. the forward-biased diode between the base and the emitter is modeled by a small-signal resistance equal to =gm . a greater gm is obtained. 4. but the impedance between the base and emitter falls to lower values.23 Response of bipolar transistor to small change in VCE .10 iB V CC = 1.16 A.22 need not be altered.

The collector voltage. the circuit generates no output.8-V battery. a useful output is provided.65) Since the collector voltage (with respect to ground) is more positive than the base voltage.11 Solution Vout = VCC . and (4. (4. 2007 at 13:42 144 (1) 144 Chap. 4 Physics of Bipolar Transistors 1 = 3:75 . RC IC = 1:108 V: (4. which is equal to Vout .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The microphone signal produces a change in IC .24(a) is modiﬁed as shown in Fig. (a) The collector bias current of 6. In other words.61) (4. the device operates in the active mode. The circuit of Fig.63) which is. The above example is not a useful circuit. (b) Determine the output signal level if the microphone produces a 1-mV signal. 4. 2006] June 30.55) r = g = 375 : m (4.60) v IB = r 1 1 mV = 375 = 2:67 A.56) (4. Exercise Repeat the above example if IS is halved.58) (4. but the result ﬂows through the 1. . 4. if the collector current ﬂows through a resistor. On the other hand.cls v. is thus given by: Example 4. (a) Verify that the transistor operates in the active mode. equal to IC = .59) (4. 4.57) (b) Drawing the small-signal equivalent of the circuit as shown in Fig. of course.92 mA ﬂows through RC .25.62) (4. where resistor RC converts the collector current to a voltage. we obtain the change in the collector current as: IC = gm v1 1 mV = 3:75 = 0:267 mA: The equivalent circuit also predicts the change in the base current as (4. leading to a potential drop of IC RC = 692 mV.24(b) and recognizing that v = v1 .64) (4.

we must determine how the supply voltage. Similarly. a 1-mV microphone signal leads to a 0. other components in the circuit must also be represented by a small-signal model.11. we simply “ground” the supply voltage in small-signal analysis. Small-Signal Model of Supply Voltage We have seen that the use of the small-signal model of diodes and transistors can simplify the analysis considerably. Upon ﬂowing through RC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.25 Simple stage with bias and small-signal excitation.5 Early Effect Our treatment of the bipolar transistor has thus far concentrated on the fundamental principles. 1:384 V = 2:216 V and guaranteeing operation in the active mode. suppose we raise RC to 200 and VCC to 3. behaves with respect to small changes in the currents and voltages of the circuit. We will study and quantify the behavior of this and other ampliﬁer topologies in the next chapter. VCC .12 Solution .4. Note that Example 4. leading to a collector voltage of 3:6 V . To emphasize that such grounding holds for only signals. 2007 at 13:42 145 (1) Sec. we observe that VCC must be replaced with a zero voltage to signify the zero change. The key principle here is that the supply voltage (ideally) remains constant even though various voltages and currents within the circuit may change with time.6 V. 4.7. Exercise What value of RC places results in a zero collector-base voltage? The foregoing example demonstrates the ampliﬁcation capability of the transistor. ignoring second-order effects in the device and their representation in the large-signal and smallsignal models. In particular. In such an analysis. The voltage drop across RC now increases to 6:92 mA 200 = 1:384 V. Considering the circuit of Example 4.267-mA change in IC . (b) As seen in the previous example. we sometimes say a node is an “ac ground. 2006] June 30. some circuits require attention to such effects if meaningful results are to be obtained. any other constant voltage in the circuit is replaced with a ground connection.8 V Q 1 Vout v1 800 mV Figure 4.4 Bipolar Transistor Models and Characteristics 145 RC 100 Ω V CC = 1. The following example illustrates this point. Thus. Since the supply does not change and since the small-signal model of the circuit entails only changes in the quantities. this change yields a change of 0:267 mA 100 = 26:7 mV in Vout .” 4. Verify that the device operates in the active mode and compute the voltage gain. However.cls v. The circuit therefore ampliﬁes the input by a factor of 26.

Exercise What happens if RC = 250 ? This example points to an important trend: if RC increases. WB . How is the Early effect represented in the transistor model? We must ﬁrst modify Eq. Illustrated in Fig.25. the slope of the proﬁle increases. in Eq. 4.26.cls v. 2 the effective base width. Equivalently.gm v1 RC and hence vout =v1 = .gm v RC = . we have vout =v1 = . where the collector voltage is somewhat higher than the base voltage and the reverse bias across the junction creates a certain depletion region width.27(a). Discovered by Early. thereby increasing the collector current. 1 1 + VV . 4. if RC ! 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.26 Small-signal equivalent circuit of the stage shown in Fig. 4. E WB T A . limit the maximum gain that can be achieved? Indeed. Does this mean that. With gm = 3:75 . Since RC is doubled. 200 Ω RC rπ vπ v1 g vπ m v out Figure 4. This result is also obtained with the aid of the small-signal model. Since the base charge proﬁle must still fall to zero at the edge of depletion region. 1:384 V = 0:416 V and the transistor is not in the forward active region. (4. then Vout = 1:8 V .11 that “the collector current does not depend on the collector voltage. (4. 4.53:4. the voltage gain must also double. we return to the internal operation of the transistor and reexamine the claim shown in Fig. this phenomenon poses interesting problems in ampliﬁer design (Chapter 5).1 and RC = 200 . 4. It can be proved that the rise in the collector current with VCE can be approximately expressed by a multiplicative factor: 2 E BE CE IC = ANqDn ni exp VV .27(b)]. 2007 at 13:42 146 (1) 146 Chap. reaching a value of 53. then the gain also grows indeﬁnitely? Does another mechanism in the circuit. the “Early effect” translates to a nonideality in the device that can limit the gain of ampliﬁers. To understand this effect. thus increasing the reverse bias and widening the depletion region in the collector and base areas.9) to include this effect.” Consider the device shown in Fig.4. 2006] June 30. Now suppose VCE is raised to VCE 2 [Fig.8) decreases. perhaps in the transistor. the equivalent circuit yields vout = . 4 Physics of Bipolar Transistors if VCC is not doubled. x0 . so does the voltage gain of the circuit. Recall from part (b) of the above example that the change in the output voltage is equal to the change in the collector current multiplied by RC .gm RC .

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V BE CE IS exp VV 1+ V : T A .

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66) (4.” . (4. models the Early effect.67) where WB is assumed constant and the second factor. 1+ VCE =VA . The quantity VA is called the “Early voltage.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. On the other hand. 4. IC With Early Effect IC VBE 1 (4. 2006] June 30.69) A VA and hence IC IS expVBE =VT . In fact. 2007 at 13:42 147 (1) Sec. 4. the dependence of IC upon VBE remains exponential but with a somewhat greater slope [Fig.4 Bipolar Transistor Models and Characteristics V CE1 n x x2 x1 n + 147 V CE2 n x ’ x2 e V BE p e V BE n p + x1 (a) (b) Figure 4.68) VCE = IS exp VT VA I VC . It is instructive to examine the I/V characteristics of Fig.cls v. for a constant VBE .27 (a) Bipolar device with base and collector bias voltages. (b) effect of higher collector voltage. 4. differentiation of (4.15 in the presence of Early effect.67) with respect to VCE yields where it is assumed VCE imation in most cases. the IC .28(b)]. (4. For a constant VCE .28(a)]. This is a reasonable approxIC V BE1 VT Without Early Effect With Early Effect .VCE characteristic displays a nonzero slope [Fig. 4.

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(4. A bipolar transistor carries a collector current of 1 mA with VCE = 2 V. 4.28 Collector current as a function of (a) VBE and (b) VCE with and without Early effect. 4. 4.67) VBE = VT ln IC I S (4.70) . With VA Example 4.28(b) reveals that the transistor in fact does not operate as an ideal current source. The variation of IC with VCE in Fig. Without Early Effect I S exp V BE (a) (b) V CE Figure 4. requiring modiﬁcation of the perspective shown in Fig. The transistor can still be viewed as a two-terminal device but with a current that varies to some extent with VCE (Fig.29).11(a). Determine the required base-emitter voltage if VA = 1 or VA = 20 V.13 Solution = 1. we have from Eq. Assume IS = 2 10.16 A.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.67) as 0 B VBE = VT ln B IC @ 1 1 C C IS 1 + VCE A VA (4. VA . we rewrite Eq. = 760:3 mV If VA (4. 2007 at 13:42 148 (1) 148 X Chap. (4. we have 1 + VCE =VA .71) = 20 V. 4 X Physics of Bipolar Transistors Q1 V1 ( I S exp V1 VT ) ( 1+ VX VA ) Figure 4. VCE =VA . 2006] June 30.1 1 .29 Realistic model of bipolar transistor as a current source. for VCE (4.72) = 757:8 mV: In fact.cls v.73) where it is assumed ln1 .

30. 4. VCE VBE VT ln I T VA S CE VT ln IC .75) 1.4.74) (4. Exercise Repeat the above example if two such transistors are placed in parallel.1 and 4. where BE CE IC = IS exp VV 1 + VV T . The large-signal model of Fig. for (4.13 must now be modiﬁed to that in Fig. IC + V ln 1 . 4. Large-Signal and Small-Signal Models The presence of Early effect alters the transistor models developed in Sections 4.4.4. IS A . VT VV .

A BE IB = 1 IS exp VV T IE = IC + IB : .

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78) Note that IB is independent of VCE and still given by the base-emitter voltage. For the small-signal model.79) .77) (4.76) (4. we note that the controlled current source remains unchanged and gm is expressed as dI gm = dV C BE (4. (4.

4 Bipolar Transistor Models and Characteristics 149 B IB VBE IE E IC ( I S exp C V1 VT ) ( 1+ V CE VA ) Figure 4. BE = V1 IS exp VV T T . 4.30 Large-signal model of bipolar transistor including Early effect. 2006] June 30.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 149 (1) Sec.

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83) Considering that the collector current does vary with VCE . 4.82) (4.80) (4.81) r = g = VT : I C m (4. I = VC : T Similarly.31(a)]: BE IC + IC = IS exp VV T It follows that . let us now apply a voltage change at the collector and measure the resulting current change [Fig. CE 1 + VV A (4.

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IC = IS exp VV VA T . 1 + VCE + VCE : V A (4.84) BE VCE .

” rO plays a critical role in high-gain ampliﬁers (Chapter 5).87) (4.88) Example 4. Called the “output resistance.85) which is consistent with Eq. rO .14 A transistor is biased at a collector current of 1 mA. (4.86) (4. IC . = 100 . rO = VICE C VA = BE IS exp VV T VA : I C (4. they satisfy Ohm’s Law. Note that both r and rO are inversely proportionally to the bias current. 4.69). (4. Since the voltage and current change correspond to the same two terminals. the small-signal model contains only one extra element. yielding an equivalent resistor: Depicted in Fig.31(b). Determine the small-signal model if and VA = 15 V. to represent the Early effect.

Finally. An important notion that has emerged from our study of the transistor is the concept of biasing. 2007 at 13:42 150 (1) 150 Chap. 4. we return to Example 4. r = g Also. We must create proper dc voltages and currents at the device terminals to accomplish two goals: (1) guarantee operation in the active mode (VBE 0. These properties are studied in Chapter 11. Figure 4.91) (4. we should remark that the small-signal model of Fig.. (2) establish a collector current that yields the required values for the small-signal parameters gm .93) (4.32 summarizes the concepts studied in this section. VCE 0). . We will conclude that the gain is eventually limited by the transistor output resistance.89) (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.92) rO = VA I C (4.31(b) does not reﬂect the highfrequency limitations of the transistor. e. 4 Physics of Bipolar Transistors C ∆I C Q1 V BE ∆V B rπ vπ g vπ m rO E (a) (b) Figure 4. rO .7). rO . and r .12 and determine the gain of the ampliﬁer in the presence of the Early effect.g.31 (a) Small change in VCE and (b) small-signal model including Early effect. Solution We have I gm = VC T and (4.90) 1 = 26 . = 2600 : m (4. The analysis of ampliﬁers in the next chapter exercises these ideas extensively.94) = 15 k : Exercise What early voltage is required if the output resistance must reach 25 k ? In the next chapter. 2006] June 30.cls v. For example. the load resistance tied to the collector faces an upper limit for a given supply voltage (Example 4. the base-emitter and base-collector junctions exhibit a depletion-region capacitance that impacts the speed.

Let us set VBE to a typical value.5 Operation of Bipolar Transistor in Saturation Mode As mentioned in the previous section. VBC 0 and the B-C junction is forward biased? We say the transistor enters the “saturation region. the junction sustains a zero voltage difference. the base-collector junction experiences less reverse bias. i. and we say the device is in “soft saturation. 2006] June 30. .” Suppose VCE = 550 mV and hence VBC = +200 mV.6 Thus.cls v. 750 mV.e. For VCE = VBE .5 Operation of Bipolar Transistor in Saturation Mode V BE VT n V CE e 151 Operation in Active Mode I C = I S exp n − e p V BE + h + V CE V BE n n p + Large−Signal Model B C I/V Characteristrics IC B Small−Signal Model C VBE IS I S exp V BE VT I S exp IC V BE1 VT V CE V BE rπ vπ g vπ m β exp V BE VT E Early Effect E n V CE B Modified Small−Signal Model C rπ vπ g vπ m rO p V BE n + E Figure 4.. 4. 2007 at 13:42 151 (1) Sec. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g. 200 mV=60 mV=dec 9:2. 4. it is desirable to operate bipolar devices in the forward active region. we study the behavior of the device outside this region and the resulting difﬁculties. e.” If the collector voltage drops further. even in this case the transistor continues to operate as in the active mode. where they act as voltage-controlled current sources. and VBC goes from a negative value toward zero. In this section. car6 About nine orders of magnitude less than one sustaining 750 mV: 750 mV .33(a)]. But what happens if VCE VBE .32 Summary of concepts studied thus far. As VCE approaches VBE . We know from Chapter 2 that a typical diode sustaining 200 mV of forward bias carries an extremely small current. and vary the collector voltage from a high level to a low level [Fig. but its depletion region still absorbs most of the electrons injected by the emitter into the base.. the B-C junction experiences greater forward bias.

where IC begins to fall for VCE less than V1 . 4 Physics of Bipolar Transistors ∆I C V CE Q1 V BE V BE + h n − e p + V CE n (a) (b) Figure 4. 2006] June 30. as illustrated in Fig. The above observations lead to the IC -VCE characteristics depicted in Fig. VT ln IC =1000 IS IS = VT ln 1000 180 mV: That is. if the collector is left open. We therefore ask. IB . VBC (4. Since IB = IC =100. Exercise Repeat the above example if VBE It is instructive to study the transistor large-signal model and I-V characteristics in the saturation region. We construct the model as shown in Fig. In fact. 4. heavy saturation leads to a sharp rise in the base current and hence a rapid fall in . assume base-collector and base-emitter junctions have identical structures and doping levels. 2007 at 13:42 152 (1) 152 Chap. we have VBE .35. rying a signiﬁcant current [Fig. then DBC is forward-biased so much that its current becomes equal to the controlled current.96) (4.33(b)]. Consequently.95) (4. about a few hundred millivolts.33 (a) Bipolar transistor with forward-biased base-collector junction. VBC = VT ln IC . How much B-C forward bias can the device tolerate if must not degrade by more than 10? For simplicity.97) = 570 mV: = 800 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34(b). 4. The term “saturation” is . (b) ﬂow of holes to collector.cls v. Note that the net collector current decreases as the device enters saturation because part of the controlled current IS 1 expVBE =VT is provided by the B-C diode and need not ﬂow from the collector terminal.34(a). A bipolar transistor is biased with VBE = 750 mV and has a nominal of 100. 4. Example 4. the B-C junction must carry no more than IC =1000. then the degrades by 10.15 Solution If the base-collector junction is forward-biased so much that it carries a current equal to onetenth of the nominal base current. what B-C voltage results in a current of IC =1000 if VBE = 750 mV gives a collector current of IC ? Assuming identical B-E and B-C junctions. a large number of holes must be supplied to the base terminal—as if is reduced. including the base-collector diode. In other words. 4.

Example 4.g. It is important to recognize that the transistor simply draws a current from any component tied to its collector.35 Transistor I/V characteristics in different regions of operation. 2007 at 13:42 153 (1) Sec. Thus.34 (a) Model of bipolar transistor including saturation effects. Saturation Forward Active Region IC V1 V CE Figure 4.. electronic circuits rarely allow operation of bipolar devices in this mode. e. RC and VCC that guarantees In soft saturation. it is the external component that deﬁnes the collector voltage and hence the region of operation. 400 mV.36. The collector voltage must not fall below the base voltage by more than 400 mV: Solution VCC . RC IC VBE . we permit soft saturation with VBC 400 mV because the current in the B-C junction is negligible. Thus. (b) case of open collector terminal. provided that various tolerances in the component values do not drive the device into deep saturation. used because increasing the base current in this region of operation leads to little change in the collector current. a resistor.5 Operation of Bipolar Transistor in Saturation Mode I S2 exp D BC B C 153 V BE VT D BC I S1 exp V BE VT V BE VBE D BE I S1 exp V BE VT VBE D BE E (a) (b) Figure 4. the collector current is still equal to IS expVBE =VT . 2006] June 30. 4.98) VCC IC RC + VBE .99) .16 For the circuit of Fig. 400 mV: (4. (4. In addition to a drop in . Thus. 4. determine the relationship between operation in soft saturation or active region. As a rule of thumb. the speed of bipolar transistors also degrades in saturation (Chapter 11).cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

2007 at 13:42 154 (1) 154 Chap. 4. Under this condition. IC RC still maintains a Exercise Determine the maximum tolerable value of RC . majority carriers in the emitter (holes) are injected into the base and swept away into the collector. A small number of base majority carriers (electrons) are injected into the emitter or recombined with the holes in the base region. We may naturally wonder if the dopant polarities can be inverted in the three regions.1 Structure and Operation Figure 4. Thus. . thus creating the base current. 4 Physics of Bipolar Transistors Acceptable Region RC IC Q1 V BE (a) V CC V CC V BE − 400 mV RC (b) Figure 4. emphasizing that the emitter is heavily doped. Also. More importantly. 4. VBE 0 and VBC 0. a linear proﬁle of holes is formed in the base region to allow diffusion. we may wonder why such a device would be useful.36 (a) Simple stage.38(b) illustrates the ﬂow of the carriers.38(a) shows the structure of a pnp transistor..) B 800 mV 200 mV C VCE.6 The PNP Transistor We have thus far studied the structure and properties of the npn transistor. the collector-emitter voltage approaches a constant value called E Figure 4. 2006] June 30. VCC must be sufﬁciently large so that VCC reasonable collector voltage. (The battery tied between C and E indicates that VCE is relatively constant in deep saturation.e.sat (about 200 mV). As with the npn counterpart. Under this condition. For a given value of RC .6.37 Transistor model in deep saturation. Figure 4. current source and can be modeled as shown in Fig. 4. with the emitter and collector made of n-type materials and the base made of a p-type material. . All of the operation principles and equations described for npn transistors apply to pnp devices as well.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. operation in the active region requires forward-biasing the base-emitter junction and reverse-biasing the collector junction. forming a “pnp” device. i. the transistor bears no resemblance to a controlled In the deep saturation region. (b) acceptable range of VCC and RC .37.

23)-(4. Figure 4. Since the base current must be included in the emitter current. 2006] June 30. 4. (2) The distinction between active and saturation regions is based on the B-C junction bias. bottom of the page). Following our convention of placing more positive nodes on the top of the page. 4. top of the page) toward a lower potential (i. (b) current ﬂow in pnp transistor..38(c) depicts the symbol of the pnp transistor along with constant voltage sources that bias the device in the active region. (1) The (conventional) current always ﬂows from a positive supply (i.cls v. (d) more intuitive view of (c).39(a) shows two branches employing npn and pnp transistors.38(d) to emphasize VEB 0 and VBC 0 and to illustrate the actual direction of current ﬂow into each terminal. here the base and collector voltages are lower than the emitter voltage. 2007 at 13:42 155 (1) Sec. we redraw the circuit as in Fig. 4.2 Large-Signal Model The current and voltage polarities in npn and pnp transistors can be confusing. on the other hand. Figure 4.6 The PNP Transistor 155 p x x2 x1 V CE V BE − e p − e n + h p + V CE h V BE n + p Hole Density (a) (b) V BE Q1 V BE (c) IE IB Q1 IC (d) V CE V CE Figure 4. the collector must not be higher than the base. For the pnp device. T (4.100) (4. 4.39(b).101) (4. In contrast to the biasing of the npn transistor in Fig. we note that IB1 and IC 1 add up to IE1 whereas IE2 “loses” IB2 before emerging as IC 2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We address this issue by making the following observations. The different cases are summarized in Fig. illustrating that the (conventional) current ﬂows from collector to emitter in npn devices and from emitter to collector in pnp counterparts.6. (3) The npn current equations (4.25) must be modiﬁed as follows for the pnp device EB IC = IS exp VV T IS exp VEB IB = VT EB IE = + 1 IS exp VV .102) . 4.38 (a) Structure of pnp transistor.e..6. where the relative position of the base and collector nodes signiﬁes their potential difference.e. (c) proper biasing. We note that an npn transistor is in the active mode if the collector (voltage) is not lower than the base (voltage).

4 Active Mode Physics of Bipolar Transistors Edge of Saturation 0 Saturation Mode I E2 I C1 I B1 Q1 I E1 0 (a) (b) Figure 4.39 (a) Voltage and current polarities in npn and pnp transistors. I B2 Q2 I C2 V CC Active Mode Edge of Saturation Saturation Mode where the current directions are deﬁned in Fig. Also.40. 2006] June 30.cls v. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The only difference between the npn and pnp equations relates to the base-emitter voltage that appears in the exponent. (b) illustration of active and saturation regions. the Early effect can be included as EB IC = IS exp VV T E . 2007 at 13:42 156 (1) 156 Chap. an expected result because VBE 0 for pnp devices and must be changed to VEB to create a large exponential term.

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but VA = 1. .16 A and = 50.41.17 Q1 1.40 Large-signal model of pnp transistor.103) IS β exp V EB VT VEB IE I S exp IC V EB VT C B IB Figure 4.41 Simple stage using a pnp transistor. In the circuit shown in Fig. 4. Example 4. Assume IS = 2 10. EC 1 + VV : A (4.2 V X RC V CC 2V 200 Ω Figure 4. determine the terminal currents of Q1 and verify operation in the forward active region.

7 V Example 4. In the circuit of Fig. 4. Invoking the illustration in Fig. thus requiring that the right-hand side of Eqs.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.101) be multiplied by a negative sign.100)-(4. VEB = +800 mV and we have EB IC jVin =0 = IS exp VV T (4.108) (4.100) and (4. 4.110) .42.42 PNP stage with bias and small-signal voltages.6 The PNP Transistor 157 We have VEB Solution = 2 V .104) (4. Exercise What is the maximum value of RC is the transistor must remain in soft saturation? (4. (4.18 IC RC 300 Ω Vout V CC 2. Vin represents a signal generated by a microphone.106) (4. we conclude that We should mention that some books assume all of the transistor terminal currents ﬂow into the device. Determine Vout for Vin = 0 and Vin = +5 mV if IS = 1:5 10.105) It follows that IB = 92:2 A IE = 4:70 mA: RC carries IC . (4.39(b). Since VX = RC IC = 0:922 V. 1:2 V = 0:8 V and hence EB IC = IS exp VV T = 4:61 mA: (4. 2006] June 30. Q1 operates in the active mode and the use of equations (4. We nonetheless continue with our notation as it reﬂects the actual direction of currents and proves more efﬁcient in the analysis of circuits containing many npn and pnp transistors. 2007 at 13:42 157 (1) Sec.16 A. 4. Q1 V in 1.107) We must now compute the collector voltage and hence the bias across the B-C junction. For Vin Solution = 0.102) is justiﬁed.cls v.109) which is lower than the base voltage.5 V Figure 4.

we expect npn and pnp transistors to have similar models. In analogy with npn transistors. and hence (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We caution the reader about this confusion.111) Vout = 1:038 V: If Vin increases to +5 mV. This is not an inconsistency and is studied in Problem 49. the collector voltage falls.43(b).6. .cls v.43 (a) Small-signal model of pnp transistor. 4.5 mV. 4. Following the convention in Fig. 4. we sometimes draw the model as shown in Fig.43(b) is not identical to that in Fig. Exercise Determine Vout is Vin = .4. 2006] June 30. E B ib rπ vπ ie E (a) ic g vπ m rO C ie rπ B vπ g vπ m rO C ib (b) ic Figure 4. one may automatically assume that the “top” terminal is the collector and hence the model in Fig. 4. the voltage gain is equal to 36.43(b). 4. A few examples prove helpful here. 4. yielding (4.114) Note that as the base voltage rises. 4.113) Vout = 0:856 V: (4. Since a 5-mV change in V1 gives a 182-mV change in Vout .43(a). VBE 1 (4. Depicted in Fig. especially if drawn as in Fig. (b) more intuitive view of (a). The small-signal model of pnp transistors may cause confusion. These results are more readily obtained through the use of the small-signal model. the small-signal model of the pnp transistor is indeed identical to that of the npn device.112) = +795 mV and IC jVin =+5 mV = 2:85 mA.31(b). a behavior similar to that of the npn counterparts in Figs.40.38(d).25. The reader may notice that the terminal currents in the small-signal model bear an opposite direction with respect to those in the large-signal model of Fig. 4. 2007 at 13:42 158 (1) 158 Chap. 4 Physics of Bipolar Transistors = 3:46 mA. 4.3 Small-Signal Model Since the small-signal model represents changes in the voltages and currents.

cls v.117) (4. .19 If the collector and base of a bipolar transistor are tied together. 4. Exercise What is the impedance of a diode-connected device operating at a current of 1 mA? Example 4. 4. Solution As illustrated in Figs.44(a).44(b)]. 4. 4. It is seen that all three topologies reduce to the same equivalent circuit because VCC is grounded in the small-signal representation. 4. we replace each transistor with its small-signal model and ground the supply voltage.118) g1 m VT : =I C Interestingly. Determine the small-signal impedance of the devices shown in Fig. Assume VA = 1.44(a). 2007 at 13:42 159 (1) Sec.116) (4.20 Draw the small-signal equivalent circuits for the topologies shown in Figs. we have vX = 1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.45(d)-f. with a bias current of IC .44 We replace the bipolar transistor Q1 with its small-signal model and apply a small-signal voltage across the device [Fig.” The same results apply to the pnp conﬁguration in Fig. 4. a two-terminal device results. we write a KCL at the input node: Solution vX + g v = i : r m X Since gm r (4. iX gm + r 1 (4.6 The PNP Transistor 159 Example 4. We call this structure a “diode-connected transistor.45(a)-(c) and compare the results.115) = 1. the device exhibits an impedance similar to that of a diode carrying the same bias current. Noting that rpi carries a current equal to vX =r . 2006] June 30. iX Q2 Q1 vX rπ vπ g vπ m (a) (b) Figure 4.

46(a). (c) another pnp stage. Example 4. 4 VCC Q1 Physics of Bipolar Transistors VCC v in Q1 v out RC v out (a) (b) (c) RC rπ vπ g vπ m rπ vπ g vπ m v in rO v out v in r O RC v out (d) rπ v in vπ g vπ m rO RC v out v in rπ vπ g vπ m r O RC v out (e) v in rπ vπ g vπ m rO RC v out v in rπ vπ g vπ m r O RC v out (f) Figure 4. . (e) small-signal equivalent of (b). 4. (d) small-signal equivalent of (a). 2006] June 30. (f) small-signal equivalent of (f).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 160 (1) 160 VCC RC v in Q 1 v out v in RC Chap.21 Draw the small-signal equivalent circuit for the ampliﬁer shown in Fig.45 (a) Simple stage using an npn transistor.cls v. Exercise Repeat the above example if a resistor is placed between the collector and base of each transistor. (b) simple stage using a pnp transistor.

2006] June 30. Solution RC 1 . and collector. 4. 2007 at 13:42 161 (1) Sec. Carriers injected by the emitter into the base approach the edge of collector depletion region and ae swept away by the high electric ﬁeld.46(b) depicts the equivalent circuit. . Bipolar transistors are electronic devices that can operate as voltage-dependent current sources. Exercise Show that the circuit depicted in Fig. Such observations simplify the analysis (Chapter 5). the base-emitter junction is forward-biased and the base-collector junction reverse-biased (forward active region).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.47 Stage using two npn devices. 4. 4.46 (a) Stage using npn and pnp devices. VCC RD R C1 Q2 v out Q1 v in Figure 4. For proper operation. Note that rO1 . and r2 appear in parallel. Figure 4. emitter. (b) small-signal equivalent of (a). The carriers ﬂow from the emitter to the collector and are controlled by the base.7 Chapter Summary A voltage-dependent current source can form an ampliﬁer along with a load resistor.47 has the same small-signal model as the above ampliﬁer. The bipolar transistor consists of two pn junctions and three terminals: base.7 Chapter Summary 161 VCC R C1 RC Q1 v in R C2 v out Q2 v in rπ1 vπ 1 g m1 rπ2 vπ 1 r O1 vπ 2 g m2 v π2 r O2 v out R C2 (a) (b) Figure 4.cls v.

6. The small-signal model of bipolar transistors consists of a linear voltage-dependent current source. The ratio of collector current and the base current is denoted by . 4.50.48. the bipolar transistor enters saturation and its performance degrades.16 A.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Suppose the voltage-dependent current source of Fig. The transconductance of a bipolar transistor is given by gm = IC =VT and remains independent of the device dimensions. 4. Determine the ratio of transistor cross section areas if the other device parameters are identical. some of which go to the emitter and some others recombine in the base region.48 if VBE 1 . What value of load resistance in Fig. 3. 1.cls v. and an output resistance. 4. a resistance tied between the base and emitter. In the forward active region. Plot the voltage gain as a function of x. choose IS 3 such that IY = 2:5 mA. 4. it is observed that the collector currents of Q1 and Q2 are equal I C1 Q1 V BE1 V BE2 I C2 Q2 Figure 4. Problems In the following problems. assume the bipolar transistors operate in the active mode. If the base-collector junction is forward-biased. (a) If IS 1 = 2IS 2 = 5 10.1(b) is necessary to achieve a voltage gain of 15? 2. 4. Repeat Problem 2 but assuming that rin and K are related: rin = a=x and K = bx. 4. VBE 2 = 20 mV. The small-signal models of npn and pnp transistors are identical. A resistance of RS is placed in series with the input voltage source in Fig. the bipolar transistor exhibits an exponential relationship between its collector current and base-emitter voltage. Determine Vout =Vin . and a diode (accounting for the base current) tied between the base and emitter. 4 Physics of Bipolar Transistors The base terminal must provide a small ﬂow of carriers. IS 1 = IS 2 = 3 10. In the circuit of Fig. unless otherwise stated. (a) Calculate VB such that IX = 1 mA. 2006] June 30. 7. Due to a manufacturing error. a bipolar transistor behaves as constant current source. How does the collector current change? 5. determine VB such that IX = 1:2 mA. 2007 at 13:42 162 (1) 162 Chap. In the circuit of Fig. 4. The large-signal model of the bipolar transistor consists of an exponential voltage-dependent current source tied between the collector and emitter. (b) With the value of VB found in (a).16 A. the base width of a bipolar transistor has increased by a factor of two. In the forward active region.2.1(a) is constructed with K = 20 mA/V.49. Consider the circuit shown in Fig. .

16 A. In the circuit of Fig.5 V. Assume IS = 5 10. Calculate VX in Fig. Calculate the value of VB that places Q1 at the edge RC 500 Ω V CC = 2 V Q1 VB Figure 4. determine the maximum value of VCC that places Q1 at the edge of saturation. 4. Assume IS = 3 10. is available (Fig.52 11.53 if IS = 6 10. and only a single voltage source.49 RC IX Q1 VB Q2 V CC = 2.16 A. 9. construct . Repeat Problem 7 if VCC is lowered to 1.16 A.52. 2006] June 30. 4.5 V Figure 4.7 Chapter Summary 163 IX Q1 VB Q2 Q3 IY Figure 4.50 (b) What value of RC places the transistors at the edge of the active mode? 8. 10. 4. Consider the circuit shown in Fig.16 A can be placed in parallel. 2007 at 13:42 163 (1) Sec. An integrated circuit requires two current sources: I1 = 1 mA and I2 = 1:5 mA.51.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.54).51 of the active region. 4. RC R1 10 k Ω 1 kΩ V CC = 2 V Q1 Figure 4. 4. Assuming that only integer multiples of a unit bipolar transistor having IS = 3 10.cls v. 12. VB .

IS 1 = 3 10. = 4 10. Calculate IX and IY . If the device operates in the forward active R1 = 5 k .16 A. and I3 = 0:45 mA. 4.16 A. 14.56.56. Calculate the collector current. Repeat Problem 12 for three current sources I1 = 0:2 mA. 4 Physics of Bipolar Transistors Q1 1. IS 1 = 2IS 2 IX R1 = 10 k .16 A. IS 2 = 5 10. Consider the circuit shown in Fig.cls v. 1 = 2 = 100.56 . If 1 = 2 = 100 and IY Q1 Q2 VB Figure 4. 2006] June 30. 4.5 V X 1 kΩ V CC = 2 V Figure 4. and VB = 800 mV. The base-emitter junction of a transistor is driven by a constant voltage. assuming = 100 and IS = 7 10. determine VB such that IC = 1 mA. If R1 = 10 k .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.16 A. 18. IC R1 Q1 VB Figure 4. Suppose a voltage source is applied between the base and collector. In the circuit of Fig. R1 = 5 k . 2007 at 13:42 164 (1) 164 Chap.55 15.54 the required circuit with minimum number of unit transistors.53 I1 I2 VB Unit Transistor Figure 4. VB = 800 mV and RB 16. compute VB such that IX = 1 mA.55. 4. In the circuit depicted in Fig. I2 = 0:3 mA. 13. 17.55. 4. In the circuit of Fig.

4.) 19. (Neglect the Early effect. e. what is the largest change in VBE that guarantees only 10 variation in gm ? 21. . Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig.5 V 10 µ A 1 kΩ RC V CC = 2. What base-emitter voltage is required? 20.16 A must provide a transconductance of 1=13 . and VA = 1. since the signal changes the collector current. = 100. Most applications require that the transconductance of a transistor remain relatively constant as the signal level varies.57. RC 50 Ω RC V CC = 2. 4.16 A. Assume IS = 8 10. Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig.57 22. prove that a change in base-collector voltage results in no change in the collector and base currents. gm = IC =VT does vary. Assume IS = 8 10. A ﬁctitious bipolar transistor exhibits an IC -VBE characteristic given by IC = IS exp VBE . = 100. Nonetheless. Of course.119) where n is a constant coefﬁcient.cls v.16 A. proper design ensures negligible variation.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10 µA Q1 1 kΩ (a) V CC = 2 V Q1 1 kΩ (b) V CC = 2 V V CC = 2 V Q1 1 mA 1 mA V CC = 2 V Q1 (d) (c) Figure 4.5 V 1 kΩ V CC = 2.5 V Q1 Q1 0. 10. If a bipolar device is biased at IC = 1 mA.58. A transistor with IS = 6 10. 2006] June 30.g. Construct the small-signal model of the device if IC is still equal to IB . 2007 at 13:42 165 (1) Sec.7 Chapter Summary 165 region.. nV T (4.8 V (a) Q1 (b) (c) Figure 4. 4. and VA = 1.58 23.

In the circuit of Fig. 29.61 (a) Assuming VA = 1. Consider the circuit shown in Fig. In Problem 27. 27. (b) If VA = 5 V. The collector voltage of a bipolar transistor varies from 1 V to 3 V while the base-emitter voltage remains constant.5 V Figure 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VCC changes from 2. In the circuit of Fig. (4.17 A. Determine VX for (a) VA = 1.61.5 V.59 VA = 5 V. VA = 5 V.59.60 28.5 to 3 V. 4. 2007 at 13:42 166 (1) 166 Chap.120) where a is a constant coefﬁcient. . 4. Construct the small-signal model of the device if IC is still equal to IS expVBE =VT . and (b) RC 1 kΩ X Q1 V B = 0. we wish to decrease VB to compensate for the change in IC . Determine the new value of VB . 25. where I1 is a 1-mA ideal current source and IS = 3 10.17 A. determine the change in the collector current of Q1 .cls v.8 V Figure 4. 4. determine VB such that IC = 1 mA. IS = 5 10. 2006] June 30. Assuming IS RC 2 kΩ = 1 10. I1 Q1 VB V CC = 2 V Figure 4.17 A and V CC Q1 0. 4 Physics of Bipolar Transistors 24. What Early voltage is necessary to ensure that the collector current changes by less than 5? 26.8 V V CC = 2. determine VB such that IC = 1 mA for a collector-emitter voltage of 1.60. A ﬁctitious bipolar transistor exhibits the following relationship between its base and collector currents: 2 IC = aIB .

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167

30. A bipolar current source is designed for an output current of 2 mA. What value of VA guarantees an output resistance of greater than 10 k . 31. In the circuit of Fig. 4.62, n identical transistors are placed in parallel. If IS = 5 10,16 A

V B = 0.8 V

Figure 4.62

and VA = 8 V for each device, construct the small-signal model of the equivalent transistor. 32. Consider the circuit shown in Fig. 4.63, where IS = 6 10,16 A and VA = 1.

2 kΩ

RC

V CC = 2.5 V Q1 VB

Figure 4.63

(a) Determine VB such that Q1 operates at the edge of the active region. (b) If we allow soft saturation, e.g., a collector-base forward bias of 200 mV, by how much can VB increase? 33. For the circuit depicted in Fig. 4.64, calculate the maximum value of VCC that produces a

RC

1 kΩ

V CC Q1

Figure 4.64

collector-base forward bias of 200 mV. Assume IS = 7 10,16 A and VA = 1. 34. Assume IS = 2 10,17 A, VA = 1, and = 100 in Fig. 4.65. What is the maximum value of RC if the collector-base must experience a forward bias of less than 200 mV?

100 k Ω

RB

RC V CC = 2.5 V Q1

Figure 4.65

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168

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35. Consider the circuit shown in Fig. 4.66, where IS = 5 10,16 A and VA = 1. If VB is chosen to forward-bias the base-collector junction by 200 mV, what is the collector current?

Q1 VB

1 kΩ

V CC = 2.5 V

Figure 4.66

36. In the circuit of Fig. 4.67, = 100 and VA = 1. Calculate the value of IS such that the base-collector junction is forward-biased by 200 mV.

RC Rp

9 kΩ

V CC = 2.5 V

1 kΩ

Q1

Figure 4.67

37. If IS 1

**= 3IS2 = 6 10,16 A, calculate IX in Fig. 4.68.
**

0.82 V

Q1

1.7 V

Q2 V CC IX

2V

Figure 4.68

**38. Determine the collector current of Q1 in Fig. 4.69 if IS
**

50 k Ω

= 2 10,17 A and = 100.

RB

1.7 V

Q1 V CC IC

2V

Figure 4.69

39. In the circuit of Fig. 4.70, it is observed that IC = 3 mA. If = 100, calculate IS . 40. Determine the value of IS in Fig. 4.71 such that Q1 operates at the edge of the active mode. 41. What is the value of that places Q1 at the edge of the active mode in Fig. 4.72? Assume IS = 8 10,16 A. 42. Calculate the collector current of Q1 in Fig. 4.73 if IS = 3 10,17 A.

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Chapter Summary

169

23 k Ω

RB

Q1 V CC IC

1.5 V

Figure 4.70

Q1 V B = 1.2 V RC

V CC

2V

2 kΩ

Figure 4.71

100 k Ω

RB

Q1 V CC

1 kΩ 1.5 V

Figure 4.72

1 kΩ

V CC Q1

2.5 V

1V

Figure 4.73

43. Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig. 4.74. Assume IS = 3 10,17 A, = 100, and VA = 1.

Q1

1.7 V

Q1 V CC

2.5 V 20

Q1 V CC

2.5 V

1 kΩ (a)

µA

V CC

2 kΩ (c)

2.5 V

500 (b)

Ω

Figure 4.74

44. Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig. 4.75. Assume IS = 3 10,17 A, = 100, and VA = 1. 45. In the circuit of Fig. 4.76, IS = 5 10,17 A. Calculate VX for (a) VA = 1, and (b) VA = 6 V.

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170

2 kΩ 5 kΩ

Chap. 4

Physics of Bipolar Transistors

V CC Q1

2.5 V

V CC Q1

2.5 V

0.5 mA

V CC Q1

2.5 V

2

µA

(a) (b)

(c)

Figure 4.75

Q1

1.7 V

X

V CC

500

2.5 V

Ω

Figure 4.76

46. A pnp current source must provide an output current of 2 mA with an output resistance of 60 k . What is the required Early voltage? 47. Repeat Problem 46 for a current of 1 mA and compare the results. 48. Suppose VA = 5 V in the circuit of Fig. 4.77.

Q1

1.7 V

X

V CC

3 kΩ

2.5 V

Figure 4.77

(a) What value of IS places Q1 at the edge of the active mode? (b) How does the result in (a) change if VA = 1? 49. The terminal currents in the small-signal model of Fig. 4.43 do not seem to agree with those in the large-signal model of Fig. 4.40. Explain why this is not an inconsistency. 50. Consider the circuit depicted in Fig. 4.78, where IS = 6 10,16 A, VA = 5 V, and I1 = 2 mA.

Q1 VB X I1 V CC

2.5 V

Figure 4.78

(a) What value of VB yields VX = 1 V? (b) If VB changes from the value found in (a) by 0.1 mV, what is the change in VX ? (c) Construct the small-signal model of the transistor. 51. In the circuit of Fig. 4.79, = 100 and VA = 1.

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Chapter Summary

360 k Ω

171

RB

Q1 V CC

4 kΩ 2.5 V

Figure 4.79

(a) Determine IS such that Q1 experiences a collector-base forward bias of 200 mV. (b) Calculate the transconductance of the transistor. 52. Determine the region of operation of Q1 in each of the circuits shown in Fig. 4.80. Assume IS = 5 10,16 A, = 100, VA = 1.

RE Q1 V CC RC

2.5 V

RB Q1

RE Q1 V CC RC

2.5 V 300 Ω

V CC

1 kΩ (c)

2.5 V

(a)

(b)

RE

0.5 mA

V CC Q1

500 Ω

2.5 V

Q1 V CC RC

2.5 V

(d)

(e)

Figure 4.80

53. Consider the circuit shown in Fig. 4.81, where, IS 1 2 = 50, VA = 1, and RC = 500 .

= 3IS2 = 5 10,16 A,

1

= 100,

Q1 V in Q2 Vout RC

V CC = 2.5 V

Figure 4.81

(a) We wish to forward-bias the collector-base junction of What is the maximum allowable value of Vin ?

Q2 by no more than 200 mV.

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Physics of Bipolar Transistors

(b) With the value found in (a), calculate the small-signal parameters of Q1 and Q2 and construct the equivalent circuit. 54. Repeat Problem 53 for the circuit depicted in Fig. 4.82 but for part (a), determine the minimum allowable value of Vin . Verify that Q1 operates in the active mode.

Q1 V in Q2 Vout RC

V CC = 2.5 V

Figure 4.82

55. Repeat Problem 53 for the circuit illustrated in Fig. 4.83.

RC Q1 V in Q2 Vout

V CC = 2.5 V

Figure 4.83

56. In the circuit of Fig. 4.84, IS 1

= 2IS2 = 6 10,17 A,

RC Q1 Vout Q2

1 = 80 and 2

= 100.

V CC = 2.5 V

V in

Figure 4.84

(a) What value of Vin yields a collector current of 2 mA for Q2 ? (b) With the value found in (a), calculate the small-signal parameters of Q1 and Q2 and construct the equivalent circuit. SPICE Problems In the following problems, assume IS;npn = 5 10,16 A, npn = 100, VA;npn = 5 V, IS;pnp = 8 10,16 A, pnp = 50, VA;pnp = 3:5 V. 57. Plot the input/output characteristic of the circuit shown in Fig. 4.85 for 0 Vin 2:5 V. What value of Vin places the transistor at the edge of saturation? 58. Repeat Problem 57 for the stage depicted in Fig. 4.86. At what value of Vin does Q1 carry a collector current of 1 mA? 59. Plot IC 1 and IC 2 as a function of Vin for the circuits shown in Fig. 4.87 for 0 Vin 1:8 V. Explain the dramatic difference between the two.

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Chapter Summary

173

RC

1 kΩ

Vout Q1 V B = 0.9 V V in

V CC = 2.5 V

Figure 4.85

V CC = 2.5 V V in

1 kΩ

Q1 Vout

Figure 4.86

I C2 I C1 V in Q1 Q3 V CC = 2.5 V V in Q2

V CC = 2.5 V

(a)

(b)

Figure 4.87

60. Plot the input/output characteristic of the circuit illustrated in Fig. 4.88 for 0 What value of Vin yields a transconductance of 50 ,1 for Q1 ?

RC

1 kΩ

Vin

2 V.

V CC = 2.5 V

Vout Q1 V in Q2

Figure 4.88

61. Plot the input/output characteristic of the stage shown in Fig. 4.89 for 0 Vin 2:5 V. At what value of Vin do Q1 and Q2 carry equal collector currents? Can you explain this result intuitively?

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Chap. 4

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1 kΩ

V CC = 2.5 V

V in

Q1 Q2

Vout

1.5 V 1 kΩ

Figure 4.89

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5

Bipolar Ampliﬁers

With the physics and operation of bipolar transistors described in Chapter 4, we now deal with ampliﬁer circuits employing such devices. While the ﬁeld of microelectronics involves much more than ampliﬁers, our study of cellphones and digital cameras in Chapter 1 indicates the extremely wide usage of ampliﬁcation, motivating us to master the analysis and design of such building blocks. This chapter proceeds as follows.

General Concepts Input and Output Impedances Biasing DC and Small−Signal Analysis

Operating Point Analysis Simple Biasing Emitter Degeneration Self−Biasing Biasing of PNP Devices

Amplifier Topologies Common−Emitter Stage Common−Base Stage Emtter Follower

Building the foundation for the remainder of this book, this chapter is quite long. Most of the concepts introduced here are invoked again in Chapter 7 (MOS ampliﬁers). The reader is therefore encouraged to take frequent breaks and absorb the material in small doses.

5.1 General Considerations

Recall from Chapter 4 that a voltage-controlled current source along with a load resistor can form an ampliﬁer. In general, an ampliﬁer produces an output (voltage or current) that is a magniﬁed version of the input (voltage or current). Since most electronic circuits both sense and produce voltage quantities,1 our discussion primarily centers around “voltage ampliﬁers” and the concept of “voltage gain,” vout =vin . What other aspects of an ampliﬁer’s performance are important? Three parameters that readily come to mind are (1) power dissipation (e.g., because it determines the battery lifetime in a cellphone or a digital camera); (2) speed (e.g., some ampliﬁers in a cellphone or analog-to-digital converters in a digital camera must operate at high frequencies); (3) noise (e.g., the front-end ampliﬁer in a cellphone or a digital camera processes small signals and must introduce negligible noise of its own).

1 Exceptions are described in Chapter 12.

175

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Chap. 5

Bipolar Ampliﬁers

5.1.1 Input and Output Impedances In addition to the above parameters, the input and output (I/O) impedances of an ampliﬁer play a critical role in its capability to interface with preceding and following stages. To understand this concept, let us ﬁrst determine the I/O impedances of an ideal voltage ampliﬁer. At the input, the circuit must operate as a voltmeter, i.e., sense a voltage without disturbing (loading) the preceding stage. The ideal input impedance is therefore inﬁnite. At the output, the circuit must behave as a voltage source, i.e., deliver a constant signal level to any load impedance. Thus, the ideal output impedance is equal to zero. In reality, the I/O impedances of a voltage ampliﬁer may considerably depart from the ideal values, requiring attention to the interface with other stages. The following example illustrates the issue.

Example 5.1

An ampliﬁer with a voltage gain of 10 senses a signal generated by a microphone and applies the ampliﬁed output to a speaker [Fig. 5.1(a)]. Assume the microphone can be modeled with a voltage source having a 10-mV peak-to-peak signal and a series resistance of 200 . Also assume the speaker can be represented by an 8- resistor.

Microphone Amplifier Speaker

A v = 10

200 Ω 10 mV

vm

Rm

8Ω

(a)

200 Ω

vm

Rm

R amp v1 R in v amp RL

8 Ω v out

(b)

(c)

Figure 5.1 (a) Simple audio system, (b) signal loss due to ampliﬁer input impedance, (c) signal loss due to ampliﬁer output impedance.

(a) Determine the signal level sensed by the ampliﬁer if the circuit has an input impedance of 2 k or 500 . (b) Determine the signal level delivered to the speaker if the circuit has an output impedance of 10 or 2 .

Solution

(a) Figure 5.1(b) shows the interface between the microphone and the ampliﬁer. The voltage

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General Considerations

177

sensed by the ampliﬁer is therefore given by

v1 = R RinR vm : in + m

For Rin

(5.1)

=2k

,

v1 = 0:91vm;

only 9 less than the microphone signal level. On the other hand, for Rin

(5.2)

= 500

, (5.3)

v1 = 0:71vm;

i.e., nearly 30 loss. It is therefore desirable to maximize the input impedance in this case. (b) Drawing the interface between the ampliﬁer and the speaker as in Fig. 5.1(c), we have

**R vout = R + L vamp : L Ramp
**

For Ramp

(5.4)

= 10

,

vout = 0:44vamp;

a substantial attenuation. For Ramp

(5.5)

=2

, (5.6)

vout = 0:8vamp :

Thus, the output impedance of the ampliﬁer must be minimized.

Exercise

If the signal delivered to the speaker is equal to 0:2vm , ﬁnd the ratio of Rm and RL .

The importance of I/O impedances encourages us to carefully prescribe the method of measuring them. As with the impedance of two-terminal devices such as resistors and capacitors, the input (output) impedance is measured between the input (output) nodes of the circuit while all independent sources in the circuit are set to zero.2 Illustrated in Fig. 5.2, the method involves applying a voltage source to the two nodes (also called “port”) of interest, measuring the resulting current, and deﬁning vX =iX as the impedance. Also shown are arrows to denote “looking into” the input or output port and the corresponding impedance. The reader may wonder why the output port in Fig. 5.2(a) is left open whereas the input port in Fig. 5.2(b) is shorted. Since a voltage ampliﬁer is driven by a voltage source during normal operation, and since all independent sources must be set to zero, the input port in Fig. 5.2(b) must be shorted to represent a zero voltage source. That is, the procedure for calculating the output impedance is identical to that used for obtaining the Thevenin impedance of a circuit (Chapter 1). In Fig. 5.2(a), on the other hand, the output remains open because it is not connected to any external sources.

2 Recall that a zero voltage source is replaced by a short and a zero current source by an open.

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Input Port

Chap. 5

Bipolar Ampliﬁers

Output Port iX

iX vx

Short

vX R out

R in

(a) (b)

Figure 5.2 Measurement of (a) input and (b) output impedances.

Determining the transfer of signals from one stage to the next, the I/O impedances are usually regarded as small-signal quantities—with the tacit assumption that the signal levels are indeed small. For example, the input impedance is obtained by applying a small change in the input voltage and measuring the resulting change in the input current. The small-signal models of semiconductor devices therefore prove crucial here.

Example 5.2

Assuming that the transistor operates in the forward active region, determine the input impedance of the circuit shown in Fig. 5.3(a).

VCC RC vX iX rπ vπ RC g vπ m

v in

Q1

rO

(a)

(b)

Figure 5.3 (a) Simple ampliﬁer stage, (b) small-signal model.

Solution

Constructing the small-signal equivalent circuit depicted in Fig. 5.3(b), we note that the input impedance is simply given by

vx = r : ix

Since r = impedance.

(5.7) or lower IC yield a higher input

=gm = VT =IC , we conclude that a higher

Exercise

What happens if RC is doubled?

To simplify the notations and diagrams, we often refer to the impedance seen at a node rather than between two nodes (i.e., at a port). As illustrated in Fig. 5.4, such a convention simply assumes that the other node is the ground, i.e., the test voltage source is applied between the node of interest and ground.

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179

Short

R in

R out

(a)

(b)

Figure 5.4 Concept of impedance seen at a node.

**Calculate the impedance seen looking into the collector of Q1 in Fig. 5.5(a).
**

rπ vπ g vπ m rO

Example 5.3

v in

Q 1 R out

R out

(a)

(b)

Figure 5.5 (a) Impedance seen at collector, (b) small-signal model.

Solution

Setting the input voltage to zero and using the small-signal model in Fig. 5.5(b), we note that v = 0, gm v = 0, and hence Rout = rO .

Exercise

What happens if a resistance of value R1 is placed in series with the base?

Example 5.4

Calculate the impedance seen at the emitter of simplicity.

VCC v in Q1

**Q1 in Fig. 5.6(a). Neglect the Early effect for
**

rπ vπ rπ vπ iX vX g vπ m

R out

(a)

(b)

Figure 5.6 (a) Impedance seen at emitter, (b) small-signal model.

Setting the input voltage to zero and replacing VCC with ac ground, we arrive at the small-signal

Solution

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circuit shown in Fig. 5.6(b). Interestingly, v

gmv + v = ,iX : r

= ,vX and

(5.8)

That is,

vX = 1 : iX gm + 1 r

Since r

(5.9)

= =gm

1=gm, we have Rout 1=gm.

Exercise

What happens if a resistance of value R1 is placed in series with the collector?

The above three examples provide three important rules that will be used throughout this book (Fig. 5.7): Looking into the base, we see r if the emitter is (ac) grounded. Looking into the collector, we see rO if the emitter is (ac) grounded. Looking into the emitter, we see 1=gm if the base is (ac) grounded and the Early effect is neglected. It is imperative that the reader master these rules and be able to apply them in more complex circuits.3

rO

VA = rπ

ac ac ac ac 1 gm

Figure 5.7 Summary of impedances seen at terminals of a transistor.

5.1.2 Biasing Recall from Chapter 4 that a bipolar transistor operates as an amplifying device if it is biased in the active mode; that is, in the absence of signals, the environment surrounding the device must ensure that the base-emitter and base-collector junctions are forward- and reverse-biased, respectively. Moreover, as explained in Section 4.4, ampliﬁcation properties of the transistor such as gm , r , and rO depend on the quiescent (bias) collector current. Thus, the surrounding circuitry must also set (deﬁne) the device bias currents properly. 5.1.3 DC and Small-Signal Analysis The foregoing observations lead to a procedure for the analysis of ampliﬁers (and many other circuits). First, we compute the operating (quiescent) conditions (terminal voltages and currents) of each transistor in the absence of signals. Called the “dc analysis” or “bias analysis,” this step determines both the region of operation (active or saturation) and the small-signal parameters of

3 While beyond the scope of this book, it can be shown that the impedance seen at the emitter is approximately equal to 1=gm only if the collector is tied to a relatively low impedance.

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181

each device. Second, we perform “small-signal analysis,” i.e., study the response of the circuit to small signals and compute quantities such as the voltage gain and I/O impedances. As an example, Fig. 5.8 illustrates the bias and signal components of a voltage and a current.

V BE

Bias (dc) Value

t IC

Bias (dc) Value

t

Figure 5.8 Bias and signal levels for a bipolar transistor.

It is important to bear in mind that small-signal analysis deals with only (small) changes in voltages and currents in a circuit around their quiescent values. Thus, as mentioned in Section 4.4.4, all constant sources, i.e., voltage and current sources that do not vary with time, must be set to zero for small-signal analysis. For example, the supply voltage is constant and, while establishing proper bias points, plays no role in the response to small signals. We therefore ground all constant voltage sources4 and open all constant current sources while constructing the smallsignal equivalent circuit. From another point of view, the two steps described above follow the superposition principle: ﬁrst, we determine the effect of constant voltages and currents while signal sources are set to zero, and second, we analyze the response to signal sources while constant sources are set to zero. Figure 5.9 summarizes these concepts.

DC Analysis Small−Signal Analysis

VCC R C1 V CB V BE I C1 I C2

Short Open

v in

v out

Figure 5.9 Steps in a general circuit analysis.

We should remark that the design of ampliﬁers follows a similar procedure . First, the circuitry around the transistor is designed to establish proper bias conditions and hence the necessary small-signal parameters. Second, the small- signal behavior of the circuit is studied to verify the required performance. Some iteration between the two steps may often be necessary so as to converge toward the desired behavior. How do we differentiate between small-signal and large-signal operations? In other words, under what conditions can we represent the devices with their small-signal models? If the signal perturbs the bias point of the device only negligibly, we say the circuit operates in the smallsignal regime. In Fig. 5.8, for example, the change in IC due to the signal must remain small. This criterion is justiﬁed because the amplifying properties of the transistor such as gm and r are

4 We say all constant voltage sources are replaced by an “ac ground.”

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considered constant in small-signal analysis even though they in fact vary as the signal perturbs IC . That is, a linear representation of the transistor holds only if the small-signal parameters themselves vary negligibly. The deﬁnition of “negligibly” somewhat depends on the circuit and the application, but as a rule of thumb, we consider 10 variation in the collector current as the upper bound for small-signal operation. In drawing circuit diagrams hereafter, we will employ some simpliﬁed notations and symbols. Illustrated in Fig. 5.10 is an example where the battery serving as the supply voltage is replaced with a horizontal bar labeled VCC .5 Also, the input voltage source is simpliﬁed to one node called Vin , with the understanding that the other node is ground.

VCC RC Q1 Vout V in V in Q1 VCC RC Vout

Figure 5.10 Notation for supply voltage.

In this chapter, we begin with the DC analysis and design of bipolar stages, developing skills to determine or create bias conditions. This phase of our study requires no knowledge of signals and hence the input and output ports of the circuit. Next, we introduce various ampliﬁer topologies and examine their small-signal behavior.

**5.2 Operating Point Analysis and Design
**

It is instructive to begin our treatment of operating points with an example.

Example 5.5

A student familiar with bipolar devices constructs the circuit shown in Fig. 5.11 and attempts to amplify the signal produced by a microphone. If IS = 6 10,16 A and the peak value of the microphone signal is 20 mV, determine the peak value of the output signal.

VCC RC

1 kΩ

Vout Q1 Vin

Figure 5.11 Ampliﬁer driven directly by a microphone.

Solution

Unfortunately, the student has forgotten to bias the transistor. (The microphone does not produce a dc output). If Vin (= VBE ) reaches 20 mV, then

V IC = IS exp V BE

T

(5.10)

5 The subscript

CC indicates supply voltage feeding the collector.

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Operating Point Analysis and Design

183

= 1:29 10,15 A:

This change in the collector current yields a change in the output voltage equal to

(5.11)

RC IC = 1:29 10,12 V:

(5.12)

The circuit generates virtually no output because the bias current (in the absence of the microphone signal) is zero and so is the transconductance.

Exercise

Repeat the above example if a constant voltage of 0.65 V is placed in series with the microphone.

As mentioned in Section 5.1.2, biasing seeks to fulﬁll two objectives: ensure operation in the forward active region, and set the collector current to the value required in the application. Let us return to the above example for a moment.

Example 5.6

Having realized the bias problem, the student in Example 5.5 modiﬁes the circuit as shown in Fig. 5.12, connecting the base to VCC to allow dc biasing for the base-emitter junction. Explain why the student needs to learn more about biasing.

VCC = 2.5 V RC

1 kΩ

Vout Q1

Figure 5.12 Ampliﬁer with base tied to

VCC .

The fundamental issue here is that the signal generated by the microphone is shorted to VCC . Acting as an ideal voltage source, VCC maintains the base voltage at a constant value, prohibiting any change introduced by the microphone. Since VBE remains constant, so does Vout , leading to no ampliﬁcation. Another important issue relates to the value of VBE : with VBE = VCC = 2:5 V, enormous currents ﬂow into the transistor.

Solution

Exercise

Does the circuit operate better if a resistor is placed in series with the emitter of Q1 ?

.cls v. using the sequence IB ! IC ! VCE . An example clariﬁes this issue. VCC . 2006] June 30. B note that the voltage drop across RC is equal to RC IC . For example. we write (5.15) (5.14) .2. VCCR VBE RC : B (5. Since the voltage drop across RB is equal to RB IB . RC IC . where the base is tied to VCC through a relatively large resistor.17) Calculation of VCE is necessary as it reveals whether the device operates in the active mode or not. Our objective is to determine the terminal voltages and currents of Q1 and obtain the conditions that ensure biasing in the active mode. we recall that the base-emitter voltage in most cases falls in the range of 700 to 800 mV and can be considered relatively constant. we have VCC RB Y IC X IB Q1 RC Figure 5. 5 Bipolar Ampliﬁers 5.13. Instead. we have computed the important terminal currents and voltages of Q1 .18) The circuit parameters can therefore be chosen so as to guarantee this condition. While not particularly interesting here. 2007 at 13:42 184 (1) 184 Chap.16) (5. In summary. but the resulting nonlinear equation(s) yield little intuition. The reader may wonder about the error in the above calculations due to the assumption of a constant VBE in the range of 700 to 800 mV. VCCR VBE RC VBE : B (5.13 Use of base resistance for base current path. IB = VCCR VBE : B With the base current known.13) . RB IB + VBE = VCC and hence (5.1 Simple Biasing Now consider the topology shown in Fig. and hence obtain VCE as VCE = VCC . How do we analyze this circuit? One can replace Q1 with its large-signal model and apply KVL and KCL. IC = VCCR VBE . we require the collector voltage to remain above the base voltage: .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. to avoid saturation completely. = VCC . the emitter current is simply equal to IC + IB . so as to forward-bias the base-emitter junction. RB . 5.

26) = 1:65 mA accurate VCE = VCC .16). Writing (5. 2006] June 30. we surmise that the base-emitter voltage required to carry typical current level is relatively large.27) (5.24) (5. IB = VCCR VBE B 17 A: It follows that (5. we calculate a new value for VBE : (5. Verify that Q1 operates in the forward active region.cls v. Thus.21) and (5.19) (5.28) .14. we have (5.22) (5. (5. 2007 at 13:42 185 (1) Sec. VCC = 2.5 V 100 k Ω 1 kΩ = 100 and RB RC Y IC X IB Q1 Figure 5. IB = VCCR VBE B = 16:5 A and hence (5.26) are quite close.14) as Solution . Since IS is relatively small.14 Simple biased stage.21) VBE = VT ln IC IS = 852 mV. (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Operating Point Analysis and Design 185 Example 5. 5.23) . we use VBE = 800 mV as an initial guess and write Eq. (5. Assume IS = 10. 5. RC IC = 0:85 V.20) IC = 1:7 mA: With this result for IC .17 A. That is.25) IC = 1:65 mA: Since the values given by (5. and iterate to obtain more accurate results.7 For the circuit shown in Fig. we consider IC enough and iterate no more. determine the collector bias current.

2.15 depicts an example.15) that IC heavily depends on .13 merits a few remarks. Second. Exercise What value of RB provides a reverse bias of 200 mV across the base-collector junction? The biasing scheme of Fig.cls v. in low-voltage design—an increasingly common paradigm in modern electronic systems— the bias is more sensitive to VBE variations among transistors or with temperature .52. 2007 at 13:42 186 (1) 186 Chap. then IC rises to 1. the topology of Fig. a parameter that may change considerably. 5. where R1 and R2 act as a voltage divider. 5.98 mA and VCE falls to 0. driving the transistor toward heavy saturation. 1+ 2 if the base current is negligible. Thus. 2006] June 30. (5.2 Resistive Divider Biasing In order to suppress the dependence of IC upon . we recognize from Eq. providing a baseemitter voltage equal to VX = R R2 R VCC . we return to the fundamental relationship IC = IS expVBE =VT and postulate that IC must be set by applying a well-deﬁned VBE . In the above example.VBE determines the base current. the effect of VBE “uncertainty” becomes more pronounced at low values of VCC because VCC . Figure 5.13 is rarely used in practice. For these reasons. 5. 5 Bipolar Ampliﬁers a value nearly equal to VBE .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.29) . First. if increases from 100 to 120. (5. Thus. The transistor therefore operates near the edge of active and saturation modes.

Figure 5.15 Use of resistive divider to deﬁne VBE . Verify that the Determine the collector current of Q1 in Fig. = 100.17 A and base current is negligible and the transistor operates in the active mode. 5.30) a quantity independent of . the design must ensure that the base current remains negligible. Example 5. 1 2 T VCC R1 Y X R2 RC IC Q1 (5. R VCC IC = IS exp R +2 R V .8 . Nonetheless.16 if IS = 10.

5 V 17 k Ω 187 R1 RC Y 5 kΩ IC X 8 kΩ Q1 R2 Figure 5.36) R1 + R2 : This condition indeed holds in this example because VCC =R1 + R2 = 100 A 43IB .35) Is the base current negligible? With which quantity should this value be compared? Provided by the resistive divider.16 Example of biased stage.33) (5. IB must be negligible with respect to the current ﬂowing through R1 and R2 : VCC (5.34) IB = 2:31 A: (5. requiring veriﬁcation at the end.cls v.32) BE IC = IS exp VV T = 231 A and (5.31) (5. (5. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Operating Point Analysis and Design VCC = 2. 2007 at 13:42 187 (1) Sec. But what if the end result indicates that IB is not negligible? We now analyze the circuit without this assumption. we have Solution VX = R R2 R VCC 1+ 2 = 800 mV: It follows that (5. Let us replace the voltage divider with a Thevenin . IB ? We also note that VCE = 1:345 V. Neglecting the base current of Q1 . 2006] June 30.37) Exercise What is the maximum value of RC if Q1 must remain in soft saturation? The analysis approach taken in the above example assumes a negligible base current. and hence Q1 operates in the active region.

As in the previous examples.40) IC = IS exp VThev . VT ln IC R 1 . 5. Calculate the collector current of Q1 in Fig. Assume .39) VX = VThev . IB RThev and (5.38) RThev = R1 jjR2 : The simpliﬁed circuit yields: (5. 5 Bipolar Ampliﬁers equivalent (Fig. (5.18(a). we rewrite (5. but the exponential dependence in IB = VThev . For this reason. 2007 at 13:42 188 (1) 188 Chap. iterations prove useful here.41) Eq.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VThev = R R2 R VCC : 1+ 2 Moreover.17 Use of Thevenin equivalent to calculate bias.17). 5. The iteration then follows the sequence VBE ! IB ! IC ! VBE ! .42) IS Thev and begin with a guess for VBE = VT lnIC =IS .41) gives rise to wide ﬂuctuations in the intermediate solutions.cls v. (5. RThev is given by the output resistance of the network if VCC is set to zero: (5. noting that VThev is equal to the open-circuit output voltage (VX when the ampliﬁer is disconnected): VCC R1 VCC RC IC X R2 R1 VCC R2 VThev Q1 V Thev R1 R2 R Thev X IB VCC RC IC Q1 Figure 5.41) as This result along with IC = IB forms the system of equations leading to the values of IC and IB . 2006] June 30. IB RThev : V T (5.

17 A. Constructing the equivalent circuit shown in Fig. we note that VThev = R R2 R VCC 1+ 2 (5.18(b). Example 5.9 Solution = 100 and IS = 10.43) . 5.

VBE 766 mV and IC = 63 A.cls v. Continuing the iteration.49) (5. In other words. The circuit is therefore still of little practical value. a 1 error in one resistor value introduces a 36 error in the collector current. After many iterations. For example. VBE RThev = 0:919 A: Thus.48) = IB = 91:9 A and VBE = VT ln IC IS = 776 mV: (5. we obtain VBE = 757 mV. (b) stage with Thevenin equivalent for the resistive divider and CC . . IB = 0:79 A and IC = 79:0 A. 2007 at 13:42 189 (1) Sec. Exercise How much can R2 be increased if Q1 must remain in soft saturation? While proper choice of R1 and R2 in the topology of Fig.47) (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. IC (5.18 (a) Stage with resistive divider bias.15 makes the bias relatively insensitive to . 5. if R2 is 1 higher than its nominal value.50) It follows that IB = 0:441 A and hence IC = 44:1 A. V = 800 mV and (5. the exponential dependence of IC upon the voltage generated by the resistive divider still leads to substantial bias variations. 2006] June 30. 5. so is VX .44) RThev = R1 jjR2 = 54:4 k : (5. still a large ﬂuctuation with respect to the ﬁrst value from above.5 V 170 k Ω 189 VCC RC R Thev X V Thev IB IC Q1 R1 RC Y 5 kΩ X 80 k Ω IC IB Q1 R2 Figure 5.45) (5. thereby arriving at the base current: IB = VThev . thus multiplying the collector current by exp0:01VBE =VT 1:36 (for VBE = 800 mV).46) We begin the iteration with an initial guess VBE = 750 mV (because we know that the voltage drop across RThev makes VBE less than VThev ).2 Operating Point Analysis and Design VCC = 2.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this occurs because RE exhibits a linear (rather than exponential) IV relationship. as described later in this chapter. E . 2007 at 13:42 190 (1) 190 Chap. an error in VX due to inaccuracies in R1 . From an intuitive viewpoint. 5 Bipolar Ampliﬁers 5.cls v.2.19 Addition of degeneration resistor to stabilize bias point. thereby lowering the sensitivity to VBE .” the VCC R1 Y X R2 P RC IC Q1 IE RE Figure 5. Also. introducing a smaller error in VBE and hence IC . let us determine the bias currents of the transistor. yielding V IE = RP 1 =R VCC R R2 R . To understand the above property.3 Biasing with Emitter Degeneration A biasing conﬁguration that alleviates the problem of sensitivity to and VBE is shown in Fig. 2006] June 30. Here. Thus.19. 5. R2 . or VCC is partly “absorbed” by RE . addition of RE in series with the emitter alters many attributes of the circuit. we have VX = VCC R2 =R1 + R2 . VBE . VP = VX . resistor RE appears in series with the emitter. Called “emitter degeneration. Neglecting the base current. VBE E 1+ 2 IC .

57) . i. (5.55) = 800 mV as an initial guess.51) (5.e.52) (5.17 A. the difference between VCC R2 =R1 + R2 and VBE is large enough to absorb and swamp such variations. An example illustrates this point. Calculate the bias currents in the circuit of Fig. 5.54) (5. Assume = 100 and IS = 5 10. How can this result be made less sensitive to VX or VBE variations? If the voltage drop across RE ..20 and verify that Q1 operates in the forward active region. (5.10 Solution We neglect the base current and write VX = VCC R R2 R 1+ 2 = 900 mV: Using VBE (5.53) if 1. How much does the collector current change if R2 is 1 higher than its nominal value? Example 5.56) (5. VBE = 100 mV. then IE and IC remain relatively constant. we have VP = VX .

Is the assumption of negligible base current valid? With IC 1 mA.9 can be followed.57) suggests that a 4-mV error in VBE leads to a 4 error in VP and hence IE . raising the emitter current by 9 mV=100 = 90 A. We may assume that the 9-mV change directly appears across RE .61) (5. (5.5 V 16 k Ω 191 R1 RC Y X 1 kΩ Q1 P RE 100 9 kΩ R2 Ω Figure 5. (5. Exercise What value of R2 places Q1 at the edge of saturation? The bias topology of Fig. and (2) VRE must be large enough (100 mV to several hundred millivolts) to suppress the effect of uncertainties in VX and VBE . and hence IE IC 1 mA: With this result. indicating a good approximation. which is reasonable because the emitter and collector currents have changed by only 9.56). the device is indeed in the active region. 5. Eq. two rules are typically followed: (1) I1 IB to lower sensitivity to . we must reexamine the assumption of VBE (5.19 is used extensively in discrete circuits and occasionally in integrated circuits. The collector voltage is given by VY = VCC . we note that this assumption is equivalent to considering VBE constant.2 Operating Point Analysis and Design VCC = 2. For greater accuracy.58) = 800 mV. Since (5. 2007 at 13:42 191 (1) Sec.59) (5.cls v.9 V. Furthermore.62) With the base voltage at 0.21. 5. The assumption is therefore reasonable. IB 10 A whereas the current ﬂowing through R1 and R2 is equal to 100 A.20 Example of biased stage. an iterative procedure similar to that in Example 5. From Eq. then (5. we conclude that the initial guess is reasonable. Let us now determine if Q1 operates in the active mode. .54) indicates that VX rises to approximately 909 mV. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. IC RC = 1 :5 V : (5. If R2 is 1 higher than its nominal value.60) VBE = VT ln IC IS = 796 mV. Illustrated in Fig. 2006] June 30.

To establish VX = VBE + RE IC = 978 mV. 200 mV. What is the maximum tolerable value of RC ? Example 5.. RC IC 1:522 V: (5.68) . Assume VCC = 2:5 V. that is. R2 . 2007 at 13:42 192 (1) 192 VCC R1 I1 I 1 >> I B R2 RE X IB Y Chap.1 translates to a collector current of 0.66) . Assuming RE IC = 200 mV. we obtain RE = 400 . = 100. RC IC . R1 + R2 = 50 k .5 mA and a VBE of 778 mV. Thus.21 so as to provide a transconductance of 1=52 for Q1 . For the base current IB = 5 A to be negligible. 5 Bipolar Ampliﬁers R C Small Enough to Avoid Saturation IC Q1 VRE >> Variations in VX and VBE Figure 5.63) yields R1 = 30:45 k R2 = 19:55 k : How large can RC be? Since the collector voltage is equal to VCC following constraint to ensure active mode operation: (5.65) (5.g. RC IC VX .64) (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. choose a value for VRE IC RE .11 must have . the value of RC is bounded by a maximum that places Q1 at the edge of saturation.g. Determined by small-signal gain requirements. (3) calculate VX = VBE + IC RE with VBE = VT lnIC =IS .. where the base current is neglected. VCC R1 + R2 IB . e.67) VCC .cls v. 5. by a factor of 10. e. Design the circuit of Fig. we pose the (5.17 A.21 that serves most applications: (1) decide on a collector bias current that yields proper small-signal parameters such as gm and r . The following example illustrates these concepts.21 Summary of robust bias conditions. 2006] June 30. and VBE .63) (5. which in conjunction with (5. Design Procedure It is possible to prescribe a design procedure for the bias topology of Fig. and IS = 5 10. we A gm of 52 Solution R2 R1 + R2 VCC = VBE + RE IC . (2) based on the expected variations of R1 . (4) choose R1 and R2 so as to provide the necessary value of VX and establish I1 IB .

2 Operating Point Analysis and Design 193 Consequently. obtaining R1 + R2 (5. It follows that R1 = 1:45 k R2 = 3:55 k : (5. (2) if we choose a very large VRE .64) as VCC R1 + R2 100IB . We rewrite (5. leading to a low input impedance. Exercise The two rules depicted in Fig. leading to RC VCC . 400 mV and hence a greater value for RC . Repeat Example 5. the collector voltage must exceed this value to avoid saturation.1.cls v.21 to lower sensitivities do impose some trade-offs. in low-voltage applications.. loading the preceding stage.1.70) =5k . Also. i. thereby limiting the minimum value of the collector voltage to avoid saturation.11 introduce a low input impedance. 5.3.71) (5.69) If RC exceeds this value. The value of RE is now given by 500 mV=0:5 mA = 1 k . then VX (= VBE + VRE ) must be high. Let us return to the above example and study these issues.e.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. an overly conservative design faces the following issues: (1) if we wish I1 to be much much greater than IB . We compute the exact input impedance of this circuit in Section 5.72) Since the base voltage has risen to 1. the collector voltage falls below the base voltage. VX IC 1:044 k : (5. the transistor can tolerate soft saturation. RC 3:044 k : (5.278 V.63) still holds. Also. As mentioned in Chapter 4.74) As seen in Section 5. VX = VBE + RE IC = 1:278 V and (5. .73) (5. 2007 at 13:42 193 (1) Sec. Specifically.11 but assuming VRE Example 5.12 Solution = 500 mV and I1 100IB . we may allow VY VX . the much smaller values of R1 and R2 here than in Example 5. up to about 400 mV of base-collector forward bias. Thus. the reduction in RC translates to a lower voltage gain. Repeat the above example if the power budget is only 1 mW and the transconductance of Q1 is not given.3. then R1 + R2 and hence R1 and R2 are quite small. 2006] June 30. The collector current and base-emitter voltage remain unchanged. 5.

compute IC . 5 Bipolar Ampliﬁers Exercise Repeat the above example if VRE is limited to 100 mV. if RC increases indeﬁnitely.4 Self-Biased Stage Another biasing scheme commonly used in discrete and integrated circuits is shown in Fig.76) (5. this stage exhibits many interesting and useful attributes. RC carries a current We now determine the collector bias current by assuming IB equal to IC . For example. we begin with an initial guess for VBE .17 A.78) = VT lnIC =IS k Determine the collector current and voltage of Q1 in Fig. and utilize VBE to improve the accuracy of our calculations. RC IC : Also. (5.13 . IB RB . VCC RB IB X RC Y IC Q1 Figure 5. 5. RBE : RC + B As usual. A result of self-biasing. 5. Let us begin the analysis of the circuit with the observation that the base voltage is always lower than the collector voltage: VX = VY .e. Example 5. Q1 remains in the active region. RB = 10 VCC = 2:5 V.. IS = 5 10. 2006] June 30.77) gives (5.77) V IC = VCC . and = 100. 5. 5.2. a critical advantage over the circuit of Fig.22 Self-biased stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. .75) VY = RB IB + VBE = RB IC + VBE : Equating the right hand sides of (5.22 if RC = 1 k .75) and (5. this important property guarantees that Q1 operates in the active mode regardless of device and circuit parameters.21.cls v. Repeat the calculations for RC = 2 k . i. 2007 at 13:42 194 (1) 194 Chap. (5.22. Called “self-biased” because the base current and voltage are provided from the collector. IC . thereby yielding VY = VCC .

78).2 Operating Point Analysis and Design 195 Assuming VBE Solution = 0:8 V.78) together with the condition RC RB = provides the basic expressions for the design of the circuit.84) The choice of RB also depends on small-signal requirements and may deviate from this value.82) = VT lnIC =IS . 1 C where VBE (5. (5.14 = 1=13 and VCC = 1:8 V. VBE must be much greater than the uncertainties in the value of VBE . Since RB IB = 81 mV. That is. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we choose RC = 10RB = and rewrite (5. RC = VCC:1I VBE 1 C R = RC : B (5.79) and hence VBE = VT lnIC =IS = 807:6 mV. IC RC VBE . 5. IC VCCR VBE . With the required value of IC known from smallsignal considerations. but it must remain substantially lower than RC . (5. C (5. IC = VCC:1RVBE . . Design the self-biased stage of Fig.83) (5.78) gives IC = 0:810 mA: (5. then with VBE = 0:8 V.78): IC = 1:545 mA. In fact. VY 0:881 V.78) as .78) and the above example suggest two important guidelines for the design of the self-biased stage: (1) VCC . 2007 at 13:42 195 (1) Sec. if RC RB = . 5. concluding that the initial guess for VBE and the value of IC given by it are reasonably accurate.22 for gm IS = 5 10. we write VBE = VT lnIC =IS = 791 mV. we have from (5. (2) RC must be much greater than RB = to lower sensitivity to . If RC = 2 k . Eq. Assume . This result serves as a quick estimate of the transistor bias . We also note that RB IB = 154:5 mV and VY = RB IB + VBE 0:955 V.80) is acceptable.cls v. Exercise What happens if the base resistance is doubled? Equation (5. VBE in the numerator of (5. then and VY = VCC conditions.80) To check the validity of the initial guess. the 9-mV error is negligible and the value of IC in (5.81) Design Procedure Equation (5. Compared with VCC .16 A and = 100. . 10 Example 5.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V. Exercise Repeat the above design with a supply voltage of 2. Circuits using pnp devices follow the same analysis and design procedures while requiring attention to voltage and current polarities.86) Also.2. 5 Bipolar Ampliﬁers Since gm Solution = IC =VT = 1=13 .88) Note that RB IB = 95 mV. Calculate the collector and voltage of Q1 in the circuit of Fig. R1 I1 RB RC R1 RC Q1 Q1 R2 Sensitive to Resistor Errors RC Q1 RE VRE R2 RB RC Q1 Always in Active Mode Sensitive to β Figure 5. VBE = 754 mV.23 Summary of biasing techniques.23 summarizes the biasing principles studied in this section.85) (5. (5.24 and determine the maximum allowable value of RC for operation in the active mode. 2006] June 30.89) . We illustrate these points with the aid of some examples. Figure 5. Example 5. IB RB + VEB = VCC : (5.cls v.13 and we have. RC VCC:1I VBE 1 C 475 : R RB = 10C = 4:75 k : (5. 2007 at 13:42 196 (1) 196 Chap. yielding a collector voltage of 754 mV + 95 mV = 849 mV. we have IC = 2 mA. 5.15 Solution The topology is the same as that in Fig. 5. and . 5.87) (5.5 Biasing of PNP Transistors The dc bias topologies studied thus far incorporate npn transistors.

95) (5. That is.25(b): Example 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.94) = IC RC.92) RC. IC RC. 5. since VX = IB RB and VY = IC RC .2 Operating Point Analysis and Design VCC Q1 Y IC RC 197 IB RB VEB X Figure 5. we assume IB is signiﬁcant and construct the Thevenin equivalent of the voltage divider as depicted in Fig. The transistor enters saturation at VY = VX . 5.16 Solution VThev = R R1 R VCC 1+ 2 RThev = R1 jjR2 : (5.max Exercise For a given RC . 2006] June 30.90) .. VEB ) and bringing Q1 closer to saturation. . VEB C = RB : From another perspective. 2007 at 13:42 197 (1) Sec. 5. (5.91) The circuit suffers from sensitivity to .max = VCC .cls v. we have IB RB as the condition for edge of saturation. As a general case.93) (5. what value of RB places the device at the edge of saturation? Determine the collector current and voltage of Q1 in the circuit of Fig. VY rises. i.e. IB = VCCR VEB B and (5. IC = VCCR VEB : B (5. thus approaching VX (= VCC . VEB and hence (5.max = VCC I.24 Simple biasing of pnp stage.96) .max . obtaining RB = RC.25(a). If RC is increased.

some iteration between IC and VEB may be necessary. 5 Bipolar Ampliﬁers VCC R2 I1 R1 I B VEB X Y IC RC (a) (b) VCC R Thev IB VEB X V Thev Y IC RC Q1 Q1 Figure 5.25 (a) PNP stage with resistive divider biasing.97) V IB = VCC . (b) Thevenin equivalent of divider and VCC . thereby R2 V = V R1 + R2 CC EB . VEB Thev R2 V .cls v. VEB : IC = (5.98) (5. V CC EB 2 = R1 + RR : Thev It follows that (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.100) indicates that if IB is signiﬁcant. 2006] June 30. Equation (5. that is.100) RThev As in Example 5. then the transistor bias heavily depends on . Adding the voltage drop across RThev and VEB to VThev yields VThev + IB RThev + VEB = VCC . if IB I1 . (5. 2007 at 13:42 198 (1) 198 Chap. RThev .99) obtaining the collector current: R2 R1 + R2 VCC . On the other hand. we equate the voltage drop across R2 to VEB .9.

Exercise What is the maximum value of RC is Q1 must remain in soft saturation? Example 5. (5. calculate the collector current and voltage of Q1 in the .102) T Note that this result is identical to Eq.17 Assuming a negligible base current. R2 VCC IC = IS exp R + R V : 1 2 (5.30).101) (5.

2 Operating Point Analysis and Design 199 circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 199 (1) Sec. 5.26. 5.103) IE = R1 . Adding to VX the emitter-base voltage and the drop across RE . 2006] June 30. What is the maximum allowable value of forward active region? VCC R2 I1 RE I B VEB X R1 Y IC RC Q1 VRE RC for Q1 to operate in the Figure 5.cls v. we obtain Solution VX + VEB + RE IE = VCC and hence (5.26 PNP stage with degeneration resistor. With IB I1 . we have VX = VCC R1 =R1 + R2 .

e.maxIC 1+ 2 . with IB = IC = .. In arriving at (5. VEB : E R1 + R2 (5.104) Using IC IE . 1+ 2 VCC R R1 R = RC. R2 VCC . Eq. we can compute a new value for VEB and iterate if necessary. we have written a KVL from VCC to ground. i. But a more straightforward approach is to recognize that the voltage drop across R2 is equal to VEB + IE RE . Also.104). we can verify the assumption IB I1 . (5.103). VCC R R2 R = VEB + IE RE .

max = RE VCC R R1 R 1+ 2 R2 V .106) (5. The maximum allowable value of RC is obtained by equating the base and collector voltages: (5.max 2 V .105) which yields the same result as in (5.108) . V : R1 + R2 CC EB 1 (5.104).V R R1 + R2 CC EB : E It follows that (5.107) RC. R RC.

RB . 2007 at 13:42 200 (1) 200 Chap. VX = RB IB + VY = RB IB + RC IC . We must write a KVL from VCC through the emitter-base junction of Q1 . Since 1 and hence IC IB .27 Self-biased pnp stage. yielding Solution VCC = VEB + VX = VEB + RB IB + IC RC . RC carries a current approximately equal to IC . creating VY = RC IC . 5.cls v.27. VCC Q1 IB RB Y IC RC Example 5. Moreover. 5 Bipolar Ampliﬁers Exercise Repeat the above example if R2 = 1. Determine the collector current and voltage of Q1 in the self-biased circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.18 X VEB Figure 5. and RC to ground.

Note that. Q1 always remains in the active mode.78).109) (5. and determine a new value for VEB . (5. VEB .112) a result similar to Eq.111) CC IC = VRB . + RC (5.110) (5. compute IC . = VEB + RB + RC IC : Thus. we begin with a guess for VEB . As usual. since the base is higher than the collector voltage. (5. etc. Exercise How far is Q1 from saturation? .

5. We study each carefully. Similarly. The reader is encouraged to review Examples (5.1 pointed to the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. leading to nine possible combinations of input and output networks and hence nine ampliﬁer topologies. respectively) so as to avoid confusion in more complex topologies. seeking to compute its gain and input and output impedances.28(d)-(f)]. The above observations reveal three possible ampliﬁer topologies.28(a)(c). 5. the large-signal behavior of ampliﬁers also becomes important in many applications. The number of possibilities therefore falls to four.4) and the three resulting rules illustrated in Fig.28(b) and (e) remain incompatible because Vout would be sensed at the input node (the emitter) and the circuit would provide no function. 5. 5.3 Bipolar Ampliﬁer Topologies Following our detailed study of biasing. Nevertheless. 5.3.1 Common-Emitter Topology Our initial thoughts in Section 4. v in v in v in (a) (b) (c) v out v out v out (d) (e) Figure 5.3 Bipolar Ampliﬁer Topologies 201 5.2)-(5.28(a)] and the output signal is sensed at the collector [Fig. But we note that the input and output connections in Figs. . The term “common-emitter” is used because the emitter terminal is grounded and hence appears in common to the input and output ports. 5.7 before proceeding further. Also. 5.6 Since the bipolar transistor contains three terminals. 2007 at 13:42 201 (1) Sec. we may surmise that three possibilities exist for applying the input signal to the device. 5. This property rules out the input connection shown in Fig.29).28(f) proves of no value as Vout is not a function of the collector current. We have encountered and analyzed this circuit in different contexts without giving it a name. (f) However. as seen in Chapter 4. If the input signal is applied to the base [Fig.1(b) and hence the topology of Fig. we identify the stage based on the input and output connections (to the base and from the collector.cls v. 4. 4. In all cases.25 as an ampliﬁer. the circuit is called a “common-emitter” (CE) stage (Fig.28 Possible input and output connections to a bipolar transistor.28(d)]. the bipolar transistors operate in the active mode. as conceptually illustrated in Figs. 6 While beyond the scope of this book. 5. we can now delve into different ampliﬁer topologies and examine their small-signal properties. 5. the output signal can be sensed from any of the terminals (with respect to ground) [Figs. 2006] June 30.28(c) because here Vin does not affect the base or emitter voltages. bipolar transistors operating in the active mode respond to base-emitter voltage variations by varying their collector current. the topology in Fig. 5.

the collector bias current) and the collector resistor. 2006] June 30. acts as an ac ground because its value remains constant with time. VCC . 5.30. and (b) analysis of the CE stage including the bias circuitry as a more realistic case. the small-signal gain is negative because raising the base voltage and hence the collector current in Fig. but this drop cannot exceed VCC . In fact. we have = vout =vin .. vout = gm v .e. Interestingly.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. As explained in Chapter 4. In order to examine the amplifying properties of the CE stage.115) . R C and v = vin .114) embodies two interesting and important properties of the CE stage. denoting the dc drop across RC with VRC and writing gm = IC =VT .30 Small-signal model of CE stage. Let us ﬁrst compute the small-signal voltage gain Av port and writing a KCL at the collector node. we express (5. 2007 at 13:42 202 (1) 202 VCC RC Vout Chap. Beginning from the output (5. v in rπ vπ g vπ m v out − RC RC v out Figure 5.29 lowers Vout . We neglect the Early effect for now. the supply voltage node.cls v. Av is proportional to gm (i.4. 5. the voltage gain of the stage is limited by the supply voltage.29 increases the collector current by gm V and hence the voltage drop across RC by gm V RC .114) Equation (5. RC . A higher collector bias current or a larger RC demands a greater voltage drop across RC . shown in Fig. Second. 5 Bipolar Ampliﬁers V in Q 1 Output Sensed at Collector Input Applied to Base Figure 5. we construct the small-signal equivalent of the circuit. We deal with the CE ampliﬁer in two phases: (a) analysis of the CE core to understand its fundamental properties.113) . Analysis of CE Core Recall from the deﬁnition of transconductance in Section 4.29 Common-emitter stage.114) as jAv j = IC RC V T (5. It follows that Av = .gmRC : (5. First.3 that a small increment of V applied to the base of Q1 in Fig.

A more aggressive design may allow Q1 to operate in soft saturation. 5.123) Under this condition. e. a 2-mVpp input signal gives rise to a 107. the maximum voltage gain is given by (5.121) The voltage gain is therefore equal to Av = . forward-biasing the base-collector junction for half of each cycle.31(a). (5.I400 mV C 2:52 k : In this case. driving Q1 into heavy saturation [Fig. VBE C 1:8 k : (5.8-mVpp output.118) Example 5. . so long as Q1 remains in soft saturation (VBC 400 mV). jAv j VCC V VBE : T Design a CE core with VCC voltage gain. the circuit can now tolerate only very small voltage swings at the output. Nevertheless.120) (5. 2007 at 13:42 203 (1) Sec. the transistor itself requires a minimum collector-emitter voltage of about VBE to remain in the active region. an input signal drives the transistor into saturation.53:9: (5.122) (5. The value of RC that places Q1 at the (5.g.19 = 1:8 V and a power budget..3 Bipolar Ampliﬁer Topologies 203 RC = VV : T Since VRC (5. 5.119) Since P = IC VCC = 1 mW.38:5: (5. along with VBE 800 mV. of 1 mW while achieving maximum = 0:556 mA. 2006] June 30.cls v. RC IC = VBE .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.126) Of course.125) Av = .gmRC = . P . we have IC edge of saturation is given by Solution VCC .124) (5. VCE 400 mV and hence RC VCC . CC jAv j VV : T (5. which.117) Furthermore. yields RC VCC I. a 2-mVpp input results in a 77-mVpp output. As illustrated in Fig. the circuit ampliﬁes properly. lowering the limit to . For example.116) VCC .

32(a). iX vX rπ vπ g vπ m RC rπ vπ g vπ m RC (5.31(b)]. the dependent current source also vanishes. 5. 5. leaving .cls v. 5. 5 Bipolar Ampliﬁers 77 mV pp 800 mV Q1 t t (a) VCC RC 2 mVpp 800 mV 400 mV 107.” Exercise Repeat the above example if VCC = 2:5 V and compare the results.8 mVpp Q1 t t (b) Figure 5. Since v = 0.128) =gm = VT =IC and decreases as the collector iX vX (a) (b) Figure 5. We say the circuit suffers from a trade-off between voltage gain and voltage “headroom. 2007 at 13:42 204 (1) 204 VCC RC 2 mVpp 800 mV Chap.127) (5. the input impedance is simply equal to bias increases.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Let us now calculate the I/O impedances of the CE stage. 2006] June 30.31 CE stage (a) with some signal levels.32(b). where the input voltage source is set to zero (replaced with a short). The output impedance is obtained from Fig. we write Rin = vX iX = r : Thus. Using the equivalent circuit depicted in Fig. (b) in saturation.32 (a) Input and (b) output impedance calculation of CE stage.

We will develop other circuits in this book that avoid this “coupling” of design speciﬁcations.3 Bipolar Ampliﬁer Topologies 205 RC as the only component seen by vX . 5.131) (5. For example.gm RC .114) suggests that the voltage gain of the CE stage can be increased indeﬁnitely if RC ! 1 while gm remains constant.33 CE stage trade-offs. Rout : Rin (5.130) The output impedance therefore trades with the voltage gain.5.4. thereby lowering both the voltage headroom and the input impedance. if the I/O impedances are speciﬁed. Rout = vX iX = RC : (5. 2006] June 30. Mentioned in Section 4.129) (5. Figure 5. In other words.33 summarizes the trade-offs in the performance of the CE topology along with the parameters that create such trade-offs. From an intuitive point of view. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. A CE stage must achieve an input impedance of Rin and an output impedance of Rout . for a given value of output impedance. Voltage Headroom (Swings) g m Voltage Gain RC Output Impedance RC Input Impedance β gm Figure 5. .20 Solution = r = =gm and Rout = RC . 2007 at 13:42 205 (1) Sec. What is the voltage gain of the circuit? Since Rin Example 5. Exercise What happens to this result if the supply voltage is halved? Inclusion of Early Effect Equation (5.132) Interestingly.cls v. then the voltage gain is automatically set. a given change in the input voltage and hence the collector current gives rise to an increasingly larger output swing as RC increases.gmRC = . RC is ﬁxed and the voltage gain can be increased by increasing IC . this trend appears valid if VCC is also raised to ensure the transistor remains in the active mode. we have Av = .

allowing us to rewrite (5.gmRC jjrO 35: (As a comparison. Since achieving a high gain proves critical in circuits such as operational ampliﬁers.143) . Example 5.142) (5. then Av 38.) For the I/O impedances.gm RC jjrO : (5.cls v.139) (5. determine the small-signal voltage gain and the I/O impedances.140) = 1. 2006] June 30.134) Figure 5.137) (5.133) We also recognize that the input impedance remains equal to r whereas the output impedance falls to Rout = RC jjrO : v in rπ vπ g vπ m rO RC v out (5. if VA (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Figure 5. (5.1 rO = VA I C Thus.136) = 26 .21 = 100 Solution We have I gm = VC T and (5. 5.34 depicts the small-signal equivalent circuit of the CE stage including the transistor output resistance. the Early effect limits the voltage gain even if RC approaches inﬁnity.29 is biased with a collector current of 1 mA and RC = 1 k . 5 Bipolar Ampliﬁers In reality. If and VA = 10 V.141) (5.135) (5. we must reexamine the above derivations in the presence of the Early effect.114) as Av = . Note that rO appears in parallel with RC .138) = 10 k : Av = .34 CE stage including Early effect. The circuit of Fig. however. we write Rin = r =g m = 2:6 k (5. 2007 at 13:42 206 (1) 206 Chap.

7 In this book. thus leaving a voltage change across the BE junction that is less than V .” this technique improves the “linearity” of the circuit and provides many other interesting properties that are studied in more advanced courses.gmrO : role in high-gain ampliﬁers. 5.29 is modiﬁed as shown in Fig. As with the CE core. some fraction of V appears across RE . Consequently.133) gives (5. We therefore expect that the voltage gain of 7 But other second-order effects limit the actual gain to about 50.” deﬁned as AI = iiout . Equation (5.29 because the entire collector current is delivered to RC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. assuming Q1 is biased properly. producing a collector current change of gm V .133). the intrinsic gain of a bipolar transistor is independent of the bias current. We rarely deal with this parameter for voltage ampliﬁers. 5.144) (5.cls v. But with RE 6= 0. CE Stage With Emitter Degeneration In many applications. where a resistor RE appears in series with the emitter. 5. (5. Another parameter of the CE stage that may prove relevant in some applications is the “current gain. the CE core of Fig. In modern integrated bipolar transistors.146) Av = . we assume gm rO 1 (and hence rO 1=gm) for all transistors. it is instructive to make some qualitative observations.148) where iout denotes the current delivered to the load and iin the current ﬂowing to the input. We now substitute gm = IC =VT and rO gm rO represents the maximum voltage gain provided by a single transistor. thereby arriving at T (5. we intend to determine the voltage gain and I/O impedances of the circuit. Let us determine the gain of a CE stage as RC ! 1. yielding a gain of nearly 200. playing a fundamental = VA =IC in Eq. VA falls in the vicinity of 5 V. 2007 at 13:42 207 (1) Sec.3 Bipolar Ampliﬁer Topologies 207 and Rout = RC jjrO = 0:91 k : (5.35(a). jAv j = VA : V Interestingly. the collector current change is also less than gm V .145) Exercise Calculate the gain if VA = 5 V. Before delving into a detailed analysis. then the base-emitter voltage would also increase by V .147) Called the “intrinsic gain” of the transistor to emphasize that no external device loads the circuit. 2006] June 30.35(b)]. but note that AI = for the stage shown in Fig. If RE were zero. . Called “emitter degeneration. 5. Suppose the input signal raises the base voltage by V [Fig. in (5.

5. Rin = r + + 1RE . 5 VCC RC Vout Bipolar Ampliﬁers ∆V RE Q1 (a) (b) Figure 5. where VCC is replaced with an ac ground and the Early effect is neglected. Depicted in Fig. we have vin = v + vRE . (b) effect of input voltage change.cls v. we ﬁrst write a KCL at the output node. R C obtaining (5. the voltage drop across RE is given by vRE = r + gm v RE : Since the voltage drop across r and RE must add up to vin .36 is the small-signal equivalent circuit. gvout : R m C (5. emitter degeneration increases the input impedance of the CE stage. gm v = . vout . Note that v appears across r and not from the base to ground. a desirable property.35 (a) CE stage with degeneration. To determine vout =vin . 2007 at 13:42 208 (1) 208 VCC RC Vout V in RE Q1 Chap.36 Small-signal model of CE stage with emitter degeneration.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.150) We also recognize that two currents ﬂow through RE : one originating from r equal to v =r and another equal to gm v . the reduction in gain is incurred to improve other aspects of the performance. A common mistake is to conclude that Rin = r + RE . the degenerated stage is lower than that of the CE core with no degeneration. v out v in rπ vπ RE g vπ m RC Figure 5. yielding an input impedance greater than =gm = r . the base current also changes by less than gm V= . How about the input impedance? Since the collector current change is less than gm V . Thus. but as explained below. Thus.149) v = . While undesirable. We now quantify the foregoing observations by analyzing the small-signal behavior of the circuit.

= v + v + gm v RE r .

v

(5.151)

(5.152) (5.153)

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Bipolar Ampliﬁer Topologies

209

= v 1 + r1 + gm RE :

Substituting for v from (5.150) and rearranging the terms, we arrive at

(5.154)

vout = ,

gm RC : vin 1 + r1 + gm RE

As predicted earlier, the magnitude of the voltage gain is lower than gm RC for RE 1, we can assume gm 1=r and hence

(5.155)

6= 0. With

(5.156)

g Av = , 1 +m RC : g R

m E

Thus, the gain falls by a factor of 1 + gm RE . To arrive at an interesting interpretation of Eq. (5.156), we divide the numerator and denominator by gm ,

Av = , 1 RC : gm + RE

(5.157)

It is helpful to memorize this result as “the gain of the degenerated CE stage is equal to the total load resistance seen at the collector (to ground) divided by 1=gm plus the total resistance placed in series with the emitter.” (In verbal descriptions, we often ignore the negative sign in the gain, with the understanding that it must be included.) This and similar interpretations throughout this book greatly simplify the analysis of ampliﬁers—often obviating the need for drawing smallsignal circuits.

Example 5.22

Determine the voltage gain of the stage shown in Fig. 5.37(a).

VCC RC v out v in RE rπ2

(a) (b)

VCC RC VCC v in Q2 RE rπ2 Q1 v out

Q1

Figure 5.37 (a) CE stage example, (b) simpliﬁed circuit.

We identify the circuit as a CE stage because the input is applied to the base of Q1 and the output is sensed at its collector. This transistor is degenerated by two devices: RE and the base-emitter junction of Q2 . The latter exhibits an impedance of r2 (as illustrated in Fig. 5.7), leading to the simpliﬁed model depicted in Fig. 5.37(b). The total resistance placed in series with the emitter is

Solution

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therefore equal to RE jjr2 , yielding

Av = , 1 RC : + RE jjr2 gm1

(5.158)

Without the above observations, we would need to draw the small-signal model of both Q1 and Q2 and solve a system of several equations.

Exercise

Repeat the above example if a resistor is placed in series with the emitter of Q2 .

Example 5.23

Calculate the voltage gain of the circuit in Fig. 5.38(a).

VCC RC v out v in RE Q1 Q2 RE VCC v in Q1 rπ2 VCC RC v out

(a) Figure 5.38 (a) CE stage example, (b) simpliﬁed circuit.

(b)

The topology is a CE stage degenerated by RE , but the load resistance between the collector of Q1 and ac ground consists of RC and the base-emitter junction of Q2 . Modeling the latter by r2 , we reduce the circuit to that shown in Fig. 5.38(b), where the total load resistance seen at the collector of Q1 is equal to RC jjr2 . The voltage gain is thus given by

Solution

Av = , RC jjr2 : 1 gm1 + RE

(5.159)

Exercise

Repeat the above example if a resistor is placed in series with the emitter of Q2 .

To compute the input impedance of the degenerated CE stage, we redraw the small-signal model as in Fig. 5.39(a) and calculate vX =iX . Since v = r iX , the current ﬂowing through RE is equal to iX + gm r iX = 1 + iX , creating a voltage drop of RE 1 + iX . Summing v and vRE and equating the result to vX , we have

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**Bipolar Ampliﬁer Topologies
**

iX vX rπ vπ v RE P RE g vπ m RC iX vX R in

( β +1) R E

211

v out

rπ

(a) (b) Figure 5.39 (a) Input impedance of degenerated CE stage, (b) equivalent circuit.

vX = r iX + RE 1 + iX ;

and hence

(5.160)

Rin = vX iX = r + + 1RE :

(5.161) (5.162)

As predicted by our qualitative reasoning, emitter degeneration increases the input impedance [Fig. 5.39(b)]. Why is Rin not simply equal to r + RE ? This would hold only if r and RE were exactly in series, i.e., if the two carried equal currents, but in the circuit of Fig. 5.39(a), the collector current, gm v , also ﬂows into node P . Does the factor + 1 bear any intuitive meaning? We observe that the ﬂow of both base and collector currents through RE results in a large voltage drop, + 1iX RE , even though the current drawn from vX is merely iX . In other words, the test voltage source, vX , supplies a current of only iX while producing a voltage drop of + 1iX RE across RE —as if iX ﬂows through a resistor equal to + 1RE . The above observation is articulated as follows: any impedance tied between the emitter and ground is multiplied by + 1 when “seen from the base.” The expression “seen from the base” means the impedance measured between the base and ground. We also calculate the output impedance of the stage with the aid of the equivalent shown in Fig. 5.40, where the input voltage is set to zero. Equation (5.153) applies to this circuit as well:

iX rπ vπ v RE P RE g vπ m RC vX

(a) Figure 5.40 Output impedance of degenerated stage.

vin = 0 = v + r + gmv RE ; yielding v = 0 and hence gm v = 0. Thus, all of iX ﬂows through RC , and Rout = vX iX = RC ;

v

(5.163)

(5.164) (5.165)

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revealing that emitter degeneration does not alter the output impedance if the Early effect is neglected.

Example 5.24

A CE stage is biased at a collector current of 1 mA. If the circuit provides a voltage gain of 20 with no emitter degeneration and 10 with degeneration, determine RC , RE , and the I/O impedances. Assume = 100. For Av

Solution

= 20 in the absence of degeneration, we require

gm RC = 20;

which, together with gm

(5.166)

= IC =VT = 26 ,1 , yields

RC = 520 :

Since degeneration lowers the gain by a factor of two,

(5.167)

1 + gm RE = 2;

i.e.,

(5.168)

RE = g1

The input impedance is given by

= 26 :

m

(5.169) (5.170)

Rin = r + + 1RE

= g + + 1RE

m 2r

because

(5.171) (5.172) (5.173) . Finally, (5.174) (5.175)

1 and RE = 1=gm in this example. Thus, Rin = 5200

Rout = RC

= 520 :

Exercise

What bias current would result in a gain of 5 with such emitter and collector resistor values?

Example 5.25

Compute the voltage gain and I/O impedances of the circuit depicted in Fig. 5.41. Assume a very large value for C1 .

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213

VCC RC Vout V in RE

Constant

Q1

C1

Figure 5.41 CE stage example.

If C1 is very large, it acts as a short circuit for the signal frequencies of interest. Also, the constant current source is replaced with an open circuit in the small-signal equivalent circuit. Thus, the stage reduces to that in Fig. 5.35(a) and Eqs. (5.157), (5.162), (5.165) apply.

Solution

Exercise

Repeat the above example if we tie another capacitor from the base to ground.

The degenerated CE stage can be analyzed from a different perspective to provide more insight. Let us place the transistor and the emitter resistor in a black box having still three terminals [Fig. 5.42(a)]. For small-signal operation, we can view the box as a new transistor (or “active” device) and model its behavior by new values of transconductance and impedances. Denoted by Gm to avoid confusion with gm of Q1 , the equivalent transconductance is obtained from Fig. 5.42(b). Since Eq. (5.154) still holds, we have

i out rπ vπ RE g vπ m

i out v in Q1 RE

v in

(a) (b) Figure 5.42 (a) Degenerated bipolar transistor viewed as a black box, (b) small-signal equivalent.

iout = gmv = gm

and hence

, 1 + r 1 + gm RE

vin

(5.176)

;

(5.177)

Gm = ivout

in

(5.178)

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1 + gm R : g

m E

(5.179)

For example, the voltage gain of the stage with a load resistance of RD is given by ,Gm RD . An interesting property of the degenerated CE stage is that its voltage gain becomes relatively independent of the transistor transconductance and hence bias current if gm RE 1. From Eq. (5.157), we note that Av ! ,RC =RE under this condition. As studied in Problem 40, this trend in fact represents the “linearizing” effect of emitter degeneration. As a more general case, we now consider a degenerated CE stage containing a resistance in series with the base [Fig. 5.43(a)]. As seen below, RB only degrades the performance of the circuit, but often proves inevitable. For example, RB may represent the output resistance of a microphone connected to the input of the ampliﬁer.

VCC RC v in RB A RE v out Q1 v in RB rπ

( β +1) R E

A

(a) (b) Figure 5.43 (a) CE stage with base resistance, (b) equivalent circuit.

To analyze the small-signal behavior of this stage, we can adopt one of two approaches: (a) draw the small-signal model of the entire circuit and solve the resulting equations, or (b) recognize that the signal at node A is simply an attenuated version of vin and write

vout = vA vout : vin vin vA

(5.180)

Here, vA =vin denotes the effect of voltage division between RB and the impedance seen at the base of Q1 , and vout =vA represents the voltage gain from the base of Q1 to the output, as already obtained in Eqs. (5.155) and (5.157). We leave the former approach for Problem 44 and continue with the latter here. Let us ﬁrst compute vA =vin with the aid of Eq. (5.162) and the model depicted in Fig. 5.39(b), as illustrated in Fig. 5.43(b). The resulting voltage divider yields

**r + + 1RE vA vin = r + + 1RE + RB :
**

Combining (5.155) and (5.157), we arrive at the overall gain as

(5.181)

vout = r + + 1RE

,gmRC vin r + + 1RE + RB 1 + 1 + g R r m E r + 1 m = r ++ + 1R RER r ,g1 r RCR E+ B + + E RC = r + , 1R + R : + E B

(5.182)

(5.183) (5.184)

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215

To obtain a more intuitive expression, we divide the numerator and the denominator by :

Av 1 ,RC RB : gm + RE + + 1

(5.185)

Compared to (5.157), this result contains only one additional term in the denominator equal to the base resistance divided by + 1. The above results reveal that resistances in series with the emitter and the base have similar effects on the voltage gain, but RB is scaled down by + 1. The signiﬁcance of this observation becomes clear later. For the stage of Fig. 5.43(a), we can deﬁne two different input impedances, one seen at the base of Q1 and another at the left terminal of RB (Fig. 5.44). The former is equal to

VCC RC RB Q1 R in2 R in1 RE v out

Figure 5.44 Input impedances seen at different nodes.

Rin1 = r + + 1RE

and the latter,

(5.186)

Rin2 = RB + r + + 1RE :

(5.187)

In practice, Rin1 proves more relevant and useful. We also note that the output impedance of the circuit remains equal to

Rout = RC

even with RB

(5.188)

6= 0. This is studied in Problem 45.

Example 5.26

A microphone having an output resistance of 1 k generates a peak signal level of 2 mV. Design a CE stage with a bias current of 1 mA that ampliﬁes this signal to 40 mV. Assume RE = 4=gm and = 100. The following quantities are obtained: RB 104 . From Eq. (5.185),

Solution

= 1 k , gm = 26 ,1 , jAv j = 20, and RE =

RC = jAv j g1 + RE + RB1 + m 2:8 k :

(5.189) (5.190)

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Exercise

Repeat the above example if the microphone output resistance is doubled.

Example 5.27

Determine the voltage gain and I/O impedances of the circuit shown in Fig. 5.45(a). Assume a very large value for C1 and neglect the Early effect.

VCC RC v in RB Q1 v out R1 R2 I1

(a) (b)

RC v in RB Q1 R2 v out R1

C1

Figure 5.45 (a) CE stage example, (b) simpliﬁed circuit.

Replacing C1 with a short circuit, I1 with an open circuit, and VCC with ac ground, we arrive at the simpliﬁed model in Fig. 5.45(b), where R1 and RC appear in parallel and R2 acts as an emitter degeneration resistor. Equations (5.185)-(5.188) are therefore written respectively as

Solution

Av = 1 ,RC jjR1RB gm + R2 + + 1 Rin = RB + r + + 1R2 Rout = RC jjR1 :

(5.191)

(5.192) (5.193)

Exercise

What happens if a very large capacitor is tied from the emitter of Q1 to ground?

Effect of Transistor Output Resistance The analysis of the degenerated CE stage has thus far neglected the Early effect. Somewhat beyond the scope of this book, the derivation of the circuit properties in the presence of this effect is outlined in Problem 48 for the interested reader. We nonetheless explore one aspect of the circuit, namely, the output resistance, as it provides the foundation for many other topologies studied later.

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Bipolar Ampliﬁer Topologies

217

Our objective is to determine the output impedance seen looking into the collector of a degenerated transistor [Fig. 5.46(a)]. Recall from Fig. 5.7 that Rout = rO if RE = 0. Also, Rout = 1 if VA = 1 (why?). To include the Early effect, we draw the small-signal equivalent circuit as in Fig. 5.46(b), grounding the input terminal. A common mistake here is to write Rout = rO + RE . Since gm v ﬂows from the output node into P , resistors rO and RE are not in series. We readily note that RE and r appear in parallel, and the current ﬂowing through RE jjr is equal to iX . Thus,

R out V in RE Q1 rπ vπ P RE iX g vπ m iX rO vX

(a)

(b)

Figure 5.46 (a) Output impedance of degenerated stage, (b) equivalent circuit.

v = ,iX RE jjr ;

(5.194)

where the negative sign arises because the positive side of v is at ground. We also recognize that rO carries a current of iX , gm v and hence sustains a voltage of iX , gm v rO . Adding this voltage to that across RE (= ,v ) and equating the result to vX , we obtain

**vX = iX , gm v rO , v = iX + gm iX RE jjr rO + iX RE jjr :
**

It follows that

(5.195) (5.196)

**Rout = 1 + gm RE jjr rO + RE jjr = rO + gm rO + 1RE jjr :
**

Recall from (5.146) that the intrinsic gain of the transistor, gm rO

(5.197) (5.198)

1, and hence

(5.199) (5.200)

Rout rO + gm rO RE jjr rO 1 + gm RE jjr :

Interestingly, emitter degeneration raises the output impedance from rO to the above value, i.e., by a factor of 1 + gm RE jjr . The reader may wonder if the increase in the output resistance is desirable or undesirable. The “boosting” of output resistance as a result of degeneration proves extremely useful in circuit design, conferring ampliﬁers with a higher gain as well as creating more ideal current sources. These concepts are studied in Chapter 9. It is instructive to examine (5.200) for two special cases RE r and RE r . For RE r , we have RE jjr ! r and

Rout rO 1 + gm r rO ;

(5.201) (5.202)

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because 1. Thus, the maximum resistance seen at the collector of a bipolar transistor is equal to rO —if the degeneration impedance becomes much larger than r . For RE r , we have RE jjr ! RE and

Rout 1 + gmRE rO :

(5.203)

Thus, the output resistance is boosted by a factor of 1 + gm RE . In the analysis of circuits, we sometimes draw the transistor output resistance explicitly to emphasize its signiﬁcance (Fig. 5.47). This representation, of course, assumes Q1 itself does not contain another rO .

R out Q1 V in RE rO

Figure 5.47 Stage with explicit depiction of

rO .

Example 5.28

We wish to design a current source having a value of 1 mA and an output resistance of 20 k . The available bipolar transistor exhibits = 100 and VA = 10 V. Determine the minimum required value of emitter degeneration resistance. Since rO = VA =IC = 10 k , degeneration must raise the output resistance by a factor of two. We postulate that the condition RE r holds and write

Solution

1 + gm RE = 2:

That is,

(5.204)

RE = g1

Note that indeed r

= 26 :

m

(5.205) (5.206)

= =gm

RE .

Exercise

What is the output impedance if RE is doubled?

Calculate the output resistance of the circuit shown in Fig. 5.48(a) if C1 is very large. Replacing Vb and C1 with an ac ground and I1 with an open circuit, we arrive at the simpliﬁed

Example 5.29 Solution

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Sec. 5.3

**Bipolar Ampliﬁer Topologies
**

R out R out R out1

219

Q1 Vb

R1 R2 C1

Q1 R2

R1

Q1 R2

I1

(a) (b) (c)

Figure 5.48 (a) CE stage example, (b) simpliﬁed circuit, (c) resistance seen at the collector.

model in Fig. 5.48(b). Since R1 appears in parallel with the resistance seen looking into the collector of Q1 , we ignore R1 for the moment, reducing the circuit to that in Fig. 5.48(c). In analogy with Fig. 5.40, we rewrite Eq. (5.200) as

Rout1 = 1 + gm R2 jjr rO :

Returning to Fig. 5.48(b), we have

(5.207)

Rout = Rout1 jjR1 = f 1 + gm R2 jjr rO g jjR1 :

(5.208) (5.209)

Exercise

What is the output resistance if a very large capacitor is tied between the emitter of ground?

Q1 and

The procedure of progressively simplifying a circuit until it resembles a known topology proves extremely critical in our work. Called “analysis by inspection,” this method obviates the need for complex small-signal models and lengthy calculations. The reader is encouraged to attempt the above example using the small-signal model of the overall circuit to appreciate the efﬁciency and insight provided by our intuitive approach.

Example 5.30

Determine the output resistance of the stage shown in Fig. 5.49(a). Recall from Fig. 5.7 that the impedance seen at the collector is equal to rO if the base and emitter are (ac) grounded. Thus, Q2 can be replaced with rO2 [Fig. 5.49(b)]. From another perspective, Q2 is reduced to rO2 because its base-emitter voltage is ﬁxed by Vb1 , yielding a zero gm2 v2 . Now, rO2 plays the role of emitter degeneration resistance for Q1 . In analogy with Fig. 5.40(a), we rewrite Eq. (5.200) as

Solution

Rout = 1 + gm1rO2 jjr1 rO1 :

(5.210)

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220

R out

Chap. 5

Bipolar Ampliﬁers

R out

Q1 V b2

Q1 r O2

Q2 V b1

(a) (b)

Figure 5.49 (a) CE stage example, (b) simpliﬁed circuit.

Called a “cascode” circuit, this topology is studied and utilized extensively in Chapter 9.

Exercise

Repeat the above example for a “stack” of three transistors.

CE Stage with Biasing Having learned the small-signal properties of the common-emitter ampliﬁer and its variants, we now study a more general case wherein the circuit contains a bias network as well. We begin with simple biasing schemes described in Section 5.2 and progressively add complexity (and more robust performance) to the circuit. Let us begin with an example.

Example 5.31

A student familiar with the CE stage and basic biasing constructs the circuit shown in Fig. 5.50 to amplify the signal produced by a microphone. Unfortunately, Q1 carries no current, failing to amplify. Explain the cause of this problem.

VCC = 2.5 V

100 k Ω

RB X

RC

1 kΩ

Vout Q1

Figure 5.50 Microphone ampliﬁer.

Many microphones exhibit a small low-frequency resistance (e.g., 100 ). If used in this circuit, such a microphone creates a low resistance from the base of Q1 to ground, forming a voltage divider with RB and providing a very low base voltage. For example, a microphone resistance of 100 yields

Solution

**VX = 100 k100 100 2:5 V + 2:5 mV:
**

Thus, the microphone low-frequency resistance disrupts the bias of the ampliﬁer.

(5.211) (5.212)

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Bipolar Ampliﬁer Topologies

221

Exercise

Does the circuit operate better if RB is halved?

How should the circuit of Fig. 5.50 be ﬁxed? Since only the signal generated by the microphone is of interest, a series capacitor can be inserted as depicted in Fig. 5.51 so as to isolate the dc biasing of the ampliﬁer from the microphone. That is, the bias point of Q1 remains independent of the resistance of the microphone because C1 carries no bias current. The value of C1 is chosen so that it provides a relatively low impedance (almost a short circuit) for the frequencies of interest. We say C1 is a “coupling” capacitor and the input of this stage is “ac-coupled” or “capacitively-coupled.” Many circuits employ capacitors to isolate the bias conditions from “undesirable” effects. More examples clarify this point later.

VCC = 2.5 V

100 k Ω

RB X

RC

1 kΩ

Vout Q1

C1

Figure 5.51 Capacitive coupling at the input of microphone ampliﬁer.

The foregoing observation suggests that the methodology illustrated in Fig. 5.9 must include an additional rule: replace all capacitors with an open circuit for dc analysis and a short circuit for small-signal analysis. Let us begin with the stage depicted in Fig. 5.52(a). For bias calculations, the signal source is set to zero and C1 is opened, leading to Fig. 5.52(b). From Section 5.2.1, we have

VCC RB X C1

(a)

VCC RB RC X Y Q1 v in X Q1 RB RC

v out

RC Y Q1 Vout

(b)

(c)

**Q1 RB R in2 R in1
**

(d)

RC RB

Q1

RC R out

(e)

Figure 5.52 (a) Capacitive coupling at the input of a CE stage, (b) simpliﬁed stage for bias calculation, (c) simpliﬁed stage for small-signal calculation, (d) simpliﬁed circuit for input impedance calculation, (e) simpliﬁed circuit for output impedance calculation.

, IC = VCCR VBE ; B

(5.213)

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**, VY = VCC , RC VCCR VBE :
**

B

(5.214)

To avoid saturation, VY VBE . With the bias current known, the small-signal parameters gm , r , and rO can be calculated. We now turn our attention to small-signal analysis, considering the simpliﬁed circuit of Fig. 5.52(c). Here, C1 is replaced with a short and VCC with ac ground, but Q1 is maintained as a symbol. We attempt to solve the circuit by inspection: if unsuccessful, we will resort to using a small-signal model for Q1 and writing KVLs and KCLs. The circuit of Fig. 5.52(c) resembles the CE core illustrated in Fig. 5.29, except for RB . Interestingly, RB has no effect on the voltage at node X so long as vin remains an ideal voltage source; i.e., vX = vin regardless of the value of RB . Since the voltage gain from the base to the collector is given by vout =vX = ,gm RC , we have

vout = ,g R : m C vin

If VA

(5.215)

vout = ,g R jjr : (5.216) m C O vin However, the input impedance is affected by RB [Fig. 5.52(d)]. Recall from Fig. 5.7 that the impedance seen looking into the base, Rin1 , is equal to r if the emitter is grounded. Here, RB simply appears in parallel with Rin1 , yielding Rin2 = r jjRB :

(5.217)

1, then

Thus, the bias resistor lowers the input impedance. Nevertheless, as shown in Problem 51, this effect is usually negligible. To determine the output impedance, we set the input source to zero [Fig. 5.52(e)]. Comparing this circuit with that in Fig. 5.32(b), we recognize that Rout remains unchanged:

Rout = RC jjrO :

(5.218)

because both terminals of RB are shorted to ground. In summary, the bias resistor, RB , negligibly impacts the performance of the stage shown in Fig. 5.52(a).

Example 5.32

Having learned about ac coupling, the student in Example 5.31 modiﬁes the design to that shown in Fig. 5.53 and attempts to drive a speaker. Unfortunately, the circuit still fails. Explain why.

VCC = 2.5 V

100 k Ω

RB X

RC

1 kΩ

C1

Q1

Figure 5.53 Ampliﬁer with direct connection of speaker.

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Sec. 5.3

Bipolar Ampliﬁer Topologies

223

Solution

Typical speakers incorporate a solenoid (inductor) to actuate a membrane. The solenoid exhibits a very low dc resistance, e.g., less than 1 . Thus, the speaker in Fig. 5.53 shorts the collector to ground, driving Q1 into deep saturation.

Exercise

Does the circuit operate better if the speaker is tied between the output node and VCC ?

Example 5.33

The student applies ac coupling to the output as well [Fig. 5.54(a)] and measures the quiescent points to ensure proper biasing. The collector bias voltage is 1.5 V, indicating that Q1 operates in the active region. However, the student still observes no gain in the circuit. (a) If IS = 5 10,17

VCC = 2.5 V

100 k Ω 1 kΩ

RB X

RC

v out

100 k Ω

C1

(a)

Q1

C2

Q1 RB

RC

1 k Ω R sp

8Ω

v in

(b)

Figure 5.54 (a) Ampliﬁer with capacitive coupling at the input and output, (b) simpliﬁed small-signal model.

A and VA

= 1, compute the

of the transistor. (b) Explain why the circuit provides no gain.

Solution

(a) A collector voltage of 1.5 V translates to a voltage drop of 1 V across collector current of 1 mA. Thus,

RC

and hence a

VBE = VT ln IC IS = 796 mV:

It follows that

(5.219) (5.220)

, IB = VCCR VBE B = 17 A;

(5.221) (5.222)

and = IC =IB = 58:8. (b) Speakers typically exhibit a low impedance in the audio frequency range, e.g., 8 . Drawing the ac equivalent as in Fig. 5.54(b), we note that the total resistance seen at the collector node is equal to 1 k jj8 , yielding a gain of

jAv j = gmRC jjRS = 0:31

(5.223)

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Exercise

Repeat the above example for RC

= 500

.

The design in Fig. 5.54(a) exempliﬁes an improper interface between an ampliﬁer and a load: the output impedance is so much higher than the load impedance that the connection of the load to the ampliﬁer drops the gain drastically. How can we remedy the problem of loading here? Since the voltage gain is proportional to gm , we can bias Q1 at a much higher current to raise the gain. This is studied in Problem 53. Alternatively, we can interpose a “buffer” stage between the CE ampliﬁer and the speaker (Section 5.3.3). Let us now consider the biasing scheme shown in Fig. 5.15 and repeated in Fig. 5.55(a). To determine the bias conditions, we set the signal source to zero and open the capacitor(s). Equations (5.38)-(5.41) can then be used. For small-signal analysis, the simpliﬁed circuit in Fig. 5.55(b) reveals a resemblance to that in Fig. 5.52(b), except that both R1 and R2 appear in parallel with the input. Thus, the voltage gain is still equal to ,gm RC jjrO and the input impedance is given by

VCC R1 RC Q1 R2 v in Q1 R1 R2 RC v out

v in

C1

(a) (b) Figure 5.55 (a) Biased stage with capacitive coupling, (b) simpliﬁed circuit.

Rin = r jjR1 jjR2 :

(5.224)

The output resistance is equal to RC jjrO . We next study the more robust biasing scheme of Fig. 5.19, repeated in Fig. 5.56(a) along with an input coupling capacitor. The bias point is determined by opening C1 and following Eqs. (5.52) and (5.53). With the collector current known, the small-signal parameters of Q1 can be computed. We also construct the simpliﬁed ac circuit shown in Fig. 5.56(b), noting that the voltage gain is not affected by R1 and R2 and remains equal to

Av = 1,RC ; gm + RE

(5.225)

where Early effect is neglected. On the other hand, the input impedance is lowered to:

Rin = r + + 1RE jjR1 jjR2 ; whereas the output impedance remains equal to RC if VA = 1.

(5.226)

As explained in Section 5.2.3, the use of emitter degeneration can effectively stabilize the bias point despite variations in and IS . However, as evident from (5.225), degeneration also lowers

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225 (1)

Sec. 5.3

**Bipolar Ampliﬁer Topologies
**

VCC R1 RC Q1 R2

(a)

225

v out Q1 v in R1 R2 RE RC

v in

C1

RE

(b)

Figure 5.56 (a) Degenerated stage with capacitive coupling, (b) simpliﬁed circuit.

the gain. Is it possible to apply degeneration to biasing but not to the signal? Illustrated in Fig. 5.57 is such a topology, where C2 is large enough to act as a short circuit for signal frequencies of interest. We can therefore write

VCC R1 RC Q1 R2 RE C2

v in

C1

Figure 5.57 Use of capacitor to eliminate degeneration.

Av = ,gm RC

and

(5.227)

**Rin = r jjR1 jjR2 Rout = RC :
**

Example 5.34

(5.228) (5.229)

Design the stage of Fig. 5.57 to satisfy the following conditions: IC = 1 mA, voltage drop across RE = 400 mV, voltage gain = 20 in the audio frequency range (20 Hz to 20 kHz), input impedance 2 k . Assume = 100, IS = 5 10,16, and VCC = 2:5 V. With IC = 1 mA IE , the value of RE is equal to 400 . For the voltage gain to remain unaffected by degeneration, the maximum impedance of C1 must be much smaller than 1=gm = 26 .8 Occurring at 20 Hz, the maximum impedance must remain below roughly 0:1 1=gm = 2:6 :

Solution

1 1 1 C2 ! 10 gm for ! = 2 20 Hz:

8 A common mistake here is to make the impedance of

(5.230)

C1 much less than RE .

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Thus,

C2 6120 F:

(This value is unrealistically large, requiring modiﬁcation of the design.) We also have

(5.231)

jAv j = gm RC = 20;

obtaining

(5.232)

RC = 512 :

(5.233)

Since the voltage across RE is equal to 400 mV and VBE = VT lnIC =IS = 736 mV, we have VX = 1:14 V. Also, with a base current of 10 A, the current ﬂowing through R1 and R2 must exceed 100 A to lower sensitivity to :

VCC R1 + R2

and hence

10IB

(5.234)

R1 + R2 25 k :

Under this condition,

(5.235)

VX R R2 R VCC = 1:14 V; 1+ 2

yielding

(5.236)

R2 = 11:4 k R1 = 13:6 k :

We must now check to verify that this choice of R1 and R2 satisﬁes the condition Rin That is,

(5.237) (5.238)

2k

.

Rin = r jjR1 jjR2 = 1:85 k :

(5.239) (5.240)

Unfortunately, R1 and R2 lower the input impedance excessively. To remedy the problem, we can allow a smaller current through R1 and R2 than 10IB , at the cost of creating more sensitivity to . For example, if this current is set to 5IB = 50 A and we still neglect IB in the calculation of VX ,

VCC R1 + R2

and

5IB

(5.241)

R1 + R2 50 k :

(5.242)

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227

Consequently,

R2 = 22:4 k R1 = 27:2 k ;

giving

(5.243) (5.244)

Rin = 2:14 k :

(5.245)

Exercise

Redesign the above stage for a gain of 10 and compare the results.

We conclude our study of the CE stage with a brief look at the more general case depicted in Fig. 5.58(a), where the input signal source exhibits a ﬁnite resistance and the output is tied to a load RL . The biasing remains identical to that of Fig. 5.56(a), but RS and RL lower the voltage gain vout =vin . The simpliﬁed ac circuit of Fig. 5.58(b) reveals Vin is attenuated by the voltage division between RS and the impedance seen at node X , R1 jjR2 jj r + + 1RE , i.e.,

VCC R1 RS v in C1 Q1 R2

(a)

RC

C2 RL

v out v in

RS R1 R2

v out X Q1 RE RC RL

RE

(b)

RS v in R1 R2

v out X Q1 RE RC RL

(b) Figure 5.58 (a) General CE stage, (b) simpliﬁed circuit, (c) Thevenin model of input network.

**vX = R1 jjR2 jj r + + 1RE : vin R1 jjR2 jj r + + 1RE + RS
**

The voltage gain from vin to the output is given by

(5.246)

vout = vX vout vin vin vX R1 R r + 1 E = , R jjRjjjj 2 jj + + + 1R R+ R RC jjRL : 1 2 r E S 1 + RE gm

(5.247) (5.248)

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As expected, lower values of R1 and R2 reduce the gain. The above computation views the input network as a voltage divider. Alternatively, we can utilize a Thevenin equivalent to include the effect of RS , R1 , and R2 on the voltage gain. Illustrated in Fig. 5.58(c), the idea is to replace vin , RS and R1 jjR2 with vThev and RThev :

**R1 vThev = R jjRjjR2R vin 1 2+ S RThev = RS jjR1 jjR2 :
**

The resulting circuit resembles that in Fig. 5.43(a) and follows Eq. (5.185):

(5.249) (5.250)

R1 Av = , 1 RC jjRLRThev R jjRjjR2R ; 1 2+ S gm + RE + + 1

(5.251)

where the second fraction on the right accounts for the voltage attenuation given by Eq. (5.249). The reader is encouraged to prove that (5.248) and (5.251) are identical. The two approaches described above exemplify analysis techniques used to solve circuits and gain insight. Neither requires drawing the small-signal model of the transistor because the reduced circuits can be “mapped” into known topologies. Figure 5.59 summarizes the concepts studied in this section.

Headroom

RC

Gain

RC rO R out A v = − g m (RC r O ) A v , R in

A v = − g mR C R out

R in

R1 C1 R2

RC Q1 R1 R2 RC

RE

RE

C2

Figure 5.59 Summary of concepts studied thus far.

5.3.2 Common-Base Topology Following our extensive study of the CE stage, we now turn our attention to the “common-base“ (CB) topology. Nearly all of the concepts described for the CE conﬁguration apply here as well. We therefore follow the same train of thought, but at a slightly faster pace. Given the ampliﬁcation capabilities of the CE stage, the reader may wonder why we study other ampliﬁer topologies. As we will see, other conﬁgurations provide different circuit properties that are preferable to those of the CE stage in some applications. The reader is encouraged to review Examples 5.2-5.4, their resulting rules illustrated in Fig. 5.7, and the possible topologies in Fig. 5.28 before proceeding further.

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Figure 5.60 shows the CB stage. The input is applied to the emitter and the output is sensed at the collector. Biased at a proper voltage, the base acts as ac ground and hence as a node “common” to the input and output ports. As with the CE stage, we ﬁrst study the core and subsequently add the biasing elements.

VCC RC Vout Q1 Vb v in

Input Applied to Emitter Output Sensed at Collector

Figure 5.60 Common-base stage.

Analysis of CB Core How does the CB stage of Fig. 5.61(a) respond to an input signal?9 If Vin goes up by a small amount V , the base-emitter voltage of Q1 decreases by the same amount because the base voltage is ﬁxed. Consequently, the collector current falls by gm V , allowing Vout to rise by gm V RC . We therefore surmise that the small-signal voltage gain is equal to

VCC RC Vout Q1 Vb v in V in

(a)

g ∆V R C m

v out rπ vπ g vπ m RC

∆V

(b)

Figure 5.61 (a) Response of CB stage to small input change, (b) small-signal model.

Av = gm RC :

(5.252)

Interestingly, this expression is identical to the gain of the CE topology. Unlike the CE stage, however, this circuit exhibits a positive gain because an increase in Vin leads to an increase in Vout . Let us conﬁrm the above results with the aid of the small-signal equivalent depicted in Fig. 5.61(b), where the Early effect is neglected. Beginning with the output node, we equate the current ﬂowing through RC to gm v :

, vout = gm v ; R

C

(5.253)

9 Note that the topologies of Figs. 5.60-5.61(a) are identical even though

Q1 is drawn differently.

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obtaining v = ,vout =gm RC . Considering the input node next, we recognize that v It follows that

= ,vin .

(5.254)

vout = g R : vin m C

As with the CE stage, the CB topology suffers from trade-offs between the gain, the voltage headroom, and the I/O impedances. We ﬁrst examine the circuit’s headroom limitations. How should the base voltage, Vb , in Fig. 5.61(a) be chosen? Recall that the operation in the active region requires VBE 0 and VBC 0 (for npn devices). Thus, Vb must remain higher than the input by about 800 mV, and the output must remain higher than or equal to Vb . For example, if the dc level of the input is zero (Fig. 5.62), then the output must not fall below approximately 800 mV, i.e., the voltage drop across RC cannot exceed VCC , VBE . Similar to the CE stage limitation, this condition translates to

VCC RC VCC − V BE

~0V ~800 mV 800 mV 0

Vb

t

V in

Figure 5.62 Voltage headroom in CB stage.

I Av = VC RC T VCC , VBE : = VT

Example 5.35

(5.255) (5.256)

The voltage produced by an electronic thermometer is equal to 600 mV at room temperature. Design a CB stage to sense the thermometer voltage and amplify the change with maximum gain. Assume VCC = 1:8 V, IC = 0:2 mA, IS = 5 10,17 A, and = 100.

Solution

Illustrated in Fig. 5.63(a), the circuit must operate properly with an input level of 600 mV. Thus, Vb = VBE + 600 mV = VT lnIC =IS + 600 mV = 1:354 V. To avoid saturation, the collector voltage must not fall below the base voltage, thereby allowing a maximum voltage drop across RC equal to 1:8 V , 1:354 V = 0:446 V. We can then write

Av = gmRC = IC RC VT = 17:2:

(5.257) (5.258) (5.259)

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**Bipolar Ampliﬁer Topologies
**

VCC RC Vout Q1 Vb Q1 RC Vout IB VCC R1 I1 R2

231

V in

600 mV

V in

600 mV

Thermometer (a) (b)

Figure 5.63 (a) CB stage sensing an input, (b) bias network for base.

The reader is encouraged to repeat the problem with IC = 0:4 mA to verify that the maximum gain remains relatively independent of the bias current.10 We must now generate Vb . A simple approach is to employ a resistive divider as depicted in Fig. 5.63(b). To lower sensitivity to , we choose I1 10IB 20 A VCC =R1 + R2 . Thus, R1 + R2 = 90 k . Also,

Vb R R2 R VCC 1+ 2

and hence

(5.260)

R2 = 67:7 k R1 = 22:3 k :

(5.261) (5.262)

Exercise

Repeat the above example if the thermometer voltage is 300 mV.

Let us now compute the I/O impedances of the CB topology so as to understand its capabilities in interfacing with preceding and following stages. The rules illustrated in Fig. 5.7 prove extremely useful here, obviating the need for small-signal equivalent circuits. Shown in Fig. 5.64(a), the simpliﬁed ac circuit reveals that Rin is simply the impedance seen looking into the emitter with the base at ac ground. From the rules in Fig. 5.7, we have

Rin = g1

m

(5.263) for

if VA = 1. The input impedance of the CB stage is therefore relatively low, e.g., 26 IC = 1 mA (in sharp contrast to the corresponding value for a CE stage, =gm).

10 This example serves only as an illustration of the CB stage. A CE stage may prove more suited to sensing a thermometer voltage.

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VCC RC

Chap. 5

VCC RC

Bipolar Ampliﬁers

Q1

ac

IX VX

Q1

Vb

R in

(a)

∆V

(b)

Figure 5.64 (a) Input impedance of CB stage, (b) response to a small change in input.

The input impedance of the CB stage can also be determined intuitively [Fig. 5.64(b)]. Suppose a voltage source VX tied to the emitter of Q1 changes by a small amount V . The baseemitter voltage therefore changes by the same amount, leading to a change in the collector current equal to gm V . Since the collector current ﬂows through the input source, the current supplied by VX also changes by gm V . Consequently, Rin = VX =IX = 1=gm. Does an ampliﬁer with a low input impedance ﬁnd any practical use? Yes, indeed. For example, many stand-alone high-frequency ampliﬁers are designed with an input resistance of 50 to provide “impedance matching” between modules in a cascade and the transmission lines (traces on a printed-circuit board) connecting the modules (Fig. 5.65).11

50− Ω Transmission Line 50− Ω Transmission Line

50 Ω

50 Ω

Figure 5.65 System using transmission lines.

The output impedance of the CB stage is computed with the aid of Fig. 5.66, where the input voltage source is set to zero. We note that Rout = Rout1 jjRC , where Rout1 is the impedance seen at the collector with the emitter grounded. From the rules of Fig. 5.7, we have Rout1 = rO and hence

Q1 rO

ac

RC R out1 R out

Figure 5.66 Output impedance of CB stage.

Rout = rO jjRC

(5.264)

11 If the input impedance of each stage is not matched to the characteristic impedance of the preceding transmission line, then “reﬂections” occur, corrupting the signal or at least creating dependence on the length of the lines.

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233

or

Rout = RC if VA = 1:

Example 5.36

(5.265)

A common-base ampliﬁer is designed for an input impedance of Rin and an output impedance of Rout . Neglecting the Early effect, determine the voltage gain of the circuit. Since Rin

Solution

= 1=gm and Rout = RC , we have

Av = Rout : R

in

(5.266)

Exercise

Compare this value with that obtained for the CE stage.

From Eqs. (5.256) and (5.266), we conclude that the CB stage exhibits a set of trade-offs similar to those depicted in Fig. 5.33 for the CE ampliﬁer. It is instructive to study the behavior of the CB topology in the presence of a ﬁnite source resistance. Shown in Fig. 5.67, such a circuit suffers from signal attenuation from the input to node X , thereby providing a smaller voltage gain. More speciﬁcally, since the impedance seen looking into the emitter of Q1 (with the base grounded) is equal to 1=gm (for VA = 1), we have

VCC RC v out RS v in Q1 X v in RS X

1 gm

1 gm

Figure 5.67 CB stage with source resistance.

vX =

1 = 1 + g R vin : m S

We also recall from Eq. (5.254) that the gain from the emitter to the output is given by

RS + g1

gm

1

vin

(5.267)

m

(5.268)

vout = g R : m C vX

(5.269)

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It follows that

vout = gm RC vin 1 + gm RS = 1 RC ; gm + RS

(5.270) (5.271)

a result identical to that of the CE stage (except for a negative sign) if RS is viewed as an emitter degeneration resistor.

Example 5.37

A common-base stage is designed to amplify an RF signal received by a 50- antenna. Determine the required bias current if the input impedance of the ampliﬁer must “match” the impedance of the antenna. What is the voltage gain if the CB stage also drives a 50- load? Assume VA = 1. Figure 5.68 depicts the ampliﬁer12 and the equivalent circuit with the antenna modeled by a

VCC RC v out

Antenna Antenna

Solution

VCC RC v out RS v in Q1 VB

Q1

VB

Figure 5.68 (a) CB stage sensing a signal received by an antenna, (b) equivalent circuit.

voltage source, vin , and a resistance, RS = 50 . For impedance matching, it is necessary that the input impedance of the CB core, 1=gm , be equal to RS , and hence

IC = gm VT = 0:52 mA:

If RC itself is replaced by a 50- load, then Eq. (5.271) reveals that

(5.272) (5.273)

Av = 1 RC gm + RS = 1: 2

The circuit is therefore not suited to driving a 50- load directly.

(5.274)

(5.275)

12 The dots denote the need for biasing circuitry, as described later in this section.

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235

Exercise

What is the voltage gain if a 50- resistor is also tied from the emitter of Q1 to ground?

Another interesting point of contrast between the CE and CB stages relates to their current gains. The CB stage displays a current gain of unity because the current ﬂowing into the emitter simply emerges from the collector (if the base current is neglected). On the other hand, as mentioned in Section 5.3.1, AI = for the CE stage. In fact, in the above example, iin = vin =RS + 1=gm, which upon ﬂowing through RC , yields vout = RC vin =RS + 1=gm. It is thus not surprising that the voltage gain does not exceed 0.5 if RC RS . As with the CE stage, we may desire to analyze the CB topology in the general case: with emitter degeneration, VA 1, and a resistance in series with the base [Fig. 5.69(a)]. Outlined in Problem 64, this analysis is somewhat beyond the scope of this book. Nevertheless, it is inVCC RC v out RE v in

(a) (b)

rO Q1 RB

VB

RE

rO Q1 R out1

RC R out2

Figure 5.69 (a) General CB stage, (b) output impedance seen at different nodes.

structive to consider a special case where RB = 0 but VA 1, and we wish to compute the output impedance. As illustrated in Fig. 5.69(b), Rout is equal to RC in parallel with the impedance seen looking into the collector, Rout1 . But Rout1 is identical to the output resistance of an emitter-degenerated common emitter stage, i.e., Fig. 5.46, and hence given by Eq. (5.197):

**Rout1 = 1 + gmRE jjr rO + RE jjr :
**

It follows that

(5.276)

Rout = RC jj f 1 + gmRE jjr rO + RE jjr g :

(5.277)

The reader may have recognized that the output impedance of the CB stage is equal to that of the CE stage. Is this true in general? Recall that the output impedance is determined by setting the input source to zero. In other words, when calculating Rout , we have no knowledge of the input terminal of the circuit, as illustrated in Fig. 5.70 for CE and CB stages. It is therefore no coincidence that the output impedances are identical if the same assumptions are made for both circuits (e.g., identical values of VA and emitter degeneration).

Example 5.38

Old wisdom says “the output impedance of the CB stage is substantially higher than that of the CE stage.” This claim is justiﬁed by the tests illustrated in Fig. 5.71. If a constant current is , injected into the base while the collector voltage is varied, IC exhibits a slope equal to rO 1 [Fig. 5.71(a)]. On the other hand, if a constant current is drawn from the emitter, IC displays much less dependence on the collector voltage. Explain why these tests do not represent practical situations.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. with current sources IB and IE replaced with open circuits because they are constant.71(c). (b) resistance seen at collector with an ideal current source in emitter.70 (a) CE stage and (b) CB stage simpliﬁed for output impedance calculation.71(d) resembles an emitter-degenerated stage (Fig.71(c) and (d).71 (a) Resistance seens at collector with emitter grounded. exhibiting an output resistance of Rout = 1 + gmRE jjr rO + RE jjr = 1 + gmr rO + r rO + r . 2006] June 30. (5.280) which is. (d) small-signal model of (b).46) with an inﬁnite emitter resistance. IC VCC IB Q1 V1 V1 (a) Open (b) IC IC VB Q1 IE V1 IC V1 rπ vπ g vπ m rO R out rπ vπ g vπ m rO R out Open (c) (d) Figure 5. making the above comparison irrelevant. yielding gm v = 0 and hence Rout = rO . each stage may be driven by a voltage source having a ﬁnite impedance. the current through r is zero. 5. 5.278) (5. the two circuits reduce to those depicted in Figs.cls v. From a small-signal point of view. On the other hand. Fig. however. much greater than rO .279) (5. (c) small-signal model of (a). In practice. In Fig. 2007 at 13:42 236 (1) 236 VCC RC Q1 v in RE v out VCC RC Q1 RE R out v in (a) Chap. 5 VCC RC Vb Q1 RE v out Bipolar Ampliﬁers VCC RC Q1 R out RE (b) Figure 5. Exercise Repeat the above example if a resistor of value R1 is inserted in series with the emitter. . Solution The principal issue in these tests relates to the use of current sources to drive each stage. of course. 5. 5.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Since this case does not reduce to any of the conﬁgurations studied earlier. Multiplying this current by RB + r .vout = RC . As usual. .3 Bipolar Ampliﬁer Topologies 237 Another special case of the topology shown in Fig.vout =gmr RC = . 5.282) v + g v = vP . 2006] June 30. we obtain the voltage at node P : RB rπ vπ P v in RE g vπ m RC v out Figure 5.281) (5. we write gm v = . 2007 at 13:42 237 (1) Sec. The current ﬂowing through r (and RB ) is then equal to v =r = .vout RB + r RC vout R + r : = R B C We also write a KCL at P : (5.72 to study its behavior.vout =gm RC .cls v.283) that is. 5. we employ the smallsignal model shown in Fig.72 CB stage with base resistance. . 5. vin . r m RE (5.69(a) occurs if VA = 1 but RB 0. vP = .vout =RC and hence v = .

still assuming VA = 1. except for a negative sign.185) for the CE stage. Figure 5. the two stages exhibit equal gains. RB may arise from the biasing network.286) vout RC RB + 1 : vin RE + + 1 gm As expected. Let us now determine the input impedance of the CB stage in the presence of a resistance in series with the base. As explained later in this section.v vout R + r . we have (5. revealing that. From the small-signal equivalent circuit shown in .284) RC vout = vin + 1RE + RB + r : Dividing the numerator and denominator by (5. Furthermore.1 It follows that out r + gm gm RC = . this expression is identical to that in (5.285) + 1. v RC B in : RE (5. Note that RB degrades the gain and is not added to the circuit deliberately. the gain is positive.73 illustrates the results.

74. r v = . we recognize that r and RB form a voltage divider. Fig. r +R vX : B Moreover.cls v. (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thereby producing13 RB rπ vπ g vπ m RC v out vX iX Figure 5.i : X r m Thus. 5 Bipolar Ampliﬁers VCC RC RB Q1 v in RE v in v out RB VCC RC v out Q1 RE Figure 5. 2007 at 13:42 238 (1) 238 Chap. 2006] June 30.288) .287) v + g v = . 5.74 Input impedance of CB stage with base resistance.73 Comparison of CE and CB stages with base resistance. KCL at the input node gives (5.

r vX =r + RB . Interestingly. the current through r + R is equal to v =r + R .1 . the base resistance is divided by + 1 when “seen” from the emitter.iX vX = r + RB iX +1 g1 + RB1 : + m (5.r r + gm r + RB vX = . an expected result from the rules illustrated in Fig. yielding a voltage of B X B across r .290) (5. 5.291) Note that Rin = 1=gm if RB = 0. where the emitter resistance is multiplied by + 1 13 Alternatively.7. This is in contrast to the case of emitter degeneration.289) and (5. .

we have (5. (b) simpliﬁed circuit. RB VA = Q1 RB 1 + g m β +1 r π + (β +1) R E VA = Q1 RE Figure 5.75 Impedance seen at the emitter or base of a transistor. 5. we must ﬁrst obtain the equivalent resistance Req . 2007 at 13:42 239 (1) Sec.cls v. Figure 5.39 Determine the impedance seen at the emitter of identical and VA = 1. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.76 (a) Example of CB stage.3 Bipolar Ampliﬁer Topologies 239 when seen from the base. but with its base tied to a ﬁnite series resistance equal to that seen at the emitter of Q1 .76(a) if the two transistors are VCC RB 1 + g m1 β +1 RC v out Q2 RX (b) v out (a) Figure 5. 5.292) RX = g 1 + Req1 + m2 1 = g1 + + 1 g1 + m2 m1 . VCC RB Q1 Q2 R eq RX RC Q2 in Fig. The circuit employs Q2 as a common-base device. Example 5.75 summarizes the two cases. (5. which from Eq. 5.76(b). these results remain independent of RC if VA = 1.291) is simply equal to Solution Req = g 1 + RB1 : + m1 Reducing the circuit to that shown in Fig. Thus. Interestingly.

294) Exercise What happens if a resistor of value R1 is placed in series with the collector of Q1 ? CB Stage with Biasing Having learned the small-signal properties of the CB core. . An example proves instructive at this point. RB : +1 (5.293) (5. we now extend our analysis to the circuit including biasing.

yielding vout = 0.77 CB stage lacking bias current.77. Explain why “haste makes waste. Solution As with Example 5. the student has shorted the signal to ac ground. drawing the design as shown in Fig. 5. the emitter voltage is equal to zero regardless of the value of vin . The situation is similar to the CE counterpart in Example 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the student quickly connects the emitter to ground so that VBE = Vb and a reasonable collector current can be established (Fig. Unfortunately.5. That is. forcing a zero bias current and hence a zero transconductance. . 2007 at 13:42 240 (1) 240 Chap. Solution Exercise In what region does Q1 operate if Vb = VCC ? Somewhat embarrassed.6. Explain why this circuit does not work.31 decides to incorporate ac coupling at the input of a CB stage to ensure the bias is not affected by the signal source.41 Figure 5. 5. 5 Bipolar Ampliﬁers Example 5.78 CB stage with emitter shorted to ground.” VCC RC v out Q1 Vb v in C1 Example 5. the design provides no dc path for the emitter current of Q1 . 2006] June 30.78).40 The student in Example 5. VCC RC Vout Q1 Vb V in C1 Figure 5. where no base current can be supported.cls v.

where RE provides a path for the bias current at the cost of lowering the input impedance. We recognize that Rin now consists of two parallel components: (1) 1=gm. 2007 at 13:42 241 (1) Sec. (b) inclusion of source resistance.79(a) is an example. we can write vX Rin vin = Rin + RS 1 g jjRE m (5. To resolve this apparent contradiction. 5.79(b). seen looking “up” into the emitter (with the base at ac ground) and (2) RE .295) As with the input biasing network in the CE stage (Fig. thereby requiring some bias element.” Thus.298) = gm RC .3 Bipolar Ampliﬁer Topologies 241 Exercise Does the circuit operate better if Vb is raised? The above examples imply that the emitter can remain neither open nor shorted to ground. 5. VCC RC v out 1 gm VCC RC v out Q1 Vb X v in R S C1 R in RE Vb Q1 v in C1 RE RE (a) (b) Figure 5. Shown in Fig.cls v.58).79 (a) CB stage with biasing. seen looking “down. we must distinguish between the two components 1=gm and RE .67. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. vout = 1 vin 1 + 1 + gm RE RS gmRC : (5.299) As usual. we consider the reduction of the input impedance due to RE undesirable.296) = 1 m g jjRE + RS (5. 2006] June 30. Rin = g1 jjRE : m (5. Following the analysis illustrated in Fig. on the other hand. such a circuit attenuates the signal. Depicted in Fig.297) 1 = 1 + 1 + g R R : m E S Since vout =vX (5. 5. lowering the overall voltage gain. the reduction in Rin manifests itself if the source voltage exhibits a ﬁnite output resistance. we have preferred solution by inspection over drawing the small-signal equivalent. noting that the latter shunts the input . we view the low input impedance of the CB stage a useful property. The reader may see a contradiction in our thoughts: on the one hand. 5.

5 Bipolar Ampliﬁers VCC RC v out i in R S C1 Q1 i2 i1 RE Vb v in Figure 5. 5. 14 In the extreme case.41) and i2 = 0. source current to ground.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. then i2 also falls.80. with only i2 reaching RC and contributing to the output signal.81 (a) CB stage with base bias network.81(a). (c) effect of bypass capacitor. the dc voltage drop across RE muts be much greater than VT .301) That is. For RE to affect the input impedance negligibly. Shown in Fig.80 Small-signal input current components in a CB stage. we must have RE and hence gm VT : 1 (5. recall from Eq.300) IC RE (5. Substituting a Thevenin equivalent for R1 and R2 as depicted in Fig. If RE decreases while 1=gm remains constant. iin splits two ways.14 Thus.81(b). By contrast. if 1=gm decreases while RE remains constant. 5. (5. then i2 rises. 2007 at 13:42 242 (1) 242 Chap. Vb R R2 R VCC : 1+ 2 (5. As shown in Fig.286) that a resistance in series with the base reduces the voltage gain of the CB stage. 2006] June 30. yielding VCC RC Q1 C1 R E (a) VCC RC R Thev Q1 V Thev RE (b) VCC RC Q1 R2 RE (c) R1 IB R2 I1 Vb R1 CB Figure 5. RE = 0 (Example 5. thus “wasting” the signal.cls v. reduction of Rin due to RE is undesirable. (b) use of Thevenin equivalent. 5. generated? We can employ a resistive divider similar to that used in the CE stage. . such a topology must ensure I1 IB to minimize sensitivity to .302) However. How is the base voltage. Vb .

and VCC = 2:5 V. Solution We begin by selecting RE . For this reason.16 A.82) for a voltage gain of 10 and an input impedance of 50 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we write (5. to minimize the undesirable effect of Rin g1 = 50 m and hence (5. VCC RC V out V in C1 Q1 R2 RE I C RE R1 Vb CB Figure 5.81(c)]. 5. a “bypass capacitor” is often tied from the base to ground. 5. RE 1=gm.306) We now determine the base bias resistors. Thus.308) = 52 A.310) Vb R R2 R VCC : 1+ 2 VCC R + R = 52 A: 1 2 .82 Example of CB stage with biasing. acting as a short circuit at frequencies of interest [Fig. RE = 500 .305) RC = 500 : (5.304) Av = gm RC . Assume IS = 5 10. Example 5. Since the voltage drop across RE is equal to 500 0:52 mA = 260 mV and VBE = VT lnIC =IS = 899 mV.309) (5.g.cls v. 5. e.42 Design a CB stage (Fig. 2006] June 30.303) IC = 0:52 mA: If the base is bypassed to ground (5. VA = 1. we have Vb = IE RE + VBE = 1:16 V: Selecting the current through R1 and R2 to be 10IB (5. = 100.307) (5.3 Bipolar Ampliﬁer Topologies 243 we recognize that a resistance of RThev = R1 jjR2 now appears in series with the base. yielding (5. 2007 at 13:42 243 (1) Sec..

3.314) = 71 pF: Since the impedance of CB appears in series with the base and plays a role similar to the term RB = + 1 in Eq. For the sake of brevity. 5. (5. we may choose jC1 ! j. (5. Appearing in series with the emitter of Q1 . Consequently. for ! = 2 900 MHz: g C1 = 20! m (5.67 and Eq.286). must remain much less than 1=gm = 50 .313) (5.83. we require that 1 1 1 1 + 1 CB ! = 20 gm and hence (5. 2006] June 30.316) R1 jjR2 rather Exercise Design the above circuit for an input impedance of 100 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The reader is encouraged to review Examples 5.3 Emitter Follower Another important circuit topology is the emitter follower (also called the “common-collector” stage).2 . for example. C1 plays a role similar to RS in Fig. 5. We ﬁrst study the core and subsequently add the biasing elements. 5 Bipolar Ampliﬁers It follows that R1 = 25:8 k R2 = 22:3 k : (5. the base-emitter voltage of Q1 tends to increase.84(a) respond to a change in Vin ? If Vin rises by a small amount Vin .cls v. Since Vout changes in the same . requiring that Vout go up. The higher emitter current translates to a greater drop across RE and hence a higher Vout . Thus. 5. In high-performance applications such as cellphones. jC1 ! j.315) CB = 0:7 pF: (A common mistake is to make the impedance of CB negligible with respect to than with respect to 1=gm . Vout is constant. then VBE must rise and so must IE . the emitter follower senses the input at the base of the transistor and produces the output at the emitter. if we assume. Emitter Follower Core How does the follower in Fig. 5. and the possible topologies in Fig. the impedances of C1 and CB must be sufﬁciently small at this frequency. we may also use the term “follower” to refer to emitter followers in this chapter. if the ampliﬁer is used at the receiver front end of a 900-MHz cellphone. Shown in Fig.5.7.311) (5. its impedance.) (5.1 . 5. 2007 at 13:42 244 (1) 244 Chap.28 before proceeding further. rules illustrated in Fig. The collector is tied to VCC and hence ac ground. 5. raising the collector and emitter currents.1 = 1=gm =20 to ensure negligible gain degradation. From another perspective. For example.271).312) The last step in the design is to compute the required values of C1 and CB according to the signal frequency.3.

As explained later.” VCC V in Q1 Vout RE V in1 V BE1 V out1 (b) V in1 + ∆V in V BE2 V out1 + ∆V out (a) Figure 5. But this means the emitter current also decreases and so does IE RE = Vout . Vout Vin .15 The reader may wonder if an ampliﬁer with a subunity gain has any practical value. then VBE2 must be less than VBE1 .84(b)]. 2006] June 30.84 (a) Emitter follower sensing an input change.85. 5.3 Bipolar Ampliﬁer Topologies VCC V in Input Applied to Base 245 Q1 RE Output Sensed at Emitter Vout Figure 5.43. v + g v = vout r m RE and hence (5. Another interesting and important observation here is that the change in Vout cannot be larger than the change in Vin . Thus. Shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the input and output impedances of the emitter follower make it a particularly useful circuit for some applications. Note that Vout is always lower than Vin by an amount equal to VBE . the gain becomes equal to unity.cls v. ﬁrst assuming VA = 1.317) v = r+ 1 vout : RE 15 In an extreme case described in Example 5. 5. 5. 2007 at 13:42 245 (1) Sec. direction as Vin . Vout Vin . Suppose Vin increases from Vin1 to Vin1 + Vin and Vout from Vout1 to Vout1 +Vout [Fig.83 Emitter follower. contradicting the assumption that Vout has increased. we expect the voltage gain to be positive. and the circuit is said to provide “level shift.85 Small-signal model of emitter follower. (b) response of the circuit. (5. the equivalent circuit yields v in rπ vπ g vπ m v out RE Figure 5. Let us now derive the small-signal properties of the follower. implying that the follower exhibits a voltage gain less than unity. If the output changes by a greater amount than the input.318) .

318).43). VCC V in Q1 Vout I1 Figure 5.87(a) therefore reduces to that shown in Fig. 5.321) Example 5. Suppose.cls v. 5.322) This result can also be derived intuitively. 5 Bipolar Ampliﬁers We also have vin = v + vout : Substituting for v from (5.87(d). (5. we wish to model vin and Q1 by a Thevenin equivalent. The Thevenin resistance is obtained by setting the input to zero [Fig. 5. 5. The Thevenin voltage is given by the open-circuit output voltage produced by Q1 [Fig.87(a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we obtain (5. Equation (5. 5. 5. the follower is typically realized as shown in Fig. (5.87(b)]. 2007 at 13:42 246 (1) 246 Chap. 2006] June 30. yielding Solution Av = 1: (5. as if Q1 operates with RE = 1 (Example 5. A constant current source ﬂowing through Q1 requires that VBE = VT lnIC =IS remain constant. as shown in Fig.86. we recognize that Vout exactly follows Vin if VBE is constant.321) suggests that the emitter follower acts as a voltage divider. the value of RE in Eq.86 Follower with current source. Thus.320) (5. Determine the voltage gain if the current source is ideal and VA = 1. Exercise Repeat the above example if a resistor of value R1 is placed in series with the collector. VBE .319) vout = 1 vin 1 + r 1 + 1 RE RE 1 : RE + g m The voltage gain is therefore positive and less than unity.321) must tend to inﬁnity. conﬁrming operation as a voltage divider. . a perspective that can be reinforced by an alternative analysis. The circuit of Fig.87(c)] and is equal to 1=gm . vThev = vin .43 In integrated circuits. Writing Vout = Vin . Since the emitter resistor is replaced with an ideal current source.

291) as RS = + 1 + 1=gm . (c) Thevenin resistance. (d) simpliﬁed circuit. The reader can show that the open-circuit voltage is equal to vin . Determine the voltage gain of a follower driven by a ﬁnite source impedance of RS [Fig. (b) Thevenin resistance seen at emitter.cls v.323) This result can also be obtained by solving the small-signal equivalent circuit of the follower.87 (a) Emitter follower stage. revealing that Solution vout = RE vin RE + RS + 1 : + 1 gm (5. Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.88(b)] is given by (5.88 (a) Follower with source impedance. the Thevenin resistance [Fig. Furthermore.88(a)] if VA = 1.44 VCC RS v out VCC Q1 Q1 RS 1 + gm β+ 1 v Thev = v in RE v out (c) Figure 5.3 Bipolar Ampliﬁer Topologies VCC Q1 v in RE (a) (b) 247 VCC Q1 v out v in v out = v in VCC Q1 v Thev = v in R Thev (c) R Thev = 1 gm v out RE (d) Figure 5. and Q1 by a Thevenin equivalent. 5. (b) Thevenin voltage . 2006] June 30. 5. We model vin . RS v in RE R Thev (a) (b) Example 5. 5. (c) simpliﬁed circuit.88(c) depicts the equivalent circuit. . 2007 at 13:42 247 (1) Sec. RS .

reducing the gain from 20 to 20 RC jj8 =RC = 0:159. the current iX and gm v ﬂow through RE . of course. we have iX r = v . 5 Bipolar Ampliﬁers Exercise What happens if RE = 1? In order to appreciate the usefulness of emitter followers.90(a). Also.89 (a) Input impedance of emitter follower. RE .325) vX = r + 1 + R : E iX (5. let us compute their input and output impedances. 2007 at 13:42 248 (1) 248 Chap.324) (5. (b) An emitter follower biased at a current of 5 mA is interposed between the CE stage and the speaker. which is the case for an emitter follower [Fig. Rsp . . (5.162) derived for a degenerated CE stage. Since the input impedance of the CE topology is independent of the collector resistor (for VA = 1). Adding the voltages across r and RE and equating the result to vX .cls v. its value remains unchanged if RC = 0. and the follower is biased with an ideal current source. Assume = 100. Determine the voltage gain of the CE ampliﬁer if (a) The stage drives an 8. vX = v + iX + gm v RE = iX r + iX + gm iX r RE . 5. Example 5. we have iX vX rπ vπ RE g vπ m R in VCC RC Q1 RE R in 0 VCC Q1 RE (a) (b) Figure 5.” This concept can be illustrated by an example. the equivalent resistance seen at the collector is now given by the parallel combination of RC and the speaker impedance. In the equivalent circuit of Fig. The key observation here is that the follower “transforms” the load resistor. (b) equivalence of CE and follower stages. 5. to a much larger value. producing a voltage drop equal to iX + gm v RE .45 A CE stage exhibits a voltage gain of 20 and an output resistance of 1 k . and hence (5. 5. no coincidence.speaker directly. VA = 1.89(a). thereby serving as an efﬁcient “buffer.326) This expression is identical to that in Eq.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.89(b)]. This is. 2006] June 30. Solution (a) As depicted in Fig. The voltage gain therefore degrades drastically.

(5. 5. we note that Rin1 = r2 + + 1Rsp = 1058 : Thus. 5. the former is equal to RS = + 1 + 1=gm.3 Bipolar Ampliﬁer Topologies 249 1 kΩ VCC RC R sp Q1 C1 v in 1 kΩ VCC RC Q2 Q1 R in1 I1 C1 R sp v in (a) (b) Figure 5. (b) From the arrangement in Fig.91(b).91 (a) Output impedance of a follower. and hence RS VCC Q1 RE R out RE RS VCC Q1 RS 1 + gm β+ 1 RE (a) (b) Figure 5. a Exercise Repeat the above example if the emitter follower is biased at a current of 10 mA. 2006] June 30.327) (5.cls v. 5. From Fig.90(b).90 (a) CE stage and (b) two-stage circuit driving a speaker. 5.328) 20 RC jjRin1 =RC = 10:28. assuming the circuit is driven by a source impedance RS [Fig. we need not resort to a small-signal model here as Rout can be obtained by inspection.88. (b) components of output resistance. We now calculate the output impedance of the follower. Interestingly. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As illustrated in Fig. the output resistance can be viewed as the parallel combination of two components: one seen looking “up” into the emitter and another looking “down” into RE . 2007 at 13:42 249 (1) Sec. 5. the voltage gain of the CE stage drops from 20 to substantial improvement over case (a).91(a)].

R S Rout = + g1 jjRE : +1 m (5. 5.329) This result can also be derived from the Thevenin equivalent shown in Fig.88(c) by setting vin to zero. .

323). the results obtained above can be readily modiﬁed to reﬂect this nonideality.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We say the follower operates as a good “voltage buffer” because it displays a high input impedance (like a voltmeter) and a low output impedance (like a voltage source). RE jjrO RE jjrO + RS 1 + g1 + m Rin = r + + 1RE jjrO .92 Follower including transistor output resistance. thereby providing higher “driving” capability. 2006] June 30.cls v. RS . to a much lower value.326) and (5. Fortunately. Figure 5. rO appears in parallel with RE .329) reveals another important attribute of the follower: the circuit transforms the source impedance. We can therefore rewrite Eqs. Effect of Transistor Output Resistance Our analysis of the follower has thus far neglected the Early effect. 2007 at 13:42 250 (1) 250 Chap. (5. 5 Bipolar Ampliﬁers Equation (5.92 illustrates a key point that facilitates the analysis: in small-signal operation.329) as VCC RS v in Q1 RE rO v in RS Q1 RE rO Figure 5. (5.

we have rO RS + 1 rO + + 1 g m Rin = r + + 1rO .43) but with a ﬁnite source impedance RS .46 (5.330) (5.331) (5. Since RE Solution = 1.332) Determine the small-signal properties of an emitter follower using an ideal current source (as in Example 5. Rout = RS 1 + g1 jjRE jjrO : + m Av = Example 5.

and hence (5.333) (5.337) . gm rO 1.334) (5. Rout = RS 1 + g1 jjrO : + m Av = rO + RS 1 + Rin + 1rO : Av rO (5.336) (5.335) Also.

The following example illustrates this point. Exercise How are the results modiﬁed if RE 1? The buffering capability of followers is sometimes attributed to their “current gain. we can say that for a current iL delivered to the load.94 Biasing a follower by means of (a) resistive divider. As usual. the follower draws only iL = + 1 from the source voltage (Fig. where RB IB is chosen much less than the voltage drop across RE . the emitter follower can operate with a base voltage near VCC .94(b) employs RB = 10 k and RE = 1 k .3 Bipolar Ampliﬁer Topologies 251 We note that Av approaches unity if RS + 1rO . vX sees the load impedance multiplied by + 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.16 A. This is because the collector is tied to VCC . Calculate the bias current and voltages if IS = 5 10. Emitter Follower with Biasing The biasing of emitter followers entails deﬁning both the base voltage and the collector (emitter) current. we follow the iterative procedure described in Section 5. and VCC = 2:5 V. a condition typically valid. VCC R1 C1 X R2 RE Q1 Vout v in RB C1 IB X Y RE Q1 Vout VCC v in (a) (b) Figure 5. Thus. unlike the CE topology. What happens if drops to 50? Example 5.94(b). 5.2. followers are often biased as shown in Fig. 2007 at 13:42 251 (1) Sec. Figure 5. 5.cls v.” Since a base current iB results in an emitter current of + 1iB . 2006] June 30.93). For this reason. Writ- . iL β+ 1 vX VCC Q1 iL Load Figure 5.19 for the CE stage. 5. 5.94(a) depicts an example similar to the scheme illustrated in Fig.47 Solution To determine the bias current. The follower of Fig. thus lowering the sensitivity to . = 100. the current ﬂowing through R1 and R2 is chosen to be much greater than the base current. allowing the same voltage for the base without driving Q1 into saturation. It is interesting to note that. 5. (b) single base resistor.3.93 Current ampliﬁcation in a follower.

2007 at 13:42 252 (1) 252 Chap.338). Exercise If RB is doubled. (5. is the circuit more or less sensitive to the variation in ? As manifested by Eq.339) and hence relatively accurate.cls v. The reader is encouraged to repeat the above iterations with = 50 and determine the exact current.95 Capacitive coupling at input and output of a follower. and RE gives RB IC + V + R I = V . leads to IC = 1:545 mA: (5. BE E C CC which. In integrated circuits. Depicted in Fig. so are VBE and RB IB .94 suffer from supply-dependent biasing.340) a value close to that in (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. IE = 1:593 V . (5. each serving a speciﬁc application.339) It follows that VBE = VT lnIC =IS = 748 mV. 5.338) 800 mV. reducing the drop across RE by 159 mV. IB RB = 159 mV whereas RE IC = 1:593 V. we expect that variation of and hence IB RB negligibly affects the voltage drop across RE and hence the emitter and collector currents. That is. IB RB is doubled ( 318 mV). 5 Bipolar Ampliﬁers ing a KVL through RB . As a rough estimate. if VCC rises.338). VCC RB C1 Q1 C2 RL v in Figure 5. 5. respectively (if . 2006] June 30. (5. 5. Since IB RB RE IC . so do VX and VY . 0:159 V=1 k = 1:434 mA. the base-emitter junction.96. this issue is resolved by replacing the emitter resistor with a constant current source (Fig. we have IC = 1:593 mA. the three ampliﬁer topologies studied here exhibit different gains and I/O impedances. Thus. emphasizing that a proper bias point must be established to deﬁne the small-signal properties of each circuit. but the bias current remains constant.4 Summary and Additional Examples This chapter has created a foundation for ampliﬁer design. implying that a twofold change in leads to a 10 change in the collector current. for = 50. 5. the topologies of Fig. CE and CB stages can provide a voltage gain greater than unity and their input and output impedances are independent of the load and source impedances. with VBE (5.95). Under this condition. Now. Using this value in Eq. since IEE is constant.

and R2 between collector and ground. (b) equivalent circuit with C1 shorted. RThev + 1 + RE : + 1 gm (5.343) . we have Solution vThev = R R1R vin 1+ S RThev = R1 jjRS : The resulting circuit resembles that in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. our emphasis is on solution by inspection and hence intuitive understanding of the circuits.97(a).43(a) and satisﬁes Eq. As usual. (c) simpliﬁed circuit .97(c)]. 5. (5. The simpliﬁed ac model is depicted in Fig. RS .97 (a) Example of CE stage. Assuming VA Example 5. and R1 with a Thevenin equivalent [Fig. 5. VA = 1). Replacing vin . 5.342) vout R2 jjRC vThev = . 5. VCC RC v out Q1 RE v in R1 RS Q1 RE R2 RC v out v Thev R Thev Q1 RE RC v out R2 R1 RS C1 R2 v in (a) (b) (c) Figure 5. 2007 at 13:42 253 (1) Sec. We assume various capacitors used in each circuit have a negligible impedance at the signal frequencies of interest. we consider a number of challenging examples. In this section. 5.97(b).48 = 1.96 Summary of bipolar ampliﬁer topologies. seeking to improve our circuit analysis techniques. determine the voltage gain of the circuit shown in Fig. 2006] June 30.341) (5.4 Summary and Additional Examples CE Stage CB Stage Follower 253 VCC RC Vout V in Q1 V in Q1 RC VCC V in Vout Vb VCC Q1 Vout RE Figure 5.185): (5. followers display a voltage gain of at most unity but their terminal impedances depend on the load and source impedances. On the other hand. revealing that R1 appears between base and ground.

5. compute the voltage gain of the circuit shown in Fig. As in the above example.98(b). R2 appears as an emitter degeneration resistor.98 (a) Example of CE stage. R1 jjRS + 1 + R R1 + RS : vin E + 1 gm (5. RC R1 RS jjR1 + 1 + R R1 + RS : vin 2 + 1 gm (5. we replace vin . As shown in the simpliﬁed diagram of Fig.98(a). 5.cls v.346) Exercise What happens if C2 is tied from the emitter of Q1 to ground? . 5 Bipolar Ampliﬁers Substituting for vThev and RThev gives R2 jjRC R1 vout = .345) vout = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.344) Exercise What happens if a very large capacitor is added from the emitter of Q1 to ground? Assuming VA Example 5. 2006] June 30. and R1 with a Thevenin equivalent and utilize Eq. RS . (b) simpliﬁed circuit. 2007 at 13:42 254 (1) 254 Chap. (5.185): Solution vout = . RC RThev + 1 + R vin 2 + 1 gm and hence (5.49 = 1. VCC RC C1 v out Q1 R1 C2 (a) v out RS Q1 R1 R2 RC v in RS R2 v in I1 (b) Figure 5.

(b) simpliﬁed circuit.4 Summary and Additional Examples 255 5. 5.cls v. Recall from Fig.99(b) thus yields (5. Req . 5. .347) Av = 1 . compute the voltage gain and input impedance of the circuit shown in Fig.75 that Req = R1 1 + g 1 : + m2 The simpliﬁed model in Fig.RC gm1 + Req .50 Assuming VA = 1. 2006] June 30.348) (5. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.99 (a) Example of CE stage.100(a) if VA Example 5.349) Rin = r1 + + 1Req = r1 + R1 + r2 : (5.75: (5. Example 5.351) Exercise Repeat the above example if R1 is placed in series with the emitter of Q2 . 5. VCC RC v out Q1 v in I1 R eq (a) (b) RC VCC Q2 VB R1 v in v out Q1 R eq Figure 5.99(a).350) (5.RC = 1 : + R1 1 + g 1 gm1 + m2 The input impedance is also obtained from Fig.51 = 1. 5. Solution The circuit resembles a CE stage (why?) degenerated by the impedance seen at the emitter of Q2 . Calculate the voltage gain of the circuit in Fig. 2007 at 13:42 255 (1) Sec.

. (b) simpliﬁed circuit.329): Solution Req = .g.101(a) if VA VCC RC v out Q1 R eq R in (a) Example 5. Q1 operates as a common-base device (why?) but with a resistance Req in series with its base [Fig. but with RC replaced by RC jjR1 : 1 Av = RC jjR1 : RS + g Solution (5. Since the base is at ac ground. concluding that Req can be viewed as the output resistance of such a stage. To obtain Req .91(a).100(b)]. R1 appears in parallel with RC and R2 is shorted to ground on both ends [Fig. the topology in Fig.101 (a) Example of CB stage.100 (a) Example of CB stage. (b) simpliﬁed circuit. In this circuit. 5. 5.271). 2007 at 13:42 256 (1) 256 VCC RC v out C1 v in RS Q1 R2 CB v in R1 Chap. 5.101(b)]. 5. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. as given by Eq. RC Q2 RB RE R in (b) Q1 R eq Figure 5. e. The voltage gain is given by (5.52 = 1.cls v. we recognize that Q2 resembles an emitter follower.352) m Exercise What happens if RC is replaced by an ideal currents source? Determine the input impedance of the circuit shown in Fig. (5. 5 Bipolar Ampliﬁers v out Q1 RS RC R1 (a) (b) Figure 5.

RB 1 +1 + g m2 jjRE : (5.353) .

2006] June 30. and another equal to 1=gm1 : eq Rin = R+ 1 + g 1 . Req . divided by + 1.101(b). from Fig. we observe that Rin contains two components: one equal to the resistance in series with the base. 2007 at 13:42 257 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5.cls v.4 Summary and Additional Examples 257 Now. 5.

where the output resistance of Q1 is explicitly drawn. Replacing vin .356) . 5.355) The reader is encouraged to obtain Rin through a complete small-signal analysis and compare the required “manual labor” to the above algebra.102(b). Noting that X is at ac ground. 5.53 Compute the voltage gain and the output impedance of the circuit depicted in Fig.102(c)]. Exercise What happens if the current gain of Q2 goes to inﬁnity? Example 5. RS .354) (5.102(a) with VA 1. and R1 with their Thevenin equivalent and recognizing that RE . VCC RS Q1 v in R1 X C2 R2 RE v out v in RS R1 Q1 RE (b) rO v out R2 (a) R Thev Q1 v Thev RE (c) v out R2 r O Figure 5. (c) simpliﬁed circuit.102 (a) Example of emitter follower. we construct the simpliﬁed circuit shown in Fig. we employ Eq. (b) circuit with C1 shorted.330) and write Solution vout RE jjR2 jjrO vThev = RE jjR2 jjrO + 1 + RThev g +1 m (5. 5. R2 . (5. and rO appear in parallel [Fig. m1B 1 1 1 R + = +1 + 1 gm2 jjRE + gm1 : (5.

(5.cls v.332): (5. 2006] June 30. 2007 at 13:42 258 (1) 258 Chap. we refer to Eq.357) Rout = RThev + g1 jjRE jjR2 jjrO +1 . 5 Bipolar Ampliﬁers and hence vout = RE jjR2 jjrO R R1R : vin R jjR jjr + 1 + RS jjR1 1 + S E 2 O g +1 m For the output resistance.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

RS jjR1 m = + g1 jjRE jjR2 jjrO : +1 m .

VCC R B2 R eq2 v in R eq1 R B1 Q2 Q1 RC v out Q3 RE v in Q3 RE R eq1 R eq2 RC v out (a) (b) Figure 5. we have from Fig.360) . As the ﬁrst step. 5.359) Exercise What happens if RS = 0? Example 5. Solution We identify the stage as a CE ampliﬁer with emitter degeneration and a composite collector load. 5. Since Req1 denotes the impedance seen looking into the emitter of Q2 with a base resistance of RB 1 .54 Determine the voltage gain and I/O impedances of the topology shown in Fig.103 (a) Example of CE stage. we represent the role of Q2 and Q3 by the impedances that they create at their emitter.75 B Req1 = R+11 + g 1 : m2 (5. (5.358) (5.103(a). (b) simpliﬁed circuit. Assume VA = 1 and equal ’s for npn and pnp transistors.

361) Av = . 5.5 Chapter Summary 259 Similarly. Req1 + g 1 + RE m3 B RC + R+21 + g 1 m1 : =. 5. It follows that (5. Rin = r3 + + 1RE + Req1 .103(b). 2006] June 30.363) Also. 2007 at 13:42 259 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. m1 leading to the simpliﬁed circuit shown in Fig.362) (5.cls v. R B1 + 1 + 1 + R E + 1 gm2 gm3 RC + Req2 (5. B Req2 = R+21 + g 1 .

the input and output impedances of ampliﬁers determine the ease with which various stages can be cascaded.5 Chapter Summary In addition to gain. . and rO .364) (5. respectively. rO (with emitter grounded).e. and 1=gm (with base grounded). Biasing techniques establish the required base-emitter and base-collector voltages while providing the base current. The impedances seen looking into the base. and emitter of a bipolar transistor are equal to r (with emitter grounded). RB1 + 1 . Signals simply perturb these conditions. carry a certain collector current and operate in the active region. r .. In order to obtain the required small-signal bipolar device parameters such as gm .365) Rout = RC + Req2 B = RC + R+21 + g 1 : m1 (5.367) Exercise What happens if RB 2 ! 1? 5.” i. Voltage ampliﬁers must ideally provide a high input impedance (so that they can sense a voltage without disturbing the node) and a low output impedance (so that they can drive a load without reduction in gain).366) (5. = r3 + + 1 RE + + 1 g m2 and (5. collector. the transistor must be “biased.

2007 at 13:42 260 (1) 260 Chap. 2006] June 30. and a moderate output impedance.105 4. The CB stage provides a moderate voltage gain. Emitter degeneration raises the output impedance of CE stages considerably. 5. and a moderate output impedance. a low input impedance. Emitter degeneration improves the linearity but lowers the voltage gain. Assume all diodes are forward-biased. An antenna can be modeled as a Thevenin equivalent having a sinusoidal voltage source V0 cos !t and an output resistance Rout . (Recall from Chapter 3 that each diode behaves as a linear D1 R1 D1 R1 D2 R1 D1 (a) (b) (c) R in R in R in D2 Figure 5. serving as a good voltage buffer. a moderate input impedance. Compute the output resistance of the circuits depicted in Fig. 2. 5. 6. The emitter follower provides a voltage gain less than unity.109.) 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7.108. IS = . Determine the input impedance of the circuits depicted in Fig. Determine the average power delivered to a load resistance RL and plot the result as a function of RL . Determine the small-signal input resistance of the circuits shown in Fig. Assume VA = 1. 5 Bipolar Ampliﬁers With a single bipolar transistor. Assume VA VCC R1 Q1 R2 R in R in (a) (b) (c) = 1. The voltage gain expressions for CE and CB stages are similar but for a sign. 5.107. The CE stage provides a moderate voltage gain. only three ampliﬁer topologies are possible: common-emitter and common-base stages and emitter followers. Compute the input resistance of the circuits depicted in Fig. 5. Problems 1. Compute the bias point of the circuits depicted in Fig. and a low output impedance.104. VCC Q1 VCC Q1 R1 R in VCC Q1 R in Q2 (d) Q2 Figure 5.104 resistance if the voltage and current changes are small. 5.cls v. a high input impedance.106. Assume = 100.105. 5. Compute the output impedance of the circuits shown in Fig. 5.

5 Chapter Summary R out RB Q1 R1 R out VB Q1 Q2 (b) (c) (d) 261 R out Q1 Q1 Q2 R out VCC VB (a) Figure 5. IS = 510. 10. and VA = 1. 2007 at 13:42 261 (1) Sec. Construct the small-signal equivalent of each of the circuits in Problem 7. 2006] June 30.106 VCC VCC Q1 R in R1 Q1 R in R1 (a) (b) Ideal VCC Q1 R in Q2 VB R1 (c) VB VCC Q2 Q1 R in (d) (e) VCC Q2 R in Q1 Figure 5. Construct the small-signal equivalent of each of the circuits in Problem 9. 5.cls v.16 A. IS = 6 10. 9. Calculate the bias point of the circuits shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Consider the circuit shown in Fig.111. Assume = 100. and VA = 1. . 5.16 A.16 A.107 VCC Q1 RC R out Q1 Q2 VB (b) R out (a) Figure 5. 5. where = 100.108 6 10. and VA = 1. 11. 8.110.

5 V 100 k Ω 500 Ω 100 k Ω Chap.5 V Q1 (a) Figure 5.112 (a) If the collector current of Q1 is equal to 0.112.5 V 500 V CC = 2.109 V CC = 2. = 100 and VA = 1.5 V 50 k Ω 3 kΩ rises 30 k Ω Q1 Figure 5. V CC = 2. 2006] June 30. calculate the value of IS .5 V Q1 (a) (b) (c) Figure 5. 5 V CC = 2. 2007 at 13:42 262 (1) 262 V CC = 2. In the circuit of Fig.5 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. how much base-collector forward bias is sustained if to 200? 12. . 5.5 V 1 kΩ 100 k Ω Bipolar Ampliﬁers V CC = 2.5 V RB 2 kΩ 3 kΩ Q1 Figure 5.110 (b) (c) V CC = 2.5 V 12 k Ω 1 kΩ Ω 16 k Ω Q1 16 k Ω Q1 Q2 13 k Ω 0.111 (a) What is the minimum value of RB that guarantees operation in the active mode? (b) With the value found in RB .cls v.5 V 34 k Ω 3 kΩ 9 kΩ V CC = 2.5 V 1 kΩ Q1 Q1 Q2 0.

114 for a gain (= gm RC ) of A0 with an V CC R1 RC Q1 R2 Figure 5.16 A. Repeat Problem 13 for a gm of at least 1=26 . and VA = 1. 5.115 is designed for a collector current of 0. determine the maximum value of R2 that guarantees operation of Q1 in the active mode. 6 10. 14. 5.117. The circuit of Fig. IS = 10.5 V R1 5 kΩ Q1 R2 Figure 5. and VA = 1.5 Chapter Summary 263 (b) If Q1 is biased at the edge of saturation. In the circuit of Fig. (b) Construct the small-signal equivalent circuit. 16. The circuit of Fig. (b) What is the error in IC if RE deviates from its nominal value by 5? 17. and VA = 1. IS = 2 10.115 (a) Determine the required value of R1 . Consider the circuit shown in Fig. Assume = 100.114 output impedance of R0 .17 A. (a) Determine the collector currents of Q1 and Q2 . 13. If = 100. = 100. 5. where IS 1 = 2IS 2 = 5 10.16 A.25 mA. and VA = 1.cls v. Assume IS = V CC = 2.113 must be designed for an input impedance of greater than 10 k and V CC = 2. What is the maximum achievable input impedance here? Assume VA = 1.116.113 a gm of at least 1=260 . 18. 2006] June 30. 1 = 2 = 100. 2007 at 13:42 263 (1) Sec. 5. calculate the value of IS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 15. .17 A. Explain why no solution exists. 5. We wish to design the CE stage depicted in Fig. determine the minimum allowable values of R1 and R2 . 5.5 V R1 RC 3 kΩ 10 k Ω Q1 R2 R E = 200 Ω Figure 5.

cls v.5 V RB Rp 1 kΩ 100 Ω Q1 Figure 5. The circuit of Fig.117 19. 9 kΩ = IS2 = 4 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 20.5 V 100 Ω 1 = 2 = 100. Compute the VCC = 2. IS 1 VA = 1.16 A.118. 5 Bipolar Ampliﬁers RC 2 kΩ Q1 R2 R E = 100 Ω Figure 5. 5. In the circuit depicted in Fig. V CC = 2. (b) Draw the small-signal equivalent circuit.118 (a) Determine the operating point of the transistor.119 must be biased with a collector current of 1 mA. and 16 k Ω Q1 Q2 Figure 5.5 V 30 k Ω Chap. 5.116 VCC = 2. 2007 at 13:42 264 (1) 264 V CC = 2. 2006] June 30.5 V 13 k Ω R1 RC Q1 1 kΩ Q2 12 k Ω R2 RE 400 Ω Figure 5.119 .

121 23. V CC = 2. 21. 5. and VA 24.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and VA = 1. where IS Calculate the operating point of Q1 . = 100. what is the value of IS ? V CC = 2.121.5 Chapter Summary 265 required value of RB if IS = 3 10.5 V 300 Ω X 10 k Ω Q1 Figure 5. Due to a manufacturing error. IS = 8 10. If = 100. = 100. 5. VX = 1:1 V. What is the minimum allowable value of RB if the base-collector VCC = 2. = 100. = 100 and VA = 1.123 (a) Determine the operating point of Q1 . V CC = 2. and VA = 1. 2007 at 13:42 265 (1) Sec.5 V Q1 400 Ω Figure 5.122. a parasitic resistor.16 A. 5. 2006] June 30. 40 k Ω Q1 Figure 5.120 22. 5.123. RP .16 A.16 A.120. 20 k Ω 500 Ω = 6 10. Consider the circuit shown in Fig. has appeared in series with the collector of Q1 in Fig. In the circuit of Fig. and VA = 1. .cls v.5 V 10 k Ω 1 kΩ = 1. In the circuit of Fig.16 A. 5.122 forward bias must not exceed 200 mV? Assume IS = 3 10.5 V RB Rp 1 kΩ 500 Ω Q1 Figure 5.

31.124 (a) Calculate VB such that Q1 carries a collector current of 1 mA. 5 Bipolar Ampliﬁers (b) Draw the small-signal equivalent circuit.126 IS = 9 10. Draw the small-signal model of the circuits in Problem 28. Assume npn VCC = 2. Determine the forward. Determine the bias point of each circuit shown in Fig. 28. In the circuit of Fig.5 V 32 k Ω 18 k Ω 100 Ω 18 k Ω Figure 5. VCC = 2.16 A. 5.125. and VA = 1. and VA = 1. 30. 26.16 A.16 A.128 such that Q1 sustains a reverse bias of 300 mV . 5.126.127 to place Q1 at the edge of saturation. 27. 2006] June 30. Calculate the value of RE in Fig.5 V Q1 Q1 Q2 1 kΩ (a) (b) VCC = 2. IS 1 = IS 2 = 3 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. IS = 8 10. (b) Construct the small-signal equivalent circuit. 29.5 V Q1 VB 500 Ω Q2 Figure 5.5 V Q1 60 k Ω 200 Ω = 2 pnp = 100. But the actual value of this resistor can vary by 5. 200 Ω = 100.124.16 A.or reverse-bias across the basecollector junction at these two extremes. Assume npn 32 k Ω = 2 pnp = 100. V CC = 2. VCC = 2. Assume = 50.cls v. 25. We have chosen RB in Fig. 5. Calculate the bias point of the circuits shown in Fig. 5. and VA = 1.125 IS = 9 10. 5. and VA = 1. Construct the small-signal model of the circuits in Problem 26.5 V Q1 Q2 300 Ω 80 k Ω (b) (a) Figure 5. 2007 at 13:42 266 (1) 266 Chap.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V Q1 RB 1 kΩ 267 5 kΩ Figure 5.130 .127 VCC = 2.5 V Q1 20 k Ω 1. 2007 at 13:42 267 (1) Sec.130(a) is called a “VBE multiplier. 5. what value of IS yields a collector current of 1 mA in Fig. and VA = 1.5 Chapter Summary VCC = 2. determine the collectorVCC R1 Q1 R2 R1 Q1 R2 R3 (a) (b) Figure 5.5 V 10 k Ω RE Q1 10 k Ω 5 kΩ Figure 5. 5. What happens if the value of RE is halved? 32. The topology depicted in Fig.”(The npn counterpart has a similar topology. IS = 8 10. 5.130(b).cls v.16 A.129? VCC = 2. If = 80 and VA = 1. 5.128 across its base-collector junction.6 k Ω Figure 5.129 33. Assume = 50. 2006] June 30.) Constructing the circuit shown in Fig.

2V T and no Early effect. What is the minimum 50 k Ω VCC = 2. 2006] June 30.134 exhibits the following hypothetical characterisRC V in 1 kΩ VCC Vout Q1 Figure 5. If the voltage gain VCC Ideal Vout V in Q1 Figure 5.133 is equal to 50 and the output impedance equal to 10 k .134 tic: IC = IS exp VBE . (The npn counterpart can also be used. If VA = 10 V and VBE = 0:8 V. We wish to design the CE stage of Fig. 5. 35.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. The CE stage of Fig.cls v.132 in the active mode. Compute the voltage gain for a bias current of 1 mA. (5.5 V Vout V in Q1 Figure 5. 37. determine the bias current of the transistor. 36. calculate the required bias current. The circuit of Fig.132 must be designed for maximum voltage gain while maintaining Q1 RC V in 1 kΩ VCC Vout Q1 Figure 5. Suppose the bipolar transistor in Fig. 2007 at 13:42 268 (1) 268 Chap. 5.) 34.131 for a voltage gain of 20. 5.368) . 5 Bipolar Ampliﬁers emitter voltage of Q1 if the base current is negligible.133 employs an ideal current source as the load.131 allowable supply voltage if Q1 must remain in the active mode? Assume VA = 1 and VBE = 0:8 V.

cls v. 43. 40. 5. what is the gain if the dc voltage drops across RC and RE are equal to 20VT and 5VT . We wish to design the degenerated stage of Fig.16A. Calculate the bias current and the value of RC if = 100. determine the relative change in the gain if IC varies by 10%: (a) gm RE is nominally equal to 3. 41. VCC VCC Q2 Vout V in Q1 V in Q1 Q2 R1 Vout V in Q1 VCC Q2 RC Vout (a) (b) (c) VCC Q2 RC Vout V in Q1 V in VCC Q2 Vout RC Q1 (d) (e) Figure 5.135.135 39. and VA = 1. 2006] June 30. Express the voltage gain of the stage depicted in Fig. Repeat Problem 38 with VA 1. 5. IS = 5 10. (5. What is the maximum gain that can be achieved in this stage? . Consider Eq. The more constant gain in the second case translates to greater circuit linearity. For the following two cases. Calculate the input impedance of the circuit.5 Chapter Summary 269 38.136 in terms of the collector bias VCC RC Vout V in Q1 RE Figure 5. Assume VA = 1. If VA = 1. Writing gm = IC =VT . respectively? 42. 5. Repeat Problem 42 for a voltage gain of 100. 5. 2007 at 13:42 269 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and VT . we note that gm and hence the voltage gain vary if IC changes with the signal level.157) for the gain of a degenerated CE stage. (b) gm RE is nominally equal to 7. IC . Determine the voltage gain and I/O impedances of the circuits shown in Fig.136 current. 5. Transistor Q2 in Figs.135(d) and (e) operates in soft saturation.137 for a voltage gain of 10 with Q1 operating at the edge of saturation. Explain why no solution exists.

5. compute the output impedance of a degenerated CE stage with VA 1. Calculate the output impedance of the circuits shown in Fig. 46.140. 5 Bipolar Ampliﬁers VCC = 2. 2007 at 13:42 270 (1) 270 Chap. Compare the output impedances of the circuits illustrated in Fig. Assume 1. 45.138. 2006] June 30. .139. Assume VA = 1. 48. Assume VA = 1.137 44. Assume 1. 5. 5. 5. Using a small-signal equivalent circuit. Assume VA = 1. Construct the small-signal model of the CE stage shown in Fig. 49. 50. Determine the voltage gain and I/O impedances of the circuits shown in Fig. 5.43(a) and prove that the output impedance is equal to RC if the Early effect is neglected. Assume 1.5 V RC Vout V in Q1 200 Ω Figure 5. 5. Compute the voltage gain the I/O impedances of the circuits depicted in Fig. Construct the small-signal model of the CE stage shown in Fig.141.138 47.43(a) and calculate the voltage gain. VCC Q2 R1 Vout V in Q1 RE (a) (b) (c) VCC RC Vout V in Q1 Q2 V in Q2 VCC RC Vout Q1 VCC RC V in RB Q1 Q2 Vout V in RB Q1 RC Vout Q2 VCC VB (d) (e) Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

5 VCC RE V in Q1 Chapter Summary VCC RE V in Vout Q1 RC Vout Q2 V in VCC Q3 VCC RE Q1 Vout RC Q2 Q2 V in VCC Q1 Vout RC 271 RC Q2 (a) (b) (c) (d) Figure 5. Assume IS = 8 10. Writing r = VT =IC . (a) Calculate the voltage gain and I/O impedances of the circuit. Repeat Example 5.217) and prove that the result remains close to r if IB RB VT (which is valid because VCC and VBE typically differ by about 0. The common-base stage of Fig. 2007 at 13:42 271 (1) Sec.141 51.33 with RB = 25k and RC = 250 .139 R out R out Q1 Q2 Q1 R out Q2 VCC Q1 RB R1 Q2 VCC I1 (a) (b) (c) Figure 5.5 V or higher.cls v. assume the capacitors are very large. 5.16 A. Also. 5. . = 100. Assume VA = 1.) 52.140 VCC Q1 Q2 R out (a) VCC Q1 Q2 R out (b) Figure 5.142. (5.143 is biased with a collector current of 2 mA. Calculate vout =vin for each of the circuits depicted in Fig. expand Eq. 5. 53. Is the gain greater than unity? 54.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. and VA = 1.

144.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V RC 10 k Ω Vout V in C1 Q1 100 Ω Vout V in 1 kΩ C1 V in 1 kΩ Vout Q1 500 Ω C1 C2 Q1 2 kΩ 11 k Ω C2 (a) (b) (c) 2 kΩ Figure 5.5 V 100 k Ω 1 kΩ 50 k Ω Chap.144 (b) (c) (d) VCC Q3 RC Vout Vout Q1 V in RS RE Vb V in Vb VCC Q2 Q1 Vout V in RC Q1 RE Vb Vb . Assume VA = 1. Determine the voltage gain of the circuits shown in Fig. 2006] June 30. 5.cls v.143 (b) How should VB and RC be chosen to maximize the voltage gain with a bias current of 2 mA? 55. 5 V CC = 2. 2007 at 13:42 272 (1) 272 V CC = 2. VCC Q3 VCC Q2 RC Vout Q1 V in (a) Figure 5.142 VCC RC 500 Ω Vout Q1 V in Vb Figure 5.5 V 1 kΩ 14 k Ω Bipolar Ampliﬁers V CC = 2.

Consider the CB stage depicted in Fig. Assume VA VCC VCC VCC R1 Q1 Q2 R1 Q1 Q2 R in (a) = 1. determine the relationship between vout1 =vin and vout2 =vin . 5.147 59.148 if VA = 1 and CB is very large. Calculate the voltage gain of the circuit shown in Fig. 1 kΩ = 100.151 provides two outputs. Assume VA = 1. 5. If IS 1 = 2IS 2 .147.146. 5.145 57. where and CB is very large. 5. IS = 8 10. VCC ideal Vout Q1 V in Vb Figure 5. Calculate the voltage gain and I/O impedances of the CB stage shown in Fig. Compute the voltage gain and I/O impedances of the stage shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 63. (b) Calculate the voltage gain and I/O impedances of the circuit. VCC = 2. 60.5 Chapter Summary 273 56. 2007 at 13:42 273 (1) Sec. 61. 5. 5.146 58. . Assume VA 1. Compute the input impedance of the stages depicted in Fig. (a) Determine the operating point of Q1 .149 if VA = 1 and CB is very large. Repeat Problem 58 for CB = 0.145. 5. 2006] June 30. 5. Calculate the voltage gain and the I/O impedances of the stage depicted in Fig.5 V 13 k Ω V out Q1 V in 400 Ω CB 12 k Ω Figure 5. 62.cls v.150 if VA 1. The circuit of Fig. VA = 1.16 A. VCC R2 R2 R1 Q1 Vb R in Q2 R2 R1 Q1 Q2 R in (b) R in (c) (d) Figure 5.

150 VCC RC R C V out1 Q1 V in Vb Q2 Vout2 Figure 5. For RE = 100 in Fig. 66. Calculate the required bias current and RE .148 VCC ideal V out Q1 V in R1 CB R2 Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5 Bipolar Ampliﬁers VCC Q2 V out Q1 V in R2 R1 CB Figure 5. Assume VA = 1. determine the voltage gain of a CB stage with emitter degeneration. Assume 1. determine the bias current of Q1 such that the gain is equal to 0.151 64.9.8. 2006] June 30. 5. A microphone having an output impedance RS = 200 drives an emitter follower as shown . and VA 1.149 VCC ideal V out Q1 V in RS Vb Figure 5. Assume = 100 and VA = 1. 67.cls v. a base resistance.152. Using a small-signal model. 5. 65. 2007 at 13:42 274 (1) 274 Chap.152 must provide an input impedance of greater than 10 k with a minimum gain of 0. The circuit of Fig.

153 .5 Chapter Summary VCC = 2. 5. Compute the voltage gain and I/O impedances of the circuits shown in Fig. VCC V in Q1 Vout Vb Q2 (a) VCC V in Q1 Vout Q2 (b) (c) VCC V in RS Q2 Q1 Vout VCC V in RE Q2 Q1 Vout RE V in VCC Q1 Vout Q2 (d) (e) Figure 5.” where Q1 plays a role somewhat similar to an emitter follower driving Q2 . determine the impedance seen at the base of Q1 .152 in Fig.154 69. 2006] June 30.153. . Figure 5. Note that IE1 IC 1 = IB2 = IC 2 = . Determine the bias current such that the output impedance does not exceed 5 VCC = 2. Assume = 100 and VA = 1. calculate the impedance seen at the emitter of Q2 .155 depicts a “Darlington pair. (b) If the base of Q1 is grounded.5 V V in Q1 Vout RE 275 Figure 5. deﬁned as IC 1 + IC 2 =IB 1 . 5.cls v. Assume VA = 1 and the collectors of Q1 and Q2 are tied to VCC .5 V V in RS Q1 I1 R out Figure 5. 5. (c) Compute the current gain of the pair. (a) If the emitter of Q2 is grounded. Assume VA = 1. 2007 at 13:42 275 (1) Sec.154.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 68.

158 illustrates a cascade of an emitter follower and a common-emitter stage. Assume IS = 7 10.155 70. V in C1 Q1 C2 100 Ω 1 kΩ Vout Figure 5. 5 Bipolar Ampliﬁers Q1 Q2 Figure 5.156 (a) Calculate the output impedance of the current source.5 V 10 k Ω Q1 .) Also. Q2 serves as a current source for the input device VCC V in Q1 R CS Vb Q2 RE Figure 5. Determine the voltage gain of the follower depicted in Fig. Figure 5. 5. 2007 at 13:42 276 (1) 276 Chap. . 5. RCS . 71. = 100. (But for bias calculations. 72.157.158 sume VA 1.cls v. and VA = 5 V.16 VCC = 2.156. 2006] June 30.157 A. AsVCC V in RC Q1 X RE Q2 Vout Figure 5. (b) Replace Q2 and RE with the impedance obtained in (a) and compute the voltage gain and I/O impedances of the circuit. assume VA = 1. In the emitter follower shown in Fig. assume the capacitors are very large.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

160 greater than 5 k . 75.159 VA = 1. and an output impedance of 1 k . The CE stage of Fig. Design Problems In the following problems. 2007 at 13:42 277 (1) Sec. We wish to design the CE stage of Fig. IS = 6 10. 5.16 A. Design the stage. If the lowest signal frequency of interest is 200 Hz. and input impedance of VCC = 2. If the transistor is allowed to sustain a basecollector forward bias of 400 mV. 5.161 impedance no greater than 500 .161 for maximum voltage gain but with an output VCC = 2.161 must achieve maximum input impedance but with a voltage gain of at least 20 and an output impedance of 1 k . 76. 2006] June 30.5 V RB V in CB RC Vout Q1 Figure 5. unless otherwise stated. estimate the minimum allowable value of CB . Assume VCC V in RC Q1 X RE Q2 Vout Vb Figure 5. assume = 100. . 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.159 shows a cascade of an emitter follower and a common-base stage. Design the CE stage shown in Fig. and VA = 1. 5. 5. 73.5 V RB V in RC Vout Q1 Figure 5. design the stage and calculate the required supply voltage. (b) Calculate the voltage gain. Figure 5. Allowing the transistor to experience at most 400 mV of base-collector forward bias. 77. vout =vin = vX =vin vout =vX . (b) Determine the voltage gain.5 Chapter Summary 277 (a) Calculate the input and output impedances of the circuit. 74. (a) Calculate the I/O impedances of the circuit. vout =vin = vX =vin vout =vX .cls v. The stage depicted in Fig. design the stage.161 must be designed for minimum supply voltage but with a voltage gain of 15 and an output impedance of 2 k .160 for a voltage gain of 10.

84. 81. We wish to design the CE stage of Fig. assume the current ﬂowing through R1 is approximately 10 times the base current. a voltage gain of 5. If the voltage gain must be equal to A0 . . 85. Design the CB ampliﬁer of Fig. 5. The CB ampliﬁer of Fig.161 for minimum power dissipation.163 for a power budget of 5 mW and a voltage gain of 10. Design the degenerated CE stage of Fig.162 impedance of 500 . 2007 at 13:42 278 (1) 278 Chap. Assume a voltage drop of 10VT = 260 mV across RE so that this resistor does not affect the input impedance signiﬁcantly. and the lowest frequency of interest is 200 Hz. 5.162 for a voltage gain of 5 and an output V CC = 2. 5 Bipolar Ampliﬁers 78. 5. 82. Design the CE stage of Fig. What is the minimum required power dissipation? Make the the same assumptions as those in Problem 83. Make the same assumptions as those in Problem 83. and a voltage drop of 200 mV across RE .163 for a voltage gain of 20 and an input V CC = 2. Design the stage of Fig. determine the trade-off between the power dissipation and the output impedance of the circuit. 5.163 for an output impedance of 200 and a voltage gain of 20. 2006] June 30. The stage of Fig.163 must achieve a voltage gain of 8 with an output impedance of 500 . 79. 5. Design the circuit.161 for a power budget of 1 mW and a voltage gain of 20. Assume RE sustains a voltage drop of 300 mV and the current ﬂowing through R1 is approximately 10 times the base current.163 impedance of 50 . and the current ﬂowing through R1 is approximately 10 times the base current. Design the circuit with the same assumptions as those in Problem 83. assuming that RE sustains 200 mV. 86. We wish to design the CB stage of Fig.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V R1 CB Q1 R2 RE Vin RC Vout Figure 5.162 for a power budget of 5 mW. 83. 5. Design the common-base stage shown in Fig. 5.5 V R1 V in R2 RE RC Vout Q1 Figure 5. 80.162 must be designed for maximum voltage gain but an output impedance of no greater than 1 k . and Q1 experiences a maximum base-collector forward bias of 400 mV. Also. 5. 5. Assume the current ﬂowing through R1 is approximately 10 times the base current.

VA. assume IS. 5.5 V R1 V in C1 Q1 RE C2 Vout RL Figure 5.9. IS.npn = 5 V.16 A. 91. RL = 50 . 88. Assume RL = 200 . The common-emitter shown in Fig.164 impedance of greater than 10 k . The follower shown in Fig.164 for a voltage gain of 0.16 A.163 for the minimum supply voltage if an input impedance of 50 and a voltage gain of 20 are required. 2006] June 30.165 gain of 0. 89.8.pnp = 8 10. with a voltage VCC = 2. The follower of Fig. Design the circuit assuming that the lowest frequency of interest is 100 MHz. 5.5 V 100 k Ω 1 kΩ V in C1 C2 P Vout Q1 500 Ω Figure 5. 5. What is the minimum load resistance.166 must amplify signals in the range of 1 MHz to 100 MHz. 5.5 Chapter Summary 279 87.165 must drive a load resistance. 2007 at 13:42 279 (1) Sec.pnp = 3:5 V.85 and an input VCC = 2. that it can drive? 90. 5.cls v. 5.166 .164 must consume 5 mW of power while achieving a voltage gain of 0.npn = 5 10.5 V R1 V in Q1 Vout RL Figure 5. Design the CB stage of Fig. RL .) SPICE Problems In the following problems. npn = 100. pnp = 50. Design the emitter follower shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VA. Make the same assumptions as those in Problem 83. (Hint: select the voltage drop across RE to be much greater than VT so that this resistor does not affect the voltage gain signiﬁcantly. V CC = 2.

e. 5. and 1 pF.5 V 100 k Ω 1 kΩ N C1 C2 IX VX Q 1 1 kΩ 500 Ω Figure 5. Repeat Problem 93 for the stage illustrated in Fig.) 92.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (e) Suppose the supply voltage is provided by an aging battery.168.. Explain why.g. Determine the value of C2 such that the gain of the circuit at 10 MHz is only 2 below its maximum (i.. How much can VCC fall while the gain of the circuit degrades by only 5? 94. (c) Compute the voltage gain of the circuit at 10 MHz.167 93. Unfortunately. 5. determine the input impedance of the circuit at 10 MHz. (b) Select the value of C1 such that it operates as nearly a short circuit (e. Predicting an output impedance of about 1 k for the stage shown in Fig. This ensures that C1 acts as a short circuit at all frequencies of interest. 2006] June 30.g. (d) With the proper value of C2 found in (c). V CC = 2.168 (a) Determine the bias conditions of Q1 .169.5 V 10 k Ω 1 kΩ Vout Q1 V in C1 P Figure 5. (One approach is to insert a resistor in series with Vin and adjust its value until VP =Vin or Vout =Vin drops by a factor of two. 1 nF.cls v. 5. 5 Bipolar Ampliﬁers (a) Using the . VN =VX is far from 0. 2007 at 13:42 280 (1) 280 Chap. (d) Determine the input impedance of the circuit at 10 MHz. determine the bias conditions of Q1 and verify that it operates in the active region. (b) Running an ac analysis. V CC = 2. Consider the self biased stage shown in Fig.166. e. a student constructs the circuit depicted in Fig. (c) Plot jVout =Vin j as a function of frequency for several values of C2 .5. 5. where VX represents an ac source with zero dc value. Which one of the two circuits is less sensitive to supply variations? .167. 1 F.. choose the value of C1 such that jVP =Vin j 0:99 at 1 MHz.op command. for C2 = 1 F). jVP =Vin j 0:99) at 10 MHz.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The ampliﬁer shown in Fig.170 employs an emitter follower to drive a 50frequency of 100 MHz. 2007 at 13:42 281 (1) Sec. 5. C2 .5 V 10 k Ω 1 kΩ 281 V in C1 1 kΩ Vout Q1 Figure 5. 5. and C3 if each one is to degrade the gain by less than 1. V CC = 2. (b) Determine the minimum acceptable value of C1 .5 Chapter Summary V CC = 2.cls v.169 95. (c) What is the signal attenuation of the emitter follower? Does the overall gain increase if RG2 is reduced to 100 ? Why? .5 V 2 kΩ 600 Ω load at a V in C1 2 kΩ X Q1 R E1 C2 Q2 200 Ω C3 50Ω Vout Figure 5. 2006] June 30.170 (a) Determine the value of RE 1 such that Q2 carries a bias current of 2 mA.

g.) We therefore observe that a “channel” of free electrons may be created at the interface between the insulator and the piece of silicon. (Even though doped with acceptors. we utilize the models to study MOS ampliﬁer topologies. 2007 at 13:42 282 (1) 6 Physics of MOS Transistors Today’s ﬁeld of microelectronics is dominated by a type of device called the metal-oxidesemiconductor ﬁeld-effect transistor (MOSFET). In Chapter 7. The key point here is that the density of electrons in the channel varies with V1 . What happens if a potential difference is applied as shown in Fig. an insulator (“dielectric”). metal) plate. Illustrated in Fig. we begin with a simple geometry consisting of a conductive (e. seeking models that prove useful in circuit design. Conceived in the 1930s but ﬁrst realized in the 1960s. memory chips containing billions of transistors. MOSFETs (also called MOS devices) offer unique properties that have led to the revolution of the semiconductor industry. as evident from Q = CV . Figure 6 illustrates the sequence of concepts covered in this chapter.. where C denotes the capacitance between the two plates. from the piece of silicon.1(a).cls v. we analyze the structure and operation of MOSFETs. the p-type silicon does contain a small number of electrons. 282 . e. Our treatment of MOS devices and circuits follows the same procedure as that taken in Chapters 2 and 3 for pn junctions. 2006] June 30. and a doped piece of silicon.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. “mirroring” any charge deposited on the top plate. potentially serving as a good conductive path if the electron density is sufﬁciently high. it attracts negative charge. Operation of MOSFETs MOS Structure Operation in Triode Region Operation in Saturation I/V Characteristics MOS Device Models Large−Signal Model Small−Signal Model PMOS Devices Structure Models 6. and sophisticated communication circuits providing tremendous signal processing capability.1 Structure of MOSFET Recall from Chapter 5 that any voltage-controlled current source can provide signal ampliﬁcation.g. 6. such a structure operates as a capacitor because the p-type silicon is somewhat conductive. In order to arrive at the structure of the MOSFET. This revolution has culminated in microprocessors having 100 million transistors. electrons. 6..1(b)? As positive charge is placed on the top plate. In this chapter. MOSFETs also behave as such controlled sources but their characteristics are different from those of bipolar transistors.

Figure 6. by reducing the thickness of the dielectric layer separating the two plates. thus ﬂowing primarily through the channel rather than through the entire body of silicon. depending on the voltages applied to the device.1(c). the term “ohmic” contact emphasizes bidirectional current ﬂow—as in a resistor.) This will serve our objective of building a voltage-controlled current source. 6.1 The ability of silicon fabrication technology to produce extremely thin but uniform dielectric layers (with thicknesses below 20 A today) has proven essential to the rapid advancement of microelectronic devices.2 These two terminals are called “source” (S) and “drain” (D) to indicate that the former can provide charge carriers and the latter can absorb them. two contacts are attached to the substrate through two heavily-doped n-type regions because direct connection of metal to the substrate would not produce a good “ohmic” contact.1 Conductive Plate Structure of MOSFET 283 Insulator V1 p−Type Silicon Channel of Electrons V1 V2 (a) (b) (c) Figure 6. either of these two terminals can drain the charge carriers from the other..2(b) for simplicity.cls v.2(a) reveals that the device is symmetric with respect to S and D. (b) operation as a capacitor. (The p-type counterpart is studied in Section 6. 2006] June 30. the value of C must be maximized. i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 (a) Hypothetical semiconductor device. as depicted in Fig. The dependence of the electron density upon V1 leads to an interesting property: if. The foregoing thoughts lead to the MOSFET structure shown in Fig. V1 can control the current by adjusting the resistivity of the channel. The dielectric layer sandwiched between the gate and the substrate plays a critical role in the performance of transistors and is created by growing silicon dioxide (or simply “oxide”) on top 1 The capacitance between two plates is given by A=t. the top conductive plate resides on a thin dielectric (insulator) layer. Thus. Called the “gate” (G).2.4. 2007 at 13:42 283 (1) Sec. 2 Used to distinguish it from other types of contacts such as diodes. A is the area of each plate. The gate plate must serve as a good conductor and was in fact realized by metal (aluminum) in the early generations of MOS technology. let us consider the types of materials used in the device. and t is the dielectric thickness.e. Before delving into the operation of the MOSFET. Figure 6. for example. this transistor operates with electrons rather than holes and is therefore called an n-type MOS (NMOS) device. (Note that the current prefers to take the path of least resistance. As explained in Section 6. it was discovered that noncrystaline silicon (“polysilicon” or simply “poly”) with heavy doping (for low resistivity) exhibits better fabrication and physical properties. Equation Q = CV suggests that. 6. with n-type source/drain and p-type substrate. (c) current ﬂow as a result of potential difference. wherein the arrow signiﬁes the source terminal. 6.” To allow current ﬂow through the silicon material.) We draw the device as shown in Fig. However.2(a) as a candidate for an amplifying device. to achieve a strong control of Q by V . which itself is deposited on the underlying p-type silicon “substrate. . where is the “dielectric constant” (also called the “permitivity”).2(c) depicts the circuit symbol for an NMOS transistor. we allow a current to ﬂow from left to right through the silicon material. 6. today’s MOSFETs employ polysilicon gates.

proper operation of the transistor requires that these junctions remain reverse-biased. of the silicon area. Polysilicon S/D Diffusion Oxide n+ t ox = 18 A Length 90 nm n+ p −substrate Oxide−Silicon Interface Figure 6. 6.3). Figure 6. The oxide thickness is denoted by tox . We should also remark that these regions in fact form diodes with the p-type substrate (Fig.” referring to a fabrication method used in early days of microelectronics. (c) circuit symbol. only the depletion region capacitance associated with the two diodes must be taken into account.2 (a) Structure of MOSFET. The outline is shown in Fig. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6. As explained later. 2006] June 30. 2007 at 13:42 284 (1) 284 Chap. The n+ regions are sometimes called source/drain “diffusion.cls v.3 Typical dimensions of today’s MOSFETs. .3 shows some of the device dimensions in today’s state-of-the-art MOS technologies. 6 Physics of MOS Transistors Source Gate Conductive Plate Drain n+ p −substrate Insulator (a) G S D n+ G n + n + S D (c) p −substrate (b) Figure 6. (b) side view. 6.2 Operation of MOSFET This section deals with a multitude of concepts related to MOSFETs.4.

While we stated in Section 6. 6.2.” VTH .2 suggests that the MOSFET may conduct current between the source and drain if a channel of electrons is created by making the gate voltage sufﬁciently positive. Since the MOSFET contains three terminals. As VG increases from zero. Our analysis will indeed conﬁrm these conjectures while revealing other subtle effects in the device.1(b) that. Fortunately. We must study the dependence of this current upon the gate voltage (e. we do not show this connection in the diagrams. since the density of electrons in the channel must increase as VG 3 The substrate acts as a fourth terminal. This circuit does not appear particularly useful but it gives us a great deal of insight. 6.cls v.5(c)].1 and 6. Thus. Let us ﬁrst consider the arrangement shown in Fig.4 Note that the device still acts as a capacitor—positive charge on the gate is mirrored by negative charge in the substrate—but no channel of mobile charge is created yet. Can the source-substrate and drain-substrate junctions carry current in this mode? To avoid this effect. Moreover.g. whereas the depletion region in a pn junction consists of two areas of negative and positive ions on the two sides of the junction. Resting on top of the oxide. and need not be supplied by the substrate.5(a). 4 Note that this depletion region contains only one immobile charge polarity. The gate potential at which the channel begins to appear is called the “threshold voltage. no current can ﬂow from the source to the drain. the substrate itself is also tied to zero. but we ignore that for now.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. in reality. 2007 at 13:42 285 (1) Sec. thereby exposing negative ions and creating a depletion region [Fig. These concepts become clearer below. 6. if VG becomes sufﬁciently positive. What happens as VG increases? To mirror the charge on the gate. forming a conductive channel [Fig. more negative ions are exposed and the depletion region under the oxide becomes deeper. another phenomenon precedes the formation of the channel. for a constant gate voltage). We say the MOSFET is on. the positive charge on the gate repels the holes in the substrate. the only current of interest is that ﬂowing between the source and the drain. free electrons are attracted to the oxide-silicon interface.2 Operation of MOSFET 285 Qualitative Analysis Formation of Channel MOSFET as Resistor Channel Pinch−off I/V Characteristics I/V Characteristics Channel Charge Density Dain Current Triode and Saturation Regions Analog Properties Transconductance Channel−Length Modulation Other Properties Body Effect Subthreshold Conduction Velocity Saturation Figure 6. with the (low-frequency) gate current being zero. Note that the gate terminal draws no (low-frequency) current as it is insulated from the channel by the oxide. where the source and drain are grounded and the gate voltage is varied. 6..1 that electrons are attracted to the interface. and falls in the range of 300 mV to 500 mV.5(b)]. Note that the electrons are readily provided by the n+ source and drain regions. for a constant drain voltage) and upon the drain voltage (e. the gate remains insulated from other terminals and simply operates as a plate of a capacitor. we expect that the magnitude of the current can be controlled by the gate voltage. It is interesting to recognize that the gate terminal of the MOSFET draws no (low-frequency) current. We say the MOSFET is off.. as VG rises. Recall from Fig. For simplicity.3 we may face many combinations of terminal voltages and currents. Does this mean the transistor never turns on?! Fortunately.g. MOSFET as a Variable Resistor The conductive channel between S and D can be viewed as a resistor. . 6. 6. 6. ensuring that these diodes are not forwardbiased. 2006] June 30. the positive charge on the gate must be mirrored by negative charge in the substrate. Furthermore.4 Outline of concepts to be studied.1 Qualitative Analysis Our study of the simple structures shown in Figs.

2007 at 13:42 286 (1) 286 Chap. Solution A MOSFET can form a voltage-controlled attenuator along with a resistor as shown in Fig.1 In the vicinity of a wireless base station. . 2006] June 30.6. Example 6. Since V cont v in RM R1 v out Figure 6.7 Use of MOSFET to adjust signal levels. (b) formation of depletion region. possibly “saturating” the circuits and prohibiting proper operation. such a voltage-dependent resistor proves extremely useful in analog and digital circuits. the signal received by a cellphone may become very strong. G S D Figure 6. (c) formation of channel.7. becomes more positive (why?). 6 Physics of MOS Transistors VG n+ p −substrate (a) VG n+ VG n+ p −substrate Depletion Region (b) VG n+ n+ p −substrate n+ Free Electrons Negative Ions (c) Figure 6. Conceptually illustrated in Fig.5 (a) MOSFET with gate voltage. Devise a variable-gain circuit that lowers the signal level as the cellphone approaches the base station. 6.6 MOSFET viewed as a voltage-dependent resistor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.cls v. the value of this resistor changes with the gate voltage.

8(a) and examine the drain current (= source current).8(c). (b) ID -VG characteristic. 6. VD is varied while VG remains constant.8(b). then ID 0 [Fig.8 (a) MOSFET with gate and drain voltages. We now raise the drain voltage as shown in Fig.” Exercise What happens to RM if the channel length is doubled? In the arrangement of Fig. (c) ID -VD characteristic. 6. The slope of the characteristic is equal to 1=Ron .5 ID VG VD VD VTH (a) (b) VG n+ p −substrate n+ ID ID VD VG ID VG ID ID VD VG R on −1 ID VG3 VG2 VG1 VD VD (c) (d) Figure 6.2 Operation of MOSFET 287 vout = R1 . no channel exists.8(b)].8(c).1) the output signal becomes smaller as Vcont falls because the density of electrons in the channel decreases and RM rises. 6. 6. no current ﬂows between S and D because the two terminals are at the same potential. the source-drain path may act as a simple resistor. yielding the ID -VD characteristic shown in Fig. 6. . 2007 at 13:42 287 (1) Sec. Each view provides valuable insight into the operation of the transistor. vin RM + R1 (6.5(c). If VG VTH .cls v. MOSFETs are commonly utilized as voltage-dependent resistors in “variable-gain ampliﬁers. and ID = 0 regardless of the value of VD . 5 The term “on-resistance” always refers to that between the source and drain as no resistance exists between the gate and other terminals. where Ron denotes the “on-resistance” of the transistor. 6. if VG VTH . the device is off. (d) ID -VD characteristics for various gate voltages . 6. On the other hand. In fact. Our brief treatment of the MOS I/V characteristics thus far points to two different views of the operation: in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. VG is varied while VD remains constant whereas in Fig.

6 Physics of MOS Transistors How does the characteristic of Fig. (c) ID -VG characteristics for different oxide thicknesses. the semiconductor industry has continued to reduce the gate oxide thickness. Exercise The current conduction in the channel is in the form of drift. (b) ID -VD characteristics for different channel lengths. For this reason. Recall from Chapter 2 that charge ﬂow in semiconductors occurs by diffusion or drift. Similarly. yielding a greater slope. 6.8(d). the resulting characteristics strengthen the notion of voltage-dependent resistance. 6. 6. Thus. How does the oxide thickness. producing less drain current for a given gate voltage [Fig. and (b) different oxide thicknesses. ID exhibits a smaller slope as a function of VD [Fig. 6. 6.9(c)] or drain voltage [Fig. Example 6. the capacitance between the gate and the silicon substrate decreases. so does the on-resistance. It is therefore desirable to minimize the channel length so as to achieve large drain currents—an important trend in the MOS technology development.9(b)]. The following example reinforces the concepts studied thus far.6 Thus. 2006] June 30. respectively.8(b) change if VG increases? The higher density of electrons in the channel lowers the on-resistance.2 Sketch the ID -VG and ID -VD characteristics for (a) different channel lengths. the current results from the drift of charge. affect the I-V characteristics? As tox increases. ID ID Solution VTH (a) VG (b) VD ID ID VTH (c) VG (d) VD Figure 6. The ID -VG and ID -VD characteristics shown in Figs. we note that a given voltage results in less charge on the gate and hence a lower electron density in the channel. As the channel length increases. 6. How about the transport mechanism in a MOSFET? Since the voltage source tied to the drain creates an electric ﬁeld along the channel.9(a)]. the drain current begins with lesser values as the channel length increases [Fig. from Q = CV . the device suffers from a higher on-resistance.8(b) and (c).9 (a) ID -VG characteristics for different channel lengths. (d) ID -VD characteristics for different oxide thicknesses.cls v. Consequently. If the mobility falls at high 6 Recall that the resistance of a conductor is proportional to the length. . play a central role in our understanding of MOS devices. 2007 at 13:42 288 (1) 288 Chap. tox .9(d)]. Depicted in Fig. 6. for VG VTH .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

producing a high drain current [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.. Illustrated in Fig. We may then surmise that W must be maximized.10(a)]. In reality.11(a). 2007 at 13:42 289 (1) Sec. so does the width of the channel. however. the transistor operates as a current source if the drain voltage is sufﬁciently positive. 6. what can we say about the on-resistance as the temperature goes up? While both the length and the oxide thickness affect the performance of MOSFETs. only the former is under the circuit designer’s control.). 6. we make two observations: (1) to form a channel.10(b). . the potential difference between the gate and the oxide-silicon interface must exceed VTH . Another MOS parameter controlled by circuit designers is the width of the transistor. Thus. and since the potential at the oxide-silicon interface rises from the source to the drain. the potential difference between 7 Recall that the resistance of a conductor is inversely proportional to the cross section area. which itself is equal to the product of the width and thickness of the conductor. a wider device can be viewed as two narrower transistors in parallel. (c) equivalence to devices in parallel. but we must also note that the total gate capacitance increases with W . then the voltage at each point along the channel with respect to ground increases as we go from the source towards the drain. on the other hand.10(c)]. this effect arises from the gradual voltage drop along the channel resistance. it can be speciﬁed in the “layout” of the transistor. (2) if the drain voltage remains higher than the source voltage. 6.cls v. From another perspective. is deﬁned during fabrication and remains constant for all transistors in a given generation of the technology.e. t ox W n+ L (a) n+ ID W ID W S G D VTH VG VD (b) (c) Figure 6. 6. We therefore observe that “lateral” dimensions such as L and W can be chosen by circuit designers whereas “vertical” dimensions such as tox cannot. Channel Pinch-Off Our qualitative study of the MOSFET thus far implies that the device acts as a voltage-dependent resistor if the gate voltage exceeds VTH . possibly limiting the speed of the circuit. the width of each device in the circuit must be chosen carefully. To understand this effect. 2006] June 30. 6. How does the gate width impact the I-V characteristics? As W increases. The latter.2 Operation of MOSFET 289 temperatures. thus lowering the resistance between the source and the drain7 and yielding the trends depicted in Fig. Since the gate voltage is constant (because the gate is conductive but carries no current in any direction).10 (a) Dimensions of a MOSFET (W and L are under circuit designer’s control. (b) ID characteristics for different values of W . i. the dimension perpendicular to the length [Fig.

. they experience the high electric ﬁeld in the depletion region surrounding the drain junction and are rapidly swept to the drain terminal. once the electrons reach the end of the channel.12(a)]. we write C = WCox to account for the width of the transistor [Fig. Denoting the gate capacitance per unit area by Cox (expressed in F/m2 or fF/m2 ). we have V = VGS .) It follows that Q = WCox VGS . then Q is the desired charge density. VTH because no mobile charge exists for VGS VTH . we conclude that. we note that if C is the gate capacitance per unit length and V the voltage difference between the gate and the channel. VG .13(a)]. 6. 6. Note that the source-substrate and drain-substrate junctions carry no current.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6 Physics of MOS Transistors the gate and the oxide-silicon interface decreases along the x-axis [Fig. and the MOSFET acts as a constant current source—similar to a bipolar transistor in the forward active region.” From Q = CV .2) . 6. 2007 at 13:42 290 (1) 290 Chap. free electrons) per unit length. We say the gate-substrate potential difference is not sufﬁcient at x = L to attract electrons and the channel is “pinched off” From these observations. What happens if VD rises even higher than VG . the drain voltage no longer affects the current signiﬁcantly. falling to a minimum at x = L.12(c). VD VTH .12(b)]. 6. VTH ? Since V x now goes from 0 at x = 0 to VD VG . Nonetheless. as shown in the next section. then the channel ceases to exist near the drain. VG VD n+ ID Potential = V G Difference < VG n+ x = VG − VD Gate−Substrate Potential Difference V (x ) VG VD − VG L L x x (a) (b) Figure 6. 2006] June 30.11 (a) Channel potential variation. VTH : (6.2. (Hereafter. Does this mean the transistor cannot conduct current? No. The density of electrons in the channel follows the same trend.2 Derivation of I/V Characteristics With the foregoing qualitative study. we denote both the gate and drain voltages with respect to the source.cls v. Channel Charge Density Our derivations require an expression for the channel charge (i.11(b)]. Moreover. 6. the device still conducts: as illustrated in Fig. VTH at x = L. also called the “charge density.e. The device therefore contains no channel between L1 and L. if the drain voltage is high enough to produce [Fig. the voltage difference between the gate and the substrate falls to VTH at some point L1 L [Fig. (b) gate-substrate voltage difference along the channel. we can now formulate the behavior of MOSFETs in terms of their terminal voltages. 6.

and the charge density falls as we go from the source to the drain. VTH . Eq. 6.2 Operation of MOSFET VG n+ Electrons 291 ID > V TH n+ VD VG VD VG n+ n+ ID VD V TH VG VD (a) VG n+ n+ ID VD E n+ 0 (b) L1 L x (c) Figure 6.3) Drain Current What is the relationship between the mobile charge density and the current? Consider a bar of semiconductor having a uniform charge density (per unit length) equal to Q and carrying a current I (Fig.11(a) that the channel voltage varies along the length of the transistor. (b) variation of length with drain voltage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30. 6. noting that V x goes from zero to VD if the channel is not pinched off. V x . Note from Chapter 2 that (1) I is given by the total charge that passes through the cross section of the bar in one second. 2007 at 13:42 291 (1) Sec.13 Illustration of capacitance per unit length. then the charge enclosed in v meters along the bar passes through the cross .12 (a) Pinchoff. (c) detailed operation near the drain. 6.2) is valid only near the source terminal. 6. Note that Q is expressed in coulomb/meter. (6.14.15). As shown in Fig. Thus. and (2) if the carriers move with a velocity of v m/s. Now recall from Fig. where the channel potential remains close to zero. (6. W n+ n+ Figure 6. we denote the channel potential at x by V x and write Qx = WCox VGS .

n E.3). V x . = +n dV . 2006] June 30. we write ID = WCox VGS .6) Interestingly.6). Since the charge enclosed in v meters is equal to Q v .15 Relationship between charge velocity and current. As explained in Chapter 2. and (6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 292 (1) 292 Chap.8) That is. V x .4). we obtain v = . dx (6. 0 x section in one second.4) where dV=dx denotes the derivative of the voltage at a given point. V x . 2 ID = 1 n Cox W 2VGS . Combining (6.cls v. our immediate need is to ﬁnd an expression for ID in terms of the terminal voltages.9) . 6 Physics of MOS Transistors VG n+ n+ ID VD V (x ) L dx Figure 6. To this end. VTH and dV=dx is independent of x. VTH VDS . I = Q v.14 Device illustration for calculation of drain current. VDS : 2 L (6.7) Z x=L x=0 ID dx = Z V x=VDS V x=0 n Cox W VGS . While it is possible to solve the above differential equation to obtain V x in terms of ID (and the reader is encouraged to do that). we have v meters W t = t1 t = t1 + 1 s L h x1 V1 x x1 V1 x Figure 6. VTH n dV x : dx (6. (6.5) (6. (6. since ID must remain constant along the channel (why?). VTH dV: (6. V x and dV=dx must vary such that the product of VGS .

8) to emphasize the choice of W and L. First.10(c)]. 6. Second. VTH 2 . As VGS increases. ID varies parabolically with VDS (Fig. Exercise What happens to the above plots if tox is halved? . reaching a maximum of ID 1 2 µ n C ox W (VGS − V TH ( L 2 Figure 6. VTH . and a larger W=L (called the device “aspect ratio”) is equivalent to placing more transistors in parallel [Fig.max2 VGS1 − V TH VGS1 VGS2 − V TH VGS3 − V TH VDS Figure 6.17 MOS characteristics for different gate-source voltages.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the ratio remains unchanged but the gate capacitance increases. Illustrated in Fig. for a constant VGS .max and VGS . VTH . 2007 at 13:42 293 (1) Sec.g. a higher gate oxide capacitance leads to a larger electron density in the channel for a given gate-source voltage. 6. so do ID.max = 1 n Cox W VGS . It is common to write W=L as the ratio of two values e.max3 VGS2 I D. 6. While only the ratio appears in many MOS equations. the individual values of W and L also become critical in most cases. 2006] June 30.cls v. VGS − V TH VDS at VDS = VGS .16).max4 Parabola ID.2 Operation of MOSFET 293 We now examine this important equation from different perspectives to gain more insight. 5 m=0:18 m (rather than 27. the linear dependence of ID upon n . 6. and W=L is to be expected: a higher mobility yields a greater current for a given drain-source voltage. if both W and L are doubled.16 Parabolic ID -VDS characteristic. ID I D. the characteristics exhibit maxima that follow a parabolic shape themselves because ID.17. For example. Plot the ID -VDS characteristics for different values of VGS . Cox . VTH 2 2 L (6.3 Solution VGS3 I D.10) Example 6.max VGS ..

i. 6. (6.2.4 A cordless telephone incorporates a single antenna for reception and transmission. 8 Some cellphones operate in the same manner. In fact. 6. VTH VDS . In particular.12) Figure 6. 6.12) suggests that the on-resistance can be controlled by the gate-source voltage.1. Solution The system is designed such that the phone receives for half of the time and transmits for the other half. . Example 6. Thus. the antenna is alternately connected to the receiver and the transmitter in regular intervals. the device can operate as an electronic switch.cls v. An electronic antenna switch is therefore necessary here. VTH .18 Detailed characteristics for small VDS . Eq. L 1 (6.e.. Ron = 1. As predicted in Section 6. the equivalent on-resistance is given by VDS =ID : ID n Cox W VGS . (6.11) Ron = From another perspective. V : n Cox L GS TH (6. if VDS 2VGS . 2007 at 13:42 294 (1) 294 Chap.19 Role of antenna switch in a cordless phone. 6 Physics of MOS Transistors The nonlinear relationship between ID and VDS reveals that the transistor cannot generally be modeled as a simple linear resistor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Explain how the system must be conﬁgured.17 can be approximated by straight lines having different slopes (Fig.g.18).9) reduces to: exhibiting a linear ID -VDS behavior for a given VGS . 2006] June 30. for VGS = VTH . at small VDS (near the origin).8 Receiver Receiver Transmitter Transmitter Figure 6. However.19). every 20 ms (Fig.. the parabolas in Fig. ID VGS2 VGS1 VDS VDS VGS3 ID VGS3 VGS2 VGS1 W V . e.

e. each of which receives and transmits signals. 2007 at 13:42 295 (1) Sec. The following example illustrates this point. (6. we obtain from Eq.15) (Since wide transistors introduce substantial capacitance in the signal path. we wish to ensure R on V out 50 Ω R on R ant Transmitter V in Figure 6.13) Ron 5:6 : Setting VGS to the maximum value. this choice of W=L may still attenuate high-frequency signals.resistor.20. Solution As depicted in Fig.20 Signal degradation due to on-resistance of antenna switch.2 Operation of MOSFET 295 Exercise Some systems employ two antennas. 6.12). determine the minimum required aspect ratio of the switch. n Cox = 100 A=V2 . The circuit designer must therefore maximize W=L and VGS .g.4. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 6. it is desirable to achieve a low on-resistance for MOS switches. (6. the switch connecting the transmitter to the antenna must negligibly attenuate the signal.cls v. 2006] June 30. VDD .14) W 1276: L (6.5 In the cordless phone of Example 6. by no more than 10. Vout 0:9 Vin and hence (6. How many switches are needed? In most applications..) . and VTH = 0:4 V. If VDD = 1:8 V. Assume the antenna can be modeled as a 50.

6. MOSFETs are sometimes called “square-law” devices to emphasize the relationship between ID and the overdrive. recall that Eqs.. 6 Physics of MOS Transistors Exercise What W=L is necessary if VDD drops to 1. 2007 at 13:42 296 (1) 296 Chap. W ID = 1 n Cox L VGS . with the triode and saturation regions in MOSFETs appearing similar to saturation and forward active regions in bipolar transistors. We also use the term “deep triode region” for VDS transistor operates as a resistor. The I-V characteristic of Fig. the drain current reaches “saturation.12 that the channel experiences pinch-off if VDS = VGS . Thus. Called the “overdrive voltage. In particular. Consequently. we hereafter denote L1 with L.16) Note that the upper limits correspond to the channel pinch-off point.8) must encompass only the channel. 6.10) if we assume L1 L. VTH rather than VDS . i. Z x=L x=0 1 ID dx = Z V x=VGS . from x = 0 to x = L1 in Fig. VTH plays a key role in MOS circuits. further increase in VDS simply shifts the pinch-off point slightly toward the drain. becomes constant for VDS VGS .” .8) are valid only where channel charge exists.17) a result independent of VDS and identical to ID. VTH dV: (6. where the parabola).12(b). 2 1 (6. implying that the current begins to fall for VDS VGS .e. respectively.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6. VTH (the rising section of the 2VGS .21 Overall MOS characteristic. (6.” the quantity VGS .2 V? Triode and Saturation Regions Equation (6. V x .7) and (6.VTH V x=0 n Cox W VGS . It follows that the integration in (6. and be modiﬁed to ID 1 2 µ n C ox W (VGS − V TH ( L 2 Triode Region Saturation Region VGS − V TH VDS Figure 6.9) expresses the drain current in terms of the device terminal voltages. VTH .21 resembles that of bipolar devices. 2006] June 30. the integral on the right hand side is evaluated up to VGS . VTH 2 . To understand why. 6. 9 Also called the “linear region.21). VTH (Fig. It is unfortunate that the term “saturation” refers to completely different regions in MOS and bipolar I-V characteristics. In reality. recall from Fig. We say the device operates in the “triode region”9 if VDS VGS .max in (6. VTH . VTH . Also.cls v. For the sake of brevity.” that is.

6.23 Simple MOS circuit. Let us assume M1 is saturated and proceed. Note that the gate-drain potential difference suits this purpose and we need not compute the gatesource and gate-drain voltages separately. what is the change in the drain voltage? VDD = 1. 2006] June 30. VTH suggests that the device can act as a voltage-controlled current source.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V RD ID X M1 W = 2 L 0.18) (6.22 Illustration of triode and saturation regions based on the gate and drain voltages. Assume n Cox = 100 A=V2 and VTH If the gate voltage increases by 10 mV.cls v.18 5 kΩ Example 6.22 to determine the region of operation. RD ID = 0:8 V: (6. Furthermore. 6. VTH > VTH ID 1 2 µ n C ox W (VGS − V TH ( L 2 Saturated Triode Region Saturation Region M1 VGS − V TH VDS (a) (b) Figure 6. 6. It is unclear a priori in which region M1 operates.17). Calculate the bias current of M1 in Fig. Since VGS = 1 V. 1V Figure 6.2 Operation of MOSFET 297 We employ the conceptual illustration in Fig. the square-law dependence of ID upon VGS . VTH 2 L = 200 A: We must check our assumption by calculating the drain potential: (6. 2007 at 13:42 297 (1) Sec. Exhibiting a “ﬂat” current in the saturation region. a MOSFET can operate as a current source having a value given by (6.6 = 0:4 V. Solution 1 ID = 2 n Cox W VGS .19) VX = VDD .20) (6.21) .23.

2006] June 30. The illustration in Fig. the drain voltage must fall to VGS .cls v. If VGS increases by 1 mV. Assume VTH = 0:4 V. VTH region. most transistors have the same dimensions and hence the same IS . (4) The gate of MOSFETs draws no bias current.27) (6.10 Determine the value of W=L in Fig.28) 10 New generations of MOSFETs suffer from gate “leakage” current. then ID = 206:7 A. but by less than VTH . 6. (1) A bipolar transistor with VBE = VCE resides at the edge of the active region whereas a MOSFET approaches the edge of saturation if its drain voltage falls below its gate voltage by VTH . ID = VDDR VDS D = 240 A: Since ID scales linearly with W=L. W j = 240 A 2 L max 200 A 0:18 4 = 02::18 : ID = 248:04 A.7 Solution = 0:6 V for M1 to enter the triode (6. (2) Bipolar devices exhibit an exponential IC -VBE characteristic while MOSFETs display a squarelaw dependence. the former provide a greater transconductance than the latter (for a given bias current).22 therefore indicates that M1 indeed operates in saturation.25) . (3) In bipolar circuits. 6. Example 6.23) Fortunately. 6 Physics of MOS Transistors The drain voltage is lower than the gate voltage. 2007 at 13:42 298 (1) 298 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.26) (6. whereas in MOS circuits. the aspect ratio of each device may be chosen differently to satisfy the design requirements. With VGS = +1 V.01 V. .24) (6. If the gate voltage increases to 1. but we neglect this effect here. M1 is still saturated. That is. The 34-mV change in VX reveals that the circuit can amplify the input.23 that places M1 at the edge of saturation and calculate the drain voltage change for a 1-mV change at the gate. lowering VX to (6. Exercise What choice of RD places the transistor at the edge of the triode region? It is instructive to identify several points of contrast between bipolar and MOS devices.22) VX = 0:766 V: (6. That is. (6.

VTH = Thus.2 Operation of MOSFET 299 changing VX by VX = ID RD = 4:02 mV: The voltage gain is thus equal to 4.32) VGS = .29) (6. VTH = VDD . L and hence VGS .33) Exercise Calculate the value of VGS if mun Cox = 100 A=V2 and VTH = 0:4 . 2006] June 30.1 + 1 + 2RD VDD n Cox W L RD n Cox W L q + VTH : (6.8 Figure 6.24 if M1 must remain saturated. 6. VDD = 1.30) Exercise Repeat the above example if RD is doubled. At the edge of saturation.1 + 1 + 2RD VDD n Cox W L RD n Cox W L q : (6. VTH 2 .31) VGS .17) (6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. (6. 2007 at 13:42 299 (1) Sec. R2D n Cox W VGS . . 6. VTH gives Solution = VDS = VDD .02 in this case. Calculate the maximum allowable gate voltage in Fig.8 V RD ID V GS X M1 W = 2 L 0. VGS .24 Simple MOS circuit.18 5 kΩ Example 6. RD ID : Substituting for ID from (6.

3 Channel-Length Modulation In our study of the pinch-off effect. 2007 at 13:42 300 (1) 300 Chap. (6. 2006] June 30. Unlike the Early effect in bipolar devices (Chapter 4). Called “channel-length modulation” and illustrated in Fig. this linear dependence of ID upon VDS still provides a great deal of insight into the circuit design implications of channel-length modulation.26 Channel-length modulation.12(b) varies with VDS to some extent. we assume hand side of (6.9 11 Since different MOSFETs in a circuit may be sized for different ’s. 6.25. the base width of bipolar devices cannot be adjusted by the circuit designer. 6. A MOSFET carries a drain current of 1 mA with VDS = 0:5 V in saturation.34) 1 ID = 2 n Cox W VGS . VTH 2 1 + VDS . What is the device output impedance? Example 6. 6 Physics of MOS Transistors 6.26).) L1 ID ID L2 VDS VDS Figure 6. 6. this phenomenon yields a larger drain current as VDS increases because ID 1=L1 in Eq.1 . we do not deﬁne a quantity similar to the Early voltage here. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. This is because is inversely proportional to L: for a longer channel.11 (By contrast.cls v. Similar to the Early effect in bipolar devices.25 Variation of ID in saturation region. L where is called the “channel-length modulation coefﬁcient. the value of L1 in Fig.” While only an approximation.17) by a corrective term: L is constant.2. Determine the change in ID if VDS rises to 1 V and = 0:1 V. VDS To account for channel-length modulation. 6.25. we observed that the point at which the channel vanishes in fact moves toward the source as the drain voltage increases. channel-length modulation results in a ﬁnite output impedance given by the inverse of the ID -VDS slope in Fig. yielding a constant Early voltage for all transistors in a given technology. but multiply the right (6. In other words. ID 1 2 µ n C ox W (VGS − V TH ( L 2 VGS − V TH Figure 6. the relative change in L (and hence in ID ) for a given change in VDS is smaller (Fig.17). the amount of channel-length modulation is under the circuit designer’s control.

In Eqs.43) . VTH 2 1 + VDS1 2 L 1 C W V . 6. ID (6.36) V ID2 = ID1 1 + VDS2 : 1+ DS 1 With ID1 (6. 2007 at 13:42 301 (1) Sec.05 V. V 2 1 + V ID2 = 2 n ox L GS TH DS 2 and hence (6. calculate ID and rO in Example 6.10 Solution 1=L.1 . The same effect was observed for bipolar current sources in Chapters 4 and 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Thus.37) = 1 mA. VDS1 = 0:5 V.35) and (6.39) (6. 1 + V ID2 = ID1 1 + VDS2 DS 1 = 1:024 mA: That is. and = 0:1 V. VDS2 = 1 V. Assuming Example 6.2 Operation of MOSFET 301 Solution We write ID1 = 1 n Cox W VGS . yielding an output impedance of (6.35) (6.42) = 24 A and rO = 20:84 k : (6. ID2 = 1:048 mA: The change in ID is therefore equal to 48 A.38) rO = VIDS D = 10:42 k : (6.cls v. W=L remains unchanged but drops to 0.36).1 . 2006] June 30. (6.9 if both W and L are doubled.41) (6.40) Exercise Does W affect the above results? The above example reveals that channel-length modulation limits the output impedance of MOS current sources.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (6. These results can be understood intuitively if we view the doubling of W=L and ID as shown in Fig. thereby doubling the transconductance. it is as if two transistors carrying equal currents are placed in parallel. Also.46) is more frequently used because ID may be predetermined by power dissipation requirements. if VGS remains constant and the width of the device is doubled. dividing (6. Among these three expressions for gm . then both IC and gm increase linearly. we have concluding that (1) gm is linearly proportional to W=L for a given VGS . VTH . VTH .46) indicates that gm is also doubled. and (2) gm is linearly proportional to VGS . L (6. If the bipolar transistor width is increased while VBE remains constant. these dependencies prove critical in understanding performance trends of MOS devices and have no counterpart in bipolar transistors. 2007 at 13:42 302 (1) 302 Chap.46) pI D for I gm = V 2.1. 6. The reader can show that this trend applies to any type of transistor. VTH for a given ID .47) GS TH revealing that (1) gm is linearly proportional to ID for a given VGS .27.11 . and (2) gm is proportional to a given W=L. we obtain gm = n Cox W VGS . a MOS transistor can be characterized by its transconductance: @I gm = @V D : GS (6. and (2) gm is inversely proportional to VGS .DV . VTH from (6. Moreover. Using Eq. Eq.45) by (6. 6. substituting for VGS . how do gm and VGS ID are doubled? Example 6. Indeed. Summarized in Table 6. VTH for a given W=L.17). (1) gm is proportional to W=L for a given ID . VTH . Moreover.17) suggests that the overdrive remains constant.17) for the saturation region.45) That is. For a MOSFET operating in saturation. (6. (6.2.12 . VTH change if both W=L and Equation (6.44) This quantity serves as a measure of the “strength” of the device: a higher value corresponds to a greater change in the drain current for a given change in VGS . Solution 12 There is some resemblance between the second column and the behavior of gm = IC =VT .17) gives p gm = 2n Cox W ID : L r (6. 6 Physics of MOS Transistors Exercise What output impedance is achieved if W and L are quadrupled and ID is halved.cls v. (6. .4 MOS Transconductance As a voltage-controlled current source. 2006] June 30.

modern MOS devices experience velocity saturation even with drain-source voltages as low as 1 V. 2007 at 13:42 303 (1) Sec. carrier mobility degrades.49) . (6. the I/V characteristics no longer follow the square-law behavior.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 m). Exercise How do gm and VGS . Owing to their very short channels (e. 6.1.2 under velocity saturation conditions. then the device experiences less velocity . VTH and no dependence on L. we have ID = vsat Q = vsat WCox VGS . 2006] June 30. Denoting the saturated velocity by vsat . while VDS remains constant.2.3 that at high electric ﬁelds.27 Equivalence of a wide MOSFET to two in parallel. 0.13 saturation and (6. V GS V GS V DS V DS Figure 6.1 Various dependencies of gm .48) (6.49) is not accurate. As a result.g. VTH : Interestingly.2 Operation of MOSFET 303 W Constant L VGS − V TH Variable g g m m W Variable L VGS − V TH Constant g g m m W Variable L VGS − V TH Constant g g m m ID VGS − V TH ID W L W L 1 VGS − V TH Table 6.5 Velocity Saturation Recall from Section 2. if L is increased substantially. eventually leading to a constant velocity. 13 Of course.2. VTH change if only W and ID are doubled? 6. Let us examine the derivations in Section 6. ID now exhibits a linear dependence on VGS This section can be skipped in a ﬁrst reading.cls v..

53) Solution = 0:5 V. An interesting phenomenon occurs as the source-substrate potential difference departs from zero: the threshold voltage of the device changes. Figure 6. 2007 at 13:42 304 (1) 304 Chap.28 illustrates this case. we have assumed that both the source and the substrate (also called the “bulk” or the “body”) are tied to ground.4 V and 0. Eq. VTH increases.28 Body effect. Substrate Contact VS p+ p −substrate n+ VG VD n+ VG VS VD Figure 6. We denote the voltage difference between the source and the substrate (the bulk) by VSB . The source terminal is tied to a potential VS with respect to ground while the substrate is grounded through a p+ contact. 6.28. Called “body effect. j2 F j. and VTH 0 = 0:6 V. 6 Physics of MOS Transistors We also recognize that @I gm = @V D GS = vsat WCox.cls v.6 Other Second-Order Effects (6. VSB Example 6. 6.12 = 100 A=V2 . if the source terminal rises to a positive voltage while the substrate is at zero. VG = VD = 1:4 V.51) Body Effect In our study of MOSFETs. a quantity independent of L and ID . n Cox W=L = 50. and and F are p technology-dependent parameters having typical values of 0.50) (6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. assume VS = 0:5 V.” this phenomenon is formulated as VTH = VTH 0 + j2 F + VSB j . Since the source-body voltage. In the circuit of Fig.4 V. 2006] June 30.2. For example. In particular. However.14 The dashed line added to the transistor symbol indicates the substrate terminal. and F yield (6. Determine the drain current if = 0.52) where VTH 0 denotes the threshold voltage with VSB = 0 (as studied earlier). this condition need not hold in all circuits. . as the source becomes more positive with respect to the substrate. then the source-substrate junction remains reverse-biased and the device still operates properly.52) and the typical values for VTH = 0:698 V: 14 The p+ island is necessary to achieve an “ohmic” contact with low resistance. p p (6. respectively. (6.

13 Solution Noting that the device operates in saturation (why?). 6.58) . 2006] June 30. the gate remains an open circuit to represent the zero gate current. (6. VTH 2 2 L = 102 A: (6. We neglect body effect in this book. and the device conducts a small current even for VGS VTH .57) In the saturation region. For VDS VGS . formation of the channel is a gradual effect.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.29(b).55) Exercise Sktech the drain current as a function of VS as VS goes from zero to 1 V. 6. Finally. 6.29(c)]. the model must reﬂect the triode region. Sketch the drain current of M1 in Fig.9) and (6. with VG = VD . Body effect manifests itself in some analog and digital circuits and is studied in more advanced texts. Note that ID does depend on VDS and is therefore not an ideal current source.3 MOS Device Models 305 Also. 6. 2007 at 13:42 305 (1) Sec. but it can still incorporate a voltage-controlled current source as depicted in Fig. we now develop models that can be used in circuit analysis and design. 6. VDS Triode Region 2 L ID = 1 n Cox W VGS . VTH VDS .1 Large-Signal Model For arbitrary voltage and current levels.56) (6. Called “subthreshold conduction.cls v. In reality.34) to express the device behavior: 2 ID = 1 n Cox W 2VGS . the device operates in saturation (why?) and hence ID = 1 n Cox W VG . VTH . lending itself to the model shown in Fig. Assume = 0. Subthreshold Conduction The derivation of the MOS I/V characteristic has assumed that the transistor abruptly turns on as VGS reaches VTH . In all three cases.30(a) versus V1 as V1 varies from zero to VDD . the transistor can be viewed as a voltage-controlled resistor [Fig. Example 6. we must resort to Eqs.3 MOS Device Models With our study of MOS I/V characteristics in the previous section. VTH . VS .” this effect has become a critical issue in modern MOS devices and is studied in more advanced texts.54) (6.29(a). VTH 2 L (6. we write 1 ID = 2 n Cox W VGS . the transistor acts as a voltage-controlled current source. VTH 2 1 + VDS Saturation Region 2 L (6. if VDS 2VGS .3. 6.

VGS drops to VTH .30(b). M1 is tied to a voltage equal to 1.5 V and VDD = 2 6. owing to body effect. large-signal models can be reduced to linear.cls v. VTH . 2006] June 30. small-signal representations. Exercise Repeat the above example if the gate of V. 6 Physics of MOS Transistors ID S µ n C ox W (VGS − V TH ( (1+ λVDS ) L 2 (a) VGS < V TH VDS > VGS − V TH G D G 1 2 2 µ n C ox W [ 2 (VGS − V TH ( VDS + VDS ] L VGS < V TH VDS >> 2 (VGS − V TH ( D 1 W (V µ n C ox GS − V TH ( L ID S R on = S (b) (c) Figure 6. 2007 at 13:42 306 (1) 306 VGS < V TH VDS < VGS − V TH G D 1 2 Chap. VTH varies with V1 if the substrate is tied to ground. (b) triode region. V1 . VTH 2 : 2 L (6.30 (a) Simple MOS circuit.59) At V1 = 0. The development . = 1 n Cox W VDD . (c) deep triode region. If V1 reaches VDD . The drain current thus varies as illustrated in Fig. turning the transistor off. Note that. (b) variation of ID with V1 . VGS falls and so does ID .3. VDD M1 V1 VDD − V TH V1 (a) (b) ID Figure 6. the nonlinear. As V1 rises.29 MOS models for (a) saturation region.2 Small-Signal Model If the bias currents and voltages of a MOSFET are only slightly disturbed by signals. VGS = VDD and the device carries maximum current.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.

cls v. 2006] June 30. 6. where iD = gm vGS and the gate remains open.e. we draw the basic model as in Fig.. (b) inclusion of channel-length modulation.31 (a) Small-signal model of MOSFET. . Viewing the transistor as a voltage-controlled current source. variation of iD with vDS .31(a). 2007 at 13:42 307 (1) Sec. we add a resistor as in Fig. i. 6. 6. Of particular interest to us in this book is the small-signal model for the saturation region.3 MOS Device Models 307 of the model proceeds in a manner similar to that in Chapter 4 for bipolar devices. To represent channel-length modulation.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.31(b): G D G D v GS g v GS m v GS g v GS m rO S (a) S (b) Figure 6.

60) (6. yielding (6.5 mA. Example 6. the denominator of (6.61) can be approximated as ID .62) A MOSFET is biased at a drain current of 0. W=L = 10.63) (6. If n Cox = 0:1 V. gm rO . calculate its small-signal parameters. and Solution We have gm = 2nCox W ID L = 11 : k Also. (Chapter 4) is equal to 20 for this choice of device dimensions and bias current.1 rO = @V D DS (6.61) 1 =1 W V .14 = 100 A=V2 . @I . Exercise Repeat the above example if W=L is doubled. .1 .64) 1 rO = I = 20 k : D (6. r (6.65) (6.66) This means that the intrinsic gain. V 2 : 2 n Cox L GS TH 1 rO I : D Since channel-length modulation is relatively small.

15 Figure 6. approaching saturation as VD falls to VG . For V1 Solution = VDD . The transistor operates in the triode region if the drain voltage is near the source potential. (b) PMOS circuit symbol. The channel now consists of holes and is formed if the gate voltage is below the source potential by one threshold voltage. Assume VDD = 2:5 V and jVTH j = 0:5 V. 6. (c) illustration of triode and saturation regions based on gate and drain voltages.33 Simple PMOS circuit. 6. Indeed. S D S G D (a) Triode Region Edge of Saturation (b) Saturation Region p+ n −substrate p+ ID > VTHP VTHP < VTHP (c) Figure 6. Figure 6. VTH = VG + jVTH j.32(b). the reader may wonder if a p-type counterpart exists for MOSFETs.32(c) conceptually illustrates the gate-drain voltages G required for each region of operation.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. VGS = 0 and M1 is off.jVTH j. As V1 falls and approaches VDD . determine the region of operation of M1 as V1 goes from VDD to zero. VGS VTH . to turn the device on. Following the conventions used for bipolar devices. VDD M1 V1 1V Example 6. That is.32 (a) Structure of PMOS device. 6. where VTH itself is negative. 2007 at 13:42 308 (1) 308 Chap. the gate-source . as illustrated in Fig. 6 Physics of MOS Transistors 6. with the source terminal identiﬁed by the arrow and placed on top to emphasize its higher potential.33.32(a). 2006] June 30. we draw the PMOS device as in Fig. In the circuit of Fig.4 PMOS Transistor Having seen both npn and pnp bipolar transistors. changing the doping polarities of the substrate and the S/D areas results in a “PMOS” device.

2007 at 13:42 309 (1) Sec. At this point.32(b). we express ID in the saturation region as 1 ID.4 PMOS Transistor 309 potential is negative enough to form a channel of holes.jVTH j = +2 V while VD = +1 V.tri j = 1 p Cox W 2jVGS j . VDS : 2 L The small-signal model of PMOS transistor is identical to that of NMOS devices (Fig. the small-signal equivalent appears as depicted in Fig. (c) smallsignal model of (b). 6. L where is multiplied by a negative sign. Solution For the NMOS version. 6.e.cls v. determine the small-signal resistances RY . For V1 = +1 V . jVTH j = 0:5 V. i. . . a negative carries little physical meaning. Example 6.34 (a) Diode-connected NMOS and PMOS devices.15 In the triode region. As V1 goes below 0. VGS becomes more negative and the transistor current rises. 2006] June 30. jVTH jjVDS j .16 For the conﬁgurations shown in Fig. VTH 2 1 .tri = . M1 is at the edge of the triode region. 6. Using the current direction shown in Fig. VDS .sat j = 2 p Cox W jVGS j .70) 2 jID.67) 1 2 ID. the transistor enters the triode region further.69) (6.31). As V1 falls further. both equations can be expressed in terms of absolute values: (6.34(a). Assume 6= 0. jVTH j2 1 + jVDS j L (6. M1 is saturated [Fig. 6.32(c)]. RX VDD M2 M1 RY vx iX v1 gm1v 1 r O1 vY iY v1 RX and M2 gm2v 1 r O2 (a) (b) (c) Figure 6.34(b). 2 p Cox W VGS ..BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) small-signal model of (a). VDS : L Alternatively. The following example illustrates this point.34)]. VTH VDS .sat = . 6.72) 15 To make this equation more consistent with that of NMOS devices [Eq. (6.71) vX = gm1 vX + rO1 i1 X (6.68) 1 jID. we can deﬁne itself to be negative and express ID as 1=2p Cox W=LVGS VTH 2 1 + VDS . yielding RX = vX i X (6. The voltage and current polarities in PMOS devices can prove confusing.5 V. turning the device on. 2 p Cox W 2VGS . 6. (6. VG = VDD . But.

16 The ﬁrst Intel microprocessor.73) RY = vY iY vY = gm2 vY + rO1 i1 Y 1 jjr : =g O2 m2 (6.44(a)].5 CMOS Technology Is it possible to build both NMOS and PMOS devices on the same wafer? Figures 6. the above structure requires more complex processing than simple NMOS or PMOS devices. In fact. was realized in NMOS technology. thereby accommodating PMOS transistors.76) In both cases. Called “complementary MOS” (CMOS) technology. For example. 2007 at 13:42 310 (1) 310 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.46) indicates that the transconductance of a PMOS device is lower for a given drain current.cls v. a local n-type substrate can be created in a p-type substrate.2(a) and 6. In analogy with their bipolar counterparts [Fig. many signiﬁcant advantages of complementary devices eventually made CMOS technology dominant and NMOS technology obsolete. the 4004.74) (6.34(c) and write (6. the structures shown in Fig. we draw the equivalent as shown in Fig. Eq.16 and the higher cost of CMOS processes seemed prohibitive. 6. (6. 6. the ﬁrst few generations of MOS technology contained only NMOS transistors. As illustrated in Fig.34(a) are called “diode-connected” devices and act as two-terminal components: we will encounter many applications of diode-connected devices in Chapters 9 and 10. Fortunately. NMOS Device B S PMOS Device D S G G D B p+ n+ n+ p+ n −well p+ n+ p −substrate Figure 6.35 CMOS technology. PMOS devices exhibit a poorer performance than NMOS transistors. We therefore prefer to use NMOS transistors wherever possible.32(a) reveal that the two require different types of substrate. an “n-well” encloses a PMOS device while the NMOS transistor resides in the p-substrate. Owing to the lower mobility of holes (Chapter 2).35. 4. . 6 Physics of MOS Transistors = g 1 jjrO1 : m1 For the PMOS version. However.75) (6. the small-signal resistance is equal to 1=gm if ! 0. 2006] June 30. 6.

tem MOSFETs enter the “saturation region” if channel pinch-off occurs.cls v. leading to “pinch-off. 6.6 Comparison of Bipolar and MOS Devices Having studied the physics and operation of bipolar and MOS transistors. If the drain-source voltage is small. mobile carriers are attracted to the oxide-silicon interface and a channel is formed. MOSFETs operating in the saturation region behave as current sources and ﬁnd wide application in microelectronic circuits.7 Chapter Summary A voltage-dependent current source can form an ampliﬁer along with a load resistor. Table 6.2 shows some of the important aspects of each device. The gate controls the current ﬂow from the source to the drain. The gate draws nearly zero current because an insulating layer separates it from the substrate.. A MOSFET consists of a conductive plate (the “gate”) atop a semiconductor substrate and two junctions (“source” and “drain”) in the substrate.2 Comparison of bipolar and MOS transistors. reducing the effective length of the device. That is. A measure of the small-signal performance of voltage-dependent current sources is the “transconductance. the channel ceases to exist near the drain. Note that the exponential IC -VBE dependence of bipolar devices accords them a higher transconductance for a given bias current. the device is not an ideal current source.e. 2007 at 13:42 311 (1) Sec. the drain voltage is less than one threshold below the gate volatge.6 Comparison of Bipolar and MOS Devices 311 6. VTH and pinch-off occurs. VTH 2 . W=L. the device operates a voltage-dependent resistor. As the drain voltage rises. 2006] June 30. MOSFETs are electronic devices that can operate as voltage-dependent current sources. Beyond a certain gate-source voltage (the “threshold voltage”).” deﬁned as the change in the output current divided by the change in . If the drain voltage reaches one threshold below the gate voltage. a depletion region is formed in the substrate under the gate area. the drain current is proportional to VGS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As the drain voltage exceeds VGS . In this region. the drain end of the channel begins to move toward the source. 6. the charge density near the drain falls.” this effect leads to variation of drain current in the saturation region. The current is also proportional to the device aspect ratio. i. the drain current is a function of VGS and VDS . Bipolar Transistor Exponential Characteristic Active: VCB > 0 Saturation: VCB < 0 Finite Base Current Early Effect Diffusion Current − MOSFET Quadratic Characteristic Saturation: VDS < VGS − V TH Triode: VDS > VGS − V TH Zero Gate Current Channel−Length Modulation Drift Current Voltage−Dependent Resistor Table 6. Called “channel-length modulation. In this region.” MOSFETs operate in the “triode” region if the drain voltage is more than one threshold below the gate voltage. As the gate voltage rises. we can now compare their properties.

4) indicates that the charge density and carrier velocity must change in opposite directions if the current remains constant. 5. Problems = 200 A=V2 . If both devices operate M1 W L W L M2 M eq Figure 6.36 2. (a) Sketch the electron density in the channel as a function of x.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Referring to Fig. .7) to obtain an expression for V x.77) Suppose the values of n Cox and W=L are unknown. An NMOS device carries 1 mA with VGS . calculate VDS and W=L. In the following problems.6 mA with VGS . Is it possible to determine these quantities by applying different values of VGS . (6. where the charge density approaches zero? Calculate the total charge stored in the channel of an NMOS device if Cox = 10 fF=m2 . L = 0:1 m. solve Eq. VTH = 1 V. (b) Sketch the local resistance of the channel (per unit length) as a function of x. . Operation across different regions and/or with large swings exempliﬁes “large-signal behavior. 6. 4. 2006] June 30. VTH and VDS and measuring ID ? 7. assume n Cox p Cox = 100 A=V2 . 6 Physics of MOS Transistors the input voltage. 2007 at 13:42 312 (1) 312 Chap. unless otherwise stated. Two identical MOSFETs are placed in series as shown in Fig.cls v. Plot both V x and dV=dx as a function of x for different values of W or VTH . explain intuitively why this combination is equivalent to a single transistor. and VGS . VTH VDS . W = 5 m. The transconductance of MOSFETs can be expressed by one of three equations in terms of the bias voltages and currents.VTH = 0:8 V. as resistors. 6.11 and assuming that VD 0. 1 VDS : L 2 (6. and VTH = 0:4 V for NMOS devices and devices. 6. the MOSFET can be represented by a small-signal model consisting of a linear voltage-dependent current source and an output resistance.36. Assuming ID is constant. 3. What are the width and length of Meq ? Consider a MOSFET experiencing pinch-off near the drain.0:4 V for PMOS 1. If the device operates in the triode region. NMOS and PMOS transistors are fabricated on the same substrate to create CMOS technology. Equation (6. The drain current of a MOSFET in the triode region is expressed as 2 ID = n Cox W VGS .” If the signal swings are sufﬁciently small. Meq . Assume VDS = 0. The small-signal model is derived by making a small change in the voltage difference between two terminals while the the other voltages remain constant. How can this relationship be interpreted at the pinch-off point.VTH = 0:6 V and 1. The small-signal models of NMOS and PMOS devices are identical.

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313

8. Compute the transconductance of a MOSFET operating in the triode region. Deﬁne gm = @ID =@VGS for a constant VDS . Explain why gm = 0 for VDS = 0. 9. An NMOS device operating with a small drain-source voltage serves as a resistor. If the supply voltage is 1.8 V, what is the minimum on-resistance that can be achieved with W=L = 20? 10. We wish to use an NMOS transistor as a variable resistor with Ron = 500 at VGS = 1 V and Ron = 400 at VGS = 1:5 V. Explain why this is not possible. 11. For a MOS transistor biased in the triode region, we can deﬁne an incremental drain-source resistance as

rDS;tri = @V DS

@ID ,1

:

(6.78)

Derive an expression for this quantity. 12. It is possible to deﬁne an “intrinsic time constant” for a MOSFET operating as a resistor:

= Ron CGS ;

(6.79)

where CGS = WLCox . Obtain an expression for and explain what the circuit designer must do to minimize the time constant. 13. In the circuit of Fig. 6.37, M1 serves as an electronic switch. If Vin 0, determine W=L

VG M1 RL

V in

Vout

Figure 6.37

14.

15. 16. 17.

such that the circuit attenuates the signal by only 5. Assume VG = 1:8 V and RL = 100 . In the circuit of Fig. 6.37, the input is a small sinusoid superimposed on a dc level: Vin = V0 cos !t + V1 , where V0 is on the order of a few millivolts. (a) For V1 = 0, obtain W=L in terms of RL and other parameters so that Vout = 0:95Vin . (b) Repeat part (a) for V1 = 0:5 V. Compare the results. For an NMOS device, plot ID as a function of VGS for different values of VDS . In Fig. 6.17, explain why the peaks of the parabolas lie on a parabola themselves. Advanced MOS devices do not follow the square-law behavior expressed by Eq. (6.17). A somewhat better approximation is:

ID = 1 n Cox W VGS , VTH ; 2 L

(6.80)

where is less than 2. Determine the transconductance of such a device. 18. For MOS devices with very short channel lengths, the square-law behavior is not valid, and we may instead write:

ID = WCox VGS , VTH vsat ;

(6.81)

where vsat is a relatively constant velocity. Determine the transconductance of such a device.

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314

Chap. 6

Physics of MOS Transistors

M1

0.5 V 0.5 V

2V 1.5 V

M1

0.5 V

2V 1.5 V

M1

0.5 V

0.5 V

(a)

(b)

(c)

M1

1.5 V 0.5 V 1.5 V

M1

0.5 V

M1

0.5 V

0.5 V

(d)

(e)

(f)

M1

0.5 V

M1

1V

M1

0.5 V

0.5 V

(g)

(h)

(i)

Figure 6.38

19. Determine the region of operation of M1 in each of the circuits shown in Fig. 6.38. 20. Determine the region of operation of M1 in each of the circuits shown in Fig. 6.39.

M1

1V 1V

M1

(a) 1V 0.2 V 1V 0.2 V 0.2 V

(b)

M1

M1

0.7 V

(c)

(d)

Figure 6.39

21. Two current sources realized by identical MOSFETs (Fig. 6.40) match to within 1, i.e., 0:99ID2 ID1 1:01ID2. If VDS1 = 0:5 V and VDS2 = 1 V, what is the maximum tolerable value of ? 22. Assume = 0, compute W=L of M1 in Fig. 6.41 such that the device operates at the edge of saturation. 23. Using the value of W=L found in Problem 22, explain what happens if the gate oxide thickness is doubled due to a manufacturing error. 24. In the Fig. 6.42, what is the minimum allowable value of VDD if M1 must not enter the

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Chapter Summary

315

I D1 M1 VB

I D2 M2

Figure 6.40

VDD = 1.8 V RD

1 kΩ

1V

M1

Figure 6.41

VDD = 1.8 V RD

500 Ω

1V

M 1 W = 10 L 0.18

Figure 6.42

**triode region? Assume = 0. 25. In Fig. 6.43, derive a relationship among the circuit parameters that guarantees M1 operates
**

VDD RD M1 W L

Figure 6.43

26. 27. 28.

29.

at the edge of saturation. Assume = 0. Compute the value of W=L for M1 in Fig. 6.44 for a bias current of I1 . Assume = 0. Calculate the bias current of M1 in Fig. 6.45 if = 0. Sketch IX as a function of VX for the circuits shown in Fig. 6.46. Assume VX goes from 0 to VDD = 1:8 V. Also, = 0. Determine at what value of VX the device changes its region of operation. Assuming W=L = 10=0:18 = 0:1 V,1 , and VDD = 1:8 V, calculate the drain current of M1 in Fig. 6.47.

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Physics of MOS Transistors

VDD = 1.8 V M1 RS

Figure 6.44

VDD RD M1 W L

Figure 6.45

VDD = 1.8 V M1 M1 VX

(a) 1V 1V

IX

IX M1 VX

IX M1 VX

IX

VX

(b)

(c)

(d)

Figure 6.46

1 kΩ

VDD RD M1

Figure 6.47

**30. In the circuit of Fig. 6.48, W=L = 20=0:18 and = transistor at the edge of saturation?
**

RD

5 kΩ

0:1 V,1 . What value of VB places the

VDD = 1.8 V

M1 VB

Figure 6.48

31. An NMOS device operating in saturation with 1=50 . (a) Determine W=L if ID = 0:5 mA. (b) Determine W=L if VGS , VTH = 0:5 V. (c) Determine ID if VGS , VTH = 0:5 V.

= 0 must provide a transconductance of

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317

32. Determine how the transconductance of a MOSFET (operating in saturation) changes if (a) W=L is doubled but ID remains constant. (b) VGS , VTH is doubled but ID remains constant. (c) ID is doubled but W=L remains constant. (d) ID is doubled but VGS , VTH remains constant. 33. If = 0:1 V,1 and W=L = 20=0:18, construct the small-signal model of each of the circuits shown in Fig. 6.49.

VDD = 1.8 V RD

100

VDD = 1.8 V RD

5 kΩ

VDD = 1.8 V

1 mA

Ω

M1

1V

M1

M1

(a)

(b)

(c)

VDD = 1.8 V M1

2 kΩ

VDD = 1.8 V M1

0.5 mA

(d)

(e)

Figure 6.49

34. The “intrinsic gain” of a MOSFET operating in saturation is deﬁned as gm rO . Derive an expression for gm rO and plot the result as a function of ID . Assume VDS is constant. 35. Assuming a constant VDS , plot the intrinsic gain, gm rO , of a MOSFET (a) as a function of VGS , VTH if ID is constant. (b) as a function of ID if VGS , VTH is constant. 36. An NMOS device with = 0:1 V,1 must provide a gm rO of 20 with VDS = 1:5 V. Determine the required value of W=L if ID = 0:5 mA. 37. Repeat Problem 36 for = 0:2 V,1 . 38. Construct the small-signal model of the circuits depicted in Fig. 6.50. Assume all transistors operate in saturation and 6= 0. 39. Determine the region of operation of M1 in each circuit shown in Fig. 6.51. 40. Determine the region of operation of M1 in each circuit shown in Fig. 6.52. 41. If = 0, what value of W=L places M1 at the edge of saturation in Fig. 6.53? 42. With the value of W=L obtained in Problem 41, what happens if VB changes to +0:8 V? 43. If W=L = 10=0:18 and = 0, determine the operating point of M1 in each circuit depicted in Fig. 6.54. 44. Sketch IX as a function of VX for the circuits shown in Fig. 6.55. Assume VX goes from 0 to VDD = 1:8 V. Also, = 0. Determine at what value of VX the device changes its region of operation. 45. Construct the small-signal model of each circuit shown in Fig. 6.56 if all of the transistors operate in saturation and 6= 0.

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318

VDD RD Vout M2 VB V in M1

(a)

Chap. 6

VDD RD Vout V in M2

(b)

**Physics of MOS Transistors
**

VDD RD Vout V in M1 M2

(c)

M1

**VDD VDD V in M1 Vout M2 VB V in M2
**

(e)

RD Vout M1

(d)

Figure 6.50

M1

2V

2V

M1

0.3 V

0.3 V

M1

0.3 V

1V 0.6 V

M1

(a) Figure 6.51

(b)

(c)

(d)

46. Consider the circuit depicted in Fig. 6.57, where M1 and M2 operate in saturation and exhibit channel-length modulation coefﬁcients n and p , respectively. (a) Construct the small-signal equivalent circuit and explain why M1 and M2 appear in “parallel.” (b) Determine the small-signal voltage gain of the circuit.

SPICE Problems In the following problems, use the MOS models and source/drain dimensions given in Appendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD , respectively. 47. For the circuit shown in Fig. 6.58, plot VX as a function of IX for 0 IX 3 mA. Explain the sharp change in VX as IX exceeds a certain value. 48. Plot the input/output characteristic of the stage shown in Fig. 6.59 for 0 Vin 1:8 V. At what value of Vin does the slope (gain) reach a maximum? 49. For the arrangements shown in Fig. 6.60, plot ID as a function of VX as VX varies from 0 to 1.8 V. Can we say these two arrangements are equivalent?

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Sec. 6.7

Chapter Summary

M1

1.5 V 0.5 V 0.9 V

319

M1

0.9

(a)

(b)

M1

0.9 V 0.4 V 1V

M1

0.9 V 0.4 V

Figure 6.52

(c)

(d)

VDD = 1.8 V M1

1V 2 kΩ

Figure 6.53

VDD = 1.8 V M1

500 Ω

VDD = 1.8 V M1

1 kΩ

VDD = 1.8 V

1 kΩ

M1

(a)

(b)

(c)

Figure 6.54

VDD = 1.8 V M1 VX IX

1V

VDD = 1.8 V M1 IX VX

(a)

(b)

VDD = 1.8 V M1 IX M1 VX IX VX

(c)

(d)

Figure 6.55

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320 (1)

320

Chap. 6

**Physics of MOS Transistors
**

V in

VDD RS V in M1 Vout RD V in

VDD M1 Vout RD M2

Vb

M1 Vout R1 M2 RD

(c)

(a)

(b)

VDD V in M1 Vout R1 RD M2 V in

VDD R2 Vout M1 M2 R1

(d)

(e)

Figure 6.56

VDD M2 V in M1 Vout

Figure 6.57

M1

0.9 V

2 0.18

VX

IX

Figure 6.58

VDD = 1.8 V

500 Ω

M1 V in

10 0.18

Vout

Figure 6.59

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321 (1)

Sec. 6.7

Chapter Summary

IX M1

0.9 V 5 0.36

321

IX M1 VX

0.9 V 5 0.36 5 0.36

VX

M2

(a)

(b)

Figure 6.60

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322

Chap. 6

Physics of MOS Transistors

50. Plot IX as a function of VX for the arrangement depicted in Fig. 6.61 as VX varies from 0 to 1.8 V. Can you explain the behavior of the circuit?

IX M1

0.9 V 5 0.18

M1

5 0.18

VX

Figure 6.61

**51. Repeat Problem 50 for the circuit illustrated in Fig. 6.62.
**

VDD = 1.8 V M1

5 0.18

IX M1

5 0.18

VX

Figure 6.62

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323 (1)

7

CMOS Ampliﬁers

Most CMOS ampliﬁers have identical bipolar counterparts and can therefore be analyzed in the same fashion. Our study in this chapter parallels the developments in Chapter 5, identifying both similarities and differences between CMOS and bipolar circuit topologies. It is recommended that the reader review Chapter 5, speciﬁcally, Section 5.1. We assume the reader is familiar with concepts such as I/O impedances, biasing, and dc and small-signal analysis. The outline of the chapter is shown below.

General Concepts Biasing of MOS Stages Realization of Current Sources MOS Amplifiers Common−Source Stage Common−Gate Stage Source Follower

7.1 General Considerations

7.1.1 MOS Ampliﬁer Topologies Recall from Section 5.3 that the nine possible circuit topologies using a bipolar transistor in fact reduce to three useful conﬁgurations. The similarity of bipolar and MOS small-signal models (i.e., a voltage-controlled current source) suggests that the same must hold for MOS ampliﬁers. In other words, we expect three basic CMOS ampliﬁers: the “common-source” (CS) stage, the “common-gate” (CG) stage, and the “source follower.” 7.1.2 Biasing Depending on the application, MOS circuits may incorporate biasing techniques that are quite different from those described in Chapter 5 for bipolar stages. Most of these techniques are beyond the scope of this book and some methods are studied in Chapter 5. Nonetheless, it is still instructive to apply some of the biasing concepts of Chapter 5 to MOS stages. Consider the circuit shown in Fig. 7.1, where the gate voltage is deﬁned by R1 and R2 . We assume M1 operates in saturation. Also, in most bias calculations, we can neglect channel-length modulation. Noting that the gate current is zero, we have

VX = R R2 R VDD : 1+ 2

(7.1)

323

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324 (1)

324

Chap. 7

VDD = 1.8 V

4 kΩ

CMOS Ampliﬁers

R1 Y

RD ID

X

10 k Ω

M1 R2 RS

1 kΩ

Figure 7.1 MOS stage with biasing.

Since VX

= VGS + ID RS ,

R2 V = V + I R : R1 + R2 DD GS D S ID = 1 n Cox W VGS , VTH 2 : 2 L

(7.2)

Also, (7.3)

Equations (7.2) and (7.3) can be solved to obtain ID and VGS , either by iteration or by ﬁnding ID from (7.2) and replacing for it in (7.3):

R 1 1 W 2 2 R1 + R2 VDD , VGS RS = 2 n Cox L VGS , VTH : r s

(7.4)

That is

**R 2 VGS = ,V1 , VTH + V1 , VTH 2 , VTH + R 2+2R V1 VDD ; 1 2 RV = ,V1 , VTH + V12 + 2V1 R 2 +DD , VTH ; 1 R2
**

where

(7.5) (7.6)

V1 =

This value of VGS can then be substituted in (7.2) to obtain ID . Of course, VY must exceed VX , VTH to ensure operation in the saturation region. Determine the bias current of M1 in Fig. 7.1 assuming VTH = 0:5 V, n Cox = 100 A=V2 , W=L = 5=0:18, and = 0. What is the maximum allowable value of RD for M1 to remain in saturation?

: n Cox W RS L

1

(7.7)

Example 7.1

Solution

We have

VX = R R2 R VDD 1+ 2 = 1:286 V:

(7.8) (7.9)

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Sec. 7.1

General Considerations

325

With an initial guess VGS = 1 V, the voltage drop across RS can be expressed as VX , VGS = 286 mV, yielding a drain current of 286 A. Substituting for ID in Eq. (7.3) gives the new value of VGS as

v u VGS = VTH + u t

= 0:954 V:

n Cox W L

2ID

(7.10) (7.11)

Consequently,

, ID = VX R VGS S = 332 A;

and hence

(7.12) (7.13)

VGS = 0:989 V:

(7.14)

This gives ID = 297 A. As seen from the iterations, the solutions converge more slowly than those encountered in Chapter 5 for bipolar circuits. This is due to the quadratic (rather than exponential) ID -VGS dependence. We may therefore utilize the exact result in (7.6) to avoid lengthy calculations. Since V1 = 0:36 V,

VGS = 0:974 V

and

(7.15)

, ID = VX R VGS S = 312 A:

The maximum allowable value of RD is obtained if VY

(7.16) (7.17)

RD = VDDI , VY D = 3:25 k :

**= VX , VTH = 0:786 V. That is,
**

(7.18) (7.19)

Exercise

What is the value of R2 that places M1 at the edge of saturation?

In the circuit of Example 7.1, assume M1 is in saturation and RD = 2:5 k and compute (a) the maximum allowable value of W=L and (b) the minimum allowable value of RS (with W=L = 5=0:18). Assume = 0.

Example 7.2

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Chap. 7

CMOS Ampliﬁers

(a) As W=L becomes larger, M1 can carry a larger current for a given VGS . With RD and VX = 1:286 V, the maximum allowable value of ID is given by

Solution

= 2:5 k

(7.20) (7.21)

ID = VDD , VY RD = 406 A:

The voltage drop across RS is then equal to 406 mV, yielding VGS = 1:286 V , 0:406 V = 0:88 V. In other words, M1 must carry a current of 406 A with VGS = 0:88 V:

**1 ID = 2 n Cox W VGS , VTH 2 L 406 A = 50 A=V2 W 0:38 V2 ; L
**

thus,

(7.22) (7.23)

A. Since

(b) With

W=L = 5=0:18, the minimum allowable value of RS gives a drain current of 406

W = 56:2: L

(7.24)

v u VGS = VTH + u t

= 1:041 V;

n Cox W L

2ID

(7.25) (7.26)

the voltage drop across RS is equal to VX

**, VGS = 245 mV. It follows that RS = VX , VGS I
**

= 604 :

D

(7.27) (7.28)

Exercise

Repeat the above example if VTH

= 0:35 V.

The self-biasing technique of Fig. 5.22 can also be applied to MOS ampliﬁers. Depicted in Fig. 7.2, the circuit can be analyzed by noting that M1 is in saturation (why?) and the voltage drop across RG is zero. Thus,

**ID RD + VGS + RS ID = VDD :
**

Finding VGS from this equation and substituting it in (7.3), we have

(7.29)

1 ID = 2 n Cox W VDD , RS + RD ID , VTH 2 ; L

(7.30)

VTH RS + RD + 4 1 n Cox L 3 7 2 W 5 ID + VDD . VTH = 0: (7. It follows that 2 2 RS + RD 2 ID .31) gives ID = 556 A: To reduce ID to 278 A.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V RD 20 k Ω 1 kΩ Example 7. where channel-length modulation is neglected.3 = 0:5 V.3 if n Cox = 100 A=V2 . VTH What value of RD is necessary to reduce ID by a factor of two? VDD = 1.2 Self-biased MOS stage. 2007 at 13:42 327 (1) Sec.3 Example of self-biased MOS stage. 2 6VDD . 7.33) Exercise Repeat the above example if VDD drops to 1. 7.31) for RD : (7.18 200 Ω Figure 7.2 V. Solution Equation (7. and = 0. W 5 M 1 L = 0.31) Calculate the drain current of M1 in Fig.1 General Considerations VDD RD RG ID M1 RS 327 Figure 7. we solve (7.cls v. 2006] June 30.32) RD = 2:867 k : (7. .

2 Common-Source Stage 7. If channel-length modulation is neglected.g R . with the input applied to the gate and the output sensed at the drain. m D vin a result similar to that obtained for the common emitter stage in Chapter 5. That is.5(a). the basic CS stage is similar to the common-emitter topology.4(b)] draws current from VDD to node Y . 7. the small-signal model in Fig.4 (a) NMOS device operating as a current source. (b) PMOS device operating as a current source. From another perspective. 6. (c) PMOS topology not operating as a current source. i. If = 0. VDD RD ID V in Input Applied to Gate (a) (b) v in Vout M1 Output Sensed at Drain v out v1 g v1 m RD Figure 7. and RD transforms the drain currents to the output voltage. For small signals. (b) small-signal mode. it draws current from node X to ground.4(c) and (d) do not operate as current sources because variation of VX or VY directly changes the gate-source voltage of each transistor.5(b) yields vin = v1 and vout = ..cls v. an NMOS device serves as a current source with one terminal tied to ground. 7.gm v1 RD . thus changing the drain current considerably.34.1. 7. (d) NMOS topology not operating as a current source. 2007 at 13:42 328 (1) 328 Chap. 7. 2006] June 30. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. NMOS or PMOS devices conﬁgured as shown in Figs.3 Realization of Current Sources MOS transistors operating in saturation can act as current sources. VDD X Vb M1 Y Y X Vb M2 VDD Vb Y Vb M1 X VDD M1 (a) (b) (c) (d) Figure 7. Speciﬁcally. (7. It is important to understand that only the drain terminal of a MOSFET can draw a dc current and still present a high impedance. these currents remain independent of VX or VY (so long as the transistors are in saturation).4(a). 7.5 (a) Common-source stage. On the other hand. revealing a small-signal impedance of only 1=gm (if = 0) rather than inﬁnity.1 CS Core Shown in Fig.34) . the small-signal model of these two structures is identical to that of the diode-connected devices in Fig. 7 CMOS Ampliﬁers 7. vout = . As illustrated in Fig.e. M1 converts the input voltage variations to proportional drain current changes.2. a PMOS transistor [Fig.

VDD = 1. VTH .4 (7. Solution We have gm = 2nCox W ID L 1 = 300 : Thus.35) concluding that if ID or RD is increased.2 Common-Source Stage 329 of p2TheCvoltage gain.6 if ID = 1 mA. RD ID VGS .41) v u VGS = VTH + u t = 1:1 V: n Cox W L 2ID (7. 2006] June 30. 2n Cox W ID RD . This concept is beyond the scope of this book.6 Example of CS stage. 2007 at 13:42 329 (1) Sec. L (7.36) RD ID VDD .39) Av = . Verify that M1 operates in saturation. VTH : Example 7. that is. 7.43) 1 It is possible to raise the gain to some extent by increasing W . .gmRD = 3:33: To check the operation region. Since gm n ox W=LID have r = Av = . we ﬁrst determine the gate-source voltage: (7.42) (7. 7.8 V RD 1 kΩ = v out v in 10 M1 W = L 0.1 For M1 to remain in saturation. we the CS stage is also limited by the supply voltage.18 Figure 7. so is the voltage drop across RD (= ID RD ). and = 0. VGS . but “subthreshold conduction” eventually limits the transconductance. (7.40) (7. VDD . n Cox 100 A=V2 .37) Calculate the small-signal voltage gain of the CS stage shown in Fig.38) (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. r (7. VTH = 0:5 V.cls v.

Rin = 1.7 Output impedance of CS stage. Since the gate current is zero (at low frequencies). RD ID = 0:8 V. 7. the current gain of a commonemitter stage is equal to . By contrast. respectively.47) (7.gmRD jjrO Rin = 1 Rout = RD jjrO : (7.44) a point of contrast to the CE stage (whose Rin is equal to r ). especially if RD is large. if RD is doubled with the intention of doubling Av . channel-length modulation may not be negligible. the device indeed operates in saturation and has a margin of 0. Since VGS .2 V with respect to the triode region. In practice. . revealing that iX v1 g v1 m rO RD vX Figure 7. The similarity between the small-signal equivalents of CE and CS stages indicates that the output impedance of the CS ampliﬁer is simply equal to Rout = RD : This is also seen from Fig. then M1 enters the triode region and its transconductance drops.46) (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 330 (1) 330 Chap. 7. v1 g v1 m (7. Av = . The high input impedance of the CS topology plays a critical role in many analog circuits. Exercise What value of VTH places M1 at the edge of saturation? Since the gate terminal of MOSFETs draws a zero current (at very low frequencies). Let us now compute the I/O impedances of the CS ampliﬁer.8 Effect of channel-length modulation on CS stage.cls v. (7. The small-signal model of CS topology is therefore modiﬁed as shown in Fig. we say the CS ampliﬁer provides a current gain of inﬁnity. 2006] June 30. in a similar manner. 7 CMOS Ampliﬁers The drain voltage is equal to VDD .45) iX RD vX Figure 7. channel-length modulation and the Early effect impact the CS and CE stages. VTH = 0:6 V.7.48) In other words.8. For example.

(b) gain as a function of device channel length. 7. R1 is tied between the gate and drain of 7. 7.gmrO : This highest voltage a p2 is theW=LI and r = gain that.2 Common-Source Stage 331 Assuming M1 operates in saturation. but recall from Chapter 6 that r 2 C WL n ox jAv j ID : L.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 v out v in M1 L (a) (b) Figure 7. 7. 7.9(b)]. VDD Av Example 7.cls v. allowing the use of (7.51) Consequently. 7. 2006] June 30. Solution The ideal current source presents an inﬁnite small-signal resistance. the trade-off between the voltage gain and the voltage headroom can be relaxed by replacing the load resistor with a current source. Having a constant gate-source voltage. Let us determine the small-signal gain and output impedance of the circuit. 2007 at 13:42 331 (1) Sec.2.1 : (7.49) gm = jAv j = pI L : D (7. The observations made in relation to Fig. we single transistor have n Cox D O ID .46) with RD = 1: Av = . Exercise Repeat the above example if a resistor of value M1 .10(a)]. Writing (7.2 CS stage With Current-Source Load As seen in the above example. M2 simply behaves as a resistor equal to its output impedance [Fig.9(a) and plot the result as a function of the transistor channel length while other parameters remain constant.1 r 2n Cox W can provide.10(b)] . determine the voltage gain of the circuit depicted in Fig.9 (a) CS stage with ideal current source as a load.4(b) therefore suggest the use of a PMOS device as the load of an NMOS CS ampliﬁer [Fig. 7.50) This result may imply that jAv j falls as L increases. jAv j increases with L [Fig.

gm1rO1 jjrO2 Rout = rO1 jjrO2 : Example 7. Equations (7. (b) small-signal model. such a topology exhibits only a moderate gain due to the relatively low impedance of the diode-connected device (Section 7.46) and (7.53) Figure 7. VDD v in M2 v out Vb M1 Figure 7.1.gm2 vin rO1 jjrO2 .10 (a) CS stage using a PMOS device as a current source. Transistor M2 generates a small-signal current equal to gm2 vin .cls v.11 shows a PMOS CS stage using an NMOS current source load.52) (7.gm2 rO1 jjrO2 : (7.11 CS stage using an NMOS device as current source.48) give Av = . 7. With = 0. 2006] June 30. because v1 = 0 and hence gm2 v1 = 0. Solution Av = . which then ﬂows through rO1 jjrO2 . M2 acts as a small-signal resistance equal to 1=gm2 .3 CS stage With Diode-Connected Load In some applications.3). producing vout = . and (7. we may use a diode-connected MOSFET as the drain load. Thus. Thus.34) yields .12(a).2. Illustrated in Fig. 7 CMOS Ampliﬁers v1 gm2v 1 r O2 v out v in M1 (b) r O1 (a) Figure 7.54) Exercise Calculate the gain if the circuit drives a loads resistance equal to RL . 7. Compute the voltage gain of the circuit. the drain node of M1 sees both rO1 and rO2 to ac ground.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6 (7. 2007 at 13:42 332 (1) 332 VDD Vb M2 v out v in M1 VDD Chap.

As depicted in Fig. (c) simpliﬁed circuit of (a).12(c).12 (a) MOS stage using a diode-connected load.59) (7. Av = .60) The contrast between (7.gm1 g 1 m p2 C 2 W=L I 1 D = . p n ox 2n Cox W=L2 ID (7.1: (7.55) (7. 2006] June 30. 7. ID .57) Interestingly. W=L1 : W=L2 s (7. 7. and hence Av = .12(b).cls v. the resistance seen at the drain is now equal to 1=gm2 jjrO2 jjrO1 .12(a) must take channel-length modulation into account. The reader may wonder why we did not consider a common-emitter stage with a diodeconnected load in Chapter 5. A more accurate expression for the gain of the stage in Fig. 7. V I =V T C2 T . 7. (b) bipolar counterpart.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.56) = . 2007 at 13:42 333 (1) Sec.2 Common-Source Stage VDD M2 Vout V in M1 V in Q1 (b) 333 VCC Q2 Vout v in M1 (c) 1 g m2 r O2 v out r O1 (a) Figure 7.57) and (7. the gain is given by the dimensions of M1 and M2 and remains independent of process parameters n and Cox and the drain current. Shown in Fig. such a circuit is not used because it provides a voltage gain of only unity: Av = .58) (7.60) arises from a fundamental difference between MOS and bipolar devices: transconductance of the former depends on device dimensions whereas that of the latter does not.gm1 g 1 m2 IC 1 1 = .gm1 .

7 . the output resistance of the stage is given by Rout = g 1 jjrO2 jjrO1 : m2 Determine the voltage gain of the circuit shown in Fig. 7.13(a) if 6= 0.62) Example 7.61) Similarly. 1 g jjrO2 jjrO1 : m2 (7. (7.

Thus. 2007 at 13:42 334 (1) 334 VDD V in M2 Vout M1 Chap. but with NMOS devices changed to PMOS transistors: M1 serves as a common-source device and M2 as a diode-connected load. 7.gm2 . 7 CMOS Ampliﬁers Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution This stage is similar to that in Fig.12(a). 2006] June 30.13 CS stage with diode-connected PMOS device.cls v. Av = .

I/O impedances. 1 jjr jjr : O1 O2 g m1 (7. As with the bipolar counterpart.4 CS Stage With Degeneration Recall from Chapter 5 that a resistor placed in series with the emitter of a bipolar transistor alters characteristics such as gain. 7.5 V.63) Exercise Repeat the above example if the gate of M1 is tied to a constant voltage equal to 0.14(b). From Fig. We expect similar results for a degenerated CS ampliﬁer.65) .14 depicts the stage along with its small-signal equivalent (if = 0). we have VDD RD Vout V in M1 RS RS v in v1 g v1 m v out RD (a) (b) Figure 7. Figure 7.14 (a) CS stage with degeneration. and linearity.64) v1 = 1 +vgin R : m S (7. vin = v1 + gmv1 RS and hence (7. (b) small-signal model.2. 7. the degeneration resistor sustains a fraction of the input voltage change.

68) Exercise What happens if 6= 0 for M2 ? In parallel with the developments in Chapter 5. Av = . we have v1 = . Also.67) if RS is replaced with 1=gm2 : Solution 1=gm2 [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. However. gmRD vin 1 + gm RS = .iX RS = iX + gm iX RS . 1 RD 1 : gm1 + gm2 (7.16).cls v. Figure 7. vout = . the current through rO is equal to iX . gm . VDD RD Vout V in M1 M2 v in 1 g m2 (b) (7. we may study the effect of a resistor appearing in series with the gate (Fig. we have .17 shows the small-signal equivalent of the circuit. the inclusion of the transistor output impedance complicates the analysis and is studied in Problem 31. 7. 2007 at 13:42 335 (1) Sec.15(a) if = 0. gm + RS a result identical to that expressed by (5.8 RD v out M1 (a) Figure 7.2 Common-Source Stage 335 Since gm v1 ﬂows through RD . RG sustains no voltage drop and does not affect the voltage gain or the I/O impedances.15 (a) Example of CS stage with degeneration.gmv1 RD and vout = . the output impedance of the degenerated CS stage plays a critical role in analog design and is worth studying here. Adding the voltage drops across rO and RS and equating the result to vX . since the gate current is zero (at low frequencies). Compute the voltage gain of the circuit shown in Fig.157) for the bipolar counterpart. 7. Since RS carries a current equal to iX (why?).67) Example 7.iX RS . 7. The gain is therefore given by (7. Transistor M2 serves as a diode-connected device. (b) simpliﬁed circuit.15(b)]. 2006] June 30. 1 RD . gm v1 = iX . Effect of Transistor Output Impedance As with the bipolar counterparts. Nonetheless. presenting an impedance of 7.66) (7.

and hence (7.9 Vb M1 M2 (a) M1 r O1 1 r g m2 O2 (b) Figure 7. we observe that the model in Fig. 7. 7.196) and (5.46(a) but with r = 1. (5.18(a) if M1 and M2 are identical. 2006] June 30. rO iX + gm iX RS + iX RS = vX . the MOS version also exhibits a “boosted” output impedance.71) (7. R out R out Example 7. Compute the output resistance of the circuit in Fig.16 CS stage with gate resistance. Solution The diode-connected device M2 can be represented by a small-signal resistance of .72) Alternatively.69) vX = r 1 + g R + R m S S iX O = 1 + gm rO RS + rO gm rO RS + rO : (7. iX v1 RS g v1 m rO vX Figure 7. Letting r ! 1 in Eqs.197) yields the same results as above. (b) simpliﬁed circuit. 5. 2007 at 13:42 336 (1) 336 Chap.18 (a) Example of CS stage with degeneration. 7 CMOS Ampliﬁers VDD RD RG M1 RS Vout V in Figure 7.17 Output impedance of CS stage with degeneration.17 is similar to its bipolar counterpart in Fig.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As expected from our study of the bipolar degenerated stage.70) (7.

since gm1 . 7. 2006] June 30.2 Common-Source Stage 337 1=gm2jjrO2 1=gm2.cls v. 2007 at 13:42 337 (1) Sec. Transistor M1 is degenerated by this resistance.70): Rout = rO1 1 + gm1 g which.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and from (7.

R out R out V b2 V b1 M1 M2 (a) M1 r O1 r O2 (b) Figure 7.75). Assume M1 and M2 are in saturation.75) Exercise Do the results remain unchanged if vice? M2 is replaced with a diode-connected PMOS de- Example 7.76) (7. 7.74) (7. (7.73) = gm2 = gm.10 Determine the output resistance of the circuit in Fig. we have Rout gm1 rO1 rO2 : We observe that this value is quite higher than that in (7. 7. (b) simpliﬁed circuit. Equation (7. transistor M2 operates as a current source. reduces to Rout = 2rO1 + g1 m 2rO1 : (7. With its gate-source voltage ﬁxed. m2 1 + g1 m2 (7. introducing a resistance of rO2 from the source of M1 to ground [Fig.19 (a) Example of CS stage with degeneration.19(a) and compare the result with that in the above example.77) 1 (which is valid in practice).71) can therefore be written as Solution Rout = 1 + gm1 rO1 rO2 + rO1 gm1rO1 rO2 + rO1 : Assuming gm1 rO2 (7.78) .19(b)].

20(c) for a voltage gain of 5. Assume n Cox = 100 A=V2 . 7. G + R1 jj 2 gm + RS (7. R R1 jjR2 R gmRD : G + R1 jj 2 Example 7.cls v. 2007 at 13:42 338 (1) 338 Chap. . 2006] June 30. 7. As mentioned in Chapter 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the voltage gain falls to (7.20 (a) CS stage with input coupling capacitor. but raises the voltage gain: (7. such a circuit no longer exhibits an inﬁnite input impedance: VDD R1 C1 V in R2 M1 RS RD Vout V in R1 RG C1 M1 R2 RS VDD RD Vout V in R1 RG C1 M1 R in R2 RS C2 VDD RD Vout (a) (b) (c) Figure 7. 7 CMOS Ampliﬁers Exercise Repeat the above example for the PMOS counterpart of the circuit. VTH = 0:5 V.20(c)]. it is possible to utilize degeneration for bias point stability but eliminate its effect on the small-signal performance by means of a bypass capacitor [Fig.80) where is assumed to be zero. 7. Rin = R1 jjR2 : Av = R R1 jjR2 R 1. 7. = 0.81) Av = .1 is similar to that analyzed for the bipolar stage in Chapter 5.5 CS Core With Biasing The effect of the simple biasing network shown in Fig. an input impedance of 50 k .20(b)].82) Design the CS stage of Fig. assume a voltage drop of 400 mV across RS . 7. (c) use of bypass capacitor.79) Thus. Also.20(a) along with an input coupling capacitor (assumed a short circuit). (b) inclusion of gate resistance. if the circuit is driven by a ﬁnite source impedance [Fig.2.11 (7.RD . and VDD = 1:8 V. Depicted in Fig. and a power budget of 5 mW. this does not alter the input impedance of the CS stage: Rin = R1 jjR2 . 7. Unlike the case of bipolar realization.

84) (7.2 Common-Source Stage 339 The power budget along with VDD = 1:8 V implies a maximum supply current of 2. 7. the gate voltage reaches 1. i.91) We must now check to verify that M1 indeed operates in saturation. we have chosen an excessively large RD . the gate-drain voltage difference exceeds VTH . e. even though VGS is reasonable.4 V.90) (7. VTH 2 2 L gives (7. This choice yields (7. along with Rin = R1 jjR2 = 50 k .. we must ensure a reasonable value for VGS . We must therefore increase gm so as to allow a lower value for RD .g. 6 and hence (7.DV GS TH = 92:1 .92) (7. requiring that R2 (7. The drain voltage is given by VDD .83) As with typical design problems. with ID known. which.87) W = 216: (7. the choice of gm and RD is somewhat ﬂexible so long as gm RD = 5. 2006] June 30.. For example. suppose we halve RD and double gm by increasing W=L by a factor of four: W = 864 L gm = 46:1 : 3 (7. VGS = 1 I gm = V 2. Since the gate voltage is equal to 1. As an initial guess. driving M1 into the triode region! How did our design procedure lead to this result? For the given ID .4 V.86) ID = 1 n Cox W VGS .88) L With VGS = 1 V and a 400-mV drop across RS . ID RD = 1:8 V . we allocate 2.e.85) RD = 463 : Writing (7. 2007 at 13:42 339 (1) Sec.78 mA. It follows that Solution RS = 148 : V.89) R1 + R2 VDD = 1:4 V. an excessively small gm (because gm RD = 5). yields.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. R1 = 64:3 k R2 = 225 k : (7.7 mA to M1 and the remaining 80 A to R1 and R2 .cls v. 1:25 V = 0:55 V. However.93) .

the voltage gain is positive and equal to VDD RD Vout V in Input Applied to Source M1 Vb Output Sensed at Drain Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. RD ID than the gate voltage minus VTH . but the drain voltage. Here. VDD . That is.96) . 7.84): VGS = 250 mV.21. ID RD . determine the maximum allowable value of RD and hence the maximum voltage gain.3 Common-Gate Stage Shown in Fig. VTH = 0:5 V. Neglect channel-length modulation. VTH 2 L (7. a high ID or RD is necessary. If W=L = 50.cls v. then the gate-source voltage of M1 decreases by the same amount. and VDD = 1:8 V. VTH to ensure M1 is saturated.95) The CG stage suffers from voltage headroom-gain trade-offs similar to those of the CB topology. V . Thus. With W=L known. M1 operates in saturation. a value higher Exercise Repeat the above example for a power budget of 3 mW and VDD = 1:2 V.21 Common-gate stage. 7 CMOS Ampliﬁers The corresponding gate-source voltage is obtained from (7. Is M1 in saturation? The drain voltage is equal to VDD . 2006] June 30. must remain above Vb .94) = 1:17 V. (7. n Cox = 100 A=V2 . 2007 at 13:42 340 (1) 340 Chap. A microphone having a dc level of zero drives a CG stage biased at ID = 0:5 mA. 7. the CG topology resembles the common-base stage studied in Chapter 5.12 Solution 1 ID = 2 n Cox W VGS . if the input rises by a small value. Av = gmRD : (7. the gate-source voltage can be determined from Example 7. yielding a gate voltage of 650 mV. In particular. to achieve a high gain. thereby lowering the drain current by gm V and raising Vout by gm V RD .

1 and (7.97) VDD .947 V V in Figure 7. we have from Fig. 7.100) Av 6:06: Figure 7. ID RD Vb .22 Signal levels in CG stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The gate voltage can be generated using a resistive divider similar to that in Fig.20(a).cls v.gmv1 = gmvX : (7.101) (7.22 summarizes the allowable signal levels in this design. Exercise If a gain of 10 is required.vX and iX v1 iX g v1 m RD v1 g v1 m RD vX vX (a) (b) Figure 7. VTH and hence (7.447 V M1 0 Vout Vb = 0. the above value of W=L and ID yield gm (7. 2007 at 13:42 341 (1) Sec.3 Common-Gate Stage 341 as VGS = 0:947 V: For M1 to remain in saturation. 7. VDD RD Vb − V TH = 0.23 (a) Input and (b) output impedances of CG stage. what value should be chosen for W=L? We now compute the I/O impedances of the CG stage.99) = 447 . Neglecting channel-length modulation for now. (7.102) . 2006] June 30. iX = . 7.23(a) v1 = .98) RD 2:71 k : Also. expecting to obtain results similar to those of the CB topology.

109) The gain is therefore equal to that of the degenerated CS stage except for a negative sign. including both channel-length modulation and a ﬁnite source impedance is beyond the scope of this book (Problem 41). Let us study the behavior of the CG stage in the presence of a ﬁnite source impedance (Fig. a resistance appearing in series with the gate terminal [Fig.cls v. vX = 1 gm vin gm + RS 1 = 1 + g R vin : m S Thus. 1 (7. we can make two observations. we write VDD RD Vout RS v in M1 X 1 gm Vb v in RS vX 1 gm Figure 7.23(b). 2006] June 30. Rin = g1 .104) Rout = RD .. First.23(b) and 7. i.103) = 0 and hence (7. from Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In a manner similar to that depicted in Chapter 5 for the CB topology. 7. an expected result because the circuits of Figs. The analysis of the common-gate stage in the general case.24 Simpliﬁcation of CG stage with signal source resistance. However.7 are identical.24) but still with = 0. Also. 7. the CG ampliﬁer exhibits a current gain of unity: the current provided by the input voltage source simply ﬂows through the channel and emerges from the drain node. v1 (7. m a relatively low value.107) (7. 2007 at 13:42 342 (1) 342 Chap.25(a)] does not alter the gain or I/O impedances (at low frequencies) because it sustains . 7 CMOS Ampliﬁers That is. In contrast to the common-source stage.106) vout = vout vX vin vX vin g = 1 +mgRD m RS = 1 RD : gm + RS (7.e. 7. 7.108) (7.105) (7.

(b) output resistance of CG stage.25 (a) CG stage with gate resistance.25(b)] is identical to that of the degenerated CS topology: Rout = 1 + gm rO RS + rO : Example 7. Second.112) = gm1 RD .26(a).3 Common-Gate Stage VDD RD Vout M1 v in RG Vb RS rO M1 R out 343 (a) (b) Figure 7.113) . 7. VDD RD Vout RS M 1 V in X M2 Vb v in RS 1 g m1 R out1 RS r O1 M1 1 r g m2 O2 (c) vX 1 g m2 (b) (a) Figure 7. 2006] June 30. We ﬁrst compute vX =vin with the aid of the equivalent circuit depicted in Fig. we have vout = gm1 RD vin 1 + gm1 + gm2 RS : (7. the output resistance of the CG stage in the general case [Fig.13 (7. 2007 at 13:42 343 (1) Sec. (b) equivalent input network.111) = 1 + g 1 g R : m1 + m2 S (7. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7.26 (a) Example of CG stage. a zero potential drop—as if its value were zero.26(b): Solution vX = gm2 jj gm1 1 1 vin gm2 jj gm1 + RS Noting that vout =vX 1 1 (7.110) For the circuit shown in Fig. (c) calculation of output resistance. calculate the voltage gain if = 0 and the output impedance if 0. 7.cls v.

7.27 for the following parameters: vout =vin Example 7. 7. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.14 = 5. we ﬁrst consider Rout1 .118) (7. VDD RD Vout RS C1 M1 X R3 R1 V in R2 Figure 7. we have vout = vX vout vin vin vX R3 = R jj1jj1=gm R gm RD .3.117) Exercise Calculate the output impedance if the gate of M2 is tied to a constant voltage. as shown in Fig.27 CG stage with biasing. the voltage divider consisting of R1 and R2 does not affect the small-signal behavior of the circuit (at low frequencies).26(c). RS . 7 CMOS Ampliﬁers To compute the output impedance. 2007 at 13:42 344 (1) 344 Chap. 7. Design the common-gate stage of Fig. Since the impedance seen to the right of node X is equal to R3 jj1=gm .115) The overall output impedance is then given by Rout = Rout1 jjRD gm1 rO1 g 1 jjRS + rO1 jjRD : m2 (7. Providing a path for the bias current to ground. . which from (7. =gm + S 3 (7.110) is equal to Rout1 = 1 + gm1rO1 g 1 jjrO2 jjRS + rO1 gm1 rO1 g 1 jjRS + rO1 : m2 m2 (7.116) (7.27. we surmise the CG ampliﬁer can be biased as shown in Fig.114) (7. As mentioned earlier. resistor R3 lowers the input impedance—and hence the voltage gain—if the signal source exhibits a ﬁnite output impedance.119) where channel-length modulation is neglected. 2006] June 30.1 CG Stage With Biasing Following our study of the CB biasing in Chapter 5.

what voltage gain can be achieved? Suppose in Example 7. allowing a lower value of RD . Thus.1 .122) and (7. We must now compute two interrelated parameters: W=L and RD . A larger value of W=L yields a greater gm . Exercise If W=L cannot exceed 100. R3 = 500 .124) . 2007 at 13:42 345 (1) Sec. 2006] June 30. and set gm RD to the required gain: (7. we wish to minimize W=L (and hence transistor capacitances). amounting to 1. What is the minimum acceptable value of W=L? For a given ID .11.1 mA for the drain current of M1 . VTH = 0:5 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 Common-Gate Stage 345 RS = 0. VGS . the drain voltage is given by VDD . and gm = 2ID =VGS . Assume n Cox = 100 A=V2 . The resistive divider consisting of R1 and R2 must establish a gate voltage equal to 1.14. R1 and R2 . if VGS = 0:8 V.11 mA. VTH = 136:4 . Allocating 10 A to the voltage divider. where VR3 denotes the voltage drop across R3 .cls v.123) gives: 2ID (7. VTH VGS . VDD = 1:8 V. dictating RD = 682 for vout =vin = 5. Let us determine whether M1 operates in saturation.35 V. we choose an initial value for VGS to arrive at a reasonable guess for W=L. From the power budget. M1 is indeed in saturation.35 V while drawing 10 A: Solution VDD = 10 A R1 + R2 R2 V = 1:35 V: R1 + R2 DD It follows that R1 (7. On the other hand. VTH increases. Since the drain voltage exceeds VG .122) VGS . The gate voltage is equal to VGS plus the drop across R3 . ID RD VGS + VR3 . For example. we leave 1. and = 0. the voltage drop across R3 is equal to 550 mV. Av VGS .121) = 45 k and R2 = 135 k . 7. 1=gm = 50 . power budget = 2 mW. as W=L decreases. we must ﬁrst compute the maximum allowable VGS . we obtain a total supply current of 1.123) VDD . VTH . Thus. then W=L = 244.15 Solution VDD . VTH + VR3 2 (7. VTH . ID RD = 1:05 V. We impose the condition for saturation as Example 7. As in Example 7. VTH RD = Av : Eliminating RD from (7.120) (7.

125) W=L It follows that 2 . 2007 at 13:42 346 (1) 346 Chap. VTH In other words.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7 CMOS Ampliﬁers and hence VGS .cls v. VR3 : Av + 1 2 (7. VDD . 2006] June 30.

VDD V in Input Applied to Gate M1 Vout RL Output Sensed at Source Figure 7. we have gmv1 rO jjRL = vout : (7. with the drain tied to VDD . Vin . Thus.4. the gate-source voltage tends to increase. Recognizing that rO appears in parallel with RL . Vout “follows” Vin . Figure 7.28. 7. The circuit’s behavior is similar to that of the bipolar counterpart.28 is raised by a small amount. we say the follower can serve as a “level shift” circuit. including channellength modulation. 7.4 Source Follower The MOS counterpart of the emitter follower is called the “source follower” (or the “commondrain” stage) and shown in Fig. V 2 : n Cox 2 DD R3 (7. 7.128) .28 Source follower. too.29(a) depicts the small-signal equivalent of the source follower.1 Source Follower Core If the gate voltage of M1 in Fig.127) Exercise Repeat the above example for Av = 10. From our analysis of emitter followers in Chapter 5. we expect this topology to exhibit a subunity gain.126) Av + 2 W=L 172:5: (7. thereby raising the source current and hence the output voltage. Since the dc level of Vout is lower than that of Vin by VGS . 7. The ampliﬁer senses the input at the gate and produces the output at the source. VID .

The voltage gain is therefore positive and less than unity. (b) simpliﬁed circuit. rO ). we can view the above result as voltage division between a resistance equal to 1=gm and another equal to rO jjRL [Fig.131): Solution Av = 1 rO1 jjrO2 : gm1 + rO1 jjrO2 (7.cls v. vin = v1 + vout : It follows that (7.129) vout = gm rO jjRL vin 1 + gmrO jjRL = 1 rO jjRL : g + rO jjRL m (7.132) .131) (at low frequencies) because it sustains a zero drop.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.16 A source follower is realized as shown in Fig. 7. (b) simpliﬁed circuit. V in M1 r O1 Vout r O2 Figure 7. 7. 2007 at 13:42 347 (1) Sec. 7. we substitute RL = rO2 in Eq. 2006] June 30.29 (a) Small-signal equivalent of source follower.131) As with emitter followers.30 (a) Follower with ideal current source.30(a). however.130) (7. Note. It is desirable to maximize RL (and Example 7. where Calculate the voltage gain of the circuit. Also.29(b)]. 7. (7. Since M2 simply presents an impedance of rO2 from the output node to ac ground [Fig.4 Source Follower 1 gm 347 v in v1 g v1 m rO v in v out RL r O v out RL (a) (b) Figure 7. that a resistance placed in series with the gate does not affect (7.30(b)]. VDD V in M1 Vout Vb M2 (a) (b) M2 serves as a current source.

7.134) The power budget and supply voltage yield a maximum supply current of 5. yielding Rout = g1 jjrO jjRL g1 jjRL : m m (7. thereby providing buffering capability. With RL Solution = 50 and rO = 1 in Fig. the source follower exhibits a very high input impedance and a relatively low output impedance.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7 CMOS Ampliﬁers If rO1 jjrO2 1=gm1. we have Av = 1 RL gm + RL and hence (7.2 As illustrated in Fig. Rout consists of the resistance seen looking up into the source in parallel with that seen looking down into RL . RS is placed in series with the source of Example 7.133) gm = 501 : (7. VTH = 0:5 V. Exercise Repeat the above example if a resistance of value M2 . and VDD = 1:8 V. the former is equal to 1=gm jjrO .cls v. . 2 The input impedance is inﬁnite at low frequencies.load with a voltage gain of 0.56 mA.28.17 Design a source follower to drive a 50.135) Exercise What voltage gain can be achieved if the power budget is raised to 15 mW? It is instructive to compute the output impedance of the source follower.136) (7. With 6= 0. = 0. Assume n Cox = 100 A=V2 . 2006] June 30. Using this value for ID in gm = 2n Cox W=LID gives p W=L = 360: (7. 7. then Av 1.137) In summary. 2007 at 13:42 348 (1) 348 Chap.5 and a power budget of 10 mW.31.

formed: Solution W=L. and RG = 50 k . 7. = 0. The unknowns in this problem are VGS .18 (7.32 Source follower with input and output coupling capacitors. Let us compute the bias current of the circuit.4. VTH 2 L 1 C W V .139) (7. Also.141) (7. 7. Assume n Cox = 100 A=V2 . we have VGS + ID RS = VDD : Neglecting channel-length modulation.32 for a drain current of 1 mA and a voltage gain of 0. 2007 at 13:42 349 (1) Sec. Note that M1 operates in saturation because the gate and drain voltages are equal. VDD = 1:8 V. V 2 : = 2 n ox L DD D S TH The resulting quadratic equation can be solved to obtain ID .4 Source Follower 349 M1 RL rO M1 rO 1 gm rO R out RL Figure 7. I R . The following three equations can be (7.cls v. 2006] June 30. With a zero voltage drop across RG .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.138) 1 ID = 2 n Cox W VGS . VTH = 0:5 V.8. Example 7. 7. we write (7. Figure 7.140) Design the source follower of Fig. the input impedance of the circuit has dropped from inﬁnity to RG .2 Source Follower With Biasing The biasing of source followers is similar to that of emitter followers (Chapter 5). VDD C1 V in RG M1 RS C2 Vout Figure 7. and RS . VTH 2 2 L ID RS + VGS = VDD .142) ID = 1 n Cox W VGS .32 depicts an example where RG establishes a dc voltage equal to VDD at the gate of M1 (why?) and RS sets the drain bias current.31 Output resistance of source follower.

the small-signal behavior of these circuits is quite similar to that of their bipolar counterparts. with the exception of the high impedance seen at the gate terminal. VDD .145) (7.149) (7.V +I R : DD TH D S Thus.142). vA D v = 867 : and (7. VTH . we have studied three basic CMOS building blocks. 2006] June 30.5 Summary and Additional Examples In this chapter. we write (7.33). v Av = 0:933 V: It follows from (7. ID RS A = VDD . 2007 at 13:42 350 (1) 350 Chap.143) as (7. To avoid this effect. integrated circuits bias the follower by means of a current source (Fig.142) and (7. the common-source stage.143) do not contain W=L and can be solved to determine VGS and RS .146) A RS = VDD I. VTH 2 . namely. 7 CMOS Ampliﬁers Av = 1 RS : gm + RS RS Av = VGS . and the source follower. VID RS 2I R GS TH + D S 2ID RS = V .140) reveals that the bias current of the source follower varies with the supply voltage.141) that (7.150) (7. (7. VTH 2 . the common-gate stage.152) Exercise What voltage gain can be achieved if W=L cannot exceed 50? Equation (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. then (7.143) If gm is written as 2ID =VGS . With the aid of (7. 7. VTH 2ID + RS 2 = V .147) (7. As observed throughout the chapter.144) (7. We have noted that the biasing .cls v.151) W = 107: L (7.148) VGS = VDD . 7.

gm1 g 1 jjrO1 jjrO2 jjrO3 m3 and (7.33 Source follower with biasing. VDD V in M1 Vout Vb M2 M3 v in M1 r O2 r O1 v out 1 r g m3 O3 (b) (a) Figure 7.34(a).5 Summary and Additional Examples VDD C1 RG M1 C2 Vout Vb M2 V in C1 RG M1 C2 Vout VDD 351 V in Figure 7. 7. M2 can be replaced with a small-signal resistance equal to rO2 . 2007 at 13:42 351 (1) Sec. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. emphasizing analysis by inspection. 2006] June 30.34 (a) Example of CS stage. In this section. The circuit now reduces to that depicted in Fig.154) Exercise Repeat the above example if M2 is converted to a diode-connected device. we consider a number of additional examples to solidify the concepts introduced in this chapter.34(b). (b) simpliﬁed circuit. . 7. with the quadratic ID -VGS relationship supplanting the exponential IC -VBE characteristic. and M3 with another equal to 1=gm3 jjrO3 .153) Rout = g 1 jjrO1 jjrO2 jjrO3 : m3 Note that 1=gm3 is dominant in both expressions. 7. Transistors M2 and M3 therefore act as the load.cls v. Example 7. yielding Solution Av = . (7. We identify M1 as a common-source device because it senses the input at its gate and generates the output at its drain. with the former serving as a current source and the latter as a diode-connected device.19 Calculate the voltage gain and output impedance of the circuit shown in Fig. schemes are also similar.

cls v. (b) simpliﬁed circuit. M2 . assume rO1 = 1 in Fig. 7. For simplicity.35(b). 7. V DD M3 V in Vb M1 Vout M2 (a) (b) 1 r g m3 O3 V in M1 Vout r O2 Figure 7. Simplifying the ampliﬁer to that in Fig.36(b). 7. 7 CMOS Ampliﬁers Example 7.155) Exercise Repeat the above example if the gate of M3 is tied to a constant voltage. 2006] June 30. 7. Example 7.36(a) presents an impedance of 1 + gm1 rO1 RS + rO1 to the drain of M2 . transistor M1 in Fig.35 (a) Example of CS stage.35(a). Neglect channel-length modulation in M1 .36 Examples of (a) CS and (b) CG stages .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1 rO1 : + g jjrO3 gm1 m3 Solution (7.21 Determine the voltage gain of the ampliﬁers illustrated in Fig. 7. Degenerated by RS . we have 2 Av = .36. transistor M1 drives the current-source load. Thus the total impedance seen at the drain is equal to 1+ gm1 rO1 RS + Solution . Operating as a CS stage and degenerated by the diode-connected device M3 . VDD V in M2 Vout Vb M1 RS V b1 M1 RS (b) VDD V b2 M2 Vout V in (a) Figure 7.20 Compute the voltage gain of the circuit shown in Fig. 2007 at 13:42 352 (1) 352 Chap.

29(b).158) Exercise What happens if a resistance of value R1 is placed in series with the drain of M1 ? . (b) In this circuit. Solution Av = 1 RD 1 : gm1 + gm2 (7. 7. (b) simpliﬁed circuit. 7. 7. Thus. VDD RD Vout V in M1 M2 I1 Vb v in 1 g m1 M 2 Example 7. 7. obtaining (7.37(a) if = 0.157) Exercise Replace RS wit a diode-connected device and repeat the analysis. we derive the model depicted in Fig.cls v. A simple method of analyzing the circuit is to replace vin and M1 with a Thevenin equivalent.22 RD v out (a) Figure 7. M1 operates as a common-gate stage and M2 as the load. giving a voltage gain of Av = . 7. M1 operates as a source follower and M2 as a CG stage (why?).gm2 f 1 + gm1 rO1 RS + rO1 jjrO1 g : Av2 = 1 rO2 : gm1 + RS (7.156) In Fig.5 Summary and Additional Examples 353 rO1 jjrO2 .37 (a) Example of a composite stage.37(b). Calculate the voltage gain of the circuit shown in Fig. From Fig.109): (7. 2006] June 30. 2007 at 13:42 353 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.36(b).

.38 Example of composite stage. 2007 at 13:42 354 (1) 354 Chap. the transistor must be “biased. 2006] June 30.160) Exercise Which one of the two gains is higher? Explain intuitively why. This load impedance is equal to 1=gm3jjrO3 jjrO4 . 7.38 produces two outputs.131) Solution 1 vout1 = gm2 jjrO2 : 1 1 vin gm2 jjrO2 + gm1 (7. drain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exhibiting a small-signal impedance of 1=gm2jjrO2 . The reader can show that if rO1 = 1.” i. rO (with source grounded).23 The circuit of Fig.159) For Vout2 . and source of a MOSFET are equal to inﬁnity. In order to obtain the required small-signal MOS parameters such as gm and rO . 7.6 Chapter Summary The impedances seen looking into the gate. Calculate the voltage gain from the input to and to X . Assume = 0 for M1 . transistor M2 acts as a load for the follower. gm3 jjrO3 jjrO4 : 1 + 1 jjr vin gm1 gm2 O2 (7. and 1=gm (with gate grounded). yielding from (7.cls v. 7 CMOS Ampliﬁers Example 7.e. resulting in 1 vout2 = . . then M3 and M4 do not affect the source follower operation. respectively . Signals simply perturb these conditions. M1 operates as a degenerated CS stage with a drain load consisting of the diode-connected device M3 and the current source M4 . VDD Vb M4 V in X M2 M3 Y M1 Vout1 Vout2 Y Figure 7. the circuit serves as a source follower. carry a certain drain current and sustain certain gate-source and drain-source voltages. For Vout1 .

a high input impedance. Problems In the following problems. The CG stage provides a moderate voltage gain. 7. = 0. 2006] June 30.8 V 50 k Ω 1 kΩ W=L if M1 must M1 Figure 7. Consider the circuit shown in Fig. The circuit of Fig.39 remain in saturation. The CS stage provides a moderate voltage gain. 7. . Source degeneration raises the output impedance of CS stages considerably. (a) Calculate the minimum allowable value of W=L if M1 must remain in saturation. 2. In the circuit of Fig.39.) 4.41.8 V R1 500 Ω = 20=0:18. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VDD = 1. 7. and a low output impedance.42 must be designed for a voltage drop of 200 mV across RS . (b) What are the required values of R1 and R2 if the input impedance must be at least 30 k . determine the maximum allowable value of VDD = 1.6 Chapter Summary 355 Biasing techniques establish the required gate voltage by means of a resistive path to the supply rails or the output node (self-biasing). With a single transistor. 2007 at 13:42 355 (1) Sec. only three ampliﬁer topologies are possible: common-source and common-gate stages and source followers. and a moderate output impedance. p Cox = 100 A=V2 .40 3. serving as a good voltage buffer. Calculate the maximum transconductance that M1 can provide (without going into the triode region. a high input impedance. 7. M1 R2 Figure 7.cls v.0:4 V for PMOS devices. We wish to design the circuit of Fig. Assume = 0. 1. The voltage gain expressions for CS and CG stages are similar but for a sign. assume n Cox = 200 A=V2 . and a moderate output impedance. and VTH = 0:4 V for NMOS devices and . unless otherwise stated.40 for a drain current of 1 mA. If W=L compute R1 and R2 such that the input impedance is at least 20 k . The source follower provides a voltage gain less than unity. a low input impedance. Source degeneration improves the linearity but lowers the voltage gain.

Due to a manufacturing error. We wish to design the stage in Fig.44 provide a transconductance of 1=100 . 2007 at 13:42 356 (1) 356 Chap.41 VDD = 1. If W=L = 50=0:18. 7. RP has appeared in the circuit of Fig.43 mA. where W=L = 20=0:18. The self-biased stage of Fig.cls v.46. 7 CMOS Ampliﬁers VDD = 1.43. Consider the circuit depicted in Fig. 8.8 V RG RD M1 Figure 7. 2006] June 30. a parasitic resistor. calculate the required value of RD . 7. 7. 7. 6.8 V 10 k Ω 1 kΩ M1 100 Ω Figure 7. calculate the values of R1 and R2 such that these resistors carry a current equal to one-tenth of ID1 . Assuming the current ﬂowing through R2 is one-tenth of ID1 . We know that circuit samples free from this error exhibit VGS = VDS whereas defective .5 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V R1 500 Ω M1 R2 RS 100 Ω Figure 7.44 must be designed for a drain current of 1 mA. 7. calculate the values of R1 and R2 so that ID1 = 0:5 VDD = 1.8 V R1 500 Ω M1 R2 RS 200 Ω Figure 7.45 for a drain current of 0. If M1 is to VDD = 1.42 5.

6 Chapter Summary VDD = 1.8 V 30 k Ω RP 2 kΩ M1 Figure 7.49 must be designed for IX = IY = 0:5 mA. Determine the values of W=L and RP . IX M1 VB IY M2 Figure 7. = 0:1 V.46 samples exhibit VGS = VDS + VTH . An NMOS current source must be designed for an output resistance of 20 k and an output current of 0. 10.48 Determine W1 and W2 such that IX = 2IY = 1 mA.8 V 10 k Ω 20 k Ω 1 kΩ M1 RS RP 200 Ω Figure 7.8 V R1 2 kΩ 357 M1 R2 Figure 7. RP has appeared in the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . 7. VB 2 = 1:2 V. In the circuit of Fig. Due to a manufacturing error. M1 and M2 have lengths equal to 0. We know that circuit samples free from this error exhibit VGS = VDS + 100 mV whereas VDD = 1. 2006] June 30.47. 9.cls v. 2007 at 13:42 357 (1) Sec.1 . Determine the values of W=L and RP . 7.47 defective samples exhibit VGS = VDS + 50 mV.48. 7.1 .25 m and = 0:1 V. Assume VDS 1 = VDS 2 = VB = 0:8 V. Compare the output resistances of the two current sources. If VB 1 = 1 V.5 mA. calculate W1 and W2 . What is the maximum tolerable value of ? 12. The two current sources in Fig. 7.45 VDD = 1. and L1 = L2 = 0:25 m. What is the output resistance of each current source? 11. a parasitic resistor.

1 .2 V.8 V M2 VB X M1 Figure 7. VDD = 1. 7.) . 2007 at 13:42 358 (1) 358 Chap.50 as a current source. W=L1 = 5=0:18. calculate VB such that VX = 0:9 V.1 . and 2 = 0:15 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VB = 1 V and W=L = 20=0:25. How are the output resistances of M1 and M2 related? Consider the circuit shown in Fig.1 . (a) What gate voltage yields a drain current of 0. VB1 = 0:2 V. and VX has a dc level of 1. 7. In the circuit of Fig.49 13. 1 = 0:1 V.52 16. In the common-source stage of Fig. = 0:1 V. VX M1 V B1 Figure 7.50 14. 7 CMOS Ampliﬁers IX M1 V B1 V B2 IY M2 Figure 7.5 mA? (Verify that M1 operates in saturation. 7. In the circuit of Fig. M1 and M2 serve as current sources. if = 0:1 V.cls v.53. 17. A student mistakenly uses the circuit of Fig. calculate the impedance seen at the source of M1 . where W=L1 = 10=0:18 and W=L2 = 30=0:18. (b) Now sketch IX as a function of VX as VX goes from 0 to VDD .1 .52. 7. W=L = 30=0:18 and = 0.51. Calculate IX VDD W L IX M1 VB M2 2W L and IY if IY Figure 7. If W=L = 10=0:25. 7.54. (a) Determine VB such that ID1 = jID2 j = 0:5 mA for VX = 0:9 V. W=L2 = 10=0:18.51 15. 2006] June 30.

(b) if W=L2 = 20=0:18.8 V Vb M2 Vout V in M1 Figure 7. 7.56 (a) Compute the required value of W=L1 . and ID = 0:25 mA. 7. (a) Compute the required gate bias voltage.8 V RD Vout V in M1 Figure 7.1 . = 0. 2006] June 30.53 VDD = 1. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V RD 2 kΩ Vout V in M1 Figure 7.54 (b) With such a drain bias current.54 is designed with W=L = 20=0:18.6 Chapter Summary VDD = 1. VDD = 1. 20. 18.55 Determine the required value of RD if the power dissipation must not exceed 1 mW. . We wish to design the stage of Fig. (b) With such a gate voltage. how much can W=L be increased while M1 remains in saturation? What is the maximum voltage gain that can be achieved as W=L increases? 19.8 V M2 VB IX VX 359 M1 Figure 7.cls v.56 must provide a voltage gain of 10 with a bias current of 0.55 for a voltage gain of 5 with W=L 20=0:18. calculate the voltage gain of the stage. Assume 1 = 0:1 V.5 mA. 7. 2007 at 13:42 359 (1) Sec. VDD = 1.1 . The circuit of Fig. and 2 = 0:15 V. calculate the required value of VB . The CS stage of Fig.

Calculate the voltage gain if 1 = 0:1 V.56. If 1 = 0:15 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We wish to design the circuit shown in Fig.59 must achieve a voltage gain of 5.59 26.1 and 2 = 0:05 V. 7. 2007 at 13:42 360 (1) 360 Chap.cls v. M2 has a long length so that 2 1 . 7. W=L1 = 20=0:18. (a) If = 0.1 . determine the required value of W=L2 . VDD Vb M2 Vout V in M1 (a) VDD V in M2 Vout Vb M1 (b) Figure 7. W=L1 = 10=0:18 and ID1 = 0:5 mA.59 for a voltage gain of 3. or (b) the bias current is doubled. 7.57 24.59.57 is preferred. 7. If the width and the length of both transistors are doubled. (b) Now calculate the voltage gain. (a) If W=L2 = 2=0:18. The circuit of Fig.5 VDD = 1. If W=L1 VDD = 1. Explain which one of the topologies shown in Fig. 27. and ID = 1 mA. Assume = 0. 7 CMOS Ampliﬁers 21. The CS stage depicted in Fig. compute the required value of W=L1 .58 mA. determine W=L2 such that M1 operates at the edge of saturation. 25. determine W=L2 . . The CS stage of Fig. 7.8 V M2 Vout V in M1 = Figure 7. 22. (b) What is the maximum allowable bias current if M1 must operate in saturation? 20=0:18. 2006] June 30. 7. (c) Explain why this choice of W=L2 yields the maximum gain.8 V V in M2 Vout Vb M1 Figure 7.58 must achieve a voltage gain of 15 at a bias current of 0. 7. In the stage of Fig. 23.1 . how does the voltage gain change? Consider two cases: (a) the bias current remains constant. In the circuit of Fig.56 is designed for a bias current of I1 with certain dimensions for M1 and M2 .

Assume = 0.60. VDD = 1. 34. 7. 7. If 6= 0. 7. (a) If RD = 1 k . determine the voltage gain of the stages shown in Fig. 7. Does the transistor operate in saturation for this choice of RD ? 31. 29.6 Chapter Summary VDD M2 Vout Vb M2 VDD M3 Vout V in M1 V in M1 M3 Vb VDD M2 Vout 361 V in M1 (a) (b) (c) VDD V in M2 Vout Vb M1 M3 Vb V in VDD M2 Vout M1 M3 V in (e) (f) VDD M2 RD Vout M1 (d) Figure 7. 2007 at 13:42 361 (1) Sec. calculate the voltage gain of the circuit.61 must provide a voltage gain of 4 with a bias current of 1 mA. 32. Calculate the voltage gain of the circuits depicted in Fig. Determine the output impedance of each circuit shown in Fig. Does the transistor operate in saturation for this choice of W=L? (b) If W=L = 50=0:18.61 30. 2006] June 30.62. 7.60 28.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. If RD = 1 k and = 0:1 V.1 . determine the required value of RD . The CS stage of Fig. Assuming gm rO 1. determine the required value of W=L. determine the gate voltage such that M1 operates at the edge of saturation. The degenerated CS stage of Fig. In the circuit of Fig.63. Assume a drop of 200 mV across RS and = 0. compute the required value of W=L for a gate voltage of 1 V. 7. Consider a degenerated CS stage with 0.61. Assume = 0.64 carries a bias current of 1 mA. Assume 6= 0.8 V RD Vout V in M1 RS Figure 7. 7. 33.cls v. What is the voltage gain of the circuit? .

Repeat Problem 34 with = 0 and compare the results. and C1 is very large. An adventurous student decides to try a new circuit topology wherein the input is applied to the drain and the output is sensed at the source (Fig. 7. 36. Assume 6= 0. Determine the values of W=L and RD for an input impedance of 50 and maximum voltage gain (while M1 remains in saturation). 37.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (a) If = 0 and I1 = 1 mA. determine W=L to obtain a voltage gain of 5.67. 2006] June 30. 7. 2007 at 13:42 362 (1) 362 VDD M2 Vout V in M1 M3 V in M1 M3 (a) (b) Chap. the drain current of M1 is deﬁned by the ideal current source I1 and remains independent of R1 and R2 (why?).cls v. Assuming gm rO .g. . In the common-source stage depicted in Fig. whether M1 comes closer to the triode region) and the voltage gain. Suppose I1 = 1 mA.1 mA from the supply. 40. = 0. (a) Compute the value of W=L to obtain a voltage gain of 5. determine the values of RD and W=L. Consider the CS stage shown in Fig.68. 7 VDD M2 RD Vout V in M1 CMOS Ampliﬁers VDD RD Vout M2 I1 Vb (c) VDD RD Vout V in M2 M1 Vb Vb V in VDD M2 M1 Vout M3 (d) (e) Figure 7. (b) Choose the values of R1 and R2 to place the transistor 200 mV away from the triode region while R1 + R2 draws no more than 0.68 must provide a voltage gain of 4 and an input impedance of 50 ..62 35.65). The common-gate stage shown in Fig. calculate the voltage gain of the circuit. where I1 deﬁnes the bias current of M1 and C1 is very large. (c) With the values found in (b). A CG stage with a source resistance of RS employs a MOSFET with 0. 41. 7. 7. 7. determine the voltage gain of the circuit and discuss the result. = 0. ID = 0:5 mA.66. RD = 500 . Suppose in Fig. what happens if W=L is twice that found in (a)? Consider both the bias conditions (e. what is the maximum allowable value of RD ? (b) With the value found in (a). 38. 39. and = 0. and Vb = 1 V. If ID = 0:5 mA.

Assume = 0. calculate the required value of W=L. 43.65 42.cls v. 7.70 is biased by means of I1 = 1 mA.69 must provide an input impedance of 50 and an output impedance of 500 . (a) What is the maximum allowable value of ID ? (b) With the value obtained in (a). 7.63 VDD = 1. (a) What value of RD places the transistor M1 100 mV away from the triode region? (b) What is the required W=L if the circuit must provide a voltage gain of 5 with the value of RD obtained in (a)? .8 V RD Vout V in M1 Figure 7.6 Chapter Summary VDD R out V in M2 M1 Vb V in R out M1 M2 I1 (b) 363 Vb (a) R out Vb M2 VDD V in M2 Vb V in M1 (c) M1 M3 M3 R out (d) Figure 7. (c) Compute the voltage gain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 2007 at 13:42 363 (1) Sec.64 V in VB M1 Vout RS Figure 7. The CG stage depicted in Fig. The CG ampliﬁer shown in Fig. 7. Assume = 0 and C1 is very large.

where a common-source stage (M1 and RD1 ) is followed by a common-gate stage (M2 and RD2 ).68 VDD = 1. 7. (b) Simplify the result obtained in (a) if RD1 ! 1. Consider the circuit of Fig.8 V RD Vout V in M1 Vb Figure 7. Repeat Problem 45 for the circuit shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . 7 VDD = 1.66 VDD = 1. (a) Writing vout =vin = vX =vin vout =vX and assuming = 0.8 V RD Vout V in M1 Figure 7. 2007 at 13:42 364 (1) 364 Chap. 45. 46. Assuming = 0.72. Explain why this stage is not a common-gate ampliﬁer. compute the overall voltage gain.8 V R1 C1 M1 V in R2 I1 C1 RD Vout CMOS Ampliﬁers Figure 7. Explain why this result is to be expected.8 V R1 C1 M1 V in I1 C1 RD Vout Figure 7. Assume = 0. 2006] June 30.73.74.cls v. calculate the voltage gain of the circuit shown in Fig.67 VDD = 1. 7.71. 7. 7.69 44. Determine the voltage gain of each stage depicted in Fig. 47.

7. 2007 at 13:42 365 (1) Sec.76 is biased through RG . 2006] June 30. Assume = 0.78 must exhibit an output impedance of less than 50 with a power budget of 2 mW. 50.71 48. Determine the values of I1 and W=L if the circuit must provide an output impedance less than 100 with VGS = 0:9 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6 Chapter Summary 365 VDD = 1. 7. 7.8 V RD Vout C1 V in M1 I1 Figure 7. 7. Assume = 0 and the capacitors are very large. 52.77 is to be designed with a maximum bias gate voltage of 1. The source follower shown in Fig. The circuit of Fig.8 if = 0. The source follower of Fig. 51. Calculate the voltage gain of the stage depicted in Fig.1 . .78 employs a current source.70 VDD M2 Vout V in M1 RS Vb V in (a) VDD M2 RD Vout M1 Vb V in M1 RS VDD M2 Vout Vb R1 (c) (b) VDD Vb M3 M2 RD Vout V in M1 (d) V in Vb RD I1 (e) VDD M1 M2 Vout Vb Figure 7. If W=L = 30=0:18 and = 0.77 for a voltage gain of 0. Assume = 0. 7.cls v. 49.8. The source follower depicted in Fig. determine the required gate bias voltage. Calculate the voltage gain if W=L = 20=0:18 and = 0:1 V.8 V. Determine the required value of W=L. 7. We wish to design the source follower shown in Fig. 53. 7.75. Compute the required value of W=L for a voltage gain of 0.

7. unless otherwise stated.81. 57.cls v. If RD ID = 1 V. Compute the required value of W=L. 2006] June 30. 58. Assume 6= 0. 2007 at 13:42 366 (1) 366 VDD R D1 M2 M1 R D2 Vout Vb X V in Chap. Assume C1 is very large and = 0. Design the CS stage shown in Fig. determine the required value of W=L. Design Problems In the following problems.82 must be designed for a voltage gain of 5 with a power budget of 2 mW.79 for a voltage gain of 0. Consider the circuit shown in Fig. 7 CMOS Ampliﬁers Figure 7.73 VDD I1 Vout RG V in M1 Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 55. Determine the voltage gain of the stages shown in Fig. 56.72 VDD R D2 V in M1 M2 R D1 X Vout Vb Figure 7. where a source follower (M1 and I1 ) precedes a common-gate stage (M2 and RD ). 7.80.8 with a power budget of 3 mW. We wish to design the source follower of Fig.82 for a voltage gain of 5 and an output impedance of 1 k . Make the same assumptions . assume = 0. (b) Simplify the result obtained in (a) if gm1 = gm2 . (a) Writing vout =vin = vX =vin vout =vX . 7. compute the overall voltage gain. 7.74 54. 7. Assume the capacitors are very large and RD = 10 k . The CS ampliﬁer of Fig. Bias the transistor so that it operates 100 mV away from the triode region.

61. Determine the required current.77 VDD = 1.75 RG V in 50 k Ω VDD = 1. 7. 60. If the overdrive voltage of the transistor must not exceed 300 mV and R1 + R2 must consume less than than 5 of the allocated power. design the circuit. 7. 2006] June 30.8 V V in 500 Ω M1 Vout RS Figure 7. We wish to design the CS stage of Fig.83 for a voltage gain of 5 and a power budget of 6 mW. Make the same assumptions as those in Problem 57. The degenerated stage depicted in Fig.76 VDD = 1.82 for maximum voltage gain but with W=L 50=0:18 and a maximum output impedance of 500 . Design the circuit of Fig. 2007 at 13:42 367 (1) Sec. 7.6 Chapter Summary VDD RD Vout C1 R3 R4 M1 R1 CB R2 367 V in Figure 7.8 V M1 Vout 1 kΩ RS Figure 7.83 must provide a voltage gain of 4 with a power budget of 2 mW while the voltage drop across RS is equal to 200 mV.8 V V in M1 Vout I1 Figure 7. 7.cls v. Assume . 59.78 as those in Problem 57.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Make the same assumptions as those in Problem 57.

85. Design the stage for a voltage 200 . The circuit shown in Fig.80 VDD RD Vout V in M1 X M2 I1 Vb Figure 7.81 the voltage drop across RS is equal to the overdrive voltage of the transistor and RD = .79 VDD V in M1 Vout RS Vb M2 (a) (b) VDD V in M1 Vout Vb M2 RS (c) VDD V in M1 Vout M2 VDD V in R1 M2 R2 (d) (e) VDD VDD V b2 V b1 Vb M3 M2 Vout V in M1 (f) M1 Vout M3 M1 Vout V in M2 Figure 7. 7. 63.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. M2 serves as a current source. 62. In the circuit of Fig.8 V V in M1 C1 Vout I1 50 Ω Chap. design the circuit such that M1 operates 200 mV away from the triode region. 2007 at 13:42 368 (1) 368 VDD = 1. 7. 7 CMOS Ampliﬁers RL Figure 7. with CS serving as a low impedance at the frequencies of interest. Assuming a power budget of 2 mW and an input impedance of 20 k . Select the values of C1 and CS so that their impedance is negligible at 1 MHz.cls v.84 must provide a voltage gain of 6. 2006] June 30.

(b) Design the circuit for a voltage gain of 15 and a power budget of 3 mW. 64.1 . 7.86. Assume RG 10rO1 jjrO2 and the dc level of the output must be equal to VDD =2. 7..83 VDD = 1. 2007 at 13:42 369 (1) Sec.1 for both . 2006] June 30. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.e.87 incorporates a degenerated PMOS current source.8 V RG C1 V in M1 RD C2 Vout 369 Figure 7.85 gain of 20 and a power budget of 2 mW.8 V R1 C1 M1 V in RS CS RD Vout Figure 7. The CS stage of Fig. where CB is very large and n = 0:5p = 0:1 V. Consider the circuit shown in Fig.5 V (i.82 VDD = 1. The degeneration must raise the output impedance of the current source to about 10rO1 such that the voltage gain remains nearly equal to the intrinsic gain of M1 . Assume = 0:1 V. 65.8 V R1 C1 M1 V in R2 RS RD Vout Figure 7.6 Chapter Summary VDD = 1.1 for both transistors and the maximum allowable level at the output is 1. (a) Calculate the voltage gain.cls v.84 VDD = 1. M2 must remain in saturation if Vout 1:5 V).8 V Vb M2 Vout V in M1 Figure 7. Assume = 0:1 V.

(b) Determine W=L1 to achieve a voltage gain of 30.88 67. Assuming a power budget of 1 mW and an overdrive of 200 mV for M1 . 2007 at 13:42 370 (1) 370 Chap. VDD = 1. design the circuit shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V RS Vb M2 Vout V in M1 Figure 7. VDD = 1.cls v.89 for an input impedance of 50 voltage gain of 5.89 . 66. Design the common-gate stage depicted in Fig. Assume a power budget of 3 mW. 7.8 V RD Vout V in M1 I1 and a Figure 7.87 transistors and a power budget of 2 mW.8 V M2 RG Vout V in M1 CMOS Ampliﬁers CB Figure 7. determine the values of W=L2 and RS so that the impedance seen looking into the drain of M2 is equal to 10rO1 . 2006] June 30.86 VDD = 1.88 for a voltage gain of 4. 7 VDD = 1.8 V M2 Vout V in M1 Figure 7. (a) If VB = 1 V. 7.

91 shows a self-biased common-gate stage. Design the CG stage shown in Fig. 2006] June 30. The circuit must provide a voltage gain of .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume RS 10=gm so that the input impedance remains approximately equal to 1=gm .93 for a voltage gain of 0.8 and a power budget of 2 mW. Select RS 10=gm and R1 + R2 = 20 k .8 V RD Vout V in M1 RS Figure 7. Consider the source follower shown in Fig. we have RS ID + VGS .92 such that it can accommodate an output swing of 500 VDD = 1. Design the source follower depicted in Fig..90 69. 7. Assume a power budget of 2 mW. Assume the output dc level is equal to VDD =2 and the input impedance exceeds 10 k . ID RD .90 such that M1 operates 100 mV away from the triode region while providing a voltage gain of 4. Vout can fall below its bias value by 250 mV without driving M1 into the triode region. VDD = 1.91 low impedance so that the voltage gain is still given by gm RD .6 Chapter Summary 371 68. where RG VDD = 1. 2007 at 13:42 371 (1) Sec. VTH + 250 mV = VDD . (Hint: since M1 is biased 250 mV away from the triode region.e.8 V RD V out V in M1 RS RG CG 10RD and CG serves as a Figure 7. 7. Assume a voltage gain of 4 and an input impedance of 50 .92 mVpp . 7.) 71. 70.94. 72. Design the circuit of Fig. 7.cls v. Figure 7. i.8 V RD V out V in M1 R1 RS R2 Figure 7. Design the circuit for a power budget of 5 mW and a voltage gain of 5. 7.

3 V (i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. respectively. 7 CMOS Ampliﬁers VDD = 1.95 with a power budget of 3 mW. 74.cls v.8 V RG V in X RS M1 C1 Vout 50 Ω RL Figure 7. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD .96 (a) Using hand calculations. VDD = 1.1 . SPICE Problems In the following problems. M2 serves as a current source. 2006] June 30. The circuit must operate VDD = 1.e. determine W=L1 such that gm1 = 100 ..8 at 100 MHz while consuming 3 mW. M2 must remain in saturation if VDS 2 0:3 V). In the circuit of Fig.9. 7.8 V V in M1 Vout Vb M2 Figure 7. design the circuit. Assume the input impedance exceeds 20 k . Assuming = 0:1 V.1 for both transistors. and a minimum allowable output of 0.93 VDD = 1. use the MOS models and source/drain dimensions given in Appendix A. 2007 at 13:42 372 (1) 372 Chap.94 0. In the source follower of Fig. 7.8 V RG V in M1 Vout RS Figure 7. 73.95.96. a voltage gain of 0. Design the circuit such that the dc voltage at node X is equal to VDD =2. . I1 is an ideal current source equal to 1 mA.8 V 10 k Ω I1 Vout W ( (1 L V in C1 1 kΩ M1 Figure 7.

6 Chapter Summary 373 (b) Select C1 for an impedance of 100 ( 1 k ) at 50 MHz. (d) What is the change in the gain if I1 varies by 20? 75.18 Figure 7. (d) What is the change in the gain if Vb changes by 50 mV? 76.. VDD 1 kΩ = Vout V in M1 M2 1 mA Vb Figure 7. 2007 at 13:42 373 (1) Sec. where M2 operates as a resistor. (b) Verify that the gain drops if the dc value of Vin is higher or lower than 1. 7. Consider the CS stage shown in Fig. M1 V in VDD = 1.18 Vout M2 0.97 employs a bias current source. 7.8 V yields an output dc level of 1 V. Figure 7. M2 VDD = 1.99 (a) Determine W2 such that an input dc level of 0.98 (a) Determine the voltage gain if Vin has a dc value of 1.cls v.99. (c) Simulate the circuit and obtain the voltage gain and output impedance at 50 MHz.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 V.97 (a) What value of Vin places M2 at the edge of saturation? (b) What value of Vin places M1 at the edge of saturation? (c) Determine the voltage gain if Vin has a dc value of 1.98 depicts a cascade of a source follower and a common-gate stage. 7. The source follower of Fig.5 V. (c) What dc value at the input reduces the gain by 10 with respect to that obtained in (a)? 77.8 V 10 0. 2006] June 30. M2 . What is the voltage gain under these conditions? (b) What is the change in the gain if the mobility of the NMOS device varies by 10? Can you explain this result using the expressions derived in Chapter 6 for the transconductance? .2 V. Assume Vb 1:2 V and W=L1 = W=L2 = 10 m=0:18 m.8 V W2 0.18 Figure 7.18 Vout V in M1 10 0.8 V 20 0.

100 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VDD = 1.18 Vout 10 0. 2007 at 13:42 374 (1) 374 Chap.cls v.18 M2 V in M1 Figure 7.100 and compare the sensitivities to the mobility.8 V W2 0. 2006] June 30. 7. Repeat Problem 77 for the circuit illustrated in Fig. 7 CMOS Ampliﬁers 78.

for example. General Concepts Op Amp Properties Linear Op Amp Circuits Noninverting Amplfier Inverting Amplifier Integrator and Differentiator Voltage Adder Nonlinear Op Amp Circuits Precision Rectifier Logarithmic Amplifier Square Root Circuit Op Amp Nonidealities DC Offsets Input Bias Currents Speed Limitations Finite Input and Output Impedances 8.” such circuits were used to study the stability of differential equations that arose in ﬁelds such as control or power systems. a plate that collected them. thus forming systems whose behavior followed a given differential equation. Similarly. developing op-amp-based circuits that perform interesting and useful functions. the analo-to-digital converter(s) used in digital cameras often employ op amps. we study the operational ampliﬁer as a black box. Vin1 and Vin2 are called the “noninverting” and “inverting” inputs. integration). and another that controlled the ﬂow—somewhat similar to MOSFETs. The outline is shown below. arriving at the equivalent circuit depicted in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8. 2 In modern integrated circuits.1(a). respectively. Since each op amp implemented a mathematical operation (e. We view the op amp as a circuit that ampliﬁes the difference between the two inputs. op amps typically have two outputs that vary by equal and opposite amounts. Op amps realized by vacuum tubes1 served as the core of electronic “integrators.1 General Considerations The operational ampliﬁer can be abstracted as a black box having two inputs and one output. the op amp symbol distinguishes between the two inputs by the plus and minus sign.. Vin2 : (8. The voltage gain is denoted by A0 : Vout = A0 Vin1 . Called “analog computers. the term “operational ampliﬁer” was born. Op amps ﬁnd wide application in today’s discrete and integrated electronics.cls v.g.2 Shown in Fig. 375 . well before the invention of the transistor and the integrated circuit. 8.1(b). 2006] June 30.1) 1 Vacuum tubes were amplifying devices consisting of a ﬁlament that released electrons. In the cellphone studied in Chapter 1.. In this chapter. 2007 at 13:42 375 (1) 8 Operational Ampliﬁer As A Black Box The term “operational ampliﬁer” (op amp) was coined in the 1940s.” etc. integrated op amps serve as building blocks in (active) ﬁlters.” “differentiators.

brings Vin1 and Vin2 close to each other.A0 Vin2 [Fig. Example 8. the ampliﬁer stages studied in Chapters 5 and 7 have only one input node (i. After all.3 is called a “unity-gain” buffer. Vin2 = VA : 0 (8. With Vin2 = 0. 8. 2 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.e. 2007 at 13:42 376 (1) 376 V in1 V in2 Vout Chap. 8.. We can then consider the effect of the op amp “nonidealities” on the performance. the op amp.2) In other words. It is instructive to plot Vout as a function of one input while the other remains at zero. Vin2 . we have Vout = A0 Vin1 . Vout = A0 Vin1 . .1(a) is always small: out Vin1 .g.2 Op amp characteristics from (a) noninverting and (b) inverting inputs to output. they sense the input voltage with respect to ground). Since realistic circuits produce ﬁnite output swings. Ampliﬁer circuits having two inputs are studied in Chapter 10.1 (a) Op amp symbol. How does the “ideal” op amp behave? Such an op amp would provide an inﬁnite voltage gain. 8 Operational Ampliﬁer As A Black Box Vout V in1 V in2 (a) (b) A 0 (V in1 − V in2 ) Figure 8.1 The circuit shown in Fig. On the other hand. the difference between Vin1 and Vin2 in Fig. The reader may wonder why the op amp has two inputs. obtaining the behavior shown in Fig. the ﬁrst-order analysis of an op-amp-based circuit typically begins with this idealization. quickly revealing the basic function of the circuit. forms the foundation for many circuit topologies that would be difﬁcult to realize using an ampliﬁer having Vout = AVin . As seen throughout this chapter. an inﬁnite input impedance. and inﬁnite speed.2(a). revealing a negative slope and hence an “inverting” behavior.. 2006] June 30. 8. 8. Following the above idealization. The very high gain of the op amp leads to an important observation. Vout V in1 Vout A0 V in1 V in2 Vout −A 0 Vout V in2 (a) (b) Figure 8. if Vin1 = 0. a zero output impedance. It must be borne in mind that Vin1 . The positive slope (gain) is consistent with the label “noninverting” given to Vin1 .cls v. the principal property of the op amp. we may say Vin1 = Vin2 if A0 = 1. Note that the output is tied to the inverting input. (b) equivalent circuit. Determine the output voltage if Vin1 = +1 V and A0 = 1000. along with the circuitry around it. Vin2 becomes only inﬁnitesimally small as A0 ! 1 but cannot be assumed exactly equal to zero. Vout = . e. In fact.2(b)]. A common mistake is to interpret Vin1 = Vin2 as if the two terminals Vin1 and Vin2 are shorted together.

Exercise What value of A0 is necessary so that the output voltage is equal to 0. In this example. the gain approaches unity as A0 becomes large. (8.5) 1000. hence the term “unity-gain buffer. (8. 2006] June 30. we study a number of circuits that utilize op amps to process analog signals. A0 = Vin = 1 V. and Vout = 0:999 V.cls v. Vin2 = A0 Vin .4 to explicitly indicate the supply voltages. 8. Vin2 is small compared to Vin and Vout .2 Op-Amp-Based Circuits A 0 = 1000 +1V 377 V in Vout Figure 8. Vout : That is.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. in which case VEE = 0.3) (8. we ﬁrst assume an ideal op amp to understand the underlying principles and subsequently examine the effect of the ﬁnite gain on the performance. Solution If the voltage gain of the op amp were inﬁnite.” For a ﬁnite gain.9999? Op amps are sometimes represented as shown in Fig. 2007 at 13:42 377 (1) Sec. Indeed. For example. the difference between the two inputs would be zero and Vout = Vin . 8. VCC V in1 V in2 VEE Vout Figure 8. 8.4) Vout = A0 : Vin 1 + A0 As expected. In each case. VEE and VCC .2 Op-Amp-Based Circuits In this section.4 Op amp with supply rails. an op amp may operate between ground and a positive supply. . we write Vout = A0 Vin1 .3 Unity-gain buffer. Vin1 .

5. Shown in Fig. in some applications (e. Op-ampbased circuits can provide such precision. However.g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.6(a). 8 Operational Ampliﬁer As A Black Box 8. if R2 approaches zero.3 because the ideal op amp draws no current at its inputs. 8. a much more precise gain (e.3 As a result.6(b). this occurs because the circuit reduces to the op amp itself.7) (8.6) Vin1 Vin2 R R2 R Vout . if R1 and R2 increase by 20. Resistor R1 simply loads the output node. Study the noninverting ampliﬁer for two extreme cases: R1 =R2 Example 8. The idea of creating dependence on only the ratio of quantities that have the same dimension plays a central role in circuit design. Of course. the voltage gain itself may suffer from a variation of.9) Due to the positive gain. e. if R2 approaches inﬁnity.. 2007 at 13:42 378 (1) 378 Chap. yielding a zero drop across R1 and hence Vin2 = Vout . e.5 Noninverting ampliﬁer. 8. with no effect on the gain if the op amp is ideal.1 Noninverting Ampliﬁer Recall from Chapters 5 and 7 that the voltage gain of ampliﬁers typically depends on the load resistor and other parameters that may vary considerably with temperature or process.000) is required. the noninverting ampliﬁer consists of an op amp and a voltage divider that returns a fraction of the output voltage to the inverting input: V in1 A0 V in V in2 R1 R2 Vout Figure 8.g..g. Illustrated in Fig.g. we note that Vout =Vin ! 1. 3 Variation with process means the circuits fabricated in different “batches” exhibit somewhat different characteristics.cls v. say. . R1 =R2 remains constant.2. this case in fact reduces to the unity-gain buffer of Fig. 1+ 2 and hence (8. the voltage gain depends on only the ratio of the resistors.2 Solution = 1 and R1 =R2 = 0. If R1 =R2 ! 1.. we have Vout =Vin ! 1. Vin2 = R R2 R Vout : 1+ 2 Since a high op amp gain translates to a small difference between Vin1 and Vin2 . If R1 =R2 ! 0. 20. 2. A/D converters).. 8. 2006] June 30.” Interestingly. as depicted in Fig. with no fraction of the output fed back to the input. 8. the circuit is called a “noninverting ampliﬁer. we have (8.8) Vout 1 + R1 : Vin R2 (8.

6 Noninverting ampliﬁer with (a) zero and (b) inﬁnite value for R2 . 8.12) Vin R2 R2 A0 Called the “gain error.11) indicates that the ﬁnite gain of the op amp creates a small error in the value of Vout =Vin .6): (8. What is the actual voltage gain? R2 suffer from a Let us now take into account the ﬁnite gain of the op amp. A0 . and substitute for Vin2 from (8.” the term 1 + R1 =R2 =A0 must be minimized according to each application’s requirements. If much greater than unity. 2007 at 13:42 379 (1) Sec. this result reduces to (8.. Based on the model shown in Fig. for 1: Vout = A0 (8.2 Op-Amp-Based Circuits 379 Vout V in R1 R2 = 0 (a) (b) Vout V in R1 R2 = Figure 8. the term A0 R2 =R1 + R2 can be factored from the denominator to permit the approximation 1 + . 2006] June 30.9) if A0 R2 =R1 + R2 1. we write Vin1 . R1 = 1 0:05R2 ).10) the “open-loop” gain and the latter the “closed-loop” gain. 1 + R1 1 : (8.1(b). 8. Vout =Vin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.11) Vin 1 + R2 A0 : R1 + R2 As expected.00 but the R1 and mismatch of 5% (i. Equation (8. . and the gain of the overall ampliﬁer.e. To avoid confusion between the gain of the op amp. Exercise Suppose the circuit is designed for a nominal gain of 2. we call the former Vout 1 + R1 1 . Vin2 A0 = Vout .1 1 .

.

3 A noninverting ampliﬁer incorporates an op amp having a gain of 1000. For a nominal gain of 5. or (b) 50. Example 8. Determine the gain error if the circuit is to provide a nominal gain of (a) 5. we have 1 + R1 =R2 Solution .

13) . 1 1 + R1 A = 0:5: R2 0 = 5. obtaining a gain error of: (8.

if 1 + R1 =R2 = 50. 8 Operational Ampliﬁer As A Black Box On the other hand. then . 2007 at 13:42 380 (1) 380 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30.

For a nonideal op amp. 0 . i. the entire input voltage appears across R2 . 8. R1 R2 X Vout V in V in Virtual Ground (a) (b) V in R2 R2 X R1 Vout A R2 R1 (c) B Figure 8. 8. producing a current of Vin =R2 .2 Inverting Ampliﬁer Depicted in Fig.7(b)]. Since the left terminal of R1 remains at zero and the right terminal at Vout .e. For this reason.” Under this condition. the “inverting ampliﬁer” incorporates an op amp along with resistors R1 and R2 while the noninverting input is grounded. Vin2 ! 0.. (c) analogy with a seesaw.R1 : Vin R2 (8. Recall from Section 8.7 (a) Inverting ampliﬁer. R 1 1 + R1 A = 5: 2 0 (8.16) . Vout = Vin R1 R2 yielding (8. the I/O impedances are derived in Problem 7.2. then a ﬁnite output swing translates to Vin1 .15) Vout = . (b) currents ﬂowing in resistors. the noninverting ampliﬁer exhibits an inﬁnite input impedance and a zero output impedance.7(a). a higher closed-loop gain inevitably suffers from less accuracy. node X bears a zero potential even though it is not shorted to ground. node X is called a “virtual ground. 8.1 that if the op amp gain is inﬁnite. which must then ﬂow through R1 if the op amp input draws no current [Fig.14) In other words. With an ideal op amp. Exercise Repeat the above example if the op amp has a gain of 500.

7(a) exhibits an input impedance equal to R2 —as can be seen from the input current. Such a short in Fig.VX =R2 and VX . That is.R Vout = . a lower R2 results in a greater gain but a smaller input impedance. 8.Vout =A0 for VX . yielding Vout = 0..g. thereby experiencing only small variations with temperature and process. 2007 at 13:42 381 (1) Sec. Vout R2 V in R1 Figure 8. displaying a similarity with the noninverting circuit but with the input applied at a different point. 8. We note from Fig. 1 1 + R2 1 + 1 Vin A0 R1 A0 (8. does not move). The above development also reveals why the virtual ground cannot be shorted to the actual ground. 8. where the point between the two arms is “pinned” (e. This behavior is similar to a seesaw [Fig.” As with its noninverting counterpart. Moreover. 8. the circuit is called the “inverting ampliﬁer. It is interesting to note that the inverting ampliﬁer can also be drawn as shown in Fig.8. 2006] June 30. This trade-off sometimes makes this ampliﬁer less attractive than its noninverting counterpart. 8. In contrast to the noninverting ampliﬁer.cls v. allowing displacement of point A to be “ampliﬁed” (and “inverted”) at point B .7(b) would force to ground all of the current ﬂowing through R2 . Let us now compute the closed-loop gain of the inverting ampliﬁer with a ﬁnite op amp gain.2 Op-Amp-Based Circuits 381 Due to the negative gain.7(c)]. If the inverting input of the op amp were not near zero potential. 8. Vin2 = .20) .7(b).17) (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vout = A0 Vin1 . the gain of this circuit is given by the ratio of the two resistors. then neither Vin =R2 nor Vout =R1 would accurately represent the currents ﬂowing through R2 and R1 . the topology of Fig.8 Inverting ampliﬁer. respectively. we obtain (8. 8.19) (8.18) 1 1 1 + R2 : 2 R1 + A0 R1 Factoring R2 =R1 from the denominator and assuming 1 + R1 =R2 =A0 =. Vin =R2 . respectively. Vout =R1 .A0 VX : Equating the currents through R2 and R1 and substituting . It is important to understand the role of the virtual ground in this circuit. in Fig.7(a) that the currents ﬂowing through R2 and R1 are given by Vin .

a higher closed-loop gain ( . we have (8.R1 =R2 ) is accompanied with a greater gain error. .21) As expected. R1 1 . Note that the gain error expression is the same for noninverting and inverting ampliﬁers. Vout . 1 1 + R1 : Vin R2 A0 R2 1.

8. We have R1 = 4 2 .4 Solution Since both the nominal gain and the gain error are given. and an input impedance of at least 10 k . 8 Operational Ampliﬁer As A Black Box Design the inverting ampliﬁer of Fig. we must ﬁrst determine the minimum op amp gain. Example 8. 2007 at 13:42 382 (1) 382 Chap.7(a) for a nominal gain of 4. 2006] June 30. a gain error of 0:1.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

2. 8. it is possible to employ complex impedances instead (Fig. In analogy with (8.26) Exercise Repeat the above example for a gain error of 1% and compare the results.23) A0 = 5000: Since the input impedance is approximately equal to R2 . RR 1 1 + 1 = 0:1: A0 R2 Thus. (8.3 Integrator and Differentiator Our study of the inverting topology in previous sections has assumed a resistive network around the op amp.22) (8. In the above example.4Vin =5000.16).9 Circuit with general impedances around the op amp. we can write Z1 Z2 Vout V in Figure 8. 8. Vout . Z1 . the virtual ground experiences a voltage of . Vin Z2 (8.25) (8. In general. our assumption leads to an error of about 0:08—an acceptable value in most applications.24) R2 = 10 k R1 = 40 k : (8. yielding an input current of Vin + 4Vin =5000=R1.Vout =5000 .9). we choose: (8. How accurate is this assumption? With A0 = 5000. That is. we assumed the input impedance is approximately equal to R2 .27) .

Integrator Suppose in Fig.10 Integrator. 8. and many other applications. As mentioned at the beginning of the chapter. 8. 8.C dVout 1 R1 dt and hence (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. electronic integrators ﬁnd usage in analog ﬁlters. Equating the currents ﬂowing through R1 and C1 gives Vout Vin f Figure 8. R 1C Z 1 1 Vin dt: (8. 4 Pole frequencies are obtained by setting the denominator of the transfer function to zero. If Z1 or Z2 is a capacitor. Z1 C1 s.1 and Z2 = R1 . 2007 at 13:42 383 (1) Sec. This is to be expected: the capacitor impedance becomes very large at low frequencies. Z1 is a capacitor and Z2 a resistor (Fig.29) indicates that Vout =Vin approaches inﬁnity as the input frequency goes to zero. 8. With an ideal op amp.29) = . This can also be seen in the time domain. Vin = .10).30) Vout = . Example 8.9. .4 the circuit operates as an integrator (and a low-pass ﬁlter). C1 s Vin R1 1 (8. control systems.R 1 s: C 1 1 Providing a pole at the origin.5 Plot the output waveform of the circuit shown in Fig.11 Frequency response of integrator. Today. 2006] June 30.31) Equation (8. we have C1 R1 X Vout V in = Figure 8. Assume a zero initial condition across C1 and an ideal op amp.28) (8. Figure 8.2 Op-Amp-Based Circuits 383 where the gain of the op amp is assumed large.12(a). two interesting functions result. integrators originally appeared in analog computers to simulate differential equations.11 plots the magnitude of Vout =Vin as a function of frequency. That is. Vout = .cls v. approaching an open circuit and reducing the circuit to the open-loop op amp.

the exponential response of Fig.32) (8. The ideal integration expressed by (8. On the other hand. When the input jumps from 0 to V1 . 8 Operational Ampliﬁer As A Black Box V1 0 V in Tb C1 V1 0 I C1 V1 R1 0 0 V in Tb R1 X Vout V1 R1 Vout − 0 V1 R 1C1 (b) − V1 T b R 1C1 t (a) Figure 8. 8. which decreases as Vout rises.V1 Tb =R1 C1 (proportional to the area under the input pulse) thereafter. the voltage across the capacitor and hence Vout remain equal to . 2007 at 13:42 384 (1) 384 Chap. so do the currents through R1 and C1 .13.12 (a) Integrator with pulse input. a constant current equal to V1 =R1 begins to ﬂow through the resistor and hence the capacitor. The above example demonstrates the role of the virtual ground in the integrator. R 1C Vin dt 1 1 1 = .12(b)]: Solution Vout = . RVC t 0 t Tb : 1 1 Z (8. for a large R1 C1 product. 8. Exercise Repeat the above example if V1 is negative. VX = VX . the RC ﬁlter creates a current equal to Vin . we have Vin . forcing the right plate voltage of C1 to fall linearly with time while its left plate is pinned at zero [Fig.) When Vin returns to zero.13(b) becomes slow enough to be approximated as a ramp. We may therefore consider the RC ﬁlter as a “passive” approximation of the integrator. (b) input and output waveforms. Denoting the potential of the virtual ground node in Fig. let us compare the integrator with a ﬁrst-order RC ﬁlter in terms of their step response.33) (Note that the output waveform becomes “sharper” as R1 C1 decreases. In fact. 8. Vout 1 R1 C1 s (8. 2006] June 30. To gain more insight. the integrator forces a constant current (equal to V1 =R1 ) through the capacitor.34) .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We now examine the performance of the integrator for A0 1. leading to an increasingly slower voltage variation across C1 . Thus.32) occurs because the left plate of C1 is pinned at zero.10 with VX .cls v. As illustrated in Fig. Vout =R1 . 8.

out : A 0 (8.39) (8.38) RX and CX is arbitrary so long as their product satisﬁes (8.2 Op-Amp-Based Circuits C1 385 V1 0 V in R1 X Vout V1 R1 0 V1 V in R1 Vout V 1 − V out R1 C1 Figure 8. 8.13 Comparison of integrator with and RC circuit.14 Simple low-pass ﬁlter.37) Such a circuit is sometimes called a “lossy” integrator to emphasize the nonideal gain and pole position.38). RX Vout CX V in Figure 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.37). and V VX = . Determine RX and CX such that this circuit exhibits the same pole as that of the above integrator.36) 1 + 1 + 1 R C s . 2007 at 13:42 385 (1) Sec. Vin 1 1 A0 A0 revealing that the gain at s = 0 is limited to A0 (rather than inﬁnity) and the pole frequency has moved from zero to sp = A +.6 Recall from basic circuit theory that the RC ﬁlter shown in Fig.14 contains a pole at .1R C : 0 1 1 1 (8.1 (8. RX CX = A0 + 1R1 C1 : The choice of choice is (8.35) Thus. .1=RX CX . 2006] June 30. An interesting RX = R1 CX = A0 + 1C1 : (8.cls v. Vout = . 8. Solution From (8. Example 8.40) It is as if the op amp “boosts” the value of C1 by a factor of A0 + 1.

9. out C1 dVin = .cls v. From a time-domain perspective. 2006] June 30.16 Frequency response of differentiator.R1 C1 dVin : dt Example 8. R1 1 Vin C1 s = .17(a) assuming an ideal op amp. 2007 at 13:42 386 (1) 386 Chap.16 plots the magnitude of Vout =Vin as a function of frequency. Figure 8. 8. VR . we can equate the currents ﬂowing through C1 and R1 : Vout Vin R 1 C1 f Figure 8.7 Plot the output waveform of the circuit shown in Fig.43) Vout = . Vin = 0 and Vout = 0 (why?).42) Exhibiting a zero at the origin. . we have R1 C1 V in X Vout Figure 8. Vout = .15 Differentiator.44) At t = 0. Z1 is a resistor and Z2 a capacitor (Fig.45) .15). (8.R1 C1 s: (8. When Vin jumps to V1 . the circuit acts as a differentiator (and a high-pass ﬁlter). 8. 8. an impulse of current ﬂows through C1 because the op amp maintains VX constant: Solution Iin = C1 dVin dt (8.41) (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. dt 1 arriving at (8. 8 Operational Ampliﬁer As A Black Box Exercise What value of RX is necessary if CX = C1 ? Differentiator If in the general topology of Fig.

Iin R1 = R1 C1 V1 t: (8.47) (8. Vin returns to zero. on the other hand.2 Op-Amp-Based Circuits V1 0 387 V in I C1 R1 V1 0 0 Tb C1 V in Tb I in X Vout Vout 0 0 (a) (b) t Figure 8. generating an output given by (8.R1 C1 V1 t: Figure 8. In the RC ﬁlter. In the ideal differentiator. . (b) input and output waveforms. 8. node X is not “pinned. = C1 V1 t: The current ﬂows through R1 .49) (8. 8.50) It follows that Vout = . the output exhibits neither an inﬁnite height (limited by the supply voltage) nor a zero width (limited by the op amp nonidealities). again creating an impulse of Iin = C1 dVin dt = C1 V1 t: (8.48) t = Tb.52) We can therefore say that the circuit generates an impulse of current C1 V1 t and “ampliﬁes” it by R1 to produce Vout . At current in C1 : (8. of course. 2007 at 13:42 387 (1) Sec.51) (8.17 (a) Differentiator with pulse input.46) Vout = .17(b) depicts the result.cls v. 2006] June 30. Exercise Plot the output if V1 is negative.Iin R1 = . It is instructive to compare the operation of the differentiator with that of its “passive” counterpart (Fig.18). In reality. the virtual ground node permits the input to change the voltage across C1 instantaneously.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.” thereby following the input change at t = 0 and limiting the initial current in the circuit to V1 =R1 .

56) (8. 2007 at 13:42 388 (1) 388 Chap.54) sp = . 2006] June 30.55). the circuit contains a pole at (8. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. R1 V1 0 C1 V in I in X Vout 0 V1 V in C1 X R1 V1 Vout (a) (b) Figure 8. R1 C1 . the passive circuit can be viewed as an approximation of the ideal differentiator. 8 Operational Ampliﬁer As A Black Box If the decay time constant.15 gives Vin .18 Comparison of differentiator and RC circuit. Vout : 1 R1 C1 s Substituting .55) Example 8. Solution The capacitor and resistor operate as a voltage divider: Vout = RX Vin RX + 1 CX s X Xs = R RC Cs + 1 : X X (8. is sufﬁciently small.8 Determine the transfer function of the high-pass ﬁlter shown in Fig. Let us now study the differentiator with a ﬁnite op amp gain.Vout =A0 for VX .53) Vout = . CX V in RX Vout RX and Figure 8. A0 + 1 : RC 1 1 (8.19 and choose CX such that the pole of this circuit coincides with (8. 8.R1C1 s Vin 1 + 1 + R1 C1 s : A0 A0 In contrast to the ideal differentiator.57) .19 Simple high-pass ﬁlter. VX = VX . we have (8. Equating the capacitor and resistor currents in Fig.cls v.

(8.60) Exercise What is the necessary value of CX if RX = R1 ? An important drawback of differentiators stems from the ampliﬁcation of high-frequency noise. In audio recording. for example. Shown in Fig. The reader may wonder if it is possible to employ a conﬁguration similar to the noninverting ampliﬁer of Fig. 8.58) A0 + 1 1 RX CX = R1 C1 : One choice of RX and CX is 1 RX = A R+ 1 0 CX = C1 .20. 8. and these voltages must then be added to create the overall musical piece.61) if the op amp is ideal. Unfortunately. 8.5 to avoid the sign reversal.55). For this (8.16. As suggested by (8. This operation is called “mixing” in the audio industry. such a circuit provides the following transfer function Vout V in Z2 Z1 Figure 8. 8. in“noise cancelling” headphones. 8. 8. 2007 at 13:42 389 (1) Sec. Z1 = R1 and Z2 = 1=C2 s yield a nonideal differentiator (why?).2 Op-Amp-Based Circuits 389 The circuit therefore exhibits a zero at the origin (s pole to be equal to (8.20 Op amp with general network. 2006] June 30. Vout = 1 + Z1 .1=RX CX . Vin Z2 (8. a number of microphones may convert the sounds of various musical instruments to voltages. the environmen- 5 The term “mixing” bears a completely different meaning in the RF and wireless industry.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For example. The general topology of Fig.5 For example. we require = 0) and a pole at .9 and its integrator and differentiator descendants operate as inverting circuits.2.59) (8. this function does not translate to ideal integration or differentiation.cls v.42) and Fig.4 Voltage Adder The need for adding voltages arises in many applications. . the increasingly larger gain of the circuit at high frequencies tends to boost noise in the circuit.

The two currents add at the virtual ground node and ﬂow through RF : RF V1 V2 R1 X R2 Vout Figure 8.Vout : R1 R2 RF That is.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if R1 .21 depicts a voltage adder (“summer”) incorporating an op amp. and R1 and R2 carry currents proportional to V1 and V2 .21 Voltage adder.RF R1 + R2 : 1 2 For example. With an ideal op amp. (8. VX = 0. 2006] June 30. Figure 8. V1 + V2 = .62) V V Vout = . 2007 at 13:42 390 (1) 390 Chap. respectively. 8 Operational Ampliﬁer As A Black Box tal noise is applied to an inverting ampliﬁer and subsequently added to the signal so as to cancel itself.cls v.

The behavior of the circuit in the presence of a ﬁnite op amp gain is studied in Problem 31. This property also proves useful in many applications. 8.g.. That is.e. 8. It is possible to place a diode around an op amp to form a “precision rectiﬁer. We note that the high gain of the op amp ensures that node X tracks Vin (for both positive and negative cycles).22(a)]. in audio recording it may be necessary to lower the “volume” of one musical instrument for part of the piece.3. Equation (8. 8. For example. The virtual ground property plays an essential role here as well. Extension to more than two voltages is straightforward..63) = R2 = R. the diodes remain off and the output voltage remains at zero.” i. This can be .e. Let us begin with a unity-gain buffer tied to a resistive load [Fig. “break” the connection between the output of the op amp and its inverting input.63) indicates that V1 and V2 can be added with different weightings: RF =R1 and RF =R2 .3 Nonlinear Functions It is possible to implement useful nonlinear functions through the use of op amps and nonlinear devices such as transistors. e.7 V. (8. This drawback prohibits the use of the circuit in high-precision applications. then R Vout = . a circuit that rectiﬁes even very small signals.R F V1 + V2 : (8. if a small signal received by a cellphone must be rectiﬁed to determine its amplitude. if the input signal amplitude is less than approximately 0.1 Precision Rectiﬁer The rectiﬁer circuits described in Chapter 3 suffer from a “dead zone” due to the ﬁnite voltage required to turn on the diodes. a task possible by varying R1 and R2 . Now suppose we wish to hold X at zero during negative cycles..64) This circuit can therefore add and amplify voltages. i. respectively.

Example 8. (b) circuit waveforms. the op amp creates VY . turning D1 barely on but with little current so that VX 0. Figure 8. That is.22(b). V in V in X Vout V in X V out R1 R1 D1 t Y VY V D. D1 turns off and the op amp produces a very large negative output (near the negative supply rail) because its noninverting input falls below its inverting input.VD. 8.23 (a) Inverting precision rectiﬁer. where D1 is inserted in the feedback loop. (b) t VX t t For Vin = 0. (b) precision rectiﬁer.3 Nonlinear Functions 391 accomplished as depicted in Fig. VX 0 and VY . and X is a virtual ground. Thus. Figure 8.23(a) in response to an input sinusoid.on t V out t (a) (b) (c) Figure 8. VY only slightly decreases to allow D1 to carry the higher current. For Vin 0. 2007 at 13:42 391 (1) Sec.on .23(b) shows the resulting waveforms. 8.22 (a) Simple op amp circuit.on for positive input cycles.on (a) Figure 8. 8. the op amp raises VY to approximately VD1. which is not possible. thus raising the current through R1 .on so that D1 is barely on. What happens if Vin becomes slightly negative? For Vout to assume a negative value. Solution . (c) circuit waveforms. let us ﬁrst assume that Vin = 0. Note that Vout is sensed at X rather than at the output of the op amp.9 Plot the waveforms in the circuit of Fig. D1 turns off (why?). That is. D1 must carry a current from X to Y . 2006] June 30.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. leading to VX = Vin and driving VY to a very positive value. R1 carries little current. Now if Vin becomes slightly positive. As Vin becomes positive.VD. To analyze the operation of this circuit. even small positive levels at the input appear at the output. In its attempt to minimize the voltage difference between the noninverting and the inverting inputs. VY rises further so that the current ﬂowing through D1 and R1 yields Vout Vin . V in D1 R1 X Y V in VY −V D.22(c) plots the circuit’s waveforms in response to an input sinusoid.

so do the currents ﬂowing through R1 and Q1. 8. It is therefore necessary to ensure Vin remains positive.2 V to +2 V. the virtual ground plays an essential role here as it guarantees the current ﬂowing through Q1 is xactly proportional to Vin .65) The output is therefore proportional to the natural logarithm of Vin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In the actual circuit. V in R1 R1 X V in Q1 Vout Figure 8. Note that Q1 operates in the active region because both the base and the collector remain at zero. Since the base is at zero.cls v. the emitter voltage must fall below zero to provide a greater collector current. With an ideal op amp. 2006] June 30. Q1 cannot carry a “negative” current. and Vout approaches the negative supply rail. Equation (8. the loop around the op amp is broken.24.24 in fact implements the inverse function of the exponential characteristic.3.24 Logarithmic ampliﬁer.VBE and hence VBE = VT ln Vin =R1 : I S (8.22(b) and 8. Also. Additional techniques can resolve this issue (Problem 39).23(a) lower the speed of the circuit as the op amp must “recover” from a saturated value before it can turn D1 on again.66) . It may be desirable in such cases to amplify weak signals and attenuate (“compress”) strong signals.2 Logarithmic Ampliﬁer Consider the circuit of Fig.3 Square-Root Ampliﬁer Recognizing that the logarithmic ampliﬁer of Fig. hence a logarithmic dependence. where a bipolar transistor is placed around the op amp. Vout = . 8.66) predicts that Vout is not deﬁned. 8.VT ln R in : I 1 S (8. 2007 at 13:42 392 (1) 392 Chap. Logarithmic ampliﬁers (“logamps”) prove useful in applications where the input signal level may vary by a large factor.3. 8. The large swings at the output of the op amp in Figs. we surmise that replacing the bipolar transistor with a MOSFET V Vout = . requiring an increase in VBE . 8 Operational Ampliﬁer As A Black Box Exercise Repeat the above example for a triangular input that goes from . R1 carries a current equal to Vin =R1 and so does Q1 . As with previous linear and nonlinear circuits. The negative sign in (8. The effect of ﬁnite op amp gain is studied in Problem 41. 8. The reader may wonder what happens if Vin becomes negative. Thus.66) is to be expected: if Vin rises.

Vin = 1 C W V . (c) representation of offset. For example. Illustrated in Fig.25 Square-root circuit. . Vos .4. (8. op amps suffer from other imperfections that may affect the performance signiﬁcantly. M1 operates in saturation. VTH : n Cox W R1 L 2Vin (8. 8. we deal with such nonidealities. 8. With its gate and drain at zero. 8.” Vout Vos V in1 − V in1 Vos (a) (b) (c) Vout Figure 8. V 2 : R1 2 n ox L GS TH (Channel-length modulation is neglected here.) Since VGS = . for Vout = 0. as conceptually shown in Fig. In practice. (b) mismatch between input devices.25.1 DC Offsets The op amp characteristics shown in Fig. 8.e. 2007 at 13:42 393 (1) Sec.26(a).Vout . 8. placing M1 at the edge of conduction. 2006] June 30.68) 8.u t If Vin is near zero. however. i. then Vout remains at . the input difference must be raised to a certain value.4 Op Amp Nonidealities Our study in previous sections has dealt with a relatively idealized op amp model—except for the ﬁnite gain—so as to establish insight.cls v. As Vin becomes more positive. What causes offset? The internal circuit of the op amp experiences random asymmetries (“mismatches”) during fabrication and packaging. . called the input “offset voltage.4 Op Amp Nonidealities 393 leads to a “square-root” ampliﬁer.2 imply that Vout = 0 if Vin1 = Vin2 .26 (a) Offset in an op amp. a zero input difference may not give a zero output difference! Illustrated in Fig.VTH .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In this section. Vout falls to allow M1 to carry a greater current. In reality..67) v u Vout = . such a circuit requires that M1 carry a current equal to Vin =R1 : M1 Vout V in R1 X Figure 8. the characteristic is “offset” to the right or to the left.

Depicted in Fig. Vout = 1 + R1 Vin + Vos : R2 .26(b). the bipolar transistors sensing the two inputs may display slightly different base-emitter voltages. Vos can appear at either input with arbitrary polarity. The same effect occurs for MOSFETs.27. We model the offset by a single voltage source placed in series with one of the inputs [Fig.2 in the presence of op amp offsets. 8. 2006] June 30. 8 Operational Ampliﬁer As A Black Box 8. 2007 at 13:42 394 (1) 394 Chap.27 Offset in noninverting ampliﬁer. the noninverting ampliﬁer now sees a total input of Vin + Vos . 8. Why are DC offsets important? Let us reexamine some of the circuit topologies studied in Section 8. thereby generating Vos V in R1 R2 Vout Figure 8.cls v. Since offsets are random and hence can be positive or negative.26(c)].BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

8. (8. Solution From Fig. The second stage 6 The reader can show that placing Vos in series with the inverting input of the op amp yields the same result..27. what is the accuracy of the weighing station? Solution An offset of 2 mV corresponds to a load of 10 kg. Explain what happens if op amp A1 exhibits an offset of 2 mV. .27. Exercise What offset voltage is required for an accuracy of 1 kg? DC offsets may also cause “saturation” in ampliﬁers.11 An electrical engineering student constructs the circuit shown in Fig. Example 8. microvolt signals) can be detected.e. generating a dc level of 200 mV at node X (if the microphone produces a zero dc output).28 to amplify the signal produced by a microphone. If the pressure meter generates 20 mV for every 100 kg of load and if the op amp offset is 2 mV. we recognize that the ﬁrst stage ampliﬁes the offset by a factor of 100.6 Example 8. thus incurring accuracy limitations. 8.10 A truck weighing station employs an electronic pressure meter whose output is ampliﬁed by the circuit of Fig. The targeted gain is 104 so that very low level sounds (i. The following example illustrates this point. We therefore say the station has an error of 10 kg in its measurements.69) In other words. 8. the circuit ampliﬁes the offset as well as the signal.

28 Two-stage ampliﬁer. the transistors in the op amp fail to provide gain and the output saturates [Fig.61)] and the integral of the input [the second term in (8. generating an output that tends to +1 or . as Vout approaches the positive or negative supply voltages. This is studied in Problem 49. The problem of offsets proves quite serious in integrators.7(a) in a similar manner. 8.29(b)].70) (8. Figure 8. Now the effect of Vos at the output is given by (8. where resistor R2 is placed in parallel with C1 .29(c) are similar at low frequencies: Vout = Vos 1 + R2 : R1 For example. . 8.5 and 8.cls v. 8.1 depending on the sign of Vos . We can therefore express Vout in the time domain as Vos dt Vout = Vos + R 1C 1 1 0 V = Vos + R os t. If A2 operates with a supply voltage of. now ampliﬁes VX by another factor of 100.29(a) integrates the offset and reaches saturation.29(a)]. 8.61)]. 3 V. We say the second stage is saturated.29(c) depicts a modiﬁcation. We now examine the effect of offset on the integrator of Fig. thereby attempting to generate Vout = 20 V. 2006] June 30. the circuit of Fig.10.61) that the response to this “input” consists of the input itself [the unity term in (8. the second op amp drives its transistors into saturation (for bipolar devices) or triode region (for MOSFETs).) Exercise Repeat the above example if the second stage has a voltage gain of 10. the output cannot exceed this value. 8. In other words. DC offsets impact the inverting ampliﬁer of Fig.71) where the initial condition across C1 is assumed zero. What happens at the output? Recall from Fig.. Of course. Even in the presence of an input signal. if Vos = 2 mV and R2 =R1 least remains away from saturation. 2007 at 13:42 395 (1) Sec.4 Op Amp Nonidealities A1 X 10 k Ω 100 Ω 10 k Ω 100 Ω 395 A2 Vout Figure 8. 8. the circuit integrates the op amp offset.9) because the circuits of Figs. Suppose the input is set to zero and Vos is referred to the noninverting input [Fig. 8. (The problem of offset ampliﬁcation in cascaded stages can be resolved through ac coupling.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8. (8.20 and Eq. and its gain falls to a small value. say. 1 C1 Zt (8.

then Vout contains a dc error of 202 mV. but at .72) = 100. (8.

R2 (8. 8 Operational Ampliﬁer As A Black Box Vout R1 VCC Vout VCC V os VEE t (a) (b) R2 C1 R1 Vout V in V os R1 R2 C1 Vout (c) (d) Figure 8.30. we arrive at the circuit in Fig. 2007 at 13:42 396 (1) 396 C1 Chap. viewing the circuit as shown in Fig. the circuit now resembles the inverting ampliﬁer of Fig. the integration function holds for input frequencies much higher than 1=R2 C1 .74) Vin R1 C1 s That is. If the input signal frequencies of interest lie well above this value. Using superposition and setting Vin to zero. (b) output waveform.72) whereas R2 C1 must be sufﬁciently large so as to negligibly impact the signal frequencies of interest. on the other hand. 8. 8. IB 1 = IB 2 .7(a). The current IB2 . (d) determination of transfer function.4. then R2 C1 s 1 and Vout = .cls v.73) Vin R1 R2 C1 s + 1 : Thus. How does R2 affect the integration function? Disregarding Vos . ﬂows through R1 and R2 . introducing an error. Interestingly.1=R2 C1 rather than at the origin.31(b). 8. 1 : (8. While relatively small ( 0:1-1 A).31(a).31(c) if IB 2 and R2 are replaced with their Thevenin equivalent.27). the circuit now contains a pole at . IB 1 has no effect on the circuit because it ﬂows through a voltage source. the input bias currents may create inaccuracies in some circuits. (c) addition of R2 to reduce effect of offset. 8. thereby yielding . 8. and using (8. Nominally. As depicted in Fig.29(d). 8. 8. As shown in Fig. we have 1 Vout = .29 (a) Offset in integrator. each bias current is modeled by a current source tied between the corresponding input and ground.2 Input Bias Current Op amps implemented in bipolar technology draw a base current from each input.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. Let us study the effect of the input currents on the noninverting ampliﬁer. which can be transformed to that in Fig. Thus. R2 =R1 must be sufﬁciently small so as to minimize the ampliﬁed offset given by (8.

8.30 Input bias currents. R1 . Vout V in I B1 I B2 (a) Vout I B1 X I B2 (b) R1 R2 R1 R2 Vout R2 − I B2 R 2 (c) Figure 8. 2007 at 13:42 397 (1) Sec.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.4 Op Amp Nonidealities 397 V in1 V in2 Vout I B1 I B2 Figure 8. (c) Thevenin equivalent.31 (a) Effect of input bias currents on noninverting ampliﬁer. (b) simpliﬁed circuit.

8.31(b) forces a zero voltage across R2 and hence a zero current through it. Since Vcorr “sees” a noninverting ampliﬁer. unlike DC offsets. The error due to the input bias current appears similar to the DC offset effects illustrated in Fig. We may therefore seek a method of canceling this error. this phenomenon is not random.76) if the op amp gain is inﬁnite. This expression suggests that IB 2 ﬂows only through R1 . R Vout = .27. we have R Vout = Vcorr 1 + R1 + IB2 R1 : 2 For Vout . For example. However. the base currents drawn from the inverting and noninverting inputs remain approximately equal. an expected result because the virtual ground at X in Fig. 8. for a given bias current in the bipolar transistors used in the op amp. 8.32). we can insert a corrective voltage in series with the noninverting input so as to drive Vout to zero (Fig. corrupting the output.75) (8.R2 IB2 . 1 = R1 IB2 R2 (8.

IB2 R1 jjR2 : (8.77) = 0.78) . Vcorr = . (8.

Thus.33 Correction for variation of beta. then Vout = 0 for Vin = 0. Vcorr is chosen as (8. the correction technique shown in Fig.78) also reveals that Vcorr can be obtained by passing a base current through a resistor equal to R1 jjR2 .32 incorporates R2 = 1 k .32 Addition of voltage source to correct for input bias currents.12 Solution = 10 A and hence Vout = 0:1 mV: Thus. (8. 2007 at 13:42 398 (1) 398 Vcorr Chap. leading to the topology shown in Fig.79) Vcorr = . Equation (8. 8. R1 V in R2 I B1 Vout I B2 R1 R2 Figure 8.33. Since varies with process and temperature. determine the output error and the required value of Vcorr .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. We have IB Example 8. Vcorr cannot remain at a ﬁxed value and must “track” . R1 = 10 k .80) Exercise Determine the correction voltage if = 200. 8. If = 100 and the circuit of Fig. Here. we observe that the input bias currents have an identical effect on the inverting ampliﬁer.9:1 V: (8. A bipolar op amp employs a collector current of 1 mA in each of the input devices.31(b). if IB 1 = IB2 . .78) implies that Vcorr depends on IB 2 and hence the current gain of transistors.cls v. From the drawing in Fig. The reader is encouraged to take the ﬁnite gain of the op amp into account and prove that Vout is still near zero. 8. 8. 8 Operational Ampliﬁer As A Black Box Vout = 0 X I B2 R1 R2 Figure 8.33 applies to this circuit as well. Fortunately.

. Vout = . creating an additional error.35.34(b) suggests that a resistor equal to R1 placed in series with the noninverting input can cancel the effect.33 to the integrator? The model in Fig.4 Op Amp Nonidealities 399 In reality. 8. the two input bias currents always suffer from a slight mismatch. the circuit integrates the input bias current. the Thevenin equivalent of R1 and IB2 [Fig.34(a) with Vin = 0 and IB 1 omitted (why?). 8.81) (8. 8. Give three possible reasons for this effect.34(b)] yields C1 C1 R1 Vout − I B2 R 1 R1 Vout I B2 (a) (b) Figure 8. the DC offset voltage of the op amp itself is still integrated (Section 8. Example 8. R 1C Z = + R 1C IB2 R1 dt B = IC 2 dt: 1 1 1 1 1 Vin dt (8.4. 8. C1 V in R1 Vout R1 Figure 8. thus causing incomplete cancellation. Third.83) (Of course.13 An electrical engineering student attempts the topology of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 399 (1) Sec.82) (8. Can we apply the correction technique of Fig. asymmetries in the op amp’s internal circuitry introduce a slight (random) mismatch between IB 1 and IB 2 . (b) Thevenin equivalent. We now consider the effect of the input bias currents on the performance of integrators.33.35 in the laboratory but observes that the output still saturates. 8.1). 8. Illustrated in Fig.cls v. The result is depicted in Fig.35 Correction for input currents in an integrator. In fact. 8. Second. 8. the ﬂow of IB 2 through C1 leads to the same result.) In other words.34 (a) Effect of input bias currents on integrator. Solution First. thereby forcing Vout to eventually saturate near the positive or negative supply rails. Problem 53 studies the effect of this mismatch on the output in Fig.35 also exhibit mismatches. 8. 2006] June 30. the two resistors in Fig. the circuit forces IB 2 to ﬂow through C1 because R1 sustains a zero voltage drop.

deferring a more detailed study to Chapter 11. we provide a simple analysis of such effects. and the gain of the op amp falls to unity at !u = A0 !1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5.36. Vin2 s = 1 + s . We utilize Eq. 8. Using this model. we must modify the op amp model offered in Fig. we can reexamine the performance of the circuits studied in the previous sections. (8. the gain begins to fall as the frequency of operation exceeds f1 .11) but replace A0 with the above transfer function: Vout s = Vin 1+ A0 : R1 + R2 + 1 + s !1 R2 1 s 1+ ! A0 (8.86) . 8. s=!1 1. 2007 at 13:42 400 (1) 400 Chap. s=!1 1 and the gain is equal to A0 . Av A0 1 f1 fu f Figure 8.4. At very high frequencies. 8.3 Speed Limitations Finite Bandwidth Our study of op amps has thus far assumed no speed limitations. Consider the noninverting ampliﬁer of Fig. This frequency is called the “unity-gain bandwidth” of the op amp. the internal capacitances of the op amp degrade the performance at high frequencies. as illustrated in Fig.84) where !1 = 2f1 . In this chapter.36 Frequency response of an op amp.36. As a simple approximation. !1 (8. 2006] June 30.cls v. The mismatch current then ﬂows through R2 rather than through C1 (why?).1. For example. To represent the gain roll-off shown in Fig.85) Multiplying the numerator and the denominator by 1 + s=!1 gives Vout s = A0 s + R2 A + 1 : Vin !1 R1 + R2 0 (8.29(c). Note that at frequencies well below !1 . the internal circuitry of the op amp can be modeled by a ﬁrst-order (one-pole) system having the following transfer function: Vout A0 Vin1 . 8. 8 Operational Ampliﬁer As A Black Box Exercise Is resistor R1 necessary if the internal circuitry of the op amp uses MOS devices? The problem of input bias current mismatch requires a modiﬁcation similar to that in Fig. In reality. 8. 8.

2007 at 13:42 401 (1) Sec. 2006] June 30.4 Op Amp Nonidealities 401 The system is still of ﬁrst order and the pole of the closed-loop transfer function is given by j!p.closed j = 1 + R R2 R A0 !1 : 1+ 2 . 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

This improvement. Example 8. 8. the bandwidth of the closed-loop circuit is substantially higher than that of the op amp itself. For a closed-loop gain of 16. (8. Av A0 A0 (1+ Op Amp Frequency Response Noninverting Amplifier Frequency Response R2 A ) R 1+ R 2 0 1 f1 (1+ fu R2 A )f R 1+ R 2 0 1 f Figure 8. If the circuit is designed for a closed-loop gain of 16. we require that 1 + R1 =R2 Solution j!p.14 A noninverting ampliﬁer incorporates an op amp having an open-loop gain of 100 and bandwidth of 1 MHz.87) As depicted in Fig.37 Frequency response of (a) open-loop op amp and (b) closed-loop circuit. accrues at the cost of a proportional reduction in gain—from A0 to 1 + R2 A0 =R1 + R2 .37.closed j = 1 + R R2 R A0 !1 1+ 2 . determine the resulting bandwidth and time constant. of course.

closed j. .90) Given by j!p.1 .51 ns.88) (8. The reader can prove that the result is similar to (8. the time constant of the circuit is equal to 2. = 16 and hence 1 0 C B = B1 + R 1 A0 C !1 A @ 1 +1 = 2 635 MHz: (8. but it is outlined in Problem 57 for the interested reader. Exercise Repeat the above example if the op amp gain is 500. The above analysis can be repeated for the inverting ampliﬁer as well.87). The analysis is beyond the scope of this book.89) R2 (8. The ﬁnite bandwidth of the op amp may considerably degrade the performance of integrators.

39 compares the response of a non-slewing circuit with that of a slewing op amp. 8. In reality. The nonlinearity can also be observed by applying a large-signal sine wave to the circuit of Fig. with a large input step. large-signal steps must face slewing prior to linear settling.7 In other words. (c) input and output waveforms in slewing regime. (b) input and output waveforms in linear regime. if placed in the topologies seen above. 8. As illustrated in Fig.40). if xt ! yt. 2006] June 30.38(c). A small step of V at the input thus results in an ampliﬁed output waveform having a time constant equal to j!p.. It is important to understand that slewing is a nonlinear phenomenon. as a ramp) and eventually settles as in the linear case of Fig. 2007 at 13:42 402 (1) 402 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. op amps do not exhibit the above behavior if the signal amplitudes are large.38(c). Figure 8. the points on the ramp section do not follow linear scaling (if x ! y .cls v.38(b)]. Consider the noninverting conﬁguration shown in Fig. The slope of the ramp is called the “slew rate” (SR).” These concepts are studied in Chapter 12.1 [Fig. If the input step is raised to 2V . where the closed-loop transfer function is given by (8.86). As suggested by the waveforms in Fig. also called “frequency compensation.38(a) and gradually increasing the frequency (Fig. 8. doubling the input amplitude doubles both the output amplitude and the output slope. The ramp section of the waveform arises because. Slew Rate In addition to bandwidth and stability problems. 8. V in t V in Vout V in R2 R1 V out ∆V 2 ∆V t V out Ramp Linear Settling t t (a) (b) (c) Figure 8. the output response is determined by the closed-loop time constant.e.38 (a) Noninverting ampliﬁer. .38(a). 8. 8. 8.40(a)]. this phenomenon often requires internal or external stabilization. some op amps may oscillate. we observe that 7 Recall that in a linear system. Slewing further limits the speed of op amps. Writing Vin t = V0 sin !t and Vout t = V0 1 + R1 =R2 sin !t.38(b). the internal circuitry of the op amp reduces to a constant current source charging a capacitor. the output ﬁrst rises with a constant slope (i. each point on the output waveform also rises by a factor of two. then 2x 6! 2y ). revealing the longer settling time in the latter case. then 2xt ! 2yt. 8.closed j. We say the op amp “slews” during this time. 8 Operational Ampliﬁer As A Black Box Another critical issue in the use of op amps is stability. the op amp output “tracks” the sine wave because the maximum slope of the sine wave remains less than the op amp slew rate [Fig. While for small-signal steps. At low frequencies. Arising from the internal circuitry of the op amp. another interesting effect is observed in op amps that relates to their response to large signals.

40 (a) Simple noninverting ampliﬁer.cls v.39 Output settling speed with and without slewing.4 Op Amp Nonidealities 403 V in t Without Slewing V out With Slewing t Figure 8. 2007 at 13:42 403 (1) Sec. dVout = V 1 + R1 ! cos !t: 0 dt R2 . 8. 2006] June 30. (b) input and output waveforms without slewing.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (c) input and output waveforms with slewing. Vout V in R2 R1 V in Vout t (a) (b) V in t1 Vout t2 (c) t Figure 8.

determine the maximum frequency of operation that avoids slewing. . between t1 and t2 . What happens if the op amp slew rate is insufﬁcient? The output then fails to follow the sinusoidal shape while passing through zero. Example 8. (8. exhibiting the distorted behavior shown in Fig. If an ampliﬁer using this op amp produces a sinusoid with a peak amplitude of 0. and the op amp slew rate must exceed this value to avoid slewing. 8.40(b).. Note that the output tracks the input so long as the slope of the waveform does not exceed the op amp slew rate.15 The internal circuitry of an op amp can be simpliﬁed to a 1-mA current source charging a 5-pF capacitor during large-signal operation. e.91) The output therefore exhibits a maximum slope of V0 ! 1 + R1 =R2 (at its zero crossing points).g.5 V.

If the op amp provides a slew rate of SR. Exercise Plot the output waveform if the input frequency is 200 MHz. the largest sinusoid permitted at the output is given by VDD V in1 V in2 Vout V min 0 Equation (8. R1 =R2 .41.92) dVout j = V !: dt max p Equating this to the slew rate. 8.41 Maximum op amp output swings. 2 (8. then the maximum frequency of the above sinusoid can be obtained by writing dVout j = SR dt max and hence (8. 2007 at 13:42 404 (1) 404 Chap.96) Called the “full-power bandwidth. for frequencies above 63. For an output given by Vout Vp = 0:5 V. . As exempliﬁed by Fig. it is common to assume the worst case. namely. the zero crossings of the output experience slewing. To deﬁne the maximum sinusoidal frequency that remains free from slewing.91) indicates that the onset of slewing depends on the closed-loop gain.cls v. Vmin sin !t + Vmax + Vmin . 2006] June 30. 8 Operational Ampliﬁer As A Black Box The slew rate is given by I=C = 0:2 V/ns. 2 2 (8. when the op amp produces its maximum allowable voltage swing without saturation.94) where Vmax and Vmin denote the bounds on the output level without saturation. Vout = Vmax . 1+ VDD V max Figure 8. where (8.95) !FP = VmaxSRVmin : . we have ! = 263:7 MHz: (8.7 MHz.93) That is.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the maximum slope is equal to Solution = Vp sin !t.” !FP serves as a measure of the useful large-signal speed of the op amp.

cls v. Many op amps can provide only a small output current even though their small-signal output impedance is very low. An electrical engineering student purchases an op amp with A0 = 10. . the circuit fails to provide large voltage swings at the output even though Rout =R1 and Rout =R2 remain much less than A0 in (8.97) vX = R R2 R vout . the op amp may need to deliver a current as high as 40 mA to R1 (why?). 2007 at 13:42 405 (1) Sec. 8. 2 V. (b) effect of ﬁnite output resistance of op amp. we write a KVL from vin to vout through R2 and R1 : R1 R2 X Vout V in v in − A 0v X R1 R2 X R out v out (a) (b) Figure 8.99). vout = vout : R out To construct another equation for vX . For an output swing of.A0 vX . Explain why.A0 vX .1 and place Rout in series with the output voltage source [Fig.42(b)].4.16 Solution 8 Op amps employing MOS transistors at their input exhibit a very high input impedance at low frequencies.42(a) using R1 = 50 and R2 = 10 .99) The additional terms . Unfortunately. 8. 8. Consider the inverting ampliﬁer shown in Fig. we view R1 and R2 as a voltage divider: (8. say.42(a). assuming the op amp suffers from an output resistance. vin + vin : 1+ 2 Substituting for vX in (8.Rout =R1 in the numerator and Rout =R2 in the denominator increase the gain error of the circuit. R1 R1 vin R2 1 + Rout + A0 + R1 : R R 2 2 (8. 8.42 (a) Inverting ampliﬁer. Recognizing that the current ﬂowing through Rout is equal to . How should the circuit be analyzed? We return to the model in Fig.97) thus yields (8. 000 and Rout = 1 and constructs the ampliﬁer of Fig. vin + R1 + R2 . Rout vout = .4 Op Amp Nonidealities 405 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.4 Finite Input and Output Impedances Actual op amps do not provide an inﬁnite input impedance8 or a zero output impedance—the latter often creating limitations in the design.98) A0 . vout =Rout . 8. We analyze the effect of this nonideality on one circuit here. Rout . Example 8. We must solve the circuit in the presence of Rout .

and an input impedance of at least 10 k . 2006] June 30.cls v. arriving at R1 = 40 k for a nominal gain of 4. 8 Operational Ampliﬁer As A Black Box Exercise If the op amp can deliver a current of 5 mA. what value of R1 is acceptable for output voltages as high as 1 V? 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Determine the minimum op amp gain required here. 8. we choose the same value of R2 in Fig. Design an inverting ampliﬁer with a nominal gain of 4.17 Solution 1 R1 A0 1 + R2 and hence . we now consider several examples of the design procedure for op amp circuits. For an input impedance of 10 k . Eq. We begin with simple examples and gradually proceed to more challenging problems.7(a).5 Design Examples Following our study of op amp applications in the previous sections. Under these conditions. (8. 2007 at 13:42 406 (1) 406 Chap.21) demands that Example 8. a gain error of 0:1.

we may select R1 = 4 k and R2 = 1 k and check the gain error from (8. Assume the op amp has an input bias current of 0.18 Solution From Fig. R1 = 4: R2 (8.102) 1 R1 A0 1 + R2 .9). closed-loop bandwidth = 50 MHz.99) at the end. 0:1 (8. For a gain error of 1%.5 and Eq. Determine the required open-loop gain and bandwidth of the op amp.100) A0 5000: (8. For example. (8. Design a noninverting ampliﬁer for the following speciﬁcations: closed-loop gain = 5. gain error = 1.2 A. Example 8. we have The choice of R1 and R2 themselves depends on the “driving capability” (output resistance) of the op amp. 8.101) Exercise Repeat the above example for a nominal gain of 8 and compare the results.

103) . 1 (8.

106) (8. the open-loop bandwidth is given by (8.1 A0 2 250 MHz : 100 (8.1 V/ns gives (8.110) dVout j = 1 V : dt max R1 C1 p Equating this result to 0.107) Thus. such a small capacitor value may prove impractical.109) 1 Vout = R. from (8.) For an input given by Vin = Vp cos !t. Exercise Repeat the above example for a gain error of 2 and compare the results.112) . the op amp must provide an open-loop bandwidth of at least 500 kHz. Example 8.104) !1 !1 !p.108) = 20 k .closed 1 + R R2 R A0 1+ 2 !p. 8.1 V/ns. (8. we have R1 C1 2 10 MHz = 1 and.105) (8.87). 2007 at 13:42 407 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. C1 = 0:796 pF: (In discrete design. 1 1 ! with a maximum slope of (8. If the op amp provides a slew rate of 0.cls v.C Vp sin !t. what is the largest peak-to-peak sinusoidal swing at the input at 1 MHz that produces an output free from slewing? Solution From (8.111) Vp = 1:59 V: (8.19 Design an integrator for a unity-gain frequency of 10 MHz and an input impedance of 20 k .29). 2006] June 30.closed R 1 + 1 + R1 . with R1 1 (8.5 Design Examples 407 and hence A0 500: Also.

These effects impact the performance of various circuits.5 V/ns? 8. Placing a bipolar device around an op amp provides a logarithmic function. for large signals. (a) Plot the input/output characteristic of this op amp. Also. most notably.” If the feedback resistor in an inverting conﬁguration is replaced with a capacitor. distorting the output waveform. the inverting input also remains close to the ground potential ans is thus called a “virtual ground. Exercise How do the above results change if the op amp provides a slew rate of 0.e.e. an op amp producing a moderate output swing requires only a very small input difference.6 Chapter Summary An op amp is a circuit that provides a high voltage gain and an output proportional to the difference between two inputs. The circuit also suffers from a gain error that is inversely proportional to the gain of the op amp. the circuit operates as an integrator. the circuit acts as a differentiator. (b) What is the largest input swing that the op amp can sense without producing “distortion” (i. the op amp suffers from a ﬁnite slew rate. An inverting conﬁguration using multiple input resistors tied to the virtual ground node can serve as a voltage adder. including dc offsets and input bias currents. nonlinearity)? .cls v. Placing a diode around an op amp leads to a precision rectiﬁer. 2007 at 13:42 408 (1) 408 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Its gain error is the same as that of the noninverting conﬁguration. The noninverting ampliﬁer topology exhibits a nominal gain equal to one plus the ratio of two resistors. i. Problems 1. 8 Operational Ampliﬁer As A Black Box In other words. Actual op amps exhibit “nonlinear” characteristics. The inverting ampliﬁer conﬁguration provides a nominal gain equal to the ratio of two resistors. and close to zero for jVout j 2 V. a circuit that can rectify very small input swings. differentiators are less common than integrators. the input peak-to-peak swing at 1 MHz must remain below 3.1 V Vout +1 V. Integrator ﬁnd wide application in analog ﬁlters and analog-todigital converters. 2006] June 30.18 V for the output to be free from slewing. integrators.. Due to its high voltage gain. Op amps suffer from various imperfections. For example. If the input resistor in an inverting conﬁguration is replaced with a capacitor. the voltage gain may be equal to 1000 for . 500 for 1 V jVout j 2 V. Due to their higher noise. With the noninverting input of the op amp tied to ground.. The speed of op amp circuits is limited by the bandwidth of the op amps.

43. 8. 8. resistor R2 deviates from its nominal value V in1 A0 V in V in2 R1 R2 Vout Figure 8. 8. Modeling the op amp as shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Compute the minimum required op amp gain.11). 4. Vin2 : (8.6 Chapter Summary 409 2. A noninverting ampliﬁer employs an op amp with a ﬁnite output impedance.113) 3. determine the gain error if A0 drops to 0:6A0 . A noninverting ampliﬁer must provide a nominal gain of 4 with a gain error of 0:1.44. 5. an adventurous student decides that it is possible to achieve a zero gain error with a ﬁnite A0 if R2 =R1 + R2 is slightly adjusted from its nominal value.45 . Vin2 0. 6. Looking at Equation (8. Vout V in1 V in2 R in A 0 (V in1 − V in2 ) Figure 8. 2006] June 30.cls v. An op amp exhibits the following nonlinear characteristic: Vout = tanh Vin1 . (a) Suppose a nominal closed-loop gain of 1 is required. A noninverting ampliﬁer incorporates an op amp having an input impedance of Rin . Determine the gain error.45. 2007 at 13:42 409 (1) Sec. In the noninverting ampliﬁer shown in Fig. determine the closed-loop gain and input impedance.44 impedance. Rout . Representing the op amp as depicted in Fig. Sketch this characteristic and determine the small-signal gain of the op amp in the vicinity of Vin1 . What happens if A0 ! 1? 8.43 What happens if A0 ! 1? 7. compute the closed-loop gain and output R out Vout V in1 V in2 A 0 (V in1 − V in2 ) Figure 8. How should R2 =R1 + R2 be chosen? (b) With the value obtained in (a). 8. A noninverting ampliﬁer employs an op amp having a nominal gain of 2000 to achieve a nominal closed-loop gain of 8.

46.48 if A0 Verify that the result reduces to expected values if R1 ! 0 or R3 ! 0. the closed-loop circuit is much more linear. Calculate the closed-loop gain of the noninverting ampliﬁer shown in Fig. 13.48 12. Figure 8. a proportionality factor. . 11.43. Modeling the op amp as shown in Fig.e.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. deﬁned as the change in Vout Vin =1 V A0 R1 Vout RS Figure 8. Also. 8. determine the closed-loop gain and input impedance.8A 0 −4 mV −2 mV A0 +2 mV +4 mV V in1 − V in2 Figure 8. Suppose RS plays the role of R2 in the noninverting ampliﬁer (Fig.. Here R0 is a constant value. Determine the minimum required op amp gain. An inverting ampliﬁer must provide a nominal gain of 8 with a gain error of 0:2. The input/output characteristic of an op amp can be approximated by the piecewise-linear behavior illustrated in Fig. 8. Calculate the gain error of the circuit if R=R2 1. 8.47). Vin = 1 V. 9. 2007 at 13:42 410 (1) 410 Chap.) 10. Vin2 j increases. i. The op amp used in an inverting ampliﬁer exhibits a ﬁnite input impedance. 8. Rin . (Note that the closed-loop gain experiences much less variation. A truck weighing station incorporates a sensor whose resistance varies linearly with the weight: RS = R0 + W . Plot the closed-loop input/output characteristic of the circuit. 8 Operational Ampliﬁer As A Black Box by R. Suppose this op amp is used in a noninverting ampliﬁer with a nominal gain of 5. A0 V in R1 R2 R3 R4 Vout = 1. where the gain drops from A0 to 0:8A0 and eventually to Vout 0. and W the weight of each truck. 2006] June 30. Determine the gain of the system.cls v.47 divided by the change in W .46 zero as jVin1 .

compute the closed-loop gain of the inverting ampliﬁer shown in Fig. If the op amp exhibits an open-loop gain of 1000 and an output impedance of 1 k . 2007 at 13:42 411 (1) Sec.51 output signal amplitude if A0 = 1. If A0 = 1 and R1 C1 = 10 ns. compute the closed-loop gain and output impedance. 20. determine the gain error. The integrator of Fig.51 must provide a pole at no higher than 1 Hz. 8. 8. respectively. An inverting ampliﬁer is designed for a nominal gain of 8 and a gain error of 0:1 using an op amp that exhibits an output impedance of 2 k . The integrator of Fig. 8. 2006] June 30.50 if A0 R1 R2 X A0 V in Vout R4 R3 = 1. Determine the closed-loop gain of the circuit depicted in Fig. 15.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. determine the required gain of the op amp.51 is used to amplify a sinusoidal input by a factor of 10. Determine the Figure 8. 17. 8. Figure 8. 16.49 18. 8.6 Chapter Summary 411 14. 8.51 senses an input signal given by Vin C1 R1 V in A0 Vout = V0 sin !t.cls v. If the input impedance of the circuit must be equal to approximately 1 k . 21. An inverting ampliﬁer employs an op amp having an output impedance of Rout . calculate the required open-loop gain of the op amp.44. .50 19. compute the frequency of the sinusoid. R3 R1 R4 R2 Vout V in Figure 8. An inverting ampliﬁer must provide an input impedance of approximately 10 k and a nominal gain of 4. Assuming A0 = 1. The integrator of Fig.49. Verify that the result reduces to expected values if R1 ! 0 or R3 ! 0. 8. Modeling the op amp as depicted in Fig. If the values of R1 and C1 are limited to 10 k and 1 nF.

Calculate the transfer function of the circuit shown in Fig. Plot Vout as a function of time if V1 = RF V1 V2 R2 X R1 A0 Vout Figure 8. Consider the integrator shown in Fig. (8. 8.43.43.44. 8. 24.42).37). 8. The op amp used in the integrator of Fig. 26.57). 23.54 V0 sin !t and V2 = V0 sin3!t.54.51 exhibits a ﬁnite output impedance and is modeled as depicted in Fig. (8. The differentiator of Fig. 8 Operational Ampliﬁer As A Black Box 22. 28. Determine the transfer function Vout =Vin and compare the location of the pole with that given by Eq.52 is used to amplify a sinusoidal input at a frequency of 1 MHz R1 C1 V in A0 Vout Figure 8.52 exhibits a ﬁnite input impedance and is modeled as shown in Fig. Suppose the op amp in Fig. by a factor of 5.52 25.44.cls v. . 8. Compute the transfer function Vout =Vin and compare the location of the pole with that given by Eq. If A0 = 1. Determine the transfer function Vout =Vin and compare the result with Eq. 8. Consider the voltage adder shown in Fig. 8.52 for a pole frequency of 100 MHz. compute the required gain of the op amp. Assume R1 = R2 and A0 = 1. If the values of R1 and C1 cannot be lower than 1 k and 1 nF. respectively.42). 2006] June 30. The op amp used in the differentiator of Fig. 8.53 if A0 = 1. Compute the transfer function and compare the result with Eq. 27. 8. 8. 8. What choice of component values reduces jVout =Vin j to unity at all frequencies? R2 C1 C2 V in R1 A0 Vout Figure 8. Repeat Problem 28 if A0 1. (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (8. We wish to design the differentiator of Fig. determine the value of R1 C1 . 2007 at 13:42 412 (1) 412 Chap. Can the resistors and capacitors be chosen so as to reduce jVout =Vin j to approximately unity? 30.52 suffers from a ﬁnite output impedance and is modeled as depicted in Fig.51 and suppose the op amp is modeled as shown in Fig.53 29. 8. 8.

where a parasitic resistor RP has appeared in parallel with D1 .54 employs an op amp having a ﬁnite output impedance.56 op amp exhibits a ﬁnite input impedance. . 8. Plot the current ﬂowing through D1 in the precision rectiﬁer of Fig. 8. Due to a manufacturing error. 39.23(a) as a function of time for a sinusoidal input. Sketch Vout and VX as a function of Vin if the op amp is ideal. The op amp in Fig. The voltage adder of Fig. 8. Suppose Vin in Fig. Figure 8. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 413 (1) Sec. 8.1 V to +1 V. 37. 34.57 shows a precision rectiﬁer producing negative cycles.6 Chapter Summary 413 31. We wish to improve the speed of the rectiﬁer shown in Fig.22(b) by connecting a diode from node Y to ground. 8.) 33. 8. Vout . 32. Using the op amp model depicted in Fig. 8.22(b) as a function of time for a sinusoidal input. With the aid of the op amp model shown in Fig. (Note that RP can RF V1 V2 R2 X R1 A0 RP Vout Figure 8.cls v. 8. 40.57 current ﬂowing through D1 as a function of time for a sinusoidal input. compute Vout in terms of V1 and V2 . Plot the current ﬂowing through D1 in the precision rectiﬁer of Fig. Calculate Vout in terms of V1 and V2 for A0 = 1 and A0 1. Plot VY . Calculate Vout in terms of V1 and V2 .58. 38. 35. where RP is a parasitic resistance and the R F V1 V2 R2 X R1 A0 RP Vout Figure 8.55 also represent the input impedance of the op amp. determine Vout in terms of V1 and V2 .56.44. Consider the precision rectiﬁer depicted in Fig.24 varies from . Use a constant-voltage model for the diode. 36. 8. Explain how this can be accomplished. 2006] June 30.43. Plot VX and VY as a function of time in response to a sinusoidal input. Rout .55. Consider the voltage adder illustrated in Fig. 8. a parasitic resistance RP has appeared in the adder of Fig.54 suffers from a ﬁnite gain. and the V in X V out R1 D1 Y Figure 8. 8.

24 by differentiating both sides of (8.61. In the noninverting ampliﬁer of Fig.1:5 V. the op amp offset is represented by a voltage source in series with the inverting input.24 must “map” an input range of 1 V to 10 V to an output range of . 8.58 41.1 V to . Suppose the gain of the op amp in Fig. 8. (b) Calculate the small-signal voltage gain at the two ends of the range. 48. Describe the operation of this circuit. 8 Operational Ampliﬁer As A Black Box Y D1 R1 RP Figure 8. 42. The logarithmic ampliﬁer of Fig.59 43. 8. Deter- R1 X V in V TH M1 Vout Figure 8. Determine the maximum offset error in Vout if each ampliﬁer is designed for a gain of 10.60 can be considered a “true” square-root ampliﬁer. 8. 2007 at 13:42 414 (1) 414 V in X V out Chap. The circuit illustrated in Fig. 47. 46. Determine the input/output characteristic of the circuit. A student attempts to construct a noninverting logarithmic ampliﬁer as illustrated in Fig. Plot the magnitude of the gain as a function of Vin and explain why the circuit is said to provide a “compressive” characteristic.60 mine Vout in terms of Vin and compute the small-signal gain by differentiating the result with respect to Vin .62. 8. Calculate Vout .cls v.66) with respect to Vin . . 8. Calculate Vout in terms of Vin for the circuit shown in Fig.24 is ﬁnite. (a) Determine the required values of IS and R1 . Q1 Vout V in R1 X Figure 8. 8.59. 45. 44. Determine the small-signal voltage gain of the logarithmic ampliﬁer depicted in Fig. Suppose each op amp in Fig. 8.28 suffers from an input offset of 3 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.

Figure 8. 51.84). 8. Suppose the input bias currents in Fig. 8. 8.64 shows an integrator employing an op amp whose frequency response is given by As = A0 s : 1+ ! 0 (8. i.29(c) must operate with frequencies as low as 1 kHz while providing an output offset of less than 20 mV with an op amp offset of 3 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8. f1 = 50 Hz. Explain the effect of op amp offset on the output of a logarithmic ampliﬁer. 55. For the inverting ampliﬁer illustrated in Fig. Determine the transfer function of the closed-loop circuit and compute the bandwidth. 8. calculate Vout if the op amp exhibits an R1 R2 A0 V in Vout Figure 8. Assume A0 = 1. The integrator of Fig.61 A0 V in R1 V OS R2 Vout Figure 8. f1 = 1 MHz.33. input offset of Vos . 2007 at 13:42 415 (1) Sec. An inverting ampliﬁer incorporates an op amp whose frequency response is given by Eq. 53.31 incur a small offset.114) . What is the maximum allowable value of R1 jjR2 if the output error due to this mismatch must remain below a certain value.63 50.6 Chapter Summary 415 R1 X V in M1 Vout Figure 8. V ? A noninverting ampliﬁer must provide a bandwidth of 100 MHz with a nominal gain of 4. 52. Determine which one of the following op amp speciﬁcations are adequate: (a) A0 = 1000. IB 1 = IB 2 + I . (8. 57. 2006] June 30.cls v. (a) A0 = 500. Repeat Problem 53 for the circuit shown in Fig.62 49. Calculate Vout . 56.e. Explain why dc offsets are not considered a serious issue in differentiators.63.. Determine the required values of R1 and R2 if C1 100 pF. 54.

what is the highest input frequency for which no slewing occurs? 59. and a total resistance of 20 k .cls v. A voltage adder must realize the following function: Vout = 1 V1 + 2 V2 . SPICE Problems . Simplify the result if 1=R1 C1 . where 1 = . With a ﬁnite op amp gain. 8 Operational Ampliﬁer As A Black Box Determine the transfer function of the overall integrator. V0 = 1 V0 lR am p ∆V ∆V = 0. Assume the largest available capacitor is 50 pF.7(a) for a nominal gain of 8 and a gain error of 0:1.2 at Vin = 2 V? Assume the gain of the op amp is sufﬁciently high.1% V0 Id ea Vout t Figure 8. The unity-gain buffer of Fig. and the capacitor must remain below 20 pF.65). 62.3 must be designed to drive a 100 load with a gain error of 0:5. 1 V . Design a noninverting ampliﬁer with a nominal gain of 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Can a logarithmic ampliﬁer be designed to have a small-signal gain (dVout =dVin ) of 2 at Vin = 1 V and 0. Assume = 10 V=s. a gain error of 0:2.64 58. C1 R1 Vout V in A (s ( !0 Figure 8. 66. Assume Rout = 100 . Design an integrator whose step response approximates V t = t with an error less than 0:1 for the range 0 V t V0 (Fig. 8.5 V. A noninverting ampliﬁer with a nominal gain of 4 senses a sinusoid having a peak amplitude of 0.0:5 V .1:5. 8. Determine the required op amp gain if the op amp has an output resistance of 1 k . 8. Design an integrator that attenuates input frequencies above 100 kHz and exhibits a pole at 100 Hz.65 V. 63. 64. 65.0:5 and 2 = . 2006] June 30. 61. Design Problems 60. the step response of an integrator is a slow exponential rather than an ideal ramp. Design the circuit if the worst-case error in 1 or 2 must remain below 0:5 and the input impedance seen by V1 or V2 must exceed 10 k . 2007 at 13:42 416 (1) 416 Chap. If the op amp provides a slew rate of 1 V/ns. Design a logarithmic ampliﬁer that “compresses” an input range of 0:1 V 2 V to an output range of . Design the inverting ampliﬁer of Fig. Assume the op amp has a ﬁnite gain but is otherwise ideal.

8. 2006] June 30.5 V 500 Ω Vout Q1 V in X 100 Ω Figure 8.68 71.17 A for D1 .cls v. What is the error in the output amplitude with respect to the input amplitude? 10 pF 1 kΩ 1 kΩ 10 pF V in Vout Figure 8.16 A. Assume IS.67 70. plot the frequency response of the circuit depicted in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Using ac analysis in SPICE. (Hint: VX Vin . 69.) . 2007 at 13:42 417 (1) Sec.68. and = 100. The arrangement shown in Fig. V in V out 1 kΩ Y D1 Figure 8. 8.67. Assuming an op amp gain of 1000 and IS = 10.6 Chapter Summary 417 67. In the circuit of Fig.Q1 = 5 10. Apply a 10-MHz sinusoid at the input and plot the output as a function of time. V CC = 2. 8. each op amp provides a gain of 500. 8. plot the input/output characteristic of the precision rectiﬁer shown in Fig.66 68.69 incorporates an op amp to “linearize” a common-emitter stage. 8. 10 k Ω 10 pF 1 kΩ 1 kΩ 10 pF V in Vout Figure 8. Repeat Problem 67 but assuming that the op amp suffers from an output resistance of 1 k .69 (a) Explain why the small-signal gain of the circuit approaches RC =RE if the gain of the op amp is very high.66.

2006] June 30. 2007 at 13:42 418 (1) 418 Chap.g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8 Operational Ampliﬁer As A Black Box (b) Plot the input/output characteristic of the circuit for 0:1 V Vin 0:2 V and an op amp gain of 100. .. using a voltage-dependent voltage source) from the above characteristic and determine the maximum error. (c) Subtract Vout = 5Vin (e.cls v.

Our study includes both bipolar and MOS implementations of each building block. We also know that a single transistor can operate as a current source but its output impedance is limited due to the Early effect (in bipolar devices) or channel-length modulation (in MOSFETs).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 Output impedance of degenerated bipolar and MOS devices. 9. How can we increase the output impedance of a transistor that acts as a current source? An important observation made in Chapters 5 and 7 forms the foundation for our study here: emitter or source degeneration “boosts” the impedance seen looking into the collector or drain.1 Cascode Stage 9.1. we deal with two other important building blocks in this chapter.” 419 . and the “current mirror” is an interesting and versatile technique employed extensively in integrated circuits.cls v. we have R out1 Vb Q1 RE Vb R out2 M1 RS Figure 9. the term “cascode” is believed to be an abbreviation of “cascaded triodes. 1 Coined in the vacuum-tube era. Shown below is the outline of the chapter. The “cascode”1 stage is a modiﬁed version of common-emitter or common-source topologies and proves useful in high-performance circuit design.1. For the circuits shown in Fig. Cascode Stages Cacode as Current Source Cacode as Amplifier Current Mirrors Bipolar Mirrors MOS Mirrors 9. 2006] June 30.1 Cascode as a Current Source Recall from Chapters 5 and 7 that the use of current-source loads can markedly increase the voltage gain of ampliﬁers. 2007 at 13:42 419 (1) 9 Cascode Stages and Current Mirrors Following our study of basic bipolar and MOS ampliﬁers in previous chapters. respectively.

2(a). In this case. Note thatIC 1 IC 2 if 1 1. 2007 at 13:42 420 (1) 420 Chap. Depicted in Fig. For example.1 2 Or simply the “cascode.1) (9. Unfortunately. determine the output resistance. 2006] June 30.1. (9.4 V to remain soft saturation. we can replace the degeneration resistor with a transistor.7) If Q1 and Q2 in Fig. then the degenerated current source “‘consumes” a headroom of 800 mV. we call Q1 the cascode transistor and Q2 the degeneration transistor.cls v.2(a) are biased at a collector current of 1 mA.3) (9. Bipolar Cascode In order to relax the trade-off between the output impedance and the voltage headroom.2(b)]. we have Rout = 1 + gm1 rO2 jjr1 rO1 + rO2 jjr1 : Since typically gm1 rO2 jjr1 (9.2(a) for the bipolar version. Let us compute the output impedance of the bipolar cascode of Fig. (9. emitter of Q1 while consuming a headroom independent of the current. 9. the idea is to introduce a high small-signal resistance (= rO2 ) in the R out R out V b1 V b2 Q1 Q2 (a) Vb Q1 r O2 (b) Figure 9.” . this transistor simply operates as a small-signal resistance equal to rO2 [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4) observing that RE or RS can be increased to raise the output resistance. This conﬁguration is called the “cascode” stage.6) (9. that rO cannot generally be assumed much greater than r . Assume = 100 and VA = 5 V for both transistors. 9.5) 1. consuming voltage headroom and ultimately limiting the voltage swings provided by the circuit using such a current source. In analogy with the resistively-degenerated counterpart in Fig. Rout 1 + gm1 rO1 rO2 jjr1 gm1rO1 rO2 jjr1 : Note. Example 9.2) (9.2 To emphasize that Q1 and Q2 play distinctly different roles here. if RE sustains 300 mV and Q1 requires a minimum collectoremitter voltage of 500 mV. 9. the voltage drop across the degeneration resistor also increases proportionally. however. Q2 requires a headroom of approximately 0. Since the baseemitter voltage of Q2 is constant. 9 Cascode Stages and Current Mirrors Rout1 = 1 + gm RE jjr rO + RE jjr = 1 + gmrO RE jjr + rO Rout2 = 1 + gmRS rO + RS = 1 + gmrO RS + rO . however. 9. 9. (b) equivalent circuit.2 (a) Cascode bipolar current source.

R out Q1 r π1 Ideal This is the maximum output impedance provided by a bipolar cascode. At room temperature.e.12). 9.3 Compare the resulting output impedance of the cascode with the upper bound given by Eq.2 3 In integrated circuits.1. the Early voltage of Q2 is equal to 50 V. i. and r = VT =IC : Solution VA2 VT IC 1 VA1 IC 2 IC 1 Rout V I T C 1 VA2 + VT IC 2 IC 1 I 1 VA V VA VT . the output resistance of Q1 with no degeneration would be equal to rO1 = 5 k . Suppose in Example 9.11) (9. Exercise What Early voltage is required for an output resistance of 500 k ? It is interesting to note that if rO2 becomes much greater than r1 . This example applies to discrete implementations. (9. 2007 at 13:42 421 (1) Sec. all bipolar transistors fabricated on the same wafer exhibit the same Early voltage.max gm1 rO1 r1 1 rO1 : (9. “cascoding” has boosted Rout by a factor of 66 here.cls v. 2006] June 30. (9.12) rO2 = 1 (Fig.. 9.8) (9.1 Cascode Stage 421 Since Q1 and Q2 are identical and biased at the same current level. .7) can be simpliﬁed by noting that gm = IC =VT . VT 26 mV and hence Rout 328:9 k : (9.3 Cascode topology using an ideal current source. r1 still appears from the emitter of Q1 to ac ground.3) [or RE = 1 in (9.9) = IC 1 = IC 2 and VA = VA1 = VA2 . then Rout1 approaches Rout.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. V + V C1 T A T where IC (9. Note that rO2 and r1 are comparable in this example. Eq. thereby limiting Rout to 1 rO1 .10) By comparison. even with Figure 9. rO = VA =IC . Example 9.1)]. After all.

1 . RoutA = 1 + gm2 RE jjr2 rO2 + RE jjr2 : It follows from (9.cls v.13) (9. 1 O2 (9. and no positive value of RoutA exists! In other words.17) RoutA = r2rO2 rr1 : .4 . 2006] June 30. it is impossible to double the output impedance of the cascode by emitter degeneration. and rO2 = 50 k . about 5 higher. we replace Q2 and RE with their equivalent resistance from (9. 9.15) Rout gm1 rO1 RoutA jjr1 : We wish this value to be twice that given by (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. r1 is typically less than rO2 .3 We wish to increase the output resistance of the bipolar cascode of Fig. Determine the required value of the degeneration resistor if Q1 and Q2 are identical.7): (9.4.7) that (9.18) In practice. r1 = 2:6 k . rO1 = 5 k . As illustrated in Fig. we have (9.1): R out R out V b1 Q1 R outA Vb Q1 R outA Solution V b2 Q2 RE Figure 9. 9 Cascode Stages and Current Mirrors Since gm1 Solution = 26 . .14) Rout gm1 rO1 rO1 jjr1 475 k : The upper bound is equal to 500 k . Exercise Repeat the above example if the Early voltage of Q1 is 10 V.2(a) by a factor of two through the use of resistive degeneration in the emitter of Q2 . 2007 at 13:42 422 (1) 422 Chap. 9. Example 9.16) RoutA jjr1 = 2rO2 jjr1 : That is. (9.

Example 9. 2006] June 30.5? What does the above result mean? Comparing the output resistances obtained in Examples 9.1 Cascode Stage 423 Exercise Is there a solution if the output impedance must increase by a factor of 1. While we have arrived at the cascode as an extreme case of emitter degeneration.2. since Q2 provides only an output impedance of rO2 .cls v. Fig.7) and (9.7 are not cascodes. That is. 9. the ratio of (9. 9.12) is equal to rO2 =rO2 + r1 . More speciﬁcally.5 shows a pnp cascode. R out R out = r O2 V b2 Q2 V b1 V b2 Q1 Q2 g m1 r O1 ( r O2 r π 1 ) Figure 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we recognize that even identical transistors yield an Rout (= 328:9 k ) that is not far from the upper bound (= 500 k ).5 PNP cascode current source. it is also possible to view the evolution as illustrated in Fig. VCC V b2 V b1 Q2 Q1 R out Figure 9.5). 9. R out V b1 X V b2 Q2 (a) R out V b1 V b1 Q1 1 r g m2 O2 VCC Q2 X V b2 Q1 R out (b) VCC 1 r g m2 O2 Q1 V b2 Q1 R out Figure 9. a value greater than 0.6 Evolution of cascode topology viewed as stacking Q1 atop Q2 .1 and 9. 9. The output impedance is given by (9. 2007 at 13:42 423 (1) Sec. we “stack” Q1 on top of it to raise Rout . where Q1 serves as the cascode device and Q2 as the degeneration device.6.7 .4 Explain why the topologies depicted in Fig.5 if rO2 r1 . For completeness.

Rout . 9. Given by (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1). since 1=gm2 rO2 .7 connect the emitter of Q1 to the emitter of Q2 .cls v. is therefore considerably lower: Solution Rout = 1 + gm1 g 1 jjrO2 jjr1 rO1 + g 1 jjrO2 jjr1 : m2 m2 In fact. the output impedance. 9 Cascode Stages and Current Mirrors Unlike the cascode of Fig. thereby presenting an impedance of 1=gm2 jjrO2 (rather than rO2 ) at node X . r1 and since gm1 gm2 (why?). 2007 at 13:42 424 (1) 424 Chap. 9. Transistor Q2 now operates as a diode-connected device (rather than a current source).2(a). the circuits of Fig. . 2006] June 30.

g Rout 1 + gm1 rO1 + g 1 m2 m2 2rO1 : The same observations apply to the topology of Fig. 9.7(b). .

Equation (9. thus presenting a small-signal resistance of rO2 from X to ground. For simplicity. source.20) (9. 9. the idea is to replace the degeneration resistor with a MOS current R out V b1 X V b2 M2 M1 Vb R out M1 r O2 Figure 9. MOS Cascodes The similarity of Eqs.21) Exercise Estimate the output impedance for a collector bias current of 1 mA and VA = 8 V.22) (9. r O 2 .19) (9.8 are identical (they need not be). 9. implying that the output impedance is proportional to the intrinsic gain of the cascode device.8.23) is an extremely important result.3) can now be written as Rout = 1 + gm1 rO2 rO1 + rO2 gm1rO1 rO2 .3) for degenerated stages suggests that cascoding can also be realized with MOSFETs so as to increase the output impedance of a current source.5 mA. Equation (9.1 . (9. assume M1 and M2 in Fig.8 MOS cascode current source and its equivalent. (9.23) where it is assumed gm1 rO1 rO2 rO 1 .1) and (9. Assume n Cox = 100 A=V2 and = 0:1 V. (9. . Illustrated in Fig. Example 9.5 Design an NMOS cascode for an output impedance of 500 k and a current of 0.

Determine the output resistance.MOS = gm1 rO1 rO2 increases with no bound. and r are inﬁnite (at low frequencies). raising rO2 eventually leads to Rout. The output resistance is given by (9. 2006] June 30.9).6 for the MOS counterpart (Fig. Rout. (9.cls v. we require that gm1 = 800 . (9. Rp . other second-order effects limit the output impedance of MOS cascodes.10 illustrates a PMOS cascode. we R out R out = r O2 V b2 M2 V b1 X V b2 M2 M1 g m1 r O1 r O2 Figure 9.23) as Example 9.1 and hence (9. 9. This observation reveals an interesting point of contrast between bipolar and MOS cascodes: in the former. During manufacturing.24) = rO2 = ID . Figure 9. has appeared in a cascode as shown in Fig.27) .9 MOS cascode viewed as stack of M1 atop of M2 .6 Solution Rout = gm1 rO1 jjRp rO2 : 4 In reality.4 This is because in MOS devices. whereas in the latter.22). It is therefore possible to rewrite (9. a large parasitic resistor. 9. 9. 9.26) Exercise What is the output resistance if W=L = 32? Invoking the alternative view depicted in Fig. 2007 at 13:42 425 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.25) 1 2nCox W ID = 800 : L It follows that We should also note that gm1 rO1 W = 15:6: L = 25 1. We observe that Rp is in parallel with rO1 . recognize that stacking a MOSFET on top of a current source “boosts” the impedance by a factor of gm2 rO2 (the intrinsic gain of the cascode transistor).1 Cascode Stage 425 We must determine W=L for both transistors such that Solution gm1 rO1 rO2 = 500 k : Since rO1 (9.11.bip = rO1 .1 = 20 k r .

As illustrated in Fig. we deﬁned the transconductance of a transistor as the change in the collector or drain current divided by the change in the base-emitter or gate-source voltage. 2006] June 30.28) Exercise What value of Rp degrades the output impedance by a factor of two? 9.10 PMOS cascode current source.2 Cascode as an Ampliﬁer In addition to providing a high output impedance as a current source.1. R out M1 V b1 V b2 M2 RP Figure 9. the output voltage is set to zero Circuit i out ac GND v in Figure 9.12 Computation of transconductance for a circuit. For our study below. and the “short-circuit transconductance” of the circuit is .cls v. the cascode topology can also serve as a high-gain ampliﬁer. (9. 9. 2007 at 13:42 426 (1) 426 Chap. In fact. we return to the original equation. be shorting the output node to ground.12. 9 VDD V b2 X V b1 M1 R out M2 Cascode Stages and Current Mirrors Figure 9.11 If gm1 rO1 jjRp is not much greater than unity.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. substituting rO1 jjRp for rO1 : Rout = 1 + gm1 rO2 rO1 jjRp + rO2 : (9. we need to understand the concept of the transconductance for circuits.22). In Chapters 4 and 6. This concept can be generalized to circuits as well. the output impedance and the gain of ampliﬁers are closely related.

write Solution Gm = ivout in iD1 =v GS 1 = gm1 : Thus.13 As depicted in Fig.29) The transconductance signiﬁes the “strength” of a circuit in converting the input voltage to a current.33) where Rout denotes the output resistance of the circuit (with the input voltage set to zero).12. in this case. Example 9. 2007 at 13:42 427 (1) Sec. Proof We know that a linear circuit can be replaced with its Norton equivalent [Fig. the transconductance of the circuit is equal to that of the transistor. 9. VDD RD v out v in M1 (a) VDD RD i out M1 (b) ac GND v in Figure 9. That is.14(a)].Gm Rout . 2006] June 30. 9. (9.13(b).5 Note the direction of iout in Fig.7 Calculate the transconductance of the CS stage shown in Fig. Norton’s theorem states that iout is obtained by shorting the output to ground vout = 0 and 5 While omitted for simplicity in Chapters 4 and 6. noting that RD carries no current (why?). = 0 is also required for the transconductance . the collector or drain must by shorted to ac ground.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 Cascode Stage 427 deﬁned as Gm = ivout jvout=0 : in (9.cls v. (9. we short the output node to ac ground and. 9.31) (9.30) (9.32) Exercise How does Gm change if the width and bias current of the transistor are doubles? Lemma The voltage gain of a linear circuit can be expressed as Av = . 9.13(a). the condition vout of transistors. 9.

14(a)..14(b)].15(b)].cls v.e. VCC I1 v out v in Q1 v in Q1 i out ac GND (9.Gm vin Rout and hence (9. gm1 vin . 2006] June 30. 9. we place an ac short from the output to ground and ﬁnd the current through it [Fig.37) (9. Gm = ivout in = gm1 : (9.38) . 9. Gm = iout =vin . We also relate iout to vin by the transconductance of the circuit.8 Determine the voltage gain of the common-emitter stage shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34) (9.15(a). iout is simply equal to the collector current of Q1 . 9. 9.36) iX Q1 vX (a) (b) (c) Figure 9.ioutRout = .35) vout = . 2007 at 13:42 428 (1) 428 Chap. Thus.15 Solution To calculate the short-circuit transconductance of the circuit. computing the short-circuit current [Fig. i.G R : m out vin Example 9.14 (a) Norton equivalent of a circuit. (b) computation of short-circuit output current . 9 Cascode Stages and Current Mirrors Vout v in i out R out Vout (a) i out v in (b) Figure 9. vout = . in Fig. In this case.

1 Cascode Stage 429 Note that rO does not carry a current in this test (why?). we obtain the output resistance as depicted in Fig. the small-signal current. the collector load impedance must be maximized. as in cascodes. (b) use of cascode to increase the output impedance. 9. produced by Q1 ﬂows through rO1 .40) Av = .Gm Rout = .gm1 vin rO1 .42) Exercise Suppose the transistor is degenerated by an emitter resistor equal to RE .1 that the circuit achieves a high output impedance and. suppose we stack a transistor on top of Q1 as shown in Fig. We know from Section 9. 9.gm1rO1 : (9.15(c): Rout = vX iX = rO1 : It follows that (9.39) (9. In the limit. . an ideal current source serving as the load [Fig. 2006] June 30. It also indicates that the voltage gain of a circuit can be increased by raising the output impedance. The transconductance falls but the ouput resistance rises. Bipolar Cascode Ampliﬁer Recall from Chapter 4 that to maximize the voltage gain of a common-emitter stage. Now.41) (9. from the above lemma.43) (9. 9. VA : V T (9. Does the voltage gain increase or decrease? The above lemma serves as an alternative method of gain calculation.gm1rO1 = .cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. a voltage gain higher than that of a CE stage. 9.16 (a) Flow of output current generated by a CE stage through rO1 .1. 2007 at 13:42 429 (1) Sec. Av = . thus generating an output voltage equal to .16(b).44) In this case. Next. gm1 vin .16(a)] yields a voltage gain of VCC I1 VCC I1 v in Q1 g v m1 in r O1 V b1 v out v in Q1 Q2 v out (a) (b) Figure 9.

gm1 rO1 gm1 rO1 jjr2 + 1 . since Q1 and Q2 carry approximately equal bias currents. 9. this transistor can be viewed as a diode-connected device having an impedance of 1=gm2 jjrO2 . As shown in Fig.gm1 gm2 rO1 jjr2 rO2 + rO1 jjr2 : Also.46) The reader may view (9. the short-circuit transconductance is equal to iout =vin . the collector current of Q1 must split between rO1 and the impedance seen looking into the emitter of Q2 . Since the base and collector voltages of Q2 are equal. As a commoni out Q2 ac GND i out Q2 r O2 X Q1 v in ac GND Q1 v in (a) g v m1 in g v m1 in r O1 (b) Figure 9. emitter stage.5).17(a).46) dubiously. we write from (9. After all. Q1 still produces a collector current of gm1 vin . To obtain the overall voltage gain.52) (9. 9. Av = . gm1 (9.17 (a) Short-circuit output current of a cascode. as shown in Fig.gm1 f 1 + gm2rO1 jjr2 rO2 + rO1 jjr2 g . (9. Dividing gm1 vin between this impedance and rO1 .47) rO2 . we have iout = gm1 vin For typical transistors. We must therefore verify that only a negligible fraction of gm1 vin is “lost” in rO1 .53) Av = . which subsequently ﬂows through Q2 and hence through the output short: iout = gm1vin : That is.Gm Rout = .49) (9.cls v. 9 Cascode Stages and Current Mirrors Let us determine the voltage gain of the bipolar cascode with the aid of the above lemma.48) That is.45) Gm = gm1 : (9. and hence iout gm1vin : (9. 2006] June 30.51) gm2 and rO1 rO2 : (9. 1=gm2 rO1 jjr2 + g 1 jjrO2 m2 rO1 jjr2 : (9. (b) detailed view of (a).33) and (9. the approximation Gm = gm1 is reasonable.17(b).gm1 rO1 gm1rO1 jjr2 : .50) (9. 2007 at 13:42 430 (1) 430 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. rO1 .

This perspective may prove useful in some cases. in the circuit of Fig.16(b) is biased at a current of 1 mA.16(a). as a commonbase transistor that senses the small-signal current produced by Q1 . For example. Assume the load is an ideal current source. The high voltage gain of the cascode topology makes it attractive for many applications. An actual current source lowers the impedance seen at the output node and hence the voltage gain.53). 2007 at 13:42 431 (1) Sec.000? It is possible to view the cascode ampliﬁer as a common-emitter stage followed by a commonbase stage. We have gm1 Example 9. 9. the circuit illustrated in Fig.cls v. the cascode ampliﬁer exhibits a gain that is higher by a factor of gm1 rO1 jjr2 —a relatively large value because rO1 and r2 are much greater than 1=gm1 . rO 1 rO2 = 5 k . The bipolar cascode of Fig. the load is assumed to be an ideal current source.1 Cascode Stage 431 Compared to the simple CE stage of Fig. jAv j = 12.18.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.19(a) suffers from a low gain because the pnp current source introduces an impedance of only rO3 from the output node to ac ground. Illustrated in Fig. 9. 9. V CC I1 v out Q2 CB Vb Stage v in Q1 CE Stage Figure 9. 654: Cascoding thus raises the voltage gain by a factor of 65. If VA = 5 V and = 100 for both transistors. But.1 . 9. (9. 9. r1 r2 2600 . (9.57) . 9. Q2 .16(b).18 Cascode ampliﬁer as a cascade of a CE stage and a CB stage. the idea is to consider the cascode device. 2006] June 30. dropping the output impedance to Rout = rO3 jj f 1 + gm2 rO1 jjr2 rO2 + rO1 jjr2 g rO3 jj gm2 rO2 rO1 jjr2 + rO1 jjr2 : (9. determine the voltage gain.9 Solution = 26 .55) Exercise What Early voltage gives a gain of 5. Thus.54) gm1 rO1 jjr2 = 65:8 and from (9.56) (9.8.

gm1 f gm2rO2 rO1 jjr2 jj gm3 rO3 rO4 jjr3 g : (9. 9.58) (9.19(b).gm1Ron jjRop .1.61) This result represents the highest voltage gain that can be obtained in a cascode stage. Example 9. Recognizing that the short-circuit transconductance. For comparable values of Ron and Rop . (b) use of cascode in the load to raise the voltage gain. 2006] June 30.9 incorporates a cascode load using VA = 4 V and = 50.59) Note that. Ron and Rop . Gm .10 Suppose the circuit of Example 9.19 (a) Cascode with a simple current-source load.60) (9.53). The output impedance is now given by the parallel combination of those of the npn and pnp cascodes.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 that cascoding also raises the output impedance of current sources.cls v.63) Ron = 329 k : (9.5 is a good candidate and arriving at the stage depicted in Fig.7). Using (9. of the stage is still approximately equal to gm1 (why?). we express the voltage gain as Av = . What is the voltage gain? pnp transistors with Solution The load transistors carry a collector current of approximately 1 mA.62) (9. Rop = gm3 rO3 rO4 jjr3 = 151 k and (9.64) . we have Ron gm2 rO2 rO1 jjr2 Rop gm3 rO3 rO4 jjr3 : (9. respectively. 2007 at 13:42 432 (1) 432 Chap. rO1 (= rO2 ) may not be equal to rO3 (= rO4 ) . How should we realize the load current source to maintain a high gain? We know from Section 9. 9. since npn and pnp devices may display different Early voltages. postulating that the circuit of Fig. 9 Cascode Stages and Current Mirrors VCC V b3 VCC V b2 Q3 v out V b1 v in Q2 Q1 V b1 v in Q2 Q1 R out VCC r O3 V b2 v out V b1 v in Q2 Q1 Q4 Q3 R op R on (a) (b) Figure 9. this gain is about half of that expressed by (9. Thus.

the gain has fallen by approximately a factor of 3 because the pnp devices suffer from a lower Early voltage and .69).14 utilizes our knowledge of the output impedance to quickly provide the voltage gain of the stage. Since and r are inﬁnite for MOS devices (at low frequencies).1 Cascode Stage 433 It follows that jAv j = gm1 Ron jjRop = 3.69) Av = . 981: (9. (b) realization of load by a PMOS cascode.5 mA.53) to arrive at (9. It is important to take a step back and appreciate our analysis techniques. Our gradual approach to constructing this stage reveals the role of each device.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.20 (a) MOS cascode ampliﬁer.65) (9. this stage also provides a short-circuit transconductance Gm output resistance is given by (9. that M1 and . 9. 9. 9. 9. load. 2007 at 13:42 433 (1) Sec.gm1 1 + gm2 rO2 rO1 + rO2 . Exercise Repeat the above example for a collector bias current of 0. Note. 2006] June 30.cls v.68) (9.67) (9. compared to a simple common-source stage.20(a) with an ideal current-source VDD V b2 V b2 VDD I1 v out V b1 X v in M1 (a) M4 M3 v out M2 X M1 (b) R op R on V b1 v in M2 Figure 9. CMOS Cascode Ampliﬁer The foregoing analysis of the bipolar cascode ampliﬁer can readily be extended to the CMOS counterpart. yielding a voltage gain of gm1 if 1=gm2 rO1 . allowing straightforward calculation of the output impedance.66) Compared to the ideal current source case. however. we can also utilize (9. The (9.gm1rO1 gm2 rO2 : In other words. the lemma illustrated in Fig. The cascode of Fig.Gm Rout . the voltage gain has risen by a factor of gm2 rO2 (the intrinsic gain of the cascode device).22). Moreover. Depicted in Fig.19(b) proves quite formidable if we attempt to replace each transistor with its small-signal model and solve the resulting circuit.

2 = 30.74) ID1. As with the bipolar counterpart. With the particular choice of device parameters here.2 gm1. and (9. Illustrated in Fig. rO1 = rO2 . 9. determine the voltage gain.4 = 40.2 = 2nCox L 1.70) (9.1 and p = 0:15 V.71) Av . p Cox = 50 A=V2 . 9. n = 0:1 V. 9 Cascode Stages and Current Mirrors M2 need not exhibit equal transconductances or output resistances (their widths and lengths need not be the same) even though they carry equal currents (why?). W=L3.1 and s . ID1 = = ID4 = 0:5 mA.11 (9.72) The cascode ampliﬁer of Fig. gm1 rO3 = rO4 .20(b) incorporates the following device parameters: W=L1. 2006] June 30. If n Cox = 100 A=V2 .1 .gm1 gm2 rO2 rO1 jjgm3 rO3 rO4 : Example 9.73) (9.2 = 577 . the circuit exhibits the following output impedance components: Ron gm2 rO2 rO1 Rop gm3 rO3 rO4 : The voltage gain is therefore equal to (9. We have Solution = gm2 . the MOS cascode ampliﬁer must incorporate a cascode PMOS current source so as to maintain a high voltage gain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.20(b). gm3 = gm4 . 2007 at 13:42 434 (1) 434 Chap.cls v.

318: (9.77) rO3.2 = 20 k and (9.80) Av = .1 : Also. (9.78) Ron 693 k Rop 250 k and (9.81) (9.70) and (9.76) (9.79) (9.75) rO1.4 = 13:3 k : Equations (9.gm1Ron jjRop .82) .W gm3.2 = I1 n D1.71) thus respectively give (9.4 = 707 .

I1 does not. 2007 at 13:42 435 (1) Sec. consider the bipolar current source shown in Fig. A cellphone must maintain its performance at . 2006] June 30. we have R2 I1 (9. where VCC R1 I1 Q1 R2 VBE (a) VDD R1 I1 M1 R2 VGS (b) Figure 9. A similar situation arises in CMOS circuits. what happens if the temperature varies? The left-hand side remains constant if the resistors are made of the same material and hence vary by the same percentage. thereby mandating that the circuits operate properly across a range of supply voltages. the bias current of CE and CS stages is a function of the supply voltage—a serious issue because in practice.2. we can write I1 = 1 n Cox W VGS . for a desired current I1 .21(b). Thus. VTH 2 2 L = 1 n Cox W R R2 R VDD .25 mA. this voltage experiences some variation. But. gradually loses voltage as it is discharged. Illustrated in Fig. however. 9. For example. 9. 9.2 Current Mirrors 435 Exercise Explain why a lower bias current results in a higher output impedance in the above example. The rechargeable battery in a cellphone or laptop computer.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. R1 and R2 divide VCC down to the required VBE . To understand how temperature affects the biasing. That is.21(a). a MOS current source biased by means of a resistive divider suffers from dependence on VDD and temperature.2 Current Mirrors 9. where the base current is neglected. Calculate the output impedance for a drain current of 0. contains two temperature-dependent parameters: VT = kT=q and IS . even if the base-emitter voltage remains constant with temperature.1 Initial Thoughts The biasing techniques studied for bipolar and MOS ampliﬁers in Chapters 4 and 6 prove inadequate for high-performance microelectronic circuits. The right-hand side. 9.21 Impractical biasing of (a) bipolar and (b) MOS current sources. Here.83) R1 + R2 VCC = VT ln IS . for example.20 C in Finland and +50 C in Saudi Arabia. Another critical issue in biasing relates to ambient temperature variations. VTH 2 L 1+ 2 .

84) : (9. 2 (9.85) .

2007 at 13:42 436 (1) 436 Chap. 9. this scheme is studied in more advanced books [1].and temperature-independent voltages and currents exists and appears in almost all microelectronic systems.22 Concept of current mirror. 9. Icopy = IREF or 2IREF . VX = VBE . In summary.23(a) be realized? The black box generates an output voltage.2 Bipolar Current Mirror Since the current source generating Icopy in Fig. (c) bipolar current mirror. such that Q1 carries a current equal to IREF : IS1 exp VX = IREF . The bandgap circuit by itself does not solve all of our problems! An integrated circuit may incorporate hundreds of current sources. the complexity of the bandgap prohibits its use for each current source in a large integrated circuit. a bandgap reference can provide a “golden current” while requiring a few tens of devices. e.23 (a) Conceptual illustration of current copying. 2006] June 30.2. In order to avoid supply and temperature dependence. V T (9. an elegant method of creating supply. 9.) VCC I REF X VBE (a) (b) (c) VCC I copy I REF Q REF V1 I REF Q REF VCC I copy ? Q1 X Q 1 Current Mirror Figure 9. the typical biasing schemes introduced in Chapters 4 and 6 fail to establish a constant collector or drain current if the supply voltage or the ambient temperature are subject to change. (The MOS counterpart is similar. Called the “bandgap reference circuit” and employing several tens of devices.cls v. How should the black box of Fig.22 conceptually illustrates our goal here. VCC I REF I copy Current Mirror Figure 9. For example. as the load impedance of CE or CS stages to achieve a high gain. Fortunately.23(a). We must therefore seek a method of “copying” the golden current without duplicating the entire bandgap circuitry. where Q1 operates in the forward active region and the black box guarantees Icopy = IREF regardless of temperature or transistor characteristics.86) . I1 is not constant even if VGS is. (b) voltage proportional to natural logarithm of current.. Figure 9. Unfortunately. 9. 9 Cascode Stages and Current Mirrors Since both the mobility and the threshold voltage vary with temperature.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Let us summarize our thoughts thus far. The golden current generated by a bandgap reference is “read” by the current mirror and a copy having the same characteristics as those of IREF is produced.22 must be implemented as a bipolar or MOS transistor. Current mirrors serve this purpose.g. we surmise that the current mirror resembles the topology shown in Fig.

VCC I REF Q REF I copy ? Q1 Figure 9.2 Current Mirrors 437 where Early effect is neglected. Explain what happens. From another perspective.REF (9. V1 = VX if IS. the black box satisﬁes the following relationship: VX = VT ln IREF : I S1 (9. Note that VX does vary with temperature but such that Icopy does not. 2006] June 30. 9. we can write IREF = IS.24 Solution The circuit provides no path for the base currents of the transistors.e.24). More fundamentally. S. We say Q1 “mirrors” or copies the current ﬂowing through QREF . since QREF and Q1 have equal base-emitter voltages. we neglect the base currents.87). 2007 at 13:42 437 (1) Sec. This holds even though VT and IS vary with temperature. a single diode-connected device satisﬁes (9. . Example 9. the base-emitter voltage of the devices is not deﬁned. we have V1 = VT ln IIREF . the inverse function of bipolar transistor characteristics. 9. i.91) which reduces to Icopy = IREF if QREF and Q1 are identical. S.REF = IS1 ..cls v.REF (9.90) Icopy = I IS1 IREF .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. From one perspective. For now.87) We must therefore seek a circuit whose output voltage is proportional to the natural logarithm of its input.23(c) consolidates our thoughts. 9. Neglecting the base-current in Fig.. Fortunately. if QREF is identical to Q1 .88) where IS. QREF takes the natural logarithm of IREF and Q1 takes the exponential of VX . Figure 9. Thus.89) (9. i.REF denotes the reverse saturation current of QREF .23(b). In other words.12 An electrical engineering student who is excited by the concept of the current mirror constructs the circuit but forgets to tie the base of QREF to its collector (Fig. displaying the current mirror circuitry. The lack of the base currents translates to Icopy = 0.e.REF exp VX VT Icopy = IS1 exp VX VT and hence (9. thereby yielding Icopy = IREF .

how do we obtain different values for these copies. yields (9. Here. thus arriving at the circuit shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VT lnIREF =IS.. In what region does QREF operate? We must now address two important questions. etc. 2007 at 13:42 438 (1) 438 Chap. given by Icopy.j = I IS.j .26(a).94) . how do we make additional copies of IREF to feed different parts of an integrated circuit? Second. 2IREF .25 Solution While i.j = IS.26(b) for simplicity. we recognize that VX can serve as the base-emitter voltage of multiple transistors. First. 9 Cascode Stages and Current Mirrors Exercise What is the region of operation of QREF ? Example 9. 2006] June 30. Q1 now carries a ﬁnite current. 9. VCC I REF Q REF VX I copy ? I REF Q REF VX VX VCC I copy ? Q1 Q1 Figure 9.22(c). The student has forgotten that a diodeconnected device is necessary here to ensure that VX remains proportional to lnIREF =IS.j IREF : S. V T (9.92) which is a function of temperature if VX is constant.g.REF . hoping that the battery VX provides the base currents and deﬁnes the base-emitter voltage of QREF and Q1 .13 Realizing the mistake in the above circuit. 9. 9. Explain what happens.21. e.REF (9. transistor Qj carries a current Icopy. the biasing of Q1 is no different from that in Fig. 5IREF . along with (9.25. 9. the student makes the modiﬁcation shown in Fig.e.87).. Icopy = IS1 exp VX . Exercise Suppose VX is slightly greater than the necessary value. V T which. 9.j exp VX .REF .93) Icopy.cls v. The circuit is often drawn as in Fig.? Considering the topology in Fig.

75 mA Q1 Q2 Q3 0. VCC I REF Q REF 0. Recall from Chapter 4 that this is equivalent to placing n unit transistors in parallel.j ( the emitter area of Qj ) is chosen to be n times IS.26 (a) Multiple copies of a reference current. all transistors are identical to ensure proper scaling of IREF .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Here.j = nIREF .5 mA Q4 Q5 Figure 9. We say the copies are “scaled” with respect to IREF .94) readily answers the second question as well: If IS. Using a bandgap reference current of 0.27 illustrates the circuit. Solution Figure 9.26(c) depicts an example where Q1 -Q3 are identical to QREF .27 . The key point here is that multiple copies of IREF can be generated with minimal additional complexity because IREF and QREF themselves need not be duplicated.cls v.14 A multistage ampliﬁer incorporates two current sources of values 0.25 mA.25 mA 0. 2006] June 30. providing Icopy = 3IREF .REF ( the emitter area of QREF ). Neglect the effect of the base current for now. (b) simpliﬁed drawing of (a).2 Current Mirrors VCC I REF Q REF I copy1 I copy2 I copy3 439 Q1 Q2 Q3 (a) VCC I REF Q1 Q REF (b) VCC I copy1 Q2 I copy2 Q3 Q REF (c) I copy3 I REF Q1 Q2 I copy = 3 I REF Q3 Figure 9. (c) combining output currents to generate larger copies. 2007 at 13:42 439 (1) Sec. Figure 9. 9. Equation (9. Example 9. design the required current sources.5 mA.75 mA and 0. then Icopy.

29 . 9. the idea is VCC I REF 0. we have IREF = 3IS exp VX VT VX Icopy = IS exp V T and hence (9. 2006] June 30. how do we create fractions of IREF ? This is accomplished by realizing QREF itself as multiple parallel transistors. VCC I REF 0. to begin with a larger IS.97) It is desired to generate two currents equal to 50 A and 500 A from a reference of 200 A. Exempliﬁed by the circuit in Fig.89) and (9. But. The use of multiple transistors in parallel provides an accurate means of scaling the reference in current mirrors.29).28 Copying a fraction of a reference current . denoted by 10AE for simplicity.90). 9 Cascode Stages and Current Mirrors Exercise Repeat the above example if the bandgap reference current is 0. Q1 . 2007 at 13:42 440 (1) 440 Chap. 9. we must employ four unit transistors for QREF such that each carries 50 A.15 (9.95) (9. Repeating the expressions in (9.28.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 mA. Design the current mirror circuit. can generate a smaller current.cls v. To produce the smaller current.25 mA I copy Q1 X Q REF1 Q REF2 Q REF3 Figure 9.REF (= 3IS here) so that a unit transistor.2 mA Solution I copy1 X Q1 AE 4A E I copy2 Q2 10 A E Figure 9.96) Icopy = 1 IREF : 3 Example 9. A unit transistor thus generates 50 A (Fig. The current of 500 A requires 10 unit transistors.

9. 9.cls v.F . 9. since IC. (9. the bipolar current mirror can be modiﬁed as illustrated in Fig.100) = Icopy =n. thereby reducing the effect of the base currents by a factor of . 2006] June 30. respectively. Our objective is to calculate Icopy .REF (9. Thus. 2007 at 13:42 441 (1) Sec. as the copied current ( n) increases.2 Current Mirrors 441 Exercise Repeat the above example for a reference current of 150 A. VCC I REF Q REF AE I copy nβ I copy Q1 I copy nA E β Figure 9.REF = Icopy n : Writing a KCL at X therefore yields (9. leads to Icopy = nIREF : 1 + 1 n + 1 (9. an effect leading to a signiﬁcant error as the number of copies (i. 1 IC. recognizing that QREF and Q1 still have equal base-emitter voltages and hence carry currents with a ratio of n.101) To suppress the above error.99) 1 IREF = IC. Effect of Base Current We have thus far neglected the base current drawn from node X in Fig.REF + Icopy n + Icopy .98) (9. which.30 Error due to base currents.30. the total copied current) increases. the base currents of Q1 and QREF can be expressed as IB1 = Icopy 1 IB.F = Icopy + Icopy n .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. so does the error in Icopy . assuming IC. the second term in the denominator is much less than unity and Icopy nIREF . The error arises because a fraction of IREF ﬂows through the bases rather than through the collector of QREF . where AE and nAE denote one unit transistor and n unit transistors. Here. More speciﬁcally. emitter follower QF is interposed between the collector of QREF and node X . However.e.F IE.. we can repeat the above analysis by writing a KCL at X : For a large and moderate n. 9.26(a) by all transistors.31.102) . We analyze the error with the aid of the diagram shown in Fig.

cls v. 2006] June 30. 9 VCC I REF P Q REF AE I copy nβ I B. obtaining the base current of QF as 1 IB. 2007 at 13:42 442 (1) 442 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.F QF X I copy Q1 Cascode Stages and Current Mirrors I copy nA E β Figure 9.F I C.31 Addition of emitter follower to reduce error due to base currents.F = Icopy 1 + n : 2 Another KCL at node P gives .

F + IC. (9.REF .103) IREF = IB.

110) . Noting that Icopy1 . 9.108) Icopy1 = IREF 4 + 15 Icopy2 = 10IREF : 15 4+ With the addition of emitter follower (Fig.REF : copy1 Thus.104) (9.106) That is. Icopy 1 + 1 + Icopy = 2 n n and hence (9. we have at X : (9.REF (the total current ﬂowing through four unit transistors) still retain their nominal ratios (why?). Compute the error in Icopy1 and Icopy2 in Fig.REF + Icopy1 + Icopy2 + IC.16 Solution IREF = IC. (9.REF = 4I + Icopy1 + 10Icopy1 + IC.105) Icopy = nIREF : 1 + 12 n + 1 (9.32).107) (9.109) (9. and IC.29 before and after adding a follower. Icopy2 . 9. the error is lowered by a factor of . we write a KCL at X : Example 9.

REF + Icopy1 + Icopy2 = 4Icopy1 + Icopy1 + 10Icopy1 = 15Icopy1 : A KCL at P therefore yields (9.2 Current Mirrors VCC I REF P 0.115) copy1 and hence Icopy1 = IREF 15 4+ 2 (9. 2006] June 30. if QREF and Q2 are identical and the base currents negligible. The current source can be realized as a pnp transistor operating in the active region [Fig. 9. In analogy with the npn counterpart of Fig. 2007 at 13:42 443 (1) Sec. i. 2 (9.112) (9. then Q2 Q1 carries a current equal to IREF .REF 2 = 15Icopy1 + 4I .cls v.116) Icopy2 = 10IREF : 15 4+ 2 (9.114) (9.113) IREF = 15Icopy1 + IC.F = IC.33(c)..111) (9.2 mA 443 QF Q 1 X 4A E I copy1 AE I copy2 Q2 10 A E Figure 9. we form the pnp current mirror depicted in Fig. We must therefore deﬁne the bias current of Q2 properly.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9. 9. the reference transistor has an area of 3AE . 9.23(c).33(a). PNP Mirrors Consider the common-emitter stage shown in Fig. 9. .e.33(b)].32 IC. For example.117) Exercise Calculate Icopy1 if one of the four unit transistors is omitted. where a current source serves as a load to achieve a high voltage gain.

a fundamental constant of the technology and independent of the bias current. we observe that QM draws a current of IREF from QREF 2 .119) (9.) The voltage gain can be written as Solution Av = . QREF 2 . . we obtain a total supply current of 800 A.33 (a) CE stage with current-source load. and Q2 are identical and neglecting the base currents. with the above choice of Early voltages. QM . Note that the base currents introduce a cumulative error as IREF is copied onto IC.17 Design the circuit of Fig. it is assumed that the golden current ﬂows from VCC to node X . requiring that the (emitter) area of Q2 be 7 times that of QREF .M . Assume VA. (b) realization of current source by a pnp device.M onto IC 2 . IREF = 100 A.85:5: (9. 9. V1 VVA.pnp = 4 V. In the mirror of Fig. From the power budget and VCC = 2:5 V.cls v. the circuit’s gain cannot reach 100. (c) proper biasing of Q2 .23(c). and VCC = 2:5 V.118) (9.npn + VA.pnp = . 9. Thus. Thus. whereas in Fig.33(c) for a voltage gain of 100 and a power budget of 2 mW.18 = 25 A. Assuming for simplicity that QREF 1 .npn = 5 V. How do we generate the latter from the former? It is possible to combine the npn and pnp mirrors for this purpose. 9. 2006] June 30. 9. and IC.gm1rO1 jjrO2 = . We can also create various scaling scenarios between QREF 1 and QM and between QREF 2 and Q2 . thereby forcing the same current through Q2 and Q1 .5! This is because the gain of the stage is simply given by the Early voltages and VT . Exercise What Early voltage is necessary for a voltage gain of 100? We must now address an interesting problem. as illustrated in Fig. Example 9. of which 100 A is dedicated to IREF and QREF . 9 VCC Vb v out v in Q1 v in Q1 Q2 v out Cascode Stages and Current Mirrors VCC Q REF X v in Q2 v out I REF Q1 VCC I1 (a) (b) (c) Figure 9. Q1 and Q2 are biased at a current of 700 A.npn VA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34.34 at a collector current of 1 mA while IREF Example 9.120) What happened here?! We sought a gain of 100 but inevitably obtained a value of 85. VA. 2007 at 13:42 444 (1) 444 Chap. (For example.pnp T A.33(c) it ﬂows from X to ground. QREF incorporates one unit device and Q1 seven unit devices. We wish to bias Q1 and Q2 in Fig. 9.

the npn and pnp scaling factors can be swapped.M = 10IREF jIC 2 j = 4IC.M or (9.122) IC.123) (9. For an overall scaling factor of 1 mA=25 A = 40. the four transistors in the current mirror circuitry require 15 units. This is why current mirrors are rarely used in discrete design.M : (9. 9. Icopy is 30 higher than IREF . 16 units. the two transistors suffer from signiﬁcant IS mismatch. 9. and in the latter case.23(c).REF 2 as it would necessitate 43 units. Note that we have implicitly dismissed the case IC. we can choose either Solution IC. Unfortunately.124) (In each case. 2006] June 30. Solution It is possible that the two transistors were fabricated in different batches and hence underwent slightly different processing. Exercise How much IS mismatch results in a 30% collector current mismatch? .2 Current Mirrors VCC I REF I C. 2007 at 13:42 445 (1) Sec.REF 1 and IC 2 = IC.M = 40IC.) In the former case.19 An electrical engineering student purchases two nominally identical discrete bipolar transistors and constructs the current mirror shown in Fig. Choose the scaling factors in the circuit so as to minimize the number of unit transistors.M Q REF1 X1 QM Q REF2 X2 v in Q2 v out Q1 445 Figure 9.121) (9.34 Generation of current for pnp devices. Exercise Calculate the exact value of IC 2 if = 50 for all transistors. As a result.cls v. Explain why.M = 8IREF jIC 2 j = 5IC. Random variations during manufacturing may lead to changes in the device parameters and even the emitter area. Example 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

2006] June 30. 9.23(a) as in Fig. (c) MOS current mirror.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. drawing the MOS counterpart of Fig. In particular. we recognize that the black box must generate VX such that VDD I REF X M1 VGS (a) (b) (c) VDD I copy1 I REF M REF VX I REF M REF VDD I copy ? X M 1 Current Mirror Figure 9.3 MOS Current Mirror The developments in Section 9.2 can be applied to MOS current mirrors as well. (b) generation of a voltage proportional to square root of current. 1 C W 2 n ox L .cls v. 9. 2007 at 13:42 446 (1) 446 Chap.2.2. 9 Cascode Stages and Current Mirrors 9.35(a).35 (a) Conceptual illustration of copying a current by an NMOS device.

VTH 1 2 = IREF .125) where channel-length modulation is neglected. (9. 1 VX . the black box must satisfy the following input (current)/output (voltage) characteristic: v u VX = u 2IREF u t n Cox . Thus.

or (2) the drain currents of the two transistors can be expressed as 2 ID. thus arriving at the NMOS current mirror depicted in Fig. 9.126) That is. W L + VTH 1 : 1 (9. it must operate as a “square-root” circuit. 9. we can view the circuit’s operation from two perspectives: (1) MREF takes the square root of IREF and M1 squares the result.35(c). VTH .35(b)]. From Chapter 6. As with the bipolar version.REF = 1 n Cox W 2 L REF VX . we recall that a diodeconnected MOSFET provides such a characteristic [Fig.

VTH 2 . L 1 . 1 Icopy = 2 n Cox W VX .

127) (9. (9. It follows that which reduces to Icopy = IREF Icopy = .128) where the threshold voltages are assumed equal.

. L REF if the two transistors are identical. WL 1 IREF .

W (9.36).13 decides to try the MOS counterpart. .20 The student working on the circuits in Examples 9. 9.12 and 9. thinking that the gate current is zero and hence leaving the gates ﬂoating (Fig.129) Example 9. Explain what happens.

2 mA VDD V in2 M2 Vout2 0. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.21 An integrated circuit employs the source follower and the common-source stage shown in Fig. Icopy is very poorly deﬁned.5 mA I1 (a) I2 VDD V in1 VDD I REF W 3( ( L 0.3 mA VDD V in2 M2 Vout2 I2 M I2 5( M1 Vout1 I1 M I1 M REF 2( W ( L (b) W ( L Figure 9. 9. e.129) and hence a copy current independent of device parameters and temperature. 9.cls v. Design a current mirror that produces I1 and I2 from a 0. In other words. an initial condition created at node X when the power supply is turned on. Example 9.36 Solution This circuit is not a current mirror because only a diode-connected device can establish (9.37(a).26. 2007 at 13:42 447 (1) Sec. they can assume any voltage.3-mA reference.37 .g.2 Current Mirrors VDD I REF X M REF Floating Node 447 I copy ? M1 Figure 9. Exercise Is MREF always off in this circuit? Generation of additional copies of IREF with different scaling factors also follows the principles shown in Fig. VDD V in1 M1 Vout1 0. Since the gates of MREF and M1 are ﬂoating. 9. The following example illustrates these concepts..

Investigated in Problem 53. This effect is beyond the scope of this book. 9. 9. leading to “tunneling” and hence noticeable gate current. CS Stage VDD Follower Vout1 VDD I REF V in1 V in2 Vout2 M REF V in3 Follower CS Stage VDD V in4 Vout3 Vout4 Figure 9. this effect mandates circuit modiﬁcations that are described in more advanced texts [1]. 9. resulting in a high output impedance. 6 In deep-submicron CMOS technologies. The idea of combining NMOS and PMOS current mirrors follows the bipolar counterpart depicted in Fig. Figure 9. 2007 at 13:42 448 (1) 448 Chap. 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we select an aspect ratio of 3W=L for the diode-connected device.3 Chapter Summary Stacking a transistor atop another forms a cascode structure. 2W=L for MI 1 . channel-length modulation in the current-source transistors does lead to additional errors.28 and 9. 9.38 NMOS and PMOS current mirrors in a typical circuit. the gate oxide thickness is reduced to less than 30 A.37(b) shows the overall circuit.6 MOS mirrors need not resort to the technique shown in Fig.31. Since MOS devices draw a negligible gate current. The cascode topology can also be considered an extreme case of source or emitter degeneration.cls v. 2006] June 30.29. The circuit of Fig.34. . On the other hand. 9 Cascode Stages and Current Mirrors Following the methods depicted in Figs. Solution Exercise Repeat the above example if IREF = 0:8 mA.38 exempliﬁes these ideas. and 5W=L for MI 2 .

Gm Rout . Current mirrors can scale a reference current by integer or non-integer factors. 2006] June 30.e. 9. (b) Noting that VCE 2 = Vb1 . 4. where Gm denotes the short-circuit transconductance of the ampliﬁer. 9. VCC RC V1 V b1 V b2 Q1 Q2 Figure 9. assuming a bias current of 0. The load of a cascode stage is also realized as a cascode circuit so as to approach an ideal current source. resistive dividers tied to the base or gate of transistors result in supply.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9.17 A and = 100 for both transistors. For example. In the circuit of Fig. where VCC = 2:5 V. a cascode stage can operate as a high-gain ampliﬁer. Current mirrors can “copy” a well-deﬁned reference current numerous times for various blocks in an analog system.2(a).39.42.41. In the bipolar cascode stage of Fig.41 is realized as shown in Fig. With its high output impedance.. Suppose the circuit of Fig.3 Chapter Summary 449 The voltage gain of an ampliﬁer can be expressed as . Setting the bias currents of analog circuits to well-deﬁned values is difﬁcult. This relationship indicates that the gain of ampliﬁers can be maximized by maximing their output impedance. assuming I1 is ideal and equal to 0. IC 1 = 0:5 mA while IC 2 = 1 mA. Current mirrors are rarely used in disrcete design as their accuracy depends on matching between transistors. If VBE or VGS are well-deﬁned. Neglect the Early effect. (a) Repeat Problem 1 for this circuit. 6. then IC or ID are not. VBE 1 .39 3.1 for the circuit shown in Fig.and temperaturedependent currents. i. a parasitic resistor RP has appeared in the cascode circuits of Fig. Due to a manufacturing error. 9. Determine the output resistance in each case. (b) With the minimum allowable value of Vb1 .5 mA. 9. 9. 9. compute the maximum allowable value of RC such that Q1 experiences a base-collector forward bias of no more than 300 mV. Consider the cascode stage depicted in Fig. 5.40. determine the value of Vb1 such that Q2 experiences a base-collector forward bias of only 300 mV.cls v. 9. 2007 at 13:42 449 (1) Sec. we have chosen RC = 1 k and VCC = 2:5 V. Problems 1. Estimate the maximum allowable bias current if each transistor sustains a base-collector forward bias of 200 mV. Repeat Example 9. IS = 6 10. (a) Compute Vb2 for a bias current of 1 mA. 2.39.5 mA. where Q3 plays the role of .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.44. 9 Cascode Stages and Current Mirrors R out R out V b1 RP RP V b2 Q2 Q1 V b1 Q2 V b2 Q1 (a) (b) (c) (d) Figure 9.p . determine the output impedance of the V bn Qn Figure 9. a student decides to extend the idea as illustrated in Fig. 9. a student adventurously swaps the collector and base terminals of the degeneration transistor. While constructing a cascode stage. arriving at the circuit shown in Fig. Assuming VA1 = VA2 = VA. 9. 2006] June 30.42 circuit.43 student can achieve? Assume the transistors are identical. 2007 at 13:42 450 (1) 450 R out V b1 RP V b2 Q2 V b2 Q2 Q1 V b1 Q1 RP R out Chap.n and VA3 = VA.cls v.43.40 R out VCC V b1 V b2 Q1 Q2 I1 Figure 9. What is the maximum output impedance that the R out V b1 V b2 Q1 Q2 I1 . . Excited by the output impedance “boosting” capability of cascodes.41 R out VCC V b1 V b2 Q1 Q2 Q3 V b3 Figure 9. 7. 8.

Assume 1. 15.9) and explain why the result resembles that in Eq. (b) Compare the result with that of a cascode stage for a given bias current (IC 1 ) and explain why this is generally not a good idea. calculate the output impedance of the circuit.16 and = 100.45 must provide a bias current of 0. (a) Writing gm = 2n Cox W=LID .9) for the bipolar counterpart.44 (a) Assuming both transistors operate in the active region. 2007 at 13:42 451 (1) Sec.cls v.23) in terms of ID and plot the result as a function of ID . Which one is a stronger function of the bias current? The cascode current source shown in Fig. (a) Calculate the required value of Vb2 . 9. (9. (9.5 V V b2 V b1 Q2 X Q1 Circuit 0. allowing the approximation VA VT if 100. 9. and W=L2 = 40=0:18. The pnp cascode depicted in Fig. Using this approximation. the Early voltage reaches tens of volts. (a) Neglecting channel-length modulation. compute the maximum tolerable value of . 9. p . 14. where VDD = 1:8 V. 9. express Eq.1 . Assume n Cox = 100 A/V2 and VTH = 0:4 V. 10. Consider the circuit shown in Fig.5 mA with an output impedance of at least 50 k . Explain which ones are considered cascode stages.5 mA to a circuit.12). (9. 9. determine the output impedance of the circuit.5 mA Figure 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume n Cox = 100 A/V2 and VTH = 0:4 V. (b) Noting that VX = Vb1 + jVBE 1 j. If n Cox = 100 A/V2 and W=L = 20=0:18 for both transistors.47 must provide a bias current of 0. W=L1 = 20=0:18. 12.46. If VCC = 2. determine the maximum allowable value of Vb1 such that Q2 experiences a base-collector forward bias of only 200 mV. What is the minimum tolerable value of Vb1 if M2 must remain in saturation? (b) Assuming = 0:1 V. Determine the output impedance of each circuit shown in Fig. 13.49. 9. (9. The MOS cascode of Fig. For discrete bipolar transistors. compute the required value of Vb2 .48 must be designed for a bias current of 0. 9.45 11. IS = 10.5 mA.3 Chapter Summary R out V b1 V b2 Q2 Q1 451 Figure 9. 2006] June 30. (b) Compare this expression with that in Eq. simplify Eq.

2007 at 13:42 452 (1) 452 Chap. 2006] June 30.50. what is the highest allowable value of Vb1 ? (b) With such a value chosen for Vb1 .cls v.51 must provide a bias current of 0.46 R out V b1 V b2 M1 M2 Figure 9.1 .48 (a) If we require a bias current of 1 mA and RD = 500 . what is the value of VX ? 16.5 mA with an output impedance of 40 k .18 Figure 9. If p Cox = 50 A/V2 and = 0:2 V. 9 Cascode Stages and Current Mirrors R out Q1 V b1 RP R out R out V b1 V b2 RB Q1 Q2 (a) R out V b1 V b1 V b2 RB (b) Q1 RB Q2 (c) Q1 Q2 Q2 (d) VCC RE V b2 V b1 Q2 Q1 V b2 VCC Q2 Q1 R out Vb V b2 I1 Q1 V b2 VCC I1 Q2 R out (g) R out (e) (f) Figure 9. Compute the output resistance of the circuits depicted in Fig. 9. Assume all of the transistors operate in saturation and gm rO 1. . 17. determine the required value of W=L1 = W=L2 . The PMOS cascode of Fig.18 M 2 W = 20 L 0.47 V b1 V b2 M 1 W = 30 L 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9.

Assume all of the transistors operate in saturation and gm rO 1. The cascode stage of Fig. 20. 9. (9.50 VDD V b2 V b1 M2 M1 R out Figure 9. The PMOS cascode of Fig.53) reduces to 2 Av V V VA V . a student adventurously constructs the circuit depicted in Fig.51 18.53.52. explain what happens if the widths of both transistors are increased by a factor of N while the transistor lengths and bias currents remain unchanged.51 is designed for a given output impedance. 19. T A+ T (9. determine the minimum required value of VA1 = VA2 . 21. If 1 = 2 = 100. Assume L. 2007 at 13:42 453 (1) Sec. Rout .49 R out R out V b1 RG M2 (a) R out V b1 V b2 V b3 R out M1 V b1 M1 M2 (b) M1 M3 M2 (c) V b1 M2 M1 (d) Figure 9. Compute the short-circuit transconductance and the voltage gain of each of the stages in Fig. Determine the output impedance of the stages shown in Fig. Having learned about the high voltage gain of the cascode stage. 9.3 Chapter Summary VDD RD V1 V b1 X V b2 M2 M1 453 Figure 9. 9. 22.cls v. 23. Assume 0 and VA 1.1 . (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9. Prove that Eq. 2006] June 30.23).130) a quantity independent of the bias current.16(b) must be designed for a voltage gain of 500. where the input is applied to the base of Q2 . Using Eq. 9.54. 9. Assume I1 = 1 mA.

(a) Replacing Q1 with rO1 . 9 Cascode Stages and Current Mirrors R out VDD V b1 V b2 M1 M2 M3 V b3 RG (a) (b) VDD V b2 V b1 M2 M1 R out (c) R out V b1 V b2 V b3 (d) M1 M2 M3 V b3 M3 Figure 9.53 rather than to the base of Q1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. explain intuitively why the voltage gain of this stage cannot be as high as that of the cascode. 9. 25.cls v. . (b) Assuming gm rO 1.52 VCC VDD Vb M2 Vout V in M1 Vb M1 V in VDD M2 Vout V in Q1 RE (c) (d) VCC V in Q2 Vout Vb Q1 RE Vb Q2 Vout (a) (b) VDD RE V b2 M2 Vout M1 V in RS (e) VDD RE V in M2 Vout M1 RS (f) (g) VCC RE V in V b1 Q2 Vout RC V b1 Figure 9. 2007 at 13:42 454 (1) 454 R out V b1 M1 M2 Chap. 2006] June 30. Calculate the voltage gain of each stage illustrated in Fig. Determine the short-circuit transconductance and the voltage gain of the circuit shown in Fig. 9. 24.55. compute the short-circuit transconductance and the voltage gain.56.

The MOS cascode of Fig. 2006] June 30. (9. determine the required value of W=L1 = W=L2 . 28. 3 = 4 = P .19 and assume 1 = 2 = N .72) in terms of the device parameters and plot the result as a function of ID .P . Consider the cascode ampliﬁer of Fig. a bipolar cascode ampliﬁer has been conﬁgured as shown in Fig. 2007 at 13:42 455 (1) Sec. (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. explain what happens if the widths of the transistors are increased by a factor of N while the transistor lengths and bias currents remain p . If n Cox = 100 A=V2 and = 0:1 V.1 for both transistors. 9. Writing gm = 2n Cox W=LID and rO = 1=ID . 9. express Eq.61) in terms of these quantities.3 Chapter Summary VCC I1 Vout V in V b1 Q2 Q1 455 Figure 9. 9. Does the result depend on the bias current? 27. (9. Express Eq. 29.55 VCC I1 Vout V b1 RP V in Q2 V in Q2 Q1 V b1 Q1 RP I1 Vout V b1 V in Q1 Q2 RE V in Q2 VCC I1 Vout V b1 Q1 VCC I1 Vout Q3 VCC V b3 VCC (a) (b) (c) (d) Figure 9. 9.57. 30.56 26.20(a) must provide a voltage gain of 200. The MOS cascode of Fig. Due to a manufacturing error. Determine the voltage gain of the circuit.20(a) is designed for a given voltage gain.54 VCC I1 Vout V b2 V b1 V in Q2 Q1 Figure 9. Av . Using Eq.cls v. V31 = VA4 = VA. VA1 = VA2 = VA.N .79) and the result obtained in Problem 28. 9.

Due to a manufacturing error.59 . VDD V b4 V b3 M2 V b2 V in M1 RP M4 M3 Vout V b2 V in M2 M1 RP V b4 V b3 VDD M4 M3 Vout V b2 V b1 M2 M1 V in M5 V in M5 V b4 V b3 VDD M4 M3 Vout V b2 V b1 M2 M1 V b4 V b3 VDD M4 M3 Vout (a) (b) (c) (d) Figure 9. a CMOS cascode ampliﬁer has been conﬁgured as shown in Fig.58. n = 0:1 V. calculate the bias current such that the circuit achieves a voltage gain of 500.59. 9 VCC Q4 V b2 Q3 Cascode Stages and Current Mirrors v out V b1 v in Q2 Q1 Figure 9.57 unchanged.1 . If n Cox = 100 A=V2 . Calculate the voltage gain of the circuit. W=L1 = = W=L4 = 20=0:18. and p Cox = 50 A=V2 . 9. In the cascode stage of Fig.cls v. and p = 0:15 V.20(b). 31.58 33. 34. 32. Determine the voltage gain of each circuit in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VDD V b4 V b3 V b2 V in M4 M3 Vout M2 M1 V b1 Figure 9. 2006] June 30. 9. Repeat Problem 30 if the lengths of both transistors are increased by a factor of N while the transistor widths and bias currents remain unchanged. 9. 2007 at 13:42 456 (1) 456 Chap.1 . Assume gm rO 1.

42.64. 2007 at 13:42 457 (1) Sec. express the value of RP in terms of other circuit VCC I REF Q REF I1 Q1 RP Figure 9. Due to a manufacturing error.63.15 if the reference current is equal to 180 A. Having learned about the logarithmic function of the circuit in Fig. Explain what happens. 9. . deﬁned as @I1 =@VCC . Due to a manufacturing error.60 39. express the value of RP in terms of other circuit parameters. 38. If I1 is half of its nominal value. We wish to generate two currents equal to 50 A and 230 A from a reference of 130 A. The parameters n Cox and VTH in Eq. 9.23(b). parameters. From Eq.61. Assume QREF and Q1 are identical. 9. If I1 is 10% greater than its nominal value.85) also vary with the fabrication process. 9. Explain intuitively why this sensitivity is proportional to the transconductance of Q1 .62 41. IX R1 Q1 V1 Q2 V REF Figure 9. (9. a student remembers the logarithmic ampliﬁer studied in Chapter 8 and constructs the circuit depicted in Fig. Assume QREF and Q1 are identical and 1. Repeat Example 9. resistor RP has appeared in series with the emitter of Q1 in Fig. 37. 9. (9. 9. determine the sensitivity of I1 to VCC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.61 40.85) (in terms of VDD ). but assuming that I1 is twice its nominal value.62. 2006] June 30. (9. Repeat Problem 40 for the circuit shown in Fig.cls v. Q1 V1 V REF R1 IX Q2 Figure 9. Repeat Problem 38 for the topology shown in Fig. Neglect the base curents. 43.3 Chapter Summary 457 35. 36. 44. Design an npn current mirror for this purpose.83). (Integrated circuits fabricated in different batches exhibit slightly different parameters.) Determine the sensitivity of I1 to VTH and explain why this issue becomes more serious at low supply voltages. 9. resistor RP has appeared in series with the base of QREF in Fig.60. Repeat Problem 35 for Eq.

67.64 VCC I REF Q REF I1 RP Q1 Figure 9. Taking base currents into account. Normalize the error to the nominal value of Icopy .cls v. compute the error in Icopy for each of the circuits illustrated in Fig. does I1 change if the threshold voltage of both transistors increases by V ? . 48. 9. 2007 at 13:42 458 (1) 458 Chap. Determine the value of RP in the circuit of Fig. 2006] June 30.65 45. Repeat Problem 44 for the circuit shown in Fig.66 47.63 VCC I REF Q REF I1 RP Q1 Figure 9. determine the value of Icopy in each circuit depicted in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. With this choice of RP . 9.68.69 such that I1 = IREF =2. With this choice of RP . does I1 change if the threshold voltage of both transistors increases by V ? 50. 9 VCC I REF Q REF RP Cascode Stages and Current Mirrors I1 Q1 Figure 9. 9. Determine the value of RP in the circuit of Fig. 46. 9. Calculate the error in Icopy for the circuits shown in Fig. Taking base currents into account.65.66. 49.70 such that I1 = 2IREF . but assuming I1 is 10% less than its nominal value. 9. 9. VCC I REF Q1 AE Q REF (a) VCC I copy 5A E VCC I copy AE I REF Q1 2A E I REF Q1 5A E I copy 3A E Q2 I2 5A E Q REF (b) Q REF (c) Figure 9.

35(c) and assume M1 and M2 are identical but 6= 0.67 VCC I REF AE AE AE I copy AE 3A E 2A E VCC I REF 5A E 9A E I copy (a) (b) Figure 9. 9.70 51.35 mA. 2006] June 30.69 VDD I REF M1 W L RP M REF I1 W L Figure 9. Repeat Example 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.71. Calculate Icopy in each of the circuits shown in Fig.68 VDD I REF M1 W L M REF I1 W L RP Figure 9. 9.cls v. Consider the MOS current mirror shown in Fig. 9. Assume all of the transistors operate in saturation. 52. 2007 at 13:42 459 (1) Sec. 53. (a) How should VDS 1 be chosen so that Icopy1 is exactly equal to IREF ? .21 if the reference current is 0.3 Chapter Summary VCC I REF Q1 nA E Q REF Q2 I2 kAE I copy1 mA E 459 Figure 9.

cls v. 2006] June 30. 55. VA. respectively.p = .71 (b) Determine the error in Icopy1 with respect to IREF if VDS 1 is equal to VGS . where the subscripts n and p refer to n-type (npn or NMOS) and p-type (pnp or PMOS) devices.72(b) ( 0:5 V). (b) Calculate the required value of Vb2 .73 bias current of 0. VTH (so that M1 resides at the edge of saturation). 9. (a) Determine W=L1 = W=L2 if = 0:1 V. We wish to design the MOS cascode of Fig. Design Problems In the following problems.72(a) such that RE sustains a voltage approximately equal to the minimum required collector-emitter R out Vb Q1 RE V b1 V b2 Q1 Q2 (b) R out (a) Figure 9.72 voltage of Q2 in Fig.0:5 V. design the degenerated current source of Fig.16 A. Assuming a bias current of 1 mA. Select Vb1 such that Q2 experiences a base-collector forward bias of only 100 mV.n = VA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. nCox = 100 A/V2 . Design the cascode current source of Fig. n = 100.p = 6 10. p = 50. 56.n = 0:4 V. and VTH.n = IS. Compare the output impedances of the two circuits.5 mA. VTH. . 54. 9.73 for an output impedance of 200 k and a R out V b1 V b2 M1 M2 Figure 9. 9.72(b) for an output impedance of 50 k .1 . 2007 at 13:42 460 (1) 460 VDD I REF 3 (W( L n 5 (W( L p 2 (W( L n Chap.p = 5 V. unless otherwise stated. 9. Assume a bias current of 1 mA. p Cox = 50 A/V2 . 9 VDD W 3( ( L p I copy I REF Cascode Stages and Current Mirrors ( W (p L 5 (W( L n 2 (W( L p ( W (n L M REF I copy W 3( ( L n M REF (a) (b) Figure 9. assume IS.

For simplicity.76 budget of 2 mW with VDD = 1:8 V.76 for a voltage gain of 200 and a power VDD V b3 V b2 V b1 V in M4 M3 Vout M2 M1 Vb2 such that Q1 and Q4 sustain a base-collector forward bias of 200 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.75 is achieved? 59.77 must deliver I1 = 0:5 mA to a circuit with a total power budget of 2 mW.5 mA. 9. The bipolar cascode ampliﬁer of Fig.cls v.3 Chapter Summary 461 57. 9.1 . assume Vb1 = Vb2 = 0:9 V. Determine the required dc levels of Vin and Vb3 . Use VCC I1 Vout V b1 V in Q2 Q1 Figure 9. 9. The current mirror shown in Fig. 2006] June 30. 60.53) and assume = 100. Select Vb1 and VCC = 2. Design the cascode ampliﬁer shown in Fig. What voltage gain Figure 9. . (c) Compute the value of Vb1 such that Q1 sustains a collector-emitter voltage of 500 mV. (9. 58. 9.75 for a power budget of 2 mW.74 must be designed for a voltage gain of 500. calculate the required bias component in Vin .5 V V b3 V b2 Q4 Q3 Vout V b1 V in Q2 Q1 Figure 9. Design the CMOS cascode ampliﬁer of Fig. (a) What is the minimum required value of VA ? (b) For a bias current of 0. 9. Assume W=L1 = = W=L4 = 20=0:18 and p = 2n = 0:2 V.74 Eq. Assuming VA = 1 and 1. 2007 at 13:42 461 (1) Sec. determine the required value of IREF and the relative sizes of QREF and Q1 .

81 must be designed for a voltage gain of 20 and a power budget of 2 mW.cls v. Q2 operates as a common-base stage. Is the solution unique? Figure 9.77 61. The common-source stage depicted in Fig. Design the circuit of Fig.78. 9. 67.1 . a voltage gain of 20.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.78 budget of 3 mW and an output impedance of 50 . 9. In the circuit of Fig.34 such that the bias current of Q2 is 1 mA and the error in IC 1 with respect to its nominal value is less than 2. Assume VA = 1 and 1. 66. 9. design the circuit. Q2 operates as an emitter follower. Design the circuit for an VCC = 2. 9. Design the circuit of Fig. Assume VA = 1 and 1. 64. 62.5 V Circuit I REF I1 Q REF Q1 Figure 9.1 .5 V RC Vout I REF V in Q REF Q1 Q2 Vb Figure 9. and p = 0:2 V. output impedance of 500 .79. design the circuit. 2006] June 30. In the circuit of Fig. and a power budget of 3 mW.30 for Icopy = 0:5 mA and an error of less than 1 with respect to the nominal value. Explain the trade-off between accuracy and power dissipation in this circuit. 9 Cascode Stages and Current Mirrors VCC = 2. n = 0:1 V. Assume VCC = 2:5 V. and p = 0:2 V.1 . Assuming W=L1 = 20=0:18. Design the circuit for a power budget of 3 mW. 65. 9. Assuming W=L2 = 10=0:18.85 and an output impedance of 100 .1 . The source follower of Fig. 9.5 V V in I REF Q REF Q1 Q2 Vout Figure 9. Design the circuit for a power VCC = 2.82 must achieve a voltage gain of 0. n = 0:1 V. .79 63.80 shows an arrangement where M1 and M2 serve as current sources for circuits 1 and 2. 2007 at 13:42 462 (1) 462 Chap.

2006] June 30. 9.3 Chapter Summary 463 VDD = 1.8 V M REF M2 I REF V in M1 Figure 9.82 68.81 VDD = 1. n = 0:1 V.8 V M4 M3 Vout M1 I REF M REF M5 V in M2 Vb Figure 9. and a power budget of 13 mW. For simplicity.) SPICE Problems . 2007 at 13:42 463 (1) Sec.83 a high voltage gain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.80 VDD = 1. Assuming W=L3 = 40=0:18. The common-gate stage of Fig. and p = 0:2 V.8 V Circuit 1 Circuit 2 1 mA I REF 0. neglect channel-length modulation in M1 .83 employs the current source M3 as the load to achieve VDD = 1.1 . an input impedance of 50 .5 mA M REF M1 M2 Figure 9. design the circuit for a voltage gain of 20. (You may not need all of the power budget.cls v.8 V I REF M REF V in M1 Vout M2 Figure 9.1 . 9.

69. npn = 100.84 (a) Tying the collector of Q2 to VCC . select the value of RP so as to minimize the error between I1 and IREF . .npn = 5 10. Fig. Vb = 0:9 V.86 (a) Select the value of Vb so that Iout is precisely equal to 0. 9. 2007 at 13:42 464 (1) 464 Chap. (b) Determine the change in Iout if Vb varies by 100 mV.5 mA Vb M3 M2 M1 Figure 9. In the circuit of Fig. determine the output impedance of the cascode and compare the results.5 mA. IS. Explain the cause of this change. (c) Using both hand analysis and SPICE simulations.87. M1 -M2 .5 V I REF Q REF RP 1 mA I1 Q1 Figure 9. VDD = 1.85 71.cls v. (a) Plot the input/output characteristic and determine the value of Vin at which the slope (small-signal gain) reaches a maximum. we wish to suppress the error due to the base currents by means of resistor RP .85.16 A. Assume W=L1. (b) What is the change in the error if the of both transistors varies by 3? (c) What is the change in the error if RP changes by 10? 70. 2006] June 30. 9. and I1 = 1 mA is an ideal current source. VA. 9.pnp = 8 10.8 V I out 0. use the MOS device models given in Appendix A.16 A.86 depicts a cascode current source whose value is deﬁned by the mirror arrangement. 72. pnp = 50. 9 Cascode Stages and Current Mirrors In the following problems. Assume W=L = 5 m=0:18 m for M1 -M3 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.npn = 5 V. Repeat Problem 69 for the circuit shown in Fig. VCC = 2. VA. Figure 9.pnp = 3:5 V. For bipolar transistors. assume IS.2 = 10 m=0:18 mum.5 V I REF Q REF 1 mA I1 Q1 RP Figure 9.84. We wish to study the problem of biasing in a high-gain cascode stage. Which circuit exhibits less sensitivity to variations in and RP ? VCC = 2.

suppose the biasing circuitry that must produce the above dc value for Vin incurs an error of 20 mV. VDD = 1.cls v. Razavi. From (a). 2001.88.8 V M5 1 mA M4 M3 Vb M2 Vout V in M1 Figure 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.87 (b) Now. assuming W=L = 10 m=0:18 m for all of the transistors. 2007 at 13:42 465 (1) References VDD = 1. Repeat Problem 72 for the cascode shown in Fig. 9. B. . Design of Analog CMOS Integrated Circuits McGraw-Hill.8 V I1 Vout Vb V in M2 M1 465 Figure 9. 73.88 References 1. 2006] June 30. explain what happens to the small-signal gain.

cls v. upon applying the result to a speaker. (10. we can identify two components: (1) the ampliﬁed version of the microphone signal and (2) the ripple waveform present on VCC . differential circuits have found increasingly wider usage in microelectronics and serve as a robust.. we can write Vout = VCC . For the latter.1(c) depicts the overall output in the presence of both the signal and the ripple. let us ﬁrst consider an example. an electrical engineering student constructs the circuit shown in Fig. a steady low-frequency component. 2007 at 13:42 466 (1) 10 Differential Ampliﬁers The elegant concept of “differential” signals and ampliﬁers was invented in the 1940s and ﬁrst utilized in vacuum-tube circuits. high-performance design paradigm in many of today’s systems. Illustrated in Fig. 10.1(a) to amplify the signal produced by a microphone. Since then. RC IC . The concepts are outlined below.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Examining the output of the commonemitter stage. The “hum” originates from the ripple. i. Unfortunately.1(b)]. Explain what happens.1 Having learned the design of rectiﬁers and basic ampliﬁer stages. 2006] June 30.1(d). 10. this phenomenon is summarized as the “supply 466 . Solution Recall from Chapter 3 that the current drawn from the rectiﬁed output creates a ripple waveform at twice the ac line frequency (50 or 60 Hz) [Fig.1) noting that Vout simply “tracks” VCC and hence contains the ripple in its entirety.1 Initial Thoughts In order to understand the need for differential circuits. the student observes that the ampliﬁer output contains a strong “humming” noise.1 General Considerations 10. Example 10. 10. This chapter describes bipolar and MOS differential ampliﬁers and formulates their large-signal and small-signal properties. General Considerations Differential Signals Differential Pair Bipolar Differential pair Qualitative Analysis Large−Signal Analysis Small−Signal Analysis MOS Differential pair Qualitative Analysis Large−Signal Analysis Small−Signal Analysis Other Concepts Cascode Pair Common−Mode Rejection Pair with Active Load 10.e.1. Figure 10.

we express the small-signal voltages at these nodes as vX = Av vin + vr vY = vr : That is. the above conjecture can be readily implemented. In fact.1 (a) CE stage powered by a rectiﬁer. denoting the ripple by vr . Alternatively. vY = Av vin : Note that Q2 carries no signal. How is that possible? Equation (10.2) (10.) Exercise What is the hum frequency for a full-wave rectiﬁer or a half-wave rectiﬁer? How should we suppress the hum in the above example? We can increase C1 .4) . (10. Figure 10. 2007 at 13:42 467 (1) Sec. 2006] June 30.3) vX . (d) ripple and signal paths to output.2(a) illustrates the core concept. (10. what if Vout is measured with respect to another point that itself experiences the supply ripple to the same extent? It is thus possible to eliminate the ripple from the “net” output. but the required capacitor value may become prohibitively large if many circuits draw current from the rectiﬁer. and the output is now measured between nodes X and Y rather than from X to ground. thus lowering the ripple amplitude. The CE stage is duplicated on the right. noise goes to the output with a gain of unity. What happens if VCC contains ripple? Both VX and VY rise and fall by the same amount and hence the difference between VX and VY remains free from the ripple. we can modify the ampliﬁer topology such that the output is insensitive to VCC . fundamentally because both Vout and VCC are measured with respect to ground and differ by RC IC . While rather abstract. (b) ripple on supply voltage. (c) effect at output.cls v. simply serving as a constant current source.1) implies that a change in VCC directly appears in Vout . But what if Vout is not “referenced” to ground?! More speciﬁcally. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 General Considerations VCC 110 V 60 Hz To Bias 467 RC Vout Q1 C1 (a) VCC Voice Signal Ripple VCC Vout Signal t (b) (c) t (d) Figure 10.” (A MOS implementation would suffer from the same problem.

2(a) and recall that the duplicate stage consisting of Q2 and RC 2 remains “idle. (c) generation of differential phases from one signal. canceling each other as they appear in vX . 10 Differential Ampliﬁers VCC Ripple Ripple VCC R C1 X Q1 Y Q2 R C2 A1 R C1 To Bias R C2 X Q1 Vout To Bias Y Q2 v in (a) (b) Figure 10.5) (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Use of two CE stages to remove effect of ripple. we can invert one of the input . 2006] June 30. 10. 2007 at 13:42 468 (1) 468 Chap.” thereby “wasting” current. vY : vX = Av vin + vr vY = Av vin + vr vX . vY = 0: Vr VCC R C1 To Bias (10.3(a)].2 Differential Signals Let us return to the circuit of Fig.6) (10. (b) use of differential input signals.3 (a) Application of one input signal to two CE stages. Unfortunately.1. the signal components at X and Y are in phase. 10.cls v. The above development serves as the foundation for differential ampliﬁers: the symmetric CE stages provide two output nodes whose voltage difference remains free from the supply ripple.7) VCC R C1 X Y Q2 − v in R C2 To Bias R C2 X Q1 V in (a) Y Q2 + v in Q1 (b) (c) Figure 10. We may therefore wonder if this stage can provide signal ampliﬁcation in addition to establishing a reference point for Vout . In our ﬁrst attempt. we directly apply the input signal to the base of Q2 [Fig. For the signal components to enhance each other at the output. 10.

2006] June 30. 2007 at 13:42 469 (1) Sec.8) (10. 10. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.11) (10. obtaining vX = Av vin + vr vY = . (b) differential signals.vin can be generated.1 General Considerations 469 phases as shown in Fig.3(b): the circuit senses two inputs that vary by equal and opposite amounts and generates two outputs that behave in a similar fashion.4(a)] and “carried by one line.12) . 10. These waveforms are examples of “differential” signals and stand in contrast to “single-ended” signals—the type to which we are accustomed from basic circuits and previous chapters of this book. V1 and V2 vary by equal and opposite amounts and have the same average (dc) level.3(b). 10. Our thought process has led us to the speciﬁc waveforms in Fig. a simple approach is to utilize a transformer to convert the microphone signal to two components bearing a phase difference of 180 .2(a). vY = 2Av vin : (10. this topology provides twice the output swing by exploiting the ampliﬁcation capability of the duplicate stage. VCM . a single-ended signal is one measured with respect to the common ground [Fig.9) vX . 10.” whereas a differential signal is measured between two nodes that have equal and opposite swings [Fig. The reader may wonder how . Illustrated in Fig.4 (a) Single-ended signals.4(b)] and is thus “carried by two lines. with respect to ground: V1 = V0 sin !t + VCM V2 = . (c) illustration of common-mode level.V0 sin !t + VCM (10.cls v. Here.” VCC Vin Vout Q1 (a) VCC Q1 Q2 Output Differential Signal V1 VCM V2 t (c) 2V0 Input Differential Signal (b) Figure 10. Figure 10.Av vin + vr and hence (10.10) Compared to the circuit of Fig.3(c). 10. More speciﬁcally. 10.4(c) summarizes the foregoing development.

cls v. For example. v in1 v in1 2V +2 V Example 10. how about the common-mode level? What is the signiﬁcance of VCM = VCC . where RC = RC 1 = RC 2 and IC denotes the bias current of Q1 and Q2 .3 Determine the common-mode level at the output of the circuit shown in Fig. VCM . Interestingly. How can the transformer of Fig. RC IC in the above example? Why is it interesting that the ripple appears in VCM but not in the differential output? We will answer these important questions in the following sections.3(c).2 Solution v in2 v in2 t Figure 10. 2006] June 30.3(b). But. RC IC . We may also say V1 and V2 are differential signals to emphasize that they vary by equal and opposite amounts around a ﬁxed level. 10. 10.” That is. 10. in the absence of differential signals. what is the output CM level? Exercise Our observations regarding supply ripple and the use of the “duplicate stage” provide sufﬁcient justiﬁcation for studying differential signals.5). In the absence of signals. Solution If a resistor of value R1 is inserted between VCC and the top terminals of RC 1 and RC 2 .3(c) produce an output CM level equal to +2 V. 10 Differential Ampliﬁers Since each of V1 and V2 has a peak-to-peak swing of 2V0 . 10.4(c)] is called the “commonmode (CM) level. 2007 at 13:42 470 (1) 470 Chap. +vin and . in the transformer of Fig. we say the “differential swing” is 4V0 . The center tap can simply be tied to a voltage equal to +2 V (Fig. the ripple affects VCM but not the differential output.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 Exercise Does the CM level change if the inputs of the ampliﬁer draw a bias current? Example 10. The dc voltage that is common to both V1 and V2 [VCM in Fig. 10. VX = VY = VCC . RC IC (with respect to ground). Thus. .vin display a CM level of zero because the center tap of the transformer is grounded. the two nodes remain at a potential equal to VCM with respect to the global ground. VCM = VCC .

2. a simple modiﬁcation yields an elegant. Recall from Section 10.4(b) suffers from some drawbacks.7. 2007 at 13:42 471 (1) Sec. 10.1 Qualitative Analysis It is instructive to ﬁrst examine the bias conditions of the circuit. 10. Illustrated in Fig. 10. VCC RC X V in1 Q1 Q2 RC Y Vin2 V in1 RD X M1 M2 I SS VDD RD Y Vin2 I EE (a) (b) Figure 10.cls v.” Thus.13) (10. intuitive analysis and subsequently formulate the large-signal and small-signal behavior. VBE1 = VBE2 IC 1 = IC 2 = IEE . 10. 10.6 (a) Bipolar and (b) MOS differential pairs.3 Differential Pair Before formally introducing the differential pair. In both cases. While sensing and producing differential signals. we must recognize that the circuit of Fig.2 that in the absence of signals.6(a).15) .e. i.2 Bipolar Differential Pair 471 10. We say the circuit is in “equilibrium. with the two inputs tied to VCM to indicate no signal exists at the input. By virtue of symmetry.” (10. 2006] June 30. the sum of the transistor currents is equal to the tail current. Our objective is to analyze the large-signal and small-signal behavior of these circuits and demonstrate their advantages over the “single-ended” stages studied in previous chapters. 10. we begin with a qualitative.14) where the collector and emitter currents are assumed equal. versatile topology. 10. 10. We call IEE the “tail current source. 2 VX = VY = VCC . the (bipolar) “differential pair”1 is similar to the circuit of Fig. 10.2 Bipolar Differential Pair 10. differential nodes reside at the common-mode level. the voltage drop across each load resistor is equal to RC IEE =2 and hence (10. We also assume each circuit is perfectly symmetric. Fortunately.4(b). the transistors are identical and so are the resistors. RC IEE : 2 1 Also called the “emitter-coupled pair” or the “long-tailed pair.6(b).” The MOS counterpart is shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.. except that the emitters of Q1 and Q2 are tied to a constant current source rather than to ground.4(b) senses two inputs and can therefore serve as A1 in Fig. For each differential pair.1.1. This observation leads to the differential pair. We therefore draw the pair as shown in Fig. the circuit of Fig.2(b).

5 V. (10. VCC .4(b).16 gives VCC . does not.15) remain unchanged. 10.13)-(10. 2007 at 13:42 472 (1) 472 Chap.18) What value of RC allows the input CM level to approach VCC is the transistors can tolerate a base-collector forward bias of 400 mV? Exercise Now. 2006] June 30. if the two input voltages are equal. . In other words. How Solution Equation 10.17) (10.16) Example 10. RC IEE VCM . Interestingly. 10 VCC R C1 X Q1 V CM I EE R C1 = R C2 = R C Q2 R C2 Y Differential Ampliﬁers Figure 10.4 A bipolar differential pair employs a load resistance of 1 k close to VCC can VCM be chosen? and a tail current of 1 mA.7 by a small amount and determine the circuit’s response. Figure 10. In the latter.7 Response of differential pair to input CM change. VX . The circuit also “rejects” the effect of supply ripple: if VCC experiences a change. thereby suggesting that neither the collector current nor the collector voltage of the transistors is affected. VCM must remain below VCC by at least 0. so are the two outputs. VCM RC IEE 2 0:5 V: That is. 10. The reader may recognize that it is the tail current source in the differential pair that guarantees constant collector currents and hence rejection of the input CM level. 2 (10.cls v. or the circuit “rejects” input CM variations. let us vary VCM in Fig. VY . so do their collector currents and voltages (why?). The “common-mode rejection” capability of the differential pair distinctly sets it apart from our original circuit in Fig.8 summarizes these results. (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the differential output. We say a zero differential input produces a zero differential output. if the base voltage of Q1 and Q2 changes. the collector voltages must not fall below the base voltages: revealing that VCM cannot be arbitrarily high. Eqs. We say the circuit does not respond to changes in the input common-mode level. Are Q1 and Q2 in the active region? To avoid saturation.

a typical transistor carries an enormous current. In fact. and since IC 1 cannot exceed IEE .8 Effect of VCM 1 and VCM 2 at output.5 V RC Vout RC Y Q2 Q1 P I EE Vin2 = +2 V RC Vout Y Vin2 = +1 V V in1 = +1 V X Figure 10. we now turn to the more interesting case of differential response. However.e. That is.9(a). i. such input signals provide a simple. 0:2 V = 1:8 V!! Since with VBE = 1:8 V. 2007 at 13:42 473 (1) Sec. then its base-emitter voltage must reach a typical value of.22) But. While not exactly differential.21) (10. where the two transistors are drawn with a vertical offset to emphasize that Q1 senses a more positive base voltage. With its base held at +1 V. and hence (10. intuitive starting point. If Q2 carries an appreciable current. thereby turning Q2 off. 10. VY VCM1 VCM2 Figure 10. 10.9 Response of bipolar differential pair to (a) large positive input difference and (b) large negative input difference. ensuring that Q2 remains off. IC 1 = IEE IC 2 = 0. with a typical base-emitter voltage of 0. 0.8 V. We hold one input constant. Q1 holds node P at approximately +1:2 V. .cls v. 2006] June 30.19) (10. how can we prove that Q1 indeed absorbs all of IEE ? Let us assume that it is not so..20) VX = VCC .8 V. VP = +2 V . Since the difference between the base voltages of Q1 and Q2 is so large. VCC = 2. we postulate that Q1 “hogs” all of the tail current.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the device therefore requires an emitter voltage of VP 0:2 V.5 V RC X V in1 = +2 V Q1 Q2 P I EE (a) (b) VCC = 2. we conclude that the conditions VBE1 = 1:8 V and VP 0:2 V cannot occur. With our treatment of the common-mode response. RC IEE VY = VCC : (10. Recall that IC 1 + IC 2 = IEE . IC 1 IEE and IC 2 6= 0. Consider the circuit shown in Fig. vary the other.2 Bipolar Differential Pair VCC R C I EE Upper Limit of VCM to Avoid Saturation 2 473 VX . and examine the currents ﬂowing in the two transistors. this means that Q1 sustains a base-emitter voltage of Vin1 . say.

15). Since VX and VY are differential. Vin2 j becomes sufﬁciently large. What is the maximum allowable base voltage if the differential input is large enough to completely steer the tail current? Assume VCC = 2:5 V. Solution . If IEE is completely steered. Thus.9(b)]. Q2 Q1 Q1 Q2 Q1 Q2 I EE VCC I EE VCC − R C 2 VCC − R C I EE 0 (b) I C2 I C1 0 (a) I EE 2 VX VY V in1 − V in2 V in1 − V in2 Figure 10. based on Eqs. we can sketch the collector currents of Q1 and Q2 as a function of the input difference [Fig. we can deﬁne a common-mode level for them. 10.23) (10.26) The above experiments reveal that. we can sketch the input/output characteristics of the circuit as shown in Fig.19). In fact. (10.5 mA and a collector resistance of 1 k . 10 Differential Ampliﬁers Symmetry of the circuit implies that swapping the base voltages of situation [Fig. the transistor carrying the current lowers its collector voltage to VCC . Vin2 . RC IEE =2. this quantity is called the “output CM level. That is. 2006] June 30. and (10. From Eqs.24) IC 2 = IEE IC 1 = 0. We have not yet formulated these characteristics but we do observe that the collector current of each transistor goes from 0 to IEE if jVin1 .14). (10. (10.10 Variation of (a) collector currents and (b) output voltages as a function of input. Given by VCC . and (10. (10. giving Q1 and Q2 reverses the (10. a nonzero differential input yields a nonzero differential output— a behavior in sharp contrast to the CM response.21). and hence VY = VCC .10(b).” Example 10. RC IEE = 2 V. the differential pair “steers” the tail current from one transistor to the other. 10.10(a)].5 A bipolar differential pair employs a tail current of 0.25).23).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. RC IEE VX = VCC : (10. It is also important to note that VX and VY vary differentially in response to Vin1 . 2007 at 13:42 474 (1) 474 Chap. 10.25) (10. the base voltage must remain below this value so as to avoid saturation. as the difference between the two inputs departs from zero.

27) and (10.11 (a) Differential pair sensing small. differential input changes. Vin2 = 0 (the equilibrium condition) and study the circuit’s behavior for a small input difference.IC 2 . however.28) How is I related to V ? If the emitters of Q1 and Q2 were directly tied to ground. (b) hypothetical change at P . In the last step of our qualitative analysis. 2006] June 30. I: I = C2 (10. We must therefore compute the change in VP . VP rises by VP . . IC 2 decreases by the same amount: VCC RC + ∆V RC Y Q1 P I EE (a) (b) + ∆V X Q2 X Q1 P Q2 Y VCM − ∆V VCM VCM − ∆V VCM ∆VP I EE Figure 10.cls v.2 Bipolar Differential Pair 475 Exercise Repeat the above example if the tail current is raised to 1 mA. We surmise that IC 1 increases slightly and. the tail voltage remains constant if the two inputs vary differentially and by a small amount—an observation critical to the small-signal analysis of the circuit. 10.31) VP = 0: (10. 10. we “zoom in” around Vin1 . Suppose. the base voltage of Q1 is raised from VCM by V while that of Q2 is lowered from VCM by the same amount.32) Interestingly. dictating that gm V . As a result.29) + VP . As illustrated in Fig.11(b). the net increase in VBE 1 is equal to V . yielding (10. 10.gmV + VP : But recall from (10. as shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VP : Similarly. since IC 1 + IC 2 = IEE . node P is free to rise or fall. VP = gm V + VP and hence (10. VP and hence 2 IC 1 = gm V .11(a).28) that IC 1 must be equal to . 2007 at 13:42 475 (1) Sec.27) (10. the net decrease in VBE 2 is equal to V (10. In the differential pair. IC 1 = IEE + I 2 IEE . then I would simply be equal to gm V .30) IC 2 = .

2007 at 13:42 476 (1) 476 Chap.31). 10 Differential Ampliﬁers The reader may wonder why (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 . thus exhibiting unequal transconductances and prohibiting the omission of gm ’s from the two sides of (10.5 mA. . With VCC = 2 V.38) (10.32) does not hold if V is large. the power budget translates to a tail current of 0.40) (Note that the change in the differential input is equal to 2V .35) (10.36) VX .33) (10.gmRC : (10.30) respectively as IC 1 = gm V IC 2 = .42) = 1040 : Exercise Redesign the circuit for a power budget of 0.34) VX = .5 mW and compare the results. It follows that Solution RC = jAV j g m (10. Example 10. With VP = 0 in Fig.37) Av = Change in Di erential Output Change in Di erential Input .gmV RC VY = gmV RC : The differential output therefore goes from 0 to (10. VY = . 2006] June 30.2gmV RC : We deﬁne the small-signal differential gain of the circuit as (10.29) and (10. 10.41) (10. Q1 and Q2 carry signiﬁcantly different currents.25 mA near equilibrium.2gmV RC = 2V = . Each transistor thus carries a current of 0.6 Design a bipolar differential pair for a gain of 10 and a power budget of 1 mW with a supply voltage of 2 V. Which one of the above equations is violated? For a large differential input. providing a transconductance of 0:25 mA=26 mV = 104 .) This expression is similar to that of the common-emitter stage.gmV and (10.11(a). we can rewrite (10.39) (10.cls v.

Exercise If both circuits are designed for the same power budget.43) jAV.2 denotes the transconductance of each of the two transistors. (10. 10. In other words.49) .46) where IEE =2 is the bias current of each transistor in the differential pair. 10.di j = gm1. IEE = 2IC . In order to derive the relationship between the differential input and output of the circuit.47) indicating that the differential pair consumes twice as much power.40) as jAV. Our interest arises from (a) the need to understand the circuit’s limitations in serving as a linear ampliﬁer.10).12 that Vout1 = VCC . collector resistances. (10. Solution The gain of the differential pair is written from (10.2 Large-Signal Analysis Having obtained insight into the operation of the bipolar differential pair. compare their voltage gains. and supply voltages. 10. the reader may naturally wonder why we are suddenly interested in this aspect of the differential pair. and IC represents the bias current of the CE stage.45) IEE = IC . This is one of the drawbacks of differential circuits.44) gm1. we now quantify its large-signal behavior.CE j = gmRC : Thus. For a CE stage (10. equal collector resistances.48) (10.2.2 RC . 2VT VT (10. 2006] June 30.7 Compare the power dissipation of a bipolar differential pair with that of a CE stage if both circuits are designed for equal voltage gains.2 Bipolar Differential Pair 477 Example 10. RC IC 2 (10. aiming to formulate the input/output characteristic of the circuit (the sketches in Fig.2 RC = gm RC and hence (10. 2007 at 13:42 477 (1) Sec. RC IC 1 Vout2 = VCC . and (b) the application of the differential pair as a (nonlinear) current-steering circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. where gm1.cls v. we ﬁrst note from Fig. and equal supply voltages. 10. Not having seen any large-signal analysis in the previous chapters.

55) IC 1 + IC 2 = IEE : (10. IC 2 exp Vin1 V Vin2 + IC 2 = IEE T and.12 Bipolar differential pair for large-signal analysis. 2007 at 13:42 478 (1) 478 Chap.54) (10. Assuming = 1 and VA = 1.55) in (10.53) (10.57) IEE (10.RC IC 1 . 10 Differential Ampliﬁers VCC RC V out1 V in1 Q1 P I EE Vout Q2 RC Vout2 Vin2 Figure 10.50) (10. Vin2 = VBE1 .58) but with the roles of Vin1 and Vin2 IC 2 = .56) contain two unknowns.55) and (10.58) . VT ln IC 2 IS1 IS2 IC 1 : = VT ln I C2 Also. IC 2 : (10. we write a KVL around the input network. Vout2 = . Vin1 .56) yields . Substituting for IC 1 from (10. (10.51) We must therefore compute IC 1 and IC 2 in terms of the input difference. and hence Vout = Vout1 . and recalling from Chapter 4 that VBE = VT lnIC =IS . VBE2 = VT ln IC 1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. a KCL at node P gives (10. 2006] June 30. VBE2 .56) Equations (10.52) Vin1 . obtaining (10. therefore.cls v. : 1 + exp Vin1 V Vin2 T The symmetry of the circuit with respect to Vin1 and Vin2 and with respect to IC 1 and IC 2 suggests that IC 1 exhibits the same behavior as (10. VBE1 = VP = Vin2 .

10VT ? Since exp.56) to obtain IC 1 . 2006] June 30. 10. 10.62) .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vin2 : 1 + exp VT Alternatively. can we say IC 1 0 and IC 2 (10.66) 4:54 10. Vin2 = . and IEE can be considered steered completely to Q2 . Vin2 is very negative.60) IC 1 ! 0 IC 2 ! IEE . expVin1 . Determine the differential input voltage that steers 98 of the tail current to one transistor. Q1 carries only 0:0045 of the tail current. if Vin1 . the reader can substitute for IC 2 from (10.5 . . IEE exp Vin1 V Vin2 T (10.69) (10. 4:54 10.2 Bipolar Differential Pair 479 exchanged: Equations (10. Vin2 =VT ! 1 and as predicted by our qualitative analysis [Fig.64) IC 1 ! IEE IC 2 ! 0: IEE if Vin1 .58) in (10.58) and (10.5: In other words.8 Solution We require that IC 1 = 0:02IEE . Vin2 IEE exp V T = Vin1 . Vin2 is very positive.59) (10.10 4:54 10. IC 1 = (10.67) (10.5 (10.61) (10. In particular.9(b)].70) . if Vin1 (10. Similarly.60) play a crucial role in our quantitative understanding of the differential pair’s operation.65) (10.68) IEE 1 .5IEE and IEE IC 2 1 + 4:54 10.cls v.63) (10. Vin2 =VT ! 0 and IEE . Example 10. IC 1 IEE :4:54 105 1 + 4 54 10. 2007 at 13:42 479 (1) Sec. then expVin1 . (10. 1 + exp Vin2 V Vin1 T Vin1 .5 What is meant by “very” negative or positive? For example.

IC 2 . From Example 10. indicating that the differential output voltage begins from a “saturated” value of +RC IEE for a very negative differential input. Vin2 : = . Exercise What differential input is necessary to steer 90% of the tail current? For the output voltages in Fig.14(b) and (c). 2007 at 13:42 480 (1) 480 Chap.74) (10.9 Sketch the output waveforms of the bipolar differential pair in Fig.77) (10.RC IC 1 . we recognize that even a differential input of 4VT 104 mV “switches” the differential pair. Vin2 j.3:91VT : (10. RC IEE . and reaches a saturated level of . 10. IEE exp Vin1 V Vin2 T = VCC .72) (10. gradually becomes a linear function of Vin1 . RC IC 1 . Vin2 becomes very positive. 10 Differential Ampliﬁers and hence Vin1 .75) Of particular importance is the output differential voltage: Vout1 . Vout2 = . we have Vout1 = VCC . Vin2 1 + exp VT and (10.73) Vout2 = VCC . Solution For the sinusoids depicted in Fig. Vin2 for relatively small values of jVin1 .71) We often say a differential input of 4VT is sufﬁcient to turn one side of the bipolar pair nearly off.RC IEE tanh 2V T (10. Vin2 j must remain well below this value for linear operation. exp Vin1 V Vin2 T = RC IEE Vin1 .cls v. 1 .14(a) in response to the sinusoidal inputs shown in Figs. the circuit operates linearly because the maximum .RC IEE as Vin1 . RC IC 2 = VCC . Vin2 1 + exp VT Vin1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8. Assume Q1 and Q2 remain in the forward active region.14(b).12. Vin2 . : 1 + exp Vin1 V Vin2 T (10. RC Vin1 . Example 10. 10. 10.13 summarizes the results. 2006] June 30. thereby concluding that jVin1 .76) (10.78) Figure 10. 10. Note that this value remains independent of IEE and IS .

thus producing Vout1 VCC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.14 differential input is equal to 2 mV.2 Bipolar Differential Pair 481 I EE I C2 I C1 0 I EE 2 V in1 − V in2 VCC I EE VCC − R C 2 VCC − R C I EE V out1 V out2 0 V in1 − V in2 + R C I EE V out1 − V out2 0 V in1 − V in2 − R C I EE Figure 10.14(d)]. For example. Vin1 VCC RC V out1 V in1 Q1 P I EE Vout2 (a) Vin1 VCM Vin2 Vin2 t (b) 1 mV 100 mV RC Vout2 Q2 Vin2 VCM t1 (c) t Vout2 1 mV x g m R C VCC VCC − R C I EE 2 VCM Vout1 Vout1 t (d) VCC − R C I EE t t1 (e) Figure 10.14(c) force a maximum input difference of 200 mV. the sinusoids in Fig.79) (10. The outputs are therefore sinusoids having a peak amplitude of 1 mV gm RC [Fig. turning Q1 or Q2 off. 10. Q1 absorbs most of the tail current.13 Variation of currents and voltages as a function of input. 10. 10. as Vin1 approaches 50 mV above VCM and Vin2 reaches 50 mV below VCM (at t = t1 ).80) . On the other hand. 2007 at 13:42 481 (1) Sec. 2006] June 30. RC IEE Vout2 VCC : (10.

15(a).15(a) to two “half circuits” [Fig.cls v. Vin2 j falls to less than 100 mV. 2007 at 13:42 482 (1) 482 Chap.85) (10.11 revealed that. As explained in previous chapters.v2 and since vin1 (10. we construct the small-signal model of the circuit as shown in Fig. The virtual-ground nature of node P for differential small-signal inputs simpliﬁes the analysis considerably.vin2 for differential operation.gmRC vin1 (10. Here.87) .3 Small-Signal Analysis Our brief investigation of the differential pair in Fig. an ideal tail current source.82) (10. We say the circuit operates as a “limiter” in this case. We now study the small-signal behavior of the circuit in greater detail.81) (10. and VA = 1. 10. we can write vout1 = . the tail node maintains a constant voltage (and hence is called a “virtual ground”).2. Exercise What happens to the above results if the tail current is halved? 10.83) = . this node can be shorted to ac ground. In Problem 28. v2 v1 + g v + v2 + g v = 0: r1 m1 1 r2 m2 2 With r1 = r2 and gm1 = gm2 . reducing the differential pair of Fig.81) translates to 2vin1 = 2v1 : (10. Assuming perfect symmetry. The result is sketched in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. v1 = vP = vin2 .86) Thus. 10. but the requirement is that the input signals not inﬂuence the bias currents of Q1 and Q2 appreciably. 10. playing a role similar to the diode limiters studied in Chapter 3. for small differential inputs.84) That is. an input difference of less than 10 mV is considered “small” for most applications. Since vP = 0. 10. 10 Differential Ampliﬁers Thereafter. the outputs remain saturated until jVin1 .14(e). the deﬁnition of “small signals” is somewhat arbitrary. we prove that this property holds in the presence of Early effect as well. As with the foregoing large-signal analysis. (10. We also obtained a voltage gain equal to gm RC . In practice. With each half resembling a commonemitter stage. In other words. the small-signal model conﬁrms the prediction made by (10. let us write a KVL around the input network and a KCL at node P : vin1 . vin1 and vin2 represent small changes in each input and must satisfy vin1 = . the two transistors must exhibit approximately equal transconductances—the same condition required for node P to appear as virtual ground. (10.15(b)]. 2006] June 30. Note that the tail current source is replaced with an open circuit.32). v1 = 0: (10.82) yields v1 = . 10. vP = vin1 .vin2 .

the Early effect in Q1 and Q2 cannot be neglected.2 Bipolar Differential Pair 483 RC v in1 r π1 vπ 1 g m1 RC vπ 1 P (a) g m2 vπ 2 vπ 2 r π2 v in2 RC v in1 r π1 vπ 1 g m1 RC vπ 1 g m2 vπ 2 vπ 2 r π2 v in2 (b) VCC RC RC V in1 Q1 (c) Q2 Vin2 Figure 10. vin2 (10. (c) simplied diagram. 2007 at 13:42 483 (1) Sec. For simplicity. Solution vout1 = . (b) simpliﬁed small-signal model.gmrO vin1 vout2 = . With ideal current sources.gmrO vin2 (10. 2006] June 30.16(b).10 Compute the differential gain of the circuit shown in Fig. vout2 = .g R . Example 10.90) (10. 10.91) .89) the same as that expressed by (10. since the two halves are identical. Also. Thus.15(c).15 (a) Small-signal model of bipolar pair. where ideal current sources are used as loads to maximize the gain. we may draw only one half.88) vout1 . 10.cls v. 10. we may draw the two half circuits as in Fig. m C vin1 .40).16(a). and the half circuits must be visualized as depicted in Fig. with the understanding that the incremental inputs are small and differential. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. vout2 = .gmRC vin2 : It follows that the differential voltage gain of the differential pair is equal to (10.

93) . we have Solution vout1 . vin2 (10.g r jjr .17 Noting that each pnp device introduces a resistance of rOP at the output nodes and drawing the half circuit as in Fig. vout2 = .16(a). vout2 = .17(b).11 Figure 10. 2007 at 13:42 484 (1) 484 VCC Chap. Example 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10 Differential Ampliﬁers v out Vout V in1 Q1 P I EE (a) (b) Q2 Vin2 v in1 Q1 r O1 r O2 Q2 v in2 Figure 10. VCC Vb Q3 V in1 Q1 P I EE (a) Q4 Vout Q2 Vin2 v in1 Q1 (b) Q3 v out Figure 10.cls v.g r : m O vin1 . 10. 10. (10.17(a) illustrates an implementation of the topology shown in Fig. Calculate the differential voltage gain. vin2 where rON denotes the output impedance of the npn transistors. 2006] June 30.16 and hence vout1 . m ON OP vin1 .92) Exercise Calculate the gain for VA = 5 V.

12 VCC 1. 10. the voltage gain is equal to (10. (10.2 Bipolar Differential Pair 485 Exercise Calculate the gain if Q3 and Q4 are conﬁgured as diode-connected devices. This property holds for any other node that appears on the axis of symmetry. 10.gm1rO1 jjrO3 jjR1 : 2 Since the resistors are linear.19(b). ∆V A Figure 10. we express the total resistance seen at the collector of Q1 as Rout = rO1 jjrO3 jjR1 : Thus.18 create a virtual ground at X if (1) R1 = R2 and (2) nodes A and B vary by equal and opposite amounts. We must emphasize that the differential voltage gain is deﬁned as the difference between the outputs divided by the difference between the inputs.19(a) if VA Vb Q3 Q4 Vout R1 V in1 Q1 P I EE (a) Example 10.12 if the incremental inputs are small and differential. 2007 at 13:42 485 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. For example. R2 Q2 Vin2 V in1 Q3 Vout R1 Q1 (b) Figure 10. the two resistors shown in Fig. We assume perfect symmetry in each case.19 Solution Drawing one of the half circuits as shown in Fig. As such.cls v. As noted above.94) Av = . 10. the symmetry of the circuit (gm1 = gm2 ) establishes a virtual ground at node P in Fig.2 Additional examples make this concept clearer. We now make an observation that proves useful in the analysis of differential circuits. the signals need not be small in this case. this gain is equal to the singleended gain of each half circuit. 10.18 R1 X R2 B ∆V Determine the differential gain of the circuit in Fig.95) . 10.

This is because Q3 and Q4 experience a constant base-emitter voltage in both cases. Assume VA = 1. 10. VX remains constant.14 Determine the gain of the degenerated differential pairs shown in Figs. 2007 at 13:42 486 (1) 486 Chap.96) Exercise Calculate the gain if VA = 4 V for all transistors.21(a) and (b). 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. and IEE = 1 mA.21(a).13 1. In the topology of Fig. node P is a virtual ground. 10.20 For small differential inputs and outputs.20(a) if VA VCC X Q3 R1 Vout V in1 Q1 P I EE (a) (b) Example 10. Calculate the differential gain of the circuit illustrated in Fig. Example 10. thereby serving as current sources and exhibiting only an output resistance. 2006] June 30. It follows that Solution Av = . R1 = R2 = 10 k . yielding the half circuit depicted in Solution .20(b)—the same as that in the above example. 10 Differential Ampliﬁers Exercise Repeat the above example if R1 6= R2 . 10. X Q4 R2 Q2 Vin2 v in1 Q3 R1 v out1 Q1 Figure 10.gm1rO1 jjrO3 jjR1 : (10. leading to the conceptual half circuit shown in Fig.

22(b). and RE = 2=gm.99) .cls v. 10. we have v 1 v 2 rpi1 = iX = . we can deﬁne the input impedance as illustrated in Fig. 10.21(c).97) m In the circuit of Fig. 10.21(b) incorporates a total degeneration resistance of 2RE . then the node between the units acts as a virtual ground [Fig. we have Av = . if RE is regarded as two RE =2 units in series.21(b).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. Assume VCC VA = 1.22(a).21 Fig. the line of symmetry passes through the “midpoint” of RE . 2007 at 13:42 487 (1) Sec. It follows that Av = . 10. 10.98) The two circuits provide equal gains if the pair in Fig.21(d)]. 2006] June 30. Exercise Design each circuit for a gain of 5 and power consumption of 2 mW. From the equivalent circuit in Fig. From Chapter 5. In other words. 10. r2 : (10. = 2:5 V.2 Bipolar Differential Pair VCC RC X Vout Q1 RE P Q2 RE I EE (a) 487 VCC RC X Vin2 V in1 Q1 RE Vout Q2 RC Y Vin2 RC Y V in1 I EE I EE (b) RC v out v in1 Q1 RE (c) RC v out v in1 Q1 RE 2 (d) Figure 10. RERC 1 : 2 + gm (10. RE + g1 RC : (10. I/O Impedances For a differential pair.

vX = v1 . 10 Differential Ampliﬁers VCC RC iX Q1 Q2 r π1 vπ 1 g m1 RC iX RC vπ 1 P g m2 RC vπ 2 vπ 2 iX r π2 vX I EE vX (a) (b) Figure 10.22 (a) Method for calculation of differential input impedance. It is also possible to deﬁne a “single-ended input impedance” with the aid of a half circuit (Fig.100) (10. v2 = 2r1 iX : It follows that (10. 2006] June 30. .23).cls v. respectively.102) but proves useful in some calculations.3 MOS Differential Pair Most of the principles studied in the previous section for the bipolar differential pair apply directly to the MOS counterpart as well.23 Calculation of single-ended input impedance.103) This result provides no new information with respect to that in (10. 10. The above quantity is called the “differential input impedance” of the circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In a manner similar to the foregoing development. vX = r : iX 1 (10. We continue to assume perfect symmetry. obtaining VCC RC iX Q1 vX Figure 10.101) vX = 2r . 10. pi1 iX (10. the reader can show that the differential and single-ended output impedances are equal to 2RC and RC . 2007 at 13:42 488 (1) 488 Chap. Also. our treatment of the MOS circuit in this section is more concise.102) as if the two base-emitter junctions appear in series. For this reason. (b) equivalent circuit of (a).

1 Qualitative Analysis Figure 10. a zero differential input gives a zero differential output. yielding VDD RD X M1 V CM I SS M2 RD Y Figure 10. and VDD = 1:8 V. it is useful to compute the “equilibrium overdrive voltage” of M1 and M2 . we require that their drain voltages not fall below VCM . 2006] June 30. VTH : VDD .cls v. VTH equil: = u ISS W : t n Cox L (10. For our subsequent derivations. Carrying a current of ISS =2. VGS . 2007 at 13:42 489 (1) Sec. we have RD 2 VDD .6 V. The circuit thus rejects input CM variations.109) .24(a) depicts the MOS pair with the two inputs tied to VCM .107) It can also be observed that a change in VCM cannot alter ID1 VY undisturbed. RD ISS 2 VCM . If ISS V. RD ISS : 2 (10. each device exhibits an overdrive of v u VGS .15 Solution From (10. VTH : (10. what is the maximum allowable load resistance? Example 10.106) As expected. VTH = 0:5 A MOS differential pair is driven with an input CM level of 1. VTH 2 .24 Response of MOS differential pair to input CM variation. We assume = 0 and hence ID = 1=2nCox W=LVGS . RD ISS =2.3 MOS Differential Pair 489 10.105) That is. To guarantee that M1 and M2 operate in saturation.3. VTH equil: .108) (10. 10.107). Note that the output CM level is equal to VDD . ID1 = ID2 = ISS 2 and (10. VCM + VTH ISS 2:8 k : (10. = ID2 = ISS =2. a greater tail current or a smaller W=L translates to a larger equilibrium overdrive. leaving VX and = 0:5 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.104) VX = VY = VDD .

then (10. then M1 carries the entire tail current. 2006] June 30. (c) qualitative plots of currents and voltages. generating VDD RD Vout X V in1 M1 M2 I SS (a) (b) VDD RD Vout Y RD RD Y Vin2 V in1 X M1 M2 Vin2 I SS I SS I D2 I D1 0 I SS 2 VX VY VDD I SS VDD − R D 2 VDD − R D I SS 0 V in1 − V in2 (c) V in1 − V in2 Figure 10.111) VX = VDD VY = VDD . Depicted in Fig.32) apply to this case equally well. It follows that .25 illustrates the response of the MOS pair to large differential inputs. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VX = VDD .25(a)]. such a scenario maintains VP constant because Eqs. Exercise What is the maximum tail current if the load resistance is 5 k . Figure 10. RD ISS VY = VDD : Similarly.25 (a) Response of MOS differential pair to very positive input.cls v. 10 Differential Ampliﬁers We may suspect that this limitation in turn constrains the voltage gain of the circuit. Figure 10. 10.26(a).25(c) sketches the characteristics of the circuit.110) (10.25(b)]. 10.113) The circuit therefore steers the tail current from one side to the other. (b) response of MOS differential pair to very negative input. RD ISS : (10. 2007 at 13:42 490 (1) 490 Chap. if Vin2 is well above Vin1 [Fig. If Vin1 is well above Vin2 [Fig. (10. Let us now examine the circuit’s behavior for a small input difference.112) (10.27)-(10. as explained later. producing a differential output in response to a differential input.

= 5=360 .6 V.115) VX . (10. L 2 and hence r W = 1738: L (10. we must choose the transistor dimensions such that gm each transistor carries a drain current of ISS =2.out = VDD . similar to that of a common-source stage.out = 1:6 V. = 0.114) (10. VY = .cls v.119) (10. 2007 at 13:42 491 (1) Sec.gmRD . each resistor must sustain a voltage drop of no more than 200 mV.3 MOS Differential Pair VDD RD + ∆V 491 RD Y M1 P I SS M2 VCM − ∆V X VCM Figure 10.117) Example 10. Assume n Cox = 100 A=V2 . and VDD = 1:8 V.122) . ID1 = gm V ID2 = . 10.2gmRD V: As expected. Solution From the power budget and the supply voltage. Since (10. we have ISS = 1:11 mA: The output CM level (in the absence of signals) is equal to (10.121) gm = 2n Cox W ISS .118) For VCM. 2006] June 30. thereby assuming a maximum value of VCM.116) Av = .120) Setting gm RD = 5.16 Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2 mW subject to the condition that the stage following the differential pair requires an input CM level of at least 1. the differential voltage gain is given by (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.gmV and (10.26 Response of MOS pair to small differential inputs. RD ISS : 2 RD = 360 : (10.

i. RD ISS + VTH 2 VCM. 10 Differential Ampliﬁers The large aspect ratio arises from the small drop allowed across the load resistors.in I SS M2 VDD RD Y V CM.124) V CM.out Figure 10. Exercise Does the above result hold if VTH = 0:2 V.5.27 VCM.cls v. Exercise If the aspect ratio must remain below 200. Thus.17 Solution = 0:4 V? We rewrite (10.107) as VCM..18 The common-source stage and the differential pair shown in Fig.in V TH (10. Example 10.in VDD . (a) For the two circuits to consume the same amount of power ID1 Solution = ISS = 2ID2 = 2ID3 . the constraint on the load resistor in this case arises from the output CM level requirement.in 2 V: (10. 10.out + VTH : This is conceptually illustrated in Fig.e.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. RD X M1 V CM. discuss the choice of (a) transistor dimensions for a given power budget.125) Interestingly. 2006] June 30.28 incorporate equal load resistors. (b) power dissipation for given transistor dimensions. . what voltage gain can be achieved? What is the maximum allowable input CM level in the above example if VTH Example 10. the input CM level can comfortably remain at VDD . 10.27. If the two circuits are designed for the same voltage gain and the same supply voltage. 2007 at 13:42 492 (1) 492 Chap.123) (10. In contrast to Example 10.

3. ID2 . 10.29. Vout = Vout1 . VDD RD V out1 V in1 M1 Vout M2 I SS RD Vout2 Vin2 Figure 10.128) (10. 10.29 MOS differential pair for large-signal analysis.121) therefore requires that the differential pair transistors be twice as wide as the CS device to obtain the same voltage gain. VGS2 ID1 + ID2 = ISS : (10. Exercise Discuss the above results if the CS stage and the differential pair incorporate equal source degeneration resistors. Equation (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.3 MOS Differential Pair VDD R V in1 v in M1 M1 M2 I SS R Vin2 493 VDD R Figure 10. 2007 at 13:42 493 (1) Sec. VGS1 = Vin2 .cls v.28 each transistor in the differential pair carries a current equal to half of the drain current of the CS transistor. ID2 : (10. we neglect channel-length modulation and write a KVL around the input network and a KCL at the tail node: Vin1 . From Fig. our objective here is to derive the input/output characteristics of the MOS pair as the differential input varies from very negative to very positive values. then the tail current of the differential pair must be twice the bias current of the CS stage for M1 -M3 to have the same transconductance.RD ID1 .127) To obtain ID1 . doubling the power consumption. Vout2 = . (b) If the transistors in both circuits have the same dimensions. 2006] June 30.2 Large-Signal Analysis As with the large-signal analysis of the bipolar pair.126) (10.129) .

Vin2 2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.130) Substituting for VGS 1 and VGS 2 in (10. we show that only the solution with the sum of the two terms is acceptable: s (10. Vin2 2 : L (10. n Cox W Vin1 . D1 D2 ID1 + ID2 . Vin2 2 = 0 D1 L (10. Vin2 2 : 2 4 L L s (10. Vin2 = VGS1 . n Cox W Vin1 . ID1 for ID2 . VGS2 n Cox L 2 W ID1 . 2ISS : 2 4 L ID1 = ISS + Vin1 . Vin2 2 = We now ﬁnd pI I .137) It follows that 16I 2 2 . VTH 2 . 2 ID1 ID2 n Cox W L 2 I .140) .128). n Cox W Vin1 . n Cox W Vin1 .138) and hence 2 2 ID1 = ISS 1 4ISS .136) 2 16ID1 ISS .139) In Problem 44. Vin2 2 . Vin2 2 . n Cox W Vin1 . p (10. Vin2 n Cox W 4ISS .131) (10.132) Squaring both sides yields Vin1 .133) (10.134) 4 ID1 ID2 = 2ISS . u VGS = VTH + u 2ID W : t n Cox L v u =u t 2 v (10. L square the result again. L and substitute ISS . 2007 at 13:42 494 (1) 494 Chap. ID2 : p p (10. 2006] June 30. n Cox W Vin1 .cls v. ID1 = 2ISS . 16ISS ID1 + 2ISS .135) (10. we have Vin1 . 2pI I : = SS D1 D2 n Cox W L p (10. 2 16ID1 ID2 = 2ISS . 10 Differential Ampliﬁers Since ID = 1=2nCox W=LVGS .

at some point that M1 or M2 turns off.cls v. can the difference under the square root vanish. then its gate-source voltage falls to a value equal to VTH . Vin2 jmax = u 2ISSW . Vin2 2 : t 2 L C n ox v (10. Vin2 jmax denotes the input difference that places one transistor at the edge of conduction.142) closely. violating the above equations. ID2 falls to zero as Vin1 . 10. 2007 at 13:42 495 (1) Sec. We must therefore determine the input difference that places one of the transistors at the edge of conduction.144) v u jVin1 . Vin1 . Equation (10.25(c). ID2 = 1 n Cox W Vin1 . Vin1 n Cox W 4ISS . 10. Vin2 2 exceeds this value! How should these results be interpreted? Implicit in our foregoing derivations is the assumption that both transistors are on.30 MOS differential pair with one device off. (10.145) where jVin1 . 10.145) is invalid for input differences greater than this value. as jVin1 . Let us now examine (10. n Cox W Vin2 . Indeed. dropping to zero for a zero input difference.142) to ISS .141). As expected from the characteristics in Fig.128) that (10. Furthermore. but leading to lengthy algebra. Vin2 j rises. for example. Instead. Vin2 2 reaches 4ISS =n Cox W=L . too? That would suggest that ID1 .30 that if. Vin1 2 : 2 4 L L That is.142) L Equations (10. Vin2 . But.141) u ID1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. or (10.143) (10. M1 Edge of Conduction + ~0 I SS M2 − I SS + VGS2 M1 VTH − Figure 10. we recognize from Fig.140).3 MOS Differential Pair 495 The symmetry of the circuit also implies that ID2 = ISS + Vin2 . Also. the right-hand side is an odd (symmetric) function of Vin1 . an effect not predicted by our qualitative sketches in Fig. This can be accomplished by equating (10. t n Cox L (10. the gate-source voltage of M2 must be sufﬁciently large to accommodate a drain current of ISS : VGS1 = VTH v u VGS2 = VTH + u 2ISSW : t n Cox L It follows from (10.25(c).142) form the foundation of our understanding of the MOS differential pair. . 2006] June 30. However.140)-(10. it appears that the argument of the square root becomes negative as Vin1 . approaches the edge of conduction. 10. s (10. Vin2 u 4ISSW .

We also note that jVin1 .31(b) and (c). 10 Differential Ampliﬁers substituting from (10.max 0 − I SS (b) − ∆V in. 10. (a) Equation (10.max − R D I SS V in1 − V in2 Figure 10.max V in1 − V in2 V out1 − V out2 + R D I SS − ∆V in. we plot ID1 and ID2 as in Fig. 10.cls v.31 Variation of (a) drain currents. where Vin = Vin1 .max + I SS V in1 − V in2 I D1 − I D2 + ∆V in.145) suggests that doubling ISS increases Vin. Example 10. Vin2 jmax can be related to the equilibrium overdrive [Eq.19 Examine the input/output characteristic of a MOS differential pair if (a) the tail current is doubled. and (c) differential output voltage as a function of input. (b) the difference between drain currents.142) also yields jID1 . displaying a greater slope. since ISS RD doubles.146) The above ﬁndings are very important and stand in contrast to the behavior of the bipolar differential pair and Eq. Figure 10.max by a factor of 2. I SS I D2 I D1 − ∆V in. (10. (10. or (b) the transistor aspect ratio is doubled. Solution p 3 In reality. arriving at the differential characteristics in Figs.145) in (10.146) provides a great deal of intuition into the operation of the MOS pair. the characteristic of Fig.106)] as follows: p jVin1 . Speciﬁcally.max 0 (c) + ∆V in. ID2 j = ISS .max 0 (a) I SS 2 + ∆V in. Vin. 2006] June 30. Thus. MOS devices carry a small current for illustration.31(a).max serves as an absolute bound on the input signal levels that have any effect on the output.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vin2 . The circuit thus behaves linearly for small values of Vin and becomes completely nonlinear for Vin Vin. Equation (10.31(c) expands horizontally.max . Vin2 jmax whereas the bipolar counterpart only approaches this condition for a ﬁnite input difference. 10. Vin2 jmax = 2VGS . 2007 at 13:42 496 (1) 496 Chap. the characteristic expands vertically as well. In other words. Furthermore.32(a) illustrates the result. VGS = VTH . VTH equil: : (10. making these observations only an approximate .78): the MOS pair steers all of the tail current3 for jVin1 .

or (b) the transistor aspect ratio is halved. From Eq.max − R D I SS −2 R D I SS (a) + 2 ∆V in. 2007 at 13:42 497 (1) Sec.max − ∆V in.3 MOS Differential Pair V out1 − V out2 +2R D I SS + R D I SS + ∆V in.max Figure 10.148) .max = 500 mV. The tail current must not exceed 3 mW=1:8 V = 1:67 mA.max 2 V in1 − V in2 + ∆V in. Vin. exhibiting a larger slope in the vicinity of Vin = 0.max 2 − R D I SS (b) + ∆V in. (10. The characteristic therefore contracts horizontally [Fig.max − ∆V in. 10.max by a factor of 2 while maintaining ISS RD constant. p Exercise Repeat the above example if (a) the tail current is halved.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we write Solution 2ISS W= 2 L n Cox Vin.147) (10.max 497 V in1 − V in2 V out1 − V out2 + R D I SS − ∆V in.32 (b) Doubling W=L lowers Vin.max = 133:6: The value of the load resistors is determined by the required voltage gain.20 Design an NMOS differential pair for a power budget of 3 mW and Assume n Cox = 100 A=V2 and VDD = 1:8 V.145). 2006] June 30. (10.32(b)]. 10.max − 2 ∆V in. Example 10.cls v.

(b) simpliﬁed circuit.151) Now.v2 (10. the differential inputs and outputs are linearly proportional.150) (10. v2 gm1 v1 + gm2 v2 = 0: Assuming perfect symmetry. v1 = vin2 .153) v1 = .142). We now use the small-signal model to prove that the tail node remains constant in the presence of small differential inputs.33 (a) Small-signal model of MOS differential pair. 2007 at 13:42 498 (1) 498 Chap.cls v.3 for the bipolar counterpart. and the circuit operates linearly.3.33(a). 10.2. Vin2 : L v (10. If = 0. Vin2 u 4ISSW t L n Cox L r = n Cox W ISS Vin1 .152) (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if jVin1 .153) (10. W (10.149) u 1 ID1 . vin1 . 2006] June 30. we have from (10. yielding RD v in1 v1 g v m1 1 P (a) RC v in1 v1 g v m1 1 g v m2 2 RC v2 v in2 g v m2 2 RD v2 v in2 (b) Figure 10.3 Small-Signal Analysis The small-signal analysis of the MOS differential pair proceeds in a manner similar to that in Section 10. ID2 2 n Cox W Vin1 . Vin2 j then n Cox L 4ISS . (10. 10 Differential Ampliﬁers Exercise How does the above design change if the power budget is raised to 5 mW? 10. The deﬁnition of “small” signals in this case can be seen from Eq. the circuit reduces to that shown in Fig.154) .

gm RD Vin1 .86) with the observation that v =r = 0 for a MOSFET. the analysis of MOS differential topologies is greatly simpliﬁed if virtual grounds can be identiﬁed. of course. (10. With node P acting as a virtual ground. Example 10. After all.RD n Cox W ISS Vin1 . small-signal operation simply means approximating the input/output characteristic [Eq. v1 =0 (10. vin2 Example 10. Exercise = 2ID =VGS . and.151) can also yield the differential voltage gain.157) Alternatively. (10. express the above result in terms of the equilibrium As with the bipolar circuits studied in Examples 10.156) (10. The following examples reinforce this concept. Assume 6= 0. (10. (10.21 Prove that (10.151)] around an operating point (equilibrium). Vout2 from (10. 2007 at 13:42 499 (1) Sec.160) Solution = . therefore. the concept of half circuit applies.161) (10.gmRD vin1 vout2 = . Since Vout1 . we have p Vout1 . 2006] June 30.151) (10. we require vin1 = . 10.155) vP = vin1 . 10.gmRD vin2 .162) This is.159) vout1 . vout1 = .158) (10. we can simply utilize Eqs. leading to the simpliﬁed topology in Fig.14.10 and 10.152) translates to vin1 = v1 and hence (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.81)-(10.RD ID1 .3 MOS Differential Pair 499 and for differential inputs. (10.vin2 . Thus. Vout2 = . 10. vout2 = .33(b). Determine the voltage gain of the circuit shown in Fig.34(a). ID2 and since gm = n Cox W=LISS (why?). VTH . Vin2 L = .g R : m D vin1 . arriving at the same result. Vin2 : r (10. Using the equation gm overdive voltage. to be expected.22 .cls v.142)] with a straight line [Eq. Here.

The voltage gain is therefore equal to Av = . 10 Differential Ampliﬁers M4 M3 Vin2 v in1 v out1 M1 (b) Figure 10. we note that the total resistance seen at the drain of M1 is equal to 1=gm3jjrO3 jjrO1 . 10.34(b).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.gm1 g 1 jjrO3 jjrO1 : m3 .cls v.34 Solution Drawing the half circuit as in Fig. 2007 at 13:42 500 (1) 500 VDD M3 Vout V in1 M1 M2 I SS (a) Chap. 2006] June 30.

35(a). VDD Example 10. Solution . compute the voltage gain of the circuit illustrated in Fig.23 Vout V in1 P I SS1 (a) M3 Q M4 Vin2 v out1 I SS2 v in1 M1 M3 (b) Figure 10.163) Exercise Repeat the above example if a resistance of value R1 is inserted in series with the sources of M3 and M4 . we construct the half circuit shown in Fig.35 Identifying both nodes P and Q as virtual grounds. Assuming = 0. 10. (10.

4 Cascode Differential Ampliﬁers Recall from Chapter 9 that cascode stages provide a substantially higher voltage gain than simple CE and CS stages do. Noting that the differential gain of differential pairs is equal to the single- . and write g Av = .24 Vout R DD R SS R DD 2 v out1 M2 Vin2 v in1 M1 R SS 2 V in1 M1 (a) (b) Figure 10. Grounding the midpoint of RSS and RDD . 10. VDD Example 10.35(b). 10.36 . RSS 2 1 : 2 + gm Exercise RDD (10. where Solution Av = .165) Repeat the above example if the load current sources are replaced with diode-connected PMOS devices. gm1 : m3 (10. 10.36(b).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.36(a).4 Cascode Differential Ampliﬁers 501 10. 2007 at 13:42 501 (1) Sec. 2006] June 30. 10.164) Exercise Repeat the above example if 6= 0.cls v. Assuming = 0. we obtain the half circuit in Fig. calculate the voltage gain of the topology shown in Fig.

cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 502 (1) 502 Chap. (10. the resulting conﬁguration can be analyzed with the aid of its half circuit.38(b). Av . 10. 10 Differential Ampliﬁers ended gain of their corresponding half circuits. Utilizing Eq.37 (a) Bipolar cascode differential pair. The developments in Chapter 9 also suggest the use of pnp cascodes for current sources I1 and I2 in Fig.gm1 gm3 rO1 jjr3 rO3 + rO1 jjr3 .61).37(a). Equation (9. 10. 10. 10.37(a). Illustrated in Fig.38(a). 2006] June 30.37(b).gm1 gm3 rO3 rO1 jjr3 jj gm5 rO5 rO7 jjr5 : (10.38 (a) Bipolar cascode differential pair with cascode loads. we express the voltage gain as V CC V b3 Q7 V b2 Q5 Q3 V b1 V in1 Q1 Q2 Vin2 v in1 I EE (a) (b) Q8 Q6 Vout Q4 Q7 Q5 Q3 v out1 Q1 Figure 10. (b) half circuit of (a). we construct the half circuit shown in Fig.167) . (b) half circuit of (a). where Q3 and Q4 serve as cascode devices and I1 and I2 are ideal. Recognizing that the bases of Q3 and Q4 are at ac ground. 10.51) readily gives the gain as VCC I1 Vout Q3 Vb V in1 Q1 Q2 Vin2 v in1 I EE (a) (b) I2 Q4 Q3 v out1 Q1 Figure 10. we surmise that cascoding boosts the gain of differential pairs as well. We begin our study with the structure depicted in Fig. Av = .166) conﬁrming that a differential cascode achieves a much higher gain. Fig. (9.

10.38(b) exempliﬁes the internal circuit of some operational ampliﬁers.39(a). Due to a manufacturing defect. a parasitic resistance has appeared between nodes A and the circuit of Fig.gm1 gm3 rO3 rO1 jjr2 jjRop : .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.25 B in Q8 B R1 Q6 Vout Q4 Q7 Q5 Q3 R1 2 v out1 Q1 Figure 10.cls v. 10.4 Cascode Differential Ampliﬁers 503 Called a “telescopic cascode. lowering the output impedance of the pnp cascode. Since the value of R1 is not given.1): Solution R1 r + r jjr jj R1 : Rop = 1 + gm5 rO7 jjr5 jj 2 O5 O7 5 2 Av = .” the topology of Fig. Eq. Thus.39(b). leading to the half circuit shown in Fig. (9. 10. 2006] June 30. 2007 at 13:42 503 (1) Sec.39 The symmetry of the circuit implies that the midpoint of R1 is a virtual ground. VCC V b3 Q7 A V b2 Q5 Q3 V b1 V in1 Q1 Q2 Vin2 v in1 I EE (a) (b) Example 10. we cannot make approximations and must return to the original expression for the cascode output impedance. Determine the voltage gain of the circuit. R1 =2 appears in parallel with rO7 .

what value of R1 degrades the We now turn our attention to differential MOS cascodes. The voltage gain is therefore equal to (10.168) The resistance seen looking down into the npn cascode remains unchanged and approximately equal to gm3 rO3 rO1 jjr2 . Following the above developments for bipolar counterparts.169) If = 50 and VA = 4 V for all transistors and IEE gain by a factor of two? Exercise = 1 mA. 10.40(a) and draw the half . (10. we consider the simpliﬁed topology of Fig.

42(a).72) that the voltage gain is given by V b3 V b2 M5 M3 V b1 V in1 M1 M2 I SS (a) (b) M7 M8 VDD M7 M6 Vout M4 Vin2 v in1 M5 M3 v out1 M1 Figure 10. shown in Fig. 10. have appeared as Noting that R1 and R2 appear in parallel with rO5 and rO6 . we must resort to the original expression for the output impedance. Av . (9. (9.41 (a) MOS telescopic cascode ampliﬁer.172) .cls v.gm1 gm3 rO3 rO1 jjgm5 rO5 rO7 : Example 10.42(b). (b) half circuit of (a). VDD M3 V b1 V in1 Vout M4 M1 M2 I SS (a) M3 Vin2 v in1 v out1 M1 (b) Figure 10. yielding the half circuit shown in Fig.41(a).171) R1 and R2 .26 Due to a manufacturing defect.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. Eq.40 (a) MOS cascode differential pair. (9. Without the value of R1 given. respectively. two equal parasitic resistances.40(b). the complete CMOS telescopic cascode ampliﬁer incorporates PMOS cascades as load current sources. It follows from Eq. Compute the voltage gain of the circuit.41(b). 2006] June 30. Av .69). 2007 at 13:42 504 (1) 504 Chap. (b) half circuit of (a). 10. From Eq. 10 Differential Ampliﬁers circuit as depicted in Fig. 10.3): Solution Rp = 1 + gm5 rO5 jjR1 rO7 + rO5 jjR1 : (10. 10. (10.170) Illustrated in Fig. we draw the half circuit as depicted in Fig.gm3rO3 gm1 rO1 : (10.

we have observed that these circuits produce no change in the output if the input CM level changes. reducing the topology to that shown in Fig.42 The resistance seen looking into the drain of the NMOS cascode can still be approximated as Rn gm3 rO3 rO1 : The voltage gain is then simply equal to (10. As VP increases. 2006] June 30. As the reader may have guessed. 2007 at 13:42 505 (1) Sec. from Chapter 5. since the base voltages of both Q1 and Q2 rise. The common-mode rejection property of differential circuits plays a critical role in today’s electronic systems. as far as node P is concerned.43(a). The change in the output CM level can be computed by noting that the stage in Fig. noting that Vout1 = Vout2 .43(b).174) Exercise Repeat the above example if in addition to the sources of M3 and M4 . In fact. What happens if the input CM level changes by a small amount? The symmetry requires that Q1 and Q2 still carry equal currents and Vout1 = Vout2 . the output common-mode level falls. But. That is. That is.cls v. we can place a short circuit between the output nodes. . Consequently.5 Common-Mode Rejection In our study of bipolar and MOS differential pairs. 10. we examine the CM rejection in the presence of nonidealities.5 Common-Mode Rejection M7 M8 VDD M7 Vb2 M6 M5 M4 M1 M2 I SS (a) (b) 505 V b3 V b2 M5 M3 V b1 V in1 R1 R2 R1 v out1 Vout M3 Vin2 v in1 M1 Figure 10. In this section. in practice the CM rejection is not inﬁnitely high. where REE denotes the output impedance of IEE . a resistor of value R3 appears between 10. so does the current through REE and hence the collector currents of Q1 and Q2. 10.43(b) resembles a degenerated CE stage. so does VP . The ﬁrst nonideality relates to the output impedance of the tail current source. Q1 and Q2 operate as an emitter follower. 10. 10.gm1 Rp jjRn : (10. R1 and R2 . Consider the topology shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.173) Av = .

the differential pair produces an output CM change in response to an input CM change. With an ideal tail current source. 2REE + gm1 RC (10.44(b). Consequently.175) RC . 2007 at 13:42 506 (1) 506 VCC RC V out1 Q1 V CM I EE P Q2 RC Vout2 Chap. then the differential output is corrupted. the transistors or the load resistors may display slightly different dimensions. leading to the output waveforms shown in Fig. (b) simpliﬁed circuit of (a). if the tail current exhibits a ﬁnite output impedance.44(c)].” These observations apply to the MOS counterpart equally well. the base voltages of Q1 and Q2 with respect to ground appear as shown in Fig. if the circuit suffers from asymmetries and a ﬁnite tail current source impedance. Depicted in Fig. the input CM variation would have no effect at the output. As an example of the effect of asymmetries. Figure 10. for example.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vin.CM . but not the differential output [Fig.45(a) for a MOS pair. we consider the simple case of load resistor mismatch. This quantity is called the “common-mode gain. so long as the quantity of interest is the difference between the outputs. On the other hand. (10. During manufacturing. After all. 10. Vin1 and Vin2 . 10. 2006] June 30. In summary. 10. As a result. the change in the tail current due to an input CM variation may affect the differential output. An alternative approach to arriving at (10. 2 1 Vin. in the presence of input CM noise. Here.176) where the term 2gm represents the transconductance of the parallel combination of Q1 and Q2 .cls v. . 5 We have chosen a MOS pair here to show that the treatment is the same for both technologies. .4 However.CM REE + 2g m =. In summary. Vout.175) is outlined in Problem 65. two differential inputs. a ﬁnite CM gain does not corrupt the differential output and hence proves benign.5 this imperfection leads to a difference between Vout1 and Vout2 . 10. The reader may naturally wonder whether this is a serious issue. older literature has considered this effect troublesome. the above study indicates that. 10 Differential Ampliﬁers VCC Vout Q2 Q1 P I EE R EE RC 2 V CM R EE (a) (b) Figure 10. a change in the output CM level introduces no corruption. with REE 1.CM = . experience some common-mode noise.43 (a) CM response of differential pair in the presence of ﬁnite tail impedance. the single-ended outputs are corrupted. We must compute the change in ID1 and ID2 and multiply the result by RD and RD + RD . random “mismatches” appear between the two sides of the differential pair. 4 Interestingly.44(b).44(a) illustrates such a situation.

6 Writing ID1 = ID2 = ID and VGS 1 = VGS 2 = VGS .5 Common-Mode Rejection 507 VCC RC Vout1 A V in1 Q1 P Q2 RC Vout2 B V in2 VA VB VA VB Vout1 Vout1 V CM I EE R EE Vout2 Vout2 Vout1 −Vout2 Vout1 −Vout2 t (a) (b) (c) t 1.177) L 1 ID2 = 2 n Cox W VGS2 . VTH 2 (10. VTH 2 . creating a voltage change of 2ID RSS 6 But with 6= 0.cls v.178) L concluding that ID1 must be equal to ID2 because VGS 1 = VGS 2 and hence VGS 1 = VGS2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we recognize that both ID1 and ID2 ﬂow through RSS . How do we determine the change in ID1 and ID2 ? Neglecting channel-length modulation. . it would. (b) effect of CM noise at output with REE = VDD R D + ∆R D Vout2 M1 P M2 ∆V V CM I SS R SS Figure 10. we ﬁrst observe that 1 ID1 = 2 n Cox W VGS1 . 2007 at 13:42 507 (1) Sec. (c) effect of CM noise at the output with REE 6= 1. RD V out1 Figure 10. the load resistor mismatch does not impact the symmetry of currents carried by M1 and M2 . 2006] June 30. (10.45 MOS pair with asymmetric loads. 10. In other words.44 (a) Differential pair sensing input CM noise.

VCM = VGS + 2ID RSS and. 2006] June 30. since VGS (10. 10 Differential Ampliﬁers across it.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . VCM = ID g1 + 2RSS : m That is.179) = ID =gm.cls v. Thus. 2007 at 13:42 508 (1) 508 Chap.

ID RD = .181) Vout = Vout1 . a bipolar current source may employ emitter degeneration and a MOS current source may incorporate a relatively long transistor.DM .182) (10. 10.DM for the circuit shown in Fig.186) yields (10. In practice.185) RD Vout VCM = 1 + 2RSS : g m (10.188) RC ACM . 1 VCM RD : g + 2RSS m It follows that (10.DM 2R D : SS (10. Assume VA Example 10.DM = 1 : + 2f 1 + gm3 R1 jjr3 rO3 + R1 jjr3 g gm1 (10. It is therefore reasonable to assume RSS 1=gm and R ACM . ID RD + RD = .186) (This result can also be obtained through small-signal analysis. (10.183) (10.46.27 Solution = 1 for Q1 and Q2 . Vout2 = ID RD . we strive to minimize this corruption by maximizing the output impedance of the tail current source.189) . thereby generating a differential output change of ID = 1 VCM : g + 2RSS m (10. For example.) We say the circuit exhibits “common mode to differential mode (DM) conversion” and denote the above gain by ACM .180) Produced by each transistor.187) Determine ACM . Recall from Chapter 5 that emitter degeneration raises the output impedance to Rout3 = 1 + gm3 R1 jjr3 rO3 + R1 jjr3 : Replacing this value for RSS in (10.184) (10. this current change ﬂows through both RD and RD +RD .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. If the circuit provides a large differential gain.cls v. The mismatches between the transistors in a differential pair also lead to CM-DM conversion. Thus.g. ADM . Example 10.191) m CMRR = g1 RC g 1 + 2 1 + gm3 R1 jjr3 rO3 + 2R1 jjr3 : RC m1 Exercise Determine the CMRR if R1 ! 1.190) Representing the ratio of “good” to “bad. CM-DM conversion cannot be simply quantiﬁed by ACM . While undesirable. RC RC . . (10. 2007 at 13:42 509 (1) Sec. 10.28 Calculate the CMRR of the circuit in Fig. and the differential gain is equal to gm1 RC .DM (10. We therefore deﬁne the “common-mode rejection ratio” (CMRR) as CMRR = A ADM : CM . Solution For small mismatches (e.46 Exercise Calculate the above result if R1 ! 1.5 Common-Mode Rejection VCC RC V out1 Q1 V CM P R out3 Vb Q3 R1 Q2 R C + ∆R C Vout2 509 Figure 10.. 1). then the relative corruption at the output is small. This effect is beyond the scope of this book [1]. 2006] June 30.DM . 10.46.” CMRR serves as a measure of how much wanted signal and how much unwanted corruption appear at the output if the input consists of a differential component and common-mode noise.

the circuit employs a symmetric differential pair. Q1 -Q2 . Recall that the op amps used in Chapter 8 have a differential input but a single-ended output [Fig.47 (a) Circuit with differential input and single-ended output.47(b) as a candidate for this task. We may naturally consider the topology shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10 Differential Ampliﬁers 10. we study an interesting combination of differential pairs and current mirrors that proves useful in many applications. along with a current-mirror load. the voltage gain is now halved because the signal swing at node X is not used. 10. additional stages precede this stage so as to provide a high gain. (b) possible implementation of (a). 2007 at 13:42 510 (1) 510 Chap. let us ﬁrst address a problem encountered in some cases. 10. VCC RC V in1 V in2 Vout X V in1 V in2 RC Y Vout (a) (b) Figure 10.47(a)]. We now introduce a topology that serves the task of “differential to single-ended” conversion while resolving the above issues. 10.48. Thus. 2006] June 30.48 Differential pair with active load. the internal circuits of such op amps must incorporate a stage that “converts” a differential input to a single-ended output.6 Differential Pair with Active Load In this section. 7 In practice.) The output is sensed with respect to ground. the output is sensed at node Y with respect to ground rather than with respect to node X .cls v. Here. To arrive at the circuit. VCC Q3 N V in1 Q1 Q2 Vin2 Vout Q4 I EE Figure 10.7 Unfortunately. Q3 -Q4 . (Transistors Q3 and Q4 are also identical. . Shown in Fig.

50. 10.49(b) and suppose the current drawn from Q3 increases from IEE =2 to IEE =2 + I .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the collector current of Q4 also increases by I .cls v. . VCC Q3 N I EE 2 + ∆V + ∆I Q4 I C4 I EE 2 − ∆I RL Vout VCM Q1 P Q2 VCM − ∆V I EE Figure 10.1 Qualitative Analysis It is instructive to ﬁrst decompose the circuit of Fig. by virtue of current mirror action. The load resistor. we recognize that the change in IC 3 is also equal to I . As depicted in Fig. Let us now determine how the change in IC 1 travels through Q3 and Q4 .49(a) (along with a ﬁctitious load RL ). is added to augment our intuition but it is not necessary for the actual operation. 2006] June 30. since the small-signal impedance seen at node N is approximately equal to 1=gm3 . jIC 3 j. Since Q4 “injects” a greater current into the output node.50 Detailed operation of pair with active load. In other words. With the input voltage changes shown here. Ignoring the role of Q3 and Q4 for the moment. 10. we observe that the fall in IC 2 translates to a rise in Vout because Q2 draws less current from RL . 10. Vout rises. Now consider the circuit in Fig. creating a voltage change of IRL across RL . 2007 at 13:42 511 (1) Sec. we note that IC 1 increases by some amount I and IC 2 decreases by the same amount. change at the input.6.6 Differential Pair with Active Load 511 10. 10. What happens? First. IC 1 .50).48 into two sections: the input differential pair and the current-mirror load. RL . in response to the differential input shown in Fig. Neglecting the base currents of these two transistors. we apply small. VN changes by I=gm3 (for small I ). the voltage across RL changes by IRL . 10. The output change can therefore be an ampliﬁed version of V . (b) response of active load to current change. In order to understand the detailed operation of the circuit. Second. As a result. This change is copied into IC 4 by virtue of the current mirror action. Q1 and Q2 produce equal and opposite changes in their collector currents in response to a differential ∆I R L V I EE 2 + ∆V + ∆I I EE 2 CC − ∆I RL Vb Q3 N − ∆V Q4 VCM Q1 P Q2 VCM I EE 2 + ∆I ∆I R L RL I EE (a) (b) Figure 10. and jIC 4 j increase by I . 10. differential changes at the input and follow the signals to the output (Fig.49 (a) Response of input pair to input change.

6. vin1 . VCC Vb Q3 V in1 Q1 P I EE (a) Q4 Vout Q2 Vin2 Figure 10.52 Differential pair with current-source loads. 10. . Specifically. 10. in the above example.53. 10.cls v. the circuit of Fig. in response to a small. Fig. 10.52. For a differential input change. The foregoing analysis directly applies to the CMOS counterpart. Our initial examination of Q3 and Q4 in Fig. 10. the current mirror transistors are identical. 2007 at 13:42 512 (1) 512 Chap.2 Quantitative Analysis The existence of the signal paths in the differential to single-ended converter circuit suggests that the voltage gain of the circuit must be greater than that of a differential topology in which only one output node is sensed with respect to ground [e. 2006] June 30. ID1 rises to ISS =2 + I and ID2 falls to ISS =2 . each path experiences a current change. The key point here is that the two paths enhance each other at the output. too. divided by the smallsignal differential input.50 indicates an interesting difference with respect to current mirrors studied in Chapter 9: here Q3 and Q4 carry signals in addition to bias currents. the combination of Q3 and Q4 plays a critical role in the operation of the circuit. where the baseemitter voltage of the load transistors remains constant and independent of signals. increasing jID4 j and raising Vout . Also. vin2 . each path forces Vout to increase.g.54) to demonstrate that both CMOS and bipolar versions are treated identically. To conﬁrm this conjecture. 10. Called an “active load” to distinguish it from the load transistors in Fig. This also stands in contrast to the current-source loads in Fig. which translates to a voltage change at the output node. we wish to determine the small-signal single-ended output. The change in ID2 tends to raise Vout .) 10. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the change in ID1 and ID3 is copied into ID4 . We deal with a CMOS implementation here (Fig.47(b)]. vout .52. I .. Q3 and Q4 [Fig.51(a)]. shown in Fig. (In this circuit. 10 Differential Ampliﬁers In summary. one through Q1 and Q2 and another through Q1 . 10. VCC Q3 N V in1 Q1 Path 1 Path 2 Q4 Q2 Vin2 Vout I EE Figure 10.51 Signal paths in pair with active load.50 contains two signal paths. differential input.

55. With the diodeconnected device. we perform the analysis in two steps.iY . 2007 at 13:42 513 (1) Sec. In M3 1 g mP M4 g v mP A iY r ON r ON P g v mN 2 v2 M2 v in2 r OP vA iX g v mN 1 r OP v out A v in1 v1 M1 Figure 10. creating a low impedance at node A. The circuit of Fig. 10. where the dashed boxes indicate each transistor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. While the transistors themselves are symmetric and the input signals are small and differential. On the other hand. we expect a relatively small voltage swing—on the order of the input swing—at this node.6 Differential Pair with Active Load VDD M3 + ∆V 513 M4 RL M1 M2 I SS − ∆V Vout Figure 10.54 presents a quandary. Also.54 MOS pair for small-signal analysis. Referring to the equivalent circuit shown in Fig. the ﬁrst step. We present two approaches to solving this circuit.cls v. . the circuit serves as an ampliﬁer. 10. M3 .55 (a) Small-signal equivalent circuit of differential pair with active load. (After all. transistors M2 and M4 provide a high impedance and hence a large voltage swing at the output node.53 MOS differential pair with active load. 2006] June 30. the circuit is asymmetric. Approach I Without a half circuit available.) The asymmetry resulting from the very different voltage swings at the drains of M1 and M2 disallows grounding node P for small-signal analysis. M3 A V in1 M1 P I SS M2 VDD M4 Vout Vin2 Figure 10. the analysis can be performed through the use of a complete small-signal model of the ampliﬁer. we note that iX and iY must add up to zero at node P and hence iX = .

cls v. vin2 = gmN rON jjrOP : The gain is indepedent of gmP and equal to that of the fully-differential circuit. gmN v2 .195) In the second step. vin2 . vin2 = gmN rON 2rON + 2rOP This is the exact expression for the gain.56(a). Recall that vThev is the voltage between A and B in the “open-circuit condition” This section can be skipped in a ﬁrst reading. As illustrated in Fig. vin2 + vout = 0: Substituting for vA and iX from above.192) (10.iY = r out + gmP vA OP vout . 2006] June 30.iX gmP jjrOP and v . iX = rOP 1 + gmP g 1 jjrOP mP vout : (10. vin2 : (10.vA + 2iX rON . 2007 at 13:42 514 (1) 514 Chap. In other words. g i 1 jjr =r mP X g OP OP = iX : mP (10. If gmP rOP 1. M1 and M2 . the use of the active load has restored the gain.200) vin1 .198) Solving for vout yields vout rOP 1 + gmP g 1 jjrOP vout mP : (10. v2 (10. . It follows that . we decompose the circuit into sections that more easily lend themselves to analysis by inspection.196) = vin1 . gmN v1 rON . we have (10. then vout (10. assuming vin1 and vin2 are differential. gmN v2 rON + vout = 0: Since v1 .194) Thus. iY . 10.iY . gmN v1 and that through rON of M2 equal to iY .1 vA = . 10 Differential Ampliﬁers . vin2 and iX = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.197) 1 vout 1 jjr gmP jjrOP + 2rON r 1 + g 1 jjr rOP 1 + gmP g OP mP g OP OP mP mP + vout = gmN rON vin1 . gmN rON vin1 .vA + iX .199) vin1 .193) (10. The current through rON of M1 is equal to iX . Approach II In this approach. we ﬁrst seek a Thevenin equivalent for the section consisting of vin1 . we write a KVL around the loop consisting of all four transistors. .

cls v.203) The reader is encouraged to obtain this result using half circuits as well. Figure 10.92) thus yields vThev = . 10. 10.6 Differential Pair with Active Load 515 [Fig. and (c) Thevenin resistance of input pair.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. where the diodeconnected transistor M3 is replaced with 1=gm3 jjrO3 and the output impedance of M4 is drawn explicitly.204) . Having reduced the input sources and transistors to a Thevenin equivalent. 10. vin2 . Noting that M1 and M2 have equal gate-source voltages (v1 = v2 ) and writing a KVL around the “output” loop.gmN rON vin1 .202) RThev = 2rON : (10. 2006] June 30. M3 A v in1 M1 P I SS M2 VDD M4 B v out v in2 (10. the circuit is symmetric. we can view vA as a divided version of vE : 1 gm3 jjrO3 vout + vThev : vA = 1 gm3 jjrO3 + RThev (10. 2007 at 13:42 515 (1) Sec. (b) Thevenin voltage.16(a). Since the voltage at node E with respect to ground is equal to vout + vThev .56(b)]. Under this condition. we set the inputs to zero and apply a voltage between the output terminals [Fig. where the subscript N refers to NMOS devices. The objective is to calculate vout in terms of vThev . To determine the Thevenin resistance. 10. Equation (10.56(c)]. resembling the topology of Fig.201) v Thev R Thev (a) vX iX iX M2 r O1 r O2 P I SS v2 v Thev A v in1 M1 P I SS M2 B v in2 M1 v1 (b) (c) Figure 10. gm1 v1 rO1 + iX + gm2 v2 rO2 = vX and hence (10.56 (a) Thevenin equivalent. we have iX . we now compute the gain of the overall ampliﬁer.57 depicts the simpliﬁed circuit.

It follows from (10. we reduce (10. rO4 gm3 jjrO3 + RThev (10. vin2 ON OP ON and hence .206) to RThev and assuming gm3 = gm4 = gmp and OP (10. Given by gm4 vA .204) and (10. 2007 at 13:42 516 (1) 516 r O3 1 g m3 Chap. and 1=gm3 rO3 = rO4 = rOP .206) Recognizing that 1=gm3 rO3 . 2006] June 30.207) 2 v + v + vout = 0: out Thev R r Thev Equations (10.205) that 0 Bg B m4 @ 1 + 1 1 jjr + R gm3 O3 Thev gm3 jjrO3 + RThev 1 gm3 jjrO3 1 C v + v + vout = 0: C out Thev A rO4 (10.cls v.57 Simpliﬁed circuit for calculation of voltage gain.201) and (10. 10 VDD M4 R Thev v Thev E B v out r O4 Differential Ampliﬁers A Figure 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the small-signal drain current of M4 must satisfy KCL at the output node: gm4vA + vout + 1 vout + vThev = 0.207) therefore give vout r 1 + r 1 = gmN rONr vin1 .205) where the last term on the left hand side represents the current ﬂowing through RThev .

29 Solution vA = . the gain of this circuit is the same as the differential gain of the topology in Fig. 10. gm4 vA . KCL at the output node indicates that the total current drawn by M2 must be equal to . vin2 = gmN rON jjrOP : (10. (10.51(b). This current ﬂows through M1 and hence through M3 . we surmised that the voltage swing at node A in Fig.56 is much less than that at the output.58. 10. Interestingly. In other words. generating Example 10.vout =rO4 .209) The gain is independent of gmp . Prove this point.208) vout vin1 . As depicted in Fig. 10. In our earlier observations. the path through the active load restores the gain even though the output is single-ended.vout rO4 + gm4 vA g 1 jjrO3 : m3 .

210) . (10.

10. The transistor currents in a differential pair remain constant as the input CM level changes. i. which is 2 larger than the equilibrium overdrive of each transistor.211) VDD M4 r O4 v out M1 P I SS M2 +v in r O3 A −v in Figure 10. 2006] June 30. the circuit “rejects” input CM changes.cls v. differential changes at the input. the circuit responds to differential inputs. each of which is simply a common-emitter stage. and two identical loads. the tail node voltage of a differential pair remains constant and is thus considered a virtual ground node.. For small.58 Exercise Calculate the voltage gain from the differential input to node A. MOS differential pairs can steer the tail current with a differential input equal to p 2ISS =n Cox W=L.e. the input differential swing of a bipolar differential pair must remain below roughly VT . i. differential signals are more immune to common-mode noise. Compared with single-ended signals.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. A differential signal consists of two single-ended signals carried over two wires. p . Bipolar differential pairs exhibit a hyperbolic tangent input/output characteristic. vA . The tail current can be mostly steered to one side with a differential input of about 4VT .e. a tail current. 1 g m3 (10.7 Chapter Summary Single-ended signals are voltages measured with respect to ground. The transistor currents change in opposite directions if a differential input is applied.7 Chapter Summary 517 That is.. A differential pair consists of two identical transistors. 2g vout . r mP OP revealing that vA is indeed much less that vout . 2007 at 13:42 517 (1) Sec. The pair can then be decomposed into two half circuits. For small-signal operation. with the two components beginning from the same dc (common-mode) level and changing by equal and opposite amounts. 10.

cls v. 5. 10. Problems 1. Similarly. 10. MOS differential pairs can provide more or less linear characteristics depending on the choice of the device dimensions. assuming VA 1. The input transistors of a differential pair can be cascoded so as to achieve a higher voltage gain.60 at X and Y and determine their peak-to-peak swings and common-mode level. the loads can be cascoded to maximize the voltage gain. 10 Differential Ampliﬁers Unlike their bipolar counterparts. 10. The gain seen by the CM change normalized to the gain seen by the desired signal is called the common-mode rejection ration.I0 cos !t + I0 . In the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. corrupting the desired signal. Repeat Problem 4 for the circuit depicted in Fig. The differential output of a perfectly symmetric differential pair remains free from input CM changes. Compute this gain. Repeat Problem 1 for the circuit of Fig. Repeat Problem 1 for the stages shown in Fig.60. 10. I1 = I0 cos !t + I0 and I2 = . In the presence of asymmetries and a ﬁnite tail current source impedance.1. we can assume VCC is a small-signal “input” and determine the (small-signal) gain from VCC to Vout . . The circuit is called a differential pair with active load.59 4. Also. 2006] June 30. 2007 at 13:42 518 (1) 518 Chap. 2. To calculate the effect of ripple at the output of the circuit in Fig.61. Assume VA 1 and 0.59. Plot the waveforms VCC I1 X RC Y RC I2 Figure 10. 10. It is possible to replace the loads of a differential pair with a current mirror so as to provide a single-ended output while maintaining the original gain. a fraction of the input CM change appears as a differential component at the output. VCC RC Vout Q1 V in I EE Vb V in M1 RS RD Vout VDD V in VCC Q1 Vout I EE RS V in VDD M1 Vout (a) (b) (c) (d) Figure 10. plot the voltage at node P as a function of time.2(a). assuming RC 1 = RC 2 . 3.

Repeat Problem 4 for the topology shown in Fig. Assuming I1 = I0 cos !t + I0 and I2 = .65. Assume IT is constant.62 6.64.62. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. plot VX and VY as a function of time for the circuits illustrated in Fig. but assume I2 = . . 2007 at 13:42 519 (1) Sec.64 10.I0 cos !t + 0:8I0 . 10. 2006] June 30.V0 cos !t + V0 . 10. Assuming V1 = V0 cos !t + V0 and V2 = .I0 cos !t + I0 . Can X and Y be considered true differential signals? 9. Repeat Problem 4 for the topology shown in Fig. plot VP as a function of time for the circuits shown in Fig.63 8.61 VCC RC X I1 RC Y I2 Figure 10.cls v.7 Chapter Summary VCC R1 RC X I1 P RC Y I2 519 Figure 10. Repeat Problem 4. 10. VCC RC X I1 Y I2 IT RC RC X I1 IT VCC RC Y I2 RC RP X I1 Y I2 VCC RC RC X I1 Y I2 RP VCC RC (a) (b) (c) (d) Figure 10.63. 7. 10. VCC I1 X RC Vb Y RC I2 Figure 10. Assume I1 is constant.

What is the maximum allowable value of RC if Q1 must remain in the active region? 15. What is the maximum value of Gm ? At what value of Vin1 . What is the maximum allowable value of IEE if Q2 must remain in the active region? 16. the small-signal transconductance of Q2 falls as Vin1 . 14. compute Gm and plot the result as a function of Vin1 . IC 1 =IC 2 = 5. 12. determine the change in VX .58) and (10. 20. 2006] June 30. 10. (b) VCC rises by V . VY .12. Vin2 rises because IC 2 decreases. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.78). 17. 10. 10. (10. 10. Using Eq.7. Consider the circuit of Fig. (10.7. Repeat Problem 12. 10. Suppose the input differential signal applied to a bipolar differential pair must not change the transconductance (and hence the bias current) of each transistor by more than 10. and VX . What is the corresponding input differential voltage? With this voltage applied. Suppose IEE = 1 mA and RC = 800 in Fig. How do VX .212) From Eqs. determine the input difference at which the transconductance of Q2 drops by a factor of 2. VY change? 13. 10. 10.60). Neglecting the Early effect.12: . 21. Explain why we say the circuit “rejects” supply noise. 10 RC RC P V1 V2 (b) Differential Ampliﬁers RC RC P V1 V2 (c) RC P I1 R1 Figure 10. Vin2 . It is possible to deﬁne a differential transconductance for the bipolar differential pair of Fig. .I Gm = @@IC 1 . Vin2 contains a dc component of 30 mV. Explain what happens to the characteristics shown in Fig.9(b). Suppose in Fig. and VX . VC 2 : V in1 in2 (10.10 if (a) IEE is halved. RC = 500 . In Fig. 23. VCC rises by V . VY . Vin2 does Gm drop by a factor of two with respect to its maximum value? 22. IEE experiences a change of I . 2007 at 13:42 520 (1) 520 RC V1 V2 (a) Chap. 10. From Eq.9(a) and assume IEE = 1 mA.cls v.58). we can compute the small-signal voltage gain of the bipolar differential pair: out .12.9(a). Determine the region of operation of Q1 . 10. but assuming that RC 1 = RC 2 + R. Vout2 : in1 in2 (10.13 if the ambient temperature goes from 27 C to 100 C. With the aid of Eq.65 11. determine the maximum allowable input.58). In the circuit of Fig. In the circuit of Fig. how does IC 1 =IC 2 change if the temperature rises from 27 C to 100 C? 19. VY . (10. In the differential pair of Fig. or (c) RC is halved? 18. (10. What happens to the characteristics depicted in Fig. Neglect the Early effect.213) Determine the gain and compute its value if Vin1 . V Av = @@ VV 1 .

(10. 2007 at 13:42 521 (1) Sec. IEE = 1 mA and VA = 5 V.15 for the circuit shown in Fig. VA. The circuit of Fig.66. 10.215) Vin1 = V0 sin !t + VCM Vin2 = .p = 4 V. determine the time t1 at which one transistor carries 95 of the tail current. (a) If V0 = 2 mV.9 suggests that a differential pair can convert a sinusoid to a square wave. In Fig. Using a small-signal model and including the output resistance of the transistors. and VCC = 2:5 V. VCC Vout V in1 Q1 P I EE Q2 Vin2 Figure 10. 10.67.n = 5 V VA. Plot the output waveforms. If VA. The study in Example 10. where IEE = 2 mA.) VCC RC Vout V in1 Q1 P I EE Q2 Vin2 RC R EE Figure 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume (10.67 30. 2006] June 30. Repeat the small-signal analysis of Fig. 27.V0 sin !t + VCM .p = 4 V. . 10. 26.9.86 holds in the presence of the Early effect. Using the circuit parameters given in Problem 24.7 Chapter Summary 521 24. Explain why the output square wave becomes “sharper” as the input amplitude increases.66 28. Consider the circuit shown in Fig. 25. calculate the required tail current. plot the output waveforms (as a function of time). Calculate the voltage gain of the circuit. In Problem 25. 10. where VCM = 1 V denotes the input common-mode level. RC = 500 . estimate the slope of the output square waves for V0 = 80 mV or 160 mV if ! = 2 100 MHz. plot the output waveforms if V0 = 80 mV or 160 mV.68 must provide a gain of 50 with R1 = R2 = 5 k .214) (10. Note that the gain is independent of the tail current. In Example 10. 29. (First. prove that Eq. What value of R1 = R2 allows a voltage gain of 50? 31. prove that P is still a virtual ground.68.cls v. 10. IEE = 1 mA. (b) If V0 = 50 mV. 10.n = 5 V and VA.

You may need to compute the gain as Av = . . compute the differential voltage gain of each VCC RC Vout RC R2 Q4 V in1 Q2 Vin2 R1 Q1 P I EE R2 Q2 Vin2 (b) VCC R1 Q3 V in1 Q1 P I EE (c) VCC R1 R2 Q4 Vout V in1 Q1 P I EE (d) R2 Vout Q2 Q4 Vin2 Q3 Q2 Vin2 Figure 10. 10. 2006] June 30. Assuming perfect symmetry and VA stage depicted in Fig.68 32. 2007 at 13:42 522 (1) 522 X Q3 R1 Vout V in1 Q1 P I EE Q2 R2 Chap. Assuming perfect symmetry and VA = 1. compute the differential voltage gain of each stage depicted in Fig. 10 VCC Q4 Differential Ampliﬁers Vin2 Figure 10. Assuming perfect symmetry and VA 1.cls v. Consider the differential pair illustrated in Fig. 10.69. VCC R1 Q3 Vout V in1 Q1 P I EE (a) 1.Gm Rout in some cases.71.70.69 33.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) Under what condition does the gain become independent of the tail currents? This is an example of a very linear circuit because the gain does not vary with the input or output signal levels. 10. 34. (a) Determine the voltage gain.

differential inputs. (c) the gate oxide thickness is doubled. 2007 at 13:42 523 (1) Sec.73 and calls it a “differential ampliﬁer” because ID Vin1 . what is the required value of ISS ? 38. Repeat Example 10. .16 for a supply voltage of 2 V. Assuming M2 is off. 39. If n Cox = 100 A=V and W=L = 20=0:18.25(a). 10. ISS = 1 mA. prove that P is still a virtual ground for small. and RD = 1 k . Formulate the trade-off between VDD and W=L for a given output common-mode level. 10.n = 0:5 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 36. 40.71 35. Explain how the equilibrium overdrive voltage of a MOS differential pair varies as a function of the current density. What happens to the tail node voltage if (a) the width of M1 and M2 is doubled. 2006] June 30.70 VCC Q3 RC Vout V in1 Q1 RE Q2 Vin2 Q4 RC I EE I EE Figure 10. 10.72). Vin2 .cls v.24 must be designed for an equilibrium overdrive of 2 200 mV.24. Without using the small-signal model. Vin1 = 1:5 V and Vin2 = 0:3 V. 10. Explain which aspects of our differential signals and ampliﬁers this circuit violates. 37. 41.7 Chapter Summary VCC RC Vout RC RC Vout Q2 RE P RE R SS (a) 523 VCC RC V in1 Q1 Vin2 V in1 Q1 R1 RE P R2 Q2 RE R SS Vin2 (b) Figure 10.24. The MOS differential pair of Fig. 10. 10. In the MOS differential pair of Fig. A MOS differential pair contains a parasitic resistance tied between its tail node and ground (Fig. For a MOSFET. An adventurous student constructs the circuit shown in Fig. 42. VCM = 1 V. In Fig. What is the minimum allowable supply voltage if the transistors must remain in saturation? Assume VTH. (b) ISS is doubled. 10. determine a condition among the circuit parameters that guarantees operation of M1 in saturation. Consider the MOS differential pair of Fig. the “current density” can be deﬁned as the drain current divided by the device width for a given channel length.

(10. Assuming that the mobility of carriers falls at high temperatures.142). VD2 : in1 in2 (10.74 shows a differential pair employing such transistors. ID2 = ISS . (a) What similarities exist between this circuit and the standard MOS differential pair? (b) Calculate the equilibrium overdrive voltage of T1 and T2 . 10 VDD RD X V in1 I SS M1 M2 P R SS RD Y Vin2 Differential Ampliﬁers Figure 10. Explain what happens to the characteristics shown in Fig. (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 45.72 VDD RD Vout V in1 M1 Vin2 Figure 10. From Eq. (10.217) where is a proportionality factor. compute the small-signal transconductance of a MOS differential pair. Figure 10.cls v. Verify p that is result is equal to 2 times the equilibrium overdrive voltage. (b) ID1 = ISS =2. (c) At what value of Vin1 . (c) ISS and W=L are halved. Explain the signiﬁcance of these cases. 48.139) is always negative if the solution with the negative sign is considered. 10. .31 as the temperature rises. (10. and (c) ID1 = ISS . Vin2 does one transistor turn off? 49. 46.142). 10. Vin2 such that ID1 . VTH 3 .73 43. From Eq. 50. Examine Eq. Vin2 and determine its maximum value. 47.I Gm = @@V D1 . Prove that the right hand side of Eq.216) Plot the result as a function of Vin1 . Suppose a new type of MOS transistor has been invented that exhibits the following I-V characteristic: ID = VGS .134) for the following cases: (a) ID1 = 0. (10. determine the value of Vin1 . (b) the threshold voltage is halved. 2006] June 30. 2007 at 13:42 524 (1) 524 Chap. explain what happens to the characteristics of Fig. Vin2 at which the transconductance drops by a factor of 2. deﬁned as I . 44. Using the result obtained in Problem 46.31 if (a) the gate oxide thickness of the transistor is doubled. calculate the value of Vin1 .

(c) Add the results obtained in (a) and (b) with proper polarities. VDD RD X Vout M1 V in P I SS M2 Vb RD Y Figure 10.76 53.77.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.75 (a) Viewing M1 as a common-source stage degenerated by the impedance seen at the source of M2 . 2007 at 13:42 525 (1) Sec.75. how does it compare with the gain of differentially-driven pairs? 52.Gm Rout in some cases. 10. 2006] June 30. Assume perfect symmetry and 0. hoping to obtain differential outputs. 10. If the voltage gain is deﬁned as vX .cls v.74 51. Assume perfect symmetry and 0. calculate vY in terms of vin . . Calculate the differential voltage gain of the circuits depicted in Fig. Calculate the differential voltage gain of the circuits depicted in Fig. 10. 10. VDD M3 Vout V in1 M1 M2 I SS Vin2 M4 Vb M5 V in1 M3 Vout M1 M2 I SS I SS (a) (b) (c) VDD M4 M6 Vin2 V in1 Vb M3 R1 Vout M1 M2 R2 VDD M4 Vin2 Figure 10. vY =vin . Assume perfect symmetry but = 0 for simplicity. You may need to compute the gain as Av = .7 Chapter Summary VDD RD Vout V in1 T1 T2 I SS Vin2 RD 525 Figure 10. A student who has a single-ended voltage source constructs the circuit shown in Fig.76. (b) Viewing M1 as a source follower and M2 as a common-gate stage. calculate vX in terms of vin .

10 Differential Ampliﬁers VDD M3 Vout V in1 M1 R1 R2 R SS M2 Vin2 V in1 M4 Vb M3 M4 Vout M1 R SS M2 VDD RS M3 M4 Vout V in1 M1 R SS M2 VDD RS Vb Vin2 Vin2 (a) (b) (c) Figure 10. Repeat Problem 55 for the circuit shown in Fig.77 54. what is the minimum required Early voltage? 55. 10.37(a) must achieve a voltage gain of 4000.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.78 56. 10. VCC Vout Q3 Vb V in1 RP Q1 RP Q2 Q4 Vb Vin2 I EE Figure 10. 10. has appeared in the circuit of Fig. If Q1 -Q4 are identical and = 100.79 . RP .cls v.79. The cascode differential pair of Fig. 2006] June 30. a parasitic resistance. VCC Vout Q3 Vb V in1 Q1 RP Q2 Vin2 Q4 I EE Figure 10.78. 2007 at 13:42 526 (1) 526 Chap. Calculate the voltage gain. Due to a manufacturing error.

the student makes the modiﬁcation shown in Fig. (Hint: Av = . compute . If W=L = 20=0:18 for M1 -M4 and n Cox = 100 A=V2 . If n Cox = 100 A=V . Calculate the voltage gain of the circuit.1 . determine the minimum allowable Early voltage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.cls v. A student adventurously modiﬁes a CMOS telescopic cascode as shown in Fig. determine W=L1 = = W=L8 .40(a) must provide a voltage gain of 300.1 . Calculate the voltage gain of the degenerated pair depicted in Fig. Assuming 0. If Q1 -Q4 are identical and so are Q5 -Q8 .82.1 .81. Realizing that the circuit of Fig. p Cox = 50 A=V . determine the required tail current. 10. (Hint: .83. 2006] June 30.41(a) is designed for a voltage gain of 200 with a 2 2 tail current of 1 mA. 10. 10. The MOS cascode of Fig. 10.80.Gm Rout .) VCC Vout Q3 Vb V in1 Q1 Q2 Vin2 Q4 I EE Figure 10.) VCC Av = Vout Q3 Vb V in1 Q1 RS Q2 Vin2 Q4 Figure 10. Assume n = 2 p = 100 and VA.n = 2VA. 2007 at 13:42 527 (1) Sec.81 suffers from a low gain. 10. Calculate the voltage gain of this topology. and . 10. Assume = 0:1 V.Gm Rout .38 is to operate as an op amp having an open-loop gain of 800. where the PMOS cascode transistors are replaced with NMOS devices. p = 0:2 V 64. The MOS telescopic cascode of Fig. n = 0:1 V. 60.84. The telescopic cascode of Fig.p .80 58. 10. 61. Determine the voltage gain of the circuit depicted in Fig.81 59.7 Chapter Summary 527 57. Is this topology considered a telescopic cascode? 62. 63. 10. 10. A student has mistakenly used pnp cascode transistors in a differential pair as illustrated in Fig.

cls v. VTH eq: (10. The bipolar differential pair depicted in Fig.83 the voltage gain of the circuit. 2007 at 13:42 528 (1) 528 Chap.82 VCC V b3 Q7 V b2 Q5 Q3 V b1 V in1 Q1 Q2 Vin2 Q6 Vout Q4 Q8 I EE Figure 10.218) 67. each having a degeneration resistor equal to 2REE . 2006] June 30. + VGS . Consider the circuit of Fig. Prove RD ISS ACM = 2 . Now draw a vertical line of symmetry through the circuit and decompose it to two common-mode half circuits. prove that RC IC 0:02VA + VT : (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (Hint: the impedance seen looking into the source of M5 or M6 is not equal to 1=gmjjrO . 10.219) .175) still holds. Prove that Eq. (10. 66.43(a) and replace REE with two parallel resistors equal to 2REE places on the two sides of the current source. 10.) 65. 10 VCC Differential Ampliﬁers Q3 Vb Vout V in1 Q1 Q4 Q2 Vin2 I EE Figure 10. Compute the common-mode gain of the MOS differential pair shown in Fig. Assume = 0 for M1 and M2 but 6= 0 for M3 . 10.85 must exhibit a common-mode gain of less than 0.86.01. Assuming VA = 1 for Q1 and Q2 but VA 1 for Q3 .

10. gm rO 1. 10. 10.86 68. 71.7 Chapter Summary VDD M7 V b3 V b2 M5 M3 V b1 V in1 M1 M2 I SS M6 Vout M4 Vin2 M8 529 Figure 10. Calculate the common-mode gain of the circuit depicted in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Repeat Problem 68 for the circuits shown in Fig. 10. Compute the common-mode rejection ratio of the stages illustrated in Fig. VTH eq: denotes the equilibrium overdrive of M1 and M2 .Gm Rout . Assume 0. For simplicity. where VGS . 2007 at 13:42 529 (1) Sec.90 if W=L3 = N W=L4 . 69.cls v.84 VCC RC v out1 Q1 v CM Vb Q3 I EE Q2 RC v out2 Figure 10. 2006] June 30.85 VDD RD X V in1 Vb M1 M2 M3 RD Y Vin2 Figure 10. and use the relationship Av = . Neglect channel-length modulation. neglect channel-length modulation in M1 and M2 but not in other transistors. 70. .88.87. 10.89 and compare the results. Determine the small-signal gain vout =i1 in the circuit of Fig.

88 VDD RD v out1 V in1 M1 P M2 R D + ∆R D v out2 Vin2 RD v out1 V in1 M1 P M2 VDD R D + ∆R D v out2 Vin2 V b1 M3 V b2 V b3 M3 M4 (b) (a) Figure 10. calculate Vout before and after the change if (a) W=L3 = W=L4 .cls v. I1 changes from I0 to I0 +I and I2 from I0 to I0 . I . (b) W=L3 = 2W=L4 73. Consider the circuit of Fig.87 VDD V b1 M3 V in1 V b2 V b3 Vout M1 M2 M5 M6 Vin2 V in1 V b2 M4 V b3 V b1 M3 Vout M1 M2 M7 (b) VDD M5 M6 M4 Vin2 (a) Figure 10. Neglecting channel-length modulation. (b) Invoking symmetry.92. In the circuit shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.89 72. 10. Assume M1 and M2 are identical and so are M3 and M4 . 2007 at 13:42 530 (1) 530 Chap. 10 VDD V b1 M3 V in1 V b2 Vout M1 M2 M5 Vin2 M4 Differential Ampliﬁers Figure 10. (a) Neglecting channel-length modulation. . 10. 2006] June 30. determine the voltage at node Y . calculate the voltage at node N .91. where the inputs are tied to a common-mode level.

90 VDD M3 M4 Vout I1 I2 RL Figure 10.92 (c) What happens to the results obtained in (a) and (b) if VDD changes by a small amount V ? 74. what is the required Early voltage for the pnp transistors? 76. 77. 2007 at 13:42 531 (1) Sec. Determine the output impedance of the circuit shown in Fig. Repeat the analysis in Fig. Neglecting channel-length modulation. VDD M3 M4 Vout I1 I2 RL Figure 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.94 for a voltage gain of 100.cls v.91 M3 N M1 v CM I SS P Y M2 VDD M4 Figure 10. We wish to design the stage shown in Fig. 10.54. If VA. 2006] June 30. 10.93. Assume gm rO 1. 10.56 but by constructing a Norton equivalent for the input differential pair.7 Chapter Summary VDD M3 M4 Vout I1 RL 531 Figure 10. 10.n = 5 V. compute the small-signal gains vout =i1 and vout =i2 in Fig. .93 75.

Gm Rout . the gain of the circuit must change by less than 2 if the collector current of either transistor changes by 10. Design the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. The differential pair depicted in Fig. compute the voltage gain of the stage. 10 Differential Ampliﬁers Vout V in1 Q1 Q2 Vin2 I EE Figure 10.96 for a gain of 50 and a power budget of 1 mW. 81. 2007 at 13:42 532 (1) 532 VCC Q3 Q4 Chap. (Hint: a 10 change in IC leads to a 10 change in gm . 10. Design the circuit of Fig.6(a) must operate with an input common-mode level of 1. 80. Assuming VCC = 2:5 V and VA = 1. Design the bipolar differential pair of Fig. Assume VCC Vb Q3 V in1 Q1 Vout Q2 Vin2 Q4 I EE Figure 10. Design the circuit for maximum voltage gain and a power budget of 3 mW.95 must provide a gain of 5 and a power budget of 4 VCC RC Vout V in1 Q1 RE Q2 Vin2 RC I EE I EE Figure 10. 10.97 for a gain of 100 and a power budget of 1 mW.n = 6 V and VCC = 2:5 V. Assume .) 82.95 mW. The bipolar differential pair of Fig. 10. 10. Assume VCC = 2:5 V. design the circuit.cls v.94 78. Moreover. Assume VCC = 2:5 V and VA = 1. 2006] June 30.96 VA.2 V without driving the transistors into saturation. 83. Design Problems 79.6(a) for a voltage gain of 10 and a power budget of 2 mW. Using the result obtained in Problem 77 and the relationship Av = .

Design the telescopic cascode of Fig. Assume an (equilibrium) overdrive of 100 mV for the NMOS devices and 150 mV 2 2 for the PMOS devices. Design the MOS differential pair of Fig. Assume Q1 -Q4 are identical and so are Q5 -Q8 . 2007 at 13:42 533 (1) Sec.29 for a voltage gain of 5 and a power dissipation of 1 mW if the equilibrium overdrive must be at least 150 mV.98 must provide a gain of 40. VCC = 2:5 V. and VDD = 1:8 V. Design the MOS differential pair of Fig.n = 5 V.8 V. n Cox = 100 A=V . Design the MOS differential pair of Fig. 85.98 (equilibrium) overdrive for all of the transistors and a power dissipation of 2 mW. 10.97 84.7 Chapter Summary VCC Q3 R1 Vout V in1 Q1 P I EE Q2 Vin2 R2 Q4 533 Figure 10.1 . VA. and VDD = 1:8 V.38(a) for a voltage gain of 2000. and the power budget is 1 mW. VCC = 2:5 V.max = 0:3 V and a power budget of 3 mW. 10. and . design 2 the circuit. Also. n Cox = 100 A=V . 87. VTH. R1 = R2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VA. p Cox = 2 100 A=V . Assuming the same VDD V b1 M3 V in1 V b2 Vout M1 M2 M5 Vin2 M4 Figure 10.1 . and VDD = 1:8 V. and VCC = 2:5 V. p = 50. 10.p = 5 V.n = 10 V. Assume = 0. Also. Assume RD = 500 . Assume Q1 -Q4 are identical and determine the required Early voltage. and VDD = 1:8 V. What is the voltage gain of the resulting design? 86. 2006] June 30.37(a) for a voltage gain of 4000. 90. Also. n Cox = 100 A=V .41(a) for a voltage gain of 600 and a power budget of 4 mW. Assume n = 0:1 V. 88. 10. n Cox = 100 A=V2 . 10. 10. Select the value of RD to place the transistor at the edge of 2 triode region for an input common-mode level of 1 V.cls v. n = 100. 10. 10.29 for an equilibrium overdrive voltage of 100 mV and a power budget of 2 mW. n Cox = 100 A=V2 . If VDD = 1.n = 0:5 V. p Cox = 50 A=V .29 for Vin. 89. Assume = 0. Design the circuit of Fig. VA. The differential pair depicted in Fig. = 0. Design the telescopic cascode of Fig. p = 0:2 V. = 100. and the power budget is 2 mW.

2006] June 30. V b1 M3 Figure 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 V.2 = 10=0:18. where the input CM level is equal to 1.100 (a) Adjust the value of Vb so as to set the output CM level to 1. Design the circuit of Fig. assume IS. Consider the differential ampliﬁer shown in Fig.pnp = 3:5 V. use the MOS device models given in the Appendix I. 93. pnp = 50. n Cox = 2p Cox = 100 A=V .pnp = 8 10.16 A. 10.48 for a voltage gain of 200 and a power budget of 3 mW with a 2. 94. Assume W=L = 10 m=0:18 m for M1 -M6 . a nominal differential voltage gain of 5. Assume VA. Assume M1 operates at the edge of 2saturation if the input common-mode level is 1 V. VCC = 2. 2007 at 13:42 534 (1) 534 Chap. compute the minimum required for M3 . determine the required value of p . 10.5 V Vb Vout V in1 Q1 Q2 Vin2 Q4 1 mA I EE Figure 10. n = 0:5p = 0:1 V. 10.101 employs two current mirrors to establish the bias for the input and load devices.1 . The differential pair of Fig. Design the differential pair of Fig. and R=R = 2.99 budget of 2 mW. For bipolar transistors.n = 2VA. use an independent voltage source for one side and a voltage-dependent voltage source for the other. . 10 Differential Ampliﬁers 91. VTH. The input CM level is equal to 1.npn = 5 V. The differential ampliﬁer depicted in Fig. npn = 100.n = 0:5 V. Also.1 . Assume a power VDD RD v out1 V in1 M1 P M2 R D + ∆R D v out2 Vin2 n = 0:1 V. VA. 10. 92.100. Assume W=L1. and neglecting channel-length modulation in M1 and M2 . (b) Determine the small-signal differential gain of the circuit. VA. VDD = 1:8 V.npn = 5 10.99 must achieve a CMRR of 60 dB (= 100). 10.) (c) What happens to the output CM level and the gain if Vb varies by 10 mV? 95.0:4 V. IS. Assume M1 -M4 are identical and so are M5 -M8 .cls v.5 V. VTH.5-V supply. SPICE Problems In the following problems.16 A.54 for a voltage gain of 20 and a power budget of 1 mW with VDD = 1:8 V.p = . (Hint: to provide differential inputs.p .2 V. n Cox = 100 A=V2 .

Consider the circuit illustrated in Fig.cls v.7 Chapter Summary VDD = 1.102. 96.103. Assume an input CM level of 1 V and Vb = 1:5 V.5 V Q3 R1 Vout V in1 Q1 Q2 Vin2 R2 Q4 1 mA I EE Figure 10. W=L = 10 m=0:18 m for all of the transistors. VCC = 2. Assume a small dc drop across R1 and R2 . I1 so that the output CM level places M3 and M4 at the edge of .103 (a) Select the value of saturation. (c) Plot the differential input/output characteristic.102 (a) Select the input CM level to place Q1 and Q2 at the edge of saturation.8 V M7 M9 I1 Vb V in1 M1 1 mA M8 Vout M4 M2 I SS Vin2 M3 Figure 10.) (b) Determine the small-signal differential gain of the circuit.101 (a) Select W=L7 so as to set the output CM level to 1. 2007 at 13:42 535 (1) Sec.8 V M7 1 kΩ 535 M3 V in1 M4 Vout M1 M2 M5 Vin2 M6 Figure 10. VDD = 1.5 V. 97. In the differential ampliﬁer of Fig. 10. 10. 10. (Assume L7 = 0:18 m. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) Select the value of R1 (= R2 ) such that these resistors reduce the differential gain by no more than 20.

5 mA M1 -M4. 2006] June 30.8 V M4 Vout M2 I SS Vin2 Figure 10. W=L = 10 m=0:18 m for level of 1.104 (a) Determine the output dc level and explain why it is equal to VX / (b) Determine the small-signal gains vout =vin1 .2 V. (c) Determine the change in the output dc level if W4 changes by 5. 98. B. M3 X V in1 M1 0. In the circuit of Fig. 2001. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 10 Differential Ampliﬁers (b) Determine the small-signal differential gain. Assume an input CM VDD = 1. References 1. 2007 at 13:42 536 (1) 536 Chap. 10. vin2 and vX =vin1 . Razavi.104. vin2 . Design of Analog CMOS Integrated Circuits McGraw-Hill.

2006] June 30. From radar and television systems in the 1940s to gigahertz microprocessors today.1. Fundamental Concepts Bode’s Rules Association of Poles with Nodes Miller’s Theorem High−Frequency Models of Transistors Bipolar Model MOS Model Transit Frequency Frequency Response of Circuits CE/CS Stages CB/CG Stages Followers Cascode Stage Differential Pair 11.1(b) to represent the circuit’s behavior at all frequencies of interest. 11.1 General Considerations What do we mean by “frequency response?” Illustrated in Fig. 11. 11. the idea is to apply a sinusoid at the input of the circuit and observe the output while the input frequency is varied. As exempliﬁed by Fig.1 Fundamental Concepts 11. In this chapter. We may loosely call f1 the useful bandwidth of the circuit. the demand for pushing circuits to higher frequencies has required a solid understanding of their speed limitations.cls v. a critical task in the study of stability and frequency compensation (12).1 Explain why people’s voice over the phone sounds different from their voice in face-to-face conversation. we study the effects that limit the speed of transistors and circuits. The outline is shown below. Example 11. We plot the magnitude of the gain as in Fig. We also develop skills for deriving transfer functions of circuits.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the circuit may exhibit a high gain at low frequencies but a “roll-off” as the frequency increases. 2007 at 13:42 537 (1) 11 Frequency Response The need for operating circuits at increasingly higher speeds has always challenged designers. identifying topologies that better lend themselves to high-frequency operation.1(a). Before investigating the cause of this roll-off. We assume bipolar transistors remain in the active mode and MOSFETs in the saturation region.1(a). we must ask: why is frequency response important? The following examples illustrate the issue. 537 .

5 kHz f Figure 11. the way you hear your own voice is different from the way other people hear your voice. exhibiting the frequency response shown in Fig. the circuits are designed to cover the entire frequency range. when you speak and listen to your own voice simultaneously. On the other hand. your skull passes some frequencies more easily than others). Thus. it sounds somewhat different from the way you hear it directly when you speak.2 When you record your voice and listen to it. Exercise Whose voice does the phone system alter more. circuits 20 Hz (a) 20 kHz f 400 Hz (b) 3. Unfortunately. Since the frequency response of the path through your skull is different from that through the air (i.2(b).cls v. Since the phone suppresses frequencies above 3. Explain why? Solution During recording. (b) gain roll-off with frequency. your voice propagates through the air and reaches the audio recorder.. Exercise Explain what happens to your voice when you have a cold? . the phone system suffers from a limited bandwidth. men’s or women’s? Example 11. your voice propagates not only through the air but also from your mouth through your skull to your ear. 2007 at 13:42 538 (1) 538 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2(a)]. 2006] June 30. 11 Frequency Response Av Roll−Off f1 (a) (b) f Figure 11.5 kHz. 11.2 processing the voice must accommodate this frequency range. In high-quality audio systems. each person’s voice is altered. on the other hand. 11. Solution Human voice contains frequency components from 20 Hz to 20 kHz [Fig.e.1 (a) Conceptual test of frequency response.

At low frequencies. the impedance of C1 falls and the voltage divider consisting of R1 and C1 attenuates Vin to a greater extent.3(a) and (b) illustrate this effect for a high-bandwidth and low-bandwidth driver. the graphics card delivering the video signal to the display of a computer must provide at least 5 MHz of bandwidth.g. 11. In fact. consider the common-source stage illustrated in Fig. let us consider the low-pass ﬁlter depicted in Fig. At low frequencies.3 Video signals typically occupy a bandwidth of about 5 MHz.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 Fundamental Concepts 539 Example 11.) (a) (b) Figure 11. As a more interesting example. 11.5(a).4(a). 1=CL s. and (b) its frequency response. thus. The circuit therefore exhibits the behavior shown in Fig. 11. 11. Figures 11. respectively. CL . Explain what happens if the bandwidth of a video system is insufﬁcient. At high frequencies. CL “steals” some of the signal current and shunts it to ground.3 Exercise What happens if the display is scanned from top to bottom? What causes the gain roll-off in Fig. (The display is scanned from left to right.” yielding a fuzzy picture. remains high.4 (a) Simple low-pass ﬁlter. where a load capacitance. Vout = Vin . the “sharp” edges on a display become “soft. nearly zero. 11. from the small-signal equivalent . 2006] June 30. For example. on the other hand.1? As a simple example. This is because the circuit driving the display is not fast enough to abruptly change the contrast from. C1 is nearly open and the current through R1 Vout R1 V in C1 Vout f V in 1. e..4(b).cls v.0 Figure 11. the signal current produced by M1 prefers to ﬂow through RD because the impedance of CL . appears at the output. complete white to complete black from one pixel to the next. As the frequency increases. leading to a lower voltage swing at the output. 2007 at 13:42 539 (1) Sec. Solution With insufﬁcient bandwidth.

Fortunately. such signals can be viewed as a summation of many sinusoids with different frequencies (and phases). 11. the parallel impedance falls and so does the amplitude of 1 + !s 1 + !s z1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 11.2 The voltage gain therefore drops at high frequencies. circuit of Fig. as the frequency increases. That is.5(b) prove useful so long as the circuit remains linear and hence superposition can be applied. responses such as that in Fig.2 Relationship Between Transfer Function and Frequency Response We know from basic circuit theory that the transfer function of a circuit can be written as Vout . (b) small-signal model of the circuit.1) The reader may wonder why we use sinusoidal inputs in our study of frequency response.1.1 we note that RD and CL are in parallel and hence: Vout = . 2007 at 13:42 540 (1) 540 VDD RD Vout V in M1 CL V in Chap. 2006] June 30. Thus.5(b). After all. an ampliﬁer may sense a voice or video signal that bears no resemblance to sinusoids.gmVin RD jj C1 s : L (11.5 (a) CS stage with load capacitance. 11 Frequency Response Vout g V in m RD CL (a) (b) Figure 11. 11.

z2 H s = A0 .

1+ ! 1+ ! p1 p2 . s s .

.

we may write ! = 5 1010 rad/s = 27:96 GHz: Example 11. Note that f (in Hz) and ! (in radians per second) are related by a factor of 2 . (11. respectively. (11. 2 We use upper case letters for frequency-domain quantities (Laplace transforms) even though they denote small- signal values. we are primarily concerned with the former.3) where H j! is obtained by making the substitution s = j! . Called the “magnitude” and the “phase. If the input to the circuit is a sinusoid of the form xt = A cos2ft = A cos !t. In this chapter. The frequencies !zj and !pj represent the zeros and poles of the transfer function.” jH j! j and 6 H j! respectively reveal the frequency response of the circuit.4 Determine the transfer function and frequency response of the CS stage shown in Fig. 1 Channel-length modulation is neglected here.5(a). . 11. then the output can be yt = AjH j!j cos !t + 6 H j! . For example.2) expressed as where A0 denotes the low frequency gain because H s ! A0 as s ! 0.

11. For the highest performance. we have H s = Vout s = . 11.3-dB bandwidth of the circuit is equal to 1=RD CL (Fig. p Vout = gm RD : p Vin 2 (11. Derive a relationship between the gain. 11. Assume VA = 1. In a manner similar to the CS topology of Fig. the . the bandwidth is given by 1=RC CL .3-dB bandwidth. Vout V in −3−dB Bandwidth −3−dB Rolloff 1 R D CL ω Figure 11. we replace s = j! and compute the magnitude of the transfer function:3 Vout = p gm RD : (11. the gain begins at gm RD at low frequencies.7) 2 3 dB. and the power consumption by IC VCC .5) For a sinusoidal input.1 Fundamental Concepts 541 Solution From Eq.gm RD jj C1 s Vin L .5 Consider the common-emitter stage shown in Fig.6) 2 2 Vin RD CL !2 + 1 2 2 As expected. (11. and the power consumption of the circuit.4) (11.gmRD : = R C s+1 D L (11. we say the .6). 2006] June 30. 2007 at 13:42 541 (1) Sec. rolling off as RD CL ! 2 becomes comparable with unity. At ! = 1=RD CL .5(a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 11.1). we wish to maximize both the gain and the bandwidth (and hence the 3 The magnitude of the complex number Solution p a + jb is equal to a2 + b2 .cls v. Since 20 log 11.7. .6 Exercise Derive the above results if 6= 0. the low-frequency gain by gm RC = IC =VT RC .

10) = R C 1s + 1 : 1 1 1 (11. 11. 11 Frequency Response VCC RC Vout V in Q1 CL Figure 11.cls v. by immersing the circuit in liquid nitrogen (T around! = 77 K).4 (b) VCC but at the cost of limiting the voltage swings.9) Thus.8) (11.7 product of the two) and minimize the power dissipation.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4(a). In practice. 2006] June 30.9) becomes more complex for CS stages (Problem 15). Solution To obtain the transfer function.11) The frequency response is determined by replacing s with j! and computing the magnitude: jH s = j!j = p R C ! +1 2 2 2 1 1 : (11. but requiring that the user carry a tank . 2007 at 13:42 542 (1) 542 Chap. we view the circuit as a voltage divider and write H s = Vout s = 1 C1 s Vin C1 s + R1 1 (11.12) 4 For example. Exercise Derive the above results if VA 1. We therefore deﬁne a “ﬁgure of merit” as IC 1 Gain Bandwidth = VT RC RC CL Power Consumption IC VCC 1 = V 1V C : T CC L (11. or (c) the load capacitance. Equation (11. the load capacitance receives the greatest attention.6 Explain the relationship between the frequency response and step response of the simple lowpass ﬁlter shown in Fig. Example 11. the overall performance can be improved by lowering (a) the temperature.

exp R. At this point. an effect neglected in Bode’s approximation. the bandwidth drops and the step response becomes slower.) As ! passes each zero frequency. (A slope of 20 dB/dec simply means a tenfold change in H for a tenfold increase in frequency.8 11. we often utilize Bode’s rules (approximations) to construct jH j! j rapidly.8 plots this behavior. as R1 C1 increases.5(a).cls v.5) indicates a pole frequency of j!p1 j = R 1C : D L (11.1 Fundamental Concepts 543 The .7 Solution Equation (11.13) The relationship between (11. creating “fuzzy” edges. 2007 at 13:42 543 (1) Sec. the slope changes from zero to . the slope of jH j! j decreases by 20 dB/dec. 11. In contrast 5 Complex poles may result in sharp peaks in the frequency response. Bode’s rules for jH j! j are as follows: As ! passes each pole frequency. revealing that a narrow bandwidth results in a sluggish time response. Figure 11. Figure 11.12) and (11. This observation explains the effect seen in Fig. . Example 11.5 Construct the Bode plot of jH j! j for the CS stage depicted in Fig.13) is that. the slope of jH j! j increases by 20 dB/dec. 11.3 Bode’s Rules The task of obtaining jH j! j from H s and plotting the result is somewhat tedious. Exercise At what frequency does jH j fall by a factor of two? 11.0 R 1C 1 R 1C 1 Vout f (a) (b) t Figure 11.C ut: 1 1 (11.9 illustrates the result. The circuit’s response to a step of the form V0 ut is given by t Vout t = V0 1 . H 1.14) The magnitude thus begins at gm RD at low frequencies and remains ﬂat up to ! = j!p1 j. 2006] June 30.1.3-dB bandwidth is equal to 1=R1 C1 .20 dB/dec. For this reason.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. it spends some time at intermediate levels (shades of gray).3(b): since the signal cannot rapidly jump from low (white) to high (black).

9 log ω Exercise Construct the Bode plot for gm = 150 . Solution j!p1 j = R 1 : C S in (11. Assume = 0 VDD RD RS M1 C in CL Vout Example 11. for RD CL ! 2 1. 11. Determine the poles of the circuit shown in Fig. and CL = 100 fF.4 Association of Poles with Nodes The poles of a circuit’s transfer function play a central role in the frequency response. 2007 at 13:42 544 (1) 544 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The designer must therefore be able to identify the poles intuitively so as to determine which parts of the circuit appear as the “speed bottleneck. Applicable to many circuits. Equation (11.8 V in Figure 11. 11.1 .1 to the transfer function.15) .10 . Setting Vin to zero.5) reveals that the pole frequency is given by the inverse of the product of the total resistance seen between the output node and ground and the total capacitance seen between the output node and ground.6). As evident from Eq. RD = 2 k . Bode’s rule provides a good approximation. 11. this observation can be generalized as follows: if node j in the signal path exhibits a small-signal resistance of Rj to ground and a capacitance of Cj to ground.1. 2006] June 30. Thus.cls v.10.5(b). (11. 11 Frequency Response to Fig. V 20log out V in g m RD −2 0 dB e /d c ω p1 Figure 11.4 serves as a good example for identifying poles by inspection. the Bode approximation ignores the 3-dB roll-off at the pole frequency—but 2 2 it greatly simpliﬁes the algebra. we recognize that the gate of M1 sees a resistance of RS and a capacitance of Cin to ground.” The CS topology studied in Example 11. then it contributes a pole of magnitude Rj Cj .

we can readily write the magnitude of the transfer function as: gm RD Vout = q : Vin 2 2 1 + !2 =!p11 + !2 !p2 (11. Similarly. (11. Assume = 0. the “output pole” is given by j!p2 j = R 1C : D L (11.17) Exercise If !p1 = !p2 . 11.gm RD .cls v. at what frequency does the gain drop by 3 dB? Compute the poles of the circuit shown in Fig. VDD RD Vout RS M1 Vb CL Example 11. With Vin = 0. 2006] June 30.18) !p1 = .11 .1 Fundamental Concepts 545 We may call !p1 the “input pole” to indicate that it arises in the input network. the small-signal resistance seen at the source of yielding a pole at Solution M1 is given by RS jj1=gm. 2007 at 13:42 545 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.9 V in C in Figure 11.11. 11.16) Since the low-frequency gain of the circuit is equal to .

Exercise How do we choose the value of pole frequency? RD such that the output pole frequency is ten times the input .1 . The output pole is given by !p2 1 : RS jj g1 Cin m = RD CL .

19) (11. V2 = .21) . an approximation given by “Miller’s Theorem” can simplify the task in some cases. i. ZF . 11. we obtain Z1 = ZF V V1 V 1. (b) equivalent of (a) as obtained from Miller’s theorem. V1 . In general.) Thus. was originally conceived for another reason. V2 = V1 ZF Z1 V1 .13(a) must be equal to that drawn by Z1 in Fig. 11 Frequency Response The reader may wonder how the foregoing technique can be applied if a node is loaded with a “ﬂoating” capacitor.20) (11. thereby allowing association of one pole with each node. VDD RD CF V in RS M1 Vout Figure 11. 2007 at 13:42 546 (1) 546 Chap. and (2) the current injected to node 2 in Fig.1.13(b).13(a) must be equal to that injected by Z2 in Fig. Miller’s theorem is such a method. we cannot utilize this technique and must write the circuit’s equations and obtain the transfer function. ap1 ZF 2 1 2 V1 V2 Z1 V1 V2 Z2 (a) (b) Figure 11.13(b). In the late 1910s. Consider the general circuit shown in Fig. 11. 11. V2 : ZF Z2 Denoting the voltage gain from node 1 to node 2 by Av .12 Circuit with ﬂoating capacitor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2 (11. He then proposed an analysis that led to the theorem. 11. pears between nodes 1 and 2. 11. we make two observations: (1) the current drawn by ZF from node 1 in Fig.e. a capacitor whose other terminal is also connected to a node in the signal path (Fig. where the ﬂoating impedance. 2006] June 30.13(a). 11. However.12 make it desirable to obtain a method that “transforms” a ﬂoating capacitor to two grounded capacitors. 11. while ensuring all of the currents and voltages in the circuit remain unchanged.12).5 Miller’s Theorem Our above study and the example in Fig. 11. To determine Z1 and Z2 . (These requirements guarantee that the circuit does not “feel” the transformation. however. 11.cls v.13(b).. We wish to transform ZF to two grounded impedances as depicted in Fig. Miller’s theorem. John Miller had observed that parasitic capacitances appearing between the input and output of an ampliﬁer may drastically lower the input impedance.13 (a) General circuit including a ﬂoating impedance.

26) where the substitution Av = . A v (11. We say such a circuit suffers from “Miller multiplication” of the capacitor.24) prove extremely useful in analysis and design. (b) equivalent circuit as obtained from Miller’s theorem. CF V in −A 0 Vout −A 0 ∆ V V in CF ( 1 + A 0 ( −A 0 Vout CF ( 1 + 1 ( A0 ∆V (a) (b) Figure 11.FA 1 = 1 + A C s .A0 is made.22) and (11.cls v. A v = (11.25) (11. the results expressed by (11.22). Av when “seen” at node 1. 11.FA and v (11.24) Called Miller’s theorem. tied between the input and output of an inverting ampliﬁer [Fig. 2006] June 30. As an important example of Miller’s theorem. let us assume ZF is a single capacitor.23) (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. What type of impedance is Z1 ? The 1=s dependence suggests a capacitor of value 1 + A0 CF .22) suggests that the ﬂoating impedance is reduced by a factor of 1 . CF . 0 F v (11. Applying (11. The effect of CF at the output can be obtained from (11. (11.24): Z2 = ZF 1 1.. 2007 at 13:42 547 (1) Sec.1 Fundamental Concepts 547 Z = 1 . 2V 1 2 ZF : = 1 1. 11. we have Z Z1 = 1 .14 (a) Inverting circuit with ﬂoating capacitor. In particular.14(a)].27) .22) V Z2 = ZF V . In other words. a capacitor CF tied between the input and output of an inverting ampliﬁer with a gain of A0 raises the input capacitance by an amount equal to 1+ A0 CF . as if CF is “ampliﬁed” by a factor of 1 + A0 .

Suppose the input voltage in Fig.1 if A0 1. 1 1 + A CF s 0 (11. The Miller multiplication of capacitors can also be explained intuitively. the voltage across CF increases by 1 + A0 V . That is. 11.28) which is close to CF s. Figure 11.14(a) goes up by a small amount V . The output then goes down by A0 V . 1 .14(b) summarizes these results. requiring that the input provide a .

29) (11. it would experience only a voltage change of V and require less charge. The above study points to the utility of Miller’s theorem for conversion of ﬂoating capacitors to grounded capacitors.15(a). 2007 at 13:42 548 (1) 548 Chap. 2006] June 30. By contrast. Assume = 0. 11. m RD !in = R 1 C .gm RD .15 Noting that M1 and RD constitute an inverting ampliﬁer having a gain of .10 VDD RD Vout C out Figure 11. 11 Frequency Response proportional charge.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.30) Cout = 1 + g 1 CF . The following example demonstrates this principle.14(b) to write: Solution Cin = 1 + A0 CF = 1 + gmRD CF and (11. 11. we utilize the results in Fig. VDD RD CF V in RS M1 Vout V in RS M1 C in (a) (b) Example 11. if CF were not a ﬂoating capacitor and its right plate voltage did not change. Estimate the poles of the circuit shown in Fig.

we have: = R 1 + g1 R C S m D F S in (11.8. 11.33) and !out = R 1 D Cout = (11. From our study in Example 11. (11.31) thereby arriving at the topology depicted in Fig.32) (11.15(b).34) RD 1 + g 1 CF m RD .

1 : (11.35) .

we call the procedure in Example 11. we know that the existence of CF lowers the voltage gain from the gate of M1 to the output at high frequencies. 11. if A0 is expressed in terms of circuit parameters at the frequency of interest.0 ω Figure 11.e. We return to this issue in Section 11. even for the purpose of ﬁnding high-frequency poles. and (b) its frequency response.1. we say Miller effect raises the input capacitance of the circuit in Fig. i.1 . 11.3. As a simple example.16 (a) Simple high-pass ﬁlter. consider the high-pass ﬁlter shown in Fig. The reader may ﬁnd the above example somewhat inconsistent. 2007 at 13:42 549 (1) Sec.16(a).1 Fundamental Concepts 549 Exercise Calculate Cin if gm = 150 .36) (11.15(a) to 1 + gm RD CF . (11.22) can be interpreted as follows: an impedance tied between the input and output of an inverting ampliﬁer with a gain of Av is lowered by a factor of 1 + Av if seen at the input (with respect to ground). RD = 2 k . Vout s = R1 Vin R1 + C1 s 1 s = R R1 C1+ 1 . Miller’s theorem requires that the ﬂoating impedance and the voltage gain be computed at the same frequency whereas Example 11.10 the “Miller approximation. It is possible that capacitors reduce the gain at low frequencies as well.” Without this approximation. 11.37) Vout = p R1 C1 ! : 2 2 2 Vin R1 C1 !1 + 1 (11. 11. Owing to this inconsistency. where the voltage division between C1 and R1 yields Vout C1 v in R1 Vout 1 R 1C 1 (a) (b) V in 1.10 uses the low-frequency gain. and CF = 80 fF.cls v.38) . 1 C1 s and hence (11.. This reduction of impedance (hence increase in capacitance) is called “Miller effect. gm RD .4.6 General Frequency Response Our foregoing study indicates that capacitances in a circuit tend to lower the voltage gain at high frequencies. After all.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.” For example. application of Miller’s theorem would be no simpler than direct solution of the circuit’s equations. Another artifact of Miller’s approximation is that it may eliminate a zero of the transfer function. 2006] June 30. The general expression in Eq.

The low-frequency roll-off may prove undesirable. As seen from Eq.out = Cm L = 2 20 kHz. in practice we must choose even a larger capacitor if a lower attenuation is desired. . Similar to the high-pass ﬁlter of Fig. we set the corner frequency 1=Ri Ci to 2 20 Hz. of course. 2006] June 30. the response exhibits a roll-off as the frequency of operation falls below 1=R1 C1 . Determine the minimum required value of C1 and the maximum tolerable value of CL .37). and recognizing that the resistance seen from the output node to ground is equal to 1=gm . we have g !p. and R1 = 100 k . Here. 2007 at 13:42 550 (1) 550 Chap. 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Setting the pole frequency to the upper end of the audio range.16. Assume = 0. thus obtaining Solution Ci = 79:6 nF: (11.42) An efﬁcient driver. this roll-off arises because the zero of the transfer function occurs at the origin.38) reveals a 3-dB attenuation at ! = 1=Ri Ci .17 lishes a gate bias voltage equal to VDD for M1 . the source follower can tolerate a very large load capacitance (for the audio band).cls v. Exercise Repeat the above example if I1 and the width of M1 are halved. gm = 1=200 .11 Figure 11.41) and hence (11. VDD V in Ci Ri M1 Vout I1 CL Ri estab- Figure 11. CL = 39:8 nF: (11. Since Eq. The load capacitance creates a pole at the output node.40) (11.16(b). much to large to be integrated on a chip. and I1 deﬁnes the drain bias current. 11. The following example illustrates this point.17 depicts a source follower used in a high-quality audio ampliﬁer. the input network consisting of Ri and Ci attenuates the signal at low frequencies. 20 kHz. To ensure that audio components as low as 20 Hz experience a small attenuation. (11. lowering the gain at high frequencies. (11. 11 Frequency Response Plotted in Fig.39) This value is. Example 11.

Nonetheless. The coupling capacitor permits independent bias voltages VDD RD Y Ci V in M2 X I1 (a) VDD RD Ri M1 Vout V in P M2 M1 Vout I1 (b) Figure 11.18(a) illustrates an example. thereby maximizing the voltage gain of the CS stage (why?).g. to maximize the voltage gain. especially at low supply voltages. For example. Ci in the above audio example).19 Typical frequency response.19 shows a typical frequency response and the terminology used to refer to its H Midband Gain Midband ωL Figure 11.. many integrated circuits also employ capacitive coupling..18(b)] as well.18(a). 11.1 Fundamental Concepts 551 Why did we use capacitor Ci in the above example? Without Ci . we wish to set VP just above VGS 2 . Figure 11.cls v. ωH ω various attributes. the two stages are quite incompatible in terms of their bias points. In other words. necessitating capacitive coupling. 11. 200 mV. the gate of M2 must reside at a voltage of at least VGS 1 + VI 1 . To convince the reader that capacitive coupling proves essential in Fig. On the other hand. e. 2007 at 13:42 551 (1) Sec. where VI 1 denotes the minimum voltage required by I1 . if the necessary capacitor values are no more than a few picofarads. Ci isolates the bias conditions of the source follower from those of the preceding stage. 2006] June 30. VTH 2 . we consider the case of “direct coupling” [Fig. 11. We call !L the lower corner or lower “cut-off” frequency and !H the upper corner or upper cut-off frequency. Figure 11. and we would not need perform the above calculations. Chosen to accommodate the signal frequencies of interest.” . VY can be chosen relatively low (placing M2 near the triode region) to allow a large drop across RD .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Called a “coupling” capacitor.g. Since VGS1 + VI 1 may reach 600-700 mV.18 Cascade of CS stage and source follower with (a) capacitor coupling and (b) direct coupling. where a CS stage precedes the source follower. Capacitive coupling (also called “ac coupling”) is more common in discrete circuit design due to the large capacitor values required in many applications (e. the band between !L and !H is called the “midband range” and the corresponding gain the “midband gain. at nodes X and Y . Here. Ci allows the signal frequencies of interest to pass through the circuit while blocking the dc content of Vin . the circuit’s gain would not fall at low frequencies.

2007 at 13:42 552 (1) 552 Chap. C n B p Cµ B C je n+ C je rπ Cµ C vπ g vπ m rO E (a) E (b) Cµ B Cπ rπ vπ g vπ m rO C E (c) Figure 11. the operation of the transistor requires a (nonuniform) charge proﬁle in the base region to allow the diffusion of carriers toward the collector.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this effect is typically more signiﬁcant than the depletion region capacitance. this model is incomplete because the base-emitter junction exhibits another effect that must be taken into account. Unfortunately.20(b). (c) complete model accounting for base charge.20(c)]. proper operation does not begin until enough charge carriers enter the base region and accumulate so as to create the necessary proﬁle. Cb . Since Cb and Cje appear in parallel. . denoted by Cje . 11. (b) small-signal model with junction capacitances.cls v. The depletion region associated with the junctions6 gives rise to a capacitance between base and emitter.2. As explained in Chapter 4.1 High-Frequency Model of Bipolar Transistor Recall from Chapter 4 that the bipolar transistor consists of two pn junctions. We may then add these capacitances to the small-signal model to arrive at the representation shown in Fig. if the transistor is suddenly turned off. Similarly. The above phenomenon is quite similar to charging and discharging a capacitor: to change the collector current. It is therefore necessary to study these capacitances carefully.2 High-Frequency Models of Transistors The speed of many circuits is limited by the capacitances within each transistor. In other words. 2006] June 30. 11. we must change the base charge proﬁle by injecting or removing some electrons or holes. and another between base and collector. the charge carriers stored in the base must be removed for the collector current to drop to zero. 11 Frequency Response 11. both forward-biased and reversed-biased junctions contain a depletion region and hence a capacitance associated with it. 11. 11. Modeled by a second capacitor between the base and emitter.20 (a) Structure of bipolar transistor showing junction capacitances.20(a)]. if the transistor is suddenly turned on. denoted by C [Fig. they are lumped into one and denoted by C [Fig. 6 As mentioned in Chapter 4.

21(a)]. 2006] June 30.22(b). exhibiting a junction capacitance denoted by CCS .cls v. In modern integrated-circuit bipolar transistors. it is often helpful to ﬁrst draw the transistor capacitances on the circuit diagram. (c) device symbol with capacitances shown explicitly. 11.21(c). Example 11.21 (a) Structure of an integrated bipolar transistor. 11. The complete model is depicted in Fig. 11. We may therefore represent the transistor as shown in Fig. the bipolar transistor is fabricated atop a grounded substrate [Fig. and CCS are on the order of a few femtofarads for the smallest allowable devices. 11. Exercise Construct the small-signal equivalent circuit of the above cascode. 11. (b) small-signal model including collectorsubstrate capacitance. we add the three capacitances of each transistor as depicted in Fig. and then construct the small-signal equivalent circuit. We hereafter employ this model in our analysis.12 Identify all of the capacitances in the circuit shown in Fig. CCS 1 and C2 appear in parallel. VCC VCC RC Vout V b1 V in Q2 Q1 V in C π1 Vb C π2 C µ1 Q1 C CS1 Q2 C CS2 C µ2 RC Vout (a) (b) Figure 11. and so do C2 and CCS 2 .21(b).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 High-Frequency Models of Transistors 553 In integrated circuits. Cje . C . 2007 at 13:42 553 (1) Sec. . Interestingly. The collector-substrate junction remains reverse-biased (why?). simplify the result. 11.22(a).22 Solution From Fig.21(b). In the analysis of frequency response. C B E B Cπ rπ vπ g vπ m rO Cµ C C CS B Cπ E E (a) (b) (c) Cµ C C CS p n Substrate n+ C CS Figure 11. 11.

2. 11.23(b)]. 2007 at 13:42 554 (1) 554 Chap.25. 11. C2 n + C1 n + p −substrate (a) (b) Figure 11. Note that CSB 1 and CSB 2 are shorted to ac ground on both ends. 11. 11 Frequency Response 11.24 Overlap capacitance between gate and drain (or source). (b) partitioning of gate-channel capacitance between source and drain. respectively. We now study these capacitances in the device in greater detail.25(b)] before constructing the small-signal model.2 High-Frequency Model of MOSFET Our study of the MOSFET structure in Chapter 6 revealed several capacitive components. The ﬁrst component presents a modeling difﬁculty because the transistor model does not contain a “channel. but. We now construct the high-frequency model of the MOSFET. CGS (including the overlap component). CGD2 is shorted 7 As mentioned in Chapter 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11. in the saturation region. (2) the capacitance between the gate and drain (including the overlap component). The exact partitioning of this capacitance is beyond the scope of this book. and two associated with the reverse-biased source-bulk and drain-bulk junctions. 11.2. the MOSFET displays three prominent capacitances: one between the gate and the channel (called the “gate oxide capacitance” and given by WLCox ). 2006] June 30. Depicted in Fig. 11. this representation consists of: (1) the capacitance between the gate and source.23 (a) Structure of MOS device showing various capacitances. Illustrated in Fig.26(a).) As mentioned in Section 11. Example 11. Solution Adding the four capacitances of each device from Fig. this (symmetric) effect persists even if the MOSFET is off. these components arise from both the physical overlap of the gate with source/drain areas7 and the fringe ﬁeld lines between the edge of the gate and the top of the S/D regions. we arrive at the circuit in Fig. (We assume the bulk remains at ac ground.24. . Shown in Fig.cls v. C1 is about 2=3 of the gate-channel capacitance whereas C2 0. 11. CSB and CDB . (3) the junction capacitances between the source and bulk and the drain and bulk. Called the gatedrain or gate-source “overlap” capacitance. we often draw the capacitances on the transistor symbol [Fig.1.23(a). Two other capacitances in the MOSFET become critical in some circuits. n+ Figure 11. 11.26(b).13 Identify all of the capacitances in the circuit of Fig.25(a). the S/D areas protrude under the gate during fabrication.” We must therefore decompose this capacitance into one between the gate and the source and another between the gate and the drain [Fig.

3 Transit Frequency With various capacitances surrounding bipolar and MOS devices.26 “out. we mean the performance of the device by itself. A measure of the intrinsic speed of transistors8 is the “transit” or “cut-off” frequency. VDD C GS2 VDD M2 Vout V in M1 V in C GS1 C GD2 C GD1 M1 V in C DB1 C SB1 (a) (b) (c) C SB2 M2 C DB2 Vout C GD1 C SB2 VDD M2 Vout M1 C GS1 C DB1 + C DB2 + C GS2 C SB1 Figure 11. CDB 2 . (b) device symbol with capacitances shown explicitly. . The circuit therefore reduces to that in Fig. 11. and CGS 2 appear in parallel at the output node. 11. 2006] June 30. 8 By “intrinsic” speed.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. construct the small-signal equivalent circuit of the ampliﬁer. without any other limitations imposed or enhancements provided by the circuit.26(c). 11. fT .2 High-Frequency Models of Transistors C GD C GD 555 G C GS v GS S C SB g mv GS rO D C DB G C GS D C DB S C SB (a) (b) Figure 11. 2007 at 13:42 555 (1) Sec. Exercise Noting that M2 is a diode-connected device.cls v. is it possible to deﬁne a quantity that represents the ultimate speed of the transistor? Such a quantity would prove useful in comparing different types or generations of transistors as well as in predicting the performance of circuits incorporating the devices.25 (a) High-frequency model of MOSFET.2.” and CDB 1 .

27(a). the idea is to inject a sinusoidal current into I out ac GND I out ac GND Q1 I in Vin C in I in Vin C in M1 Figure 11. Zin . the speed of complex circuits using such devices is quite lower. For the bipolar device in Fig. 11 Frequency Response deﬁned as the frequency at which the small-signal current gain of the device falls to unity.45) 2: . Iout = gm r Iin r C s + 1 = r C s + 1: At the transit frequency. g !T Cm The transit frequency of MOSFETs is obtained in a similar fashion.49) Note that the collector-substrate or drain-bulk capacitance does not affect fT owing to the ac ground established at the output.43) = gmIin Zin . 11. We neglect C and CGD here (but take them into account in Problem 26).27 Conceptual setup for measurement of fT of transistors. the inevitable reduction of the supply voltage has reduced the gate-source overdive voltage from about 400 mV to 100 mV.14 .27 (without the biasing circuitry). By what factor has the fT of MOSFETs increased? Example 11. fin . We therefore write: (11. Of course.44) (11. Also. 2007 at 13:42 556 (1) 556 Chap. We note that. Modern bipolar and MOS transistors boast fT ’s above 100 GHz. is increased. !T = 2fT . the input capacitance of the device lowers the input impedance. and hence the input voltage Vin = Iin Zin and the output current. the magnitude of the current gain falls to unity: 2 2 2 r C !T = 2 (11. The minimum channel length of MOSFETs has been scaled from 1 m in the late 1980s to 65 nm today.47) That is. Illustrated in Fig. 2006] June 30. as fin increases. Zin = C1 s jjr : Since Iout (11.1 (11. 11.48) g g 2fT Cm or C m : GS (11.46) (11. the base or gate and measure the resulting collector or drain current while the input frequency.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

if n = 400 cm2 =(Vs). we prescribe the following steps: 1. 5. 6. Speciﬁcally. Determine which capacitors impact the low-frequency region of the response and compute the low-frequency cut-off.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. as studied in Chapter 12. For example. Calculate the midband gain by replacing the above capacitors with short circuits while still neglecting the transistor capacitances.g..9 Bode’s approximation simpliﬁes the task of plotting the frequency response if the poles and zeros are known. Determine the high-frequency poles and zeros by inspection or by computing the transfer function. Miller’s theorem may prove useful here. VTH : 2 L2 (11. 2. the transistor capacitances can be neglected as they typically impact only the high-frequency region.50) Thus. In many cases. 4.3 Analysis Procedure 557 Solution It can proved (Problem 28) that 2fT = 3 n VGS . Noting ac grounds (e.3 Analysis Procedure We have thus far seen a number of concepts and tools that help us study the frequency response of circuits. it is possible to associate a pole with each node in the signal path. the transit frequency has increased by approximately a factor of 59. 11. Bipolar and MOS devices exhibit various capacitances that limit the speed of circuits. the supply voltage or constant bias voltages). merge the capacitors that are in parallel and omit those that play no role in the circuit. 9 In a more general case.cls v. we have observed that: The frequency response refers to the magnitude of the transfer function of a system. In order to methodically analyze the frequency response of various circuits. the frequency response also includes the phase of the transfer function. Miller’s theorem proves helpful in decomposing ﬂoating capacitors into grounded elements. . Exercise Determine the fT if the channel length is scaled down to 45 nm but the mobility degrades to 300 cm2 =(Vs). 3. Identify and add to the circuit the capacitances contributed by each transistor. then 65-nm devices having an overdrive of 100 mV exhibit an fT of 226 GHz. 11. 2007 at 13:42 557 (1) Sec. 2006] June 30. Plot the frequency response using Bode’s rules or exact calculations. In this calculation. We now apply this procedure to various ampliﬁer topologies.

2006] June 30. 1=Cb s.55) Figure 11. We write Vout =Vin = Vout =VX VX =Vin .min : (11. Thus. this network attenuates the low frequencies.4. in parallel with RS in the midband gain expression: Vout s = .52) Similar to the high-pass ﬁlter of Fig. (b) effect of bypassed degeneration.1 Low-Frequency Response As mentioned in Section 11. we place a “bypass” capacitor in parallel with RS [Fig. the gain of ampliﬁers may fall at low frequencies due to certain capacitors in the signal path. Vout =VX = . neglect channel-length modulation. Let us consider a general CS stage with its input bias network and an input coupling capacitor [Fig. the transistor capacitances VDD R1 X V in Ci M1 R2 RS V in RD Vout Ci R1 X M1 R2 RS Cb VDD RD Vout g m RD 1 + g m RS 1 R SCb (a) (b) 1 + g m RS R SCb (c) Vout VX g m RD ω Figure 11.RD VX RS jj C1 s + g1 b m . 2007 at 13:42 558 (1) 558 Chap.cls v. 11.51) (11. the stage operates as a degenerated CS ampliﬁer.16. negligibly affect the frequency response. dictating that the lower cut-off be chosen below the lowest signal frequency. 11.gmRD RS Cb s + 1 : = R C s+g R +1 S b m S (11. leaving only Ci as the frequency-dependent component. 11. At frequencies well below the zero.54) (11.53) In applications demanding a greater midband gain. 11 Frequency Response 11.RD =RS + 1=gm and VX s = R1 jjR2 Vin R1 jjR2 + C1s i R1 jjR2 Ci s : = R jjR C s + 1 1 2 i (11.min (e. fsig.6. and at frequencies well above . we place its impedance.28 (a) CS stage with input coupling capacitor.28(c) shows the Bode plot of the frequency response in this case. To quantify the role of Cb ..g.28(a)]. and note that both R1 and R2 are tied between X and ac ground.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.28(b)] so as to remove the effect of degeneration at midband frequencies. 20 Hz in audio applications): 1 2 R1 jjR2 Ci fsig.4 Frequency Response of CE and CS Stages 11.1. At low frequencies. (c) frequency response with bypassed degeneration.

it is not added deliberately.29(b).cls v.10 and can be reduced to one if Vin . RS and r are replaced with their Thevenin equivalent [Fig. 11. we now study the high-frequency response. 11.29(c)].29 (a) CE and CS stages. 11. (c) small-signal equivalents. the circuit experiences no degeneration. 11.2 High-Frequency Response Consider the CE and CS ampliﬁers shown in Fig. the pole frequency must be chosen quite smaller than the lowest signal frequency of interest. 10 The Early effect and channel-length modulation are neglected here.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. where the source-bulk capacitance of M1 is grounded on both ends. With this uniﬁed model. i.4. VCC VCC RL V in RS Q1 Vout V in RS M1 RL Vout V in RS Cπ Q1 C CS VDD RL Cµ Vout V in C GS C SB (a) (b) VDD RL C GD M1 Vout C DB Cµ V in RS Vout Cπ rπ vπ g Vπ m C CS RL V in RS C GD Vout C GS v GS g mV GS C DB RL (c) C XY R Thev X V Thev C in VX Y g mV X C out RL Vout (d) Figure 11. .4 Frequency Response of CE and CS Stages 559 the pole. 2006] June 30. ﬁrst applying Miller’s approximation to develop insight and then performing an accurate analysis to arrive at more general results. The small-signal equivalents of these circuits differ by only r [Fig.e. 2007 at 13:42 559 (1) Sec. In practice. 11.29(a). Thus.29(d)]. we arrive at the complete circuits depicted in Fig. where RS may represent the output impedance of the preceding stage. 11. The above analysis can also be applied to a CE stage. Note that the output resistance of each transistor would simply appear in parallel with RL . RS r and hence RThev RS . Identifying the capacitances of Q1 and M1 . (d) uniﬁed model of both circuits. Both types exhibit low-frequency rolloff due to the input coupling capacitor and the degeneration bypass capacitor. (b) inclusion of transistor capacitances..

we can decompose CXY into two grounded components (Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 560 (1) 560 Chap.10.cls v. However.3 Use of Miller’s Theorem With CXY tied between two ﬂoating nodes. following Miller’s approximation as in Example 11. we cannot simply associate one pole with each node.30): CX = 1 + gm RL CXY CY = 1 + g 1 CXY : m RL . 11. 11 Frequency Response 11. 2006] June 30.4.

57) Now.56) (11. each node sees a resistance and capacitances only to ground. (11. we write 1 Thev Cin + 1 + gm RL CXY . In accordance with our notations in Section 11.1.

C = 100 fF. R Thev V Thev CX C in X vX Y g mv X C out CY RL Vout CE Stage rπ V Thev = V in r π + RS R Thev = R S r π CS Stage V Thev = V in R Thev = R S C X = C GD ( 1 + g m R L ( 1 ( C Y = C GD ( 1 + g m RL CX = C µ ( 1 + g m RL ( 1 ( CY = C µ ( 1 + g m RL Figure 11.29(a).59) m L If gm RL 1. the base-emitter or gate-source capacitance. The output pole is roughly determined by the load resistance.in j = R (11. 11. C = 20 fF. = 100.15 Solution = 2:6 k . Fig. RS = 200 .58) (11. (11. and the basecollector or gate-drain capacitance. 11. and CCS = 30 fF. The input pole is approximately given by the source resistance. the collector-substrate or drain-bulk capacitance. Which node appears as the speed bottleneck (limits the bandwidth)? (b) Is it possible to choose RL such that the output pole limits the bandwidth? (a) Since r Example 11.out j = RL Cout + 1 + g R CXY j!p.30 Parameters in uniﬁed model of CE and CS stages with Miller’s approximation.59) thus . and the Miller multiplication of the base-collector or gate-drain capacitance. we have RThev = 186 .58) and (11. In the CE stage of Fig. The intuition gained from the application of Miller’s theorem proves invaluable. IC = 1 mA. the capacitance at the output node is simply equal to Cout + CXY .30 and Eqs. (a) Calculate the input and output poles if RL = 2 k . 1 1 : j!p. The Miller multiplication makes it undesirable to have a high gain in the circuit.

63) With the values assumed in this example.4 Frequency Response of CE and CS Stages 561 give j!p.62) 1. the student uses a MOSFET half as wide as that in the original design.in j !p. (b) We must seek such a value of RL that yields j!p.61) We observe that the Miller effect multiplies C by a factor of 78.in j = 2 516 MHz j!p. then we have CCS + C . 11. Solution Both the width and the bias current of the transistor are halved.30 and Eqs. determine the gain and the poles of the circuit. Exercise Repeat the above example if IC = 2 mA and C = 180 fF. (11. Assuming that the bias current is also halved. gm RL .60) (11. and so is its transconductance (why?). 11. gm RS jjr C RL RS jjr C : (11. As a result. the input pole remains the speed bottleneck here. implying that no solution exists. Thus.16 An electrical engineering student designs the CS stage of Fig.58) and (11. 2007 at 13:42 561 (1) Sec. making its contribution much greater than that of C . in the layout phase.out j = 2 1:59 GHz: (11. Reducing the transistor width by a factor of two also lowers all of the capacitances by the same factor. Unfortunately. is therefore halved. From Fig. the left-hand side is negative.out j: 1 RS jjr C + 1 + gmRL C If gm RL 1 : RL CCS + 1 + g 1 C R m L (11.59).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we can express the poles as 1 R in RS 2 + 1 + gm2 L CXY 2 . The small-signal gain. Example 11. 2006] June 30. The reader can prove that this holds even if gm RL is not much greater than unity. the input pole limits the bandwidth. 11.29(a) for a certain lowfrequency gain and high-frequency response.cls v.

1 CXY . j!p.out j = C out + 1 + 2 RL 2 g R 2 j!p.in j = C .

gm .in has risen in magnitude by more than a factor of two. the gain is halved and the bandwidth is roughly doubled.65) m L where Cin . suggesting that the gain-bandwidth product is approximately constant. We observe that !p. CXY and Cout denote the parameters corresponding to the original device width.64) (11. . In other words. (11. and !p.out by approximately a factor of two (if gm RL 2).

At Node X : Vout .67): .4 Direct Analysis The use of Miller’s theorem in the previous section provides a quick and intuitive perspective of the performance. The circuit of Fig.4. That is. we must carry out a more accurate analysis so as to understand the limitations of Miller’s approximation in this case.29(d) contains two nodes and can therefore be solved by writing two KCLs. 2007 at 13:42 562 (1) 562 Chap. However.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vout CXY s = gm VX + Vout R + Cout s : L We compute VX from (11. 11 Frequency Response Exercise What happens if both the width and the bias current are twice their nominal values? 11. 2006] June 30. 11. VX CXY s = VX Cin s + VXR VThev At Node Y : VX .11 .cls v.

Thev 1 (11.66) (11. m and substitute the result in (11.68) Vout CXY s . CXY s + Cin s + R Thev It follows that .66) to arrive at (11.67) 1 CXY s + R + Cout s VX = Vout C s L g XY .

11.72) Note from Fig.70) a = RThev RL Cin CXY + Cout CXY + Cin Cout b = 1 + gmRL CXY RThev + RThev Cin + RL CXY + Cout : (11.71) (11.69) Vout CXY s . (11.70) must be multiplied by r =RS + r to obtain Vout =Vin —without affecting the location of the poles and the zero. where (11.73) . (11. Let us examine the above results carefully. gm L + Cout s Vout = . 1 CXY s + R1 CXY s .VThev : R Thev (11.30 that for a CE stage. The transfer function exhibits a zero at !z = Cgm : XY 11 Recall that we denote frequency-domain quantities with upper-case letters. gm RL VThev s = as2 + bs + 1 .

we ﬁrst make an interesting observation in regards to the quadratic denominator: if the poles are given by !p1 and !p2 .e.12 As expected. the system contains two poles given by the values of s that force the denominator to zero.) Since CXY (i. 2006] June 30. We can solve the quadratic as2 + bs + 1 = 0 to determine the poles but the results provide little insight. Instead.cls v. 11..4 Frequency Response of CE and CS Stages 563 (The Miller approximation fails to predict this zero. the zero typically appears at very high frequencies and hence is unimportant. the base-collector or the gate-drain overlap capacitance) is relatively small. we can write . 2007 at 13:42 563 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

s .

s as + bs + 1 = ! + 1 ! + 1 p1 .

72). simplifying the result as illustrated in Fig. this zero does become problematic in the internal circuitry of op amps. (11. we recognize from (11.76) that b j!p2 j = a (11. 11. and CSB 2 do not affect the circuit (why?).79) R R R XY = 1 + gm RL CXYC Thev + +Thev Cin ++ LCC + Cout : RThev RL in CXY Cout CXY Cin out Example 11. !p11 + !p21 !p11 .31(c). Noting that CSB 1 . we add the remaining capacitances as depicted in Fig.17 Using the dominant-pole approximation. 11. . 1 p2 1 2 s 2 (11. 11.78) (11. b = !1 .77) does reveal the Miller effect of CXY but it also contains the additional term RL CXY + Cout [which is close to the output time constant predicted by (11. CGS 2 . !p2 .76) j!p1 j = 1 + g R C R + R1 C + R C + C : m L XY Thev Thev in L XY out (11.31(b).59)].75) = ! ! + ! + ! s + 1: p1 p2 p1 p2 Now suppose one pole is much farther from the origin than the other: !p2 !p1 . i.e.31(a). where Solution Cin = CGS1 CXY = CGD1 Cout = CDB1 + CGD2 + CDB2 : (11. To determine the “nondominant” pole. .75) and (11.77) How does this result compare with that obtained using the Miller approximation? Equation (11. (This is called the “dominant pole” approximation to emphasize that !p1 dominates the frequency response).74) (11. p1 and from (11.80) (11. Assume both transistors operate in saturation and 6= 0.81) (11. .. .82) 12 As explained in more advanced courses. Then. compute the poles of the circuit shown in Fig.

In the CS stage of Fig.31 It follows from (11.10 s. (11.1 .in j = 2 571 MHz j!p. gm = 150 . and RL = 2 k . we have RS = 200 .59) yield j!p.83) (11.20 s. 11.77) and (11. (c) the dominant-pole approximation.85) (11. (11.84) Exercise Repeat the above example if 6= 0. Eqs. Also. 2007 at 13:42 564 (1) 564 C SB2 M2 VDD Vb V in RS M1 M2 Vout V in RS M1 C GS1 C DB1 C GD2 C GD1 C DB2 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (11.out j = 2 428 MHz: (b) The transfer function in Eq. (a) With gm RL Example 11.2 and b = 6:39 10.58) and (11. CGS = 250 fF. Thus.18 Solution = 13:3. Plot the frequency response with the aid of (a) Miller’s approximation. CDB = 100 fF.88) j!p1 j = 2 264 MHz j!p2 j = 2 4:53 GHz: .79) that !p1 1 + g r jjr C R + R1 C + r jjr C + C m1 O1 O2 XY S S in O1 O2 XY out 1 + gm1rO1 jjrO2 CXY RS + RS Cin + rO1 jjrO2 CXY + Cout : !p2 RS rO1 jjrO2 Cin CXY + Cout CXY + Cin Cout (11. (b) the exact transfer function. = 0. CGD = 80 fF.70) gives a zero at gm =CGD a = 2:12 10.86) = 2 13:3 GHz).cls v. (11.29(a).87) (11. 11 Frequency Response Vout V in RS C XY Vout M1 C in C out r O1 r O2 (a) (b) (c) Figure 11. 2006] June 30.

From Eqs.79). Miller’s Approx.90) 13 and the .32 plots the results.4 Frequency Response of CE and CS Stages 565 Note the large error in the values predicted by Miller’s approximation. 2007 at 13:42 565 (1) Sec. The low-frequency gain is equal to 22 dB bandwidth predicted by the exact equation is around 250 MHz.cls v.32 Exercise Repeat the above example if the device width (and hence its capacitances) and the bias current are halved. 13 The large discrepancy between more advanced courses.outj and j!p2 j results from an effect called “pole splitting” and studied in . (11. This error arises because we have multiplied CGD by the midband gain 1 + gm RL rather than the gain at high frequencies.5 Input Impedance The high-frequency input impedances of the CE and CS ampliﬁers determine the ease with which these circuits can be driven by other stages. 2006] June 30.13 (c) The results obtained in part (b) predict that the dominant-pole approximation produces relatively accurate results as the two poles are quite far apart. 11. we have j!p1 j = 2 249 MHz j!p2 j = 2 4:79 GHz: Figure 11.4. Exact Eq. j!p.89) (11. (11. 20 10 0 −10 −20 −30 7 10 10 8 10 Frequency (Hz) 9 10 10 Figure 11.77) and (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Our foregoing analysis of the frequency response and particularly the Miller approximation readily yield this impedance. 11.3-dB 30 Magnitude of Transfer Function (dB) Dominant−Pole Appr.

the input impedance of a CE stage consists of two parallel components: C + 1 + gm RD C and r .34(a). current of Q1 and Vb is chosen to ensure operation in the forward active region (Vb is less than the collector bias voltage). 11.14 That is. 2007 at 13:42 566 (1) 566 Chap. 11. the use of capacitive coupling leads to low-frequency roll-off in CB and CG ampliﬁers. How large should Ci be? Since Ci appears in series with RS . VCC Cµ Cπ Z in (a) Figure 11. (b) resulting frequency response.34 (a) CB stage with input capacitor coupling.33(a).cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the Miller effect may substantially lower the input impedance at high frequencies. 11.1 Low-Frequency Response As with CE and CS stages. where I1 deﬁnes the bias VCC RC Vout Q1 V in RS Ci I1 Vb Vout V in RD RS + 1 gm gm (1 + g m RS ( Ci (b) ω (a) Figure 11. the output impedance of the preceding stage (denoted by RS ) is excluded. 11 Frequency Response As illustrated in Fig. we 14 In calculation of the input impedance. 2006] June 30.5. Consider the CB circuit depicted in Fig. the MOS counterpart exhibits an input impedance given by (11.5 Frequency Response of CB and CG Stages 11. .92) With a high voltage gain.33 Input impedance of (a) CE and (b) CS stages.91) Zin C + 1 + 1 R C s : gm D GD GS (11. VDD C GD RD M1 C CS Z in C GS RC Q1 C DB (b) Zin C + 1 + 1 R C s jjr : gm D Similarly.

1 + 1=gm Cs = 1 + ggm RC Cis + g : RS i m m Equation (11. where rO = 1 and the transistor capacitances are VCC RC C CS Y Q1 V in RS X (a) (b) VDD RD Vout Vout C DB Y C GD M1 V in RS X C SB Vb C GS Cµ Vb Cπ Figure 11. 2007 at 13:42 567 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. From another perspective. 11. and so do CGD and CDB of M1 . we note that (1) C and CGS + CSB go to ground.35. included. avoiding Miller effect. 11. with all of the capacitances seeing ground at one of their terminals.94) Vout s = RC Vin RS + Ci s. 2006] June 30. Since Vb is at ac ground. yielding j!p. revealing a pole at j!p j = 1 + ggmR C m S i (11. and write (11.93) implies that the signal does not “feel” the effect of Ci if jCi s. The high-frequency response of these circuits does not suffer from Miller effect.cls v.1 j RS + 1=gm. 11.5. the total resistance seen to ground is given by RS jj1=gm . we can readily associate one pole with each node. RC =RS the resulting transfer function as + 1=gm.1 in the midband gain expression. (11.X j = . Consider the stages shown in Fig. Eq. (3) no capacitance appears between the input and output networks.95) and suggesting that this pole must remain quite lower than the minimum signal frequency of interest.5 Frequency Response of CB and CG Stages 567 replace RS with RS + Ci s. 11.34(b). At node X . In fact. These two conditions are equivalent. (2) CCS and C of Q1 appear in parallel to ground.35 (a) CB and (b) CG stages including transistor capacitances.93) (11.2 High-Frequency Response We know from Chapters 5 and 7 that CB and CG stages exhibit a relatively low input impedance ( 1=gm ). an important advantage in some cases.94) yields the response shown in Fig.

j!p.97) . at Y . L Y (11. Similarly. where CX 1 . RS jj g1 CX m (11.Y j = R 1C .96) = C or CGS + CSB .

36(b). The input pole is thus given by Solution j!p.36 Noting that CGD2 and CSB 2 play no role in the circuit. 11 Frequency Response where CY = C + CCS or CGD + CDB . we add the device capacitances as depicted in Fig. 11.36(a).cls v.15 Compute the poles of the circuit shown in Fig. For this reason.19 V in X C SB1 + C GS1 (a) (b) Figure 11. the input pole of the CB/CG stage rarely creates a speed bottleneck. 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.X j = . C SB2 VDD M2 Vout RS M1 Vb V in RS Y M1 Vb VDD M2 Vout C DB1 + C GD1 + C GS2 + C DB2 Example 11. It is interesting to note that the “input” pole magnitude is on the order of the fT of the transistor: CX is equal to C or roughly equal to CGS while the resistance seen to ground is less than 1=gm. Assume = 0. 2006] June 30. 2007 at 13:42 568 (1) 568 Chap.

cellphones). its gate is connected to a The CS stage of Example 11..98) m1 Since the small-signal resistance at the output node is equal to 1=gm2 .e. Example 11.18 is reconﬁgured to a common-gate ampliﬁer (with RS tied to the source of the transistor).20 . where the input capacitance becomes undesirable. 15 One exception is encountered in radio-frequency circuits (e. we have 1 : j!p.. Plot the frequency response of the circuit.99) Exercise Repeat the above example if constant voltage. M2 operates as a current source. RS jj g 1 1 CSB1 + CGD1 : (11.Y j = 1 CDB1 + CGD1 + CGS2 + CDB2 g m2 (11.g. i.

more than a factor of two lower than that of the CS stage. (11.16 we obtain from Eqs. the low-frequency gain is now equal to RD =RS +1=gm = 5:7. 2006] June 30.X j = 2 5:31 GHz j!p. limits the bandwidth.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 569 (1) Sec.Y j = 2 442 MHz: With no Miller effect. The output pole.3-dB bandwidth is around 450 MHz.37 plots the result. 11.11 and that of CE/CS stages. the junction capacitances quite equal. CSB = CDB .6 Frequency Response of Followers The low-frequency response of followers is similar to that studied in Example 11.96) and (11.cls v. We thus study the high-frequency behavior here. 11. Also.37 Exercise Repeat the above example if the CG ampliﬁer drives a load capacitance of 150 fF. CSB and CDB sustain different reverse bias voltages and are therefore not . 20 Magnitude of Frequency Response (dB) 15 10 5 0 −5 −10 −15 −20 6 10 7 8 9 10 10 10 Frequency (Hz) 10 10 Figure 11. The lowfrequency gain is equal to 15 dB 5:7 and the .101) j!p. In Chapters 5 and 7. the input pole has dramatically risen in magnitude.6 Frequency Response of Followers 569 Solution With the values given in Example 11.18 and noting that (11. we noted that emitter and source followers provide a high input impedance and a relatively low output impedance while suffering from a sub-unity (positive) 16 In reality.97).100) (11. Figure 11. however.

38 (a) Emitter follower and (b) source follower including transistor capacitances. 2006] June 30. Emitter followers.39. Since the bipolar and MOS versions in Fig. Recognizing that VX = Vout + V and the current through the parallel combination of r and C is given by V =r + V C s. 11 Frequency Response voltage gain.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we ﬁrst analyze the emitter follower and subsequently let r (or ) approach inﬁnity to obtain the transfer function of the source follower. the resulting analysis is beyond the scope of this book. The emitter follower is loaded with CL to create both a more general case and greater similarity between the bipolar and MOS counterparts. 2007 at 13:42 570 (1) 570 Chap. We observe that each circuit contains two grounded capacitors and one ﬂoating capacitor.38 differ by only r . and occasionally source followers. Cµ V in RS Cπ X Y VCC RS C GS Vout CL C GD V in X Y VDD C DB M1 Vout C SB + C L Q1 (a) (b) Figure 11. While the latter may be decomposed using Miller’s approximation. out RS r and another at the output node: (11. Vout + V .104) . Consider the small-signal equivalent shown in Fig. We therefore perform a direct analysis by writing the circuit’s equations.38 illustrates the stages with relevant capacitances. are utilized as buffers and their frequency characteristics are of interest. 11. 11.103) V = 1 Vout CL s . Figure 11. Vin + V + V C s + V + V C s = 0.39 Small-signal equivalent of emitter follower.102) V + V C s + g V = V C s: m out L r The latter gives (11. r + gm + C s (11. we write a KCL at node X : RS V in Cµ X Cπ rπ Vπ g Vπ m Vout CL Figure 11.

Vin as2 + bs + 1 where a = RS C C + C CL + C CL g m b = RS C + C + 1 + RS CL : gm r gm g j!z j = Cm .cls v.102) and with the assumption r .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.105) C Vout = 1 + gm s . 2006] June 30. .6 Frequency Response of Followers 571 which. gm1 leads to (11. 2007 at 13:42 571 (1) Sec. 11. upon substitution in (11.

the two poles do not fall far from each other. respectively: Solution a = 2:58 10. Vin as2 + bs + 1 where (11.21 (11. we obtain a and b from Eqs.2 b = 5:8 10.113) !p1 = 2 .115) .108) which. necessitating direct solution of the quadratic denominator.112) (11. from (11. In practice. To compute the poles. The above results also apply to the source follower if r ! 1 and corresponding capacitance