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002
CIRCUITS AND
ELECTRONICS
Introduction and Lumped Circuit Abstraction
6.002 Fall 2000 Lecture
1
1
ADMINISTRIVIA
Lecturer: Prof. Anant Agarwal
Textbook: Agarwal and Lang (A&L)
Readings are important!
Handout no. 3
Assignments —
Homework exercises
Labs
Quizzes
Final exam
6.002 Fall 2000 Lecture
1
2
Two homework assignments can
be missed (except HW11).
Collaboration policy
Homework
You may collaborate with
others, but do your own
writeup.
Lab
You may work in a team of
two, but do you own writeup.
Info handout
Reading for today —
Chapter 1 of the book
6.002 Fall 2000 Lecture
1
3
What is engineering?
Purposeful use of science
What is 6.002 about?
Gainful employment of
Maxwell’s equations
From electrons to digital gates
and opamps
6.002 Fall 2000 Lecture
1
4
6
.
0
0
2
Simple amplifier abstraction
Instruction set abstraction
Pentium, MIPS
Software systems
Operating systems, Browsers
Filters
Operational
amplifier abstraction
abstraction

+
Digital abstraction
Programming languages
Java, C++, Matlab 6.001
Combinational logic
f
Lumped circuit abstraction
R S
+ –
Nature as observed in experiments
… 0.4 0.3 0.2 0.1 I
… 12 9 6 3 V
Physics laws or “abstractions”
Maxwell’s
Ohm’s
V = R I
abstraction for
tables of data
Clocked digital abstraction
Analog system
components:
Modulators,
oscillators,
RF amps,
power supplies 6.061
Mice, toasters, sonar, stereos, doom, space shuttle
6.170
6.455
6.004
6.033
M L C V
6.002 Fall 2000 Lecture
1
5
Lumped Circuit Abstraction
Consider
I
The Big Jump
from physics
to EECS
+

V
?
Suppose we wish to answer this question:
What is the current through the bulb?
6.002 Fall 2000 Lecture
1
6
We could do it the Hard Way…
Apply Maxwell’s
Differential form Integral form
Faraday’s
∇× E = −
∂B
∫
E ⋅ dl = −
∂φ
B
∂t
∂t
Continuity ∇⋅ J = −
∂
∂
ρ
t
∫
J ⋅ dS = −
∂
∂
q
t
Others
∇⋅ E =
ρ
∫
E ⋅ dS =
q
ε
0
ε
0
6.002 Fall 2000 Lecture
1
7
Instead, there is an Easy Way…
First, let us build some insight:
Analogy
F
a ?
I ask you: What is the acceleration?
You quickly ask me: What is the mass?
I tell you: m
F
You respond:
a =
m
Done ! ! !
6.002 Fall 2000 Lecture
1
8
Instead, there is an Easy Way…
First, let us build some insight:
F
a ?
Analogy
In doing so, you ignored
the object’s shape
its temperature
its color
point of force application
Pointmass discretization
6.002 Fall 2000 Lecture
1
9
The Easy Way…
Consider the filament of the light bulb.
A
B
We do not care about
how current flows inside the filament
its temperature, shape, orientation, etc.
Then, we can replace the bulb with a
discrete resistor
for the purpose of calculating the current.
6.002 Fall 2000 Lecture
1
10
The Easy Way…
A
B
Replace the bulb with a
discrete resistor
for the purpose of calculating the current.
+
–
V
A
I
R
and I =
V
R
B
In EE, we do things
the easy way…
R represents the only property of interest!
Like with pointmass: replace objects
F
with their mass m to find
a =
m
6.002 Fall 2000 Lecture
1
11
The Easy Way…
+
–
V
A
I
R
and I =
V
R
B
In EE, we do things
the easy way…
R represents the only property of interest!
R relates element v and i
V
I =
R
called element vi relationship
6.002 Fall 2000 Lecture
1
12
R is a lumped element abstraction
for the bulb.
6.002 Fall 2000 Lecture
1
13
R is a lumped element abstraction
for the bulb.
Not so fast, though …
A
B
A
S
B
S
I
+
–
V
black box
Although we will take the easy way
using lumped abstractions for the rest
of this course, we must make sure (at
least the first time) that our
abstraction is reasonable. In this case,
ensuring that
V I
are defined
for the element
6.002 Fall 2000 Lecture
1
14
A
V I
must be defined
B
A
S
B
S
I
+
–
V
for the element
black box
6.002 Fall 2000 Lecture
1
15
l
I
must be defined. True when
I
into S
A
= I out of
S
B
True only when
∂q
= 0 in the filament!
∂t
∫
J ⋅ dS
S
A
∫
J ⋅ dS
S
B
∫
J ⋅ dS −
∫
J ⋅ dS =
∂q
S
A
S
B
∂t
I
A
I
B
I
A
= I
B
only if
0 =
∂
∂
t
q
So let’s assume this
6.002 Fall 2000 Lecture
1
16
f
r
o
m
M
a
x
w
e
l
V
Must also be defined.
s
e
e
A
&
L
So let’s assume this too
V
AB
So
V
AB
=
∫
AB
E ⋅ dl
defined when
0 =
∂
∂
t
B
φ
outside elements
6.002 Fall 2000 Lecture
1
17
Lumped Matter Discipline (LMD)
0 =
∂
∂
t
B
φ
outside
0 =
∂
∂
t
q
inside elements
bulb, wire, battery
Or self imposed constraints:
More in
Chapter 1
of A & L
Lumped circuit abstraction applies when
elements adhere to the lumped matter
discipline.
6.002 Fall 2000 Lecture
1
18
Demo
Lumped element examples
whose
captured by their V–I
relationship.
only for the
sorts of
questions we
as EEs would
like to ask!
is completely behavior
Demo
Exploding resistor demo
can’t predict that!
Pickle demo
can’t predict light, smell
6.002 Fall 2000 Lecture
1
19
So, what does this buy us?
Replace the differential equations
with simple algebra using lumped
circuit abstraction (LCA).
For example —
a
+
–
1
R
2
R
3
R
b
d
R
4
V
R
5
c
What can we say about voltages in a loop
under the lumped matter discipline?
6.002 Fall 2000 Lecture
1
20
What can we say about voltages in a loop
under LMD?
+
–
1
R
2
R
3
R
a
b
d
R
4
V
R
5
c
∫
E ⋅ dl =
t
B
∂
∂
−
φ
under DMD
0
∫
E ⋅ dl +
∫
E ⋅ dl +
∫
E ⋅ dl = 0
ca ab bc
+ V
ca
+ V
ab
+ V
bc
=
0
Kirchhoff’s Voltage Law (KVL):
The sum of the voltages in a loop is 0.
6.002 Fall 2000 Lecture
1
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What can we say about currents?
Consider
S
I
ca
I
da
ba
I
a
6.002 Fall 2000 Lecture
1
22
What can we say about currents?
ca da
ba
I
a
I
S
I
S
J ⋅ dS =
t
q
∂
∂
−
under LMD
0
∫
I
ca
+ I
da
+ I
ba
= 0
Kirchhoff’s Current Law (KCL):
The sum of the currents into a node is 0.
simply conservation of charge
6.002 Fall 2000 Lecture
1
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KVL and KCL Summary
KVL:
∑
j
ν
j
= 0
loop
KCL:
∑
j
i
j
= 0
node
6.002 Fall 2000 Lecture
1
24
6.002
CIRCUITS AND
ELECTRONICS
Amplifiers 
Small Signal Model
6.002 Fall 2000 Lecture
10
1
Review
MOSFET amp
S
V
L
R
DS
i
v
O
v
I
Saturation discipline — operate
MOSFET only in saturation region
Large signal analysis
1. Find v
O
vs v
I
under saturation discipline.
2. Valid v
I
, v
O
ranges under saturation discipline.
Reading: Small signal model  Chapter 8
6.002 Fall 2000 Lecture
10
2
Large Signal Review
1
v
O
vs v
I
v
O
= V
S
−
K
(v
I
−1)
2
R
L
2
valid for v
I
≥ V
T
and
v
O
≥ v
I
– V
T
(same as i
DS
≤
K
v
O
2
)
2
6.002 Fall 2000 Lecture
10
3
Large Signal Review
2
Valid operating ranges
v
V
5V
corresponding
v
I
−V
T
interesting
v
I
−V
T
region for v
O
v
I
−V
T
S
O
O
v =
O
v >
O
v <
1V
v
I
V
T
1V 2V
“interesting” region
for v
I
. Saturation
discipline satisfied.
6.002 Fall 2000 Lecture
10
4
But…
S
V
O
v
O
v =
I
v
5V
1V
v
I
−V
T
v
I
v
O
Demo
V
T
1V 2V
Amplifies alright,
but distorts
v
I
v
O
t
Amp is nonlinear … /
6.002 Fall 2000 Lecture
10
5
Small Signal Model
~ 5V
V
S
~1V
Hmmm …
( )
L
T I
S O
R
V v K
V v
2
2
−
− =
Amp all right, but nonlinear!
I
v
O
v
T
V
V 1 V 2 ~
Insight:
( )
O I
V , V
Focus on this line segment
So what about our linear amplifier ???
But, observe v
I
vs v
O
about some
point (V
I
, V
O
) … looks quite linear !
6.002 Fall 2000 Lecture
10
6
Trick
o
v
i
v
I
V
O
V
( )
O I
V V ,
O
v ∆
looks
linear
∆v
I
Operate amp at V
I
, V
O
Æ DC “bias” (good choice: midpoint
of input operating range)
Superimpose small signal on top of V
I
Response to small signal seems to be
approximately linear
6.002 Fall 2000 Lecture
10
7
Trick
o
v
i
v
I
V
O
V
( )
O I
V V ,
O
v ∆
looks
linear
∆v
I
Operate amp at V
I
, V
O
Æ DC “bias” (good choice: midpoint
of input operating range)
Superimpose small signal on top of V
I
Response to small signal seems to be
approximately linear
Let’s look at this in more detail —
I
III from a circuit viewpoint
graphically
next
II mathematically
week
6.002 Fall 2000 Lecture
10
8
I Graphically
We use a DC bias V
I
to “boost” interesting input
signal above V
T
, and in fact, well above V
T
.
interesting
input signal
+
–
+
–
S
V
L
R
v
O
∆v
I
V
I
Offset voltage or bias
6.002 Fall 2000 Lecture
10
9
Graphically
interesting
v
O
∆v
I
S
V
L
R
+
–
+
–
input signal
V
I
S
V
O
v
O
V
operating
point
O I
V V ,
I
V
T
V
O
v v =
0
I
−V
T
v
I
Good choice for operating point:
midpoint of input operating range
6.002 Fall 2000 Lecture
10
10
Small Signal Model
aka incremental model
aka linearized model
Notation —
Input:
total
v
I
= V
I
+ v
i
DC small
variable bias signal (like ∆v
I
)
bias voltage aka operating point voltage
Output: v
O
= V
O
+ v
o
Graphically,
v
v
v
i
v
o
V
I
V
O
I
O
0 t
0
t
6.002 Fall 2000 Lecture
10
11
II Mathematically
(… watch my fingers)
v
O
= V
S
−
R
L
K
(v
I
−V
T
)
2
V
O
= V
S
−
R
L
K
(V
I
−V
T
)
2
2
2
substituting v
I
= V
I
+ v
i
v
i
<< V
I
v
O
= V
S
−
R
L
K
( [V
I
+ v
i
]− v
T
)
2
2
= V
S
−
R
L
K
( [V
I
−V
T
]+ v
i
)
2
2
= V
S
−
R
L
K
([V
I
−V
T
]
2
+ 2[V
I
− v
T
]v
i
2
i
v + )
2
O
V + v
o
= (
2
T I
L
S
V V
2
K R
V − − ) − R
L
K (V
I
−V
T
)v
i
From ,
v
o
= −R
L
K (
T I
) V −V v
i
g
m
related to V
I
6.002 Fall 2000 Lecture
10
12
Mathematically
v
o
= −R
L
K (
T I
) V −V v
i
g
m
related to V
I
v
o
= −g
m
R
L
v
i
For a given DC operating point voltage V
I
,
V
I
– V
T
is constant. So,
v
o
= − A v
i
constant w.r.t. v
i
In other words, our circuit behaves like a linear amplifier
for small signals
6.002 Fall 2000 Lecture
10
13
Another way
v
O
= V
S
−
R
L
K
(v
I
−V
T
)
2
2
v
o
=
dv
d
I
V
S
−
R
L
2
K
(v
I
−V
T
)
2
⋅ v
i
I I
v = V
slope at V
I
v
o
= −R
L
K (V
I
−V
T
) ⋅ v
i
g
m
= K (V
I
−V
T
)
A = −g
m
R
L
amp gain
Also, see Figure 8.9 in the course notes
for a graphical interpretation of this result
6.002 Fall 2000 Lecture
10
14
More next lecture …
Demo
DS
i
I
V
O
v
load line
operating point
input signal response
V
O
How to choose the bias point:
1. Gain component g
m
∝ V
I
2. v
i
gets big Æ distortion.
So bias carefully
3. Input valid operating range.
Bias at midpoint of input operating
range for maximum swing.
6.002 Fall 2000 Lecture
10
15
6.002 Fall 2000 Lecture
1
11
6.002
CIRCUITS AND
ELECTRONICS
Small Signal Circuits
6.002 Fall 2000 Lecture
2
11
Small signal notation
v
A
= V
A
+ v
a
total operating
point
small
signal
( )
i
V v
I
I
out
I OUT
v v f
dv
d
v
v f v
I I
⋅ =
=
=
) (
S
V
L
R
o O O
v V v + =
I
V
+
–
+
–
i I I
v V v + =
i
v
Review:
6.002 Fall 2000 Lecture
3
11
I Graphical view
(using transfer function)
behaves linear
for small
perturbations
I
v
O
v
Review:
6.002 Fall 2000 Lecture
4
11
II Mathematical view
( )
L
T I
S O
R
V v K
V v
2
2
−
− =
( )
i
V v
L T I S
I
o
v
R V v
K
V
dv
d
v
I I
⋅
− −
=
=
2
2
related to V
I
constant for fixed
DC bias
( )
i L T I o
v R V V K v ⋅ − − =
g
m
Review:
6.002 Fall 2000 Lecture
5
11
Demo
Choosing a bias point:
DS
i
O
v
L
S L
T I
KR
V KR
V v
2 1 1 + + −
+ =
T I
V v =
2
O DS
v
2
K
i <
load line
L
O
L
S
DS
R
v
R
V
i − =
How to choose the bias point,
using yet another graphical view
based on the load line
O
V
I
V
input signal
response
I L m
V R g ∝ 1. Gain
2. Input valid operating range for amp.
3. Bias to select gain and input swing.
6.002 Fall 2000 Lecture
6
11
III The Small Signal Circuit View
We can derive small circuit equivalent
models for our devices, and thereby conduct
small signal analysis directly on circuits
( )
2
T I D
V v
2
K
i − =
+
–
R
OUT
v
V
S
+
–
I
v
1
e.g. large signal
circuit model
for amp
We can replace large signal models with
small signal circuit models.
Foundations: Section 8.2.1 and also in the
last slide in this lecture.
6.002 Fall 2000 Lecture
7
11
Small Signal Circuit Analysis
1 Find operating point using DC bias
inputs using large signal model.
Develop small signal (linearized)
models for elements.
Replace original elements with small
signal models.
2
3
Analyze resulting linearized circuit…
Key: Can use superposition and other
linear circuit tools with linearized
circuit!
6.002 Fall 2000 Lecture
8
11
Small Signal Models
MOSFET
A
large
signal
( )
2
2
T GS DS
V v
K
i − =
D
S
GS
v
Small signal?
6.002 Fall 2000 Lecture
9
11
Small Signal Models
MOSFET
A
large
signal
( )
2
2
T GS DS
V v
K
i − =
D
S
GS
v
Small signal:
small
signal
D
S
gs
v
( )
gs T GS ds
v V V K i − =
gs m ds
v g i =
( )
2
2
T GS DS
V v
K
i − =
( )
gs
V v
T GS
GS
ds
v V v
K
v
i
GS GS
⋅
−
∂
∂
=
=
2
2
( )
gs T GS ds
v V V K i ⋅ − =
g
m
i
ds
is linear in v
gs
!
6.002 Fall 2000 Lecture
10
11
DC Supply V
S
B
large
signal
S S
V v =
s
I i
S
S
s
i
i
V
v
S S
⋅
∂
∂
=
=
0 v
s
=
+
–
S S
V v =
S
i
+
–
s
v
s
i
DC source behaves
as short to small
signals.
Small signal
6.002 Fall 2000 Lecture
11
11
Similarly, R C
large
signal
small
signal
R
+
–
R
v
R
i
R
+
–
r
v
r
i
R R
i R v =
( )
r
I i
R
R
r
i
i
Ri
v
R R
⋅
∂
∂
=
=
r r
i R v ⋅ =
6.002 Fall 2000 Lecture
12
11
Large signal
( )
2
2
T I DS
V v
K
i − =
( )
L T I S O
R V v
K
V v
2
2
− − =
L
R
O
v
+
–
I
v
+
–
S
V
DS
i
L
R
o
v
+
–
i
v
ds
i
( )
i T I ds
v V V K i ⋅ − =
0 = +
o L ds
v R i
L ds o
R i v − =
( )
i L T I o
v R V V K v ⋅ − − =
i L m
v R g ⋅ − =
Small signal
Amplifier example:
Notice, first we need to find operating
point voltages/currents.
Get these from a large signal analysis.
6.002 Fall 2000 Lecture
13
11
To find the relationship between the small signal parameters of
a circuit, we can replace large signal device models with
corresponding small signal device models, and then analyze the
resulting small signal circuit.
Foundations: (Also see section 8.2.1 of A&L)
KVL, KCL applied to some circuit C yields:
III The Small Signal Circuit View
b B out OUT a A
v V v V v V + + + + + + +
" " "
Replace total variables with
operating point variables plus small signal variables
Operating point variables themselves satisfy the
same KVL, KCL equations
B OUT A
V V V + + + +
" " "
so, we can cancel them out
B OUT A
v v v
+ + + + + + " " " "
1
b out a
v v v + + + +
" " "
Leaving
2
Since small signal models are linear, our linear tools will now
apply…
But is the same equation as with small signal
variables replacing total variables, so must reflect same
topology as in C, except that small signal models are used.
2
1
2
6.002 Fall 2000 Lecture
1
12
6.002
CIRCUITS AND
ELECTRONICS
Capacitors
and FirstOrder Systems
6.002 Fall 2000 Lecture
2
12
5V
0V
C
A
B
5V
A
B
C
5
0
5
0
5
0
Reading:
Chapters 9 & 10
Demo
5V
Expected
Observed
Expect this, right?
But observe this!
Delay!
Motivation
6.002 Fall 2000 Lecture
3
12
The Capacitor
G
D
S
nchannel MOSFET
symbol
nchannel
MOSFET
nchannel
s
i
l
i
c
o
n
n
m
e
t
a
l
+
+
+
+
+
+
o
x
i
d
e
drain
gate
source
C
GS
G
D
S
n
p
6.002 Fall 2000 Lecture
4
12
Ideal Linear Capacitor
obeys DMD!
total charge on
capacitor
0 q q = − + =
d
EA
C =
+ +
+ + + +
 
    
A
E
d
coulombs farads volts
v C q =
i
C
q
+
–
v
6.002 Fall 2000 Lecture
5
12
Ideal Linear Capacitor
dt
dq
i =
( )
dt
Cv d
=
dt
dv
C =
i
v C q =
C
q
+
–
v
A capacitor is an energy storage device
Æ memory device Æ history matters!
=
2
2
1
Cv E
6.002 Fall 2000 Lecture
6
12
Apply node method:
C
+
–
( ) t v
C
( ) t v
I
+
–
R
Thévenin Equivalent:
0 = +
−
dt
dv
C
R
v v
C I C
I C
C
v v
dt
dv
C R = +
0
t t ≥
( )
0
t v
C
given
units
of time
Analyzing an RC circuit
6.002 Fall 2000 Lecture
7
12
Let’s do an example:
( )
I I
V t v =
( )
0
0 V v
C
= given
I C
C
V v
dt
dv
C R = +
X
C
+
–
( ) t v
C
( ) t v
I
+
–
R
6.002 Fall 2000 Lecture
8
12
Example…
Method of homogeneous and particular
solutions:
1
2
3
Find the particular solution.
Find the homogeneous solution.
The total solution is the sum of
the particular and homogeneous
solutions.
Use the initial conditions to solve
for the remaining constants.
( )
I I
V t v =
( ) ( ) ( ) t v t v t v
CP CH C
+ =
total homogeneous particular
( )
0
0 V v
C
= given
I C
C
V v
dt
dv
C R = +
X
6.002 Fall 2000 Lecture
9
12
1 Particular solution
I CP
CP
V v
dt
dv
C R = +
I CP
V v = works
I I
I
V V
dt
dV
C R = +
0
In general, use trial and error.
v
CP
: any solution that satisfies the
original equation X
6.002 Fall 2000 Lecture
10
12
2 Homogeneous solution
0 = +
CH
CH
v
dt
dv
C R
Y
v
CH
: solution to the homogeneous
equation
(set drive to zero)
Y
0 = +
st
st
e A
dt
e dA
C R
0 = +
st st
e A e s CA R
st
CH
e A v =
assume solution
of this form. A, s ?
Discard trivial A = 0 solution,
0 1= + s C R
Characteristic equation
RC
s
1
− =
RC
t
CH
Ae v
−
= or
RC
called time
constant
τ
6.002 Fall 2000 Lecture
11
12
3 Total solution
Find remaining unknown from initial
conditions:
CH CP C
v v v + =
RC
t
I C
e A V v
−
+ =
also
( )
RC
t
I 0 C
C
e
R
V V
dt
dv
C i
−
−
− = =
thus
Given,
so,
or
0 C
V v =
at t = 0
A V V
I 0
+ =
I 0
V V A − =
( )
RC
t
I 0 I C
e V V V v
−
− + =
6.002 Fall 2000 Lecture
12
12
t
C
v
I
V
0
V
( )
RC
t
I 0 I C
e V V V v
−
− + =
RC
0
6.002 Fall 2000 Lecture
13
12
t
C
v
V 5
V 0
V V
I
5 =
V V
O
0 =
5
0
V V
I
0 =
V V
O
5 = 5
0
t
C
v
V 5
V 0
RC
t
e
−
+5 5
RC
t
e
−
5
RC = τ
Remember
demo
B
Examples
6.002 Fall 2000 Lecture
1
13
6.002
CIRCUITS AND
ELECTRONICS
Digital Circuit
6.002 Fall 2000 Lecture
2
13
C
+
–
C
v
I
v
+
–
R
t
C
v
O
V
I
V
( )
RC
t
I O I C
e V V V v
−
− + =
1
( )
O C
V v = 0
t
I
V
I
v
0
Review
time constant RC
RC
6.002 Fall 2000 Lecture
3
13
Let’s apply the result to
an inverter.
A
B
V
S
V
S
X
C
GS
t
A
v
V 5
0
1 Æ 0 at A
A B
X
First, rising delay t
r
at B
6.002 Fall 2000 Lecture
4
13
A
B
V
S
V
S
X
C
GS
ideal
t
A
v
V 5
0
1 Æ 0 at A
First, rising delay t
r
at B
observed
t
B
v
V 5
0
6.002 Fall 2000 Lecture
5
13
A
B
V
S
V
S
X
C
GS
t
A
v
V 5
0
1 Æ 0 at A
OH
V
r
t
rising delay of X
First, rising delay t
r
at B
t
B
v
V 5
0
6.002 Fall 2000 Lecture
6
13
Equivalent circuit for 0Æ1 at B
+
–
B
v
S I
V v =
+
–
L
R
GS
C
( )
GS L
C R
t
S S B
e V V v
−
− + = 0
1 From
Now, we need to find t for which
v
B
= V
OH
.
S I
V v =
for t ≥ 0
( ) 0 0 =
B
v
6.002 Fall 2000 Lecture
7
13
GS L
C R
t
S S OH
e V V v
−
− =
Or
Find t
r
:
OH S
C R
t
S
V V e V
GS L
r
− =
−
S
OH S
GS L
r
V
V V
C R
t −
=
−
ln
S
OH S
GS L r
V
V V
C R t
−
− = ln
6.002 Fall 2000 Lecture
8
13
GS L
C R
t
S S OH
e V V v
−
− =
Or
Find t
r
:
OH S
C R
t
S
V V e V
GS L
r
− =
−
S
OH S
GS L
r
V
V V
C R
t −
=
−
ln
S
OH S
GS L r
V
V V
C R t
−
− = ln
e.g. K R
L
1 =
pF C
GS
1 . 0 =
V V
S
5 =
V V
OH
4 =
5
4 5
ln 10 1 . 0 10 1 t
12 3
r
−
× × × − =
−
ns 16 . 0 =
! 1 . 0 ns RC =
6.002 Fall 2000 Lecture
9
13
Falling Delay t
f
S
V
+
–
L
R
+
–
B
v
GS
C
ON
R
( )
( ) V
V v
S B
5
0 =
X
Falling delay t
f
is
the t for which v
B
falls to V
OL
Equivalent circuit for 1 Æ 0 at B
6.002 Fall 2000 Lecture
10
13
Falling Delay t
f
Equivalent circuit for 1 Æ0 at B
ON L TH
R R R  =
L ON
ON
S TH
R R
R
V V
+
=
Thévenin replacement …
+
–
B
v
TH
V
TH
R
GS
C
+
–
S
V
+
–
L
R
+
–
B
v
GS
C
ON
R
( )
( ) V
V v
S B
5
0 =
X
6.002 Fall 2000 Lecture
11
13
( )
GS TH
C R
t
TH S TH B
e V V V v
−
− + =
1 From
Falling decay t
f
is
the t for which v
B
falls to V
OL
( )
GS TH
f
C R
t
TH S TH OL
e V V V V
−
− + =
or
TH S
TH OL
GS TH f
V V
V V
C R t
−
−
− = ln
6.002 Fall 2000 Lecture
12
13
TH S
TH OL
GS TH f
V V
V V
C R t
−
−
− = ln
e.g.
5
1
ln 10 1 . 0 10
12 −
⋅ ⋅ − =
f
t
ps 6 . 1 =
! 1 ps RC =
K R
L
1 =
pF C
GS
1 . 0 =
V V
S
5 =
V V
OL
1 =
Ω =10
ON
R
V V R
TH TH
0 , 10 ≈ Ω ≈
6.002 Fall 2000 Lecture
13
13
For recitation: Slow may be better
Problem
pin 2
pin 1
chip
L
C
So the engineers decided to speed it up…
made R
L
small
made R
ON
small
R
L
R
ON
ideal slow! observed
v:
v
6.002 Fall 2000 Lecture
14
13
For recitation: Slow may be better
Problem
pin 2
pin 1
chip
L
C
ideal slow! observed
…
but, disaster!
v:
v
expected
v:
V
IL
observed
6.002 Fall 2000 Lecture
15
13
Why? Consider
…
1 Case
1
R
0
R
pin1
ok
Demo
6.002 Fall 2000 Lecture
16
13
Why? Consider
…
2 Case
1
R
0
R
pin1
2
R
pin2
P
C
crosstalk!
Demo
model for crosstalk:
+
–
v
R
P
C
+
–
6.002 Fall 2000 Lecture
17
13
3 Case
…
6.002 expert saw the solution
Detailed analysis in recitation.
P
C
1
R
0
R
2
R
+
–
slower transitions!
6.002 Fall 2000 Lecture
1
14
6.002
CIRCUITS AND
ELECTRONICS
State and Memory
6.002 Fall 2000 Lecture
2
14
C
+
–
C
v
I
v
+
–
R
1
Recall
Reading: Sections 10.3, 10.5, and 10.7
Review
V v
I I
0 t
≥
=
for
( )
RC
t
I I C
e V V v
−
− + = ( )
C
v 0
( )
C
v 0
6.002 Fall 2000 Lecture
3
14
t
I
v
0
t
C
v
0
I
V
( ) 0
C
v
I
v
I
V
This lecture will dwell on the
memory property of capacitors.
For the RC circuit in the previous slide
Notice that the capacitor voltage for is
independent of the form of the input voltage
before . Instead, it depends only on the
capacitor voltage at , and the input voltage
for .
0 t
≥
0 t
≥
0 t
=
0 t
=
0 t
≥
( )
RC
t
I I C
e V V v
−
− + = ( )
C
v 0
6.002 Fall 2000 Lecture
4
14
V C q =
for linear capacitors,
capacitor voltage V
is also state variable
state variable, actually
State : summary of past inputs relevant
to predicting the future
State
6.002 Fall 2000 Lecture
5
14
( ) ( )
RC
t
I C I C
e V v V v
−
− + = 0
1
Back to our simple RC circuit
( ) ( ) ( ) t v v f v
I C C
, 0 =
State
Summarizes the past input relevant
to predicting future behavior
6.002 Fall 2000 Lecture
6
14
We are often interested in circuit
response for
zero state v
C
(0) = 0
zero input v
I
(t) = 0
zero input response or ZIR
( )
RC
t
C C
e v v
−
= 0
RC
t
I I C
e V V v
−
− =
Correspondingly,
zero state response or ZSR
2
3
State
6.002 Fall 2000 Lecture
7
14
Why memory?
Or, why is combinational logic insufficient?
One application of STATE
DIGITAL MEMORY
Examples
Consider adding 6 numbers on your
calculator
“Remembering” transient inputs
2 + 9 + 6 + 5 + 3 + 8
M+
6.002 Fall 2000 Lecture
8
14
A 1bit memory element
Memory Abstraction
Remembers input when store goes high.
Like a camera that records input (d
IN
) when the
user presses the shutter release button.
The recorded value is visible at d
OUT
.
IN
d
OUT
d
store M
IN
d
store
OUT
d
remembers the 1
The
6.004
view
The
NEC
View
☺
$
¥
6.002 Fall 2000 Lecture
9
14
A First attempt
Building a memory element …
store
storage
node
d
IN
d
OUT
C
*
6.002 Fall 2000 Lecture
10
14
A
Stored value leaks away
store pulse width >> R
ON
C
Building a memory element …
C R
t
C
L
e v
−
⋅ = 5
5
ln
OH
L
V
C R T − =
2
from
v
C
t
T
5V
V
OH
v
C
store = 1
d
IN
d
OUT
C
*
v
C
store = 0
d
IN
d
OUT
C
*
R
L
6.002 Fall 2000 Lecture
11
14
Input resistance R
IN
B
Second attempt buffer
R
IN
store
buffer
d
IN
d
OUT
C
*
5
ln
OH
IN
V
C R T − =
L IN
R R >>
Better, but still not perfect.
Demo
Building a memory element …
6.002 Fall 2000 Lecture
12
14
Does this work?
C
Third attempt buffer + refresh
store
d
IN
d
OUT
C
*
store
Building a memory element …
No. External value can
influence storage node.
6.002 Fall 2000 Lecture
13
14
Works!
D
Fourth attempt buffer + decoupled
refresh
store
d
IN
d
OUT
C
*
store
Building a memory element …
6.002 Fall 2000 Lecture
14
14
A Memory Array
Decoder
Address
IN
d
OUT
d
S M
IN
d
OUT
d
S M
IN
d
OUT
d
S M
IN
d
OUT
d
S M
A
B
C
D
0 0
1 0
0 1
1 1
IN store
OUT
a
0
a
1
2
A
B
C
D
store
4bit memory
Address
IN
OUT
6.002 Fall 2000 Lecture
15
14
Truth table for decoder
a
0
a
1
A B C D
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
6.002 Fall 2000 Lecture
16
14
Agarwal’s top 10 list on memory
10 I have no recollection, Senator.
9 I forgot the homework was due today.
8 Adlibbing ZSR
7 I think, therefore I am.
6 I think that was right.
5 I forgot the rest …
≡
6.002 Fall 2000 Lecture
1
15
6.002
CIRCUITS AND
ELECTRONICS
SecondOrder Systems
6.002 Fall 2000 Lecture
2
15
SecondOrder Systems
C
A
B
5V
+
–
5V
C
GS
large
loop
2KΩ
50Ω
2KΩ
Demo
Our old friend, the inverter, driving another.
The parasitic inductance of the wire and
the gatetosource capacitance of the
MOSFET are shown
[Review complex algebra appendix for next class]
S
6.002 Fall 2000 Lecture
3
15
SecondOrder Systems
C
A
B
5V
+
–
5V
C
GS
large
loop
2KΩ
50Ω
2KΩ
Demo
+
–
5V
C
GS
2KΩ
B
L
Relevant circuit:
S
6.002 Fall 2000 Lecture
4
15
Now, let’s try to speed up our inverter by
closing the switch S to lower the effective
resistance
t
v
A
5
0
v
B
0 t
v
C
0
t
Observed Output
2kΩ
2kΩ
6.002 Fall 2000 Lecture
5
15
t
v
A
5
0
v
B
0 t
v
C
0
t
Observed Output
~50Ω
50Ω
Huh!
6.002 Fall 2000 Lecture
6
15
v, i state variables
+
–
C
L
+
–
) (t v
) (t v
I
) (t i
Node method:
dt
dv
C t i = ) (
dt
dv
C dt v v
L
t
I
= −
∫
∞ −
) (
1
2
2
) (
1
dt
v d
C v v
L
I
= −
I
v v
dt
v d
LC = +
2
2
time
2
dt
di
L v v
I
= −
i dt v v
L
t
I
= −
∫
∞ −
) (
1
Recall
First, let’s analyze the LC network
6.002 Fall 2000 Lecture
7
15
Recall, the method of homogeneous and
particular solutions:
( ) ( ) t v t v v
H P
+ =
1
2
3
Find the particular solution.
Find the homogeneous solution.
L
4 steps
The total solution is the sum of the
particular and homogeneous.
Use initial conditions to solve for the
remaining constants.
Solving
6.002 Fall 2000 Lecture
8
15
And for initial conditions
v(0) = 0 i(0) = 0 [ZSR]
I
v
0
V
0
t
Let’s solve
I
v v
dt
v d
LC = +
2
2
For input
6.002 Fall 2000 Lecture
9
15
1 Particular solution
0
2
2
V v
dt
v d
LC
P
P
= +
0
V v
P
= is a solution.
6.002 Fall 2000 Lecture
10
15
0
2
2
= +
H
H
v
dt
v d
LC
Solution to
Homogeneous solution 2
Recall, v
H
: solution to homogeneous
equation (drive set to zero)
Fourstep method:
D
t j
2
t j
1 H
o o
e A e A v
ω ω −
+ =
General solution,
Roots C
o
j s ω ± =
LC
1
o
= ω
Assume solution of the form
*
A
? s , A , Ae v
st
H
= =
so, 0
2
= +
st st
Ae e LCAs
*
Differential equations are commonly
solved by guessing solutions
1 − = j
LC
j s
1
± =
B
LC
s
1
2
− =
characteristic
equation
6.002 Fall 2000 Lecture
11
15
Total solution 3
Find unknowns from initial conditions.
t j
2
t j
1 0
o o
e A e A V ) t ( v
ω ω −
+ + =
) ( ) ( ) ( t v t v t v
H P
+ =
0 ) 0 ( = v
2 1 0
0 A A V + + =
0 ) 0 ( = i
t j
o 2
t j
o 1
o o
e j CA e j CA ) t ( i
ω ω
ω ω
−
− =
dt
dv
C t i = ) (
so,
o 2 o 1
j CA j CA 0 ω ω − =
or,
2 1
A A =
A V 2
0
= −
2
0
1
V
A − =
( )
t j t j
0
0
o o
e e
2
V
V ) t ( v
ω ω −
+ − = so,
6.002 Fall 2000 Lecture
12
15
Remember Euler relation
(verify using Taylor’s
expansion)
x j x e
jx
sin cos + =
x
e e
jx jx
cos
2
=
+
−
t sin CV ) t ( i
o o 0
ω ω =
t cos V V ) t ( v
o 0 0
ω − = so, where
LC
1
o
= ω
Total solution 3
The output looks sinusoidal
6.002 Fall 2000 Lecture
13
15
) (t v
0
2V
0
V
0
2
π
2
3π
π
π 2
t
o
ω
) (t i
o 0
CV ω
0
2
π
2
3π
π
π 2
t
o
ω
o 0
CV ω −
Plotting the Total Solution
6.002 Fall 2000 Lecture
14
15
Summary of Method
1
2
3
Write DE for circuit by applying
node method.
Find particular solution v
P
by guessing
and trial & error.
Find homogeneous solution v
H
4 Total solution is v
P
+ v
H
,
solve for remaining constants using
initial conditions.
Assume solution of the form Ae
st
.
Obtain characteristic equation.
Solve characteristic equation
for roots s
i
.
Form v
H
by summing A
i
e
s
i
t
terms.
D
C
A
B
6.002 Fall 2000 Lecture
15
15
What if we have:
We can obtain the answer directly from
the homogeneous solution (V
0
= 0).
V v
C
= ) 0 (
0 ) 0 ( =
C
i
C
L
C
i
+
–
C
v
Example
6.002 Fall 2000 Lecture
16
15
We can obtain the answer directly from
the homogeneous solution (V
0
= 0).
t j
2
t j
1 C
o o
e A e A ) t ( v
ω ω −
+ =
V v
C
= ) 0 (
0 ) 0 ( =
C
i
2 1
A A V + =
o 2 o 1
j CA j CA 0 ω ω − =
or
2
2 1
V
A A = =
( )
t j t j
C
o o
e e
2
V
v
ω ω −
+ = or
t cos V v
o C
ω =
t sin CV i
o o C
ω ω − =
V v
C
= ) 0 (
0 ) 0 ( =
C
i
C
L
C
i
+
–
C
v
Example
6.002 Fall 2000 Lecture
17
15
t
o
ω
π 2
C
v
V
C
i
t
o
ω
π 2
o
CVω −
o
CVω
Example
6.002 Fall 2000 Lecture
18
15
2
2 2
2
1
2
1
2
1
CV Li Cv
C C
= + Notice
Energy
2
2
1
:
C
Cv C
2
2
1
:
C
Li L
t
o
ω
π 2
C
E
2
2
1
CV
t
o
ω
π 2
L
E
2
2
1
CV
Total energy in the system is a constant,
but it sloshes back and forth between the
Capacitor and the inductor
6.002 Fall 2000 Lecture
19
15
RLC Circuits
See A&L Section 12.2
add R
no R
+
–
C
R L
+
–
) (t v
) (t v
I
) (t i
) (t v
t
Damped sinusoids with R – remember demo!
6.002
CIRCUITS AND
ELECTRONICS
Sinusoidal Steady State
6.002 Fall 2000 Lecture
16
1
Review
We now understand the why of:
5V
C
R
L
v
Today, look at response of networks
to sinusoidal drive.
Sinusoids important because signals can be
represented as a sum of sinusoids. Response to
sinusoids of various frequencies  aka frequency
response  tells us a lot about the system
6.002 Fall 2000 Lecture
16
2
Motivation
For motivation, consider our old friend,
the amplifier:
S
V
v
O
v
i
C
v
+
–
+
–
GS
C
R
V
BIAS
Observe v
o
amplitude as the frequency of the
input v
i
changes. Notice it decreases with
frequency.
Also observe v
o
shift as frequency changes
(phase).
Need to study behavior of networks for
sinusoidal drive.
Demo
6.002 Fall 2000 Lecture
16
3
Sinusoidal Response of RC Network
Example:
+
–
R
i
C
+
v
I
v
C
–
v
I
(t) = V
i
cosωt for t ≥ 0 (V
i
real)
= 0 for t < 0
v
C
(0) = 0 for t = 0
I
v
0
t
6.002 Fall 2000 Lecture
16
4
1
1
1
1
e
c
t
u
r
Example:
+
–
R
Our Approach
i
C
+
v
I
v
C
–
Determine v
C
(t)
I
n
d
u
lg
e
m
e
!
E
f
f
o
r
t
l
e
c
t
u
r
e
sneaky approach
very
sneaky
Usual
approach
agony
easy
t
e
0
:
0
:
0
0
2
1
0
:
2
l
s
h
i
T
t
x
e
N
6.002 Fall 2000 Lecture
16
5
Let’s use the usual approach…
1 Set up DE.
2 Find v
p
.
3 Find v
H
.
4 v
C
= v
P
+ v
H
, solve for unknowns
using initial conditions
6.002 Fall 2000 Lecture
16
6
Usual approach…
1
Set up DE
RC
dv
C
+ v
C
= v
I
dt
= V
i
cosωt
That was easy!
6.002 Fall 2000 Lecture
16
7
2 Find v
p
RC
dv
P
+
dt
v
P
= V
i
cosωt
First try:
v
P
= A
Æ nope
Second try:
v
P
= A cosωt
Æ nope
Third try:
v
P
= A cos(
amplitude
φ ω + t
frequency
)
phase
− RCAω sin(ωt +φ) + A cos(ωt +φ) = V
i
cosωt
− RCAω sin ωt cosφ − RCAω cosωt sin φ +
A cosωt cosφ − Asinωt sinφ = V
i
cosωt
.
.
gasp !
.
works, but trig nightmare!
6.002 Fall 2000 Lecture
16
8
6.002 ll 2000 Lecture
9
16
Let’s get sneaky!
Try solution
st
p PS
e V v =
st
i
st
p
st
p
e V e V
dt
e dV
RC = +
st
i
st
p
st
p
e V e V e sRCV = +
i p
V V ) 1 sRC ( = +
sRC 1
V
V
i
p
+
=
Nice
property
of
exponentials
IS PS
PS
v v
dt
dv
RC = + (S: sneaky :))
st
i
e V =
Find particular solution to another input…
p
V complex amplitude
Thus,
st
i
PS
e
sRC 1
V
v ⋅
+
=
st
i
e V is particular solution to
easy!
where we replace s = jω
ly
t j
i
e V
ω
solution for
t j
i
e
RC j
V
ω
ω
⋅
+ 1
Fa
2 Fourth try to find v
P
…
using the sneaky approach
Fact 1: Finding the response to
V
i
e
jωt
was easy.
Fact 2: v
I
= V
i
cos ωt
= real[V
i
e
jωt
] = real[v
IS
]
from Euler relation,
j
I
v
P
v
response
IS
v
PS
v
response
real
part
real
part
e
jωt
= cosωt + sin ωt
an inverse superposition argument,
assuming system is real, linear.
6.002 Fall 2000 Lecture
16
10
2 Fourth try to find v
P
…
so, complex
P
v = Re[v
PS
] = Re[V
p
e
jωt
]
V
i
= Re
1+ jωRC
⋅ e
jωt
= Re
V
i
(1− jωRC)
⋅ e
jωt
1+ω
2
R
2
C
2
= Re
C R 1
2 2 2
ω +
V
i
⋅ e
jφ
e
jωt
, tanφ = −ωRC
= Re
+
2 2 2
C R 1 ω
V
i
⋅ e
j( ωt +φ )
v
P
=
C R 1
2 2 2
ω +
V
i
⋅ cos(ωt +φ )
Recall, v
P
is particular response to V
i
cosωt .
6.002 Fall 2000 Lecture
16
11
3 Find v
H
−t
Recall, v
H
= Ae
RC
6.002 Fall 2000 Lecture
16
12
4 Find total solution
v
C
=
P
v + v
H
t
−
v
C
=
2 2 2
C R 1 + ω
V
i
cos( ωt +φ ) + Ae
RC
where φ = tan
−1
( −ωRC )
Given v
C
(0) = 0 for t = 0
so,
A = −
1
2 2 2
ω C R +
V
i
cos(φ)
Done! Phew!
6.002 Fall 2000 Lecture
16
13
Sinusoidal Steady State
We are usually interested only in the
particular solution for sinusoids,
i.e. after transients have died.
t
−
Notice when t →∞, v
C
→ v
P
as e
RC
→ 0
2 2 2
i
C
cos(
C R 1
V
+
=
ω
tan where φ =
A − =
p
V
RC
t
Ae ) t
−
+ +φ ω
) RC (
1
ω −
−
cos(
1
2 2 2
φ
ω C R
V
i
+
0
v
)
Described as
SSS: Sinusoidal Steady State
p
V ∠
6.002 Fall 2000 Lecture
16
14
Sinusoidal Steady State
All information about SSS is contained
in V
p
, the complex amplitude!
Recall
RC j 1
V
V
i
p
ω +
=
Steps 3 ,
were a waste of
time!
4
V
p
1
=
V
i
1+ jωRC
V
p
ω
2 2 2
i
C R 1
V
+
=
1
e
jφ
where
φ = tan
−1
−ωRC
2 2 2
1
1
C R
V
V
i
p
ω +
=
RC
V
V
i
p
ω φ
1
tan : phase
−
− = ∠
magnitude
6.002 Fall 2000 Lecture
16
15
Sinusoidal Steady State
Visualizing the process of finding the
particular solution v
P
sneak
in
V
i
e
jωt
drive
algebraic
equation
+
complex
algebra
take
real
part
t j
p
e V
ω
particular
solution
t V
i
ω cos
D.E.
+
nightmare
trig.
drive
[
p
V t V ∠ + ω cos
p
]
the sneaky path!
6.002 Fall 2000 Lecture
16
16
Magnitude Plot
transfer function
V
H ( jω) =
V
p
i
2 2 2
1
1
C R
V
V
i
p
ω +
=
V
p
1
V
i
log
scale
ω
log
1
ω =
scale
RC
From demo: explains v
o
fall off
for high frequencies!
6.002 Fall 2000 Lecture
16
17
Phase Plot
φ = tan
−1
−ωRC
V
φ = ∠
p
V
i
0
π
−
4
π
−
2
ω
RC
1
= ω
log scale
6.002 Fall 2000 Lecture
16
18
6.002 Fall 2000 Lecture
1
17
6.002
CIRCUITS AND
ELECTRONICS
The Impedance Model
6.002 Fall 2000 Lecture
2
17
Sinusoidal Steady State (SSS)
Reading 13.1, 13.2
+
–
O
v t V v
i I
ω cos =
+
–
R
C
Focus on steady state, only care
about v
P
as v
H
dies away.
Focus on sinusoids.
Reading: Section 13.3 from course notes.
SSS
Review
Sinusoidal Steady State (SSS)
Reading 13.1, 13.2
6.002 Fall 2000 Lecture
3
17
3
4
H
v
total
Review
V
p
contains all the information we need:
p
p
V
V
∠
Amplitude of output cosine
phase
sneak
in
V
i
e
jωt
drive
complex
algebra
take
real
part
The Sneaky Path
p
V
t V
i
ω cos [ ]
p p
V t V ∠ + ω cos
set
up
DE
usual
circuit
model
nightmare
trig.
1
v
P
t j
p
e V
ω
RC j
V
i
ω + 1
2
6.002 Fall 2000 Lecture
4
17
i
p
V
V
transfer
function
( ) ω
ω
j H
RC j V
V
i
p
=
+
=
1
1
( )
p p O
V t V v ∠ + = ω cos
2 2 2
1
1
C R ω +
break frequency
Bode plot
ω
RC
1
= ω
1
RC
1
ω
2
1
remember
demo
ω
RC
1
= ω
4
π
−
2
π
−
0
i
p
V
V
∠
⎟
⎠
⎞
⎜
⎝
⎛
−
−
1
RC
tan
1
ω
The Frequency View
Review
6.002 Fall 2000 Lecture
5
17
Is there an even simpler way
to get V
p
?
RC j
V
V
i
p
ω +
=
1
Divide numerator and denominator by jωC.
R
C j
C j
V V
i p
+
=
ω
ω
1
1
Let’s explore further…
Hmmm… looks like a voltage divider
relationship.
R Z
Z
V V
C
C
i p
+
=
6.002 Fall 2000 Lecture
6
17
The Impedance Model
Is there an even simpler way to get V
p
?
Consider:
t j
r R
e I i
ω
=
t j
r R
e V v
ω
=
R R
Ri v =
t j
r
t j
r
e RI e V
ω ω
=
r r
RI V =
R
R
i
+
–
R
v
Resistor
t j
C C
e I i
ω
=
t j
C C
e V v
ω
=
C
C
i
+
–
C
v
Capacitor
C C
I
C j
1
V
ω
=
dt
dv
C i
C
C
=
t j
C
t j
C
e j CV e I
ω ω
ω =
C
Z
L
L
i
+
–
L
v
t j
l L
e I i
ω
=
t j
l L
e V v
ω
=
dt
di
L v
L
L
=
t j
l
t j
l
e j LI e V
ω ω
ω =
Inductor
l l
I L j V ω =
L
Z
6.002 Fall 2000 Lecture
7
17
In other words,
For a drive of the form V
c
e
jωt
,
complex amplitude V
c
is related to the
complex amplitude I
c
algebraically,
by a generalization of Ohm’s Law.
inductor
L j Z
l
ω =
l l l
I Z V =
l
I
+
–
l
V
L
Z
resistor
r r r
I Z V =
R Z
r
=
R
Z
r
I
+
–
r
V
capacitor
C j
1
Z
C
ω
=
c C c
I Z V =
impedance
c
I
+
–
c
V
C
Z
The Impedance Model
6.002 Fall 2000 Lecture
8
17
Impedance model:
All our old friends apply!
KVL, KCL, superposition…
Back to RC example…
i
R C
C
i c
V
Z Z
Z
V
R
C j
1
C j
1
V
+
=
+
=
ω
ω
i c
V
RC j 1
1
V
ω +
=
Done!
+
–
C
v
I
v
+
–
R
C
+
–
c
V
i
V
+
–
R Z
R
=
C j
Z
C
ω
1
=
c
I
6.002 Fall 2000 Lecture
9
17
Another example, recall series RLC:
We will study this and other functions
in more detail in the next lecture.
R
C j
L j
R V
V
i
r
+ +
=
ω
ω
1
R C L
R i
r
Z Z Z
Z V
V
+ +
=
CR j LC
CR j V
V
i
r
ω ω
ω
+ + −
=
1
2
+
–
L
r
I
C
R
+
–
r
V
i
V
t j
r
e V
ω
( )
r r
V t V ∠ + ω cos
t j
i
e V
ω
t V
i
ω cos
Remember, we want only the steadystate
response to sinusoid
6.002 Fall 2000 Lecture
10
17
The Big Picture…
t V
i
ω cos [ ]
p p
V t V ∠ + ω cos
set
up
DE
usual
circuit
model
nightmare
trig.
6.002 Fall 2000 Lecture
11
17
The Big Picture…
t V
i
ω cos [ ]
p p
V t V ∠ + ω cos
set
up
DE
usual
circuit
model
nightmare
trig.
V
i
e
jωt
drive
complex
algebra
take
real
part
6.002 Fall 2000 Lecture
12
17
The Big Picture…
No D.E.s, no trig!
t V
i
ω cos [ ]
p p
V t V ∠ + ω cos
set
up
DE
usual
circuit
model
nightmare
trig.
V
i
e
jωt
drive
complex
algebra
take
real
part
complex
algebra
impedancebased
circuit model
6.002 Fall 2000 Lecture
13
17
Back to
LC RC j 1
RC j
V
V
2
i
r
ω ω
ω
− +
=
( )
( )
( ) RC j LC 1
RC j LC 1
RC j LC 1
RC j
2
2
2
ω ω
ω ω
ω ω
ω
− −
− −
⋅
+ −
=
( ) ( )
2
2
2
i
r
RC LC 1
RC
V
V
ω ω
ω
+ −
=
: Low ω RC ω ≈
: High ω
L
R
ω
≈
: 1 LC = ω 1 ≈
Let’s study this transfer function
+
–
L
r
I
C +
–
r
V
i
V
R
LC RC j 1
RC j
V
V
2
i
r
ω ω
ω
− +
=
Observe
6.002 Fall 2000 Lecture
14
17
Graphically
( ) ( )
2
2
2
1 RC LC
RC
V
V
i
r
ω ω
ω
+ −
=
More next week…
: Low ω RC ω ≈
: High ω
L
R
ω
≈
: 1 LC = ω 1 ≈
i
r
V
V
LC
1
ω
L
R
ω
RC ω
1 “Band Pass”
Remember this trick to sketch the form of
transfer functions quickly.
6.002 Fall 2000 Lecture
1
18
6.002
CIRCUITS AND
ELECTRONICS
Filters
6.002 Fall 2000 Lecture
2
18
Review
+
–
C
v
I
v
+
–
R
C
Reading: Section 14.5, 14.6, 15.3 from A & L.
+
–
c
V
i
V
+
–
R
Z
C
Z
i
R C
C
c
V
Z Z
Z
V ⋅
+
=
RC j 1
1
R
C j
1
C j
1
V
V
i
c
ω
ω
ω
+
=
+
=
6.002 Fall 2000 Lecture
3
18
A Filter
RC j 1
1
V
Z Z
Z
V
i
R C
C
c
ω +
= ⋅
+
=
“Low Pass Filter”
ω
1
( )
i
c
V
V
H = ω
Demo
with audio
+
–
c
V
i
V
+
–
R
Z
C
Z
6.002 Fall 2000 Lecture
4
18
Quick Review of Impedances
Just as
2 1
ab
ab
AB
R R
I
V
R + = =
L j R
I
V
Z
1
ab
ab
AB
ω + = =
1
R
ab
I
+
–
ab
V
2
R
A
B
1
R
ab
I
+
–
ab
V
L jω
A
B
6.002 Fall 2000 Lecture
5
18
Quick Review of Impedances
Similarly
L 2 C 1 AB
Z R  Z R Z + + =
L
2 C
2 C
1
Z
R Z
R Z
R +
+
+ =
L j
CR j 1
R
R
2
2
1
ω
ω
+
+
+ =
1
R
L
A
B
2
R C
6.002 Fall 2000 Lecture
6
18
We can build other filters by
combining impedances
( ) ω Z
L
R
C
ω
Z
6.002 Fall 2000 Lecture
7
18
We can build other filters by
combining impedances
HPF
High Pass Filter
ω
( ) ω H
ω
( ) ω H
LPF
Low Pass Filter
ω
( ) ω H
HPF
( ) ω Z
L
R
C ω
Z
+
–
+
–
+
–
6.002 Fall 2000 Lecture
8
18
Check out:
R
C j
1
L j
R
V
V
i
r
+ +
=
ω
ω
RC j LC 1
RC j
2
ω ω
ω
+ −
=
( ) ( )
2
2
2
i
r
RC LC 1
RC
V
V
ω ω
ω
+ −
=
ω
+
–
L
C
R
+
–
r
V
i
V
LC
1
o
= ω
At resonance,
ω = ω
o
and
Z
L
+ Z
C
= 0,
so V
i
sees
only R!
More later…
Intuitively:
i
r
V
V
1
L
b
lo
c
k
s
h
ig
h
f
r
e
q
C
b
l
o
c
k
s
l
o
w
f
r
e
q
6.002 Fall 2000 Lecture
9
18
What about:
+
–
L
C
R
+
–
lc
V
i
V
Band Stop Filter
i
lc
V
V
ω
1
C open
L open
Check out V
l
and V
c
in the lab.
6.002 Fall 2000 Lecture
10
18
Another example:
+
–
+
–
L
R
i
V
C
o
V
i
o
V
V
o
ω
ω
BPF
C
s
h
o
r
t
L
s
h
o
r
t
Application: see AM radio coming up shortly
6.002 Fall 2000 Lecture
11
18
AM Radio Receiver
crystal radio demo
Thévenin
antenna
model
+
–
L
R
i
V C
demodulator
amplifier
antenna
6.002 Fall 2000 Lecture
12
18
AM Receiver
“Selectivity” important —
relates to a parameter “Q” for the filter. Next…
+
–
L
R
i
V C
demodulator
amplifier
f
signal
strength
540 …1000 1010 1020 1030 … 1600 KHz
10 KHz
filter
WBZ
News
Radio
6.002 Fall 2000 Lecture
13
18
Recall,
Selectivity:
Look at series RLC in more detail
+
–
L
C
R
+
–
r
V
i
V
C j
1
L j R
R
V
V
i
r
ω
ω + +
=
i
r
V
V
ω
o
ω
2
1
higher Q
1
Define quality factor
Δ
=
Q
o
ω
ω
ω Δ
bandwidth
⇒
Q high
more selective
6.002 Fall 2000 Lecture
14
18
ω
ω
Δ
=
o
Q
LC
1
o
= ω
Quality Factor Q
⎟
⎠
⎞
⎜
⎝
⎛
− +
=
+ +
=
CR
1
R
L
j 1
1
C j
1
L j R
R
i
V
r
V
ω
ω
ω
ω
?
ω Δ
at =0
ω
ο
ω
ο
:
6.002 Fall 2000 Lecture
15
18
Note that abs magnitude is
2
1
when
1 j 1
1
CR
1
R
L
j 1
1
V
V
i
r
±
=
⎟
⎠
⎞
⎜
⎝
⎛
− +
=
ω
ω
i.e. when
1
CR
1
R
L
± = −
ω
ω
0
LC
1
L
R
2
= −
ω
ω m
:
ω Δ
ω
ω
Δ
=
o
Q
Quality Factor Q
Looking at the roots of both equations,
LC
4
L
R
2
1
L 2
R
2
2
1
+ + = ω
LC
4
L
R
2
1
L 2
R
2
2
2
+ + − = ω
L
R
= − = Δ
2 1
ω ω ω
6.002 Fall 2000 Lecture
16
18
R
L
L
R
Q
o o
ω ω
= =
The lower the R (for series R),
the sharper the peak
ω
ω
Δ
=
o
Q
Quality Factor Q
LC
1
o
= ω
6.002 Fall 2000 Lecture
17
18
Another way of looking at Q :
cycle per lost energy
stored energy
2π = Q
0
2
r
2
r
2
R I
2
1
I L
2
1
2
ω
π
π =
R
L
Q
o
ω
=
Quality Factor Q
6.002 Fall 2000 Lecture
1
19
6.002
CIRCUITS AND
ELECTRONICS
The Operational Amplifier
Abstraction
6.002 Fall 2000 Lecture
2
19
MOSFET amplifier — 3 ports
power
port
input
port
output
port
+
–
I
v
+
–
O
v
+
–
S
V
Amplifier abstraction
+
–
I
v
+
–
S
V
+
–
O
v
I
v
O
v
Function of v
I
Review
6.002 Fall 2000 Lecture
3
19
Can use as an abstract building block for
more complex circuits (of course, need
to be careful about input and output).
Today
Introduce a more powerful amplifier
abstraction and use it to build more
complex circuits.
Reading: Chapter 15 from A & L.
I
v
O
v
Function of v
I
Review
6.002 Fall 2000 Lecture
4
19
Operational Amplifier
Op Amp
OUT
v
+
–
+
–
IN
v
More abstract representation:
input
port
S
V
output
port
power
port
S
V −
+
–
+
–
+
–
6.002 Fall 2000 Lecture
5
19
Circuit model (ideal):
i.e. ∞ input resistance
0 output resistance
“A” virtually ∞
No saturation
O
v
Av
∞ → A
+
–
+
–
v
v
+
v
–
0 = i
+
0 = i
–
6.002 Fall 2000 Lecture
6
19
(Note: possible confusion with MOSFET saturation!)
Using it…
+
–
V V
S
12 − = −
L
R
O
v
+
–
12V
+
–
12V
V V
S
12 =
Demo
IN
v
μV 10 μV 10 −
O
v
V 12
V 12 −
6
10 ~ A
but unreliable,
temp. dependent
saturation
active region
IN
v
6.002 Fall 2000 Lecture
7
19
Let us build a circuit…
Circuit: noninverting amplifier
Equivalent circuit model
1
R
O
v
+
–
2
R
IN
v
+
v
−
v
( )
− +
−v v A
+
–
0 = i
+
0 = i
–
o
p
a
m
p
1
R
O
v
+
–
2
R
IN
v
+
–
+
v
−
v
6.002 Fall 2000 Lecture
8
19
Let us analyze the circuit:
Find v
O
in terms of v
IN
, etc.
What happens when “A” is very large?
( )
− +
− = v v A v
O
⎟
⎠
⎞
⎜
⎝
⎛
+
− =
2 1
2
R R
R
v v A
O IN
IN
2 1
2
O
Av
R R
AR
1 v = ⎟
⎠
⎞
⎜
⎝
⎛
+
+
2 1
2
IN
O
R R
AR
1
Av
v
+
+
=
6.002 Fall 2000 Lecture
9
19
Let’s see… When A is large
Gain:
determined by resistor ratio
insensitive to A, temperature, fab variations
2 1
2
IN
O
R R
AR
1
Av
v
+
+
=
( )
2
2 1
IN
R
R R
v
+
≈
gain
Demo
Suppose
6
10 A =
R 9 R
1
=
R R =
2
R R 9
R 10
1
v 10
v
6
IN
6
O
+
+
⋅
=
10 v v
IN O
⋅ ≈
10
1
10 1
v 10
6
IN
6
⋅ +
⋅
=
2 1
2
IN
R R
AR
Av
+
≈
6.002 Fall 2000 Lecture
10
19
e.g. v
IN
= 5V
Suppose I perturb the circuit…
(e.g., force v
O
momentarily to 12V somehow).
Stable point is when v
+
≈ v

.
Key: negative feedback Æ portion of
output fed to –ve input.
e.g. Car antilock brakes
Æ small corrections.
Why did this happen?
Insight:
+
–
R
IN O
v 2 v =
+
–
R
IN
v
+
v
−
v
negative
feedback
2
v
O
5V
5V
10V
0 i =
–
A
12V
6V
6V
6.002 Fall 2000 Lecture
11
19
Question: How to control a
highstrung device?
Antilock brakes
Michelin
no
yes
f
e
e
d
b
a
c
k
yes/no
is it
turning?
it’s
all about
control
d
i
s
c
v. v. powerful brakes
apply
release
6.002 Fall 2000 Lecture
12
19
More op amp insights:
Observe, under negative feedback,
0
A
v
R
R R
A
v
v v
IN
1
2 1
O
→
⎟
⎠
⎞
⎜
⎝
⎛ +
= = −
− +
− +
≈ v v
We also know
i
+
≈ 0
i

≈ 0
Æyields an easier analysis method
(under negative feedback).
6.002 Fall 2000 Lecture
13
19
Insightful analysis method
under negative feedback
+
–
1
R
O
v
+
–
2
R
IN
v
IN
v
c
2
2 1
IN O
R
R R
v v
+
=
g
IN
v
b
0 = i
e
2
IN
R
v
d
2
IN
R
v
f
0 i
0 i
v v
≈
≈
≈
−
+
− +
IN
v
a
6.002 Fall 2000 Lecture
14
19
Question:
+
–
O
v
+
–
IN
v
+
v
−
v
?
0
1
= R
∞ =
2
R
2
2 1
R
R R
v v
IN O
+
= or
with
IN O
v v ≈
IN
v
c
IN
v
b
IN
v
a
6.002 Fall 2000 Lecture
15
19
Buffer
voltage gain = 1
input impedance = ∞
output impedance = 0
current gain = ∞
power gain = ∞
+
–
O
v
+
–
IN
v
IN O
v v ≈
Why is this circuit useful?
6.002 Fall 2000 Lecture
1
2
6.002
CIRCUITS AND
ELECTRONICS
Basic Circuit Analysis Method
(KVL and KCL method)
6.002 Fall 2000 Lecture
2
2
0 =
∂
∂
t
B
φ
0 =
∂
∂
t
q
Outside elements
Inside elements
Allows us to create the lumped circuit
abstraction
wires
resistors
sources
Review
Lumped Matter Discipline LMD:
Constraints we impose on ourselves to simplify
our analysis
6.002 Fall 2000 Lecture
3
2
LMD allows us to create the
lumped circuit abstraction
Lumped circuit element
+

v
i
power consumed by element =
vi
Review
6.002 Fall 2000 Lecture
4
2
KVL:
loop
KCL:
node
0 =
∑
j
j
ν
0 =
∑
j
j
i
Review
Review
Maxwell’s equations simplify to
algebraic KVL and KCL under LMD!
6.002 Fall 2000 Lecture
5
2
KVL
0 = + +
bc ab ca
v v v
0 = + +
ba da ca
i i i
KCL
DEMO
1
R
2
R
4
R
5
R
3
R
a
b
d
c
+
–
Review
6.002 Fall 2000 Lecture
6
2
Method 1:
Basic KVL, KCL method of
Circuit analysis
Goal: Find all element v’s and i’s
write element vi relationships
(from lumped circuit abstraction)
write KCL for all nodes
write KVL for all loops
1.
2.
3.
lots of unknowns
lots of equations
lots of fun
solve
6.002 Fall 2000 Lecture
7
2
Method 1:
Basic KVL, KCL method of
Circuit analysis
For R,
For voltage source,
For current source,
Element Relationships
IR V =
0
V V =
0
I I =
3 lumped circuit elements
R
0
V
o
I
+ –
J
6.002 Fall 2000 Lecture
8
2
KVL, KCL Example
The Demo Circuit
+
–
1
R
2
R
4
R
5
R
3
R
a
b
d
c
0 0
V = ν
+
–
1
ν
+
–
5
ν
+
–
3
ν
+ –
2
ν
+
–
4
ν
+
–
6.002 Fall 2000 Lecture
9
2
Associated variables discipline
ν
i
+

Element e
Then power consumed
by element e
i ν = is positive
Current is taken to be positive going
into the positive voltage terminal
6.002 Fall 2000 Lecture
10
2
KVL, KCL Example
The Demo Circuit
+
–
1
R
2
R
4
R
5
R
3
R
a
b
d
c
0 0
V = ν
+
–
1
ν
+
–
5
ν
+
–
3
ν
+ –
1 L
2 L
4 L
3 L
2
ν
+
–
4
ν
+
–
2
i
1
i
0
i
5
i
3
i
4
i
6.002 Fall 2000 Lecture
11
2
Analyze
12 unknowns
5 0 5 0
, ι ι ν ν … …
1. Element relationships
3. KVL for loops
0 0
V v =
1 1 1
R i v =
2 2 2
R i v =
3 3 3
R i v =
4 4 4
R i v =
5 5 5
R i v =
given
2. KCL at the nodes
redundant
0
4 3 1
= − + v v v
0
2 1 0
= + + − v v v
0
2 5 3
= − + v v v
0
5 4 0
= + + − v v v redundant
0
4 1 0
= + + i i i
0
1 3 2
= − + i i i
0
4 3 5
= − − i i i
0
5 2 0
= − − − i i i
a:
b:
d:
e:
6 equations
3 independent
equations
3 independent
equations
1
2
u
n
k
n
o
w
n
s
1
2
e
q
u
a
t
i
o
n
s
/
u
g
h
@
#
!
( ) i v,
L1:
L2:
L3:
L4:
6.002 Fall 2000 Lecture
12
2
Other Analysis Methods
Method 2—
Apply element combination rules
B
C
D
⇔
N
R R R + + +
2 1
⇔
1
G
2
G
N
G
N
G G G + +
2 1
i
i
R
G
1
=
⇔
+ – + – + –
1
V
2
V
2 1
V V +
⇔
J J
1
I
2
I
2 1
I I +
J
A
1
R
2
R
3
R
N
R
…
Surprisingly, these rules (along with superposition, which
you will learn about later) can solve the circuit on page 8
6.002 Fall 2000 Lecture
13
2
Other Analysis Methods
Method 2—
Apply element combination rules
V
I
3 2
3 2
R R
R R
+
V
I
3 2
3 2
1
R R
R R
R R
+
+ =
+
–
V
? = I
1
R
3
R
2
R
+
–
+
–
R
Example
1
R
R
V
I =
6.002 Fall 2000 Lecture
14
2
1.
2.
3.
4.
5.
Select reference node ( ground)
from which voltages are measured.
Label voltages of remaining nodes
with respect to ground.
These are the primary unknowns.
Write KCL for all but the ground
node, substituting device laws and
KVL.
Solve for node voltages.
Back solve for branch voltages and
currents (i.e., the secondary unknowns)
Particular application of KVL, KCL method
Method 3—Node analysis
6.002 Fall 2000 Lecture
15
2
Example: Old Faithful
plus current source
0
V
1
R
2
R
4
R
5
R
3
R
J
1
I
0
V
+
–
1
e
2
e
Step 1
Step 2
6.002 Fall 2000 Lecture
16
2
Example: Old Faithful
plus current source
0 ) ( ) ( ) (
2 1 3 2 1 1 0 1
= + − + − G e G e e G V e
KCL at
1
e
0 ) ( ) ( ) (
1 5 2 4 0 2 3 1 2
= − + − + − I G e G V e G e e
KCL at
2
e
for
convenience,
write
i
i
R
G
1
=
0
V
1
R
2
R
4
R
5
R
3
R
J
1
e
1
I
0
V
+
–
2
e
Step 3
6.002 Fall 2000 Lecture
17
2
Example: Old Faithful
plus current source
0 ) ( ) ( ) (
2 1 3 2 1 1 0 1
= + − + − G e G e e G V e
KCL at
1
e
0 ) ( ) ( ) (
1 5 2 4 0 2 3 1 2
= − + − + − I G e G V e G e e
KCL at
2
l
move constant terms to RHS & collect unknowns
) ( ) ( ) (
1 0 3 2 3 2 1 1
G V G e G G G e = − + + +
1 4 0 5 4 3 2 3 1
) ( ) ( ) ( I G V G G G e G e + = + + + −
i
i
R
G
1
=
2 equations, 2 unknowns Solve for e’s
(compare units)
0
V
1
R
2
R
4
R
5
R
3
R
J
1
e
1
I
0
V
+
–
2
e
Step 4
6.002 Fall 2000 Lecture
18
2
In matrix form:
+
=
+ + −
− + +
1 0 4
0 1
2
1
5 4 3 3
3 3 2 1
I V G
V G
e
e
G G G G
G G G G
conductivity
matrix
unknown
node
voltages
sources
( )( )
2
3 5 4 3 3 2 1
1 0 4
0 1
3 2 1 3
3 5 4 3
2
1
G G G G G G G
I V G
V G
G G G G
G G G G
e
e
− + + + +
+
+ +
+ +
=
Solve
( )( ) ( )( )
5
G
3
G
4
G
3
G
2
3
G
5
G
2
G
4
G
2
G
3
G
2
G
5
G
1
G
4
G
1
G
3
G
1
G
1
I
0
V
4
G
3
G
0
V
1
G
5
G
4
G
3
G
1
e
+ + + + + + + +
+ + + +
=
( )( ) ( )( )
5 3 4 3
2
3 5 2 4 2 3 2 5 1 4 1 3 1
1 0 4 3 2 1 0 1 3
2
G G G G G G G G G G G G G G G G G
I V G G G G V G G
e
+ + + + + + + +
+ + + +
=
(same denominator)
Notice: linear in , , no negatives
in denominator
0
V
1
I
6.002 Fall 2000 Lecture
19
2
Solve, given
K 2 . 8
1
G
G
5
1
=
)
`
¹
K 9 . 3
1
G
G
4
2
=
)
`
¹
K 5 . 1
1
G
3
=
0
1
= I
( )( )
( ) ( )
2
3
G
5
G
4
G
3
G
3
G
2
G
1
G
1
I
0
V
4
G
3
G
2
G
1
G
0
V
1
G
3
G
2
e
− + + + + +
+ + + +
=
1
5 . 1
1
9 . 3
1
2 . 8
1
3
G
2
G
1
G = + + = + +
1
2 . 8
1
9 . 3
1
5 . 1
1
G G G
5 4 3
= + + = + +
0
2
2
V
5 . 1
1
1
9 . 3
1
1
5 . 1
1
2 . 8
1
e
−
× + ×
=
0 2
6 . 0 V e =
If
, then
V V 3
0
=
0 2
8 . 1 V e =
Check out the
DEMO
6.002 Fall 2000 Lecture
1
20
6.002
CIRCUITS AND
ELECTRONICS
Operational Amplifier Circuits
6.002 Fall 2000 Lecture
2
20
Operational amplifier abstraction
Building block for analog systems
We will see these examples:
Digitaltoanalog converters
Filters
Clock generators
Amplifiers
Adders
Integrators & Differentiators
Reading: Chapter 15.5 & 15.6 of A & L.
+
–
Review
∞ input resistance
0 output resistance
Gain “A” very large
6.002 Fall 2000 Lecture
3
20
Consider this circuit:
−
+
≈
+
=
v
R R
R
v v
2 1
2
1
1
2
R
v v
i
−
−
=
2
iR v v
OUT
− =
−
2
1
2
R
R
v v
v ⋅
−
− =
−
−
1
2
2
1
2
1
R
R
v
R
R
v −
⎥
⎦
⎤
⎢
⎣
⎡
+ =
−
1
2
2
1
2 1
2 1
2
1
R
R
v
R
R R
R R
R
v −
+
⋅
+
=
( )
2 1
1
2
v v
R
R
− =
subtracts!
+
–
2
R
+
–
1
R
+
–
1
R
2
R
+
v
−
v
i
i
OUT
v
+
–
1
v
2
v
6.002 Fall 2000 Lecture
4
20
Another way of solving —
use superposition
1
2 1
1
R
R R
v v
OUT
+
⋅ =
+
1
2 1
2 1
2 1
R
R R
R R
R v +
⋅
+
⋅
=
1
2
1
R
R
v =
2
1
2
2
v
R
R
v
OUT
− =
+
–
2 1
 R R
+
–
1
R
2
R
2
OUT
v
2
v
+
–
+
–
1
R
2
R
1
OUT
v
1
v
2
R
+
v
1
R
2 1
OUT OUT OUT
v v v + =
( )
2 1
1
2
v v
R
R
− =
0
1
→ v 0
2
→ v
Still subtracts!
6.002 Fall 2000 Lecture
5
20
Let’s build an intergrator…
dt i
C
1
v
t
O
∫
∞ −
=
Let’s start with the following insight:
v
O
is related to dt i
∫
I
v
+
–
O
v
+
–
∫
dt
i
+
–
i
+
–
O
v
C
But we need to somehow convert
voltage v
I
to current.
6.002 Fall 2000 Lecture
6
20
But, v
O
must be very small compared
to v
R
, or else
R
v
i
I
≠
When is v
O
small compared to v
R
?
First try… use resistor
i
R
v
I
→
O
O
v
dt
dv
RC >> when
I
O
v
dt
dv
RC ≈
dt v
RC
1
v
t
I O
∫
∞ −
≈ or
I O
O
v v
dt
dv
RC = +
R
v
larger the RC,
smaller the v
O
for good
integrator
ωRC >> 1
I
v
+
–
i
+
–
O
v
C
R
v
+
–
R
Demo
6.002 Fall 2000 Lecture
7
20
There’s a better way…
R
v
i
I
=
so,
+
–
+
–
R
I
v
+
–
+
–
R
R
v
I
I
v
C
v
+
–
+
–
O
v
i
i
under negative feedback V 0 v ≈
−
Notice
C O
v v − =
dt
R
v
C
1
v
t
I
O
∫
∞ −
− =
We have our integrator.
+
–
6.002 Fall 2000 Lecture
8
20
Now, let’s build a differentiator…
I
v
+
–
O
v
+
–
dt
d
But we need to somehow convert current
to voltage.
i is related to
dt
dv
I
Let’s start with the following insights:
dt
dv
C i
I
=
+
–
I
v
i
C
6.002 Fall 2000 Lecture
9
20
Demo
C I
v v =
dt
dv
C i
I
=
dt
dv
RC v
I
O
− =
Recall
+
–
i
i
current
to
voltage
iR v
O
− =
V 0
+
–
+
–
R
I
v +
–
O
v
C
C
v
i
Differentiator…
+
–
i
+
–
R
v
O
6.002 Fall 2000 Lecture
1
21
6.002
CIRCUITS AND
ELECTRONICS
Op Amps Positive Feedback
6.002 Fall 2000 Lecture
2
21
Consider this circuit — negative feedback
+
–
+
–
1
R
1
R
v
IN
IN
v
+
–
IN OUT
v
R
R
v
1
2
− =
2
R
What’s the difference?
Consider what happens when there is a pertubation…
Positive feedback drives op amp into saturation:
S OUT
V v ± →
and this — positive feedback
+
–
+
–
1
R
IN
v
+
–
2
R
IN OUT
v
R
R
v
1
2
− =
“ ”
s
e
e
a
n
a
l
y
s
i
s
o
n
n
e
x
t
p
a
g
e
Negative vs Positive Feedback
6.002 Fall 2000 Lecture
3
21
+
–
+
–
1
R
IN
v
2
R
OUT
v
( )
− +
− = v v A v
OUT
+ ⋅
+
−
=
IN 1
2 1
IN OUT
v R
R R
v v
A
IN
2 1
IN 1
OUT
2 1
1
Av
R R
v AR
v
R R
AR
+
+
−
+
=
+
= Av
IN
1
2
IN
2 1
1
2 1
1
OUT
v
R
R
Av
R R
AR
R R
R
1
v − = ⋅
+
−
+
−
=
+
− =
+
−
2 1
1
IN
2 1
1
OUT
R R
R
1 A v
R R
AR
1 v
+
–
1
R
IN
v
2
R
OUT
v
+
v
−
v
( )
− +
− v v A
+
–
Static Analysis of Positive Feedback Ckt
6.002 Fall 2000 Lecture
4
21
Representing dynamics of op amp…
+
v
−
v
o
v
*
Av
+
–
+
–
*
v
) (
− +
−v v
R
C
+
–
6.002 Fall 2000 Lecture
5
21
Representing dynamics of op amp…
Consider this circuit and let’s analyze its
dynamics to build insight.
+
–
1
R
2
R
o
v
3
R
4
R
Let’s develop equation representing time
behavior of v
o
.
Circuit model
1
R
2
R
3
R
4
R
+
–
*
v
) (
− +
−v v
R
C
+
–
+
–
+
–
o
v
+
v
−
v
A
v
o
6.002 Fall 2000 Lecture
6
21
A
v
v Av v
o
o
= =
* *
or
) γ γ ( A
RC
T where 0
T
v
dt
dv
o o
+
−
−
= = + or
o
o
v
R R
R v
v
+
=
+
=
+
γ
2 1
1
o
o
v
R R
R v
v
−
=
+
=
−
γ
4 3
3
0 ) γ γ ( =
+
−
−
+
o
o
v
RC
A
dt
dv
1
time
−
0 ) γ γ (
1
=
+
−
−
+ +
o
o
v
RC
A
RC dt
dv
or
neglect
_ *
*
v v v
dt
dv
RC − = +
+
o
v ) γ γ (
−
−
+
=
Dynamics of op amp…
_
v v
A
v
dt
dv
A
RC
o o
− = +
+
0 ) 0 ( v
o
=
6.002 Fall 2000 Lecture
7
21
Consider a small disturbance to v
o
(noise).
Now, let’s build some useful circuits with
positive feedback.
+
>
−
γ γ if
stable e K v
positive is T
T
t
o
−
=
−
>
+
γ γ if
unstable e K v
negative is T
T
t
o
=
−
=
+
γ γ if
neutral K v
large very is T
o
=
o
v
t
neutral
stable
K
disturbance
unstable
6.002 Fall 2000 Lecture
8
21
One use for instability: Build on the
basic op amp as a comparator
+
–
+
v
o
v
S
V +
S
V −
−
v
− +
− v v
o
v
S
V +
S
V −
0
t
0 v →
−
+
v
o
v
6.002 Fall 2000 Lecture
9
21
Now, use positive feedback
+
–
2
R
o
v
1
R
i
v
2 1
1
R R
R v
v
o
+
=
+
5 . 7 v =
+
5 . 7 v − =
−
15 v
o
=
15 v
o
− =
15
e.g.
2 1
=
=
S
V
R R
5 . 7 v
5 . 7 ) v v (
i
>
> =
−
−
5 . 7 − <
<
−
+ −
v
v v
i
v
6.002 Fall 2000 Lecture
10
21
Now, use positive feedback
+
–
2
R
o
v
1
R
i
v
2 1
1
R R
R v
v
o
+
=
+
2 1
1
R R
R V
v
S
+
=
+
2 1
1
R R
R V
v
S
+
−
=
−
S o
V v + =
15
S o
V v − =
15 −
15
e.g.
2 1
=
=
S
V
R R
5 . 7 v
v ) v v (
i
>
> =
−
+ −
5 . 7 − <
<
−
+ −
v
v v
i
v
6.002 Fall 2000 Lecture
11
21
Why is hysteresis useful?
e.g., analog
to digital
o
v
i
v
S
V
S
V −
0 5 . 7 5 . 7 −
15 −
15
hysteresis
Demo
Demo
t
i
v
5 . 7
5 . 7 −
o
v
6.002 Fall 2000 Lecture
12
21
Without hysteresis
analog
to digital
t
i
v
5 . 7
5 . 7 −
i
v
o
v
6.002 Fall 2000 Lecture
13
21
Oscillator — can create a clock
Demo
+
–
R
C
v
1
R
1
R
o
v
2
o
v
C
0
0 at
=
= =
C
S o
v
t V v Assume
t
S
V
S
V −
2
S
V
2
S
V
−
o
v
+
v
+
v
−
v
−
v
C
v
−
v
−
v
C
v
6.002 Fall 2000 Lecture
14
21
We built an oscillator using an op amp.
t
Why do we use a clock in a digital system?
(See page 735 of A & L)
sender receiver
1 1 0
a 1,1,0?
b When is the signal valid?
Æ Discretization of time
one bit of information associated with
an interval of time (cycle)
Clocks in Digital Systems
can use as a clock
common timebase  when to “look” at a signal
(e.g. whenever the clock is high)
clock
6.002 Fall 2000 Lecture
1
22
6.002
CIRCUITS AND
ELECTRONICS
Energy and Power
6.002 Fall 2000 Lecture
2
22
Why worry about energy?
small batteries
Æ good
Today:
How long will the battery last?
in standby mode
in active use
Will the chip overheat and selfdestruct?

6.002 Fall 2000 Lecture
3
22
Look at energy dissipation in
MOSFET gates
Let us determine
standby power
active use power
Let’s work out a few related examples first.
C: wiring capacitance and
C
GS
of following gate
V
S
C
R
O
v
+
–
I
v
+
–
6.002 Fall 2000 Lecture
4
22
Example 1:
Power
Energy dissipated in time T
R
V
VI P
2
= =
VIT E =
+
–
R
I
V
+
–
V
6.002 Fall 2000 Lecture
5
22
Example 1:
for our gate
ON L
S
R R
V
P
+
=
2
0 = P
O
v
S
V
ON
R
L
R
I
v high
S
V
ON
R
L
R
O
v
I
v
low
6.002 Fall 2000 Lecture
6
22
Example 2:
Consider
Find energy dissipated in each cycle.
Find average power .
P
S
V
+
–
1
R
C
2
R
1
S
2
S
open S
closed S
2
1
t
closed S
open S
2
1
1
T
2
T
T
6.002 Fall 2000 Lecture
7
22
T
1
: S
1
closed, S
2
open
t
C
v
S
V
C R
t
1
S
1
e
R
V
−
t
i
1
S
R
V
+
–
C
v
+
–
1
R
C
S
V
i
assume
v
C
= 0 at t = 0
6.002 Fall 2000 Lecture
8
22
Total energy provided by source during T
1
dt i V E
1
T
0
S
∫
=
dt e
R
V
C R
t
T
0
1
2
S
1
1
−
∫
=
1
1
T
0
C R
t
1
1
2
S
e C R
R
V
−
− =


.

\

− =
−
C R
T
2
S
1
1
e 1 V C
1
2
S 1
2
S
R in dissipated V C
2
1
E
, C on stored V C
2
1
=
C R T if V C
1 1
2
S
>> ≈
I.e., if we wait long enough
Independent
of R!
6.002 Fall 2000 Lecture
9
22
T
2
: S
2
closed, S
1
open
+
–
C
v
2
R
C
So, initially,
2
S
CV
2
1
= energy stored in capacitor
Assume T
2
>> R
2
C
So, capacitor discharges ~fully in T
2
So, energy dissipated in R
2
during T
2
2
S 2
CV
2
1
E =
E
1
, E
2
independent of R
2
!
Initially, v
C
= V
S
(recall T
1
>> R
1
C)
6.002 Fall 2000 Lecture
10
22
Putting the two together:
Energy dissipated in each cycle
2
S
2
S
CV
2
1
CV
2
1
+ =
2 1
E E E + =
C g dischargin & charging
in dissipated energy CV E
2
S
=
Assumes C charges and discharges fully.
frequency
T
f
1
=
T
E
P =
T
CV
S
2
=
f CV
S
2
=
Average power
6.002 Fall 2000 Lecture
11
22
Back to our inverter —
O
v
IN
v
C
S
V
L
R
ON
R
t
2
T
T
2
T
IN
v
f
T
1
=
What is for the following input? P
6.002 Fall 2000 Lecture
12
22
Equivalent Circuit
S
V
+
–
L
R
C
ON
R
t
2
T
T
2
T
IN
v
f
T
1
=
What is for the following input? P
6.002 Fall 2000 Lecture
13
22
We can show (see section 12.2 of A & L)
( )
( )
2
ON L
2
L
2
S
ON L
2
S
R R
R
f CV
R R 2
V
P
+
+
+
=
f CV
R 2
V
P
2
S
L
2
S
+ =
when R
L
>> R
ON
What is for gate? P
r
e
m
e
m
b
e
r
r
e
m
e
m
b
e
r
STATIC
P
DYNAMIC
P
related to switching
capacitor
independent of f.
MOSFET ON half
the time.
6.002 Fall 2000 Lecture
14
22
f CV
R
V
P
S
L
S
2
2
2
+ =
when R
L
>> R
ON
In standby mode,
half the gates in a
chip can be
assumed to be on.
So per
gate is still .
Relates to standby
power.
STATIC
P
L
2
S
R 2
V
What is for gate? P
In standby mode,
f Æ0 ,
so dynamic power
is 0
6.002 Fall 2000 Lecture
15
22
Some numbers…
a chip with 10
6
gates clocking
at 100 MHZ
V 5 V
10 100 f
k 10 R
F f 1 C
S
6
L
=
× =
Ω =
=
× × × +
×
=
− 6 15
4
6
10 100 25 10
10 2
25
10 P
  microwatts 5 . 2 milliwatts 25 . 1 10
6
+ =
problem!
1.25KW! 2.5W
not bad
mW 150 W 5 . 2
V 1 V 5
V reduce
f
V
S
2
S
→
→
α
α
next
lecture
must get rid of this
6.002 Fall 2000 Lecture
1
23
6.002
CIRCUITS AND
ELECTRONICS
Energy, CMOS
6.002 Fall 2000 Lecture
2
23
Reading: Section 11.5 of A & L.
S
V
+
–
1
R
C
2
R
1
S
2
S
f
T T T
1
2 1
= + =
f CV P
S
2
=
T
1
: closed
T
2
: open
open
closed
ON L
S
R R
V
P
+
=
2
O
v
S
V
ON
R
L
R
I
v
Review
6.002 Fall 2000 Lecture
3
23
Inverter —
O
v
I
v
C
S
V
L
R
ON
R
f CV
R
V
P
S
L
S
2
2
2
+ =
related to switching
capacitor.
independent of f.
MOSFET ON half
the time.
STATIC
P
DYNAMIC
P
constant time
" RC "
2
T
R R
ON L
>>
>>
Square wave input
f
T
1
=
Demo
Review
In standby mode, half
the gates in a chip can
be assumed to be on.
So per gate is
still .
STATIC P
L
2
S
R 2
V
In standby mode,
f Æ0 ,
so dynamic power is 0
6.002 Fall 2000 Lecture
4
23
f CV
R
V
P
S
L
S
2
2
2
+ =
Chip with 10
6
gates clocking at 100 MHz
V 5 V , 10 100 f , K 10 R F, f 1 C
S
6
L
= × = Ω = =
problem!
1.25KWatts 2.5Watts
not bad
+
• independent of f
• also standby power
(assume ½ MOSFETs
ON if f Æ0)
• must get rid of this!
• αf
• αV
S
2
reduce V
S
5VÆ1V
2.5VÆ150mW
[ ] watts 5 . 2 milliwatts 25 . 1 10
6
μ + =
⎥
⎦
⎤
⎢
⎣
⎡
× × × +
× ×
=
− 6 2 15
3
2
6
10 100 5 10
10 10 2
5
10 P
gates
Review
6.002 Fall 2000 Lecture
5
23
How to get rid of static power
Intuition:
O
v
S
V
ON
R
L
R
I
v high low
i
idea!
O
v
S
V
I
v high low
S
V
L
R
O
v
I
v
low
off
MOSFET
high
6.002 Fall 2000 Lecture
6
23
New Device PFET
• Nchannel MOSFET (NFET)
D
S
G
on when v
GS
≥ V
TN
off when v
GS
< V
TN
e.g. V
TN
= 1V
• Pchannel MOSFET (PFET)
on when v
GS
≤ V
TP
off when v
GS
> V
TP
e.g. V
TP
= 1V
S
D
G
ON when
less than 4V
5V
6.002 Fall 2000 Lecture
7
23
Consider this circuit:
S
D
G
D
S
G
O
v
I
v
+
–
S
V
PU = pull up
PD = pull down
works like an inverter!
IN OUT
6.002 Fall 2000 Lecture
8
23
Consider this circuit:
v
I
= 0V (input low)
V 5
v
O
=
V 5 V
S
=
V 0 v
I
=
+
–
p
ON
R
v
I
= 5V (input high)
V 0
v
O
=
V 5 V
S
=
V 5 v
I
=
+
–
n
ON
R
Called “CMOS logic”
Complementary
MOS
(our previous logic was called “NMOS”)
works like an inverter!
IN OUT
6.002 Fall 2000 Lecture
9
23
O
v
I
v
S
V
C
t
T
I
v
T
f
1
=
From f CV P
S
2
=
Key: no path from V
S
to GND!
no static power!
Let’s compute DYNAMIC
P
S
V
+
–
p
ON
R
C
n
ON
R
closed for
v
I
low
closed for
v
I
high
6.002 Fall 2000 Lecture
10
23
For our previous example —
1 , MHz 100 f , V 5 V F, f 1 C
S
= = =
“keep
all
else
same”
f CV P
S
2
=
6 2 15
10 100 5 10 × × × =
−
gate per μwatts 5 . 2 =
chip gate 10 for μwatts 5 . 2
6
= P
P
PIII?
~240
watts 1.2 GHz 8x10
6
PIV?
~1875
watts 3 GHz 25x10
6
PII?
~30
watts
600
MHz 2x10
6
PII?
~15
watts
300
MHz 2x10
6
Pentium?
~2.5
watts
100
MHz 10
6
f Gates
g
a
s
p
!
6.002 Fall 2000 Lecture
11
23
and use big heatsink
How to reduce power
A V
S
5V Æ 3V Æ 1.8V Æ 1.5V
~PIV Æ 170 watts Æ better, but high
Æ Æ next time:
power supply
B Turn off clock when not in use.
C Change V
S
depending on need.
6.002 Fall 2000 Lecture
12
23
CMOS Logic
NAND:
Z A B
0 0 1
0 1 1
1 0 1
1 1 0
S
D
G
V 0
on
V 5
S
D
G
V 5
off
V 5
A
S
V
B
A B
Z
6.002 Fall 2000 Lecture
13
23
B A B A F + = ⋅ = e.g.
In general, if we want to implement F
short when
A = 0 or B = 0,
open otherwise
short when
A · B is true,
else open
A
B
short
when F
is true,
else open
S
V
Z
short
when F
is true,
else open
r
e
m
e
m
b
e
r
D
e
M
o
r
g
a
n
’
s
l
a
w
6.002 Fall 2000 Lecture
1
24
6.002
CIRCUITS AND
ELECTRONICS
Power Conversion Circuits
and Diodes
6.002 Fall 2000 Lecture
2
24
Power Conversion Circuits (PCC)
Power efficiency of converter important,
so use lots of devices:
MOSFET switches, clock circuits,
inductors, capacitors, op amps, diodes
Reading: Chapter 16 and 4.4 of A & L.
PCC
110V
60Hz
+
–
5V DC
solar cells,
battery
PCC
+
–
5V DC
3V
DC
DCtoDC UP converter
R
6.002 Fall 2000 Lecture
3
24
First, let’s look at the diode
Can use this exponential model with
analysis methods learned earlier
analytical graphical incremental
(Our fake expodweeb was modeled after this device!)
D
v
D
i
D
v
D
i
S
I − mV
V
D
v
+
–
D
i
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
− = 1 e I i
T
D
V
v
S D
A 10 I
12
S
−
=
V 025 . 0 V
T
=
q
T k
V
T
=
Boltzmann’s constant
temperature in Kelvins
charge of an electron
6.002 Fall 2000 Lecture
4
24
Another analysis method:
piecewise–linear analysis
P–L diode models:
D
v
D
i
0
Ideal diode model
Æ i
D
= 0
“open”
or
off
v
D
< 0
Æ v
D
= 0
“short”
or
on
i
D
≥ 0
6.002 Fall 2000 Lecture
5
24
D
v
D
i
V 6 . 0
0 v
D
=
0 i
D
=
“Practical” diode model
ideal with offset
V 6 . 0
+
–
Another analysis method:
piecewise–linear analysis
Open segment
Short segment
6.002 Fall 2000 Lecture
6
24
Another analysis method:
piecewise–linear analysis
Replace nonlinear characteristic with
linear segments.
Perform linear analysis within each
segment.
Piecewise–linear analysis method
6.002 Fall 2000 Lecture
7
24
(We will build up towards an ACtoDC converter)
R
O
v
+
–
+
–
I
v
V 6 . 0
+
–
Example
Consider
v
I
is a sine wave
6.002 Fall 2000 Lecture
8
24
0 v
O
=
0 i
D
=
“Open segment”:
R
+
–
I
v
+
–
+
–
V 6 . 0
6 . 0 v
I
<
R
O
v
+
–
+
–
I
v
( ) R / 6 . 0 v i
I D
− =
6 . 0 v v
I O
− =
“Short segment”:
R
+
–
+
–
+
–
V 6 . 0
6 . 0 v
I
≥
I
v
Example
V 6 . 0
+
–
Equivalent
circuit
6.002 Fall 2000 Lecture
9
24
Example
t
6 . 0
I
v
O
v
6.002 Fall 2000 Lecture
10
24
Now consider — a halfwave rectifier
I
v
R
O
v
+
–
+
–
V 6 . 0
+
–
C
6.002 Fall 2000 Lecture
11
24
A halfwave rectifier
t
diode on diode off
C
current
pulses
charging
capacitor
MIT’s supply shows
“snipping” at the peaks
(because current drawn
at the peaks)
I
v
O
v
Demo
6.002 Fall 2000 Lecture
12
24
DCtoDC UP Converter
The circuit has 3 states:
I. S is on, diode is off
i increases linearly
II. S turns off, diode turns on
C charges up, v
O
increases
III. S is off, diode turns off
C holds v
O
(discharges into load)
t
S
v
S
closed
S
open
T
p
T
O
v
+
–
+
–
DC
I
V
C
S
v
load
i
switch
S
D
o
n
o
t
u
s
e
r
e
s
is
t
iv
e
e
le
m
e
n
t
s
!
6.002 Fall 2000 Lecture
13
24
More detailed analysis
I. Assume i(0) = 0, v
O
(0) > 0
S on at t = 0, diode off
+
–
I
V
C
i
L
O
v
t
i
L
T V
T i
I
= ) (
T
dt
di
L V
I
=
i is a ramp
L
V
I
= slope
2
) T ( Li
2
1
: T t at stored energy E = = Δ
L
T V
E
I
2
2
2
= Δ
6.002 Fall 2000 Lecture
14
24
II. S turns off at t = T
diode turns on (ignore diode voltage drop)
+
–
I
V
C
L
O
v
S
i
Diode turns off at T′ when i tries to go negative.
t
i
T
0
L
T V
I
LC
O
1
= ω
T
′
P
T
State III starts here
6.002 Fall 2000 Lecture
15
24
II. S turns off at t = T, diode turns on
Diode turns off at T′ when I tries to go negative.
LC
O
1
= ω
ignore
diode
drop
) (T v
O
O
v
T
′
t
T
0
Capacitor voltage
P
T
O
v Δ
t
i
T
0
L
T V
I
T
′
P
T
LC
O
1
= ω
III.
Let’s look at the voltage profile
6.002 Fall 2000 Lecture
16
24
II. S turns off at t = T, diode turns on
Diode turns off at T′ when I tries to go negative.
LC
O
1
= ω
ignore
diode
drop
) (T v
O
O
v
T
′
t
T
0
Capacitor voltage
P
T
O
v Δ
t
i
T
0
L
T V
I
T
′
P
T
LC
O
1
= ω
III.
Let’s look at the voltage profile
6.002 Fall 2000 Lecture
17
24
III. S is off, diode turns off
C holds v
O
after T′
i is zero
+
–
I
V
C
S
O
v
+
–
Eg, no load
O
v
T
′
t
0
Capacitor voltage
P
T
6.002 Fall 2000 Lecture
18
24
III. S is off, diode turns off
C holds v
O
after T′
i is zero
until S turns ON at T
P
, and cycle repeats
I II III I II III …
Thus, v
O
increases each cycle, if there is no load.
t
O
v
) (n v
O
P
T 2
P
T 3
+
–
I
V
C
S
O
v
+
–
Eg, no load
P
T
6.002 Fall 2000 Lecture
19
24
What is v
O
after n cycles Æ v
O
(n) ?
Use energy argument … (KVL tedious!)
Each cycle deposits ∆E in capacitor.
2
) T t ( i L
2
1
E = = Δ
2
I
L
T V
L
2
1
⎟
⎠
⎞
⎜
⎝
⎛
=
L
T V
2
1
E
2
2
I
= Δ
After n cycles, energy on capacitor
L 2
T nV
E n
2
2
I
= Δ
This energy must equal
2
O
) n ( Cv
2
1
or
LC
T nV
) n ( v
2
2
I
O
=
LC
1
O
= ω
n T V ) n ( v
O I O
ω =
so,
L 2
T nV
) n ( Cv
2
1
2
2
I
2
O
=
6.002 Fall 2000 Lecture
20
24
How to maintain v
O
at a given value?
recall
L
T V
E
I
2
2
2
= Δ
Another example of negative feedback:
( )
( ) ↑ ↓ −
↓ ↑ −
T v v
T v v
ref O
ref O
then if
then if
O
v
+
–
+
–
I
V
load
control
change T
T
p
T
pwm
+
ref
v
compare
–
O
v
6.002 Fall 2000 Lecture
1
25
6.002
CIRCUITS AND
ELECTRONICS
Violating the Abstraction Barrier
6.002 Fall 2000 Lecture
2
25
Case 1: The Double Take
Problem
R
i
V
O
V
“0” Æ “1”
t
O
V
“0”
“1”
t
O
V
“0”
“1”
observed expected
in forbidden region!
huh?
6.002 Fall 2000 Lecture
3
25
(a) DC case
R
i
V
O
V
1
V
very high
impedance,
like open
circuit
OK
DC V 5 V
i
=
DC V 5 V
O
=
DC V 5 V
1
=
6.002 Fall 2000 Lecture
4
25
t
V 5 . 2 =
O
V
t
i
V
(b) Step
not ok!
t
1
V
looks ok!
b.1
b.3
b.2
V 0
V 5
0 = t
0 = t
0 = t T
T 2
V 5
V 5
R
i
V
O
V
1
V
very high
impedance,
like open
circuit
O
V
6.002 Fall 2000 Lecture
5
25
R
i
V
. . . .
instantaneous R divider
finite propagation speed
of signals
characteristic
impedance
→ R
T 2
T
5
2.5
0
V 5
0
V 5
0
V 5
6.002 Fall 2000 Lecture
6
25
Question: So why did our circuits work?
More in 6.014
t
V 5
V 5 . 2
3. Termination
P
a
r
a
l
l
e
l
t
e
r
m
i
n
a
t
i
o
n
D
E
M
O
a
d
d
R
a
t
t
h
e
e
n
d
0
V
O
2. Keep wires short
t
V 5
0
0
V
O
D
E
M
O
u
s
e
s
m
a
l
l
w
i
r
e
“
S
o
u
r
c
e
T
e
r
m
i
n
a
t
i
o
n
”
1. Look only at V
1
t
0 T
V 5
0
V
1
D
E
M
O
6.002 Fall 2000 Lecture
7
25
Case 2: The Double Dip
Problem Æ strange spikes on supply
driving a 50 Ω
resistor!
V
0
1
0
1
OK
Why?
input
driving a 50 Ω
resistor!
V
0
6.002 Fall 2000 Lecture
8
25
V
dt
Ldi
Drop across inductor
Inverter current
v inductor
solution 1. short wires
2. low inductance wires
3. avoid big current swings
V
S
V
S
6.002 Fall 2000 Lecture
9
25
Case 3: The Double Team, or,
Slower may be faster!
Problem
a given chip
worked,
but was slow.
Let’s try speeding it up by using stronger
drivers
actual
ideal
ideal
C
Disaster!
L
ω
actual
6.002 Fall 2000 Lecture
10
25
Why?
Consider
crosstalk!
1
R
0
R
DEMO
2
R
C
dt
dV
α
DEMO
ok
dt
dV
C
6.002 Fall 2000 Lecture
11
25
How does this relate to chip?
Load output!
— put cap on outputs of chip
— jitter edges
— slew edges
dt
dV
small
DEMO
Solution
6.002 Fall 2000 Lecture
12
25
Case 4: The Double Jump
Careful abstraction violation for the
better…
Recall
o
V
i
V
o
V
i
V
expect
but, observe
o
V
i
V
6.002 Fall 2000 Lecture
13
25
Case 4: The Double Jump
Careful abstraction violation for the
better…
i
V
V 5
5V
0V
3V 5V+
3V
So, pullup has
stronger drive
as output rises
6.002 Fall 2000 Lecture
1
3
6.002
CIRCUITS AND
ELECTRONICS
Superposition, Thévenin and Norton
6.002 Fall 2000 Lecture
2
3
0 =
∑
loop
i
V
Review
Circuit Analysis Methods
z Circuit composition rules
z Node method – the workhorse of 6.002
KCL at nodes using V ’s referenced
from ground
(KVL implicit in “ ”)
( )
j i
e e − G
z KVL: KCL:
0 =
∑
node
i
I
VI
6.002 Fall 2000 Lecture
3
3
Consider
Linearity
Write node equations –
V
I
1
R
2
R
+
–
J
0
2 1
= − +
−
I
R
e
R
V e
Notice:
linear in
I V e , ,
VI , eV No
terms
e
6.002 Fall 2000 Lecture
4
3
Consider
Linearity
Write node equations 
Rearrange 
V
I
1
R
2
R
+
–
J
0
2 1
= − +
−
I
R
e
R
V e
I
R
V
e
R R
+ =
+
1 2 1
1 1
G e
S
=
conductance
matrix
node
voltages
linear sum
of sources
linear in
I V e , ,
6.002 Fall 2000 Lecture
5
3
Linearity
or I
R R
R R
V
R R
R
e
2 1
2 1
2 1
2
+
+
+
=
… … + + + + + =
2 2 1 1 2 2 1 1
I b I b V a V a e
Write node equations 
Rearrange 
0
2 1
= − +
−
I
R
e
R
V e
I
R
V
e
R R
+ =
+
1 2 1
1 1
G e
S
=
conductance
matrix
node
voltages
linear sum
of sources
linear in
I V e , ,
Linear!
6.002 Fall 2000 Lecture
6
3
Linearity
Homogeneity
Superposition
⇒
6.002 Fall 2000 Lecture
7
3
Linearity
Homogeneity
Superposition
Homogeneity
1
x
2
x
y
.
.
.
1
x α
2
x α
y α
.
.
.
⇓
⇒
6.002 Fall 2000 Lecture
8
3
Linearity
Homogeneity
Superposition
Superposition
a
x
1
a
x
2
a
y
.
.
.
.
.
.
b
x
1
b
x
2
b
y
⇒
b a
x x
1 1
+
b a
x x
2 2
+
b a
y y +
⇓
.
.
.
6.002 Fall 2000 Lecture
9
3
Linearity
Homogeneity
Superposition
Specific superposition example:
1
V
0
1
y
0
2
V
2
y
0
1
+ V
2
0 V +
2 1
y y +
⇓
⇒
6.002 Fall 2000 Lecture
10
3
Method 4: Superposition method
The output of a circuit is
determined by summing the
responses to each source
acting alone.
i
n
d
e
p
e
n
d
e
n
t
s
o
u
r
c
e
s
o
n
l
y
6.002 Fall 2000 Lecture
11
3
i
+
–
0 = V
+

v
i
short
+

v
i
0 = I
J
+

v
i
open
+

v
6.002 Fall 2000 Lecture
12
3
Back to the example
Use superposition method
V
I
1
R
2
R
+
–
J
e
6.002 Fall 2000 Lecture
13
3
Back to the example
Use superposition method
V acting alone
V
0 = I
2
R
+
–
e
1
R
I acting alone
0 = V
I
1
R
2
R
J
e
V
R R
R
e
V
2 1
2
+
=
I
R R
R R
e
I
2 1
2 1
+
=
I
R R
R R
V
R R
R
e e e
I V
2 1
2 1
2 1
2
+
+
+
= + =
sum superposition
Voilà !
6.002 Fall 2000 Lecture
14
3
salt
water
output shows
superposition
Demo
constant
+
–
sinusoid
+
–
?
6.002 Fall 2000 Lecture
15
3
Consider
Yet another method…
resistors
no
units
By setting
0
, 0
=
= ∀
i
I
n n
0
, 0
=
= ∀
i
V
m m
All
0
, 0
= ∀
= ∀
m m
n n
V
I
J
+
–
m
V
n
I
A
r
b
i
t
r
a
r
y
n
e
t
w
o
r
k
N
By superposition
Ri I V v
n
n
n m
m
m
+ + =
∑ ∑
β α
+

v J
i
i
resistance
units
independent of external
excitation and behaves like a
voltage “ ”
TH
v
also
independent
of external
excitement &
behaves like
a resistor
6.002 Fall 2000 Lecture
16
3
Or
i R v v
TH TH
+ =
As far as the external world is concerned
(for the purpose of IV relation),
“Arbitrary network N” is indistinguishable
from:
i
+
–
TH
R
TH
v
J
+

v
Thévenin
equivalent
network
TH
R
TH
v open circuit voltage
at terminal pair (a.k.a. port)
resistance of network seen
from port
( ’s, ’s set to 0)
m
V
n
I
N
6.002 Fall 2000 Lecture
17
3
Method 4:
The Thévenin Method
Replace network N with its Thévenin
equivalent, then solve external network E.
E
Thévenin equivalent
+
–
TH
R
TH
v
+

v
i
E
J
+
–
+
–
i
+

v
N
6.002 Fall 2000 Lecture
18
3
Example:
1
R
V
+
–
1
i
1
R
V
+
–
1
i
TH
TH
R R
V V
i
+
−
=
1
1
I
2
R
J
I
TH
R
TH
V +
–
6.002 Fall 2000 Lecture
19
3
Example:
:
TH
R
:
TH
V
2
IR V
TH
=
2
R R
TH
=
+

TH
V
2
R
J
I
+

TH
R
2
R
6.002 Fall 2000 Lecture
20
3
Graphically, i R v v
TH TH
+ =
i
Open circuit
( ) 0 ≡ i
TH
v v =
OC
V
Short circuit
( ) 0 ≡ v
TH
TH
R
v
i
−
=
SC
I −
v
TH
R
1
TH
v
SC
I −
OC
V
“ ”
6.002 Fall 2000 Lecture
21
3
Method 5:
The Norton Method
in recitation,
see text
J
+
–
+
–
i
+

v
Norton
equivalent
TH
TH
N
R
V
I =
N TH
R R =
N
I
J
6.002 Fall 2000 Lecture
22
3
Summary
…
101100 …
Discretize matter
LMD LCA
Physics EE
R, I, V Linear networks
Analysis methods (linear)
KVL, KCL, I —V
Combination rules
Node method
Superposition
Thévenin
Norton
Next
Nonlinear analysis
Discretize voltage
6.002 Fall 2000 Lecture
1
4
6.002
CIRCUITS AND
ELECTRONICS
The Digital Abstraction
6.002 Fall 2000 Lecture
2
4
Review
z Discretize matter by agreeing to
observe the lumped matter discipline
zAnalysis tool kit: KVL/KCL, node method,
superposition, Thévenin, Norton
(remember superposition, Thévenin,
Norton apply only for linear circuits)
Lumped Circuit Abstraction
6.002 Fall 2000 Lecture
3
4
Discretize value Digital abstraction
Interestingly, we will see shortly that the
tools learned in the previous three
lectures are sufficient to analyze simple
digital circuits
Reading: Chapter 5 of Agarwal & Lang
Today
6.002 Fall 2000 Lecture
4
4
Analog signal processing
But first, why digital?
In the past …
By superposition,
The above is an “adder” circuit.
2
2 1
1
1
2 1
2
0
V
R R
R
V
R R
R
V
+
+
+
=
If
,
2 1
R R =
2
2 1
0
V V
V
+
=
1
V
1
R
2
R
+
–
2
V
+
–
0
V
and
might represent the
outputs of two
sensors, for example.
1
V
2
V
6.002 Fall 2000 Lecture
5
4
Noise Problem
… noise hampers our ability to distinguish
between small differences in value —
e.g. between 3.1V and 3.2V.
Receiver:
huh?
add noise on
this wire
t
6.002 Fall 2000 Lecture
6
4
Value Discretization
Why is this discretization useful?
Restrict values to be one of two
HIGH
5V
TRUE
1
LOW
0V
FALSE
0
…like two digits 0 and 1
(Remember, numbers larger than 1 can be
represented using multiple binary digits and
coding, much like using multiple decimal digits to
represent numbers greater than 9. E.g., the
binary number 101 has decimal value 5.)
6.002 Fall 2000 Lecture
7
4
Digital System
sender receiver
S
V
R
V
noise
S
V
“0” “0” “1”
0V
2.5V
5V
HIGH
LOW
t
R
V
“0” “0” “1”
0V
2.5V
5V
t
V V
N
0 =
N
V
S
V
“0” “0” “1”
2.5V t
With noise
V V
N
2 . 0 =
S
V
“0” “0” “1”
0V
2.5V
5V
t
0.2V
t
6.002 Fall 2000 Lecture
8
4
Digital System
Better noise immunity
Lots of “noise margin”
For “1”: noise margin 5V to 2.5V = 2.5V
For “0”: noise margin 0V to 2.5V = 2.5V
6.002 Fall 2000 Lecture
9
4
Voltage Thresholds
and Logic Values
1
0
1
0
sender receiver
1
0
0V
2.5V
5V
6.002 Fall 2000 Lecture
10
4
forbidden
region
V
H
V
L
3V
2V
But, but, but …
What about 2.5V?
Hmmm… create “no man’s land”
or forbidden region
For example,
sender receiver
0V
5V
1 1
0 0
“1” V 5V
“0” 0V V
H
L
6.002 Fall 2000 Lecture
11
4
sender receiver
But, but, but …
Where’s the noise margin?
What if the sender sent 1: ? V
H
Hold the sender to tougher standards!
5V
0V
1
1
0
0
V
0H
V
0L
V
IH
V
IL
6.002 Fall 2000 Lecture
12
4
sender receiver
V
H
But, but, but …
Where’s the noise margin?
What if the sender sent 1: ?
Hold the sender to tougher standards!
5V
0V
“1” noise margin:
“0” noise margin:
V
IH

V
0H
V
IL

V
0L
1
1
0
0
V
0H
V
0L
V
IH
V
IL
Noise margins
6.002 Fall 2000 Lecture
13
4
Digital systems follow static discipline: if
inputs to the digital system meet valid input
thresholds, then the system guarantees its
outputs will meet valid output thresholds.
sender
receiver
0 1 0 1
t
5V
V
0H
V
0L
0V
V
IH
V
IL
0 1 0 1
t
5V
V
0H
V
0L
0V
V
IH
V
IL
6.002 Fall 2000 Lecture
14
4
Processing digital signals
Recall, we have only two values —
Map naturally to logic: T, F
Can also represent numbers
1,0
6.002 Fall 2000 Lecture
15
4
Processing digital signals
Boolean Logic
If X is true and Y is true
Then Z is true else Z is false.
Z = X AND Y
X, Y, Z
are digital signals
“0” , “1”
Z = X • Y
Boolean equation
Enumerate all input combinations
Truth table representation:
Z X Y
AND gate
Z
X
Y
0 0 0
0 1 0
1 0 0
1 1 1
6.002 Fall 2000 Lecture
16
4
Adheres to static discipline
Outputs are a function of
inputs alone.
Combinational gate
abstraction
Digital logic designers do not
have to care about what is
inside a gate.
6.002 Fall 2000 Lecture
17
4
Demo
Noise
Z
X
Y
Z = X • Y
Z
Y
X
6.002 Fall 2000 Lecture
18
4
Z = X • Y
Examples for recitation
X
t
Y
t
Z
t
6.002 Fall 2000 Lecture
19
4
In recitation…
Another example of a gate
If (A is true) OR (B is true)
then C is true
else C is false
C = A + B
Boolean equation
OR
OR gate
C
A
B
Z
X
Y
NAND
Z = X • Y
More gates
B B
Inverter
6.002 Fall 2000 Lecture
20
4
Boolean Identities
AB + AC = A • (B + C)
X • 1 = X
X • 0 = X
X + 1 = 1
X + 0 = X
1 = 0
0 = 1
output
B
C
B • C
A
Digital Circuits
Implement: output = A + B • C
6.002 Fall 2000 Lecture
1
5
6.002
CIRCUITS AND
ELECTRONICS
Inside the Digital Gate
6.002 Fall 2000 Lecture
2
5
Review
z Discretize value 0, 1
z Static discipline
meet voltage thresholds
Specifies how gates must be designed
sender receiver
forbidden
region
OL
V
OH
V
IL
V
IH
V
The Digital Abstraction
6.002 Fall 2000 Lecture
3
5
Review
C A B
0 0 1
0 1 1
1 0 1
1 1 0
A
B
C
NAND
Combinational gate abstraction
outputs function of input alone
satisfies static discipline
6.002 Fall 2000 Lecture
4
5
For example:
a digital circuit
Demo
D
A
B
C
A Pentium III class microprocessor
is a circuit with over 4 million gates !!
The RAW chip
being built at the
Lab for Computer Science at MIT
has about 3 million gates.
3 gates here
( ) ( )
B A C D
⋅ ⋅ =
B A
⋅
6.002 Fall 2000 Lecture
5
5
How to build a digital gate
Analogy
A
B
C
l
i
k
e
p
o
w
e
r
s
u
p
p
l
y
(
l
i
k
e
s
w
i
t
c
h
e
s
)
taps
if A=ON AND B=ON
C has H 0
else C has no H 0
2
2
Use this insight to build an AND gate.
6.002 Fall 2000 Lecture
6
5
How to build a digital gate
C
B
A
OR gate
6.002 Fall 2000 Lecture
7
5
Electrical Analogy
+
–
Bulb C is ON if A AND B are ON,
else C is off
Key: “switch” device
V
A B
C
6.002 Fall 2000 Lecture
8
5
Electrical Analogy
Key: “switch” device
C
in
out
control
3Terminal device
if C = 0
short circuit between in and out
else
open circuit between in and out
For mechanical switch,
control mechanical pressure
in
out
1
=
C
equivalent ckt
0 = C
in
out
6.002 Fall 2000 Lecture
9
5
Consider
=
S
V
“1”
+
–
S
V
L
R
C
IN
OUT
OUT
V
S
V
0 = C
OUT
V
S
V
1 = C
OUT
V
S
V
L
R
C
OUT
V
Truth table for
C
0 1
1 0
OUT
V
6.002 Fall 2000 Lecture
10
5
What about?
Truth table for
O
V
2
c
0 0 1
0 1 1
1 0 1
1 1 0
1
c
Truth table for
O
V
2
c
0 0 1
0 1 0
1 0 0
1 1 0
1
c
S
V
OUT
V
1
c
2
c
S
V
OUT
V
1
c
2
c
6.002 Fall 2000 Lecture
11
5
What about?
can also build compound gates
S
V
D
A
B
C
( ) C B A D + ⋅ =
6.002 Fall 2000 Lecture
12
5
The MOSFET Device
3 terminal lumped element
behaves like a switch
MetalOxide
Semiconductor
FieldEffect
Transistor
: control terminal
: behave in a symmetric
manner (for our needs)
G
S D,
gate
≡
source
D
S
G
drain
6.002 Fall 2000 Lecture
13
5
The MOSFET Device
Understand its operation by viewing it
as a twoport element —
“Switch” model (S model) of the MOSFET
D
S
G
i
G
GS
v
+
–
DS
v
DS
i
+
–
C
h
e
c
k
o
u
t
t
h
e
t
e
x
t
b
o
o
k
f
o
r
i
t
s
i
n
t
e
r
n
a
l
s
t
r
u
c
t
u
r
e
.
T GS
V v <
T GS
V v ≥
V V
T
1 ≈ typically
on
G
D
S
DS
i
G off
D
S
6.002 Fall 2000 Lecture
14
5
Check the MOS device
on a scope.
Demo
GS
v
+
–
DS
v
DS
i
+
–
T GS
V v ≥
DS
i
DS
v
T GS
V v <
DS
i
DS
v
vs
6.002 Fall 2000 Lecture
15
5
A MOSFET Inverter
S
V
L
R
A
IN
B
A
B
V 5 =
Note the power of abstraction.
The abstract inverter gate representation
hides the internal details such as power
supply connections, , , etc.
(When we build digital circuits, the
and are common across all gates!)
L
R GND
v
OUT
6.002 Fall 2000 Lecture
16
5
The T1000 model laptop desires gates that satisfy
the static discipline with voltage thresholds. Does
out inverter qualify?
IN
v
OUT
v
OUT
v
IN
v
5V
5V
0V
=1V
T
V
= 0.5V
OL
V
= 4.5V
OH
V
= 0.9V
IL
V
= 4.1V
IH
V
Our inverter satisfies this.
receiver
OL
V
OH
V
IL
V
IH
V
5
4.5
0.5
0
sender
5
4.1
0.9
0
1:
0:
1
0
Example
6.002 Fall 2000 Lecture
17
5
E.g.:
Does our inverter satisfy the static
discipline for these thresholds:
= 0.2V
OL
V
= 4.8V
OH
V
= 0.5V
IL
V
= 4.5V
IH
V
= 0.5V
OL
V
= 4.5V
OH
V
= 1.5V
IL
V
= 3.5V
IH
V
yes
no
x
6.002 Fall 2000 Lecture
18
5
Switch resistor (SR) model
of MOSFET
…more accurate MOS model
D
S
G
D
S
T GS
V v <
G
T GS
V v ≥
ON
R
D
S
G
e.g. Ω = K R
ON
5
6.002 Fall 2000 Lecture
19
5
SR Model of MOSFET
MOSFET
S model
T GS
V v ≥
T GS
V v <
DS
i
DS
v
MOSFET
SR model
T GS
V v ≥
T GS
V v <
DS
i
DS
v
ON
R
1
D
S
G
D
S
T GS
V v <
G
T GS
V v ≥
ON
R
D
S
G
6.002 Fall 2000 Lecture
20
5
Using the SR model
=
S
V
“1”
+
–
S
V
L
R
C
IN
OUT
OUT
v
S
V
0 = C
OUT
v
S
V
1 = C
OUT
v
S
V
L
R
C
OUT
v
Truth table for
C
0 1
1 0
OUT
V
T GS
V v ≥
ON
R
ON
R
OL
V
L
R
ON
R
ON
R
S
V
OUT
v ≤
+
=
L
R
L
R
Choose R
L
, R
ON
, V
S
such that:
6.002 Fall 2000 Lecture
1
6
6.002
CIRCUITS AND
ELECTRONICS
Nonlinear Analysis
6.002 Fall 2000 Lecture
2
6
Discretize matter t LCA
m1 X KVL, KCL, iv
m2 X Composition rules
m3 X Node method
m4 X Superposition
m5 X Thévenin, Norton
any
circuit
linear
circuits
Review
6.002 Fall 2000 Lecture
3
6
Discretize value t Digital abstraction
X Subcircuits for given “switch”
setting are linear! So, all 5
methods (m1 – m5) can be
applied
1
1
=
=
B
A
A
B
S
V
L
R
C
S
V
L
R
C
ON
R
ON
R
SR MOSFET Model
Review
6.002 Fall 2000 Lecture
4
6
Today
Nonlinear Analysis
X Analytical method
based on m1, m2, m3
X Graphical method
X Introduction to incremental analysis
6.002 Fall 2000 Lecture
5
6
How do we analyze nonlinear
circuits, for example:
D
v
+

D
D
i
D
v
D
i
0 , 0
D
bv
D
ae i =
a
D
v
+

V
+
–
Hypothetical
nonlinear
device
D
D
i
(Expo Dweeb ☺)
(Curiously, the device supplies power when v
D
is negative)
6.002 Fall 2000 Lecture
6
6
Method 1: Analytical Method
Using the node method,
(remember the node method applies for linear or
nonlinear circuits)
D
bv
D
ae i =
2
0 = +
−
D
D
i
R
V v
1
2 unknowns 2 equations
Solve the equation by
trial and error
numerical methods
6.002 Fall 2000 Lecture
7
6
Method 2: Graphical Method
Notice: the solution satisfies equations
and
2 1
D
v
D
i
a
D
bv
D
ae i =
2
D
v
D
i 1
R
v
R
V
i
D
D
− =
R
V
V
R
slope
1
− =
6.002 Fall 2000 Lecture
8
6
Combine the two constraints
1
4
1
1
1
=
=
=
=
b
a
R
V e.g.
A i
V v
D
D
4 . 0
5 . 0
=
=
D
v
D
i
5 . 0 ~
4 . 0 ~
R
V
V
1
1
a
¼
called “loadline”
for reasons you
will see later
6.002 Fall 2000 Lecture
9
6
Method 3: Incremental Analysis
Motivation: music over a light beam
Can we pull this off?
LED: Light
Emitting
expoDweep ☺
D
v
+

) (t v
I
+
–
D
i
LED
R
i
AMP
light intensity I
R
in photoreceiver
R R
I i ∝
light
intensity
D D
i I ∝
I
v
t
music signal
) (t v
I
light sound ) (t i
R
) (t i
D
nonlinear
linear
problem! will result in distortion
6.002 Fall 2000 Lecture
10
6
Problem:
The LED is nonlinear distortion
I D
v v =
D
v
D
i
v
D
t
t
D
i
v
D
D
i
t
6.002 Fall 2000 Lecture
11
6
If only it were linear …
v
D
t
D
i
D
v
D
i
it would’ve been ok.
What do we do?
Zen is the answer
… next lecture!
6.002 Fall 2000 Lecture
1
7
6.002
CIRCUITS AND
ELECTRONICS
Incremental Analysis
6.002 Fall 2000 Lecture
2
7
Nonlinear Analysis
X Analytical method
X Graphical method
Today
X Incremental analysis
Reading: Section 4.5
Review
6.002 Fall 2000 Lecture
3
7
Method 3: Incremental Analysis
Motivation: music over a light beam
Can we pull this off?
LED: Light
Emitting
expoDweep ☺
D
v
+

) (t v
I
+
–
D
i
LED
R
i
AMP
light intensity I
R
in photoreceiver
R R
I i ∝
light
intensity
D D
i I ∝
I
v
t
music signal
) (t v
I
light sound ) (t i
R
) (t i
D
nonlinear
linear
problem! will result in distortion
6.002 Fall 2000 Lecture
4
7
Problem:
The LED is nonlinear distortion
I D
v v =
D
v
D
i
v
D
t
t
D
i
v
D
D
i
t
6.002 Fall 2000 Lecture
5
7
Insight:
D
v
D
i
D
I
D
V
DC offset
or DC bias
Trick:
d D D
i I i + =
I
V
D
v
+

) (t v
i
+
–
LED
+
–
I
v
d D D
v V v + =
I
V
i
v
small region
looks linear
(about V
D
, I
D
)
6.002 Fall 2000 Lecture
6
7
Result
v
d
very small
D
i
D
v
d
i
D
I
D
V
6.002 Fall 2000 Lecture
7
7
Result
t
D
v
D
V
I D
v v =
t
D
I
D
i
~linear!
Demo
d
v
d
i
D
i
6.002 Fall 2000 Lecture
8
7
total
variable
DC
offset
small
superimposed
signal
The incremental method:
(or small signal method)
1. Operate at some DC offset
or bias point V
D
, I
D
.
2. Superimpose small signal v
d
(music) on top of V
D
.
3. Response i
d
to small signal v
d
is approximately linear.
Notation:
d D D
i I i
+ =
6.002 Fall 2000 Lecture
9
7
( )
D D
v f i =
What does this mean
mathematically?
Or, why is the small signal response
linear?
We replaced
D D D
v V v ∆ + =
using Taylor’s Expansion to expand
f(v
D
) near v
D
=V
D
:
( )
D
V v
D
D
D D
v
dv
v df
V f i
D D
∆ ⋅ + =
=
) (
" + ∆ ⋅ +
=
2
2
2
) (
! 2
1
D
V v
D
D
v
dv
v f d
D D
large DC
increment
about V
D
nonlinear
d
v
neglect higher order terms
because is small
D
v ∆
6.002 Fall 2000 Lecture
10
7
( )
D
V v
D
D
D D
v
v d
v f d
V f i
D D
∆ ⋅ + ≈
=
) (
equating DC and timevarying parts,
D
V v
D
D
D
v
v d
v f d
i
D D
∆ ⋅ = ∆
=
) (
constant
w.r.t. ∆v
D
constant w.r.t. ∆v
D
slope at V
D
, I
D
( )
D D
V f I = operating point
constant w.r.t. ∆v
D
X :
We can write
( )
D
V v
D
D
D D D
v
v d
v f d
V f i I
D D
∆ ⋅ + ≈ ∆ +
=
) (
so,
D D
v i
∆ ∝ ∆
By notation,
d D
i i
= ∆
d D
v v
= ∆
6.002 Fall 2000 Lecture
11
7
Equate DC and incremental terms,
D
bv
D
e a i =
From X :
constant
In our example,
d
bV bV
d D
v b e a e a i I
D D
⋅ ⋅ + ≈ +
D
bV
D
e a I =
d
bV
d
v b e a i
D
⋅ ⋅ =
operating point
d D d
v b I i ⋅ ⋅ =
small signal
behavior
linear!
aka bias pt.
aka DC offset
6.002 Fall 2000 Lecture
12
7
D
bV
D
e a I =
operating point
d D d
v b I i ⋅ ⋅ =
D
v
D
i
D
I
D
V
slope at
V
D
, I
D
operating
point
we are
approximating
A with B
A
B
d
v
d
i
Graphical interpretation
6.002 Fall 2000 Lecture
13
7
We saw the small signal
D
I
I
V
D
V
+

+
–
LED
D
bV
D
e a I =
Large signal circuit:
Small signal response:
d D d
v b I i =
graphically
mathematically
now, circuit
small signal circuit:
Linear!
d
i
i
v
d
v
+
 b I
D
1
+
–
behaves like:
d
v
+

d
i
b I
1
R
D
=
6.002 – Fall 2002: Lecture 8
1
6.002
CIRCUITS AND
ELECTRONICS
Dependent Sources
and Amplifiers
6.002 – Fall 2002: Lecture 8
2
Nonlinear circuits — can use the
node method
Small signal trick resulted in linear
response
Today
Dependent sources
Reading: Chapter 7.1, 7.2
Review
Amplifiers
6.002 – Fall 2002: Lecture 8
3
Dependent sources
+ –
v
R
i
R
v
i =
Resistor
2terminal 1port devices
+ –
v
i
I i =
I
Independent
Current source
Seen previously
control
port
output
port
I
i
I
v
O
i
O
v
+
–
+
–
New type of device: Dependent source
2port device
E.g., Voltage Controlled Current Source
Current at output port is a function of voltage
at the input port
) v ( f
I
6.002 – Fall 2002: Lecture 8
4
Dependent Sources: Examples
independent
current
source
Example 1: Find V
0
I I =
+
–
V
R
R I V
0
=
6.002 – Fall 2002: Lecture 8
5
voltage
controled
current
source
Example 2: Find V
( )
V
K
V f I = =
+
–
V
R
I
i
I
v
O
i
O
v
+
–
+
–
+
–
V
R
( )
I
I
v
K
v f =
Dependent Sources: Examples
6.002 – Fall 2002: Lecture 8
6
voltage
controled
current
source
R
V
K
IR V = =
KR V =
2
KR V =
3 3
10 10 ⋅ =
−
Volt 1 =
or
or
Example 2: Find V
( )
V
K
V f I = =
+
–
V
R
e.g. K = 10
3
Amp·Volt
R = 1kΩ
Dependent Sources: Examples
6.002 – Fall 2002: Lecture 8
7
Another dependent source example
I
v
+
–
( )
IN D
v f i =
L
R
+
–
S
V
e.g.
( )
IN D
v f i =
( )
2
IN
1 v
2
K
− =
for v
IN
≥ 1
IN
i
IN
v
D
i
O
v
+
–
+
–
otherwise
0 i
D
=
Find v
O
as a function of v
I
.
6.002 – Fall 2002: Lecture 8
8
Another dependent source example
I
v
+
–
( )
IN D
v f i =
L
R
S
V
e.g.
( )
IN D
v f i =
( )
2
IN
1 v
2
K
− =
for v
IN
≥ 1
IN
i
IN
v
D
i
O
v
+
–
+
–
otherwise
0 i
D
=
Find v
O
as a function of v
I
.
6.002 – Fall 2002: Lecture 8
9
Another dependent source example
Find v
O
as a function of v
I
.
I
v
+
–
I
v
S
V
O
v
L
R
( )
2
IN D
1 v
2
K
i − =
for v
IN
≥ 1
otherwise
0 i
D
=
6.002 – Fall 2002: Lecture 8
10
Another dependent source example
0 = + + −
O L D S
v R i V
KVL
L D S O
R i V v − =
( )
L I S O
R v
K
V v
2
1
2
− − = for v
I
≥ 1
S O
V v = for v
I
< 1
I
v
+
–
I
v
S
V
O
v
L
R
( )
2
IN D
1 v
2
K
i − =
for v
IN
≥ 1
otherwise
0 i
D
=
Hold that thought
6.002 – Fall 2002: Lecture 8
11
Next, Amplifiers
6.002 – Fall 2002: Lecture 8
12
Why amplify?
Signal amplification key to both analog
and digital processing.
Analog:
Besides the obvious advantages of being
heard farther away, amplification is key
to noise tolerance during communication
AMP
IN OUT
Input
Port
Output
Port
6.002 – Fall 2002: Lecture 8
13
Why amplify?
Amplification is key to noise tolerance
during communication
useful
signal
huh?
1 mV
n
o
i
s
e
10 mV
No amplification
6.002 – Fall 2002: Lecture 8
14
AMP
Try amplification
not bad!
n
o
i
s
e
6.002 – Fall 2002: Lecture 8
15
Why amplify?
Digital:
IN
OUT
Digital System
IL
V
IH
V
5V
0V
OL
V
OH
V
5V
0V
t
5V
0V
IL
V
IH
V
IN
OUT
t
5V
0V
OL
V
OH
V
Valid region
6.002 – Fall 2002: Lecture 8
16
Why amplify?
Digital:
Static discipline requires amplification!
Minimum amplification needed:
IL
V
IH
V
OL
V
OH
V
IL IH
OL OH
V V
V V
−
−
6.002 – Fall 2002: Lecture 8
17
An amplifier is a 3ported device, actually
We often don’t show the power port.
Also, for convenience we commonly observe
“the common ground discipline.”
In other words, all ports often share a
common reference point called “ground.”
How do we build one?
POWER
IN OUT
Amplifier
Power port
Input
port
Output
port
I
i
I
v
O
i
O
v
+
–
+
–
6.002 – Fall 2002: Lecture 8
18
Remember?
0 = + + −
O L D S
v R i V
KVL
L D S O
R i V v − =
( )
L I S O
R v
K
V v
2
1
2
− − = for v
I
≥ 1
S O
V v = for v
I
< 1
Claim: This is an amplifier
I
v
+
–
I
v
S
V
O
v
L
R
( )
2
IN D
1 v
2
K
i − =
for v
IN
≥ 1
otherwise
0 i
D
=
6.002 – Fall 2002: Lecture 8
19
So, where’s the amplification?
Let’s look at the v
O
versus v
I
curve.
amplification
1 >
∆
∆
I
O
v
v
Ω = = = k 5 R ,
V
mA
2 K , V 10 V
L
2
S
e.g.
O
v ∆
I
v ∆
( )
2
1
2
− − =
I L S O
v R
K
V v
( )
2
1 5 10 − − =
I O
v v
( )
2
3 3
1 10 5 10
2
2
10 − ⋅ ⋅ ⋅ − =
−
I
v
1
I
v
S
V
O
v
6.002 – Fall 2002: Lecture 8
20
Plot v
O
versus v
I
( )
2
I O
1 v 5 10 v − − =
10.00 1.0
~ 0.00 2.4
1.50 2.3
2.80 2.2
4.00 2.1
5.00 2.0
8.75 1.5
10.00 0.0
v
O
v
I
0.1 change
in v
I
1V change
in v
O
Gain!
Measure v
O
.
Demo
6.002 – Fall 2002: Lecture 8
21
One nit …
1
I
v
O
v
Mathematically,
( )
2
1
2
− − =
I L S O
v R
K
V v
What
happens
here?
So is mathematically predicted behavior
6.002 – Fall 2002: Lecture 8
22
One nit …
D
i
S
V
O
v
L
R
VCCS
1
I
v
O
v
For v
O
>0, VCCS consumes power: v
O
i
D
For v
O
<0, VCCS must supply power!
( )
2
1
2
− − =
I L S O
v R
K
V v
( )
2
1
2
− =
I D
v
K
i for v
I
≥ 1
However, from
What
happens
here?
6.002 – Fall 2002: Lecture 8
23
If VCCS is a device that can source
power, then the mathematically
predicted behavior will be observed —
( )
2
1
2
− − =
I L S O
v R
K
V v i.e.
where v
O
goes ve
I
v
O
v
6.002 – Fall 2002: Lecture 8
24
If VCCS is a passive device,
then it cannot source power,
so v
O
cannot go ve.
So, something must give!
Turns out, our model breaks down.
( )
2
1
2
− =
I D
v
K
i
Commonly
will no longer be valid when v
O
≤ 0 .
e.g. i
D
saturates (stops increasing)
and we observe:
I
v
O
v
1
6.002 Fall 2000 Lecture
1
9
6.002
CIRCUITS AND
ELECTRONICS
MOSFET Amplifier
Large Signal Analysis
6.002 Fall 2000 Lecture
2
9
Amp constructed using dependent source
Superposition with dependent sources:
one way tleave all dependent sources in;
solve for one independent source at a
time [section 3.5.1 of the text]
Next, quick review of amp …
Reading: Chapter 7.3–7.7
+
–
+
–
a
′
a
v
b
′
b
) (v f i =
a
′
a
b
′
b control
port
DS
output
port
Dependent source in a circuit
Review
6.002 Fall 2000 Lecture
3
9
Amp review
L D S O
R i V v − =
( )
2
I
1 v
2
K
−
for v
I
≥ 1V
= 0 otherwise
S
V
O
v
L
R
+
–
( )
2
I D
1 v
2
K
i − =
I
v
VCCS
6.002 Fall 2000 Lecture
4
9
Key device Needed:
Let’s look at our old friend, the MOSFET …
A
B
v
C
( ) v f i =
voltage controlled
current source
6.002 Fall 2000 Lecture
5
9
Key device Needed:
Our old friend, the MOSFET …
First, we sort of lied. The onstate behavior of the
MOSFET is quite a bit more complex than either the
ideal switch or the resistor model would have you believe.
D
S
G
D
S
T GS
V v <
G
T GS
V v ≥
?
6.002 Fall 2000 Lecture
6
9
Graphically
DS
v
DS
i
T GS
V v ≥
T GS
V v <
T GS
V v ≥
1 GS
v
Saturation
region
T
r
i
o
d
e
r
e
g
i
o
n
S MODEL
DS
v
DS
i
SR MODEL
DS
v
DS
i
Demo
T GS
V v <
T GS
V v <
2 GS
v
3 GS
v
+
–
DS
v
+
–
DS
i
GS
v
.
.
.
T GS DS
V v v − =
Cutoff
region
6.002 Fall 2000 Lecture
7
9
Graphically
DS
v
DS
i
T GS
V v ≥
T GS
V v <
T GS
V v ≥
1 GS
v
Saturation
region
T
r
i
o
d
e
r
e
g
i
o
n
S MODEL
DS
v
DS
i
SR MODEL
DS
v
DS
i
T GS
V v <
T GS
V v <
2 GS
v
3 GS
v
+
–
DS
v
+
–
DS
i
GS
v
.
.
.
T GS DS
V v v − =
Notice that
MOSFET
behaves like a
current source
when
T GS DS
V v v − ≥
6.002 Fall 2000 Lecture
8
9
MOSFET SCS Model
D
S
G
D
S
T GS
V v <
G
( )
2
2
T GS
V v
K
− =
when
T GS DS
V v v − ≥
( )
GS DS
v f i =
T GS
V v ≥
D
S
G
When
the MOSFET is in its saturation region, and the
switch current source (SCS) model of the MOSFET is
more accurate than the S or SR model
T GS DS
V v v − ≥
6.002 Fall 2000 Lecture
9
9
Reconciling the models…
T GS DS
V v v − ≥
T GS DS
V v v − <
use SCS model
use SR model
Note: alternatively (in more advanced courses)
or, use SU Model (Section 7.8 of A&L)
S MODEL SR MODEL SCS MODEL
for fun!
for digital
designs
for analog
designs
When to use each model in 6.002?
DS
v
DS
i
T GS
V v ≥
T GS
V v <
T GS
V v ≥
1 GS
v
Saturation
region
T
r
i
o
d
e
r
e
g
i
o
n
DS
v
DS
i
DS
v
DS
i
T GS
V v <
T GS
V v <
2 GS
v
3 GS
v
.
.
.
T GS DS
V v v − =
6.002 Fall 2000 Lecture
10
9
Back to Amplifier
in saturation
region
I
v
O
v
AMP
S
V
S
V
L
R
I
v
O
v
G
D
S
( )
2
2
T I DS
V v
K
i − =
To ensure the MOSFET operates as a VCCS,
we must operate it in its saturation region
only. To do so, we promise to adhere to the
“saturation discipline”
6.002 Fall 2000 Lecture
11
9
MOSFET Amplifier
in saturation
region
S
V
L
R
I
v
O
v
G
D
S
( )
2
2
T I DS
V v
K
i − =
To ensure the MOSFET operates as a VCCS,
we must operate it in its saturation region
only. We promise to adhere to the
“saturation discipline.”
In other words, we will operate the amp
circuit such that
v
GS
≥ V
T
and v
DS
≥ v
GS
– V
T
at all times.
v
O
≥ v
I
– v
T
6.002 Fall 2000 Lecture
12
9
Let’s analyze the circuit
First, replace the MOSFET with its
SCS model.
for
T I O
V v v − ≥ I GS
v v =
G
I
v
+
–
+
–
S
V
O
v
L
R
D
S
A
( )
2
2
T I DS
V v
K
i − =
6.002 Fall 2000 Lecture
13
9
Let’s analyze the circuit
for
T I O
V v v − ≥ I GS
v v =
G
I
v
+
–
+
–
S
V
O
v
L
R
D
S
A
( )
2
2
T I DS
V v
K
i − =
or ( )
L T I S O
R V v
K
V v
2
2
− − =
for
T I
V v ≥
T I O
V v v − ≥
S O
V v =
for
T I
V v <
(MOSFET turns off)
L DS S O
R i V v − = B
1
Analytical method: I O
v vs v
(v
O
= v
DS DS
in our example in our example) )
6.002 Fall 2000 Lecture
14
9
2
Graphical method
:
B
From A ( ) ,
2
2
T I DS
V v
K
i − = :
2
O DS
DS
O
T I O
v
2
K
i
K
i 2
v
V v v
≤
⇓
≥
⇓
− ≥
for
I O
v vs v
L
0
L
S
DS
R
v
R
V
i
− =
6.002 Fall 2000 Lecture
15
9
2
Graphical method
:
B
Constraints and must be met A B
A ( ) ,
2
2
T I DS
V v
K
i − = :
S
V
DS
i
O
v
2
2
O DS
v
K
i ≤
L
S
R
V
L
o
a
d
l
i
n
e
B
for
GS
v =
I
v
A
2
2
O DS
v
K
i ≤
L
O
L
S
DS
R
v
R
V
i
− =
I O
v vs v
6.002 Fall 2000 Lecture
16
9
2
Graphical method
Constraints and must be met.
Then, given V
I
, we can find V
O
, I
DS
.
A B
S
V
DS
i
O
v
L
S
R
V
B
I
v
A
2
2
O DS
v
K
i ≤
I O
v vs v
I
V
DS
I
O
V
6.002 Fall 2000 Lecture
17
9
Large Signal Analysis
of Amplifier
(under “saturation discipline”)
1 v
O
versus v
I
2
Valid input operating range and
valid output operating range
6.002 Fall 2000 Lecture
18
9
Large Signal Analysis
1 v
O
versus v
I
I
v
S
V
( )
L T I S
R V v
K
V
2
2
− −
O
v
T
V
gets into
triode region
T I O
V v v − =
6.002 Fall 2000 Lecture
19
9
2
What are valid operating ranges
under the saturation discipline?
DS
i
O
v
2
2
O DS
v
K
i ≤
S
V
L
S
R
V
L
O
L
S
DS
R
v
R
V
i − =
Large Signal Analysis
T I O
T I
V v v
V v
− ≥
≥
2
2
O DS
v
K
i ≤
Our
Constraints
=
T I
0
=
DS
i
=
S O
V v
V v
and
?
I
v
( )
2
2
T I DS
V v
K
i − =
6.002 Fall 2000 Lecture
20
9
=
T I
0
=
DS
i
=
S O
V v
V v
and
2
What are valid operating ranges
under the saturation discipline?
DS
i
O
v
2
2
O DS
v
K
i ≤
L
O
L
S
DS
R
v
R
V
i − =
Large Signal Analysis
I
v
( )
2
2
T I DS
V v
K
i − =
L
S L
T I
KR
V KR
V v
2 1 1 + + −
+ =
L
S L
O
KR
V KR
v
2 1 1 + + −
=
L
O
L
S
DS
R
v
R
V
i − =
6.002 Fall 2000 Lecture
21
9
Valid input range:
L
S L
T
KR
V KR
V
2 1 1 + + −
+
v
I
: V
T
to
corresponding output range:
L
S L
KR
V KR 2 1 1 + + −
v
O
: V
S
to
2
Valid operating ranges under the
saturation discipline?
Large Signal Analysis
Summary
1 v
O
versus v
I
( )
L
2
T I S O
R V v
2
K
V v − − =
ADMINISTRIVIA
Lecturer: Prof. Anant Agarwal Readings are important! Handout no. 3
Assignments —
Textbook: Agarwal and Lang (A&L)
Homework exercises Labs Quizzes Final exam
6.002 Fall 2000
Lecture 1
2
Two homework assignments can be missed (except HW11). Collaboration policy Homework You may collaborate with others, but do your own writeup. Lab You may work in a team of two, but do you own writeup. Info handout
Reading for today —
Chapter 1 of the book
6.002 Fall 2000
Lecture 1
3
What is engineering? Purposeful use of science
What is 6.002 about? Gainful employment of Maxwell’s equations From electrons to digital gates and opamps
6.002 Fall 2000
Lecture 1
4
Nature as observed in experiments
V I 3 0.1 6 0.2 9 0.3 12 0.4 … …
Physics laws or “abstractions” Maxwell’s abstraction for Ohm’s tables of data V=RI Lumped circuit abstraction +– V C L R Simple amplifier abstraction Operational amplifier abstraction abstraction Digital abstraction Combinational logic f
6.002
M
S
+ 
Filters Analog system components: Modulators, oscillators, RF amps, power supplies 6.061
Clocked digital abstraction Instruction set abstraction Pentium, MIPS 6.004 Programming languages Java, C++, Matlab 6.001 Software systems 6.033 Operating systems, Browsers
Mice, toasters, sonar, stereos, doom, space shuttle 6.455 6.170 5
6.002 Fall 2000 Lecture 1
Lumped Circuit Abstraction
The Big Jump from physics to EECS I
Consider
+
V

?
Suppose we wish to answer this question: What is the current through the bulb?
6.002 Fall 2000
Lecture 1
6
We could do it the Hard Way…
Apply Maxwell’s Differential form ∂B Faraday’s ∇× E = − ∂t ∂ρ Continuity ∇ ⋅ J = − ∂t Others Integral form ∂φ B ∫ E ⋅ dl = − ∂t ∂q ∫ J ⋅ dS = − ∂t q E ⋅ dS = ∫
ρ ∇⋅E = ε0
ε0
6.002 Fall 2000
Lecture 1
7
Instead, there is an Easy Way…
First, let us build some insight: Analogy F
a?
I ask you: What is the acceleration? You quickly ask me: What is the mass? F You respond: a = m Done !! ! I tell you: m
6.002 Fall 2000
Lecture 1
8
there is an Easy Way… First. let us build some insight: Analogy F a? In doing so.Instead.002 Fall 2000 Lecture 1 9 . you ignored the object’s shape its temperature its color point of force application Pointmass discretization 6.
discrete resistor 6. shape. etc. Then.The Easy Way… Consider the filament of the light bulb. we can replace the bulb with a for the purpose of calculating the current. A B We do not care about how current flows inside the filament its temperature.002 Fall 2000 Lecture 1 10 . orientation.
A + V – B I R and discrete resistor V I= R In EE.The Easy Way… A B Replace the bulb with a for the purpose of calculating the current. we do things the easy way… R represents the only property of interest! Like with pointmass: replace objects F with their mass m to find a = m 6.002 Fall 2000 Lecture 1 11 .
002 Fall 2000 Lecture 1 12 .The Easy Way… A + V – B I R and I= V R In EE. we do things the easy way… R represents the only property of interest! R relates element v and i V I= R called element vi relationship 6.
R is a lumped element abstraction for the bulb.002 Fall 2000 Lecture 1 13 . 6.
R is a lumped element abstraction for the bulb. In this case.002 Fall 2000 Lecture 1 14 . we must make sure (at least the first time) that our abstraction is reasonable. ensuring that V I are defined for the element 6. Not so fast. though … I A + S A V B – SB black box Although we will take the easy way using lumped abstractions for the rest of this course.
002 Fall 2000 Lecture 1 15 .A + I SA SB V B – V I must be defined for the element black box 6.
I must be defined.002 Fall 2000 . True when I into S A = I out of S B ∂q True only when = 0 in the filament! ∂t SA ∫ J ⋅ dS ∫ J ⋅ dS ∂q ∫ J ⋅ dS − ∫ J ⋅ dS = ∂t SA SB SB from ell axw M IA IB ∂q =0 I A = I B only if ∂t So let’s assume this Lecture 1 16 6.
002 Fall 2000 Lecture 1 17 . see A&L So let’s assume this too VAB defined when So VAB = ∫AB E ⋅ dl ∂φ B =0 ∂t outside elements 6.V Must also be defined.
Lumped Matter Discipline (LMD) Or self imposed constraints: More in Chapter 1 of A & L ∂φ B = 0 outside ∂t ∂q = 0 inside elements ∂t bulb. battery Lumped circuit abstraction applies when elements adhere to the lumped matter discipline. wire.002 Fall 2000 Lecture 1 18 . 6.
002 Fall 2000 Lecture 1 19 . smell 6. Demo Exploding resistor demo can’t predict that! Pickle demo can’t predict light.Demo only for the sorts of questions we as EEs would like to ask! Lumped element examples whose behavior is completely captured by their V–I relationship.
So. For example — a b R1 R2 V + – R3 R4 d R5 c What can we say about voltages in a loop under the lumped matter discipline? 6. what does this buy us? Replace the differential equations with simple algebra using lumped circuit abstraction (LCA).002 Fall 2000 Lecture 1 20 .
002 Fall 2000 Lecture 1 21 . 6.What can we say about voltages in a loop under LMD? a V + – b R1 R2 R3 R4 d R5 c ∂φ B under DMD ∫ E ⋅ dl = − ∂t 0 ∫ E ⋅ dl + ∫ E ⋅ dl + ∫ E ⋅ dl = 0 ab bc ca + Vca + Vab + Vbc = 0 Kirchhoff’s Voltage Law (KVL): The sum of the voltages in a loop is 0.
What can we say about currents? Consider I ca S a I da I ba 6.002 Fall 2000 Lecture 1 22 .
What can we say about currents? I ca S a I da I ba ∂q ∫S J ⋅ dS = − ∂t I ca + I da + I ba = 0 Kirchhoff’s Current Law (KCL): The sum of the currents into a node is 0.002 Fall 2000 Lecture 1 23 . simply conservation of charge under LMD 0 6.
002 Fall 2000 Lecture 1 24 .KVL and KCL Summary KVL: ∑ jν j = 0 loop KCL: ∑jij = 0 node 6.
002 CIRCUITS AND ELECTRONICS Amplifiers Small Signal Model 6.002 Fall 2000 Lecture 10 1 .6.
Chapter 8 6.Review MOSFET amp VS RL vO vI iDS Saturation discipline — operate MOSFET only in saturation region Large signal analysis 1.002 Fall 2000 Lecture 10 2 . vO ranges under saturation discipline. Valid vI . Find vO vs vI under saturation discipline. Reading: Small signal model . 2.
002 Fall 2000 Lecture 10 3 .Large Signal Review 1 vO vs vI vO = VS − K (vI −1)2 RL 2 valid for vI ≥ VT and vO ≥ vI – VT K 2 (same as iDS ≤ vO ) 2 6.
Saturation discipline satisfied. 6.002 Fall 2000 Lecture 10 4 .Large Signal Review 2 Valid operating ranges V S v O vO > vI −VT vO = vI −VT vO < vI −VT vI 5V corresponding interesting region for vO 1V VT 1V 2V “interesting” region for vI .
002 Fall 2000 Lecture 10 5 . but distorts t Amp is nonlinear … / 6.But… VS 5V vO vO = vI −VT vO 1V VT 1V vI vI Demo vI vO 2V Amplifies alright.
VO ) ~ 1V VT 1V vI ~ 2V 2 K (vI − VT ) vO = VS − RL 2 Amp all right. VO) … looks quite linear ! 6.002 Fall 2000 Lecture 10 6 .Small Signal Model vO ~ 5V VS Focus on this line segment (VI . observe vI vs vO about some point (VI . but nonlinear! Hmmm … So what about our linear amplifier ??? Insight: But.
002 Fall 2000 Lecture 10 7 .VO ) vi looks linear VI ∆vI Operate amp at VI .Trick ∆vO VO vo (VI . VO Æ DC “bias” (good choice: midpoint of input operating range) Superimpose small signal on top of VI Response to small signal seems to be approximately linear 6.
002 Fall 2000 Lecture 10 next week 8 .VO ) vi looks linear VI Operate amp at VI . VO Æ DC “bias” (good choice: midpoint of input operating range) ∆vI Superimpose small signal on top of VI Response to small signal seems to be approximately linear Let’s look at this in more detail — I graphically II mathematically III from a circuit viewpoint 6.Trick ∆vO VO vo (VI .
well above VT . and in fact.002 Fall 2000 Lecture 10 9 .I Graphically We use a DC bias VI to “boost” interesting input signal above VT. VS interesting input signal RL ∆vI + – VI + – vO Offset voltage or bias 6.
Graphically interesting input signal VS RL ∆vI + – VI + – vO VS VO vO operating point VI . VO 0 VT VI vO = vI −VT vI Good choice for operating point: midpoint of input operating range 6.002 Fall 2000 Lecture 10 10 .
vI VI vi VO vO vo 0 t 0 t 11 6.002 Fall 2000 Lecture 10 .Small Signal Model aka incremental model aka linearized model Notation — Input: vI = VI + vi total DC small variable bias signal (like ∆vI) bias voltage aka operating point voltage Output: vO = VO + vo Graphically.
002 Fall 2000 Lecture 10 12 .II Mathematically (… watch my fingers) RL K 2 vO = VS − (vI −VT ) VO = VS − RL K (VI −VT )2 2 2 substituting vI = VI + vi vi << VI RL K vO = VS − 2 = VS − RL K 2 ( [VI + vi ] − vT )2 ( [VI −VT ] + vi )2 RL K [VI −VT ]2 + 2 [VI − vT ]vi + vi 2 = VS − 2 RL K VO + vo = VS − (VI − VT )2 − RL K (VI −VT ) vi 2 From . vo = −RL K (VI −VT ) vi gm related to ( ) VI 6.
vi In other words.r. VI – VT is constant.t.Mathematically vo = −RL K (VI −VT ) vi gm related to VI vo = −g m RL vi For a given DC operating point voltage VI.002 Fall 2000 Lecture 10 13 . So. vo = − A vi constant w. our circuit behaves like a linear amplifier for small signals 6.
Another way RL K vO = VS − (vI −VT )2 2 R K 2 L v −V VS − I T 2 d vo = dv I v = V I I slope at VI ( ) ⋅ vi vo = −RL K (VI −VT ) ⋅ vi g m = K (VI −VT ) A = −g m RL amp gain Also. see Figure 8.9 in the course notes for a graphical interpretation of this result 6.002 Fall 2000 Lecture 10 14 .
So bias carefully 3. Gain component g m ∝ VI 2. 6. Bias at midpoint of input operating range for maximum swing.More next lecture … iDS load line input signal response operating point VI Demo VO vO How to choose the bias point: 1. Input valid operating range. vi gets big Æ distortion.002 Fall 2000 Lecture 10 15 .
002 Fall 2000 Lecture 11 1 .6.002 CIRCUITS AND ELECTRONICS Small Signal Circuits 6.
Review: Small signal notation vA = VA + va total operating point small signal vOUT = f (vI ) d f (vI ) ⋅ vi vout = dv I v I =VI VS vI = VI + vi vi VI RL + – + – Lecture 11 vO = VO + vo 6.002 Fall 2000 2 .
002 Fall 2000 Lecture 11 3 .Review: I Graphical view (using transfer function) vO behaves linear for small perturbations vI 6.
Review: II Mathematical view K (vI − VT ) vO = VS − RL 2 2 V − K (v − V )2 R T L d S 2 I vo = dv I v I =VI ⋅ vi vo = − K (VI − VT ) RL ⋅ vi gm related to VI constant for fixed DC bias 6.002 Fall 2000 Lecture 11 4 .
002 Fall 2000 Lecture 11 5 . 6.How to choose the bias point. Gain g m RL ∝ VI 2. 3. using yet another graphical view based on the load line i DS i DS < K 2 vO 2 Demo V v i DS = S − O load line RL RL input signal response VI vO v I = VT VO − 1 + 1 + 2 KR LV S v I = VT + KR L Choosing a bias point: 1. Bias to select gain and input swing. Input valid operating range for amp.
6.III The Small Signal Circuit View We can derive small circuit equivalent models for our devices.g.2.1 and also in the last slide in this lecture. large signal circuit model for amp R vI + – vOUT K 2 iD = (vI − VT ) 2 VS + – 1 We can replace large signal models with small signal circuit models.002 Fall 2000 Lecture 11 6 . Foundations: Section 8. and thereby conduct small signal analysis directly on circuits e.
Develop small signal (linearized) models for elements. Replace original elements with small signal models.Small Signal Circuit Analysis 1 2 3 Find operating point using DC bias inputs using large signal model.002 Fall 2000 Lecture 11 7 . Analyze resulting linearized circuit… Key: Can use superposition and other linear circuit tools with linearized circuit! 6.
Small Signal Models A MOSFET large signal vGS D iDS = K (vGS − VT )2 2 Small signal? S 6.002 Fall 2000 Lecture 11 8 .
002 Fall 2000 Lecture 11 .Small Signal Models A MOSFET large signal vGS D iDS = S K (vGS − VT )2 2 Small signal: K 2 iDS = (vGS − VT ) 2 ∂ ids = ∂vGS K (v − V )2 ⋅ v gs T 2 GS vGS =VGS ids is linear in vgs ! ids = K (VGS − VT ) ⋅ v gs gm small signal v gs D ids = K (VGS − VT ) v gs S ids = g m v gs 9 6.
002 Fall 2000 Lecture 11 10 .B DC Supply VS large signal iS + vS = VS – vS = VS Small signal ∂VS vs = ∂iS is + vs – vs = 0 ⋅ is iS = I S DC source behaves as short to small signals. 6.
002 Fall 2000 Lecture 11 11 .C Similarly. R iR + vR R – v R = R iR large signal vr = ∂ ( RiR ) ⋅ ir ∂iR iR = I R vr = R ⋅ ir small signal ir + vr R – 6.
Amplifier example: Large signal RL vO Small signal + V – S + vi – RL vo + v – I iDS ids iDS K 2 = (vI − VT ) 2 K (vI − VT )2 RL 2 ids = K (VI − VT ) ⋅ vi ids RL + vo = 0 vo = −ids RL vo = − K (VI − VT )RL ⋅ vi = − g m RL ⋅ vi vO = VS − Notice.002 Fall 2000 Lecture 11 12 . Get these from a large signal analysis. first we need to find operating point voltages/currents. 6.
we can replace large signal device models with corresponding small signal device models. III The Small Signal Circuit View Foundations: (Also see section 8.To find the relationship between the small signal parameters of a circuit.002 Fall 2000 Lecture 11 13 .2. we can cancel them out + va + vout + vb + 2 But 2 is the same equation as 1 with small signal variables replacing total variables.1 of A&L) KVL. and then analyze the resulting small signal circuit. except that small signal models are used. so 2 must reflect same topology as in C. Since small signal models are linear. KCL equations + VA Leaving + VOUT + VB + so. our linear tools will now apply… 6. KCL applied to some circuit C yields: + vA + + vOUT + + vB + 1 Replace total variables with operating point variables plus small signal variables + VA + v a + VOUT + vout + VB + vb + Operating point variables themselves satisfy the same KVL.
002 CIRCUITS AND ELECTRONICS Capacitors and FirstOrder Systems 6.002 Fall 2000 Lecture 12 1 .6.
002 Fall 2000 Lecture 12 Expect this.Motivation Demo A 5V B 5V 0V 5V C 5 A 0 5 B 0 5 C 0 Delay! 6. right? But observe this! Expected Observed Reading: Chapters 9 & 10 2 .
002 Fall 2000 Lecture 12 .The Capacitor D G S drain gate m+ e+ t + a+ l + + o x i d e nchannel MOSFET symbol source s i l nchannel p i MOSFET nchannel c o n n D G CGS S 3 n 6.
002 Fall 2000 Lecture 12 4 .Ideal Linear Capacitor + + A ++++ d EA d obeys DMD! total charge on capacitor = +q − q = 0 C= E i C q + v – q = C v coulombs farads volts 6.
002 Fall 2000 Lecture 12 5 .Ideal Linear Capacitor i C q q = C v dq i= dt d (Cv ) = dt dv =C dt E = 1 Cv 2 2 + v – A capacitor is an energy storage device memory device history matters! 6.
002 Fall 2000 Lecture 12 t ≥ t0 vC (t0 ) given 6 .Analyzing an RC circuit Thévenin Equivalent: vI (t ) + – R C + vC (t ) – Apply node method: vC − vI dvC +C =0 R dt dvC RC + vC = vI dt units of time 6.
Let’s do an example: + v I (t ) + – R C vC (t ) – vI (t ) = VI vC (0 ) = V0 given dvC RC + vC = VI dt X 6.002 Fall 2000 Lecture 12 7 .
Use the initial conditions to solve for the remaining constants. 3 The total solution is the sum of the particular and homogeneous solutions. 6.002 Fall 2000 Lecture 12 8 . 2 Find the homogeneous solution.Example… vI (t ) = VI vC (0 ) = V0 given dvC RC + vC = VI dt total homogeneous X vC (t ) = vCH (t ) + vCP (t ) particular Method of homogeneous and particular solutions: 1 Find the particular solution.
use trial and error.002 Fall 2000 Lecture 12 9 . vCP : any solution that satisfies the original equation X 6.1 Particular solution RC dvCP + vCP = VI dt vCP = VI works RC 0 dVI + VI = VI dt In general.
2 Homogeneous solution dvCH RC + vCH = 0 dt Y vCH : solution to the homogeneous equation Y (set drive to zero) vCH = A e st assume solution of this form. A.002 Fall 2000 Lecture 12 10 . R C s +1 = 0 s= − or 1 RC −t RC Characteristic equation vCH = Ae RC called time constant τ 6. s? dA e st RC + A e st = 0 dt R CA s e st + A e st = 0 Discard trivial A = 0 solution.
002 Fall 2000 Lecture 12 11 . so.3 Total solution vC = vCP + vCH vC = VI + A e −t RC Find remaining unknown from initial conditions: Given. or thus also vC = V0 at t = 0 V0 = VI + A A = V0 − VI vC = VI + (V0 − VI ) e iC = C −t RC dvC (V − VI ) =− 0 e R dt −t RC 6.
002 Fall 2000 Lecture 12 12 .vC = VI + (V0 − VI ) e −t RC vC VI V0 0 RC t 6.
002 Fall 2000 Lecture 12 13 .Examples vC 5V 5V vC 5 + 5e 0V VO = 0V VI = 5V −t RC 5e −t RC t 5 0 0V VO = 5V VI = 0V t 5 0 τ = RC Remember B demo 6.
6.002 Fall 2000 Lecture 13 1 .002 CIRCUITS AND ELECTRONICS Digital Circuit 6.
Review vI VI 0 vI + – t R C + vC – vC (0 ) = VO vC = VI + (VO − VI ) e −t RC 1 vC VI VO RC time constant RC t 6.002 Fall 2000 Lecture 13 2 .
Let’s apply the result to an inverter. rising delay tr at B B VS VS A vA 5V B X t CGS 0 1 0 at A 6. A X First.002 Fall 2000 Lecture 13 3 .
First.002 Fall 2000 Lecture 13 4 . rising delay tr at B VS VS A vA 5V B X CGS 0 1 0 at A t 5V vB ideal observed 0 t 6.
First.002 Fall 2000 Lecture 13 5 . rising delay tr at B VS VS A vA 5V B X t CGS 0 1 0 at A 5V VOH vB rising delay of X 0 tr t 6.
we need to find t for which vB = VOH .002 Fall 2000 Lecture 13 6 .Equivalent circuit for 0 1 at B vI = VS + – RL CGS + vB – vI = VS vB (0 ) = 0 for t ≥ 0 From 1 vB = VS + (0 − VS ) e −t RL CGS Now. 6.
002 Fall 2000 Lecture 13 7 .Or vOH = VS − VS e −t RL CGS Find tr : VS e −t r RL CGS = VS − VOH VS − VOH − tr = ln RL CGS VS VS − VOH t r = − RL CGS ln VS 6.
1 ns ! 6.Or vOH = VS − VS e −t RL CGS Find tr : VS e −t r RL CGS = VS − VOH VS − VOH − tr = ln RLCGS VS VS − VOH t r = − RL CGS ln VS e. RL = 1K VS = 5V VOH = 4V −12 CGS = 0.16 ns RC = 0.1 pF 3 t r = −1 × 10 × 0.002 Fall 2000 Lecture 13 5−4 ln 5 8 .1 × 10 = 0.g.
002 Fall 2000 Lecture 13 9 .Falling Delay tf Falling delay tf is the t for which vB falls to VOL Equivalent circuit for 1 RL 0 at B vB (0 ) = VS (5V ) VS + – RON X CGS + vB – 6.
Falling Delay tf Equivalent circuit for 1 RL 0 at B vB (0 ) = VS (5V ) VS + – RON X Thévenin replacement … RTH CGS + vB – VTH + – CGS + vB – RTH = RL  RON VTH 6.002 Fall 2000 RON = VS RON + RL Lecture 13 10 .
002 Fall 2000 Lecture 13 11 .From 1 vB = VTH + (VS − VTH ) e −t RTH CGS Falling decay tf is the t for which vB falls to VOL VOL = VTH + (VS − VTH ) e RTH CGS or −t f VOL − VTH t f = − RTH CGS ln VS − VTH 6.
t f = − RTH CGS ln VOL − VTH VS − VTH RON = 10Ω e.002 Fall 2000 Lecture 13 12 . t f = −10 ⋅ 0.1 pF RTH ≈ 10Ω.g.6 ps RC = 1 ps ! 1 ln 5 6. RL = 1K VS = 5V VOL = 1V VTH ≈ 0V −12 CGS = 0.1 ⋅10 = 1.
002 Fall 2000 Lecture 13 13 .For recitation: Slow may be better Problem chip pin 2 pin 1 v CL v: ideal observed slow! So the engineers decided to speed it up… RL RON made RL small made RON small 6.
For recitation: Slow may be better Problem chip pin 2 pin 1 v CL v: ideal observed slow! … v: but. disaster! observed expected VIL 6.002 Fall 2000 Lecture 13 14 .
002 Fall 2000 Lecture 13 15 .Why? Consider Case 1 R1 … pin1 Demo R0 ok 6.
002 Fall 2000 Lecture 13 16 .Why? Consider Case 2 … CP Demo R1 pin1 pin2 R2 R0 crosstalk! CP R model for crosstalk: + v – + – 6.
6.… Case 3 6.002 expert saw the solution R1 CP R0 R2 + – slower transitions! Detailed analysis in recitation.002 Fall 2000 Lecture 13 17 .
002 Fall 2000 Lecture 14 1 .002 CIRCUITS AND ELECTRONICS State and Memory 6.6.
Review Recall vI + – v I = VI for R C + vC – vC (0 ) t ≥0 −t vC = VI + (vC (0)− VI ) e RC 1 Reading: Sections 10.5. and 10.002 Fall 2000 Lecture 14 2 .3. 10.7 6.
002 Fall 2000 Lecture 14 3 . and the input voltage for t ≥ 0 . Instead. 6. For the RC circuit in the previous slide vI VI vI t ≥0 VI 0 t vC vC = VI + (vC (0)− VI ) e RC −t vC (0 ) 0 t Notice that the capacitor voltage for t ≥ 0 is independent of the form of the input voltage before t = 0 . it depends only on the capacitor voltage at t = 0 .This lecture will dwell on the memory property of capacitors.
002 Fall 2000 Lecture 14 4 . actually 6.State State : summary of past inputs relevant to predicting the future q=CV for linear capacitors. capacitor voltage V is also state variable state variable.
vI (t )) vC = VI + (vC (0 ) − VI ) e −t RC Summarizes the past input relevant to predicting future behavior 6.State Back to our simple RC circuit 1 vC = f (vC (0 ).002 Fall 2000 Lecture 14 5 .
State We are often interested in circuit response for zero state vC (0) = 0 zero input Correspondingly.002 Fall 2000 Lecture 14 6 . zero state response or ZSR vC = VI − VI e −t RC vI (t) = 0 2 zero input response or ZIR vC = vC (0 ) e −t RC 3 6.
002 Fall 2000 Lecture 14 7 .One application of STATE DIGITAL MEMORY Why memory? Or. why is combinational logic insufficient? Examples Consider adding 6 numbers on your calculator 2+9+6+5+3+8 M+ “Remembering” transient inputs 6.
The recorded value is visible at dOUT .Memory Abstraction A 1bit memory element d IN store M d OUT The 6.002 Fall 2000 Lecture 14 remembers the 1 8 . d IN store d OUT 6. Like a camera that records input (dIN) when the user presses the shutter release button.004 view $ The NEC View ☺ ¥ Remembers input when store goes high.
Building a memory element … A First attempt dIN * store dOUT C storage node 6.002 Fall 2000 Lecture 14 9 .
Building a memory element … A dIN store = 1 * * vC d OUT C dIN store = 0 vC d OUT C vC 5V VOH T t RL Stored value leaks away vC = 5 ⋅ e −t RL C T = − RLC ln VOH 5 from 2 store pulse width >> RON C 6.002 Fall 2000 Lecture 14 10 .
Building a memory element … B Second attempt buffer dIN * C dOUT RIN buffer store Input resistance RIN VOH T = − RIN C ln 5 RIN >> RL Better. but still not perfect.002 Fall 2000 Lecture 14 11 . Demo 6.
6. External value can influence storage node.Building a memory element … C Third attempt buffer + refresh store dIN store dOUT C Does this work? * No.002 Fall 2000 Lecture 14 12 .
002 Fall 2000 Lecture 14 13 .Building a memory element … D Fourth attempt buffer + decoupled refresh store dIN store dOUT C Works! * 6.
A Memory Array 4bit memory store Address IN OUT Decoder 00 A d IN S M d OUT d IN S M d OUT d IN S M d OUT d IN S M d OUT 01 B A 2 Address 10 a0 a1 C B 11 D C IN store D OUT 6.002 Fall 2000 Lecture 14 14 .
002 Fall 2000 Lecture 14 15 .Truth table for decoder a0 0 0 1 1 a1 0 1 0 1 A 1 0 0 0 B 0 1 0 0 C 0 0 1 0 D 0 0 0 1 6.
Adlibbing ≡ ZSR I think. Senator.002 Fall 2000 Lecture 14 16 .Agarwal’s top 10 list on memory 10 9 8 7 6 5 I have no recollection. therefore I am. I forgot the rest … 6. I forgot the homework was due today. I think that was right.
6.002 CIRCUITS AND ELECTRONICS SecondOrder Systems 6.002 Fall 2000 Lecture 15 1 .
driving another.002 Fall 2000 Lecture 15 2 . The parasitic inductance of the wire and the gatetosource capacitance of the MOSFET are shown [Review complex algebra appendix for next class] 6.SecondOrder Systems Demo 2KΩ A + – large loop 5V 50Ω S 5V 2KΩ B CGS C Our old friend. the inverter.
002 Fall 2000 Lecture 15 3 .SecondOrder Systems Demo 2KΩ A + – large loop 5V 50Ω S 5V 2KΩ C B CGS Relevant circuit: 2KΩ L CGS B 5V + – 6.
Observed Output 5 vA 0 2kΩ t vB 0 2kΩ t vC 0 Now. let’s try to speed up our inverter by closing the switch S to lower the effective resistance 6.002 Fall 2000 Lecture 15 4 t .
002 Fall 2000 Lecture 15 5 .Observed Output 5 vA 0 ~50Ω t vB 0 50Ω t vC 0 Huh! t 6.
i state variables Lecture 15 6 . let’s analyze the LC network + – L C i (t ) vI (t ) + v(t ) – Node method: i (t ) = C t dv dt Recall dv 1 ∫ (vI − v) dt = C dt L −∞ vI − v = L di dt 1 (v I − v ) L d 2v =C 2 dt 1 t ∫ (vI − v) dt = i L −∞ d 2v LC 2 + v = vI dt time2 6.002 Fall 2000 v.First.
v = vP (t ) + vH (t ) 6.Solving Recall. 4 steps The total solution is the sum of the particular and homogeneous. Find the homogeneous solution. Use initial conditions to solve for the remaining constants.002 Fall 2000 Lecture 15 7 . the method of homogeneous and particular solutions: 1 2 3 Find the particular solution.
002 Fall 2000 Lecture 15 8 .Let’s solve d 2v LC 2 + v = vI dt For input V0 vI 0 And for initial conditions v(0) = 0 i(0) = 0 [ZSR] t 6.
1
Particular solution
d 2 vP LC 2 + vP = V0 dt vP = V0
is a solution.
6.002 Fall 2000
Lecture
15
9
2
Homogeneous solution Solution to
d 2 vH LC 2 + vH = 0 dt
Recall, vH :
solution to homogeneous equation (drive set to zero)
Fourstep method:
A Assume solution of the form* vH = Ae st , A, s = ?
so,
LCAs 2 e st + Ae st = 0
1 s =− LC
2
B
characteristic equation
1 s=±j LC
C Roots D
j = −1
s = ± jω o
ωo =
1 LC
General solution,
vH = A1e jωot + A2 e − jωot
Lecture
*
Differential equations are commonly solved by guessing solutions
6.002 Fall 2000
15
10
3
Total solution
v(t ) = vP (t ) + vH (t )
v( t ) = V0 + A1e jωot + A2 e − jωot
Find unknowns from initial conditions. v(0) = 0 0 = V0 + A1 + A2 i ( 0) = 0 dv i (t ) = C dt
i( t ) = CA1 jωo e jωot − CA2 jωo e − jωot
so, or,
0 = CA1 jωo − CA2 jωo
A1 = A2
− V0 = 2 A V0 A1 = − 2
so,
V0 jωot v( t ) = V0 − (e + e − jωot ) 2
Lecture
15
11
6.002 Fall 2000
3
Total solution
Remember Euler relation
e jx = cos x + j sin x
(verify using Taylor’s expansion)
e jx + e − jx = cos x 2
so,
v( t ) = V0 − V0 cos ωot i( t ) = CV0ωo sin ωot
where
1 ωo = LC
The output looks sinusoidal
6.002 Fall 2000
Lecture
15
12
v(t )
Plotting the Total Solution
2V0
V0
0
π
2
i (t )
π
3π 2
2π
ωo t
CV0ωo
0
π
2
π
3π 2
2π
ωo t
− CV0ωo
6.002 Fall 2000 Lecture
15
13
Summary of Method
1 2 3 Write DE for circuit by applying node method. Find particular solution vP by guessing and trial & error. Find homogeneous solution vH A Assume solution of the form Aest . B Obtain characteristic equation. C Solve characteristic equation for roots si . D Form vH by summing Ai esit terms. 4 Total solution is vP + vH , solve for remaining constants using initial conditions.
Lecture
15
14
6.002 Fall 2000
Example
What if we have:
L
iC
+ C vC –
vC (0) = V iC (0) = 0
We can obtain the answer directly from the homogeneous solution (V0 = 0).
6.002 Fall 2000
Lecture
15
15
Example
iC
+ C vC –
L
vC (0) = V iC (0) = 0
We can obtain the answer directly from the homogeneous solution (V0 = 0).
vC ( t ) = A1e jωot + A2 e − jωot vC (0) = V iC (0) = 0
V = A1 + A2
0 = CA1 jωo − CA2 jωo
or A1 = A2 = or
V 2
vC =
V jω o t (e + e− jωot ) 2
vC = V cos ωot iC = −CV ωo sin ωot
6.002 Fall 2000 Lecture
15
16
Example vC V 2π ωo t CVωo iC 2π − CVωo ωo t 6.002 Fall 2000 Lecture 15 17 .
but it sloshes back and forth between the Capacitor and the inductor 6.002 Fall 2000 Lecture 15 18 .Energy EC C: 1 2 CvC 2 1 CV 2 2 2π EL ωo t 1 2 L : LiC 2 1 CV 2 2 2π ωo t Notice 1 1 1 2 2 CvC + LiC = CV 2 2 2 2 Total energy in the system is a constant.
RLC Circuits R vI (t ) + – L C i (t ) + v(t ) – v(t ) no R add R t Damped sinusoids with R – remember demo! See A&L Section 12.2 6.002 Fall 2000 Lecture 15 19 .
6.002 Fall 2000 Lecture 16 1 .002 CIRCUITS AND ELECTRONICS Sinusoidal Steady State 6.
tells us a lot about the system 6.aka frequency response . look at response of networks to sinusoidal drive.002 Fall 2000 Lecture 16 2 . Response to sinusoids of various frequencies . Sinusoids important because signals can be represented as a sum of sinusoids.Review We now understand the why of: 5V R L C v Today.
6. the amplifier: V S Demo vO R vi VBIAS + – + – CGS vC Observe vo amplitude as the frequency of the input vi changes.Motivation For motivation. Need to study behavior of networks for sinusoidal drive. consider our old friend.002 Fall 2000 Lecture 16 3 . Also observe vo shift as frequency changes (phase). Notice it decreases with frequency.
Sinusoidal Response of RC Network Example: iC vI + – R + vC – vI (t ) = Vi cos ω t =0 vC (0) = 0 for t ≥ 0 (Vi real) for t < 0 for t = 0 vI 0 t 6.002 Fall 2000 Lecture 16 4 .
Our Approach Example: R iC + vC – vI + – Determine vC(t) Effort Usual approach dulge me! In agony easy sneaky approach very sneaky 6.002 Fall 2000 lec tu re 11 :0 0 11 :2 0 12 N ex :0 t 0 le ct ur e t Th is Lecture 16 5 .
vC = vP + vH.Let’s use the usual approach… 1 2 3 4 Set up DE. Find vp.002 Fall 2000 Lecture 16 6 . solve for unknowns using initial conditions 6. Find vH.
Usual approach… 1 Set up DE RC dvC + vC = vI dt = Vi cos ω t That was easy! 6.002 Fall 2000 Lecture 16 7 .
2 Find vp dvP + vP = Vi cos ωt RC dt First try: Second try: Third try: vP = A vP = A cos ωt Æ nope Æ nope vP = A cos(ωt + φ ) frequency amplitude phase − RCAω sin(ωt + φ ) + A cos(ωt + φ ) = Vi cos ωt − RCAω sin ωt cos φ − RCAω cos ωt sin φ + A cos ωt cos φ − A sin ωt sin φ = Vi cos ωt . . . gasp ! works.002 Fall 2000 Lecture 16 8 . but trig nightmare! 6.
Let’s get sneaky! Find particular solution to another input… dvPS + vPS = vIS RC dt = Vi e st vPS = V p e st Try solution RC dV p e st (S: sneaky :)) Nice property of exponentials dt sRCV p e st + V p e st = Vi e st ( sRC + 1 )V p = Vi Vi Vp = 1 + sRC + V p e st = Vi e st Vi ⋅ e st 1 + sRC is particular solution to Vi e st Thus.002 Fall 2000 Lecture 16 9 . vPS = ly Vi ⋅ e jω t 1 + jωRC easy! Vi e jω t solution for where we replace s = jω complex amplitude Vp 6.
002 Fall 2000 Lecture 16 10 . linear. 6. assuming system is real. Fact 2: vI = Vi cos ωt = real[Vi e jω t ] = real[vIS ] from Euler relation. e jω t = cos ωt + j sin ωt real part vI response vP vIS response vPS real part an inverse superposition argument.2 Fourth try to find vP… using the sneaky approach Fact 1: Finding the response to Vi e jω t was easy.
6. complex vP = Re[vPS ] = Re[V p e jωt ] Vi = Re ⋅ e jω t 1+ jωRC Vi (1 − jωRC ) ⋅ e jω t = Re 1 + ω 2 R 2C 2 Vi j φ jω t = Re ⋅ e e .2 Fourth try to find vP… so.002 Fall 2000 Lecture 16 11 . vP is particular response to Vi cos ωt . tan φ = −ωRC 2 2 2 1+ω R C Vi = Re ⋅ e j( ωt +φ ) 1 + ω 2 R 2C 2 vP = Vi 1+ω R C 2 2 2 ⋅ cos( ωt + φ ) Recall.
3 Find vH Recall. vH = Ae −t RC 6.002 Fall 2000 Lecture 16 12 .
Vi A=− cos(φ ) 2 2 2 1+ ω R C Done! Phew ! 6.002 Fall 2000 Lecture 16 13 .4 Find total solution vC = vP + vH vC = Vi 1+ω R C 2 2 2 cos( ωt + φ ) + Ae − t RC where φ = tan −1 ( −ωRC ) Given vC(0) = 0 for t = 0 so.
vC → vP as e vC = Vi 1+ω R C 2 2 2 − t RC →0 t RC 0 cos( ωt + φ ) + Ae − where φ = tan −1 ( −ωRC ) Vi A=− cos(φ ) 2 2 2 1+ ω R C Vp Described as SSS: Sinusoidal Steady State ∠Vp 6. i.Sinusoidal Steady State We are usually interested only in the particular solution for sinusoids.002 Fall 2000 Lecture 16 14 . Notice when t → ∞. after transients have died.e.
Sinusoidal Steady State All information about SSS is contained in Vp . 4 were a waste of time! Vp 1 = Vi 1+ jωRC Vp Vi = 1 1 + ω 2 R 2C 2 1 1 + ω 2 R 2C 2 e jφ where φ = tan −1 − ωRC magnitude Vp Vi Vp Vi = phase φ : ∠ = − tan −1 ωRC 6. the complex amplitude! Recall Vi Vp = 1 + jωRC Steps 3 .002 Fall 2000 Lecture 16 15 .
E.Sinusoidal Steady State Visualizing the process of finding the particular solution vP Vi cos ωt drive D.002 Fall 2000 Lecture 16 16 . V p cos[ωt + ∠V p ] particular solution sneak in Vi e jωt drive algebraic take equation real + part complex algebra V p e jω t the sneaky path! 6. + nightmare trig.
Magnitude Plot transfer function Vp H ( jω ) = Vi Vp Vi = 1 1 + ω 2 R 2C 2 Vp Vi 1 log scale log scale 1 ω= RC ω From demo: explains vo fall off for high frequencies! 6.002 Fall 2000 Lecture 16 17 .
Phase Plot φ = tan −1 − ωRC φ =∠ Vp Vi ω= 0 1 RC − − π π 4 2 log scale ω 6.002 Fall 2000 Lecture 16 18 .
6.002 Fall 2000 Lecture 17 1 .002 CIRCUITS AND ELECTRONICS The Impedance Model 6.
2 Reading: Section 13.2 vI = Vi cos ωt + – R C + vO – SSS Focus on steady state.3 from course notes. 13. 6. 13. Focus on sinusoids.1. Sinusoidal Steady State (SSS) Reading 13.Review Sinusoidal Steady State (SSS) Reading 13. only care about vP as vH dies away.1.002 Fall 2000 Lecture 17 2 .
Review Vi cos ωt usual circuit model 1 set up DE V p cos[ωt + ∠V p ] nightmare trig. vP sneak in Vi e jωt drive complex algebra Vp 2 3 vH take 4 real total part The Sneaky Path V p e jω t Vi 1 + jωRC Vp contains all the information we need: Vp ∠V p 6.002 Fall 2000 Amplitude of output cosine phase Lecture 17 3 .
Review vO = V p cos(ωt + ∠V p ) Vp Vi = 1 = H ( jω ) transfer function 1 + jωRC remember demo Vp Vi 1 1 + ω 2 R 2C 2 1 1 2 1 ωRC Bode plot ∠ Vp Vi 1 ω= RC break frequency ω ω= 0 1 RC ω ⎛ − ωRC ⎞ π tan −1 ⎜ ⎟ − ⎝ 1 ⎠ 4 − π 2 The Frequency View 6.002 Fall 2000 Lecture 17 4 .
002 Fall 2000 Lecture 17 5 .Is there an even simpler way to get Vp ? Vi Vp = 1 + jωRC Divide numerator and denominator by jωC. 1 V p = Vi jω C 1 +R jω C Hmmm… looks like a voltage divider relationship. ZC V p = Vi ZC + R Let’s explore further… 6.
The Impedance Model Is there an even simpler way to get Vp ? Consider: + vR – iR i R = I r e jω t vR = Vr e jω t vR = RiR Vr e jω t = RI r e jω t Vr = RI r R Resistor + vC – iC iC = I C e jω t C vC = VC e jω t Capacitor dvC iC = C dt I C e jω t = CVC jωe jω t VC = 1 IC j ωC ZC + vL – iL iL = I l e jω t diL vL = L dt Vl e jω t = LI l jωe jω t Vl = jωL I l ZL L vL = Vl e jω t Inductor 6.002 Fall 2000 Lecture 17 6 .
The Impedance Model In other words. 6. by a generalization of Ohm’s Law. complex amplitude Vc is related to the complex amplitude Ic algebraically. capacitor Ic + Vc – ZC Vc = Z C I c 1 ZC = j ωC impedance inductor Il + Vl – ZL Vl = Z l I l Z l = j ωL resistor + Vr – Ir ZR Vr = Z r I r Zr = R For a drive of the form Vc e jωt .002 Fall 2000 Lecture 17 7 .
Back to RC example… R vI + – + C vC – Impedance model: ZR = R Ic + Vc – 1 ZC = jωC Vi + – 1 ZC jωC Vc = Vi = Vi 1 ZC + Z R +R jωC Vc = 1 Vi 1 + jωRC Done! All our old friends apply! KVL.002 Fall 2000 Lecture 17 8 . KCL. superposition… 6.
recall series RLC: Remember. we want only the steadystate response to sinusoid Ir L Vi e jω t Vi + – C R + Vr – Vr e jω t Vi cos ωt Vr = Vi Z R Z L + ZC + Z R Vr cos(ωt + ∠Vr ) Vi R Vr = 1 j ωL + +R jωC Vr = Vi jωCR − ω 2 LC + 1 + jωCR We will study this and other functions in more detail in the next lecture. 6.Another example.002 Fall 2000 Lecture 17 9 .
The Big Picture… Vi cos ωt usual circuit model set up DE V p cos[ωt + ∠V p ] nightmare trig. 6.002 Fall 2000 Lecture 17 10 .
002 Fall 2000 Lecture 17 11 .The Big Picture… Vi cos ωt usual circuit model set up DE V p cos[ωt + ∠V p ] nightmare trig. Vi e jωt drive complex algebra take real part 6.
s.The Big Picture… Vi cos ωt usual circuit model set up DE V p cos[ωt + ∠V p ] nightmare trig. no trig! 6. Vi e jωt drive complex algebra take real part impedancebased circuit model complex algebra No D.002 Fall 2000 Lecture 17 12 .E.
002 Fall 2000 Lecture 17 13 .Back to Vr jωRC = Vi 1 + jωRC − ω 2 LC Vi L + – Ir C R + Vr – Let’s study this transfer function Vr jωRC = Vi 1 + jωRC − ω 2 LC (1 − ω 2 LC ) − jωRC jωRC = ⋅ 2 (1 − ω LC ) + jωRC (1 − ω 2 LC ) − jωRC Vr = Vi (1 − ω 2 LC ) + (ωRC ) 2 ωRC 2 Observe Low ω : ≈ ωRC R High ω : ≈ ωL ω LC = 1 : ≈ 1 6.
002 Fall 2000 Lecture 17 14 . More next week… 6.Graphically Vr = Vi ωRC (1 − ω 2 LC ) + (ωRC ) 2 2 Low ω : ≈ ωRC R High ω : ≈ ωL ω LC = 1 : ≈ 1 Vr Vi 1 “Band Pass” ωRC 1 LC R ωL ω Remember this trick to sketch the form of transfer functions quickly.
002 Fall 2000 Lecture 18 1 .002 CIRCUITS AND ELECTRONICS Filters 6.6.
15. 14. 6.002 Fall 2000 Lecture 18 2 .3 from A & L.Review R vI + – ZR C + vC – Vi + – ZC + Vc – ZC Vc = ⋅ Vi ZC + Z R 1 Vc 1 j ωC = = 1 Vi + R 1 + jωRC j ωC Reading: Section 14.5.6.
A Filter ZR Vi + – ZC + Vc – ZC 1 ⋅ Vi = Vc = ZC + Z R 1 + jωRC Vc H (ω ) = Vi 1 “Low Pass Filter” Demo with audio 6.002 Fall 2000 Lecture 18 ω 3 .
002 Fall 2000 Lecture 18 4 .Quick Review of ImpedancesJust as I ab R1 R2 A + Vab B A – RAB Vab = = R1 + R2 I ab I ab R1 + j ωL B Vab – Z AB Vab = = R1 + jωL I ab 6.
002 Fall 2000 Lecture 18 5 .Quick Review of Impedances Similarly A R1 Z AB = R1 + Z C  R2 + Z L R2 C L B = R1 + = R1 + Z C R2 + ZL Z C + R2 R2 + jωL 1 + jωCR2 6.
002 Fall 2000 Lecture 18 6 .We can build other filters by combining impedances Z (ω ) L Z R C ω 6.
002 Fall 2000 Lecture 18 7 .We can build other filters by combining impedances Z (ω) L Z R C H (ω ) ω + – HPF High Pass Filter ω H (ω ) + – LPF Low Pass Filter ω H (ω ) + – HPF ω 6.
002 Fall 2000 Lecture 18 . so Vi sees only R! More later… 8 6.Check out: Vi + – Intuitively: L C + R Vr – Vr 1 Vi C k bloc eq w fr s lo ωo = 1 LC L bloc ks hig h freq ω R Vr = 1 Vi jω L + +R jω C j ω RC = 1 − ω 2 LC + j ω RC Vr = Vi (1 − ω 2 LC ) + (ω RC ) 2 ω RC 2 At resonance. ω = ωo and ZL + ZC = 0.
6.002 Fall 2000 Lecture 18 9 .What about: + Vlc L C – Vi + – R Vlc Vi 1 C open Band Stop Filter L open ω Check out Vl and Vc in the lab.
002 Fall 2000 Lecture 18 10 .Another example: R + Vi + – L C Vo – Vo Vi rt sho L BPF Cs ωo ho rt ω Application: see AM radio coming up shortly 6.
002 Fall 2000 Lecture 18 11 .AM Radio Receiver antenna R Vi + – Thévenin antenna model crystal radio demo L C demodulator amplifier 6.
AM Receiver R Vi + – C demodulator amplifier L signal strength 10 KHz filter WBZ News Radio f 540 …1000 1010 1020 1030 … 1600 KHz “Selectivity” important — relates to a parameter “Q” for the filter.002 Fall 2000 Lecture 18 12 . Next… 6.
002 Fall 2000 Lecture 18 13 .Selectivity: Look at series RLC in more detail L C Vi + – Recall. Vr R = Vi R + jω L + 1 jω C R + Vr – Vr Vi 1 1 2 higher Q bandwidth Δω ωo ωo Define Q = Δω quality factor ω high Q ⇒ more selective 6.
002 Fall 2000 Lecture 18 14 .Quality Factor Q Q= ωo Δω ωο: Vr R = Vi R + jω L + 1 = 1 ⎛ω L − 1 ⎞ 1 + j⎜ ⎟ jω C R ωCR ⎠ ⎝ at ωο =0 1 ωo = LC Δω ? 6.
R 1 R2 4 ω1 = + + 2 L 2 L2 LC R 1 ω2 = − + 2L 2 R2 4 + L2 LC R Δω = ω1 − ω2 = L 6. when 1 1 = ⎛ L 1 ⎞ 1 ± j1 1 + j⎜ ω − ⎟ ⎝ R ω CR ⎠ ωL 1 − = ±1 R ω CR ω2 m ωR L − 1 =0 LC Looking at the roots of both equations.002 Fall 2000 Lecture 18 15 .Quality Factor Q ωo Q= Δω Δω : Note that abs magnitude is when Vr = Vi 1 2 i.e.
002 Fall 2000 Lecture 18 16 . the sharper the peak 6.Quality Factor Q ωo Q= Δω Q= ωo R L = ωo L R 1 ωo = LC The lower the R (for series R).
Quality Factor Q Another way of looking at Q : energy stored Q = 2π energy lost per cycle = 2π 1 L Ir 2 2 1 2 2π Ir R ω0 2 ωo L Q= R 6.002 Fall 2000 Lecture 18 17 .
002 CIRCUITS AND ELECTRONICS The Operational Amplifier Abstraction 6.6.002 Fall 2000 Lecture 19 1 .
002 Fall 2000 Lecture 19 2 .Review MOSFET amplifier — 3 ports + + input vI port – + vO output port – VS power port – Amplifier abstraction VS + vI – + + v – O vI vO Function of vI – 6.
Reading: Chapter 15 from A & L.Review vI vO Function of vI Can use as an abstract building block for more complex circuits (of course. Today Introduce a more powerful amplifier abstraction and use it to build more complex circuits. need to be careful about input and output).002 Fall 2000 Lecture 19 3 . 6.
002 Fall 2000 Lecture 19 4 .Operational Amplifier Op Amp VS power port output port + – + – input port + – −VS More abstract representation: + vIN – + – vOUT 6.
e.Circuit model (ideal): + i=0 + v – – i=0 vO v+ + – Av A→∞ v– i. ∞ input resistance 0 output resistance “A” virtually ∞ No saturation 6.002 Fall 2000 Lecture 19 5 .
002 Fall 2000 Lecture 19 6 .Using it… 12V + – + – 12V VS = 12V vIN vO − VS = −12V RL – + Demo 12V vO active region saturation − 10 μV − 12V 10μV vIN A ~ 106 but unreliable. dependent (Note: possible confusion with MOSFET saturation!) 6. temp.
002 Fall 2000 Lecture 19 7 .Let us build a circuit… Circuit: noninverting amplifier v+ vIN + – v− + – R1 R2 vO Equivalent circuit model + i=0 op amp vO v+ v − vIN + – – i=0 + A(v + − v − ) – R1 R2 6.
vO = A(v + − v − ) R2 ⎞ ⎛ = A⎜ vIN − vO ⎟ R1 + R2 ⎠ ⎝ ⎛ AR2 ⎞ vO ⎜ 1 + ⎟ = AvIN ⎝ R1 + R2 ⎠ AvIN vO = AR2 1+ R1 + R2 What happens when “A” is very large? 6. etc.002 Fall 2000 Lecture 19 8 .Let us analyze the circuit: Find vO in terms of vIN.
Let’s see… When A is large AvIN AvIN ≈ vO = AR2 AR2 1+ R1 + R2 R1 + R2 ≈ vIN Suppose (R1 + R2 ) R2 gain A = 10 6 R1 = 9 R R2 = R 10 6 ⋅ vIN vO = 10 6 R 1+ 9R + R 10 6 ⋅ vIN = 1 6 1 + 10 ⋅ 10 vO ≈ vIN ⋅ 10 Demo Gain: determined by resistor ratio insensitive to A. fab variations 6. temperature.002 Fall 2000 Lecture 19 9 .
e.Why did this happen? Insight: 5V v+ v− + – 10V A 6V 12V vIN + – 5V vO = 2vIN 6V negative feedback e.g.g. vIN = 5V – i =0 R vO 2 R Suppose I perturb the circuit… (e. Key: negative feedback portion of output fed to –ve input. 6.. force vO momentarily to 12V somehow).002 Fall 2000 Lecture 19 10 .g. Stable point is when v+ ≈ v. Car antilock brakes small corrections..
002 Fall 2000 Lecture 19 di s c 11 .Question: How to control a highstrung device? Antilock brakes is it turning? yes/no ack b eed f yes release apply no it’s all about control Michelin v. powerful brakes 6. v.
More op amp insights: Observe.002 Fall 2000 Lecture 19 12 . under negative feedback. ⎛ R1 + R2 ⎞ ⎜ ⎟vIN R1 ⎠ v v+ − v− = O = ⎝ →0 A A v+ ≈ v− We also know i+ ≈ 0 i ≈ 0 yields an easier analysis method (under negative feedback). 6.
002 Fall 2000 Lecture 19 13 .Insightful analysis method under negative feedback v+ ≈ v− i+ ≈ 0 i− ≈ 0 a vIN g vO = vIN + c vIN e i=0 R1 + R2 R2 vO vIN R2 vIN + – b vIN – R1 f vIN d R2 R2 6.
Question: a vIN v + + – c vIN vIN + – b vIN v − vO ? vO ≈ vIN or R1 + R2 vO = vIN R2 with R1 = 0 R2 = ∞ 6.002 Fall 2000 Lecture 19 14 .
002 Fall 2000 Lecture 19 15 .Why is this circuit useful? + vIN + – – vO vO ≈ vIN Buffer voltage gain = 1 input impedance = ∞ output impedance = 0 current gain = ∞ power gain = ∞ 6.
6.002 CIRCUITS AND ELECTRONICS Basic Circuit Analysis Method (KVL and KCL method) 6.002 Fall 2000 Lecture 2 1 .
Review Lumped Matter Discipline LMD: Constraints we impose on ourselves to simplify our analysis ∂φ B =0 ∂t ∂q =0 ∂t Outside elements Inside elements wires resistors sources Allows us to create the lumped circuit abstraction 6.002 Fall 2000 Lecture 2 2 .
Review LMD allows us to create the lumped circuit abstraction i + v  Lumped circuit element power consumed by element = vi 6.002 Fall 2000 Lecture 2 3 .
002 Fall 2000 Lecture 2 4 .Review Review Maxwell’s equations simplify to algebraic KVL and KCL under LMD! KVL: ∑ jν j = 0 loop KCL: ∑jij = 0 node 6.
Review a R1 R4 + – b R2 R3 d R5 c DEMO vca + vab + vbc = 0 ica + ida + iba = 0 KVL KCL 6.002 Fall 2000 Lecture 2 5 .
write KCL for all nodes 3. KCL method of Circuit analysis Goal: Find all element v’s and i’s 1.Method 1: Basic KVL.002 Fall 2000 Lecture 2 6 . write KVL for all loops lots of unknowns lots of equations lots of fun solve 6. write element vi relationships (from lumped circuit abstraction) 2.
I = I 0 V0 Io 3 lumped circuit elements 6.Method 1: Basic KVL.002 Fall 2000 Lecture 2 7 . V = IR R +– For voltage source. KCL method of Circuit analysis Element Relationships For R. V = V0 For current source.
KVL. KCL Example a ν1 + – R1 ν 0 = V0 – + + – b R2 R3 +ν 3 – ν4 – + R4 d ν2 – + ν5 – + R5 c The Demo Circuit 6.002 Fall 2000 Lecture 2 8 .
002 Fall 2000 Lecture 2 9 .Associated variables discipline i + ν  Element e Current is taken to be positive going into the positive voltage terminal Then power consumed by element e = νi is positive 6.
KCL Example a ν 0 = V0 – + + – i0 ν1 L1 – + – + ν2 i4 i1 L 2 + R1 ν 4 R4 – R3 b i3 d +ν 3 – i2 i5 + R2 ν 5 R5 L3 – c The Demo Circuit L4 6.KVL.002 Fall 2000 Lecture 2 10 .
Element relationships (v.ι0 …ι5 1.Analyze ν 0 …ν 5 . i ) given v3 = i3 R3 v0 = V0 v4 = i4 R4 v1 = i1 R1 v5 = i5 R5 v2 = i2 R2 12 unknowns 6 equations 2. KCL at the nodes a: i0 + i1 + i4 = 0 3 independent b: i2 + i3 − i1 = 0 equations d: i5 − i3 − i4 = 0 e: − i0 − i2 − i5 = 0 redundant 3.002 Fall 2000 Lecture 2 11 . KVL for loops L1: − v0 + v1 + v2 = 0 3 independent equations L2: v1 + v3 − v4 = 0 L3: v3 + v5 − v2 = 0 s L4: − v0 + v4 + v5 = 0 redundant on ti s ua own eq nkn u 1 2 12 ugh @#! 6.
which you will learn about later) can solve the circuit on page 8 6. these rules (along with superposition.Other Analysis Methods Method 2— Apply element combination rules R1 R2 R3 A B … RN ⇔ R1 + R2 + + RN G1 G2 GN ⇔ G1 + G2 1 Gi = Ri + GN C V1 +– V2 +– ⇔ V1 + V2 +– D I1 I2 ⇔ I1 + I 2 Surprisingly.002 Fall 2000 Lecture 2 12 .
002 Fall 2000 Lecture 2 13 .Other Analysis Methods Method 2— Apply element combination rules Example I =? V + – R1 R2 R3 I V + – R1 I V + – R R2 R3 R2 + R3 R2 R3 R2 + R3 R = R1 + V I= R 6.
Write KCL for all but the ground node. Solve for node voltages. the secondary unknowns) 6. Select reference node ( ground) from which voltages are measured. Label voltages of remaining nodes with respect to ground. KCL method 1. Back solve for branch voltages and currents (i.. 3.002 Fall 2000 Lecture 2 14 . 5. These are the primary unknowns.e.Method 3—Node analysis Particular application of KVL. substituting device laws and KVL. 2. 4.
002 Fall 2000 Lecture 2 15 .Example: Old Faithful plus current source V0 R1 R 3 R2 R4 e2 + V e1 – 0 R5 I1 Step 1 Step 2 6.
002 Fall 2000 Lecture 2 16 . write 1 Gi = Ri KCL at e2 (e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0 Step 3 6.Example: Old Faithful plus current source V0 R1 R 3 R2 R4 e2 + V e1 – 0 R5 KCL at e1 (e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0 for I1 convenience.
2 unknowns (compare units) 6.002 Fall 2000 Lecture 2 Solve for e’s Step 4 17 .Example: Old Faithful plus current source V0 R1 R 3 R2 R4 e2 + V e1 – 0 R5 I1 Gi = KCL at e1 (e1 − V0 )G1 + (e1 − e2 )G3 + (e1 )G2 = 0 KCL at l2 (e2 − e1 )G3 + (e2 − V0 )G4 + (e2 )G5 − I1 = 0 1 Ri move constant terms to RHS & collect unknowns e1 (G1 + G2 + G3 ) + e2 (−G3 ) = V0 (G1 ) e1 (−G3 ) + e2 (G3 + G4 + G5 ) = V0 (G4 ) + I1 2 equations.
I1 .In matrix form: G1 + G2 + G3 − G3 − G3 e1 G1V0 = G3 + G4 + G5 e2 G4V0 + I1 conductivity matrix Solve unknown node voltages sources G3 G3 + G4 + G5 G1V0 G3 G1 + G2 + G3 G4V0 + I1 e1 2 e = (G1 + G2 + G3 )(G3 + G4 + G5 ) − G3 2 G +G +G G V + G G V + I 3 4 5 1 0 3 4 0 1 e = 1 G G +G G +G G +G G +G G +G G +G 2 +G G +G G 1 3 1 4 1 5 2 3 2 4 2 5 3 3 4 3 5 e2 = ( )( ) ( )( ) (G3 )(G1V0 ) + (G1 + G2 + G3 )(G4V0 + I 1 ) G1G3 + G1G4 + G1G5 + G2G3 + G2G4 + G2 G5 + G3 + G3G4 + G3G5 2 (same denominator) Notice: linear in V0 .002 Fall 2000 Lecture 2 18 . no negatives in denominator 6.
9 K I1 = 0 G G V + G +G +G G V + I e = 3 10 1 2 3 40 1 2 G + G + G + G + G + G −G 2 1 2 3 3 4 5 3 1 1 1 G +G +G = + + =1 1 2 3 8.9 V e2 = 8.5 0 1 1− 2 1. then e2 = 1.6V0 Check out the DEMO If V0 = 3V .5 1 G3 = 1.2 K G2 1 = G4 3.5 e2 = 0.9 8.8V0 6. given G1 1 = G5 8.Solve.2 3.2 1.5 3.2 1 1 1 × + 1× 3.002 Fall 2000 Lecture 2 19 .5 K ( ( )( )( ) ) G3 + G4 + G5 = 1 1 1 + + =1 1.9 1.
6.002 Fall 2000 Lecture 20 1 .002 CIRCUITS AND ELECTRONICS Operational Amplifier Circuits 6.
5 & 15. 6.Review Operational amplifier abstraction + – ∞ input resistance 0 output resistance Gain “A” very large Building block for analog systems We will see these examples: Digitaltoanalog converters Filters Clock generators Amplifiers Adders Integrators & Differentiators Reading: Chapter 15.002 Fall 2000 Lecture 20 2 .6 of A & L.
002 Fall 2000 Lecture 20 subtracts! 3 .Consider this circuit: i i v2 + – v1 + – R2 R1 v− – v+ + R2 R1 + vOUT – R2 v = v1 R1 + R2 ≈ v− + vOUT = v − − iR2 v2 − v − = v− − ⋅ R2 R1 R ⎡ R ⎤ = v − ⎢1 + 2 ⎥ − v2 2 R1 ⎣ R1 ⎦ = v1 R2 R + R2 R ⋅ 1 − v2 2 R1 + R2 R1 R1 v2 − v − i= R1 R2 = (v1 − v2 ) R1 6.
002 Fall 2000 Lecture 20 Still subtracts! 4 .Another way of solving — use superposition v1 → 0 R2 R1 v2 + R1 v1 + v2 → 0 v+ + R2 vOUT1 – + R1  R2 vOUT2 – – R2 – R1 vOUT2 R2 = − v2 R1 vOUT1 R1 + R2 =v ⋅ R1 + v1 ⋅ R2 R1 + R2 = ⋅ R1 + R2 R1 = v1 R2 R1 vOUT = vOUT1 + vOUT2 R2 = (v1 − v2 ) R1 6.
002 Fall 2000 Lecture 20 5 t .Let’s build an intergrator… vI + – ∫ dt + vO – Let’s start with the following insight: i + i + – C vO – 1 vO = ∫ i dt C −∞ vO is related to ∫ i dt But we need to somehow convert voltage vI to current. 6.
RC O + vO = vI dt smaller the vO vR dvO when RC >> vO for good dt integrator dvO RC ≈ vI ωRC >> 1 dt t 1 or vO ≈ ∫∞vI dt RC − Demo 6.002 Fall 2000 Lecture 20 6 .First try… use resistor + vR – i vI + – R C + vO – vI →i R But. or else v i≠ I R When is vO small compared to vR ? dv larger the RC. vO must be very small compared to vR.
6.There’s a better way… Notice i i – + v − ≈ 0V under negative feedback v i= I so.002 Fall 2000 Lecture 20 . R – R vI + – + vI R – vI + vC – + – R + + t vO 1 vI – vO = − ∫ dt C −∞ R 7 vO = −vC We have our integrator.
002 Fall 2000 Lecture 20 8 .Now. 6. let’s build a differentiator… d dt + vO – vI + – Let’s start with the following insights: i vI + – C dvI i=C dt dvI i is related to dt But we need to somehow convert current to voltage.
Differentiator… Recall i i – + R i – + + vO – vO = −iR 0V i R – + current to voltage C vI + – + vC – vO vI = vC dvI i=C dt Demo 6.002 Fall 2000 dvI vO = − RC dt Lecture 20 9 .
6.002 CIRCUITS AND ELECTRONICS Op Amps Positive Feedback 6.002 Fall 2000 Lecture 21 1 .
002 Fall 2000 21 2 .Negative vs Positive Feedback Consider this circuit — negative feedback vIN R1 R2 – R1 vIN + + R – + vOUT = − 2 vIN – R1 and this — positive feedback + – R2 vIN + – R1 sis e aly pag an t ee nex s on + R2 “vOUT = − R vIN ” – 1 What’s the difference? Consider what happens when there is a pertubation… Positive feedback drives op amp into saturation: vOUT → ±VS Lecture 6.
002 Fall 2000 Lecture 21 3 .Static Analysis of Positive Feedback Ckt v IN + – R1 + – v + R2 v − R2 vOUT v IN + – R1 + – A(v + − v − ) vOUT vOUT = A(v + − v − ) = Av + v − vIN = A OUT ⋅ R1 + vIN R1 + R2 = AR1vIN AR1 vOUT − + AvIN R1 + R2 R1 + R2 AR1 R1 vOUT 1 − = vIN A1 − R1 + R2 R1 + R2 1 − R1 R +R R 1 2 ⋅ AvIN = − 2 vIN = AR1 R1 − R1 + R2 vOUT 6.
Representing dynamics of op amp… v+ + – v− C (v + − v − ) R + v* – vo + – Av* 6.002 Fall 2000 Lecture 21 4 .
002 Fall 2000 Lecture 21 5 . R2 R1 + – vo R3 Circuit model R1 R2 R4 vo A + v* – + vo – v+ v− + – C (v + − v − ) R + – R3 R4 Let’s develop equation representing time behavior of vo .Representing dynamics of op amp… Consider this circuit and let’s analyze its dynamics to build insight. 6.
Dynamics of op amp… vo = Av * dv* * RC + v = v+ − v_ dt RC dvo vo + = v+ − v_ A dt A + = ( γ − − ) vo γ neglect vo or v = A * v+ = vo R1 + = γ vo R1 + R2 vo R3 − v = = − vo γ R3 + R4 or dvo 1 A − + + + ( γ − γ ) vo = 0 RC RC dt dvo A − + + ( γ − γ ) vo = 0 dt RC time −1 or dvo vo RC + = 0 where T = − + A( γ − γ ) dt T vo ( 0 ) = 0 6.002 Fall 2000 Lecture 21 6 .
002 Fall 2000 Lecture 21 7 . − > + if γ γ T is positive vo = K e − t T stable if + − γ > γ T is negative vo = K e t T unstable if + − γ = γ T is very large vo = K neutral unstable vo K neutral stable t disturbance Now.Consider a small disturbance to vo (noise). 6. let’s build some useful circuits with positive feedback.
One use for instability: Build on the basic op amp as a comparator + VS v+ + – − VS v− vo + VS vo 0 v+ − v− − VS vo v →0 − v + t Lecture 21 8 6.002 Fall 2000 .
5 6.Now. use positive feedback vi – + R2 R1 vo vo R1 v = R1 + R2 + v = 7. R1 = R2 VS = 15 v− < v+ v − < −7.g.5 + vo = 15 vi e.5 vo = −15 v − = −7.5 ( vi = v − ) > 7.002 Fall 2000 Lecture 21 9 .5 v − > 7.
5 vo = −VS − 15 v − = − VS R1 R1 + R2 6.g. use positive feedback vi – + R2 R1 vo vo R1 v = R1 + R2 + VS R1 v = R1 + R2 + vo = +VS 15 vi e. R1 = R2 VS = 15 ( vi = v − ) > v + v − > 7.Now.002 Fall 2000 Lecture 21 10 .5 v− < v+ v − < −7.
5 Demo 6.002 Fall 2000 Lecture 21 11 . analog to digital 7..5 t − 7.5 0 7 .vo VS 15 hysteresis − 7 .5 vi Demo − VS − 15 Why is hysteresis useful? vi v o e.g.
5 − 7.5 vo vi t 6.002 Fall 2000 Lecture 21 12 .Without hysteresis analog to digital vi 7.
002 Fall 2000 Assume Lecture vo = VS vC = 0 21 at t = 0 13 .Oscillator — can create a clock R vC C vo 2 vo VS VS 2 VS − 2 − VS v+ v− vC – + R1 R1 vo v v+ − t Demo 6.
0? When is the signal valid? common timebase .1. t can use as a clock Why do we use a clock in a digital system? (See page 735 of A & L) 1 sender 1 0 receiver clock a b 1.Clocks in Digital Systems We built an oscillator using an op amp. whenever the clock is high) Discretization of time one bit of information associated with an interval of time (cycle) 6.when to “look” at a signal (e.002 Fall 2000 Lecture 21 14 .g.
002 Fall 2000 Lecture 22 1 .002 CIRCUITS AND ELECTRONICS Energy and Power 6.6.
Why worry about energy?  small batteries good Today: How long will the battery last? in standby mode in active use Will the chip overheat and selfdestruct? 6.002 Fall 2000 Lecture 22 2 .
6.Look at energy dissipation in MOSFET gates VS R + + vI – C vO – C: wiring capacitance and CGS of following gate Let us determine standby power active use power Let’s work out a few related examples first.002 Fall 2000 Lecture 22 3 .
002 Fall 2000 Lecture 22 4 .Example 1: V + – I R + V – Power V2 P = VI = R Energy dissipated in time T E = VIT 6.
002 Fall 2000 Lecture 22 5 .Example 1: for our gate VS RL vI high VS RL vO vI low vO RON VS P= RL + RON 2 RON P=0 6.
002 Fall 2000 Lecture 22 6 . Find average power P.Example 2: Consider R1 S1 S2 VS + – C R2 T T1 T2 S1 closed S1 open S 2 open S 2 closed t Find energy dissipated in each cycle. 6.
002 Fall 2000 Lecture 22 7 . S2 open i VS + – R1 C + vC – assume vC = 0 at t = 0 vC VS VS R1 t i VS e R1 −t R1C t 6.T1 : S1 closed.
.Total energy provided by source during T1 E = ∫ VS i dt 0 T1 =∫ T1 VS e R1 0 2 2 −t R1C dt −t T1 R1C 0 =− VS R1C e R1 −T1 2 R1C = C VS 1 − e ≈ C VS if T1 >> R1C 2 I.e.002 Fall 2000 Lecture 22 Independent of R! 8 . 2 1 2 E1 = C VS dissipated in R1 2 6. if we wait long enough 1 2 C VS stored on C .
S1 open + vC – C R2 Initially.T2 : S2 closed.002 Fall 2000 Lecture 22 9 . vC = VS So. E2 independent of R2 ! 6. (recall T1 >> R1C) 1 2 energy stored in capacitor = CVS 2 Assume T2 >> R2C So. capacitor discharges ~fully in T2 So. energy dissipated in R2 during T2 1 2 E2 = CVS 2 E1. initially.
Putting the two together: Energy dissipated in each cycle E = E1 + E2 1 1 2 2 = CVS + CVS 2 2 E = CVS 2 energy dissipated in charging & discharging C Assumes C charges and discharges fully. Average power P= E T 2 CVS = T = CVS f 2 frequency f = 6.002 Fall 2000 Lecture 22 1 T 10 .
002 Fall 2000 Lecture 22 11 .Back to our inverter — VS RL vO vIN RON C What is P for the following input? vIN T 2 T T 2 t 1 T= f 6.
002 Fall 2000 Lecture 22 12 .Equivalent Circuit RL VS + – C RON What is P for the following input? vIN T 2 T T 2 t 1 T= f 6.
2 of A & L) P= VS RL 2 + CVS f 2( RL + RON ) (RL + RON )2 2 2 when RL >> RON VS 2 P= + CVS f 2 RL 2 P STATIC independent of f.002 Fall 2000 Lecture 22 13 .What is P for gate? We can show (see section 12. MOSFET ON half the time. er mb me re be em rem r P DYNAMIC related to switching capacitor 6.
002 Fall 2000 Lecture 22 14 . 6. half the gates in a chip can be assumed to be on. S 2 In standby mode. so dynamic power is 0 2RL Relates to standby power.What is P for gate? when RL >> RON VS 2 P= + CVS f 2 RL In standby mode. f 0. So P STATIC per gate is still V 2 .
25 milliwatts + 2.002 Fall 2000 Lecture 22 15 .5W not bad must get rid of this α VS 2 α f reduce VS 5 V → 1V 2.5 W → 150 mW next lecture 6.5 microwatts ] problem ! 1.Some numbers… a chip with 106 gates clocking C =1f F at 100 MHZ RL = 10 kΩ f = 100 × 10 6 VS = 5 V 25 P = 10 6 + 10 −15 × 25 × 100 × 10 6 2 × 10 4 = 10 6 [1.25KW! 2.
002 CIRCUITS AND ELECTRONICS Energy.002 Fall 2000 Lecture 23 1 .6. CMOS 6.
6.Review VS RL vI vO RON T1: closed T2: open R VS P= RL + RON 2 1 open closed S2 R2 VS + – S1 C 1 T = T1 + T2 = f P = CVS f 2 Reading: Section 11.002 Fall 2000 Lecture 23 2 .5 of A & L.
002 Fall 2000 Lecture 23 3 .Review Inverter — vI VS RL vO RON C Demo 1 Square wave input T= f 2 VS 2 P= + CVS f 2 RL RL >> RON T >>" RC" 2 time constant P STATIC P DYNAMIC independent of f. f 0. so dynamic power is 0 6. MOSFET ON half the time. In standby mode. So P STATIC per gate is still VS2 . In standby mode. 2RL related to switching capacitor. half the gates in a chip can be assumed to be on.
25KWatts problem ! • independent of f • also standby power (assume ½ MOSFETs ON if f 0) • must get rid of this! + 2.5V 150mW 6. VS = 5 V ⎡ 52 6 −15 2 6⎤ P = 10 ⎢ + 10 × 5 × 100 × 10 ⎥ 3 gates ⎣ 2 × 10 × 10 ⎦ = 10 6 [1.5 μ watts ] 1.Review P= VS 2 + CVS f 2 RL 2 Chip with 106 gates clocking at 100 MHz C = 1 f F.25 milliwatts + 2.5Watts not bad • αf • αVS2 reduce VS 5V 1V 2. RL = 10 KΩ . f = 100 × 10 6 .002 Fall 2000 Lecture 23 4 .
How to get rid of static power Intuition: VS i VS RL RL vI high vO low RON idea ! vI low vO high MOSFET off VS vI high vO low 6.002 Fall 2000 Lecture 23 5 .
g. VTP = 1V 5V .g.002 Fall 2000 Lecture 23 6 on when vGS ≤ VTP off when vGS > VTP e.New Device PFET • Nchannel MOSFET (NFET) D G S on when vGS ≥ VTN off when vGS < VTN e. VTN = 1V • Pchannel MOSFET (PFET) S G D ON when less than 4V 6.
002 Fall 2000 Lecture 23 7 .Consider this circuit: VS vI G + – S D D S PU = pull up vO PD = pull down G works like an inverter! IN OUT 6.
002 Fall 2000 Lecture 23 8 .Consider this circuit: works like an inverter! IN OUT vI = 5V (input high) VS = 5V vI = 0V (input low) VS = 5V RON p + vI = 5V – vO RON n = 0V + vI = 0V – vO = 5V Complementary MOS (our previous logic was called “NMOS”) Called “CMOS logic” 6.
002 Fall 2000 Lecture 23 9 .Key: no path from VS to GND! no static power! Let’s compute P DYNAMIC VS vI T vI vO C 1 f = T t RON p closed for vI low closed for vI high VS + – From C RON n P = CVS f 2 6.
2 GHz watts ~1875 3 GHz watts “keep all else same” s p! ga 6.002 Fall 2000 Lecture 23 10 . VS = 5 V .For our previous example — C = 1 f F. 1 P = CV S f = 10 − 15 2 × 5 2 × 100 × 10 6 = 2 . f = 100 MHz . 5 μwatts per gate P = 2 . 5 μwatts for 10 6 gate chip Gates 106 2x106 2x106 8x106 25x106 f P Pentium? PII? PII? PIII? PIV? 100 ~2.5 MHz watts 300 ~15 MHz watts 600 ~30 MHz watts ~240 1.
but high ~PIV and use big heatsink B Turn off clock when not in use. C Change VS depending on need.002 Fall 2000 Lecture 23 11 .How to reduce power A VS 5V 3V 1.5V 170 watts better.8V 1. next time: power supply 6.
CMOS Logic NAND: VS A B Z A B A B 0 0 0 1 1 0 1 1 Z 1 1 1 0 5V 0V G S on D 5V 5V G S off D 6.002 Fall 2000 Lecture 23 12 .
else open e. F = A ⋅ B = A + B short when A = 0 or B = 0. if we want to implement F VS short when F is true. open otherwise A B short when F is true.g. else open Z short when A · B is true.In general. else open mber law reme gan’s eMor D 6.002 Fall 2000 Lecture 23 13 .
002 CIRCUITS AND ELECTRONICS Power Conversion Circuits and Diodes 6.6.002 Fall 2000 Lecture 24 1 .
4 of A & L. capacitors. battery 3V DC PCC + – 5V DC DCtoDC UP converter Power efficiency of converter important. so use lots of devices: MOSFET switches. 6.002 Fall 2000 Lecture 24 2 .Power Conversion Circuits (PCC) PCC 110V 60Hz + – 5V DC solar cells. op amps. diodes R Reading: Chapter 16 and 4. inductors. clock circuits.
002 Fall 2000 Lecture 24 3 . let’s look at the diode iD + vD – v ⎛ VD ⎞ ⎜ e T − 1⎟ iD = I S ⎜ ⎟ ⎠ ⎝ I S = 10 −12 A VT = 0.025V Boltzmann’s constant temperature in Kelvins charge of an electron kT VT = q iD iD − IS vD mV vD V Can use this exponential model with analysis methods learned earlier analytical graphical incremental (Our fake expodweeb was modeled after this device!) 6.First.
002 Fall 2000 Lecture 24 4 .Another analysis method: piecewise–linear analysis P–L diode models: iD iD ≥ 0 “short” or on vD = 0 vD < 0 “open” or off iD = 0 0 vD Ideal diode model 6.
6V vD 6.002 Fall 2000 Lecture 24 5 .6V vD = 0 iD = 0 0.Another analysis method: piecewise–linear analysis “Practical” diode model ideal with offset iD Short segment Open segment +– 0.
Another analysis method: piecewise–linear analysis Piecewise–linear analysis method Replace nonlinear characteristic with linear segments.002 Fall 2000 Lecture 24 6 . Perform linear analysis within each segment. 6.
002 Fall 2000 Lecture 24 7 .Example (We will build up towards an ACtoDC converter) Consider + vI + – 0.6V +– R vO – vI is a sine wave 6.
6 ) / R vI ≥ 0.6V + vI < 0.002 Fall 2000 Lecture 24 8 .6 +– 0.6 – “Open segment”: iD = 0 +– 0.6 V +– + Equivalent circuit vI + – R vO – “Short segment”: iD = (vI − 0.6 + vI – R vO = 0 – 6.6V + + vI – R vO = vI − 0.Example 0 .
6 t 6.Example vI vO 0.002 Fall 2000 Lecture 24 9 .
Now consider — a halfwave rectifier 0.002 Fall 2000 Lecture 24 10 .6V +– vI + – C + R vO – 6.
A halfwave rectifier vI diode on diode off vO C current pulses charging capacitor t Demo MIT’s supply shows “snipping” at the peaks (because current drawn at the peaks) 6.002 Fall 2000 Lecture 24 11 .
III.002 Fall 2000 . S is on. diode turns off C holds vO (discharges into load) Lecture 24 12 6. vO increases S is off.DCtoDC UP Converter i se Do not u resistive s! el em en t + VI + DC – switch vS C vO – load S vS closed S open S T t Tp The circuit has 3 states: I. diode turns on C charges up. II. diode is off i increases linearly S turns off.
Assume i(0) = 0. vO(0) > 0 S on at t = 0.More detailed analysis I.002 Fall 2000 Lecture 24 13 2 . diode off L VI + – i i vO C VI T i (T ) = L VI slope = L T t di VI = L dt i is a ramp 1 ΔE = energy stored at t = T : Li( T )2 2 VI T 2 ΔE = 2L 6.
S turns off at t = T L i diode turns on (ignore diode voltage drop) vO S VI + – C VI T L i State III starts here 0 T T′ 1 ωO = LC TP t Diode turns off at T′ when i tries to go negative.002 Fall 2000 Lecture 24 14 . 6.II.
002 Fall 2000 Lecture 24 15 . diode turns on Let’s look at the voltage profile VI T L i 0 T T′ 1 ωO = LC TP t Capacitor voltage ignore diode drop vO III. 6. ΔvO vO (T ) 1 LC ωO = 0 T T′ TP t Diode turns off at T′ when I tries to go negative. S turns off at t = T.II.
ΔvO vO (T ) 1 LC ωO = 0 T T′ TP t Diode turns off at T′ when I tries to go negative.002 Fall 2000 Lecture 24 16 . diode turns on Let’s look at the voltage profile VI T L i 0 T T′ 1 ωO = LC TP t Capacitor voltage ignore diode drop vO III. S turns off at t = T.II. 6.
002 Fall 2000 Lecture 24 17 .III. S is off. no load + VI + – S C vO – C holds vO after T′ i is zero Capacitor voltage vO 0 T′ TP t 6. diode turns off Eg.
vO vO (n) TP 2TP 3TP 6.002 Fall 2000 Lecture 24 t 18 . diode turns off Eg. vO increases each cycle. S is off.III. and cycle repeats I II III I II III … Thus. if there is no load. no load + VI + – S C vO – C holds vO after T′ i is zero until S turns ON at TP.
002 Fall 2000 Lecture 24 19 . energy on capacitor nVI T 2 nΔE = 2L 1 This energy must equal CvO ( n )2 2 so. 1 ΔE = L i( t = T )2 2 2 1 VI T 2 ΔE = 2 1 ⎛ VI T ⎞ 2 L = L⎜ ⎟ 2 ⎝ L ⎠ After n cycles. or 2 1 nVI T 2 2 CvO ( n ) = 2 2L nVI T 2 vO ( n ) = LC vO ( n ) = VI T ωO n 2 2 1 ωO = LC 6.What is vO after n cycles vO(n) ? Use energy argument … (KVL tedious!) Each cycle deposits ∆E in capacitor.
How to maintain vO at a given value? + VI + – vO – load pwm vO control change T compare + vref – T Tp recall VI T 2 ΔE = 2L 2 Another example of negative feedback: if if (v (v O O − vref ) ↓ − vref ) ↑ then T ↓ then T ↑ 20 6.002 Fall 2000 Lecture 24 .
6.002 CIRCUITS AND ELECTRONICS Violating the Abstraction Barrier 6.002 Fall 2000 Lecture 25 1 .
002 Fall 2000 Lecture 25 2 .Case 1: The Double Take Problem “0” “1” Vi R VO expected observed VO “1” VO “1” huh? “0” t t “0” in forbidden region! 6.
002 Fall 2000 Lecture 25 3 .(a) DC case R Vi VO V1 very high impedance. like open circuit Vi = 5V DC VO = 5V DC V1 = 5V DC OK 6.
002 Fall 2000 Lecture 25 t 4 .3 t=0 VO t 5V VO = 2.(b) Vi Step R VO V1 very high impedance.2 not ok! 2T t 5V V1 looks ok! t=0 T 6. like open circuit 5V Vi b.1 0V b.5V t=0 b.
.. Vi R→ characteristic impedance instantaneous R divider finite propagation speed of signals 5V 0 5V 0 2T 5V 0 T 6.002 Fall 2000 Lecture 25 5 .5 R 5 ..2.
014 6.002 Fall 2000 Lecture 25 6 . Keep wires short EMO all wire D sm us e 5V VO 0 t le l Paral ation in term 0 3.5V 0 t More in 6.Question: So why did our circuits work? 5V V1 1. Termination O DEM at the R add end 5V VO 2. Look only at V1 O DEM ce Sour ation” “ in Term 0 0 T t 2.
Case 2: The Double Dip Problem strange spikes on supply V 1 0 0 1 OK driving a 50 Ω resistor! 0 V input driving a 50 Ω resistor! Why? Lecture 25 7 6.002 Fall 2000 .
low inductance wires 3.Drop across inductor VS V Ldi dt Inverter current v inductor VS solution 1. avoid big current swings 6. short wires 2.002 Fall 2000 Lecture 25 8 .
Slower may be faster! Problem a given chip worked.Case 3: The Double Team.002 Fall 2000 Lecture 25 9 . ideal C actual Let’s try speeding it up by using stronger drivers ideal ω L actual Disaster! 6. but was slow. or.
Why? Consider DEMO ok R1 C DEMO R0 dV α dt dV C dt R2 crosstalk! 6.002 Fall 2000 Lecture 25 10 .
How does this relate to chip? Solution DEMO small dV dt Load output! — put cap on outputs of chip — jitter edges — slew edges Lecture 25 11 6.002 Fall 2000 .
Case 4: The Double Jump Careful abstraction violation for the better… Recall Vo Vi expect Vo Vi but.002 Fall 2000 Lecture 25 12 . observe Vo Vi 6.
Case 4: The Double Jump Careful abstraction violation for the better… 5V Vi 5V 0V 3V 5V + 3V So. pullup has stronger drive as output rises 6.002 Fall 2000 Lecture 25 13 .
6.002 Fall 2000 Lecture 3 1 .002 CIRCUITS AND ELECTRONICS Superposition. Thévenin and Norton 6.
Review Circuit Analysis Methods KVL: ∑Vi = 0 loop KCL: ∑ Ii = 0 node VI Circuit composition rules Node method – the workhorse of 6.002 KCL at nodes using V ’s referenced from ground (KVL implicit in “ (ei − e j ) G ”) 6.002 Fall 2000 Lecture 3 2 .
VI terms 6.Linearity Consider R1 e I V + – R2 Write node equations – e −V e + −I =0 R1 R2 Notice: linear in e.002 Fall 2000 Lecture 3 3 .V . I No eV .
Linearity Consider R1 V + – R2 I Write node equations e −V e + −I =0 R1 R2 Rearrange 1 1 R + R e 1 2 conductance matrix = linear in e.V . I V + I R1 node linear sum voltages of sources G e = S 6.002 Fall 2000 Lecture 3 4 .
Linearity Write node equations e −V e + −I =0 R1 R2 Rearrange 1 1 R + R e 1 2 conductance matrix = linear in e.002 Fall 2000 Lecture 3 5 . I V + I R1 node linear sum voltages of sources G or e = S e= R2 RR V+ 1 2 I R1 + R2 R1 + R2 e = a1V1 + a2V2 + … + b1 I1 + b2 I 2 + … Linear! 6.V .
002 Fall 2000 Lecture 3 6 .Linearity ⇒ Homogeneity Superposition 6.
. . y ⇓ αx1 αx2 . .Linearity ⇒ Homogeneity Superposition Homogeneity x1 x2 . αy 6. .002 Fall 2000 Lecture 3 7 .
002 Fall 2000 Lecture 3 8 . . . y a + yb 6. ya x1b x2 b . . . . yb ⇓ x1a + x1b x2 a + x2 b .Linearity ⇒ Homogeneity Superposition Superposition x1a x2 a . .
Linearity ⇒ Homogeneity Superposition Specific superposition example: V1 0 y1 0 V2 y2 ⇓ V1 + 0 0 + V2 y1 + y2 6.002 Fall 2000 Lecture 3 9 .
Method 4: Superposition method The output of a circuit is determined by summing the responses to each source acting alone. urces o ent s d epen nly ind o 6.002 Fall 2000 Lecture 3 10 .
002 Fall 2000 Lecture 3 11 .i i + v short + v  V =0 + – i i + v open + v  I =0 6.
002 Fall 2000 Lecture 3 12 .Back to the example Use superposition method R1 e I V + – R2 6.
Back to the example Use superposition method V acting alone R1 e V + – R2 I = 0 eV = R2 V R1 + R2 I acting alone R1 R2 e I R1 R2 eI = I R1 + R2 V =0 sum superposition R2 R1 R2 e = eV + eI = V+ I R1 + R2 R1 + R2 6.002 Fall 2000 Lecture 3 Voilà ! 13 .
Demo salt water constant + – + – ? sinusoid output shows superposition 6.002 Fall 2000 Lecture 3 14 .
Consider Yet another method… n itrary etwork N Arb resistors Vm In + – i + v  i By superposition v = ∑ α mVm + ∑ β n I n + Ri m n no resistance units units By setting ∀n I n = 0.002 Fall 2000 Lecture 3 15 . ∀mVm = 0 independent of external excitation and behaves like a voltage “ vTH ” 6. ∀mVm = 0. i = 0 i = 0 also independent of external excitement & behaves like a resistor All ∀n I n = 0.
k.a. I n ’s set to 0) 6.002 Fall 2000 Lecture 3 16 . port) resistance of network seen from port ( Vm ’s.Or v = vTH + RTH i As far as the external world is concerned (for the purpose of IV relation). “Arbitrary network N” is indistinguishable from: RTH N Thévenin equivalent network + vTH – + v  i vTH RTH open circuit voltage at terminal pair (a.
6.002 Fall 2000 Lecture 3 17 .Method 4: The Thévenin Method N + – + – i + v  E Thévenin equivalent RTH i + v  + vTH – E Replace network N with its Thévenin equivalent. then solve external network E.
Example: i1 R1 + V – R2 I i1 R1 + V – RTH VTH + I – i1 = V − VTH R1 + RTH 6.002 Fall 2000 Lecture 3 18 .
Example: VTH : VTH = IR2 + VTH  R2 I RTH : RTH = R2 + RTH  R2 6.002 Fall 2000 Lecture 3 19 .
i v = vTH + RTH i 1 RTH v vTH “V ” OC − I SC Open circuit (i ≡ 0) Short circuit (v ≡ 0) v = vTH − vTH i = RTH VOC − I SC 6.002 Fall 2000 Lecture 3 20 .Graphically.
002 Fall 2000 Lecture 3 21 .Method 5: in recitation. see text The Norton Method i + – + – + v  IN RTH = RN Norton equivalent IN = VTH RTH 6.
I — V Combination rules Node method Superposition Thévenin Norton Next Nonlinear analysis Discretize voltage … 6. I.002 Fall 2000 Lecture 3 101100 … 22 . V LCA EE Linear networks Analysis methods (linear) KVL.Summary Discretize matter LMD Physics R. KCL.
002 Fall 2000 Lecture 4 1 .6.002 CIRCUITS AND ELECTRONICS The Digital Abstraction 6.
Thévenin.002 Fall 2000 Lecture 4 2 . Norton apply only for linear circuits) 6. Thévenin.Review Discretize matter by agreeing to observe the lumped matter discipline Lumped Circuit Abstraction Analysis tool kit: KVL/KCL. Norton (remember superposition. node method. superposition.
002 Fall 2000 Lecture 4 3 . we will see shortly that the tools learned in the previous three lectures are sufficient to analyze simple digital circuits Reading: Chapter 5 of Agarwal & Lang 6.Today Discretize value Digital abstraction Interestingly.
V0 = R2 R1 V1 + V2 R1 + R2 R1 + R2 V1 + V2 2 If R1 = R 2 .002 Fall 2000 Lecture 4 4 . why digital? In the past … Analog signal processing R1 V1 + – V2 R2 V0 V 1 and V 2 might represent the outputs of two sensors. + – By superposition. V0 = The above is an “adder” circuit. for example. 6.But first.
002 Fall 2000 Lecture 4 5 . between 3. 6.Noise Problem t add noise on this wire Receiver: huh? … noise hampers our ability to distinguish between small differences in value — e.2V.g.1V and 3.
E. numbers larger than 1 can be represented using multiple binary digits and coding. much like using multiple decimal digits to represent numbers greater than 9.g.Value Discretization Restrict values to be one of two HIGH 5V TRUE 1 LOW 0V FALSE 0 0 and 1 …like two digits Why is this discretization useful? (Remember. the binary number 101 has decimal value 5.002 Fall 2000 Lecture 4 6 ..) 6.
5V 0V LOW VS noise VN VR VN = 0V receiver VR “0” “1” “0” 5V t 2.Digital System sender VS 5V “0” “1” “0” HIGH 2.5V 0V 6.2V VS “0” “1” “0” t t 2.5V 0V t With noise VS “0” “1” “0” 5V 2.2V 0.002 Fall 2000 VN = 0.5V t Lecture 4 7 .
002 Fall 2000 Lecture 4 8 .5V 6.5V For “0”: noise margin 0V to 2.Digital System Better noise immunity Lots of “noise margin” For “1”: noise margin 5V to 2.5V = 2.5V = 2.
Voltage Thresholds and Logic Values 5V 1 sender 0 1 0 0V 1 2.5V receiver 0 6.002 Fall 2000 Lecture 4 9 .
5V 1 sender 0 0V 3V 2V forbidden region VH VL 1 receiver 0 “1” “0” 6.But. but.5V? Hmmm… create “no man’s land” or forbidden region For example. but … What about 2.002 Fall 2000 V H 5V V L 10 0V Lecture 4 .
but.But. but … Where’s the noise margin? What if the sender sent 1: 5V 1 sender 0 V 0H VH ? Hold the sender to tougher standards! 1 V IH V IL V 0L receiver 0 0V 6.002 Fall 2000 Lecture 4 11 .
V  0H V 0L 12 .But.002 Fall 2000 Lecture 4 IH V IL . but … Where’s the noise margin? What if the sender sent 1: 5V 1 sender 0 V 0H VH ? Hold the sender to tougher standards! 1 Noise margins V IH V IL V 0L receiver 0 0V “1” noise margin: V “0” noise margin: 6. but.
then the system guarantees its outputs will meet valid output thresholds.5V V 0H V IH V IL V 0L 0V 0 1 0 1 sender t 5V V 0H V IH V IL V 0L 0V 0 1 0 1 receiver t Digital systems follow static discipline: if inputs to the digital system meet valid input thresholds. 6.002 Fall 2000 Lecture 4 13 .
F Can also represent numbers 6.002 Fall 2000 Lecture 4 14 .0 Map naturally to logic: T. we have only two values — 1.Processing digital signals Recall.
Processing digital signals Boolean Logic If X is true and Y is true Then Z is true else Z is false. “1” AND gate Truth table representation: X Y Z 0 0 1 1 0 1 0 1 0 0 0 1 Enumerate all input combinations 6. Z are digital signals “0” . Z = X AND Y Z = X • Y Boolean equation X Y Z X.002 Fall 2000 Lecture 4 15 . Y.
002 Fall 2000 Lecture 4 16 .Combinational gate abstraction Adheres to static discipline Outputs are a function of inputs alone. 6. Digital logic designers do not have to care about what is inside a gate.
Demo X Y Z Noise X Y Z = X • Y 6.002 Fall 2000 Lecture 4 17 Z .
Examples for recitation X t Y t Z t Z = X • Y 6.002 Fall 2000 Lecture 4 18 .
002 Fall 2000 Lecture 4 19 .In recitation… Another example of a gate If (A is true) OR (B is true) then C is true else C is false C = A + B A B Boolean equation OR C OR gate B Inverter X Y More gates B Z NAND Z = X • Y 6.
Boolean Identities X X X X 1 = 0 0 = 1 AB + AC = A • (B + C) • 1 = X • 0 = X + 1 = 1 +0 = X Digital Circuits Implement: B C A output = A + B • C B•C output 6.002 Fall 2000 Lecture 4 20 .
002 CIRCUITS AND ELECTRONICS Inside the Digital Gate 6.002 Fall 2000 Lecture 5 1 .6.
Review The Digital Abstraction Discretize value 0.002 Fall 2000 Lecture 5 2 . 1 Static discipline meet voltage thresholds sender VOH VOL receiver VIH VIL forbidden region Specifies how gates must be designed 6.
Review Combinational gate abstraction outputs function of input alone satisfies static discipline A B C NAND A 0 0 1 1 B 0 1 0 1 C 1 1 1 0 6.002 Fall 2000 Lecture 5 3 .
For example: a digital circuit A B C A⋅ B Demo D ) D = ( ⋅ (A ⋅ B ) C 3 gates here A Pentium III class microprocessor is a circuit with over 4 million gates !! The RAW chip being built at the Lab for Computer Science at MIT has about 3 million gates. 6.002 Fall 2000 Lecture 5 4 .
How to build a digital gate Analogy l ik e power supply A (li taps ) itches ke sw B C if A=ON AND B=ON C has H20 else C has no H20 Use this insight to build an AND gate. 6.002 Fall 2000 Lecture 5 5 .
How to build a digital gate OR gate A C B 6.002 Fall 2000 Lecture 5 6 .
002 Fall 2000 Lecture 5 7 .Electrical Analogy A B C V + – Bulb C is ON if A AND B are ON. else C is off Key: “switch” device 6.
002 Fall 2000 Lecture 5 8 .Electrical Analogy Key: “switch” device equivalent ckt in in C =0 out in control C out 3Terminal device if C = 0 else C=1 out short circuit between in and out open circuit between in and out For mechanical switch. control mechanical pressure 6.
Consider RL IN VOUT + VS – VS = VS RL VOUT C OUT “1” C VS VOUT C =0 Truth table for C VOUT 0 1 1 0 VS VOUT C =1 6.002 Fall 2000 Lecture 5 9 .
002 Fall 2000 Lecture 5 10 .What about? VS VOUT Truth table for c1 c2 VO 0 0 1 0 1 1 1 0 1 1 1 0 c1 c2 VS Truth table for c1 c2 VO 0 0 1 0 1 0 1 0 0 1 1 0 VOUT c1 c2 6.
002 Fall 2000 Lecture 5 11 .What about? can also build compound gates VS D A B C D = (A ⋅ B) + C 6.
The MOSFET Device
MetalOxide Semiconductor FieldEffect Transistor
drain D
G gate
≡
S source
3 terminal lumped element behaves like a switch
G : control terminal D, S : behave in a symmetric manner (for our needs)
6.002 Fall 2000 Lecture 5
12
The MOSFET Device
ut eck o tbook Ch ex l the t s interna for it ture. iG t r uc s
Understand its operation by viewing it as a twoport element —
G
D S
iDS
+
+ vGS –
vDS
– D iDS on S
D G vGS < VT
off
G vGS ≥ VT
S
VT ≈ 1V typically
“Switch” model (S model) of the MOSFET
6.002 Fall 2000
Lecture 5
13
Demo
Check the MOS device on a scope. i
DS
+ + vGS – vDS –
iDS vGS ≥ VT
vGS < VT iDS vs vDS
6.002 Fall 2000 Lecture 5
vDS
14
A MOSFET Inverter
VS = 5V
vOUT
RL
B
A
IN
A
Note the power of abstraction.
B
The abstract inverter gate representation hides the internal details such as power supply connections, RL, GND, etc. (When we build digital circuits, the and are common across all gates!)
6.002 Fall 2000 Lecture 5
15
Example
vOUT
5V
vIN
vOUT
0V V T =1V
5V
v IN
The T1000 model laptop desires gates that satisfy the static discipline with voltage thresholds. Does out inverter qualify?
VOL = 0.5V VOH = 4.5V 1:
sender 5 4.5 V OH
VIL = 0.9V VIH = 4.1V
receiver
5 4.1 0.9
1
VIH VIL
0 Our inverter satisfies this.
6.002 Fall 2000 Lecture 5
0:
0.5 0
VOL
0
16
E.g.: Does our inverter satisfy the static discipline for these thresholds:
VOL = 0.2V VOH = 4.8V VOL = 0.5V VOH = 4.5V
VIL = 0.5V VIH = 4.5V
yes
x
VIL = 1.5V VIH = 3.5V
no
6.002 Fall 2000
Lecture 5
17
Switch resistor (SR) model of MOSFET
…more accurate MOS model
D D G S RON
D G
G
S vGS < VT
vGS ≥ VT S
e.g. RON = 5 KΩ
6.002 Fall 2000
Lecture 5
18
SR Model of MOSFET
D G D D G S RON
G
S vGS < VT
vGS ≥ VT S
MOSFET S model
MOSFET SR model
iDS
vGS ≥ VT
vGS ≥ VT iDS
1 RON
vGS < VT vDS
vGS < VT vDS
6.002 Fall 2000
Lecture 5
19
VS such that: V R v = S ON ≤ V OL OUT R +R L ON vGS ≥ VT RON vOUT 6. RON.Using the SR model RL IN vOUT + VS – VS = VS RL vOUT C OUT “1” C VS RL Truth table for vOUT RON C =0 C VOUT 0 1 1 0 VS RL C =1 Choose RL.002 Fall 2000 Lecture 5 20 .
6.002
CIRCUITS AND ELECTRONICS
Nonlinear Analysis
6.002 Fall 2000
Lecture 6
1
Review
Discretize matter m1 m2 m3 m4 m5 KVL, KCL, iv Composition rules Node method Superposition Thévenin, Norton LCA any circuit linear circuits
6.002 Fall 2000
Lecture 6
2
Review
Discretize value Digital abstraction Subcircuits for given “switch” setting are linear! So, all 5 methods (m1 – m5) can be
applied
VS
RL
A =1 B =1
VS
RL
C
A B
C RON RON
SR MOSFET Model
6.002 Fall 2000
Lecture 6
3
Today
Nonlinear Analysis Analytical method based on m1, m2, m3 Graphical method Introduction to incremental analysis
6.002 Fall 2000
Lecture 6
4
How do we analyze nonlinear circuits, for example:
Hypothetical nonlinear D device (Expo Dweeb ☺)
iD
V
+ –
+ vD 
+ vD iD
D
iD
iD = aebvD
a
0,0
6.002 Fall 2000 Lecture 6
vD
(Curiously, the device supplies power when vD is negative)
5
Method 1: Analytical Method
Using the node method,
(remember the node method applies for linear or nonlinear circuits)
vD − V + iD = 0 R
iD = aebvD
1 2
2 unknowns
2 equations
Solve the equation by trial and error numerical methods
6.002 Fall 2000
Lecture 6
6
Method 2: Graphical Method
Notice: the solution satisfies equations 1 and 2
iD
2
iD = aebvD vD
a
iD
V vD 1 iD = − R R
1 slope = − R
V R
V
6.002 Fall 2000 Lecture 6
vD
7
Combine the two constraints
iD
V 1 R ~ 0 .4 a ¼
~ 0.5
called “loadline” for reasons you will see later
V 1 vD = 0.5V iD = 0.4 A
vD
e.g.
V =1 R =1 1 4 b =1 a=
6.002 Fall 2000
Lecture 6
8
002 Fall 2000 linear problem! will result in distortion Lecture 6 9 .Method 3: Incremental Analysis Motivation: music over a light beam Can we pull this off? iD iR vI (t ) + – + vD LED light intensity I D ∝ iD vI music signal AMP iR ∝ I R light intensity IR in photoreceiver LED: Light Emitting expoDweep ☺ t vI (t ) iD (t ) light iR (t ) sound nonlinear 6.
Problem: The LED is nonlinear iD distortion iD t vD t vD vD = vI iD vD t 6.002 Fall 2000 Lecture 6 10 .
002 Fall 2000 Lecture 6 11 .If only it were linear … iD iD vD vD t it would’ve been ok. What do we do? Zen is the answer … next lecture! 6.
002 Fall 2000 Lecture 7 1 .6.002 CIRCUITS AND ELECTRONICS Incremental Analysis 6.
5 6.002 Fall 2000 Lecture 7 2 .Review Nonlinear Analysis Analytical method Graphical method Today Incremental analysis Reading: Section 4.
Method 3: Incremental Analysis Motivation: music over a light beam Can we pull this off? iD iR vI (t ) + – + vD LED light intensity I D ∝ iD vI music signal AMP iR ∝ I R light intensity IR in photoreceiver LED: Light Emitting expoDweep ☺ t vI (t ) iD (t ) light iR (t ) sound nonlinear 6.002 Fall 2000 linear problem! will result in distortion Lecture 7 3 .
Problem: The LED is nonlinear iD distortion iD t vD t vD vD = vI iD vD t 6.002 Fall 2000 Lecture 7 4 .
Insight: ID iD small region looks linear (about VD .002 Fall 2000 Lecture 7 . ID) VD vD DC offset or DC bias Trick: vi (t ) + – VI iD = I D + id + vD LED vD = VD + vd VI vI + – vi 5 6.
Result iD id ID VD vD very small vd 6.002 Fall 2000 Lecture 7 6 .
Result
vD = vI
vd
VD
vD
t
iD iD
id
ID
~linear!
t
Demo
6.002 Fall 2000 Lecture 7
7
The incremental method:
(or small signal method)
1. Operate at some DC offset or bias point VD, ID . 2. Superimpose small signal vd (music) on top of VD . 3. Response id to small signal vd is approximately linear. Notation:
iD = I D + id
total DC small variable offset superimposed signal
6.002 Fall 2000
Lecture 7
8
What does this mean mathematically?
Or, why is the small signal response linear? nonlinear
iD = f (vD )
We replaced
large DC
vD = VD + ∆vD
vd
increment about VD
using Taylor’s Expansion to expand f(vD) near vD=VD :
iD = f (VD ) +
+
df (vD ) ⋅ ∆vD dvD vD =VD
1 d 2 f (v D ) 2! dvD 2 v ⋅ ∆vD +
D =VD
2
neglect higher order terms because ∆vD is small
6.002 Fall 2000 Lecture 7
9
iD ≈ f (VD ) +
constant w.r.t. ∆vD We can write
d f (v D ) ⋅ ∆vD d vD vD =VD
constant w.r.t. ∆vD slope at VD, ID
X : I D + ∆iD ≈ f (VD ) +
d f (v D ) ⋅ ∆ vD d vD vD =VD
equating DC and timevarying parts,
I D = f (VD )
operating point
d f (v D ) ∆iD = ⋅ ∆vD d vD vD =VD
constant w.r.t. ∆vD so, ∆ iD ∝ ∆vD
6.002 Fall 2000 Lecture 7
By notation, ∆ iD = id ∆ v D = vd
10
In our example,
iD = a e
bv D
From X : I D + id ≈ a e bVD + a e bVD ⋅ b ⋅ vd Equate DC and incremental terms,
I D = a ebVD
operating point aka bias pt. aka DC offset
id = a ebVD ⋅ b ⋅ vd id = I D ⋅ b ⋅ vd
constant small signal behavior linear!
6.002 Fall 2000
Lecture 7
11
Graphical interpretation
I D = a ebVD
operating point
id = I D ⋅ b ⋅ vd
A
iD ID
slope at VD, ID B operating point vd vD
id
VD
we are approximating A with B
6.002 Fall 2000
Lecture 7
12
We saw the small signal Large signal circuit:
VI
graphically mathematically now, circuit
+ –
+ LED VD 
ID
I D = a ebVD
Small signal response: id = I D b vd + vd 
behaves like: small signal circuit:
id
R=
1 ID b
vi
+ –
+ vd 
id
1 I Db Linear!
6.002 Fall 2000
Lecture 7
13
6.002
CIRCUITS AND ELECTRONICS
Dependent Sources and Amplifiers
6.002 – Fall 2002: Lecture 8
1
7.1.002 – Fall 2002: Lecture 8 2 .Review Nonlinear circuits — can use the node method Small signal trick resulted in linear response Today Dependent sources Amplifiers Reading: Chapter 7.2 6.
002 – Fall 2002: Lecture 8 3 .g.Dependent sources Seen previously Resistor Independent Current source + i + i v – R v – I v i= R i=I 2terminal 1port devices New type of device: Dependent source iI i O + control port vI f ( vI ) + vO – 2port device output port – E.. Voltage Controlled Current Source Current at output port is a function of voltage at the input port 6.
002 – Fall 2002: Lecture 8 4 .Dependent Sources: Examples Example 1: Find V + R V – independent current source I = I0 V = I0R 6.
002 – Fall 2002: Lecture 8 5 .Dependent Sources: Examples Example 2: Find V voltage controled current source + R V – K I = f (V ) = V + R V – iI + vI f (vI ) = K vI iO + vO – – 6.
002 – Fall 2002: Lecture 8 6 .g.Dependent Sources: Examples Example 2: Find V voltage controled current source + R V – K I = f (V ) = V e. K = 103 Amp·Volt R = 1kΩ K V = IR = R V or V 2 = KR or V = KR = 10 −3 ⋅ 10 3 = 1 Volt 6.
g.002 – Fall 2002: Lecture 8 7 .Another dependent source example RL iIN iD VS + – vI + – + vIN + vO – – e. 6. iD = f (vIN ) iD = f (vIN ) K 2 = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise Find vO as a function of vI .
002 – Fall 2002: Lecture 8 8 . 6. iD = f (vIN ) K 2 = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise Find vO as a function of vI .Another dependent source example VS RL iIN iD vI + – + vIN + vO – – iD = f (vIN ) e.g.
6.Another dependent source example VS RL vI vI vO K 2 iD = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise + – Find vO as a function of vI .002 – Fall 2002: Lecture 8 9 .
002 – Fall 2002: Lecture 8 10 .Another dependent source example VS RL vI vI vO K 2 iD = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise + – KVL − VS + iD RL + vO = 0 vO = VS − iD RL K 2 vO = VS − (vI − 1) RL 2 vO = VS Hold that thought for vI ≥ 1 for vI < 1 6.
002 – Fall 2002: Lecture 8 11 . Amplifiers 6.Next.
amplification is key to noise tolerance during communication 6.Why amplify? Signal amplification key to both analog and digital processing.002 – Fall 2002: Lecture 8 12 . Analog: IN AMP OUT Input Port Output Port Besides the obvious advantages of being heard farther away.
002 – Fall 2002: Lecture 8 13 .Why amplify? Amplification is key to noise tolerance during communication No amplification e nois 10 mV useful signal 1 mV huh? 6.
Try amplification e nois AMP not bad! 6.002 – Fall 2002: Lecture 8 14 .
002 – Fall 2002: Lecture 8 15 .Why amplify? Digital: Valid region 5V 5V VIH IN VIL 0V OUT Digital System 0V VOH VOL 5V VIH VIL IN V OH V OL 5V OUT 0V t 0V t 6.
Why amplify? Digital: Static discipline requires amplification! Minimum amplification needed: VIH VIL VOH VOL VOH − VOL VIH − VIL 6.002 – Fall 2002: Lecture 8 16 .
002 – Fall 2002: Lecture 8 17 . for convenience we commonly observe “the common ground discipline. actually Power port Input port iI +v – I Amplifier + v Output – O port iO We often don’t show the power port.” In other words. Also. all ports often share a common reference point called “ground.An amplifier is a 3ported device.” POWER IN OUT How do we build one? 6.
Remember? VS RL vI vI vO K 2 iD = (vIN − 1) for vIN ≥ 1 2 iD = 0 otherwise + – KVL − VS + iD RL + vO = 0 vO = VS − iD RL K 2 vO = VS − (vI − 1) RL 2 vO = VS Claim: This is an amplifier for vI ≥ 1 for vI < 1 6.002 – Fall 2002: Lecture 8 18 .
K = 2 2 .So.g. VS = 10V . mA e. where’s the amplification? Let’s look at the vO versus vI curve.002 – Fall 2002: Lecture 8 amplification 19 . RL = 5 kΩ V K 2 vO = VS − RL (vI − 1) 2 2 2 = 10 − ⋅10 −3 ⋅ 5 ⋅ 103 (vI − 1) 2 vO = 10 − 5 (vI − 1) vO VS 2 ∆vO 1 ∆vI vI ∆vO >1 ∆v I 6.
50 ~ 0.00 2.00 10.4 vO 10.0 1.5 2.3 2.Plot vO versus vI vO = 10 − 5 (vI − 1) 2 vI 0.00 8.1 change in vI 1V change in vO Gain! Demo Measure vO .0 2.80 1.00 4.002 – Fall 2002: Lecture 8 20 .75 5.1 2. 6.0 1.2 2.00 0.
K 2 vO = VS − RL (vI − 1) 2 So is mathematically predicted behavior 6.One nit … vO What happens here? 1 vI Mathematically.002 – Fall 2002: Lecture 8 21 .
VCCS consumes power: vO iD For vO<0. from vI iD = K (vI − 1)2 2 VS RL vO for vI ≥ 1 VCCS iD For vO>0.002 – Fall 2002: Lecture 8 22 . VCCS must supply power! 6.One nit … vO K 2 vO = VS − RL (vI − 1) 2 What happens here? 1 However.
e. vO = VS − RL (vI − 1) 2 vI where vO goes ve 6.If VCCS is a device that can source power.002 – Fall 2002: Lecture 8 23 . then the mathematically predicted behavior will be observed — vO K 2 i.
something must give! Turns out.If VCCS is a passive device. so vO cannot go ve.002 – Fall 2002: Lecture 8 24 . So. our model breaks down. e. then it cannot source power. iD saturates (stops increasing) and we observe: Commonly vO 1 vI 6.g. K 2 iD = (vI − 1) 2 will no longer be valid when vO ≤ 0 .
6.002 Fall 2000 Lecture 9 1 .002 CIRCUITS AND ELECTRONICS MOSFET Amplifier Large Signal Analysis 6.
5.3–7.7 6. quick review of amp … Reading: Chapter 7.1 of the text] Next.002 Fall 2000 Lecture 9 2 . solve for one independent source at a time [section 3.Review Amp constructed using dependent source control a a′ port DS b output b ′ port Dependent source in a circuit v + – a + a′ – b i = f (v ) b′ Superposition with dependent sources: one way leave all dependent sources in.
Amp review VS RL vO VCCS vI + – K 2 iD = (vI − 1) 2 for vI ≥ 1V = 0 otherwise vO = VS − iD RL K (vI − 1)2 2 6.002 Fall 2000 Lecture 9 3 .
the MOSFET … 6.Key device Needed: v A B i = f (v ) voltage controlled current source C Let’s look at our old friend.002 Fall 2000 Lecture 9 4 .
D G vGS < VT D G S vGS ≥ VT S ? 6. we sort of lied. the MOSFET … First.Key device Needed: Our old friend. The onstate behavior of the MOSFET is quite a bit more complex than either the ideal switch or the resistor model would have you believe.002 Fall 2000 Lecture 9 5 .
Graphically + vGS – iDS v+ DS – Demo egio n iDS vGS ≥ VT iDS vGS ≥ VT iDS vDS = vGS − VT vGS 1 Saturation region T ri o de r vGS 2 .. vGS3 vDS vGS < VT vDS vGS < VT vDS S MODEL SR MODEL vGS < VT Cutoff region 6.002 Fall 2000 Lecture 9 6 ..
002 Fall 2000 Lecture 9 . vGS3 vDS vGS < VT vDS vGS < VT vDS S MODEL SR MODEL vGS < VT vDS ≥ vGS − VT Notice that MOSFET behaves like a current source 7 when 6..Graphically + vGS – iDS v+ DS – egio n iDS vGS ≥ VT iDS vGS ≥ VT iDS vDS = vGS − VT vGS 1 Saturation region T ri o de r vGS 2 ..
MOSFET SCS Model When vDS ≥ vGS − VT the MOSFET is in its saturation region.002 Fall 2000 Lecture 9 8 . and the switch current source (SCS) model of the MOSFET is more accurate than the S or SR model D G vGS < VT D G S vGS G ≥ VT S D iDS = f (vGS ) K 2 = (vGS − VT ) 2 S when vDS ≥ vGS − VT 6.
.. vGS3 vDS vDS vDS vGS < VT SCS MODEL for analog designs S MODEL for fun! SR MODEL for digital designs When to use each model in 6.Reconciling the models… iDS vGS ≥ VT vGS ≥ VT vGS < VT vGS < VT iDS iDS vDS = vGS − VT vGS 1 Saturation region T ri o de r egio n vGS 2 .002? Note: alternatively (in more advanced courses) vDS ≥ vGS − VT vDS < vGS − VT use SCS model use SR model or.8 of A&L) 6.002 Fall 2000 Lecture 9 9 . use SU Model (Section 7.
we must operate it in its saturation region only.002 Fall 2000 Lecture 9 10 . To do so. we promise to adhere to the “saturation discipline” 6.Back to Amplifier VS vI AMP vO VS RL vI G D S vO K 2 iDS = (vI − VT ) 2 in saturation region To ensure the MOSFET operates as a VCCS.
We promise to adhere to the “saturation discipline. we must operate it in its saturation region only.” In other words.MOSFET Amplifier VS RL vI G D S vO K 2 iDS = (vI − VT ) 2 in saturation region To ensure the MOSFET operates as a VCCS.002 Fall 2000 Lecture 9 at all times. we will operate the amp circuit such that vGS ≥ VT and vDS ≥ vGS – VT vO ≥ vI – vT 6. 11 .
replace the MOSFET with its SCS model.Let’s analyze the circuit First.002 Fall 2000 Lecture 9 12 . VS RL vO G D + vI – iDS vGS = vI + – K 2 = (vI − VT ) 2 A S for vO ≥ vI − VT 6.
Let’s analyze the circuit VS RL vO G D + vI – iDS = vGS = vI + – K (vI − VT )2 2 A S for vO ≥ vI − VT (vO = vDS in our example) 1 Analytical method: vO vs vI vO = VS − iDS RL B K 2 or vO = VS − (vI − VT ) RL for vI ≥ VT 2 vO ≥ vI − VT vO = VS vI < VT (MOSFET turns off) for 6.002 Fall 2000 Lecture 9 13 .
002 Fall 2000 Lecture 9 14 .Graphical method vO vs vI K 2 From A : iDS = (vI − VT ) . 2 vO ≥ vI − VT 2 for ⇓ 2iDS vO ≥ K ⇓ K 2 iDS ≤ vO 2 B : iDS VS v0 = − RL RL 6.
002 Fall 2000 vO A and B must be met Lecture 9 15 .2 Graphical method vO vs vI K 2 K 2 A : iDS = (vI − VT ) . for iDS ≤ vO 2 2 V v iDS = S − O B : RL RL iDS VS RL B iDS Lo ad K 2 ≤ vO 2 A vI = vGS li n e VS Constraints 6.
given VI. we can find VO. Then. 6.002 Fall 2000 Lecture 9 16 . IDS .2 Graphical method vO vs vI iDS VS RL B iDS ≤ K 2 vO 2 A vI I DS VI vO VO VS Constraints A and B must be met.
Large Signal Analysis of Amplifier (under “saturation discipline”) 1 2 vO versus vI Valid input operating range and valid output operating range 6.002 Fall 2000 Lecture 9 17 .
Large Signal Analysis 1 vO versus vI vO VS K 2 VS − (vI − VT ) RL 2 VT vO = vI − VT gets into triode region vI 6.002 Fall 2000 Lecture 9 18 .
Large Signal Analysis 2 What are valid operating ranges under the saturation discipline? Our Constraints vI ≥ VT vO ≥ vI − VT iDS iDS ≤ K 2 ≤ vO 2 K 2 vO 2 iDS VS RL K 2 iDS = (vI − VT ) 2 vI v V iDS = S − O RL RL vO VS ? 6.002 Fall 2000 vI = VT vO = VS and iDS = 0 Lecture 9 19 .
002 Fall 2000 Lecture 9 vI = VT vO = VS and iDS = 0 20 .Large Signal Analysis 2 What are valid operating ranges under the saturation discipline? iDS iDS K 2 ≤ vO 2 K 2 iDS = (vI − VT ) 2 vI VS vO iDS = − RL RL vO − 1 + 1 + 2 KRLVS vI = VT + KRL − 1 + 1 + 2 KRLVS vO = KRL VS vO iDS = − RL RL 6.
002 Fall 2000 Lecture 9 21 .Large Signal Analysis Summary 1 vO versus vI vO = VS − K (vI − VT )2 RL 2 2 Valid operating ranges under the saturation discipline? Valid input range: vI : VT to − 1 + 1 + 2 KRLVS VT + KRL corresponding output range: vO : VS to − 1 + 1 + 2 KRLVS KRL 6.
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