This action might not be possible to undo. Are you sure you want to continue?
Document Revision: 1.01 Date: 3rd April, 2005
16301 Blue Ridge Road, Missouri City, Texas 77489 USA Telephone: 1-713-283-9970 Fax: 1-281-416-2806 E-mail: firstname.lastname@example.org Web: www.bipom.com
This document is available for download from www.bipom.com
manufacturability. reliability. In a very simplistic form. memory and even other micro-controllers. weight. displays. a micro-controller system can be viewed as a system that reads from (monitors) inputs. availability. Many interface methods have been developed over the years to solve the complex problem of balancing circuit design criteria such as features. keypads. power consumption. size. switches. such as sensors. performs processing and writes to ( controls ) outputs.Overview Micro-controllers are useful to the extent that they communicate with other devices. Input Devices Microcontroller Output Devices Microcontroller Interfaces Digital Analog On/Off Parallel Serial Voltage Current Asynchronous 1-wire RS232/RS485 Ethernet Synchronous 2-wire (I2C) 4-wire (SPI. motors. cost. Microwire) Page 2 . Many microcontroller designs typically mix multiple interfacing methods.
4 P2.7 P2.1 P2.4 P2.3 P2.0 2 5 8 0 3 6 9 # A B C D 4 7 * Rows Page 3 .5 8051 Microcontroller (AT89C51ED2) P2.7 P2.0 Digital Input Example: Keypad Interface 4X4 Matrix Keypad Interface P2.6 P2.6 Columns Columns P2.5 8051 Microcontroller (AT89C51ED2) Rows 1 P2.2 P2.Digital Inputs/Outputs On/OFF control and monitoring. Advantages • • • • Simplest interface Lowest-cost to implement (built into the microcontroller) High speed Low programming overhead • • • Disadvantages Only on/off control/monitoring Short distance.3 P2. Single device control/monitoring Digital Input Example: Reading the status of buttons or switches Single-ended (non-matrix) switches P2. few feet maximum.1 P2.2 P2.
1 P0.3 P0.2 P0.Digital Output Example: LED control VCC LED Interface Current Limiting Resistors 8051 Microcontroller (AT89C51ED2) LED's P0.4 Page 4 .0 Digital Output Example: Relay control VCC Relay Interface 8051 Microcontroller (AT89C51ED2) 7407 P1.
Analog Inputs/Outputs Voltage-based control and monitoring.5V 0 to 4V 0 to 5V +/.4V +/. Disadvantages • • • • Advantages Simple interface Low cost for low-resolutions High speed Low programming overhead • • • • High cost for higher resolutions Not all microcontrollers have analog inputs/outputs built-in Complicates the circuit design when external ADC or DAC are needed.2. Voltage type: Typical ranges • • • • • • 0 to 2. Short distance. few feet maximum.5V +/.5V Current type: Typical ranges • • 0-20mA 4-20mA Analog Interface Vcc Amplifier Potentiometer LM35 Temperature Sensor Vcc Vcc Analog/ Digital Converter (ADC) 8051 Microcontroller (AT89C51ED2) Digital/ Analog Converter (DAC) Strain-gage 4-20mA Output Page 5 .
2 P2.1 P0.4 P0.2 P0.7 P0.5 P0.1 P2.6 P0.1 P0.7 P0.g.6 P0.g.5 P0.4 P0.Parallel Bus Consists of multiple digital inputs/outputs. Most common types: • • • • 4-bit 8-bit ( e.0 D7 D6 D5 D4 D3 D2 D1 D0 E R/W RS Hello World 8-bit LCD Interface Alphanumeric LCD 8051 Microcontroller (AT89C51ED2) P0. ISA ) 32-bit ( e.3 P0.2 P0.0 D7 D6 D5 D4 D3 D2 D1 D0 E R/W RS Hello World Page 6 . Centronics ) 16-bit ( e.0 P2. PCI ) Disadvantages • Large number of microcontroller pins that needed for implementing the parallel bus • • • Advantages High speed High throughput: Several bits are transmitted on one clock transition Low cost Example: LCD Interface 4-bit LCD Interface Alphanumeric LCD 8051 Microcontroller (AT89C51ED2) P0.g.
I2C is 5V. many examples Supports multi-master configuration Disadvantages • • • Short distance Slow speed: 100 KHz although 400 KHz and 1 MHz slave devise exist. Maximum allowable capacitance on the lines is 400 pF.2K SDA (P1.7) SCL (P1. Only the device with the correct address communicates with the master. To start the communications. Typical device capacitance is 10 pF. Originated by Philips Semiconductor in the early 80’s to connect a microcontroller to peripheral devices in TV sets. Signals: DATA (SDA). CLOCK (SCL) and Ground. SDA is always bi-directional. These can not coexist with slower devices. Advantages Multiple slave devices can be accessed with only 3 wires Low-cost to implement Implemented in hardware or software Ease to implement. Limited device addresses • • • • • 2-wire (I2C) interface VCC 2. By definition.Serial Buses I2C ( Inter Integrated Circuit bus ) 2-wire interface with one master and multiple slaves ( multi-master configurations possible ). the bus master (typically a microcontroller) places the address of the device with which it intends to communicate (the slave) on the bus. SCL is bidirectional only in multi-master mode.6) SDA AT24C04 SCL EEPROM 8051 Microcontroller (AT89C51ED2) SCL SDA A0 A1 A2 Lithium Battery DS1307 Real-Time Clock Crystal Page 7 .2K 2. All slave devices monitor the bus to determine if the master device is sending their address.
Data Validity Data can change while the clock is low. Start condition is defined as SDA signal going low while SCL signal is high. Acknowledge (ACK) Page 8 . Data should remain stable while the clock is going high.Start and Stop An I2C master prepares to communicate with a slave device first by generating a Start condition on the bus. Stop condition is defined as SDA going high while SCL is high.
A0.Writing a byte to a serial EEPROM (24C04 ) on the I2C bus: where Device Address is defined as P0. P2 indicate the page number ( 2Kbit pages ). P1. A2 indicate the device number on the bus. Reading a byte from a serial EEPROM (24C04 ) on the I2C bus ( starting from the current address ) Example: Page 9 . A1.
SPI bus is a master/slave interface. Advantages • • • • • Multiple slave devices can be accessed with only few wires Low-cost Implemented in hardware or software Ease to implement. one is referred to as the "master" and the other as the "slave" device.3 P3. Whenever two devices communicate. 4MHz or higher if implemented in hardware ) • • Disadvantages Short distance Data and clock lines can be shared but each device requires a separate Chip Select signal. SPI is full duplex: Data is simultaneously transmitted and received. many examples Can be high speed ( e. limiting the number of devices in limited I/O systems Example: Multimedia Card ( MMC ) Interface using SPI MMC Interface P3.g.7 CS DIN DOUT P3. The master drives the serial clock. Signals: DATA IN.4 CLK 8051 Microcontroller (AT89C51ED2) Multimedia Card MMC Page 10 . CLOCK. DATA OUT.5 P3. CS ( Chip Select ) Originated by Motorola. A synchronous clock shifts serial data into and out of the microcontrollers in blocks of 8 bits. SPI bus is a relatively simple synchronous serial interface for connecting low speed external devices using minimal number of wires.SPI ( Serial Peripheral Interface ) 4-wire interface with one master and multiple slaves.
One signal wire carries both operating power and signal.com/applications/ds18xx_app.pdf Page 11 . please refer to BiPOM Application Note: Temperature Measurements with 1-Wire Bus Sensors http://www.bipom. Usually the network is built using a wire pair where one wire carries the signal and power and the other wire is ground. and memory chips from a single wire interface ( DATA and Ground ). Theoretically 300 meters but this is limited in practice due to noise and cable capacitance Disadvantages • • Slow speed 1-wire slave devices typically has to come from one source: Dallas Semiconductor For more information on the 1-wire bus. many examples Relatively long distance.1-wire Originated by Dallas Semiconductor ( now part of MAXIM ) to address a variety of peripherals. sensors. Advantages Multiple slave devices can be accessed with only 2 wires Low-cost Implemented in hardware or software Ease to implement. The system is sensitive to the right timing to operate well.
not so much for chip to chip or chip to sensor Low speed for long distance. Single master/single slave Page 12 . 50 feet maximum for low baud rates although longer distances work in practice. 115200 baud can be achieved with small microcontrollers using short distances Requires transceiver chips which add to system cost ( TTL/CMOS level RS232 can be used without transceiver chips ). many examples • • • • Disadvantages More suitable for system to system communications. with low baud rates and error correction Immune to noise due to +/-5 Volts or higher voltage levels for logic “0” and “1” Implemented in hardware or software Ease to implement.RS232 Asynchronous communications Advantages • • • • • • Popular interface with many examples Many compatible legacy devices Relatively long distance.
reflected waves will result in distortions of the original waveform to the point where data errors occur. Otherwise. Correct termination resistor that matches the characteristic impedance of the cable is very important in RS485. not so much for chip to chip or chip to sensor Requires transceiver chips and twisted pair cable with terminating resistors which add to system cost. Page 13 . thousands of feet Immune to noise due to differential voltage Implemented in hardware or software Ease to implement. RS485 Network Topology: Any station can communicate with any other station. but not at the same time. many examples Widely used in industrial automation Higher speeds beyond 115200 baud • • Disadvantages More suitable for system to system communications.RS485 Asynchronous communications Advantages • • • • • • • Popular interface with many examples Very long distance.
more with hubs and switches Immune to noise Widely used in industrial automation due to noise immunity Disadvantages • • • • • Cost More suitable for system to system communications. not so much for chip to chip/sensor Requires Ethernet chipset.Ethernet Advantages • • • • Very high speed ( 10Mbit to 100Mbit/s ) Very long distance. jack and special cabling that add to system cost. Complicated to implement High code footprint Page 14 . transformer. hundreds of feet can be achieved.
(10 bits defined but not implemented) ARP.7V to 5.5V From 1. Differential: <50mV (recessive). half-duplex N/A (circuit board N/A (circuit board level) level) Network Interface Network Voltage open drain.0V. HighSpeed: ~0 to 3. SO. not address based Network Inventory Automatic. slave select N/A.5V max.8V to 5. SDA) N/A Limited by max. device specific VDD-related level: <20% (30%). 64 bits (secondary address) 2 (CAN_H.8V to 5.com ) 1-Wire Network Concept Number of Signal Lines Optional signals Network Size single master.1.75ms (short frame). halfduplex MS bit first plus MS bit first. through check sum Parasitic only Data Protection Collision Detection Slave supply N/A N/A VDD only N/A N/A VDD only .5V. SMBDAT) SMBSUS#.0) Yes (Rev. message-based protocol. CAN_L. Address Resolution Protocol (Rev. single master. (SCL. frame acknowledge Yes: CSMA/CD VDD only. driver specification MS bit first.5mA. >70% of VDD MS bit first plus Acknowledge bit. 400pF bus capacitance requirement 2 SMBUS™ SPI™ MicroWire/PLUS™ single master.Appendix A: Comparison of Serial Digital Data Networks ( from MAXIM website: www. 10nF total load open drain. device specific I C* multiple masters. 2400.5V. >70% (80%) of VDD (inconsistent) MS bit first. 2.maxim-ic. multiple slaves 2. multiple slaves 1 (LIN) N/A Up to 40m. slave addresses hardcoded in firmware Standard: ~0 to 100k bps. frames Yes. half-duplex 7 bits.5V (dominant). frames.3k bps Overdrive: ~0 to 142k bps) Standard: ~ 5.0 V.8V. ~4. terminated) 2nd GND. DI.4ms Overdrive: ~0.5ms (long frame) Even parity. acknowledge response 8 bits (primary address). Shield 40m @1M bps1000m @ 50k bps (example) Differential open drain/source or open coll. resistive open drain. bits. message-based protocol. multiple multiple masters. >60% of VDD (receiver spec.6ms (at maximum speed) 8-bit and 16-bit CRC Yes.8V. SI. multiple slaves 1 (IO) N/A Up to 300 m (with suitable master circuit) open drain. 36V nominalSlave to master: <1./emitter VDD-VD (diode drop). 400pF bus capacitance requirement 4. multiple slaves 4. halfduplex. through nonmatching CRC Parasitic (typical). (10 bits defined but not implemented) N/A. 350m per segment of max. (CS\. slaves multiple slaves 2 (lines can be swapped) N/A Max. SMBALERT# Limited by max. supports dynamic topology change Standard: ~0 to 16. >11mA LS bit first. full-duplex Logic Thresholds Vary with network voltage <0. (CS\. frames Yes ("medium" and "strong" collisions) Parasitic and/or local supply At 1M bps 19µs At 20k bps 1. resistive or active master pull-up From 2.5V. max. resistive master pull-up 8 to 18V VDD-related level: <20%.7ms (standard) or 39µs from start of frame to (extended) from start 1st data bit of frame to 1st data bit 15-bit CRC. >70% of VDD (inconsistent) Push-pull with tristate From 1. check sum. DO.0 only) VDD only N/A N/A Primary address. SK) N/A M-Bus (EN1434) CAN (ISO11898) LIN Bus single master.4M bps 2. multiple slaves multiple slaves 2. 27.)<40%. not address based N/A. local or remote source Check sum. 2. duplex half-duplex 7 bits. 250 slaves.0 only) N/A Address Format 56 bits N/A Message identifier 11 Message identifier 8 bits (standard format). Power. >2. 2400 bps: 13. 2. device specific Fixed level: <0. (SMBCLK. fullAcknowledge bit. >80% of VDD (driver spec. device specific Fixed level: >1.) LS bit first.8 to 6. >3. Fast: ~0 to 400k bps.8 to 5. max. Push-pull with or active master resistive or active tristate pull-up master pull-up From 1.0 V VDD-related level: <30%. SCK) N/A single master. VDD-related level: <20% (30%).5V. halfduplex multiple masters. including 2 parity 29 bits (extended bits format) N/A.1. >2. 180nF M to S: voltage drive S to M: current load ~40V Master to slave: 24V.1V Transmission LS bit first. VDD (exception) N/A. 9600 bps ~0 to 1M bps ~1k to ~20k bps Access Time Standard: ~95µsFast: ~95µs @ 100k ~23µs(at maximum bps speed) N/A Yes (multi-master operation only) VDD only PEC Packet Error Code (Rev. >1. slave select (CS\) (CS\) hard-coded hard-coded in firmware in firmware Automatic Gross Data Rate 10k to 100k bps ~0 to ~10 M bps (device specific) ~0 to ~5 M bps (device specific) 300.