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Introduction to Microwind

Layout and simulation of a CMOS inverter

Lab Contents:
Section-1 Introduction

Section-2 Microwind Editor
2.1 Palette Menu
2.2 Vertical size scaling
2.3 Design Rule Checker
2.4 Simulation Results
2.5 Microwind 3-D viewer

Section-3 Layout of MOSFET
3.1 layout Steps

Section-4 Inverter Layout & Simulation

1. Introduction
In this lab an important VLSI tool Microwind is studied. The main objective of this lab is
to understand the features of this software and practice layout and simulation of simple
devices like MOSFETS and inverter.

Microwind is a windows based VLSI tool designed specially for designing and
simulating microelectronic circuits at layout level. The tool features full editing facilities,
e.g. copy, cut, paste, duplicate, and move operations. This software also provides various
views of the layout such as 2D cross section, 3D process viewer, etc. The software is
capable of providing limited simulation facilities as well as by building layouts of some
basic devices.

In the next section we will discover the important features of software in detail.

2. Microwind Editor

. Stretch and Copy commands no longer affect that layer. pads.This is the main window of the Microwind. • Use "View->Protect all" to protect all layers. The ticks are erased. The list of layers is given in figure 2. Figure 1: Microwind Editor window 2. past. The Cut. use the layout editor to insert contacts. A little tick indicates the current layer. MOS devices. All layers can be edited. You may cut.1 Palette Menu The palette is located on the right side of the screen. • If you remove the tick on the right side of the layer. the layer is switched to protected mode. The selected layer by default is a polysilicon (PO). complex contacts and path in one single click. duplicate. • Use "View->Unprotect all" to remove the protection. generate matrix of layout.

inductance. Figure 2: Palette Menu Window 2. Navigator window is shown in figure: 3 . node name.2 Navigator Menu Select view->Navigator window This menu gives the information about capacitance. device properties and detailed electrical properties. resistance.

Details about the position and type of the errors appear on the screen. the VSS and the desired MOS currents appear in the upper window. In that mode. You can change the selected start node in the node list. • Click on Voltage vs Time to obtain the transient analysis of all visible signals. . The errors are highlighted in the display window. Click on the icon above or on Analysis ->Design Rule Checker to run the DRC. with an appropriate message giving the nature of the error. The delay between the selected start node and selected stop node is computed at VDD/2. the dissipated power within the simulation is also displayed.4 Simulation Results The "Run Simulation" icon or the command Simulate -> Start Simulation both gives access to the automatic extraction and analog simulation of the layout. 2. • Click on Voltage and Currents so as to make all voltage curves appear in the lower window. You can do the same for the selected stop node. Figure 3: Navigator Window 2. and the VDD.3 Design Rule Checker The design rule checker (DRC) scans all the design and verifies that all the minimum design rules are respected. in the right upper menu of the window.

the DC response of the operational amplifier. • Click on Voltage vs. Layout of MOSFET The n-channel MOS is built using polysilicon as the gate material and N+ diffusion to make the source and drain. and the stop node is the first varying node. The second click on “Simulate” computes the same for start node varying from VDD to 0. Initially the start node is the first clock or pulse of the node list. This mode is very useful for monitoring the output signal of oscillators. • Click on Frequency & Voltages so as to make all voltage curves appear in the lower window. . The p-channel MOS is built using polysilicon as the gate material and P+ diffusion to make the source and drain. 3. The first simulation computes the value of the stop node for start node varying from 0 to VDD. Both transistors are shown in figure 5. and to plot the variation of the switching frequency of one selected signal. See the self-aligned diffusion after the polysilicon gate is fabricated. Voltage to obtain transfer characteristics between the X-axis selected node and the Y-axis selected node. 2. Zoom or shift the drawing at any place Figure4: 3D view of a layout. This mode is useful for the computing of the Inverter characteristics (commutation point).5 Microwind 3D viewer In the Microwind 3D viewer is used to see the step-by-step fabrication of any portion of layout. or for the Schmitt trigger to see the hysteresis phenomenon. See how the contacts and metal layers are created.

Draw the 0. Click open. 7. which is shown in figure 11. • Following are the steps used for the NMOS device: 1.5µ X1. Click on the “show palette” window. • Click file menu. To join the N+ diffusion and metal 1 add the “Contacts N+diff/Metal1.1.25µ in the middle of N+ diffusion. This shown in figure 10. It acts as a Gate of NMOS transistor shown in figure 9. 6.rul” file. • Select the Foundry file from File menu. Layout Steps • Open the Microwind Editor window. This is shown in the figure 8. Select “cmos025.5µ size of the N+ Diffusion in the Microwind. From the palette window click on the “N+ diffusion” 3. Draw “polysilicon” having length of 0. Draw it on the N+ diffusion separately in order to make ohmic contacts to the Source and Gate of the NMOS transistor. This is shown in figure7 2. which is shown in figure 6. select ‘new’ and save it with name “nmos. . Select metal1 from palette window. NMOS transistor layout is complete. 4. Polysilicon Gate SiO2 Insulator L D W Source Drain G SB G p+ p+ channel n substrate S substrate connected to VDD p transistor Polysilicon Gate SiO2 Insulator L D D W Source Drain G SB G n+ n+ channel p substrate S S substrate connected n transistor to GND Figure 5: NMOS and PMOS Transistors 3.msk” • Now you can start to make layout in Microwind with desired process. 5.

Figure 6: Foundry file selection in Microwind Figure 7: Palette window in Microwind Editor .• Similarly you can make the layout of the PMOS transistor as well. The only difference is that you use P+ diffusion instead of N+ and the whole transistor is built inside an N-well as shown in the figure 12.

Figure 8: N+diffudion Figure 9: Polysilicon drawn on N+ diffusion .

Figure 10:Metal1 shown on N+ diffusion Figure11: Contacts N+diff/Metal1 added on Metal1 & N+ diffusion .

5µm pMOS L = 0.msk” Begin to draw your layout with Microwind layout editor.25.rul foundry file from file menu.5 time more than nMOS to have matching delays. Figure12: Layout of a pMOS Transistor 4. (You can draw them similarly or there is a shortcut for MOS generator in the palette menu) Keep the dimensions as follows: nMOS L = 0.Layout • The basic transistor circuit of inverter is given in figure 12 Figure 13: Inverter Circuit • Select coms0. . Click “new” and it with name “Inverter.25µm W = 0. You have already drawn NMOS layout and draw PMOS layout.25µm • Width of pMOS should be kep 2. Inverter Layout and Simulation Step I.25µm W = 1.

then no messages will appear.Simulation .05 ns • Push “Assign” • Similarly assign the output node name “Out” • Also assign the Vdd+ and Vss. Please modify your layout until no error messages appear. then the warning messages will appear near the errors.0V High Level 2.to the PMOS and NMOS respectively (Make sure that n-well is also assigned Vdd) • Finally save your layout. Figure 14: Inverter Layout Step II . A clock window appears & make sure the properties on the windows is below: Low-level 0.05 Time high 1.95 Rise time 0. • Your layout should look like figure 14: Save your layout. If there are some errors. • Run DRC by selecting: >Analysis>Design Rule Checker • If your layout is correct.95 Fall time 0.5V Time low 1. Step III.Add properties to input signals for simulation • Click on the clock icon and then click on the input of the inverter in the layout then double click the clock of layout.

• The output waveform is shown in the given figure: 15 Figure 15: Inverter Output .• Click on “Run simulation” • You will see the desired output of the inverter.