A COMPREHENSIVE TUTORIAL
± System design approach with HDLs ± History of VHDL ± Why VHDL ?
± Simulation Cycle ± Digital Simulator
Modeling of Hardware Language Basics
± Building Blocks in VHDL ± Design Units and Libraries
Objects and Data Types Structural Description
± Basic Features ± Configuration Specification ± Configuration Declaration
± Process Statement ± Behavioral Modeling - Sequential View ± Behavioral Modeling - Concurrent View
» » »
Eliminates hardware prototyping expenses Reduces design time Increases design reliability at lower costs/time req.Introduction
Approach with HDLs
± HDL is mostly related to the front end part of the
design flow where a system is described with programming language constructs. ± A complex system can be easily decomposed into smaller pieces : improves modularity ± Allows a design to be simulated and synthesized before being manufactured.
Algorithm HDL Description (Behavioral) Register Transfer Level simulation and verification Level of abstraction
Synthesizer Structural Description Technology mapping (with ready-made primitives) + Floor Planning Physical Layout
± Public Availability
Developed initiated under Government Contract Now is an IEEE standard
± Design Methodology and Design Technology
Support ± Technology and Process Independent ± Wide Range of Descriptive capabilities
Digital System (e.Introduction(contd. box) level to gate level Capability of mixing descriptions
± Design Exchange ± Large Scale Design and Design re-use
In digital simulation only logic level of the measured quantity is determined.
capabilities. In analog simulation the precise values of the measured quantities are determined
Purpose of simulation is to verify the behavior of a system by applying stimulation at the inputs and monitoring the response of the system over a period of time. no precise value is required. A simulator with both digital and analog simulation Purely digital simulator. There are three types of simulators :
± ± ±
Purely analog simulator.
The interval is chosen as the smallest unit of time after which a node can change its state.Simulation Fundamentals(contd. Evaluates circuit behavior at intervals of time. Maintains a time wheel to model propagation of time.
The system is described with a Hardware Description Language (HDL). Maintains node values at logic level. The design contains a number of concurrently operating blocks connected with each other by signals.
± Multiple levels of abstraction for modeling
Behavioral Structural Dataflow
± Behavioral model.
. ± A VHDL process models a block and a VHDL signal models the connection between different blocks.Modeling Hardware
The VHDL Language ± A language for describing digital and analog systems. ± Makes no assumptions about the technology. timing model and structural
model are integrated.
Digital circuits consist of components and interconnection between them A component can in turn be composed of subcomponents and their interconnections A component interacts with other components through pins Component is modeled as entity Component pins are modeled as ports Interconnections between components are modeled as signals
Behavioral Model ehavioral
The behavior of a component is modeled inside an architecture body of the entity It may be described using a collection of concurrently executing statements A concurrent statement is sensitive to a set of input signals and is executed whenever any of its sensitive signal changes its value A concurrent statement called process statement can contain one or more sequential statements A set of sequential statements can be clubbed together in a subprogram
The flow of data through the entity is modelled primarily using concurrent signal assignment statements. The structure of the entity is not explicitly specified but it can be implicitly deduced.
. Architecture MYARCH of MYENT is begin SUM <= A xor B after 8ns end MYARCH.
end behavioral. architecture behavioral of Xor_gate is begin process begin Out1 <= In1 xor In2. end Xor_gate . in2 : in bit. Out1 : out bit).
. in2. end process.A simple Example
entity Xor_gate is port (in1. wait on In1.
Primary design unit
± entity decl.VHDL Libraries Design Units
A VHDL library is a host dependent storage facility for intermediate-form representations of analyzed design units A design unit is a VHDL construction that can be independently analyzed and stored in a design library. A design unit may be a primary or a secondary one. package decl and configuration decl
Secondary design unit ± architecture body and package body In a library. there can be only one primary unit of same name but there can be multiple secondary units by same name A secondary unit can have name same as primary unit
± parameter .list
± declarations statements
± declarations. declarations. port. subprogram body
± declarations.Building Blocks in VHDL
provides a name to the component contains the port definitions in the interface list can contain some generic definitions which can be used to override default values
entity identifier is generic interface_list. declarations begin statements end [entity] [identifier]. port interface_list.
B : in Bit. Sum : out Bit. Cout : out Bit ). end Adder.
A B Sum Cout
entity Adder is port ( A : in Bit.
encapsulates the behavior and timing information contains a number of concurrent statements there can be multiple architecture bodies for a given entity
architecture identifier of entity_name is declarations begin statements end [architecture] [identifier].
. Cout <= A and B after 6 ns. B) Sum <= A or B after 5 ns.ExampleExample-1
architecture Behavioral_Desc of Adder is begin process (A. end process.
Out : out Bit). Out => SUM). B1 : And_Comp port_map ( X => A.
end Struct_Desc. Y : in Bit.ExampleExample-2
architecture Struct_Desc of Adder is
-.component instantiations A1 : Or_Comp port_map ( X => A. Out => Cout). end component. y =>B. Out : out Bit). Y : in Bit. component And_Comp port ( X : in Bit.declarations component Or_Comp port ( X : in Bit. end component. y =>B.
Subprograms are of two types : functions and procedures A subprogram consists of a sequence of declarations and statements which can be repeated from different locations in VHDL descriptions subprograms can be overloaded functions can be used for operator overloading procedures can assign values to its parameter objects while functions can not A subprogram can be separated into its subprogram declaration and subprogram body
Two forms of subprogram .specification » procedure identifier interface_list » [pure | impure] function identifier interface_list return type_mark Full form of subprogram body is subprogram-specification is declarations begin statements end identifier.
Full form of subprogram declaration is
Examples of function declaration ± Object class of parameter is implicit function Mod_256 (X : Integer) return Byte. the parameter is interpreted as having mode in.Functions
Intended to be used strictly for computing values and not for changing value of any objects associated with the function¶s formal parameters All parameters must be of mode in and class signal or constant or File.
. If no class is specified parameters are interpreted as being of class constant. Parameter of type FILE has no mode. If no mode is specified. ± Object class of parameter is explicit function Mod_256(constant X : in Integer) return Byte.
-.Function Specification function Min (X. end if. Y : Integer) return Integer.
. end Min.Example
function Min (X. else return Y. Y : Integer) return Integer is begin if (X < Y) then return X.
Parameter of type FILE has no mode. If no class is specified parameters of mode in are interpreted as being of class constant and parameters of mode out or inout are interpreted as being of class variable. ± Object class of parameter is explicit procedure Mod_256(variable X : inout Integer). out or inout If no mode is specified the parameter is interpreted as having mode in. Examples of procedure declaration ± Object class of parameter is implicit procedure Mod_256 (X : inout Integer).
Procedures are allowed to change the values of the objects associated with its formal parameters Parameters of procedures may of mode in.
Procedure Specification Procedure ModTwo (X : inout Integer) is begin case X is When 0 | 1 => null.Example
Procedure declaration --. -. When others X := X mod 2. end ModTwo.
.X is of class variable
Procedure ModTwo (X : inout Integer). end case.
component declarations etc. Example : package logic is type Three_level_logic is (µ0¶.
package identifier is declarations end [package] [identifier]. constants. µ1¶.Packages
Allows data types. object declarations (signal. µz¶). end logic. shared variables and files). function invert (Input : Three_level_logic) return Three_level_logic. subprograms. to be shared by multiple design units.
Package declarations and bodies are separately described Package declarations contain public and visible declarations Items declared inside package body is not visible outside the package body Package body has the same name as the corresponding package declaration
package body identifier is declarations end [package body] [identifier].
when µ1¶ => return µ0¶.)
Example of a package body for package logic
package body logic is -.Package Body (contd. end invert. when µZ¶ => return µZ¶. end logic.subprogram body of function invert function invert (Input: Three_level_logic) return Three_level_logic is begin case Input is when µ0¶ => return µ1¶.
then no explicit use clause is necessary for the architecture
Simple examples : Makes all items of package std_logic_1164 in library ieee visible » use ieee. Makes Three_level_logic in package Logic in library work visible » use work.Logic.USE CLAUSE
Use clause preceding an unit makes all the elements of a package or a particular element of a package visible to the unit An architecture body inherits the use clauses of its entity.Three_level_logic.
. So if those use clauses are sufficient for the descriptions inside the architecture.std_logic_1164.all.
Logic. use my_lib.)
library my_lib. entity Inverter is port (X : in Three_level_logic.Use Clause (contd. use my_lib.Three_level_logic. end inverter.Invert. Y : out Three_level_logic).Logic.
configuration referenced in a configuration declaration must be analyzed before the configuration declaration is analyzed
A library clause makes library visible and an use clause makes the units inside the library visible to other units library Basic_Library. Use Logic.Logic.
. architecture.Analysis Rules for Units
Units can be separately analyzed provided following rules are obeyed ± a secondary unit can be analyzed only after its primary unit is analyzed ± a library unit that references another primrary unit can be analyzed only after the referred unit has been analyzed ± an entity.all. Use Basic_Library.
every object has a type. Three basic VHDL data types are ± integer types ± floating point types ± enumerated types Data types can be user defined
. i.g signal) In VHDL.Objects and Data Types
Something that can hold a value is an object (e.e the types are determined prior to simulation. the type determining the kind of value the object can hold VHDL is strongly typed language The type of every object and expression can be determined statically.
Data type Scalar Type Integer Float Physical Enumeration
Integer and enumeration types are called discrete types Integer. Real and Physical types are called numeric types
Composite Type Access Type Record Array
µz¶).1 to 200.)
» Most atomic » Can be ordered along a single scale
type Byte is range -128 to 127. µ1¶.
consists of enumeration literal
± a literal is either an identifier or a character literal
type Three_Level_Logic is (µ0¶.
type fraction_type is range 100. GREEN.
. BLUE). type Bit_pos is range 7 downto 0.1. type Color_set is (RED.Data Types(contd.
--.secondary unit ns = 1000 ps.) Physical Type
Values of physical type represent measurement of
some physical quantity such as time.primary unit ps = 1000 fs.Data Types : Scalar Type (contd.secondary unit end units.
Any value of a physical type is an integral multiple of
the primary unit of measurement for the type Example type Time is range -(2**31 -1) to (2**31 -1) units fs . distance etc. --. --.
These are symbols whose value is immediately evident from the symbol Six Literal Types ± integer.6#e+4 43. ± bit_string and physical literal. Examples ± 2 19878 16#D2# 8#720# 2#1000100 ± 1. characters. floating. strings.6E-4 ± ³ABC()%´ ± B´1100´ X´Ff´ O´70´ ± 15 ft 10 ohm 2.9 65971.3333 8#43.3 sec
Composite type are used to define collection of
Can be decomposed into smaller atomic types Composite Types are of two types
Records - heterogeneous composite Record Type definition specifies one or more elements,
each element having a different name and possibly a different type.
type OpCode is (add, sub, compl); type address is range 16#0000# to 16#FFFF#; type instruction is record
Opc_field : OpCode; Op1 : Address; Op2 : Address;
Arrays - homogenous composite type
± type Word is array (15 downto 1) of Bit;
Can have multiple dimensions
± type Arr2Dim is array
(integer range1 to 3, integer range 5 to 7) of integer;
Each dimension must be of discrete type
± integer or enumerated
Can be constrained or unconstrained
array has bounds specified
± unconstrained array has no bounds
± range is a subtype indication
type Column is range 1 to 80. type Matrix is array (Row.Constrained Arrays
The type and range are both specified by discrete range Two Forms ± simple range specification
type Word is array (15 downto 1) of Bit.
. Column range 1 to 40 ) of Boolean. type Matrix is array (Row range 1 to 10. type Severity_level_stats is array(Note to Failure) of Integer. Column) of Boolean. type Row is range 1 to 24.
Integer range <>) of Pixel. Two predefined unconstrained array ± type Bit_vector is array (Natural range <>) of Bit. Useful in defining interface list having variable number of bits in ports
The type of each dimension is given but range bounds and direction is not specified ± type Screen is array (Integer range <>. ± type String is array (Positive range <>) of Character.
.positional ± (Numerator => 155.Aggregates
Values of composites can be given in aggregate notation An aggregate is a parenthesized list of element associations.named ± ( Low | Falling => µ0¶) -. each element specifies values of an element of the array or the record Value association may be named or positional Examples ± (155. 203) (µ1¶. Denominator=>200) -. µ0¶) -.
access variable.access type declaration variable MOD_PTR : PTR.Access Type
Values belonging to an access type are pointers to a dynamically allocated object of some other type. Example :
type module is record size : integer. --. They are similar to pointers in Pascal or C language. default null
. delay : time. The objets of an access type can only belong to variable class. type PTR is access module. end record. --. the default value of that objet is null. When an objet of access type is declared.
> > >
Objects of FILE types represent files in the host environment Provides a mechanism by which a VHDL design may communicate with host environment A file can be opened. file F1 : intFileType. or tested for an end-of-file condition by using special procedures and functions that are implicitly declared for every FILE type Example : type intFileType is file of integer.txt´. read. written to. file F2 : intFileType is ³myFile. closed.
.. Failure).. ± type Severity_Level is (Note. ± type String is array (Positive range <>) of Character. DEL). SOH. Warning.1) to (2**31 .7FFF_FF8#E+32 to 6#0. Error. ± type Character is (NUL.7FFF_FF8#E+32 ± type Boolean is (False. µa¶. . .... Each implementation can define range of pre-defined types
differently Scalar Types : ± type Integer is -(2**31 . Composite Types : ± type Bit_vector is array (Natural range <>) of Bit.. True).. ± type Bit is (µ0¶. µb¶.. µ1¶)..1) ± type Real is -16#0.
Referencing Elements of Composite
Can be referenced in entirety or by element An indexed name is used to refer to an element The type of an indexed name is the type array element A slice name is a reference to a contiguous subset of elements in an one-dimensional array Examples ± type Byte is array (7 downto 0) of Bit. º S_byte (3 downto 1) --. ± signal S_byte : Byte. ± type S_memory is array (0 to 2**16 -1) of Byte.slice of three elements º S_mem (2**15 -1 to 2**16 -1) --.slice of 2**15 elements º S_mem (0) (0 downto 0) --. ± signal S_mem : S_memory.slice of one element
± to specify an index constraint of a array
dimension of unconstrained type
subtype Register is Bit_Vector (7 downto 0).Subtypes
A subtype is a type with a constraint A value belongs to a subtype of a given type if it belongs to the type and satisfies the constraint The given type is called the base type of the subtype Subtypes of a type are fully compatible with each other Two ways to constraint a type by a subtype ± a range constraint that defines a subset of values of a scalar type
subtype LowerCase is Character range µa¶ to µz¶.
Attribute is a named characteristic It may belong to the following classes of items in VHDL
± ± ± ± ± ± ±
type. the same may referenced as
± name ¶attribute_identifier
Attributes may be pre-defined or user-defined
. functions signals. variable and constants entities. configurations and packages components statement labels literal. subtypes procedure. and if it does have a value. file
A particular attribute for a particular item may have a value. architectures. group.
µlow ± Example
type Bit_position is range 15 downto 0.)
Pre-defined attributes for scalar subtypes ± µleft. µright. µhigh.Attributes (contd. Bit_position¶left = 15 Bit_position¶low = 0 Bit_position¶right = 0 Bit_position¶high = 15
µhigh. µrange. µrightof ± Example
Bit_position¶pos(15) = 15 Bit_position¶val(15) = 15
Attributes (contd. µlength. µreverse_range
Pre-defined attributes for any physical subtype or any discrete subtype ± µpos. µleftof. with ascending range
T¶rightof(x) = T¶succ(x) T¶leftof(x) = T¶pred(x)
Pre-defined attributes for constrained array subtypes and array objects ± µleft.)
± For any physical or discrete type T
T¶succ(x) = T¶val(T¶pos(x) + 1) T¶pred(x) = T¶val(T¶pos(x) . µlow.1)
± For a physical or discrete type T. µval. µsucc. µright.
type int_type is range 1 to 100. attribute INDEX of Cout : signal is 5.
± Attribute Specification :
.Attributes (contd. associates a user-defined attribute with one or more named entities and defines a value of that attribute of that attribute for that named entity signal Cin.)
User Defined Attribute :
± Attribute declaration
syntax: attribute identifier : type_mark. attribute INDEX : int_type. type_mark. Cout : int_type. attribute CAPACITANCE of all : signal is 10 pF.
assigns value 3 to signal s1 end
. architecture att_example of att_example is subtype int_subtype is integer range 1 to 100. s3 begin --.accessing the attribute value s1 <= s3¶SIG_NUM. --. s3 : int_subtype.attribute declaration attribute SIG_NUM : int_subtype.for s2. s2.Attributes (contd. --.)
entity att_example is end.attribute specification attribute SIG_NUM of s1 : signal is 1. --. --. signal s1. --.for s1 only attribute SIG_NUM of others : signal is 3.
. Variables have no hardware equivalent. Every object must be of a type and has to be defined in its declaration. Signals are like wires. ± constant ROM_size : integer := 16#FFFF#. Constants are assigned only once. constants and files
Signals and variables can be assigned values in succession. ± file F1 : integer_file is ³test. ± signal enable : Bit := µ0¶.Objects Four types of objects
± signals. ± type integer_file is file of integer. A file declaration declares a file of specified type.txt´. ± variable fetch : Boolean := TRUE. variables. ± variable address : integer range 0 to ROM_size := 10.
Object class must be constant.constants º Ports (entity. variable or file.Objects (contd.
º Indexes of Loop and Generate statements
. components. ³out´ or ³inout´. Procedure Parameters . signal or file. . signal.Mode should be ³in´.Object class may be constant.
Following are Implicitly defined Objects
º Generics .signals º Subprograms
Function Parameters . blocks) .Mode should be ³in´.Within the sequence of statements these are considered as constants and hence can¶t be modified.
local component declaration. out. Four VHDL constructs that specify this ± entity declaration. variable or file ± Mode : in. buffer(for ports only) or linkage(for ports only) ± Data type
. The object in a single interface element have three properties in common ± Object Class : signal. constant. block statement and subprogram specification Each interface element declares one or more interface objects.Specifies interfaces or potential points of communication between units. inout.
Actual communication path between separate units.
. Four VHDL constructs that specify this ± Component instantiation statement ± binding indication ± block statement ± subprogram call Association may be named or positional.
It can be done by
Instantiation of a declared Component A component is instantiated. The component needs to be bound to some actual entity(architecture) with a configuration.Structural Description
± Component Instantiation Statement It is concurrent statement. Direct instantiation statement (VHDL 93 feature) No component needs to declared. No separate binding is required.
Block Statement Generate Statement Configuration Specification Configuration Declaration
. An entity(architecture) can be directly instantiated.
(: VHDL 93 feature)
. correspondence between a given portion of description and a portion of hardware is easier to see in structural descriptions Component Instantiation statement is basic unit of structural Description. Component instantiation can be done by
» Instantiating a declared component and providing binding
information to bind it with actual entity(architecture) » Directly instantiating an entity(architecture).Basic Features
Structural description of a piece of hardware is a description of what its sub-components are and how the sub-components are connected Structural description is more concrete than behavioral description.e. No separate component declaration and binding information is needed. i.
types and directions of ports) is visible The statement identifies the child component and specifies the connectivity of the local signals or ports of parent component with the ports of child component General Form of the statement label: instantiated_unit generic map association-list port map association-list. instantiated_unit ::= [component] component_name | entity entity_name [(architecture_identifier)] | configuration configuration_name
Component Instantiation statement specifies an instance of a component (child component) occurring inside another component (parent component) At the point of instantiation. only the external view of the child component (the names.
the port association list associates an actual with a local The associated actual must be » an object of class signal » open » static expression if port mode is ³in´
Generic/Port map associations are omitted if the corresponding component declaration lacks generics/ports The component_name must reference a component declared by a component declaration.g through a visible package) A port of Component Declaration is called a local In a component instantiation statement. (e. The component declaration need not occur in the architecture body containing the instantiation but it must be visible at the point of instantiation.
Component Declaration port ( I1. signal S1. O1 : out Bit). I2 : Bit. end component. I2=>S2.Example
architecture Parent_body of Parent is component And2 -. begin Child : And2 port map ( I1=>S1. S3 : Bit. S2.
. O1=>S3). -Instance end Parent_body.
Entity Vs Component
Entity is a library unit which can be compiled separately and it never occurs inside another library unit Entity declaration declares something that really ³exists´ in the design library
Component Decl only occurs inside a library unit. It may occur inside a Package Decl or an architecture body Component declaration merely declares a template that does not exist in the design library
which is not a resolved signal. on the association of an actual with local ± VHDL requires that the type of actual be the same as the type of the local ± VHDL requires that if the local is readable. and if the local is writable.Port Association
VHDL imposes three kinds of restrictions based on type mode and resolvability. then the actual must also be readable. It follows that an actual. may not be associated with more than one locals of mode out or inout
. then the actual must also be writable ± Association with a local of mode out or inout creates a source for the actual.
O1 : out Bit). end generate. end component.Example
entity Invert_8 is port ( Inputs : in Bit_vector (1 to 8). architecture Invert_8 of Invert_8 is component Inverter port ( I1 : Bit. Outputs : out Bit_vector (1 to 8)). Outputs(I)). end Invert_8.
. begin G: for I in 1 to 8 generate inv : Inverter port map (Inputs(I). end Invert_8.
Allowed inside ± Entity Declarations ± Component Declarations ± Blocks
. and the size of array objects (in particular the size of ports) Generics are declared as interface elements. the number of instantiated sub-components.Generics
Generics provide a channel for static information to be communicated to a design-block from its environment. ± The only object type permitted is constant. the range of subtypes. Typical use of generics are to parameterize timing. ± The only mode permitted is in.
eO => cO). eO : out bit_vector(1 to eg)). s3 : bit_vector(1 to 3). end component.and_gate(and_gate_arch) generic map (eg => cg) port map (eI1 => cI1. architecture and_gate_arch of and_gate is begin --. architecture top of top is signal s1. eI2 => cI2. for all : gate use entity work. component gate generic (cg : integer). entity top is end.
. cO => s3).implementation not shown end. port (cI1. cI2 => s2. cI2 : in bit_vector(1 to cg). eI2 : in bit_vector(1 to eg). end. end. s2. cO : out bit_vector(1 to cg)).entity and_gate is Example generic (eg : integer). port (eI1. begin AND1 : gate generic map (cg => 3) port map (cI1 => s1.
block declarative part.
. constant. subprogram.
Blockinternal block representing a portion of a Statement A block statement defines an
design. subtype. These items are local to block scope. block statement part Block Header Block header explicitly identifies certain values. signals which are to be imported from the enclosing environment into the block and associated with formal generics and ports Block Declarative Part Type. signal «etc can be declared in the block declarative part. Blocks may be hierarchically nested to support design decomposition A block may have three parts » block header. Block Statement Part Block statement part consists a set of concurrent statements.
end block.block header part generic (bg : time). constant con_a : time := 1 ns. begin --. architecture arc of ent is signal sig_a : integer.block statement part sig_b <= sig_a after bg. port map (bp1 => sig_a). generic map (bg => con_a). begin B : block --. end
. port (bp1 : in integer).Example
entity ent is end.block declarative part signal sig_b : integer. --.
A generate statement provides a mechanism for iterative or conditional elaboration of a portion of description Consists of a generation-scheme and a set of enclosed concurrent statements Following VHDL concurrent statements may be enclosed by the generate statement ± Process statement ± Block Statement ± Concurrent assertion statement ± concurrent signal assignment ± concurrent procedure call ± concurrent instantiation statement ± another generate statement
Generate Statements (contd.)
General Form is label-identifier : generation-scheme generate concurrent-statements end generate identifier; There are two kinds of generation scheme ± if-scheme ± for-scheme
entity Invert_8 is port ( Inputs : in Bit_vector (1 to 8); Outputs : out Bit_vector (1 to 8)); end Invert_8; architecture Invert_8 of Invert_8 is component Inverter port ( I1 : Bit; O1 : out Bit); end component; begin G: for I in 1 to 8 generate inv : Inverter port map (Inputs(I), Outputs(I)); end generate; end Invert_8;
Identifies which instances are configured Consists of an instantiation label (or a label list) followed by colon and the component name Specifies mapping between the component and the entity It may also contain a generic/port association list
This construct allows the designer to specify the selection of entity declaration and architecture body for each component instance. General Form is for component_specification use binding_indication .
And_gate1(And_gate1). U2 : Inverter use entity work. ± for all : And_gate use entity work. Use of others means that the configuration specification applies to all the instantiations of the given component except for those instances which are already configured by the preceding configuration specifications
. ± for others : Inverter use entity work.Inv2(Inv2_body). Instantiation label allows two key words all and others Use of all means that the configuration specification applies to all the instantiations of the given component.Inv1(Inv1_body).Configuration Specification
Example ± for U1.
The binding of a component instance to design entities can be performed by configuration specification which appears in the declarative part of the design-block in which the the corresponding component instance resides.
. This has following two benefits ± Provides support for top-down design methodology ± Allows a designer to take advantage of a library of reusable components.Configuration Declaration
Configures sub-component hierarchy. leaving the component in the design-block unbound. the user can defer the binding of the component instance until later. Configuration declaration provides the mechanism for specifying such deferred binding. Otherwise.
--. --. for intel --.component configuration for instantiations in intel end for.
Consider the configuration declaration for an entity COMM_BOARD that fits into a full PC slot
configuration FULL_SLOT of COMM_BOARD is for ARCH_COMM_BOARD for CPU : PROCESSOR use entity std_parts.SPARC(intel) generic map (Clock => 40 ns).for PROCESSOR « --.for architecture ARCH_COMM_BOARD end FULL_SLOT.
.configuration of other different units end for.for intel end for. --.
Sequential View ± Signal Assignment ± Delay in Signal Assignments ± Variable Assignment ± Sequential Statements
Conditional Control Iterative Control Assertion Statement
Sequential vs Concurrent Process Statement ± Wait Statement Behavioral Modeling .
Concurrent View ± Concurrent Signal Assignment ± Conditional Signal Assignment ± Selected Signal Assignment Resolved Signals
Behavioral Modeling .Behavioral Description (contd.
Sequential vs Concurrent
In VHDL there are two levels at which designer must define the behavior of a discrete system. with no defined relative order. ± A concurrent statement executes asynchronously. Process statements are executed concurrently but the statements inside a process statement are executed sequentially. Concurrent statements are used for data-flow and structural descriptions ± The process statement is a concurrent statement which delineates set of sequential statements.
. Used for algorithmic descriptions.
± The sequential level involves programming the
behavior of each process that will be used in the model. Sequential statements are executed in the order in which they appear. sequential and concurrent level.
The process statement is a concurrent statement that defines a specific behavior to be executed when the process becomes active. General Form is : process_label: process declarations begin statements end process. The behavior of the process is described with a set of sequential statements.
The process remains suspended until its reactivation condition is met
A process is either active or suspended A process becomes active when any of the signal read by the process changes its value All active processes are executed concurrently A process may be suspended upon execution of a wait statement in the process.Process Statement (Contd.
± signal sensitivity wait on signal-list. it is possible to designate sensitivity signals using a sensitivity list.Wait Statement
Three kind of reactivation condition can be specified in a wait statement ± timeout wait for time-expression. e. Conditions can be mixed.g wait on A. If a process is always sensitive to one set of signals. B until Enable = 1. It is illegal to use wait statement in a process with a sensitivity list Every process is executed once upon initialization
. ± condition wait until condition.
this is equivalent to Or_process : process begin Output <= In1 or In2. end process. --. In2) begin Output <= In1 or In2.
The following process implements a simple OR gate---. end process. In2. wait on In1.this process is sensitive to signals In1 and In2 Or_process : process (In1.
This assignment occurs in a process or subprogram It is sequentially executed There are two fundamental types of assignment ± Signal Assignment ± Variable assignment
This assigns value to the current value of the signal at the beginning of the next cycle
A signal is comprised of a current value and a projected waveform The current value always holds the value of the signals as read by other process The projected waveform contains scheduled values on this signal at future times. Simplest form
signal_name <= value.
Delay in signal assignment ± It is possible to assign values with a delay ± Delay is relative to current time ± If no explicit delay is specified a delta delay is assumed ± General Form :
signal_value <= value after time-expression
.Signal Assignment (contd.
Consider this Example signal A : Bit := 0. assert ( B = A) report ³ B is not equal to A´ severity error. P1 : process begin B <= A. signal B : Bit := 1. end process. wait on B. Will the message be printed ?
A driver is a collection of value time pairs referred to as transactions Every concurrent statement which assigns to a signal creates a driver for that signal Only one driver is allowed for a signal unless it is a resolved signal Initial value of the driver is taken from the default value of the declaration which is visible to the source process. If source process is in another component it is taken from the port .
Delay in Signal Assignment
There are two types of delay that can be applied when assigning a time/value pair into the driver of a signal ± Inertial Delay ± Transport Delay
Example : Z <= reject 4 ns inertial A after 10ns
. The value appears at the output after the specified inertialdelay. If the input is not stable for specified rejection limit (pulse rejection limit). no output change occurs. Inertial signal assignment has the form : signal_object <= [ [ reject pulse-rejection-limit ] inertial ] expression after inertial-delayvalue.Inertial Delay
Inertial delay models the delays often found in switching circuits. An input value must remain stable for a specified time (pulse rejection limit) before the value is allowed to propagate to the output.
any change in the input (no matter how small) is transported to the output after the specified delay time period To use a transport delay model. ie. where spikes would be propagated through instead of being ignored
This delay models pure propagation delay. the keyword transport must be used in a signal assignment statement Ideal delay modeling can be obtained by using this delay model.
A variable is declared in a process or a subprogram When a variable is declared with a process it retains its value throughout the simulation.e it is never re-initialized Variables declared in subprograms are reinitialized whenever the subprogram is called General Form of variable assignment is ± variable_name := expression. i. The variable assignment updates the value immediately after the assignment without any delay
e statements are executed when a given condition is true VHDL provides two types of conditional control statements ± if then elsif ± case end case
These sequential statements provide conditional control i.
General form is if condition then statement elsif condition then statement else statement end if.
In2. end process. wait on In1.
And_process : process begin if In1 = µ0¶ or In2 = µ0¶ then Out <= µ0¶ after Delay. end if. else Out <= µ1¶ after Delay. elsif In1 = µX¶ or In2 = µX¶ then Out <= µX¶ after Delay.
General Form is case expression is when value => statements when value | value => statements when discrete_range => statements when others => statements end case
end case. end process
Select_process : process begin case X is when 1 => Out <= µ0¶. when others => out <= µX¶. when 2 | 3 => Out <= µ1¶.
In this control the execution iterates over the statements until some condition is met VHDL provides iterative control inform three kinds of loop statements ± Simple loop ± for loop ± while loop
Simple loop encloses a set of statements in a structure which is set to loop forever General Form is loop_label : loop statements end loop loop_label.
end loop Loop1. B := 20.Example
P1 : process variable A : Integer :=0. wait. end process.A. begin Loop1 :loop A := A + 1. variable B : Integer.
. Loop2 :loop B := B . end loop Loop2.
General Form of while loop: loop_label: while condition loop statements end loop loop_label. While Loop
General Form of for loop: loop_label: for loop_variable in range loop statements end loop loop_label.For Loop.
.A. wait. Loop2: while B >= (A * A) loop B := B . end process. end loop Loop1. begin Loop1: for A in 1 to 10 loop B := 20.Example P1 : process variable B : Integer := 1. end loop Loop2.
end loop Loop1. B := 20. B : Integer :=0. begin Loop1 :loop A := A + 1. exit Loop1 when A = 20.Exitsequential statement closely associated Statement Exit statement is a
with loops and causes the loop to be exited Exit statement has two general forms : ± exit loop_label.
P1 : process variable A.
. ± exit loop_label when condition. end process.
and then loop execution resumes with else new value of j. Loop identifier j increments var1 := var1 + 1. end if. is not elsif var1 < var2 executed. next. i. null.Next Statement
Next statement is used to advance control to the next iteration of the loop General Form is : next loop_label when condition. k := k + 1.e last statement k := k + 1. if var1 = var2 then execution jumps to the end of the loop. end loop.
. Example : for j in 1 to 10 loop When next statement is executed.
± When the condition is FALSE the message is sent to system output with an indication of the severity of the message ± The severity levels are Note.
. Error and Failure ± If no message is given the default message is ³Assertion Violation´. The default level is Error Example assert (A = B) report ³A is not equal to B´ severity Error. Warning.Assertion Statement
The assertion statement has the syntax assert condition report message severity level.
Concurrent Signal Assignment
A concurrent signal assignment statement
represents an equivalent process that assigns values to signals Simple example of concurrent signal assignment is
target_sig <= source_sig after delay_period.
It is one of the primary mechanisms for modeling
the data-flow behavior of an entity There are two forms of concurrent signal assignment :
1) conditional signal assignment 2) selected signal assignment
in2) begin Out1 <= In1 . end arch_sub.Example
architecture arch_sub of sub is begin process (in1.In2 after Delay. end process.
. waveformN-1 when conditionN-1 else waveformN.Conditional Signal Assignment
This is a special form of concurrent signal assignment. The behavior is similar to that of an if statement in a process statement
. General Form is: target <= options waveform1 when condition1 else . Signal Assignment is done when condition is true.
architecture Conditional of AND_gate is begin Y <= transport µ1¶ after Delay when A=µ1¶ and B=µ1¶ else µ0¶ after Delay.
. architecture ConditionalEq of AND_gate is begin process(A. end Conditional. end ConditionalEq. else Y <= transport µ0¶ after Delay.B) begin if A=µ1¶ and B=µ1¶ then Y <= transport µ1¶ after Delay. end process.
. .Selected Signal Assignment
Selected Signal Assignment behaves very much like the case statement in a process statement General Form is: with expression select target <= options waveform1 when choices1. waveformN when choicesN.
A Package with a procedure modeling the functionality of an OR gate package gate is procedure Or_gate(signal In1.Complete Example
Example 1 -. end gate. In2 : bit. end Or_gate. signal Out1 : out bit) is begin Out1 <= In1 or In2. package body gate is procedure Or_gate(signal In1. end gate. signal Out1 : out bit). In2 : bit.
end Half_adder.Behavioral Description of a Half Adder entity Half_adder is generic ( AB_to_sum : TIME := 0 ns.
. port ( A : in bit. Carry : out bit ). B : in bit. AB_to_carry : TIME := 0 ns ).Half Adder
Example 2 -. Sum : out bit.
architecture Behavioral of Half_adder is begin process begin Sum <= A xor B after AB_to_sum.
. end process. Carry <= A and B after AB_to_carry. wait on A. end Behavioral.B.Half Adder (contd.
Example 2 -.all. B : in bit.
use WORK. Carry_in : in bit. -.gate.use the Package gate entity Full_adder is port ( A : in bit. Sum : out bit. end Full_adder.
.Structural Description of a Full Adder that instantiates Half Adder and Uses procedure Or_gate from the package gate. Carry_out : out bit ).
Half_adder(behavioral).Full Adder (contd. AB_to_carry : TIME := 0 ns ).
. Carry : out bit ).)
architecture structural of Full_adder is component Half_adder generic ( AB_to_sum : TIME := 0 ns. end component. for all : Half_adder use entity work. Sum : out bit. B : in bit. port ( A : in bit.
5 ns) port map (A. Carry_out). Sum => Sum. B. U1 : Half_adder generic map (5 ns.
. Temp_carry1). 5 ns) port map (A => Temp_sum. B => Carry_in. Carry => Temp_carry2). Temp_sum.Full Adder (contd.)
signal Temp_sum : bit. signal Temp_carry1 : bit. Temp_carry2. U3 : Or_gate ( Temp_carry1. end structural. begin U0 : Half_adder generic map (5 ns. signal Temp_carry2 : bit.
. entity fa_test is -. for all : Half_adder use entity work. use STD.textio. end component. B : in bit. use STD. use testpackage. Sum : out bit. architecture bench of fa_test is component Full_adder -.standard.Test Bench
library STD. library testpackage.Component declaration for Full Adder port ( A : in bit.all.all.testpackage.Entity for the test bench end fa_test.all. Carry_out : out bit ). Carry_in : in bit.
variable rando : integer. begin rando := 1. Sum. file dataout : text is out "data.)
signal A. signal Sum. Carry_in : bit. B.Test Bench (contd. signal temp : bit_vector(0 to 31).
. B.out". A <= temp(31). a2: process variable sttr : line. Carry_in. Carry_out : bit. Carry_in <= temp(29). Carry_out). begin a1: Full_adder port map ( A. B <= temp(30).
. write(sttr. string('(" B = ")). rando := (rando * 3)/2 +1. write(sttr. wait for 0 ns. write(sttr. string('(" Carry_in = ")). A).Test Bench (contd. write(sttr. write(sttr. wait.)
for i in 0 to 40 loop temp <= int2vec(rando). Carry_in). end loop. Carry_out). string('(" A = ")). end bench. Sum). write(sttr. write(sttr. string('(" Carry_out = ")). string('(" Sum = ")). end process. B). wait for 1 ms. write(sttr. writeline (dataout. sttr). write(sttr.