CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 1
Chapter 1 Homework Solutions
1.11 Using Eq. (1) of Sec 1.1, give the base10 value for the 5bit binary number 11010
(b
4
b
3
b
2
b
1
b
0
ordering).
From Eq. (1) of Sec 1.1 we have
b
N1
2
1
+ b
N2
2
2
+ b
N3
2
3
+
...
+ b
0
2
N
=
∑
i=1
N
b
Ni
2
i
1 × 2
1
+ 1× 2
2
+ 0 × 2
3
+ 1 × 2
4
+ 0 × 2
5
=
1
2
+
1
4
+
0
8
+
1
16
+
0
32
=
16 + 8 + 0 + 2 + 0
32
=
26
32
=
13
16
1.12 Process the sinusoid in Fig. P1.2 through an analog sample and hold. The sample
points are given at each integer value of t/T.
1 2 3 4 5 6 7 8 0
1
2
3
4
5
6
7
8
A
m
p
l
i
t
u
d
e
t
T
__
9
10
11
12
13
14
15
9 10 11
Sample times
Figure P1.12
1.13 Digitize the sinusoid given in Fig. P1.2 according to Eq. (1) in Sec. 1.1 using a
fourbit digitizer.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 2
1 2 3 4 5 6 7 8 0
1
2
3
4
5
6
7
8
A
m
p
l
i
t
u
d
e
t
T
__
9
10
11
12
13
14
15
9 10 11
Sample times
1000
1100
1110
1111
1101
1010
0110
0011
0010
0010
0101
1000
Figure P1.13
The figure illustrates the digitized result. At several places in the waveform, the digitized
value must resolve a sampled value that lies equally between two digital values. The
resulting digitized value could be either of the two values as illustrated in the list below.
Sample Time 4bit Output
0 1000
1 1100
2 1110
3 1111 or 1110
4 1101
5 1010
6 0110
7 0011
8 0010 or 0001
9 0010
10 0101
11 1000
1.14 Use the nodal equation method to find v
out
/v
in
of Fig. P1.4.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 3
v
in
R
1
R
2
R
3
R
4
v
1
v
out
g
m
v
1
Figure P1.14
A B
Node A:
0 = G
1
(v
1
v
in
) + G
3
(v
1
) + G
2
(v
1
 v
out
)
v
1
(G
1
+ G
2
+ G
3
)  G
2
(v
out
) = G
1
(v
in
)
Node B:
0 = G
2
(v
out
v
1
) + g
m1
(v
1
) + G
4
( v
out
)
v
1
(g
m1
 G
2
) + v
out
(G
2
+ G
4
) = 0
v
out
=
¦
¦
¦
¦
¦
¦
G
1
+G
2
+G
3
G
1
v
in
g
m1
 G
2
0
¦
¦
¦
¦
¦
¦
G
1
+G
2
+G
3
 G
2
g
m1
 G
2
G
2
+ G
4
v
out
v
in
=
G
1
(G
2
 g
m1
)
G
1
G
2
+ G
1
G
4
+ G
2
G
4
+ G
3
G
2
+ G
3
G
4
+ G
2
g
m1
1.15 Use the mesh equation method to find v
out
/v
in
of Fig. P1.4.
v
in
R
1
R
2
R
3
R
4
v
1
v
out
g
m
v
1
i
a
i
b
i
c
Figure P1.15
0 = v
in
+ R
1
(i
a
+ i
b
+ i
c
) + R
3
(i
a
)
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 4
0 = v
in
+ R
1
(i
a
+ i
b
+ i
c
) + R
2
(i
b
+ i
c
) + v
out
i
c
=
v
out
R
4
i
b
= g
m
v
1
= g
m
i
a
R
3
0 = v
in
+ R
1
\

.


i
a
+ g
m
i
a
R
3
+
v
out
R
4
+ R
3
i
a
0 = v
in
+ R
1
\

.


i
a
+ g
m
i
a
R
3
+
v
out
R
4
+ R
2
\

.


g
m
i
a
R
3
+
v
out
R
4
+ v
out
v
in
= i
a
(R
1
+ R
3
+ g
m
R
1
R
2
) + v
out
R
1
R
4
v
in
= i
a
(R
1
+ g
m
R
1
R
3
+ g
m
R
2
R
3
) + v
out
\

.


R
1
+ R
2
+ R
4
R
4
v
out
=
¦
¦
¦
¦
¦
¦
R
1
+R
3
+ g
m
R
1
R
3
v
in
R
1
+ g
m
R
1
R
3
+ g
m
R
2
R
3
v
in
¦
¦
¦
¦
¦
¦
R
1
+ R
3
+ g
m
R
1
R
3
R
1
/ R
4
R
1
+ g
m
R
1
R
3
+ g
m
R
2
R
3
(R
1
+ R
2
+R
4
) / R
4
v
out
=
v
in
R
3
R
4
(1  g
m
R
2
)
(R
1
+ R
3
+ g
m
R
1
R
3
) (R
1
+ R
2
+ R
4
)  (R
2
1
+ g
m
R
2
1
R
3
+ g
m
R
1
R
2
R
3
)
v
out
=
v
in
R
3
R
4
(1  g
m
R
2
)
R
1
R
2
+ R
1
R
4
+ R
1
R
3
+ R
2
R
3
+ R
3
R
4
+ g
m
R
1
R
3
R
4
v
out
v
in
=
R
3
R
4
(1  g
m
R
2
)
R
1
R
2
+ R
1
R
4
+ R
1
R
3
+ R
2
R
3
+ R
3
R
4
+ g
m
R
1
R
3
R
4
1.16 Use the source rearrangement and substitution concepts to simplify the circuit
shown in Fig. P1.6 and solve for i
out
/i
in
by making chaintype calculations only.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 5
i
in
R
1
R
2
R
3
v
1
i
out
r
m
i
i
i
in
R
1
R
2
R
3
v
1
i
out
r
m
i
i
r
m
i
i
in
R
1
R
2
R
3
v
1
i
out
Rr
m
i
r
m
i
Figure P1.16
i
out
=
r
m
R
3
i
i =
R
1
R + R
1
 r
m
i
in
i
out
i
in
=
r
m
R
1
/R
3
R + R
1
 r
m
1.17 Find v
2
/v
1
and v
1
/i
1
of Fig. P1.7.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 6
i
1
R
L
v
1
g
m
(v
1
v
2
)
v
2
Figure P1.17
v
2
v
1
= g
m
(v
1
 v
2
) R
L
v
2
(1 + g
m
R
L
) = g
m
R
L
v
1
v
2
v
1
=
g
m
R
L
1 + g
m
R
L
v
2
= i
1
R
L
substituting for v
2
yields:
i
1
R
L
v
1
=
g
m
R
L
1 + g
m
R
L
v
1
i
1
=
R
L
( 1 + g
m
R
L
)
g
m
R
L
v
1
i
1
= R
L
+
1
g
m
1.18 Use the circuitreduction technique to solve for v
out
/v
in
of Fig. P1.8.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 7
v
in
R
1
R
2
v
1
A
v
(v
in
 v
1
)
v
out
v
in
R
1
R
2
v
1
A
v
v
1
v
out
A
v
v
in
N
1
N
2
Figure P1.18a
Multiply R
1
by (A
v
+ 1)
v
in
R
1
(A
v
+1)
R
2
v
1 v
out
A
v
v
in
Figure P1.18b
v
out
=
A
v
v
in
R
2
R
2
+ R
1
(A
v
+1)
v
out
v
in
=
A
v
R
2
R
2
+ R
1
(A
v
+1)
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 8
v
out
v
in
=
A
v
A
v
+ 1
R
2
R
2
A
v
+ 1
+ R
1
As A
v
approaches infinity,
v
out
v
in
=
R
2
R
1
1.19 Use the Miller simplification concept to solve for v
out
/v
in
of Fig. A3 (see
Appendix A).
v
in
R
1
R
2
R
3
v
out
r
m
i
a
i
a
i
b
Figure P1.19a (Figure A3 Mesh analysis.)
v
1
K =
v
out
v
1
=
r
m
i
a
i
a
R
2
=
r
m
R
2
Z
1
=
R
3
1 +
r
m
R
2
Z
2
=
R
3
r
m
R
2

r
m
R
2
 1
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 9
Z
2
=
r
m
R
3
R
2
r
m
R
2
+ 1
=
R
3
R
2
r
m
+ 1
v
in
R
1
R
2
v
out
r
m
i
a
i
a
Z
1
Z
2
Figure P1.19b
i
a
=
v
in
(R
2
 Z
1
)
(R
2
 Z
1
) + R
1
\

.


1
R
2
v
out
= r
m
i
a
v
out
=
v
in
r
m
(R
2
 Z
1
)
(R
2
 Z
1
) + R
1
\

.


1
R
2
v
out
v
in
=
r
m
(R
2
 Z
1
)
(R
2
 Z
1
) + R
1
\

.


1
R
2
v
out
v
in
=
r
m
R
3
(R
1
R
2
+ R
1
R
3
+ R
1
r
m
+ R
2
R
3
)
1.110 Find v
out
/i
in
of Fig. A12 and compare with the results of Example A1.
R
1 R
3
v
1
g
m
v
1
R'
2
v
out i
in
Figure P1.110
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 10
v
1
= i
in
(R
1
 R
'
2
)
v
out
= g
m
v
1
R
3
= g
m
R
3
i
in
(R
1
 R
'
2
)
v
out
i
in
= g
m
R
3
(R
1
 R
'
2
)
R
'
2
=
R
2
1 + g
m
R
3
R
1
 R
'
2
=
R
1
R
2
1 + g
m
R
3
(1 + g
m
R
3
) R
1
+ R
2
1 + g
m
R
3
R
1
 R
'
2
=
R
1
R
2
(1 + g
m
R
3
) R
1
+ R
2
v
out
i
in
=
g
m
R
1
R
2
R
3
R
1
+ R
2
+ R
3
+ g
m
R
1
R
3
The A.11 result is:
v
out
i
in
=
R
1
R
3
 g
m
R
1
R
2
R
3
R
1
+ R
2
+ R
3
+ g
m
R
1
R
3
if g
m
R
2
>> 1 then the results are the same.
1.111 Use the Miller simplification technique described in Appendix A to solve for the
output resistance, v
o
/i
o
, of Fig. P1.4. Calculate the output resistance not using the Miller
simplification and compare your results.
v
in
R
1
R
2
R
3
R
4
v
1
v
out
g
m
v
1
Figure P1.111a
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 11
Z
o
with Miller
K = g
m
R
4
Z
2
=
R
2
g
m
R
4
g
m
R
4
 1
=
R
2
g
m
R
4
1 + g
m
R
4
Z
0
= R
4
 Z
2
=
g
m
R
2
R
2
4
1 + g
m
R
4
(1 + g
m
R
4
) R
4
+ g
m
R
2
R
2
4
1 + g
m
R
4
Z
0
= R
4
 Z
2
=
g
m
R
2
R
2
4
R
4
+ g
m
R
4
( R
4
+ R
2
)
Z
o
without Miller
R
1
R
3
R
2
R
4
v
1
v
T
g
m
v
1
i
T
Figure P1.111b
v
1
= (R
1
 R
3
)
\

.


i + g
m
v
1

v
T
R
4
v
1
[1 + g
m
(R
1
 R
3
)] = ( R
1
 R
3
)
\

.


i
T
+ 
v
T
R
4
(1) v
1
=
(R
1
 R
3
) (i
T
R
4
+  v
T
)
R
4
[1 + g
m
(R
1
 R
3
)]
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 12
(2) v
1
=
v
T
(R
1
 R
3
)
R
1
 R
3
+ R
2
Equate (1) and (2)
v
T
(R
1
 R
3
)
R
1
 R
3
+ R
2
=
(R
1
 R
3
) (i
T
R
4
 v
T
)
R
4
[1 + g
m
(R
1
 R
3
)]
v
T
R
1
 R
3
+ R
2
=
i
T
R
4
 v
T
R
4
[1 + g
m
(R
1
 R
3
)]
v
T
¹
´
¦
)
`
¹
R
4
[1 + g
m
(R
1
 R
3
)] + R
2
+ R
1
R
3
= i
T
R
4
(R
2
+ R
1
R
3
)
Z
0
=
R
4
(R
2
+ R
1
R
3
)
R
2
+ R
4
+ g
m
R
4
(R
1
R
3
) + R
1
R
3
Z
0
=
R
4
R
2
+
R
1
R
3
R
4
R
1
+ R
3
R
2
+ R
4
+
g
m
R
4
R
1
R
3
+ R
1
R
3
R
1
+R
3
Z
0
=
R
4
R
2
(R
1
+ R
3
) + R
1
R
3
R
4
(R
2
+ R
4
) (R
1
+ R
3
) + R
1
R
3
+ g
m
R
1
R
3
R
4
Z
0
=
R
1
R
2
R
4
+ R
2
R
3
R
4
+ R
1
R
3
R
4
R
1
R
2
+ R
2
R
3
+ R
3
R
4
+ R
1
R
4
+ R
1
R
3
+ g
m
R
1
R
3
R
4
1.112 Consider an ideal voltage amplifier with a voltage gain of A
v
= 0.99. A resistance
R = 50 kΩ is connected from the output back to the input. Find the input resistance
of this circuit by applying the Miller simplification concept.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions : 9/20/2002 13
0.99v
1
R=50K
v
1
v
out
i
Figure P1.112
R
in
=
R
1  K
K = 0.99
R
in
=
50 KΩ
1  0.99
=
50 K Ω
0.01
= 5 Meg Ω
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 1
Chapter 2 Homework Solutions
Problem 2.11
List the five basic MOS fabrication processing steps and give the purpose or function of
each step.
Oxidation: Combining oxygen and silicon to form silicondioxide (SiO
2
).
Resulting SiO
2
formed by oxidation is used as an isolation barrier (e.g., between
gate polysilicon and the underlying channel) and as a dielectric (e.g., between two
plates of a capacitor).
Diffusion: Movement of impurity atoms from one location to another (e.g., from
the silicon surface to the bulk to form a diffused well region).
Ion Implantation: Firing ions into an undoped region for the purpose of doping it
to a desired concentration level. Specific doping profiles are achievable with ion
implantation which cannot be achieved by diffusion alone.
Deposition: Depositing various films on to the wafer. Used to deposit dielectrics
which cannot be grown because of the type of underlying material. Deposition
methods are used to lay down polysilicon, metal, and the dielectric between them.
Etching: Removal of material sensitive to the etch process. For example, etching
is used to eliminate unwanted polysilicon after it has been laid out by deposition.
Problem 2.12
What is the difference between positive and negative photoresist and how is photoresist
used?
Positive: Exposed resist changes chemically so that it can dissolve upon exposure
to light. Unexposed regions remain intact.
Negative: Unexposed resist changes chemically so that it can dissolve upon
exposure to light. Exposed regions remain intact.
Photoresist is used as a masking layer which is paterned appropriately so that
certain underlying regions are exposed to the etching process while those regions
covered by photoresist are resistant to etching.
Problem 2.13
Illustrate the impact on source and drain diffusions of a 7° angle off perpendicular ion
implant. Assume that the thickness of polysilicon is 8000 Å and that out diffusion from
point of ion impact is 0.07 µm.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 2
Figure P2.13
Ion implantation
After ion implantation
After diffusion
Polysilicon
Gate
7
o
Implanted ions
Implanted ions
diffused
Polysilicon
Gate
Polysilicon
Gate
Polysilicon
Gate
No overlap of
gate to diffusion
Significant overlap of
polysilicon to gate
(a)
(b)
(c)
Problem 2.14
What is the function of silicon nitride in the CMOS fabrication process described in
Section 2.1
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 3
The primary purpose of silicon nitride is to provide a barrier to oxygen so that when
deposited and patterned on top of silicon, silicon dioxide does not form below where the
silicon nitride exists.
Problem 2.15
Give typical thickness for the field oxide (FOX), thin oxide (TOX), n
+
or p
+
, pwell, and
metal 1 in units of µm.
FOX: ~ 1 µm
TOX: ~ 0.014 µm for an 0.8 µm process
N+/p+: ~ 0.2 µm
Well: ~ 1.2 µm
Metal 1: ~ 0.5 µm
Problem 2.21
Repeat Example 2.21 if the applied voltage is 2 V.
N
A
= 5 × 10
15
/cm
3,
N
D
= 10
20
/cm
3
φ
o
=
kT
q
ln
\

.



N
A
N
D
n
2
i
=
1.381×10
23
×300
1.6×10
19
ln
\

.

 5×10
15
×10
20
(1.45×10
10
)
2
= 0.9168
x
n
=
2ε
si
(φ
o
−v
D
)N
A
qN
D
(N
A
+ N
D
)
1/2
=
2×11.7×8.854×10
14
(0.9168 +2.0) 5×10
15
1.6×10
19
×10
20
( 5×10
15
+ 10
20
)
1/2
= 43.5×10
12
m
x
p
= −
2ε
si
(φ
o
− v
D
)N
D
qN
A
(N
A
+ N
D
)
1/2
=
2×11.7×8.854×10
14
(0.9168 +2.0) 10
20
1.6×10
19
×5×10
15
( 5×10
15
+ 10
20
)
1/2
= −0.869 µm
x
d
= x
n
− x
p
= 0 + 0.869 µm = 0.869 µm
C
j0
=
dQ
j
dv
D
= A
ε
si
qN
A
N
D
2(N
A
+ N
D
) (φ
o
)
1/2
C
j0
= 1×10
3
×1×10
3
11.7×8.854×10
14
×1.6×10
19
×5×10
15
×1×10
20
2(5×10
15
+1×10
20
) (0.917)
1/2
= 21.3 fF
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 4
C
j0
=
C
j0
\

.


1 −
φ
0
v
D
1/2
=
21.3 fF
\

.


1 −
2
0.917
1/2
= 11.94 fF
Problem 2.22
Develop Eq. (2.29) using Eqs. (2.21), (2.27), and (2.28).
Eq. 2.21
x
d
= x
n
− x
p
Eq. 2.27
x
n
=
2ε
si
(φ
o
− v
D
)N
A
qN
D
(N
A
+ N
D
)
1/2
Eq. 2.28
x
p
= −
2ε
si
(φ
o
− v
D
)N
D
qN
A
(N
A
+ N
D
)
1/2
x
d
=
2ε
si
(φ
o
− v
D
)N
2
A
+ 2ε
si
(φ
o
− v
D
)N
2
D
qN
A
N
D
(N
A
+ N
D
)
1/2
x
d
= (φ
o
− v
D
)
1/2
2ε
si
\

.

N
2
A
+ N
2
D
qN
A
N
D
(N
A
+ N
D
)
1/2
Assuming that 2N
A
N
D
<< (N
A
+ N
D
)
2
Then
x
d
= (φ
o
− v
D
)
1/2
2ε
si
( )
N
A
+ N
D
2
qN
A
N
D
(N
A
+ N
D
)
1/2
x
d
= (φ
o
− v
D
)
1/2
2ε
si
( )
N
A
+ N
D
qN
A
N
D
1/2
Problem 2.23
Redevelop Eqs. (2.27) and (2.28) if the impurity concentration of a pn junction is given
by Fig. 2.22 rather than the step junction of Fig. 2.21(b).
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 5
Referring to Figure P2.23
N
D
x
0
N
D
 N
A
(cm
3
)
x
0
x
p
E
0
x
x
x
d
φ
0
− v
D
N
A
qN
D
qN
A
x
n
Figure P2.23
E(x)
V(x)
ρ(x)
N
D
 N
A
= ax
Using Poisson’s equation in one dimension
d
2
V
dx
2
= 
ρ(x)
ε
ρ(x)= qax , when x
p
< x < x
n
d
2
V
dx
2
= 
qax
ε
E(x) = 
dV
dx
=
qa
2ε
x
2
+ C
1
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 6
E(x
p
) = E(x
n
) = 0
then
0 =
qa
2ε
x
2
p
+ C
1
C
1
= 
qa
2ε
x
2
p
E(x) =
qa
2ε
x
2
−
qa
2ε
x
2
p
=
qa
2ε
\

.

x
2
− x
2
p
The voltage across the junction is given as
V = −
⌡
1
⌠
x
p
x
n
E(x)dx = −
qa
2ε
⌡
1
⌠
x
p
x
n
\

.

x
2
 x
2
p
dx
V = −
qa
2ε
¦
¦
¦
\

.

 x
3
3
− x
2
p
x
x
n
x
p
V = −
qa
2ε
\

.



x
3
n
3
− x
2
p
x
n
−
\

.



x
3
p
3
− x
2
p
x
p
V = −
qa
2ε
\

.



x
3
n
3
− x
2
p
x
n
− x
3
p
\

.


1
3
− 1 = −
qa
2ε
x
3
n
3
− x
2
p
x
n
+
2
3
x
3
p
Since x
p
= x
n
V = −
qa
2ε
−
x
3
p
3
+ x
3
p
+
2
3
x
3
p
= −
qa
2ε
x
3
p
−
1
3
+ 1 +
2
3
= −
qa
2ε
x
3
p
\

.


4
3
V = −
2qa
3ε
x
3
p
V represents the barrier potential across the junction, φ
0
− V
D
. Therefore
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 7
φ
0
− V
D
=
2qa
3ε
x
3
p
x
p
= − x
n
=
\

.

 3ε
2qa
1/3
(φ
0
− V
D
)
1/3
Problem 2.24
Plot the normalized reverse current, i
RA
/i
R
, versus the reverse voltage v
R
of a silicon pn
diode which has BV = 12 V and n = 6.
i
RA
i
R
=
1
1 − (v
R
/BV)
n
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14
V
R
i
RA
/i
R
Figure P2.24
Problem 2.25
What is the breakdown voltage of a pn junction with N
A
= N
D
= 10
16
/cm
3
?
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 8
BV ≅
ε
si
(N
A
+ N
D
)
2qN
A
N
D
E
2
max
BV ≅
11.7×8.854×10
14
(10
16
+ 10
16
)
2×1.6×10
19
×10
16
×10
16
(3×10
5
)
2
= 58.27 volts
Problem 2.26
What change in v
D
of a silicon pn diode will cause an increase of 10 (an order of
magnitude) in the forward diode current?
i
D
= I
s
exp
\

.


v
D
V
t
− 1 ≅ I
s
exp
\

.


v
D
V
t
10 i
D
i
D
=
I
s
exp
\

.


v
D1
V
t
I
s
exp
\

.


v
D2
V
t
=
exp
\

.


v
D1
V
t
exp
\

.


v
D2
V
t
= exp
\

.


v
D1
 v
D2
V
t
10 = exp
\

.


v
D1
 v
D2
V
t
V
t
ln(10) = v
D1
 v
D2
25.9 mV × 2.303 = 59.6 mV = v
D1
 v
D2
v
D1
 v
D2
= 59.6 mV
Problem 2.31
Explain in your own words why the magnitude of the threshold voltage in Eq. (2.319)
increases as the magnitude of the sourcebulk voltage increases (The sourcebulk pn
diode remains reversed biased.)
Considering an nchannel device, as the gate voltage increases relative to the bulk,
the region under the gate will begin to invert. What happens near the source? If the
source is at the same potential as the bulk, then the region adjacent to the edge of
the source inverts as the rest of the bulk region under the gate inverts. However, if
the source is at a higher potential than the bulk, then a greater gate voltage is
required to overcome the electric field induced by the source. While a portion of
the region under the gate still inverts, there is no path of current flow to the source
because the gate voltage is not large enough to invert right at the source edge. Once
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 9
the gate is greater than the source and increasing, then the region adjacent to the
source can begin to invert and thus provide a current path into the channel.
Problem 2.32
If V
SB
= 2 V, find the value of V
T
for the nchannel transistor of Ex. 2.31.
2φ
F
= 0.940
γ = 0.577
V
T0
= 0.306
V
T
= V
T0
+ γ ( −2φ
F
+ v
SB
 − −2φ
F
)
V
T
= 0.306 + 0.577 ( 0.940 + 2 − 0.940) = 0.736 volts
V
T
= 0.736 volts
Problem 2.33
Rederive Eq. (2.327) given that V
T
is not constant in Eq. (2.322) but rather varies
linearly with v(y) according to the following equation.
V
T
= V
T0
+ a v(y)
<< correction to book
⌡
1
⌠
0
L
i
D
dy
=
⌡
1
⌠
0
v
DS
Wµ
n
Q
I
(y)
dv(y) =
⌡
1
⌠
0
v
DS
Wµ
n
C
ox
[v
GS
− v(y) − V
T
(y)] dv(y)
V
T
(y)= V
T0
+ a v(y)
i
D
L =
⌡
1
⌠
0
v
DS
Wµ
n
C
ox
[v
GS
− v(y) − V
T0
− a v(y)] dv(y)
i
D
L = Wµ
n
C
ox
⌡
1
⌠
0
v
DS
[v
GS
− V
T0
− v(y) (1 + a)] dv(y)
i
D
L = Wµ
n
C
ox
(v
GS
− V
T0
)v(y) − (1 + a)
v(y)
2
2
v
DS
0
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 10
i
D
=
Wµ
n
C
ox
L
(v
GS
− V
T0
) v
DS
− (1 + a)
v
DS
2
2
Problem 2.34
If the mobility of an electron is 500 cm
2
/(V⋅s) and the mobility of a hole is 200 cm
2
/(V⋅s),
compare the performance of an nchannel with a pchannel transistor. In particular,
consider the value of the transconductance parameter and speed of the MOS transistor.
Since K’ = µC
ox
, the transconductance of an nchannel transistor will be 2.5 time greater
than the transconductance of a pchannel transistor. Remember that mobility will degrade
as a function of terminal conditions so transconductance will degrade as well. The speed
of a circuit is determined in a large part by the capacitance at the terminals and the
transconductance. When terminal capacitances are equal for an nchannel and pchannel
transistor of the same dimensions, the higher transconductance of the nchannel results in
a faster circuit.
Problem 2.35
Using Ex. 2.31 as a starting point, calculate the difference in threshold voltage between
two devices whose gateoxide is different by 5% (i.e., t
ox
= 210 Å).
φ
F
(substrate) = −0.0259 ln
3× 10
16
1.45 × 10
10
= −0.377 V
φ
F
(gate) = 0.0259 ln
4 × 10
19
1.45 × 10
10
= 0.563 V
φ
MS
= φ
F
(substrate) − φ
F
(gate) = −0.940 V.
C
ox
= ε
ox
/t
ox
=
3.9 × 8.854 × 10
14
210 × 10
8
= 1.644 × 10
7
F/cm
2
Q
b0
= − \

.

2 × 1.6 × 10
19
× 11.7 × 8.854 × 10
14
× 2 × 0.377 × 3 × 10
16
1/2
= − 8.66 × 10
8
C/cm
2
.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 11
Q
b0
C
ox
=
−8.66 × 10
8
1.644 × 10
7
= −0.5268 V
Q
ss
C
ox
=
10
10
× 1.60 × 10
19
1.644 × 10
7
= 9.73 × 10
3
V
V
T0
= − 0.940 + 0.754 + 0.5268 − 9.73 × 10
3
= 0.331 V
γ =
2 × 1.6 × 10
19
× 11.7 × 8.854 × 10
14
× 3 × 10
16
1/2
1.644 × 10
7
= 0.607 V
1/2
Problem 2.36
Repeat Ex. 2.31 using N
A
= 7 × 10
16
cm
3
, gate doping, N
D
= 1 × 10
19
cm
3
.
φ
F
(substrate) = −0.0259 ln
7× 10
16
1.45 × 10
10
= −0.3986 V
φ
F
(gate) = 0.0259 ln
1 × 10
19
1.45 × 10
10
= 0.527 V
φ
MS
= φ
F
(substrate) − φ
F
(gate) = −0.9256 V.
C
ox
= ε
ox
/t
ox
=
3.9 × 8.854 × 10
14
200 × 10
8
= 1.727 × 10
7
F/cm
2
Q
b0
= − \

.

2 × 1.6 × 10
19
× 11.7 × 8.854 × 10
14
× 2 × 0.3986 × 7 × 10
16
1/2
= − 13.6 × 10
8
C/cm
2
.
Q
b0
C
ox
=
−13.6 × 10
8
1.727 × 10
7
= −0.7875 V
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 12
Q
ss
C
ox
=
10
10
× 1.60 × 10
19
1.727 × 10
7
= 9.3 × 10
3
V
V
T0
= − 0.9256 + 0.797 + 0.7875 − 9.3 × 10
3
= 0.6496 V
γ =
2 × 1.6 × 10
19
× 11.7 × 8.854 × 10
14
× 7 × 10
16
1/2
1.727 × 10
7
= 0.882 V
1/2
Problem 2.41
Given the component tolerances in Table 2.41, design the simple lowpass filter
illustrated in Fig P2.41 to minimize the variation in pole frequency over all process
variations. Pole frequency should be designed to a nominal value of 1MHz. You must
choose the appropriate capacitor and resistor type. Explain your reasoning. Calculate the
variation of pole frequency over process using the design you have chosen.
R
Figure P2.4.1
C v
in
v
out
 To minimize distortion, we would choose minimum voltage coefficient for
resistor and capacitor.
 To minimize variation, we choose components with the lowest tolerance.
The obvious choice for the resistor is Polysilicon. The obvious choice for the capacitor is
the MOS capacitor. Thus we have the following:
We want ω
3dB
=2π×10
6
= 1/RC
C = 2.2 fF/µm
2
to 2.7 fF/µm
2
; R = 20 Ω/! to 40 Ω/!
Nominal values are
C = 2.45 fF/µm
2
; R = 30 Ω/!
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 13
In order to minimize total area used, you can do the following:
Set resistor width to 5µm (choosing a different width is OK).
Define:
N = the number of squares for the resistor
A
C
= area for the capacitor.
Then:
R = N × 30
C = A
C
× C’ (use C’ to avoid confusion)
We want:
RC =
1
2π×10
6
Total area = A
tot
= N×25+A
C
A
tot
= 25×N +
1.59×10
6
N
To minimize area, set
∂A
tot
∂N
= 25 −
1.59×10
6
N
2
= 0
N = 252 ⇒ A
C
= 6308 µm
2
Nominal values for R and C:
R = 7.56 kΩ ;
C = 15.45 pF
Minimum values for R and C:
R = 5.04 kΩ ;
C = 13.88 pF
Maximum values for R and C:
R = 10.08 kΩ ;
C = 17.03 pF
Max pole frequency =
1
(2π)(5.04k) (13.88pF)
⇒ 2.275 MHz
Min pole frequency =
1
(2π)(10.08k) (17.03pF)
⇒ 927 kHz
Problem 2.42
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 14
List two sources of error that can make the actual capacitor, fabricated using a CMOS
process, differ from its designed value.
Sources of error are:
 Variations in oxide thickness between the capacitor plates
 Dimensional variations of the plates due to the tolerance in
 Etch
 Mask
 Registration error (between layers)
Problem 2.43
What is the purpose of the n
+
implantation in the capacitor of Fig. 2.41(a)?
The implant is required to form a diffusion with a doping similar to that of the drain and
source. As the voltage across the capacitor varies, depleting the bottom plate of carriers
causes the capacitor to have a voltage coefficient which can have a bad effect on analog
performance. With a highlydoped diffusion below the top plate, voltage coefficient is
minimized.
Problem 2.44
Consider the circuit in Fig. P2.44. Resistor R
1
is an nwell resistor with a nominal value of
10 kΩ when the voltage at both terminals is 3 V. The input voltage, v
in
, is a sine wave with an
amplitude of 2 VPP and a dc component of 3 V. Under these conditions, the value of R
1
is given
as
R
1
= R
nom
1 + K
\

.

 v
in
+ v
out
2
where R
nom
is 10K and the coefficient K is the voltage coefficient of an nwell resistor
and has a value of 10K ppm/V. Resistor R
2
is an ideal resistor with a value of 10 kΩ.
Derive a timedomain expression for v
out
. Assume that there are no frequency
dependencies.
TBD
Problem 2.45
Repeat problem 21 using a P+ diffused resistor for R
1
. Assume that a P+ resistor’s
voltage coefficient is 200 ppm/V. The nwell in which R1 lies, is tied to a 5 volt supply.
TBD
Problem 2.46
Consider problem 2.45 again but assume that the nwell in which R1 lies is not
connected to a 5 volt supply, but rather is connected as shown in Fig. P2.46.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 15
R
1
Figure P2.46
v
in
v
out R
2
R
nwell
p substrate
FOX
nwell
n+
FOX
p+ diffusion
Voltage effects a resistor’s value when the voltage between any point along the current
path in the resistor and the material in which it lies. The voltage difference causes a
depletion region to form in the resistor, thus increasing its resistance. This idea is
illustrated in the diagram below.
nwell
p+ diffusion
+
V
x

I
V
1
x
+
0 Volts

Voltage difference
causes depletion region
narrowing the current path
VDD
VDD
In order to keep the depletion region from varying along the direction of the current path,
the potential of the material below the p+ diffusion (nwell in this case) must vary in the
same way as the potential of the p+ diffusion. This is accomplished by causing current to
flow in the underlying material (nwell) in parallel with the current in the p+ diffusion as
illustrated below.
nwell
p+ diffusion
I
p+
V
1
x
I
nwell
∆V
p+
∆V
nwell
R
p+
R
nwell
V
x
VDD
VDD
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 16
It is easy to see that if ∆V
p+
= ∆V
nwell
then V
x
= 0. Thus by attaching the nwell in
parallel with the desired current path, the effects of voltage coefficient of the p+ material
are eliminated. There is a secondorder effect due to the fact that the nwell resistor will
have a voltage coefficient due to the underlying material (p substrate) tied to ground.
Even with this nonideal effect, significant improvement is achieved by this method.
Problem 2.51
Assume v
D
= 0.7 V and find the fractional temperature coefficient of I
s
and v
D
.
1
I
s
dI
s
dT
=
3
T
+
1
T
V
Go
V
t
=
3
300
+
1
300
1.205
0.0259
= 0.1651
dv
D
dT
= −
V
Go
1.942 × 10
3
v
D
T
−
3V
t
T
= −
1.205 − 0.7
300
−
3×0.0259
300
= 1.942 × 10
3
1
v
D
dv
D
dT
=
1.942 × 10
3
0.7
= 2.775 × 10
3
Problem 2.52
Plot the noise voltage as a function of the frequency if the thermal noise is 100 nV/ Hz
and the junction of the 1/f and thermal noise (the 1/f noise corner) is 10,000 Hz.
1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz
10 µV/ Hz
1 µV/ Hz
100 nV/ Hz
frequency
noise
voltage
Problem 2.61
Given the polysilicon resistor in Fig. P2.61 with a resistivity of ρ = 8×10
4
Ωcm,
calculate the resistance of the structure. Consider only the resistance between contact
edges. ρ
s
= 50 Ω/ ❑
Fix problem: Eliminate . ρ ρρ ρ
s
= 50 Ω ΩΩ Ω/ ❑ ❑❑ ❑ because it conflicts with ρ ρρ ρ = 8× ×× ×10
4
Ω ΩΩ Ωcm
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 17
R =
ρL
WT
=
8×10
4
× 3×10
4
1×10
4
× 8000×10
8
= 30 Ω
Problem 2.62
Given that you wish to match two transistors having a W/L of 100µm/0.8µm each.
Sketch the layout of these two transistors to achieve the best possible matching.
Best matching is achieved using the following principles:
 unit matching
 common centroid
 photolithographic invariance
Figure P2.62
Metal 2
Metal 2
Via 1
Metal 1
25 µm
0.8 µm
Problem 2.63
Assume that the edge variation of the top plate of a capacitor is 0.05µm and that capacitor
top plates are to be laid out as squares. It is desired to match two equal capacitors to an
accuracy of 0.1%. Assume that there is no variation in oxide thickness. How large would
the capacitors have to be to achieve this matching accuracy?
Since capacitance is dominated by the area component, ignore the perimeter (fringe)
component in this analysis. The units in the analysis that follows is micrometers.
C = C
AREA
(d ± 0.05)
2
where d is one (both) sides of the square capacitor.
C
1
C
1
=
(d + 0.05)
2
(d − 0.05)
2
= 1.001
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 18
C
1
C
1
=
(d + 0.05)
2
(d − 0.05)
2
= 1.001
d
2
+ 0.1d + 0.05
2
= 1.001\

.

d
2
− 0.1d + 0.05
2
Solving this quadratic yields
d = 200.1
Problem 2.64
Show that a circular geometry minimizes perimetertoarea ratio for a given area
requirement. In your proof, compare against rectangle and square.
A
circle
= π r
2
A
square
= d
2
if A
square
= A
circle
then
r =
d π
π
P
circle
P
square
=
2d π
4d
=
π
2
< 1
Ideally,
C
perimeter
C
area
= 0, so since
P
circle
P
square
< 1, the impact of perimeter on a circle is less
than on a square.
Problem 2.65
Show analytically how the Yiannoulospath technique illustrated in Fig. 2.65 maintains a
constant areatoperimeter ratio with noninteger ratios.
Area of one unit is:
A
u
= L
2
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 19
Total area = N × A
u
Total periphery = 2(N + 1)
C
Total
= K
A
× N × A
u
+ K
P
× 2(N + 1)
where K
A
and K
P
represent area and perimeter capacitance (per unit area and per unit
length) respectively.
Consider two capacitors with different numbers of units but drawn following the template
shown in Fig. 2.65(a). Their ratio would be
Figure P2.65 (a)
One unit
L
L
C
1
C
2
=
K
A
× N
1
× A
u
+ K
P
× 2(N
1
+ 1)
K
A
× N
2
× A
u
+ K
P
× 2(N
2
+ 1)
The ratio of the area and peripheral components by themselves are
\

.


C
1
C
2 AREA
=
K
A
× N
1
× A
u
K
A
× N
2
× A
u
=
N
1
N
2
\

.


C
1
C
2 PER
=
K
P
× 2(N
1
+ 1)
K
P
× 2(N
2
+ 1)
=
N
1
+ 1
N
2
+ 1
N
1
+ 1
N
2
+ 1
≠
N
1
N
2
unless N
1
= N
2
Therefore, the structure in Fig. P2.65(a) cannot achieve constant area to perimeter ratio.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 20
Consider Fig. P2.65(b).
Figure P2.65 (b)
One unit
Total area = (N + 1) × A
u
Total periphery = 2(N + 1) (as before)
Notice what has happened. By adding the extra unit area, two peripheral units are
eliminated but two additional ones are added resulting in no change in total periphery.
However, one additional area has been added. Thus
C
1
C
2
=
K
A
× (N
1
+ 1) × A
u
+ K
P
× 2(N
1
+ 1)
K
A
× (N
2
+ 1) × A
u
+ K
P
× 2(N
2
+ 1)
The ratio of the area and peripheral components by themselves are
\

.


C
1
C
2 AREA
=
K
A
× (N
1
+ 1) × A
u
K
A
× (N
2
+ 1) × A
u
=
N
1
+ 1
N
2
+ 1
\

.


C
1
C
2 PER
=
K
P
× 2(N
1
+ 1)
K
P
× 2(N
2
+ 1)
=
N
1
+ 1
N
2
+ 1
N
1
+ 1
N
2
+ 1
=
N
1
+ 1
N
2
+ 1
!!!
Problem 2.66
Design an optimal layout of a matched pair of transistors whose W/L are 8µm/1µm. The
matching should be photolithographic invariant as well as common centroid.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 21
Figure P2.66
Metal 2
Metal 2
Via 1
Metal 1
2 µm
1 µm
Problem 2.67
Figure P2.67 illustrates various ways to implement the layout of a resistor divider.
Choose the layout that BEST achieves the goal of a 2:1 ratio. Explain why the other
choices are not optimal.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 22
A
B
A B
R
2R
A
B
A
B
(a)
A B
2x x
(b)
A
B
(c)
A
B
(d) (e)
(f)
Figure P2.67
Option A suffers the following:
 Orientation of the 2R resistor is partly orthogonal to the 1R resistor. Matched resistors should
have the same orientation.
 Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes
should surround all active resistors.
Option B suffers the following:
 Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes
should surround all active resistors.
 Resistors do not share a common centroid as they should.
Option C suffers the following:
 Resistors do not share a common centroid as they should.
 Uncertainty is introduced with the additional notch at the contact head.
Option D suffers the following:
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 23
 Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes
should surround all active resistors.
Option E suffers the following:
 Nothing
Option F suffers the following:
 Violates the unitmatching principle
 Resistors do not have the appropriate etch compensating (dummy) resistors. Dummy stripes
should surround all active resistors.
 Resistors do not share a common centroid as they should.
Unit Matching Etch Comp. Orientation Common
Centroid
(a) Yes No No Yes
(b) Yes No Yes No
(c) Yes Yes Yes No
(d) Yes No Yes Yes
(e) Yes Yes Yes Yes
(f) No No Yes No
Clearly, option (e) is the best choice.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 1
Chapter 3 Homework Solutions
Problem 3.11
Sketch to scale the output characteristics of an enhancement nchannel device if V
T
= 0.7
volt and I
D
= 500 µA when V
GS
= 5 V in saturation. Choose values of V
GS
= 1, 2, 3, 4,
and 5 V. Assume that the channel modulation parameter is zero.
0.00E+00
1.00E04
2.00E04
3.00E04
4.00E04
5.00E04
6.00E04
0 1 2 3 4 5 6
V
GS
I
DS
Problem 3.12
Sketch to scale the output characteristics of an enhancement pchannel device if V
T
= 0.7
volt and I
D
= 500 µA when V
GS
= 1, 2, 3, 4, and 6 V. Assume that the channel
modulation parameter is zero.
6.00E04
5.00E04
4.00E04
3.00E04
2.00E04
1.00E04
0.00E+00
6 5 4 3 2 1 0
V
GS
I
DS
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 2
Problem 3.13
In Table 3.12, why is γ
P
greater than γ
N
for a nwell, CMOS technology?
The expression for γ is:
γ =
2ε
si
q N
SUB
C
ox
Because γ is a function of substrate doping, a higher doping results in a larger value for γ.
In general, for an nwell process, the well has a greater doping concentration than the
substrate and therefore devices in the well will have a larger γ.
Problem 3.14
A largesignal model for the MOSFET which features symmetry for the drain and source
is given as
i
D
= K'
W
L
¹
´
¦
)
`
¹
[(v
GS
− V
TS
)
2
u(v
GS
− V
TS
)] − [(v
GD
− V
TD
)
2
u(v
GD
− V
TD
)]
where u(x) is 1 if x is greater than or equal to zero and 0 if x is less than zero (step
function) and V
TX
is the threshold voltage evaluated from the gate to X where X is either S
(Source) or D (Drain). Sketch this model in the form of i
D
versus v
DS
for a constant value
of v
GS
(v
GS
> V
TS
) and identify the saturated and nonsaturated regions. Be sure to extend
this sketch for both positive and negative values of v
DS
. Repeat the sketch of i
D
versus
v
DS
for a constant value of v
GD
(v
GD
> V
TD
). Assume that both V
TS
and V
TD
are positive.
v
GS
constant
v
GD
constant
v
GD
V
TD
>0
v
GS
V
TS
>0
v
GS
V
TS
<0
v
GD
V
TD
<0
K'(W/L)(v
GS
V
TS
)
2
K'(W/L)(v
GD
V
TD
)
2
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 3
Problem 3.15
Equation (3.112) and Eq. (3.118) describe the MOS model in nonsaturation and
saturation region, respectively. These equations do not agree at the point of transition
between saturation and nonsaturation regions. For hand calculations, this is not an issue,
but for computer analysis, it is. How would you change Eq. (3.118) so that it would
agree with Eq. (3.112) at v
DS
= v
DS
(sat)?
i
D
= K'
W
L
(v
GS
− V
T
) −
v
DS
2
v
DS
(3.112)
i
D
= K'
W
2L
(v
GS
− V
T
)
2
(1 + λv
DS
), 0 < (v
GS
− V
T
) ≤ v
DS
(3.118)
What happens to Eq. 3.112 at the point where saturation occurs?
i
D
= K'
W
L
(v
GS
− V
T
) −
v
DS
(sat)
2
v
DS
(sat)
v
DS
(sat)= v
GS
− V
T
then
i
D
= K'
W
L
(v
GS
− V
T
) v
DS
(sat) −
v
2
DS
(sat)
2
i
D
= K'
W
L
(v
GS
− V
T
) (v
GS
− V
T
) −
(v
GS
− V
T
)
2
2
i
D
= K'
W
L
( v
GS
− V
T
)
2
−
(v
GS
− V
T
)
2
2
= K'
W
L
(v
GS
− V
T
)
2
2
i
D
= K'
W
L
(v
GS
− V
T
)
2
2
which is not equal to Eq.(3.118) because of the channellength modulation term.
Since Eq. (3.118) is valid only during saturation when v
DS
> v
DS
(sat) we can subtract
v
DS
(sat) from the v
DS
in the channellength modulation term. Doing this results in the
following modification of Eq. (3.118).
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 4
i
D
= K'
W
2L
(v
GS
− V
T
)
2
1 + λ (v
DS
− v
DS
(sat)) , 0 < (v
GS
− V
T
) ≤ v
DS
When v
DS
= v
DS
(sat) , this expression agrees with the nonsaturation equation at the
point of transition into saturation. Beyond saturation, channellength modulation is
applied to the difference in v
DS
and v
DS
(sat) .
Problem 3.21
Using the values of Tables 3.11 and 3.21, calculate the values of CGB, CGS, and CGD
for a MOS device which has a W of 5 µm and an L of 1 µm for all three regions of
operation.
We will need LD in these calculations. LD can be approximated from the value given for
CGSO in Table 3.21.
LD =
220 × 10
12
24.7 × 10
4
≅ 89 × 10
9
Off
C
GB
= C
2
+ 2C
5
= C
ox
(W
eff
)(L
eff
) + 2CGBO(L
eff
)
W
eff
= 5 µm
L
eff
= 1 µm  2×89 nm = 822 × 10
9
C
GB
= 24.7 × 10
4
× (5× 10
6
)( 822 × 10
9
) + 2×700 × 10
12
×822 × 10
9
C
GB
= 11.3 × 10
15
F
C
GS
= C
1
≅ C
ox
(LD)(W
eff
) = CGSO(W
eff
)
C
GS
= ( 220 × 10
12
) ( 5 × 10
6
) = 1.1 × 10
15
C
GD
= C
2
≅ C
ox
(LD)(W
eff
) = CGDO(W
eff
)
C
GD
= ( 220 × 10
12
) ( 5 × 10
6
)= 1.1 × 10
15
Saturation
C
GB
= 2C
5
= CGBO (L
eff
)
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 5
C
GB
= 700 × 10
12
(822 × 10
9
) = 575 × 10
18
C
GS
= CGSO(W
eff
) + 0.67C
ox
(W
eff
)(L
eff
)
C
GS
= 220 × 10
12
× 5 × 10
6
+ 0.67 × 24.7 × 10
4
× 822 × 10
9
× 5 × 10
6
C
GS
= 7.868 × 10
15
C
GD
= C
3
≅ C
ox
(LD)(W
eff
) = CGDO(W
eff
)
C
GD
= CGDO(W
eff
) = 220 × 10
12
× 5 × 10
6
= 1.1 × 10
15
Nonsaturated
C
GB
= 2C
5
= CGBO (L
eff
)
C
GB
= CGBO (L
eff
) = 700 × 10
12
× 822 × 10
9
= 574 × 10
18
C
GS
= (CGSO + 0.5C
ox
L
eff
)W
eff
C
GS
= (220 × 10
12
+ 0.5 × 24.7 × 10
4
× 822 × 10
9
) × 5 × 10
6
= 6.18 × 10
15
C
GD
= (CGDO + 0.5C
ox
L
eff
)W
eff
C
GD
= (220 × 10
12
+ 0.5 × 24.7 × 10
4
× 822 × 10
9
) × 5 × 10
6
= 6.18 × 10
15
Problem 3.22
Find C
BX
at V
BX
= 0 V and 0.75 V of Fig. P3.7 assuming the values of Table 3.21 apply
to the MOS device where FC = 0.5 and PB = 1 V. Assume the device is nchannel and
repeat for a pchannel device.
Change problem to read: “V
BX
= == = 0 V and 0.75 V (with the junction always reverse
biased)…”
1.6µm
Figure P3.22
2.0µm
Polysilicon
Metal
Active Area
0.8µm
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 6
AX = 1.6 × 10
6
× 2.0 × 10
6
= 3.2 × 10
12
PX = 2×1.6 × 10
6
+ 2.0 × 2.0 × 10
6
= 7.2 × 10
6
NMOS case:
C
BX
=
(CJ)(AX)
1 −
\

.


v
BX
PB
MJ
+
(CJSW)(PX)
1 −
\

.


v
BX
PB
MJSW
C
BX
=
(770 × 10
6
)( 3.2 × 10
12
)
1 −
\

.


0
PB
MJ
+
(380 × 10
12
)( 7.2 × 10
6
)
1 −
\

.


0
PB
MJSW
= 5.2 × 10
15
PMOS case:
C
BX
=
(560 × 10
6
)( 3.2 × 10
12
)
1 −
\

.


0
PB
MJ
+
(350 × 10
12
)( 7.2 × 10
6
)
1 −
\

.


0
PB
MJSW
= 4.31 × 10
15
v
BX
 = 0.75 volts reverse biased
NMOS case:
C
BX
=
(CJ)(AX)
1 −
\

.


v
BX
PB
MJ
+
(CJSW)(PX)
1 −
\

.


v
BX
PB
MJSW
,
C
BX
=
(770 × 10
6
)( 3.2 × 10
12
)
1 −
\

.


0.75
1
0.5
+
(380 × 10
12
)( 7.2 × 10
6
)
1 −
\

.


0.75
1
0.38
C
BX
=
2.464 × 10
15
1.323
+
2.736 × 10
15
1.237
= 4.07 × 10
15
PMOS case:
C
BX
=
(560 × 10
6
)( 3.2 × 10
12
)
1 −
\

.


0.75
1
0.5
+
(350 × 10
12
)( 7.2 × 10
6
)
1 −
\

.


0.75
1
0.35
C
BX
=
1.79 × 10
15
1.323
+
2.52 × 10
15
1.216
= 3.425 × 10
15
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 7
Problem 3.23
Calculate the value of C
GB
, C
GS
, and C
GD
for an nchannel device with a length of 1 µm
and a width of 5 µm. Assume V
D
= 2 V, V
G
= 2.4 V, and V
S
= 0.5 V and let V
B
= 0 V.
Use model parameters from Tables 3.11, 3.12, and 3.21.
LD =
220 × 10
12
24.7 × 10
4
≅ 89 × 10
9
L
eff
= L  2 × LD = 1 × 10
6
− 2 × 89 × 10
9
= 822 × 10
9
V
T
= V
T0
+ γ [ ] 2φ
F
 + v
SB
− 2φ
F

V
T
= 0.7 + 0.4 [ ] 0.7 + 0.5
− 0.7 = 0.803
v
GS
− v
T
=2.4 − 0.5 − 0.803 = 1.096 < v
DS
thus saturation region
C
GB
= CGBO x L
eff
= 700 × 10
12
× 822 × 10
9
= 0.575 fF
C
GS
= CGSO(W
eff
) + 0.67C
ox
(W
eff
)(L
eff
)
C
GS
= 220 × 10
12
× 5 × 10
6
+ 0.67 × 24.7 × 10
4
× 822 × 10
9
× 5 × 10
6
C
GS
= 7.868 × 10
15
C
GD
= C
3
≅ C
ox
(LD)(W
eff
) = CGDO(W
eff
)
C
GD
= CGDO(W
eff
) = 220 × 10
12
× 5 × 10
6
= 1.1 × 10
15
Problem 3.31
Calculate the transfer function v
out
(s)/v
in
(s) for the circuit shown in Fig. P3.31. The
W/L of M1 is 2µm/0.8µm and the W/L of M2 is 4µm/4µm. Note that this is a small
signal analysis and the input voltage has a dc value of 2 volts.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 8
Figure P3.31
5 Volts
v
IN
= 2V
(dc)
+ 1mV
(rms)
v
out
+

W/L = 2/0.8
W/L = 4/4
M1
M2
v
IN
= 2V
(dc)
+ 1mV
(rms)
R
M1
C
M2
Figure P3.31b
v
out
+

v
out
(s)
v
IN
(s)
=
1/SC
M2
R
M1
+ 1/SC
M2
=
1
SC
M2
R
M1
+ 1
V
T1
= V
T0
+ γ [ ] 2φ
F
 + v
SB
− 2φ
F

V
T1
= 0.7 + 0.4 [ ] 0.7 + 2.0
− 0.7 = 1.02
R
M1
=
1
K'(W/L)
M1
(v
GS1
− V
T1
)
= 1.837 kΩ
C
M2
= W
M2
× L
M2
× C
ox
= 4 × 10
6
× 4 × 10
6
× 24.7 × 10
4
= 39.52 × 10
15
R
M1
C
M2
= 1.837 kΩ × 39.52 × 10
15
= 72.6 × 10
12
v
out
(s)
v
IN
(s)
==
1
S
13.77 × 10
9
+ 1
Problem 3.32
Design a lowpass filter patterened after the circuit in Fig. P3.31 that achieves a 3dB
frequency of 100 KHz.
1
2πRC
= 100,000
There is more than one answer to this problem because there are two free parameters.
Use the resistance from Problem 3.31.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 9
R
M1
= 1.837 kΩ
C
M2
=
1
2π ×1.837× 10
3
×1 × 10
5
= 866.4 pF
Choose W = L
C
M2
= W
M2
× L
M2
× C
ox
= W
2
M2
× 24.7 × 10
4
= 866.4 × 10
12
W
2
M2
= 350.8 × 10
9
W
M2
= 592 × 10
6
Problem 3.33
Repeat Examples 3.31 and 3.32 if the W/L ratio is 100 µm/10 µm.
Problem correction: Assume λ λλ λ = 0.01.
Repeat of Example 3.31
NChannel Device
g
m
= (2K'W/L)I
D

g
m
= 2×110 × 10
6
×10 × 50 × 10
6
= 332 × 10
6
g
mbs
= g
m
γ
2(2φ
F
 + V
SB
)
1/2
g
mbs
= 332 × 10
6
0.4
2(0.7+2.0)
1/2
= 40.4 × 10
6
g
ds
= I
D
λ
g
ds
= 50 × 10
6
× 0.01 = 500 × 10
9
PChannel Device
g
m
= (2K'W/L)I
D

CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 10
g
m
= 2×50 × 10
6
×10 × 50 × 10
6
= 224 × 10
6
g
mbs
= g
m
γ
2(2φ
F
 + V
SB
)
1/2
g
mbs
= 224 × 10
6
0.57
2(0.8+2.0)
1/2
= 38.2 × 10
6
g
ds
= I
D
λ
g
ds
= 50 × 10
6
× 0.01 = 500 × 10
9
Repeat of Example 3.32
NChannel Device
g
m
= βV
DS
= 110 × 10
6
× 10× 1 = 1.1 × 10
3
g
mbs
=
βγV
DS
2(2φ
F
 + V
SB
)
1/2
=
110 × 10
6
×0.4 ×1× 10
2(0.7+2)
1/2
= 134 × 10
6
V
T
= V
T0
+ γ [ ] 2φ
F
 + v
SB
− 2φ
F

V
T
= 0.7 + 0.4 [ ] 0.7 + 2.0
− 0.7 = 1.02
g
ds
= β(V
GS
− V
T
− V
DS
) = 10 ×110 × 10
6
(5 − 1.02 − 1) = 3.28 × 10
3
PChannel Device
g
m
= βV
DS
= 50 × 10
6
× 10× 1 = 500 × 10
6
g
mbs
=
βγV
DS
2(2φ
F
 + V
SB
)
1/2
=
50 × 10
6
×0.57 ×1× 10
2(0.8+2)
1/2
= 85.2 × 10
6
V
T
 = V
T0
 + γ [ ] 2φ
F
 + v
BS
− 2φ
F

V
T
 = 0.7 + 0.57 [ ] 0.8 + 2.0
− 0.8 = 1.144
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 11
g
ds
= β(V
GS
− V
T
− V
DS
) = 10 ×50 × 10
6
(5 − 1.144− 1) = 1.428 × 10
3
Problem 3.34
Find the complete smallsignal model for an nchannel transistor with the drain at 4 V,
gate at 4 V, source at 2 V, and the bulk at 0 V. Assume the model parameters from Tables
3.11, 3.12, and 3.21, and W/L = 10 µm/1 µm.
V
T
= V
T0
+ γ [ ] 2φ
F
 + v
SB
− 2φ
F

V
T
= 0.7 + 0.4 [ ] 0.7 + 2.0
− 0.7 = 1.02
I
D
=
K'W
2L
( )
v
GS
− v
T
2
(1 + λ v
DS
) =
110 × 10
6
×10
2
( ) 2  1.02
2
(1 + 0.4×2) = 570 × 10
6
g
m
= (2K'W/L)I
D

g
m
= 2×110 × 10
6
×10 × 570 × 10
6
= 1.12 × 10
3
g
mbs
= g
m
γ
2(2φ
F
 + V
SB
)
1/2
g
mbs
= 1.12 × 10
3
0.4
2(0.7+2.0)
1/2
= 136 × 10
6
g
ds
= I
D
λ
g
ds
= 570 × 10
6
× 0.04 = 22.8 × 10
9
LD =
220 × 10
12
24.7 × 10
4
≅ 89 × 10
9
L
eff
= L  2 × LD = 1 × 10
6
− 2 × 89 × 10
9
= 822 × 10
9
C
GB
= CGBO x L
eff
= 700 × 10
12
× 822 × 10
9
= 0.575 fF
C
GS
= CGSO(W
eff
) + 0.67C
ox
(W
eff
)(L
eff
)
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 12
C
GS
= 220 × 10
12
× 10 × 10
6
+ 0.67 × 24.7 × 10
4
× 822 × 10
9
× 10 × 10
6
C
GS
= 15.8 × 10
15
C
GD
= CGDO(W
eff
)
C
GD
= CGDO(W
eff
) = 220 × 10
12
× 10 × 10
6
= 2.2 × 10
15
Problem 3.35
Consider the circuit in Fig P3.35. It is a parallel connection of n mosfet transistors.
Each transistor has the same length, L, but each transistor can have a different width, W.
Derive an expression for W and L for a single transistor that replaces, and is equivalent to,
the multiple parallel transistors.
The expression for drain current in saturation is:
I
D
=
K'W
2L
( )
v
GS
− v
T
2
(1 + λ v
DS
)
For multiple transistors with the same drain, gate, and source voltage, the drain current
can be expressed simply as
I
D(i)
=
\

.


W
L
i
( )
v
GS
− v
T
2
(1 + λ v
DS
)
The drain current in each transistor is additive to the total current, thus
I
D(TOTAL)
=
( )
v
GS
− v
T
2
(1 + λ v
DS
)
∑\

.


W
L
i
Since the lengths are the same, we have
I
D(TOTAL)
=
1
L
( )
v
GS
− v
T
2
(1 + λ v
DS
)
∑
W
i
Problem 3.36
Consider the circuit in Fig P3.36. It is a series connection of n mosfet transistors. Each
transistor has the same width, W, but each transistor can have a different length, L.
Derive an expression for W and L for a single transistor that replaces, and is equivalent to,
the multiple parallel transistors. When using the simple model, you must ignore body
effect.
Error in problem statement : replace “parallel” with “series”
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 13
Figure P3.36
M1
M2
Mn
Assume that all devices are in the nonsaturation region.
Consider the case for two transistors in series as illustrated below.
M1
M2
v
1
v
2
v
G
M3
v
2
v
G
The drain current in M1 is
i
1
=
K'W
L
(v
GS
− V
T
) v
DS
−
v
2
DS
2
i
1
= β
1
(v
GS
− V
T
) v
1
−
v
2
1
2
= β
1
(v
G
− V
T
) v
1
−
v
2
1
2
i
1
= β
1
V
on
v
1
−
v
2
1
2
where
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 14
V
on
= v
G
− V
T
v
1
= V
on
− V
2
on
−
2i
1
β
1
v
2
1
= 2V
on
− 2V
on
V
2
on
−
2i
1
β
1
−
2i
1
β
1
The drain current in M2 is
i
2
= β
2
(v
G
− v
1
− V
T
)( v
2
− v
1
) −
( v
2
− v
1
)
2
2
i
2
= β
2
( V
on
− v
1
)( v
2
− v
1
) −
( v
2
− v
1
)
2
2
i
2
= β
2
V
on
v
2
− V
on
v
1
+
v
2
1
2
−
v
2
2
2
Substitue the earlier expression for v
1
and equate the drain currents (drain currents must
be equal)
i
2
=
β
1
β
2
β
1
+ β
2
V
on
v
2
−
v
2
2
2
The expression for the current in M3 is
i
3
= β
3
(v
GS
− V
T
) v
2
−
v
2
2
2
= β
3
V
on
v
2
−
v
2
2
2
The drain current in M3 must be equivalent to the drain current in M1 and M2, thus
β
3
=
β
1
β
2
β
1
+ β
2
=
\

.

 1
β
1
+
1
β
2
1
=
\

.


L
1
K'W
1
+
L
2
K'W
2
1
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 15
Since the widths are equal and the transconductances are equal
β
3
=
1
K'W
(L
1
+ L
2
)
This analysis is easily extended to address any number of transistors (repeat the analysis
with M3 and another transistor in series with it—two at a time)
L
EQUIVALENT
=
∑
0
i
L
i
Problem 3.51
Calculate the value for V
ON
for n MOS transistor in weak inversion assuming that fs and
fn can be approximated to be unity (1.0).
Assume (from Level 1 parameters):
GAMMA = 0.4
PHI = 0.7
COX = 24.7 × 10
4
F/m
2
v
SB
= 0
NFS = 7 × 10
15
(m
2
) from Table 3.41
v
on
= V
T
+ fast
where
fast =
kT
q
1 +
q × NFS
COX
+
GAMMA × f
s
(PHI + v
SB
)
1/2
+ f
n
(PHI + v
SB
)
2(PHI + v
SB
)
if
f
s
= f
n
=1
fast =
kT
q
1 +
q × NFS
COX
+
GAMMA × (PHI + v
SB
)
1/2
+ (PHI + v
SB
)
2(PHI + v
SB
)
fast = 0.0259
1 +
1.6 × 10
19
× 7 × 10
15
24.7 × 10
4
+
0.4 × (0.7 + 0)
1/2
+ (0.7 + 0)
2(0.7 + 0)
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 16
fast = 0.0259 (1 + .453 + 0.739) = 56.77 × 10
3
v
on
= V
T
+ fast =0.0259 + 56.77 × 10
3
= 82.67 × 10
3
Problem 3.52
Develop an expression for the small signal transconductance of a MOS device operating
in weak inversion using the large signal expression of Eq. (3.55).
i
D
≅
W
L
I
DO
exp
\

.


v
GS
n(kT/q)
g
m
=
∂I
D
∂V
GS
=
W
L
\

.


1
n(kT/q)
I
DO
exp
\

.


v
GS
n(kT/q)
=
I
D
n(kT/q)
Problem 3.53
Another way to approximate the transition from strong inversion to weak inversion is to
find the current at which the weakinversion transconductance and the stronginversion
transconductance are equal. Using this method and the approximation for drain current in
weak inversion (Eq. (3.55)), derive an expression for drain current at the transition
between strong and weak inversion.
g
m
=
W
L
\

.


1
n(kT/q)
I
DO
exp
\

.


v
GS
n(kT/q)
= (2K'W/L)I
D
\

.


W
L
2
\

.


1
n(kT/q)
2
I
2
DO
exp
\

.


2v
GS
n(kT/q)
= (2K'W/L)I
D
I
D
=
\

.


1
2K'
\

.


W
L
\

.


I
DO
n(kT/q)
2
exp
\

.


2v
GS
n(kT/q)
I
D
=
\

.


1
2K'
I
DO
\

.


1
n(kT/q)
2
exp
\

.


v
GS
n(kT/q)
×
\

.


W
L
I
DO
exp
\

.


v
GS
n(kT/q)
I
D
=
\

.


1
2K'
I
DO
\

.


1
n(kT/q)
2
exp
\

.


v
GS
n(kT/q)
× I
D
2K' [n(kT/q)]
2
= I
DO
exp
\

.


v
GS
n(kT/q)
=
I
D
W/L
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 17
I
D
= 2K'
W
L
[n(kT/q)]
2
Problem 3.61
Consider the circuit illustrated in Fig. P3.61. (a) Write a SPICE netlist that describes
this circuit. (b) Repeat part (a) with M2 being 2µm/1µm and it is intended that M3 and
M2 are ratio matched, 1:2.
Part (a)
Problem 3.61 (a)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Part (b)
Problem 3.61 (b)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u M=2
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Problem 3.62
Use SPICE to perform the following analyses on the circuit shown in Fig. P3.61: (a) Plot
v
OUT
versus v
IN
for the nominal parameter set shown. (b) Separately, vary K' and V
T
by
+10% and repeat part (a)—four simulations.
Parameter NChannel PChannel Units
V
T
0.7 0.7 V
K' 110 50 µA/V
2
l 0.04 0.05 V
1
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 18
v
IN
v
OUT
R =50kΩ
1
2
3
4
Figure P3.61
VDD = 5 V
M1
M2
M3
W/L = 1µ/1µ W/L = 1µ/1µ
W/L = 1µ/1µ
Problem 3.62
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
*.MODEL pch PMOS VTO=0.7 KP=50U LAMBDA=0.05
*
*.MODEL nch NMOS VTO=0.77 KP=110U LAMBDA=0.04
*.MODEL pch PMOS VTO=0.7 KP=50U LAMBDA=0.05
*
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
*.MODEL pch PMOS VTO=0.77 KP=50U LAMBDA=0.05
*
*.MODEL nch NMOS VTO=0.7 KP=121U LAMBDA=0.04
*.MODEL pch PMOS VTO=0.7 KP=50U LAMBDA=0.05
*
.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04
.MODEL pch PMOS VTO=0.7 KP=55U LAMBDA=0.05
.dc vin 0 5 .1
.probe
.end
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 19
0V 2V
4V
0V
2V
4V
K'
N
=121u
V
TN
= 0.77
K'
P
= 55u
V
TP
= 0.77
V
OUT
V
IN
Problem 3.63
Use SPICE to plot i
2
as a function of v
2
when i
1
has values of 10, 20, 30, 40, 50, 60, and
70 µA for Fig. P3.63. The maximum value of v
2
is 5 V. Use the model parameters of V
T
= 0.7 V and K' = 110 µA/V
2
and λ = 0.01 V
1
. Repeat with λ = 0.04 V
1
.
v
2
Figure P3.63
M1
M2
W/L = 10µm/2µm
i
1
i
2
W/L = 10µm/2µm
+
−
p3.63
M1 1 1 0 0 nch l = 2u w = 10u
M2 2 1 0 0 nch l = 2u w = 10u
I1 0 1 DC 0
V1 3 0 DC 0
V_I2 3 2 DC 0
.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7
*.MODEL nch NMOS VTO=0.7 KP=110U LAMBDA=0.04 GAMMA = 0.4 PHI = 0.7
.dc V1 0 5 .1 I1 10u 80u 10u
.END
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 20
Lambda = 0.01
V
2
I
2
I
2
= 10uA
I
2
= 20uA
I
2
= 30uA
I
2
= 40uA
I
2
= 50uA
I
2
= 60uA
I
2
= 70uA
10uA
40uA
60uA
80uA
1 2 3 4 5 0
Lambda = 0.04
V
2
I
2
I
1
= 10uA
I
1
= 20uA
I
1
= 30uA
I
1
= 40uA
I
1
= 50uA
I
1
= 60uA
I
1
= 70uA
10uA
40uA
60uA
80uA
1 2 3 4 5 0
Problem 3.64
Use SPICE to plot i
D
as a function of v
DS
for values of v
GS
= 1, 2, 3, 4 and 5 V for an n
channel transistor with V
T
= 1 V, K' = 110 µA/V
2
, and l = 0.04 V
1
. Show how SPICE
can be used to generate and plot these curves simultaneously as illustrated by Fig. 3.13.
p3.64
M1 2 3 0 0 nch l = 1u w = 5u
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 21
VGS 3 0 DC 0
VDS 4 0 DC 0
V_IDS 4 2 DC 0
.MODEL nch NMOS VTO=1 KP=110U LAMBDA=0.01 GAMMA = 0.4 PHI = 0.7
.dc VDS 0 5 .1 VGS 0 5 1
.END
V
DS
I
DS
2mA
4mA
1 2 3 4 5 0
0
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
Problem 3.65
Repeat Example 3.61 if the transistor of Fig. 3.65 is a PMOS having the model
parameters given in Table 3.12.
p3.65
V_IDS 5 2 DC 0
VGS 3 0 DC 0
VDS 5 0 DC 0
M1 2 3 0 0 pch l = 1u w = 5u
.MODEL pch PMOS VTO=0.7 KP=50U LAMBDA=0.051 GAMMA = 0.57 PHI = 0.8
.dc VDS 0 5 .1 VGS 0 5 1
.END
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 22
V
DS
I
DS
1mA
4 3 2 1 0 5
2mA
3mA
0mA
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
Problem 3.66
Repeat Examples 3.62 through 3.64 for the circuit of Fig. 3.62 if R1 = 200 KΩ.
0V 2V
4V
0V
2V
4V
V
IN
V
OUT
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 23
AC Analysis
20
20
40
e2 e4 e6 e8
0
Frequency
vdb(2)
e2 e4 e6 e8
0
90
Frequency
vp(2)
45
Transient Analysis
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 24
2us
6us
0V
2V
4V
4us
0V
2V
4V
0
V(2)
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 1
Chapter 4 Homework Solutions
Problem 4.11
Using SPICE, generate a set of parametric IV curves similar to Fig. 4.13 for a transistor
with a W/L = 10/1. Use model parameters from Table 3.12.
Figure P4.11
V
1
(volts)
V
1
V
G
2.5
I
V
G
= 1 V
V
G
= 2 V
V
G
= 3 V
V
G
= 4 V
V
G
= 5 V
A B
I (mA)
0.0
5.0
10.0
2.5
0.0 2.5
Problem 4.12
The circuit shown in Fig. P4.12 illustrates a singlechannel MOS resistor with a W/L of
2µm/1µm. Using Table 3.12 model parameters, calculate the smallsignal on resistance
of the MOS transistor at various values for V
S
and fill in the table below.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 2
Figure P4.12
V
S
5 Volts
I = 0.0
The equation for threshold voltage with absolute values so that it can be applied to n
channel or pchannel transistors without confusion.
V
T
= V
T0
 + γ
2φ
F
 + v
SB

− 2φ
F

r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
L
K'W(V
GS
 − V
T
)
(when V
DS
= 0)
For nchannel device,
V
T0
= 0.7
γ = 0.4
2φ
F
 = 0.7
The table below shows the value of V
GS
and V
SB
for each value of V
S
V
S
(volts) V
GS
(volts) V
SB
(volts)
0.0 5 0
1.0 4 1
2.0 3 2
3.0 2 3
4.0 1 4
5.0 0 5
Using V
S
= 0, calculate V
T
V
T
= V
T0
 + γ
2φ
F
 + v
SB

− 2φ
F
 = 0.7 + 0.4[ ] 0.7 + 0.0
− 0.7 = 0.7
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 3
Calculate r
on
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
110µ × 2(5 − 0.7
− 0)
= 1057 Ω
Repeat for V
S
= 1
V
T
 = 0.7 + 0.4[ ] 0.7 + 1.0
− 0.7 = 0.887
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
110µ × 2(4 − 0.887
− 0)
= 1460 Ω
Repeat for V
S
= 2
V
T
 = 0.7 + 0.4[ ] 0.7 + 2.0
− 0.7 = 1.023
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
110µ × 2(3 − 1.023
− 0)
= 2299 Ω
Repeat for V
S
= 3
V
T
 = 0.7 + 0.4[ ] 0.7 + 3.0
− 0.7 = 1.135
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
110µ × 2(2 − 1.135
− 0)
= 5253 Ω
Repeat for V
S
= 4
V
T
 = 0.7 + 0.4[ ] 0.7 + 4.0
− 0.7 = 1.233
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
110µ × 2(1 − 1.233
− 0)
= 19549 Ω
The negative sign means that the device is off due to the fact that V
GS
< V
T
Thus
r
ON
= infinity
Repeat for V
S
= 5
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 4
V
T
 = 0.7 + 0.4[ ] 0.7 + 5.0
− 0.7 = 1.320
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
110µ × 2(0 − 1.320
− 0)
= 3442 Ω
The negative sign means that the device is off due to the fact that V
GS
< V
T
Thus
r
ON
= infinity
Summary:
V
S
(volts) R (ohms)
0.0 1057
1.0 1460
2.0 2299
3.0 5253
4.0 infinity
5.0 infinity
Problem 4.13
The circuit shown in Fig. P4.13 illustrates a singlechannel MOS resistor with a W/L of
4µm/1µm. Using Table 3.12 model parameters, calculate the smallsignal on resistance
of the MOS transistor at various values for V
S
and fill in the table below. Note that the
most positive supply voltage is 5 volts.
Figure P4.13
V
S
I = 0.0
5 Volts
The equation for threshold voltage with absolute values so that it can be applied to n
channel or pchannel transistors without confusion.
V
T
= V
T0
 + γ
2φ
F
 + v
SB

− 2φ
F

CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 5
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
For pchannel device,
V
T0
 = 0.7
K' = 50µ
γ = 0.57
2φ
F
 = 0.8
The table below shows the value of V
GS
and V
SB
for each value of V
S
V
S
(volts) V
GS
(volts) V
BS
(volts)
0.0 0 5
1.0 1 4
2.0 2 3
3.0 3 2
4.0 4 1
5.0 5 0
Using V
S
= 5, calculate V
T
V
T
= V
T0
 + γ
2φ
F
 + v
SB

− 2φ
F
 = 0.7 + 0.57[ ] 0.8 + 0.0
− 0.8 = 0.7
Calculate r
on
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
50µ × 4(5 − 0.7
− 0)
= 1163 Ω
Repeat for V
S
= 4
V
T
 = 0.7 + 0.57[ ] 0.8 + 1.0
− 0.8 = 0.955
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
50µ × 4(4 − 0.955
− 0)
= 1642 Ω
Repeat for V
S
= 3
V
T
 = 0.7 + 0.57[ ] 0.8 + 2.0
− 0.8 = 1.144
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 6
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
50µ × 4(3 − 1.144
− 0)
= 2694 Ω
Repeat for V
S
= 2
V
T
 = 0.7 + 0.4[ ] 0.8 + 3.0
− 0.8 = 1.301
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
50µ × 4(2 − 1.301
− 0)
= 7145 Ω
Repeat for V
S
= 1
V
T
 = 0.7 + 0.57[ ] 0.8 + 4.0
− 0.8 = 1.439
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
50µ × 4(1 − 1.439
− 0)
= 11390 Ω
The negative sign means that the device is off due to the fact that V
GS
< V
T
Thus
r
ON
= infinity
Repeat for V
S
= 0
V
T
 = 0.7 + 0.57[ ] 0.8 + 5.0
− 0.8 = 1.563
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
1
50µ × 4(0 − 1.563
− 0)
= 3199 Ω
The negative sign means that the device is off due to the fact that V
GS
< V
T
Thus
r
ON
= infinity
Summary:
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 7
V
S
(volts) R (ohms)
0.0 infinity
1.0 infinity
2.0 7145
3.0 2694
4.0 1642
5.0 1163
Problem 4.14
The circuit shown in Fig. P4.3 illustrates a complementary MOS resistor with an n
channel W/L of 2µm/1µm and a pchannel W/L of 4µm/1µm. Using Table 3.12 model
parameters, calculate the smallsignal on resistance of the complementary MOS resistor
at various values for V
S
and fill in the table below. Note that the most positive supply
voltage is 5 volts.
Figure P4.3
V
S
I = 0.0
5 Volts
Summary for nchannel device from Problem 4.12:
V
S
(volts) R (ohms)
0.0 1057
1.0 1460
2.0 2299
3.0 5253
4.0 infinity
5.0 infinity
Summary for pchannel device from Problem 4.13:
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 8
V
S
(volts) R (ohms)
0.0 infinity
1.0 infinity
2.0 7145
3.0 2694
4.0 1642
5.0 1163
Table showing both and their parallel combination:
V
S
(volts) R (ohms), nchannel R (ohms), pchannel R (ohms), parallel
0.0 1057 infinity 1057
1.0 1460 infinity 1460
2.0 2299 7145 1739
3.0 5253 2694 1781
4.0 infinity 1642 1642
5.0 infinity 1163 1163
Problem 4.15
For the circuit in Figure P4.15(a) assume that there are NO capacitance parasitics
associated with M1. The voltage source v
in
is a smallsignal value whereas voltage
source V
dc
has a dc value of 3 volts. Design M1 to achieve the frequency response
shown in Figure P4.15(b).
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 9
Figure P4.4
v
in
5 Volts
2 pF v
out
V
dc
M1
0 dB
6 dB
12 dB
18 dB
24 dB
2
0
M
H
z
1
0
M
H
z
5
M
H
z
2
.
5
M
H
z
4
0
M
H
z
8
0
M
H
z
1
6
0
M
H
z
v
out
/v
in
(a)
(b)
f(3 dB) = 20 MHz, thus w = 40π M rad/s
Note that since no dc current flows through the transistor, the dc value of the drainsource
voltage is zero.
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
L
K'W(V
GS
 − V
T
)
Then
1
RC
=
K'W(V
GS
 − V
T
)
LC
= 40 π Μ rad/s
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 10
W
L
=
C × 40 π × 10
6
K'(V
GS
 − V
T
)
Calculate VT due to the back bias.
V
T
= V
T0
+ γ
\

.

2φ
f
 + v
bs

 2φ
f
 = 0.7 + 0.4 \

.

0.7 + 3.0
 0.7 = 1.135
W
L
=
40 π × 10
6
× 2 × 10
12
110 × 10
6
(2 − 1.135)
= 2.64
Problem 4.16
Using the result of Problem 4, calculate the frequency response resulting from changing
the gate voltage of M1 to 4.5 volts. Draw a Bode diagram of the resulting frequency
response.
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T

− V
DS
)
=
L
K'W(V
GS
 − V
T
)
Calculate VT due to the back bias (same as previous problem).
V
T
= V
T0
+ γ
\

.

2φ
f
 + v
bs

− 2φ
f
 = 0.7 + 0.4 \

.

0.7 + 3.0
− 0.7 = 1.135
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T
)
r
ON
=
1
110 × 10
6
× 2.64(4.5 − 3 − 1.135)
== 9434 Ω
ω(3 dB) =
1
r
ON
C
=
1
9.434 × 10
3
× 2 × 10
12
= 53 × 10
6
rad/s
f(3 dB) = 8.44 × 10
6
Hz
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 11
Figure P4.16
0 dB
6 dB
12 dB
18 dB
24 dB
2
0
M
H
z
1
0
M
H
z
5
M
H
z
2
.
5
M
H
z
4
0
M
H
z
8
0
M
H
z
1
6
0
M
H
z
v
out
/v
in
8.44 MHz
Problem 4.17
Consider the circuit shown in Fig. P4.17 Assume that the slow regime of charge
injection is valid for this circuit. Initially, the charge on C
1
is zero. Calculate v
OUT
at
time t
1
after φ
1
pulse occurs. Assume that CGS0 and CGD0 are both 5 fF. C
1
=30 fF.
You cannot ignore body effect. L = 1.0 µm and W = 5.0 µm.
Figure P4.17
C
1
v
out
M1
2.0
φ
1
t
1
φ
1
0 V
5 V
CHANGE PROBLEM:
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 12
Use model parameters from Table 3.12 and 3.21 as required
U = 5 × 10
8
The equation for the slow regime is given as
V
error
=
\

.


W · CGD0 +
C
channel
2
C
L
π U C
L
2β
+
W · CGD0
C
L
(V
S
+ V
T
− V
L
)
and
V
S
= 2.0 volts
V
L
= 0.0 volts
V
T
is calculated below
The source of the transistor is at 2.0 volts, so the threshold for the switch must be
calculated with a backgate bias of 2.0 volts.
V
T
= V
T0
+ γ
\

.

2φ
f
 + v
bs

− 2φ
f
 = 0.7 + 0.4 \

.

0.7 + 2.0
− 0.7 = 1.023
V
T
= 1.023
C
channel
= W × L × C
ox
= 5 × 10
6
× 1 × 10
6
× 24.7 × 10
4
= 12.35 × 10
15
F
V
HT
= V
H
− V
S
− V
T
= 5 − 2 − 1.023 = 1.98
Verify slow regime:
βV
2
HT
2C
L
=
110 × 10
6
× 3.91
2 × 30 × 10
15
= 7.17 × 10
9
>> 5 × 10
8
thus slow regime
V
error
=
\

.


W · CGD0 +
C
channel
2
C
L
π U C
L
2β
+
W · CGD0
C
L
(V
S
+ V
T
− V
L
)
V
error
=
\

.


5 × 10
6
× 220 × 10
12
+
12.35 × 10
15
2
30 × 10
15
×
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 13
×
π × 5 × 10
8
× 30 × 10
15
2×110 × 10
6
+
5 × 10
6
· 220 × 10
12
30 × 10
15
(2 + 1.023 − 0 ) = 0.223
V
out
(t1) = 2.0 − V
error
= 2.0 − 0.223 = 1.777
Problem 4.18
In Problem 4.17, how long must φ
1
remain high for C
1
to charge up to 99% of the
desired final value (2.0 volts)?
r
ON
=
1
∂I
D
/∂V
DS
=
L
K'W(V
GS
 − V
T
)
r
ON
=
1
5 × 110 × 10
6
× (3 − 1.135)
= 972.3 Ω
r
ON
C
1
= 972.3 × 30 × 10
15
= 29.2 ps
v
O
(t) C
1
= 2 × ( ) 1 − e
t/RC
= 0.99 × 2.0
e
t/RC
) = 0.01
t = −RC ln(0.01) = 134.3 ps
Problem 4.19
In Problem 4.17, the charge feedthrough could be reduced by reducing the size of M1.
What impact does reducing the size (W/L) of M1 have on the requirements on the width
of the φ
1
pulse width?
The width of φ
1
must increase since a decrease in size (and thus feedthrough) increases
resistance and thus the time required to charge the capacitor to the desired final value.
Problem 4.110
Considering charge feedthrough due to slow regime only, will reducing the magnitude of
the φ
1
pulse impact the resulting charge feedthrough? What impact does reducing the
magnitude of the φ
1
pulse have on the accuracy of the voltage transfer to the output?
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 14
Reducing the magnitude does not effect the result of feedthrough in the slow regime
because all of the charge except residual channel charge (at the point where the device
turns off) returns to the voltage source. Decreasing the magnitude does effect the
accuracy because the time required to charge the capacitor is increased due to higher
resistance when the device is on.
Problem 4.111
Repeat Example 4.11 with the following conditions. Calculate the effect of charge
feedthrough on the circuit shown in Fig. 4.19 where V
s
= 1.5 volts, C
L
= 150 fF, W/L =
1.6µm/0.8µm, and V
G
is given for two cases illustrated below. The fall time is 0.1ns
instead of 8ns.
Case 1: 0.1ns fall time
V
T
= V
T0
+ γ
\

.

2φ
f
 + v
bs

− 2φ
f
 = 0.7 + 0.4 \

.

0.7 + 1.5
− 0.7 = 0.959
V
HT
= V
H
− V
S
− V
T
= 5 − 1.5 − 0.959 = 2.541
U =
V
H
t
=
5
0.1 × 10
9
= 50 × 10
9
βV
2
HT
2C
L
=
2×110 × 10
6
× 2.541
2
2 × 150 × 10
15
= 4.735 × 10
9
<< 50 × 10
9
thus fast mode
C
channel
= W × L × C
ox
= 1.6 × 10
6
× 0.8 × 10
6
× 24.7 × 10
4
= 3.162 × 10
15
F
V
error
=
\

.


W·CGD0 +
C
channel
2
C
L
\

.



V
HT
−
β V
3
HT
6U C
L
+
W·CGD0
C
L
(V
S
+ V
T
− V
L
)
V
error
=
\

.



1.6 × 10
6
× 220 × 10
12
+
3.162 × 10
15
2
150 × 10
15
\

.



2.541 −
220 × 10
6
× 2.541
3
6×50 ×10
9
×150 × 10
15
+
+
1.6 × 10
6
×·220 × 10
12
150 × 10
15
(1.5 + 0.96 − 0 )
V
error
= (12.89 × 10
3
) ( ) 2.46 + 1.267 × 10
3
= 32.98 × 10
3
V
out
(t1) = 2.0 − V
error
= 2.0 − 32.98 × 10
3
= 1.967
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 15
Case 2: 8ns fall time
V
T
= V
T0
+ γ
\

.

2φ
f
 + v
bs

 2φ
f
 = 0.7 + 0.4 \

.

0.7 + 1.5
 0.7 = 0.959
V
HT
= V
H
− V
S
− V
T
= 5  1.5  0.959 = 2.541
v
G
= V
H
− Ut
U =
V
H
t
=
5
8 × 10
9
= 625 × 10
6
βV
2
HT
2C
L
=
2×110 × 10
6
× 6.457
2 × 150 × 10
15
= 4.735 × 10
9
>> 625 × 10
6
thus slow regime
V
error
=
\

.


W · CGD0 +
C
channel
2
C
L
π U C
L
2β
+
W · CGD0
C
L
(V
S
+ V
T
− V
L
)
and
V
S
= 1.5 volts
V
L
= 0.0 volts
C
channel
= W × L × C
ox
= 1.6 × 10
6
× 0.8 × 10
6
× 24.7 × 10
4
= 3.162 × 10
15
F
V
error
=
\

.


W · CGD0 +
C
channel
2
C
L
π U C
L
2β
+
W · CGD0
C
L
(V
S
+ V
T
− V
L
)
V
error
=
\

.


1.6 × 10
6
× 220 × 10
12
+
3.162 × 10
15
2
150 × 10
15
×
Error!
V
out
(t1) = 2.0 − V
error
= 2.0 − 0.0163 = 1.984
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 16
Problem 4.112
Figure P4.112 illustrates a circuit that contains a chargecancellation scheme. Design
the size of M2 to minimize the effects of charge feedthrough. Assume slow regime.
Figure P4.112
C
1
v
out
M1
2.0
φ
1
t
1
φ
1
0 V
5 V
M2
φ
1
When U is small, the expression for the charge feedthrough due to M1 in the slow regime
can be approximated as
V
error
=
\

.


W · CGD0 +
C
channel
2
C
L
π U C
L
2β
+
W · CGD0
C
L
(V
S
+ V
T
− V
L
)
V
error
≅
W · CGD0
C
L
(V
S
+ V
T
− V
L
)
Because M2 is driven by the inversion of φ
1
, charge is injected in the opposite direction
from that of M1. The charge injected is due to the overlap capacitance and due to the
channel capacitance. The overlap capacitance from the drain or source is simply
C
overlap
= W · CGD0
Because both the drain and the source are involved, the charge injected from both must
be added.
Capacitance due to the channel once M2 channel inverts is simply
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 17
C
channel
= W · L · C
ox
Consider the voltage on C
1
due to charge injected from the overlap and the channel
separately.
The error voltage due to overlap is approximated to be
V
error_overlap
≅
2 · W · CGD0
C
L
(V
S
+ V
T
− V
L
)
Notice the factor of “2” to account for the overlap from the drain and the source.
The error voltage due to the channel is approximated to be
V
error_channel
≅
C
channel
C
L
(5 − V
S
− V
T
)
where the “5” comes from the maximum value of φ
1
.
If V
L
is zero, then the total error voltage due to M2 alone is approximately
V
error_M2
≅
2 · W
2
· CGD0
C
L
(V
S
+ V
T
) +
C
channel
C
L
(5 − V
S
− V
T
)
Since the error voltage due to M2 is in the opposite direction to that due to M1 then to
minimize the overall effect due to charge injection, the error due to M1 and M2 should be
made equal. Therefore
W
1
· CGD0
C
L
(V
S
+ V
T
) =
2 · W
2
· CGD0
C
L
(V
S
+ V
T
) +
C
channel
C
L
(5 − V
S
− V
T
)
(W
1
· CGD0) (V
S
+ V
T
) = (2 · W
2
· CGD0) (V
S
+ V
T
) + C
channel_M2
(5 − V
S
− V
T
)
(W
1
· CGD0) (V
S
+ V
T
) = (2 · W
2
· CGD0) (V
S
+ V
T
) + W
2
L
2
C
OX
(5 − V
S
− V
T
)
W
1
= 2 · W
2
+
W
2
L
2
C
OX
(5 − V
S
− V
T
)
CGD0 (V
S
+ V
T
)
W
1
= W
2
\

.


2 +
L
2
C
OX
(5 − V
S
− V
T
)
CGD0 (V
S
+ V
T
)
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 18
W
2
= W
1
\

.


2 +
L
2
C
OX
(5 − V
S
− V
T
)
CGD0 (V
S
+ V
T
)
1
Design L
2
to be the minimum allowed device length and calculate W
2
.
Problem 4.31
Figure P4.31 illustrates a sourcedegenerated current source. Using Table 3.12 model
parameters calculate the output resistance at the given current bias.
Figure P4.31
10 µA
v
OUT
+

V
GG
100K
2/1
The smallsignal model of this circuit is shown below
g
m
v
gs
g
mbs
v
bs
r
ds
v
s
+

v
out
+

r
i
out
First calculate dc terminal conditions.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 19
I
D
= 10 µA
V
S
= I
D
× R = 10 × 10
6
× 100 × 10
3
= 1 volt
V
S
= V
SB
r
out
=
v
out
i
out
= r + r
ds
+ [(g
m
+ g
mbs
)r
ds
]r ≅ (g
m
r
ds
)r
g
m
≅ (2K'W/L)I
D
 = 2× 110×10
6
×2/1 × 10×10
6
= 66.3 ×10
6
g
mbs
= g
m
γ
2(2φ
F
 + V
SB
)
1/2
= 66.3×10
6
0.4
2(0.7 + 1)
1/2
= 10.17×10
6
g
ds
≅ I
D
λ = 10×10
6
× 0.04 = 400×10
9
r
ds
=
1
g
ds
= 2.5×10
6
thus
r
out
= 100 × 10
3
+ 2.5×10
6
+ [(66.3 ×10
6
+ 10.17×10
6
) 2.5×10
6
] 100 × 10
3
= 21.7×10
6
r
out
= 21.7×10
6
Problem 4.32
Calculate the minimum output voltage required to keep device in saturation in Problem
4.31.
The minimum voltage across drain and source while remaining in saturation is V
ON
V
ON
=
2i
D
β
=
2 × 10 ×10
6
2 × 110 ×10
6
=
10
110
= 0.302
The minimum drain voltage is
V
D
(min) = V
S
(min) + V
ON
= 1 + 0.302 = 1.302
Problem 4.33
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 20
Using the cascode circuit shown in Fig. P4.33, design the W/L of M1 to achieve the
same output resistance as the circuit in Fig. P4.31. Ignore body effect.
Figure P4.33
v
OUT
+

V
GC
M1
M2
10 µA
2/1
r
DS1
=
1
g
m1
1
g
m
= 100 kΩ
g
m1
=
1
100 kΩ
≅ 2K'(W/L)
1
I
D
= 2× 110×10
6
× 10×10
6
(W/L)
1
\

.


W
L
1
=
\

.

 10
5
2× 110×10
6
× 10×10
6
2
=
1
22
From the previous problem,
g
m2
= 66.3 ×10
6
r
ds2
= 2.5×10
6
Note that the terminal conditions of M2 must change in order to support the larger gate
voltage required on M1. This will be addressed in the next problem.
Problem 4.34
Calculate the minimum output voltage required to keep device in saturation in Problem
4.33. Compare this result with that of Problem 4.32. Which circuit is a better choice in
most cases?
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 21
First calculate the gate voltage of M1
V
GS1
=
2I
D
K'(W/L)
+ V
T
=
20 µ
110 µ (1/22)
+ 0.7 = 2.7
From Problem 4.32, V
ON2
= 0.302
Therefore, the minimum output voltage to keep devices in saturation is
V
out
(min) = V
GS1
+ V
ON2
= 2.7 + .302 = 3.02
In for the circuit in problem 4.32, the minimum output voltage is lower than the circuit
in 4.33 and is thus generally a better choice.
Problem 4.35
Calculate the output resistance and the minimum output voltage, while maintaining all
devices in saturation, for the circuit shown in Fig. P4.35. Assume that I
OUT
is actually
10µA. Simulate this circuit using SPICE LEVEL 3 model (Table 3.41) and determine
the actual output current, I
OUT
. Use Table 3.12 for device model information.
Figure P4.35
v
OUT
+

M1
M2
M3
M4
5/1 5/1
5/1
5/1
10 µA
i
OUT
First calculate node voltages and currents.
Assume a near perfect current mirror so that the current in all devices is 10 µA.
Calculate node voltages.
V
GS3
= V
G3
=
2i
D
β
+ V
T
=
2 × 10 ×10
6
5 × 110 ×10
6
+ 0.7 =
20
550
+ 0.7 = 0.891
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 22
V
SB2
= V
G3
= 0.891
V
DS1
= V
G3
+ V
GS4
− V
GS2
because all devices are matched.
g
m2
= g
m4
≅ (2K'W/L)I
D
 = 2× 110×10
6
×5/1 × 10×10
6
= 104.9 ×10
6
g
mbs2
=g
mbs4
= g
m2
γ
2(2φ
F
 + V
SB
)
1/2
= 104.9 ×10
6
0.4
2(0.7 + 0.891)
1/2
= 16.63×10
6
r
out
=
v
out
i
out
= r
ds1
+ r
ds2
+ [(g
m2
+ g
mbs2
)r
ds2
] r
ds1
g
ds1
= g
ds2
≅ I
D
λ = 10×10
6
× 0.04 = 400×10
9
r
ds1
=r
ds2
=
1
g
ds
= 2.5×10
6
r
out
= r
ds1
+ r
ds2
+ [(g
m2
+ g
mbs2
)r
ds2
] r
ds1
= 2.5×10
6
+ 2.5×10
6
r
out
= 2.5×10
6
+ 2.5×10
6
+ [(104.9 ×10
6
+ 16.63×10
6
) 2.5×10
6
] 2.5×10
6
r
out
= 764×10
6
Spice Simulation
Spice simulation circuit
VOUT
M1
M2
M3
M4
5/1 5/1
5/1
5/1
10 µA
i
OUT
VPLUS
IBIAS
1
2
3
4
5
Problem 4.35
M4 4 4 3 0 nch w=5u l=1u
M3 3 3 0 0 nch w=5u l=1u
M2 2 4 1 0 nch w=5u l=1u
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 23
m1 1 3 0 0 nch w=5u l=1u
ibias 5 4 10u
vplus 5 0 5
vout 2 0 3
.op
.model nch NMOS
+ LEVEL = 3
+ VTO = 0.70
+ UO = 660
+ TOX = 1.40E08
+ NSUB = 3E+16
+ XJ = 2.0e7
+ LD = 1.6E08
+ NFS = 7e+11
+ VMAX = 1.8e5
+ DELTA = 2.40
+ ETA = 0.1
+ KAPPA = 0.15
+ THETA = 0.1
+ CGDO = 2.20E10
+ CGSO = 2.20E10
+ CGBO = 7.00E10
+ MJ = 0.50
+ CJSW = 3.50E10
+ MJSW = 0.38
.model pch PMOS
+ LEVEL = 3
+ VTO = 0.70
+ UO = 210
+ TOX = 1.40E08
+ NSUB = 6.00e16
+ XJ = 2.0e7
+ LD = 1.5E08
+ NFS = 6E+11
+ VMAX = 2.00e5
+ DELTA = 1.25
+ ETA = 0.1
+ KAPPA = 2.5
+ THETA = 0.1
+ CGDO = 2.20E10
+ CGSO = 2.20E10
+ CGBO = 7.00E10
+ MJ = 0.50
.end
DC Operating Point Analysis, 27 deg C
Fri Aug 30 23:00:34 2002

>>> i(vout) = 1.0157e005
i(vplus) = 1.0000e005
v(0) = 0.0000e+000
v(1) = 8.5259e001
v(2) = 3.0000e+000
v(3) = 8.1511e001
v(4) = 1.7609e+000
v(5) = 5.0000e+000
Problem 4.36
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 24
Calculate the output resistance, and the minimum output voltage, while maintaining all
devices in saturation, for the circuit shown in Fig. P4.36. Assume that I
OUT
is actually
10µA. Simulate this circuit using SPICE Level 3 model (Table 3.41) and determine the
actual output current, I
OUT
. Use Table 3.12 for device model information.
Figure P4.36
v
OUT
+

M1
M2
M3
M4
1/1
4/1 4/1
4/1
10 µA 10 µA
i
OUT
First calculate node voltages and currents.
Assume a near perfect current mirror so that the current in all devices is 10 microamps.
Calculate node voltages.
V
GS4
= V
G4
=
2i
D
β
+ V
T
=
2 × 10 ×10
6
1 × 110 ×10
6
+ 0.7 =
20
110
+ 0.7 = 1.126
V
GS3
= V
G3
=
2i
D
β
+ V
T
=
2 × 10 ×10
6
4 × 110 ×10
6
+ 0.7 =
20
440
+ 0.7 = 0.913

VGS of M2 must be solved taking into account the backbias voltage and its effect on
threshold voltage. The following equations relate to M2 terminals (subscripts dropped
for simplicity)
V
GS
= V
G
− V
S
=
2i
D
β
+ V
T0
+ γ
\

.

2φ
f
 + v
SB
− 2φ
f

Noting that the bulk terminal is ground we get
V
G
− V
S
=
2i
D
β
+ V
T0
+ γ
\

.

2φ
f
 + v
S
−  2φ
f

CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 25
V
G
− V
S
−
2i
D
β
− V
T0
+ γ 2φ
f
 = γ
\

.

2φ
f
 + v
S
V
G
−
2i
D
β
− V
T0
+ γ 2φ
f
 − V
S
= γ
\

.

2φ
f
 + v
S
A − V
S
= γ
\

.

2φ
f
 + v
S
where
A = V
G
−
2i
D
β
− V
T0
+ γ 2φ
f

(A − V
S
)
2
= γ
2
\

.

2φ
f
 + v
S
A
2
− 2AV
S
+ V
2
S
= γ
2
\

.

2φ
f
 + v
S
V
2
S
− V
S
( 2A + γ
2
) + A
2
− γ
2
\

.

2φ
f

= 0
Now solving numerically:
A = V
G
−
2i
D
β
− V
T0
+ γ 2φ
f
 = 1.126 −
20
440
− 0.7 + 0.4 0.7 = 0.5475
V
2
S
− V
S
[2(0.5475) + 0.4
2
] + 0.5475
2
− 0.4
2
( ) 0.7
= 0
V
2
S
− V
S
(1.255) + 0.1877 = 0
V
S
= 0.1736
V
ON
=
2i
D
β
=
20
440
= 0.2132
V
OUT
(min)
= V
ON
+ V
S
= 0.2132 + 0.1736 = 0.3868
Small signal calculation of output resistance:
g
m1
= g
m2
≅ (2K'W/L)I
D
 = 2× 110×10
6
×4/1 × 10×10
6
= 93.81 ×10
6
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 26
g
mbs2
= g
m2
γ
2(2φ
F
 + V
SB
)
1/2
= 93.81 ×10
6
0.4
2(0.7 + 0.1736)
1/2
= 20.07×10
6
r
out
=
v
out
i
out
= r
ds1
+ r
ds2
+ [(g
m2
+ g
mbs2
)r
ds2
] r
ds1
g
ds1
= g
ds2
≅ I
D
λ = 10×10
6
× 0.04 = 400×10
9
r
ds1
=r
ds2
=
1
g
ds
= 2.5×10
6
r
out
= r
ds1
+ r
ds2
+ [(g
m2
+ g
mbs2
)r
ds2
] r
ds1
= 2.5×10
6
+ 2.5×10
6
r
out
= 2.5×10
6
+ 2.5×10
6
+ [(93.81 ×10
6
+ 20.07×10
6
) 2.5×10
6
] 2.5×10
6
r
out
= 717×10
6
Spice Simulation
M1
M2
M3
M4
1/1
4/1 4/1
4/1
10 µA 10 µA
i
OUT
Spice simulation circuit
VOUT
VPLUS
IBIAS2
1
2
3
4
5
IBIAS1
Problem 4.36
M4 3 3 0 0 nch w=1u l=1u
M3 4 4 0 0 nch w=4u l=1u
M2 2 3 1 0 nch w=4u l=1u
m1 1 4 0 0 nch w=4u l=1u
ibias1 5 3 10u
ibias2 5 4 10u
vplus 5 0 5
vout 2 0 3
.op
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 27
.model nch NMOS
+ LEVEL = 3
+ VTO = 0.70
+ UO = 660
+ TOX = 1.40E08
+ NSUB = 3E+16
+ XJ = 2.0e7
+ LD = 1.6E08
+ NFS = 7e+11
+ VMAX = 1.8e5
+ DELTA = 2.40
+ ETA = 0.1
+ KAPPA = 0.15
+ THETA = 0.1
+ CGDO = 2.20E10
+ CGSO = 2.20E10
+ CGBO = 7.00E10
+ MJ = 0.50
+ CJSW = 3.50E10
+ MJSW = 0.38
.model pch PMOS
+ LEVEL = 3
+ VTO = 0.70
+ UO = 210
+ TOX = 1.40E08
+ NSUB = 6.00e16
+ XJ = 2.0e7
+ LD = 1.5E08
+ NFS = 6E+11
+ VMAX = 2.00e5
+ DELTA = 1.25
+ ETA = 0.1
+ KAPPA = 2.5
+ THETA = 0.1
+ CGDO = 2.20E10
+ CGSO = 2.20E10
+ CGBO = 7.00E10
+ MJ = 0.50
.end
Problem 4.36
DC Operating Point Analysis, 27 deg C
Mon Sep 02 16:24:37 2002

>>> i(vout) = 8.1815e006
i(vplus) = 2.0000e005
v(0) = 0.0000e+000
v(1) = 3.2664e001
v(2) = 3.0000e+000
v(3) = 1.1450e+000
v(4) = 8.4156e001
v(5) = 5.0000e+000
Problem 4.37
Design M3 and M4 of Fig. P4.37 so that the output characteristics are identical to the
circuit shown in Fig. P4.36. It is desired that I
OUT
is ideally 10µA.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 28
Figure P4.37
v
OUT
+

M1
M2
M3
M4
4/1
4/1
5µA 5µA
i
OUT
By comparison with the circuit in P4.36, the output transistors are identical but the bias
currents are halved. In order to achieve the same gate voltages on M1 and M2, the W/L
of M3 and M4 must be half of those in Fig P4.36. This is illustrated in the following
equations.
V
GS
=
2i
D
K'(W/L)
+ V
T
V
GS
(5µA) =
2(5µA)
K'(W/L)
5µA
+ V
T
= V
GS
(10µA) =
2(10µA)
K'(W/L)
10µA
+ V
T
2(5µA)
K'(W/L)
5µA
=
2(10µA)
K'(W/L)
10µA
5µA
(W/L)
5µA
=
10µA
(W/L)
10µA
(W/L)
10µA
(W/L)
5µA
=
10µA
5µA
= 2
(W/L)
10µA
= 2(W/L)
5µA
Thus for Fig. 4.37
(W/L)
4
= 1/2
(W/L)
3
= 2/1
Problem 4.38
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 29
For the circuit shown in Fig. P4.38, determine I
OUT
by simulating it using SPICE Level
3 model (Table 3.41). Use Table 3.12 for device model information. Compare the
results with the SPICE results from Problem 4.36.
Figure P4.38
v
OUT
+

M1
M2
M3
M4
1/1
4/1
10 µA 10 µA
4/1
4/1
4/1
i
OUT
M1
M2
M3
M4
1/1
4/1 4/1
4/1
10 µA 10 µA
i
OUT
Spice simulation circuit
VOUT
VPLUS
IBIAS2
1
2
3
4
5
IBIAS1
6
M5
Problem 4.38
M5 4 3 6 0 nch w=4u l=1u
M4 3 3 0 0 nch w=1u l=1u
M3 6 4 0 0 nch w=4u l=1u
M2 2 3 1 0 nch w=4u l=1u
m1 1 4 0 0 nch w=4u l=1u
ibias1 5 3 10u
ibias2 5 4 10u
vplus 5 0 5
vout 2 0 3
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 30
.op
.model nch NMOS
+ LEVEL = 3
+ VTO = 0.70
+ UO = 660
+ TOX = 1.40E08
+ NSUB = 3E+16
+ XJ = 2.0e7
+ LD = 1.6E08
+ NFS = 7e+11
+ VMAX = 1.8e5
+ DELTA = 2.40
+ ETA = 0.1
+ KAPPA = 0.15
+ THETA = 0.1
+ CGDO = 2.20E10
+ CGSO = 2.20E10
+ CGBO = 7.00E10
+ MJ = 0.50
+ CJSW = 3.50E10
+ MJSW = 0.38
.model pch PMOS
+ LEVEL = 3
+ VTO = 0.70
+ UO = 210
+ TOX = 1.40E08
+ NSUB = 6.00e16
+ XJ = 2.0e7
+ LD = 1.5E08
+ NFS = 6E+11
+ VMAX = 2.00e5
+ DELTA = 1.25
+ ETA = 0.1
+ KAPPA = 2.5
+ THETA = 0.1
+ CGDO = 2.20E10
+ CGSO = 2.20E10
+ CGBO = 7.00E10
+ MJ = 0.50
.end
Problem 4.38
DC Operating Point Analysis, 27 deg C
Mon Sep 02 18:01:39 2002

i(vout) = 1.0233e005
i(vplus) = 2.0000e005
v(0) = 0.0000e+000
v(1) = 3.0942e001
v(2) = 3.0000e+000
v(3) = 1.1450e+000
v(4) = 8.6342e001
v(5) = 5.0000e+000
v(6) = 2.4681e001
Notice that the output current is more accurate than that simulated in problem 4.36. This
is because M3 and M1 have more closely matched terminal conditions.
Problem 4.41
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 31
Consider the simple current mirror illustrated in Fig. P4.20. Over process, the absolute
variations of physical parameters are as follows:
Width variation +/ 5%
Length variation +/ 5%
K’ variation +/ 5%
V
T
variation +/ 5mV
Assuming that the drain voltages are identical, what is the minimum and maximum
output current measured over the process variations given above.
Figure P4.41
i
O
M1 M2
+

+

+

V
DS1
V
DS2
V
GS
20 µA
3/1 3/1
i
D
= K'
W
L
(v
GS
− V
T
)
2
and
v
GS
=
2i
D
K'(W/L)
+ V
T
Thus, combining these expressions for the circuit in Fig. P4.41,
i
O
= K'
2
\

.


W
L
2
(v
GS2
− V
T2
)
2
i
O
= K'
2
\

.


W
L
2
\

.


2×20×10
6
K'
1
(W/L)
1
+ V
T1
− V
T2
2
Minimum and Maximum occurs under the following conditions
K'
1
K'
2
(W/L)
1
(W/L)
2
V
T1
V
T2
i
O
(min) Max Min Max Min Min Max
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 32
i
O
(max) Min Max Min Max Max Min
Substituting in the expression for drain current yields:
K'
1
K'
2
(W/L)
1
(W/L)
2
V
T1
V
T2
27.82 µ 115.5 µ 104.5 µ 3.316 2.714 0.695 0.705
56.93 µ 104.5 µ 115.5 µ 2.714 3.316 0.705 0.695
Problem 4.42
Consider the circuit in Fig. P4.21 where a single MOS diode (M2) drives two current
mirrors (M1 and M3). A signal (v
sig
) is present at the drain of M3 (due to other circuitry
not shown). What is the effect of v
sig
on the signal at the drain of M1, v
OUT
? Derive
the transfer function v
sig
(s)/ v
OUT
(s). You must take into account the gatedrain
capacitance of M3 but you can ignore the gatedrain capacitance of M1. Given that
I
BIAS
=10µA, W/L of all transistors is 2µm/1µm, and using the data from Table 3.12 and
Table 3.21, calculate v
OUT
for v
sig
=100mV at 1MHz.
Figure P4.42
v
OUT
+

M1
I
BIAS
M2 M3
v
sig
I
BIAS
I
BIAS
The smallsignal model for Fig. 4.42 is
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 33
v
sig
g
m3
v
gs3
r
3
C
gd3
1/g
m2
C
gs1
+C
gs2
g
m1
v
g1
r
1
v
g1
v
sig
C
gd3
Z
g
m1
v
g1
r
1
v
g1
v
OUT
v
OUT
v
g1
= v
sig
\

.


Z
Z + 1/sC
gd3
v
OUT
= g
m1
r
1
v
g1
= g
m1
r
1
\

.


Z v
sig
Z + 1/sC
gd3
v
OUT
v
sig
= g
m1
r
1
\

.


s C
gd3
s (C
gd3
+C
gs1
+C
gs2
) + g
m1
¦
¦
¦
¦
¦
¦ v
OUT
(ω)
v
sig
(ω)
= g
m1
r
1
\

.


 ω C
gd3
[ω (C
gd3
+C
gs1
+C
gs2
)]
2
+ g
2
m1
The transfer function has the following poles and zeros.
ω
p
=
\

.


g
m1
C
gd3
+ C
gs1
+ C
gs2
ω
z
=
g
m1
C
gd3
r
1
=
1
λi
d
=
1
0.04 × 10 × 10
6
= 2.5 × 10
6
g
m1
= 2K'(W/L)i
D
= 2 × 110 × 10
6
× 2× 10 × 10
6
= 66.33 × 10
6
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 34
C
gs1
=
2
3
C
ox
× W × L + CGSO × W = 3.29 fF + 0.44 fF = 3.73 fF
C
gs1
= C
gs2
C
gd3
= CGSO × W = 0.44 fF
Substituting numerical values yields:
¦
¦
¦
¦
¦
¦ v
OUT
(ω)
v
sig
(ω)
= 66.33 × 10
6
× 2.5 × 10
6
×
×
\

.

 6.28 × 10
6
× 0.44 × 10
15
[6.28 × 10
6
(0.44 × 10
15
+ 3.73 × 10
15
+ 3.73 × 10
15
)]
2
+ (66.33 × 10
6
)
2
¦
¦
¦
¦
¦
¦ v
OUT
(ω)
v
sig
(ω)
= 6.91 × 10
3
at ω = 6.28 Mrps
For v
sig
= 100 mV
v
OUT
= v
sig
× 6.91 × 10
3
= 100 × 10
3
× 6.91 × 10
3
= 691 µV
Problem 4.51
Show that the sensitivity of the reference circuit shown in Fig. 4.52(b) is unity.
β
P
2
V
DD
− V
REF
−
 
V
TP
2
=
β
N
2
V
REF
− V
TN
2
\

.

 β
P
β
N
1/2
\

.

V
DD
− V
REF
−
 
V
TP
=
\

.

V
REF
− V
TN
V
REF
=
\

.


β
P
β
N
1/2
\

.

V
DD
−
 
V
TP
+ V
TN
1 +
\

.


β
P
β
N
1/2
When:
β
P
= β
N
,
 
V
TP
= V
TN
then
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 35
V
REF
=
V
DD
2
∂V
REF
∂ V
DD
= ??
Use a smallsignal model to simplify analysis.
Figure P4.51
V
REF
+

V
DD
g
mp
g
mn
∂V
REF
∂V
DD
=
v
REF
v
DD
∂V
REF
∂V
DD
=
1/g
mN
1/g
mN
+ 1/g
mP
=
g
mP
g
mN
+ g
mP
∂V
REF
∂V
DD
=
2β
P
I
D
2β
P
I
D
+ 2β
N
I
D
=
I
D
I
D
+ I
D
= 1/2
V
REF
S
V
DD
=
\

.

 ∂V
REF
∂V
DD
\

.


V
DD
V
REF
=
\

.


1/2
1/2
= 1
Problem 4.52
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 36
Fig P4.52 illustrates a reference circuit that provides an interesting reference voltage
output. Derive a symbolic expression fo V
REF
.
M1 M2
M3
M4
1/1
4/1
4/1
4/1
Fig. P4.52
V
REF
I
5 volts
V
GS1
+ V
GS3
− V
GS4
= V
REF
V
REF
= V
ON1
+ V
T1
+ V
ON3
+ V
T3
− V
ON4
− V
T4
V
T4
= V
T3
V
ON1
= V
ON3
V
ON4
= 2V
ON3
V
REF
= 2V
ON1
+ V
T1
+ V
T3
− 2V
ON1
− V
T3
= V
T1
V
REF
= V
T1
Problem 4.53
Figure P4.53 illustrates a current reference. The W/L of M1 and M2 is 100/1. The
resistor is made from nwell and its nominal value is 400kΩ at 25 °C. Using Table 3.12
and an nwell resistor with a sheet resistivity of 1kΩ/sq. ± 40% and temperature
coefficient of 8000 ppm/°C, calculate the total variation of output current seen over
process, temperature of 0 to 70 °C, and supply voltage variation of ± 10%. Assume that
the temperature coefficient of the threshold voltage is –2.3 mV/°C.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 37
M1 M2
Fig. P4.53
I
out
R
5 volts
I
REF
=
V
DD
−
2I
REF
β
+ V
T
R
1
R
2I
REF
β
=
V
DD
− V
T
R
− I
REF
Define V = V
DD
− V
T
2I
REF
β
= (V − I
REF
R)
2
I
2
REF
R
2
− 2I
REF
\

.


VR +
1
β
+ V
2
= 0
I
2
REF
− 2I
REF
\

.


V
R
+
1
βR
2
+
V
2
R
2
= 0
I
REF
=
V
R
+
1
βR
2
±
1
R
2V
βR
+
1
β
2
R
2
I
REF
=
V
DD
− V
T
R
+
1
βR
2
±
1
R
2(V
DD
− V
T
)
βR
+
1
β
2
R
2
R
min
(25°C) = 500kΩ × (1 − 0.4) = 300kΩ
R
max
(25°C) = 500kΩ × (1 + 0.4) = 700kΩ
R(T) = R(T
0
) × ( ) 1 + TC×∆T
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 38
R
min
(0 °C) = R
min
(25 C) × ( ) 1 + 8000×10
6
× 25 = 300 × 0.8 = 240kΩ
R
max
(70 °C) = R
max
(25 C) × ( ) 1 + 8000×10
6
× 45 = 700 × 1.36 = 952kΩ
V
T(min)
(25°C) = 0.7 − 0.15 = 0.55
V
T(max)
(25°C) = 0.7 + 0.15 = 0.85
V
T(min)
(70°C) = 0.55 − 45 × 0.0023 = 0.4465
V
T(max)
(0°C) = 0.85 + 25 × 0.0023 = 0.9075
K'
(max)
(25°C) = 110 × 10
6
× 1.1 = 121 × 10
6
K'
(min)
(25°C) = 110 × 10
6
× 0.9 = 99 × 10
6
K' (T) = K' (T
0
) ×
\

.


T
T
0
1.5
K'
(min)
(70°C) = 99 × 10
6
×
\

.


343
298
1.5
= 80.17 × 10
6
K'
(max)
(0°C) = 121 × 10
6
×
\

.


273
298
1.5
= 138 × 10
6
Minimum and Maximum occurs under the following conditions
K' V
T
V
DD
R
I
REF
(min) Max Max Min Max
I
REF
(max) Min Min Max Min
K' V
T
V
DD
R
I
REF
(min)
80.17 × 10
6
0.9075 4.5 952 K
I
REF
(max)
138 × 10
6
0.4465 5.5 240 K
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 39
Plugging in these minimums and maximums yields the following over process and
temperature:
I
REF
(min) = 3.81 × 10
6
I
REF
(max) = 21.3 × 10
6
Problem 4.54
Figure 4.54 illustrates a current reference circuit. Assume that M3 and M4 are identical
in size. The sizes of M1 and M2 are different. Derive a symbolic expression for the
output current I
out
.
M1
M2
M4
Fig. P4.54
V
DD
M5
I
out
M3
R
Assume that M3 and M4 make a perfect current mirror, as does M2 and M5.
V
GS2
− V
GS1
+ IR = 0
V
T1
+ V
ON1
− V
T2
− V
ON2
= IR
IR = V
ON1
− V
ON2
=
2i
D
K'(W/L)
1
−
2i
D
K'(W/L)
2
IR =
2i
D
K'
\

.


1
(W/L)
1
−
1
(W/L)
2
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 40
I =
1
R
2i
D
K'
\

.


1
(W/L)
1
−
1
(W/L)
2
Problem 4.55
Find the smallsignal output resistance of Fig. 4.53(b) and Fig. 4.54(b).
Figure 4.53(b)
V
REF
+

V
DD
R
R
1
R
2
I
Figure 4.54(b)
V
REF
+

V
DD
R
R
1
R
2
I
V
π
+

r
π
R
2
R
1
R
g
m
V
π r
ο
V
T
I
T
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 41
+

R
2
R
1
R
g
m
V
g r
ο
V
T
I
T
V
g
Part a:
v
π
= v
t
\

.


r
π
 R
1
r
π
 R
1
+ R
2
i
t
=
\

.


v
t
r
π
 R
1
+ R
2
+
\

.


v
t
R
+ g
m
v
π
+
v
t
r
ο
i
t
= v
t
\

.


1
r
π
 R
1
+ R
2
+
\

.


1
R
+
\

.


g
m
(r
π
 R
1
)
r
π
 R
1
+ R
2
+
1
r
ο
v
t
i
t
=
R r
ο
(r
π
 R
1
+ R
2
)
R r
ο
+ r
ο
(r
π
 R
1
+ R
2
) + R r
ο
g
m
(r
π
 R
1
) + R (r
π
 R
1
+ R
2
)
if r
π
 R
1
>> R
2
then
v
t
i
t
=
1
g
m
Part b:
v
G
= v
t
\

.


R
2
R
1
+ R
2
i
t
= g
m
v
G
+
v
t
r
ο
+
v
t
R
+
v
t
R
1
+ R
2
i
t
v
t
=
g
m
R
2
R
1
+ R
2
+
1
r
ο
+
1
R
+
1
R
1
+ R
2
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 42
if R
2
>> R
1
then
i
t
v
t
= g
m
+
1
r
ο
+
1
R
+
1
R
2
if g
m
>>
1
R
2
, g
m
>>
1
r
ο
, g
m
>>
1
R
then
i
t
v
t
= g
m
Problem 4.56
Using the reference circuit illustrated in Fig. 4.53(b), design a voltage reference having
V
REF
=2.5 when V
DD
=5.0. Assume that I
S
= 1 fA and β
F
=100. Evaluate the sensitivity of
V
REF
with respect to V
DD
.
Figure 4.53 (b)
V
REF
+

V
DD
R
R
1
R
2
I
I
1
I
B
IR = 2.5
Choose R = 250 kΩ, I = 10µA
I = I
1
+ I
E
choose I
E
= 1 µA, and I
1
= 9 µA
With β=100, base current is insignificant and will be ignored.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 43
I
1
=
2.5
R
1
+ R
2
= 9 µA =
2.5
R
1
+ R
2
R
1
+ R
2
= 277.8 kΩ
V
REF
= I
1
R
2
+ V
EB
2.5 = 9 µA R
2
+ 0.0259 × ln
\

.

 1 µA
1 fA
R
2
= 218.1 kΩ
R
1
= 59.64 kΩ
V
EB
=
V
REF
R
1
R
1
+ R
2
V
REF
= V
EB
R
1
+ R
2
R
1
=
\

.


R
1
+ R
2
R
1
V
t
ln
\

.

 V
DD
− V
REF
R I
S
V
REF
S
V
DD
=
\

.

 ∂V
REF
∂V
DD
\

.


V
DD
V
REF
=
\

.


V
DD
V
REF
V
t
\

.


R I
S
V
DD
− V
REF
\

.


1
R I
S
\

.


R
1
+ R
2
R
1
V
REF
S
V
DD
=
\

.


V
DD
V
REF
V
t
\

.


1
V
DD
− V
REF
\

.


R
1
+ R
2
R
1
V
REF
S
V
DD
=
\

.


5
2.5
0.0259
\

.


1
2.5
\

.


277.8
59.64
= 0.0965
Problem 4.61
An improved bandgap reference generator is illustrated in Fig. P4.61. Assume that the
devices M1 through M5 are identical in W/L. Further assume that the area ratio for the
bipolar transistors is 10:1. Design the components to achieve an output reference voltage
of 1.262 V. Assume that the amplifier is ideal. What advantage, if any, is there in
stacking the bipolar transistors?
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 44
+

R
2
R
1
V
REF
+

+

V
R1
Figure P4.61
I
2
I
1
Q
2b
M1 M2 M3 M4 M5
Q
3
V
DD
Q
2a
Q
1a
Q
1b
opamp polarity
corrected
¦
¦
V
REF
T=T0
= V
G0
+ V
t0
(γ − α) = 1.262 @ 300 K
KV
t0
= V
G0
− V
BE0
+ V
t0
(γ − α)
K =
\

.


R
2
R
1
ln (10) =
V
G0
− V
BE0
+ V
t0
(γ − α)
V
t0
V
BE0
=
kT
q
ln
\

.


I
I
S
I =
∆V
BE
R
1
=1 µA
R
1
=
0.0259 ln(10)
1 µA
= 59.64 kΩ
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 45
K =
1.205  0.53 + 0.0259(2.2)
0.0259
= 28.26 kΩ =
\

.


R
2
R
1
ln (10)
R
2
= 732 kΩ
Stacking bipolar transistors reduces sensitivity to amplifier offset.
Problem 4.62
In an attempt to reduce the noise output of the reference circuit shown in Fig. P4.61, a
capacitor is placed on the gate of M5. Where should the other side of the capacitor be
connected and why?
The other end of the capacitor should be connected to V
DD
. At high frequencies, the
capacitor is a smallsignal short circuit. Therefore, highfrequency noise on V
DD
also
appears at the gate of M5 and thus is not amplified by M5. If on the other hand, the
capacitor was connected to ground, noise on V
DD
would appear as v
GS
of M5 and thus be
amplified to the output.
Problem 4.63
In qualitative terms, explain the effect of low Beta for the bipolar transistors in
Fig. P4.61?
In our analysis, we assume that
I
E
= I
S
e
(V
BE
/ V
t
)
but in reality, this is the expression for I
C
.
If β is large, then the approximation is warranted, but if not, the performance will deviate
from the ideal.
Problem 4.64
Consider the circuit shown in Fig. P4.64. It is a variation of the circuit shown in Fig.
P4.61. What is the purpose of the circuit made up of M6M9 and Q4?
This circuit performs basecurrent compensation so that none of the base currents in Q
1b
and Q
2b
flow into Q
1a
and Q
2a
respectively.
Problem 4.65
Extend Example 4.61 to the design of a temperatureindependent current based upon the
circuit shown in Fig. 4.64. The temperature coefficient of the resistor, R
4
, is +1500
ppm/°C.
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 46
+

R
2
R
3
R
1
Q
1
Q
2
+

V
R1
Figure P4.65
I
2
I
1
R
4
I
REF
M1 M2
opamp polarity
corrected
\

.


A
e1
A
e2
= 10
V
eb
= 0.7 , R
2
= R
3
, V
t
= 26 mV , TC
4
= 1500 ppm/°C
V
G0
= 1.205 , γ = 3.2 , α = 1 , T
0
= 27 °C
Since the amp forces V
+
= V
−
, then I
1
= I
2
I
REF
= I
4
+ 2 I
1
=
V
REF
R
4
+ 2 I
1
I
1
=
∆V
be
R
1
=
1
R
1
kT
q
ln(10)
We want
∂I
REF
∂T
= 0
T = T
0
∂I
REF
∂T
=
∂
∂T
\

.


V
REF
R
4
+
∂
∂T
(2 I
1
)
2
∂I
1
∂T
=
\

.


2K
q
ln(10)
R
1
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 47
∂
∂T
\

.


V
REF
R
4
=
∂V
REF
∂T
R
4
− V
REF
∂R
4
∂T
R
2
4
∂R
4
∂T
=
∂
∂T
(R
4
+ R
4
TC
4
∆T) = R
4
TC
4
∂V
REF
∂T
= K
\

.


V
t0
T
0
+
V
BE0
− V
G0
T
0
+
(α − γ)V
t0
T
0
∂I
REF
∂T
=
1
R
4
K
\

.


V
t0
T
0
+
V
BE0
− V
G0
T
0
+
(α − γ)V
t0
T
0

V
REF
R
4
TC
4
+
\

.


2K
q
ln(10)
R
1
K =
R
2
R
1
ln
\

.


A
e1
A
e2
=
R
2
R
1
ln(10)
choose
R
2
R
1
= 10 then K = 23.03
I
1
=
∆ V
BE
R
1
=
kT
q
ln(10)
R
1
= 2 µA
thus
R
1
= 29.93 kΩ , and R
2
= 299.3 kΩ
assume that V
REF
= 1.262 and solve for R
4
R
4
=
T
0
R
1
2 V
t
ln(10)
V
G0
−V
BE0
T
0
+
(γ −α)V
t0
T
0
− K
\

.


V
t0
T
0
+
V
REF
TC
4
T
0
T
0
R
4
=
R
1
2 V
t
ln(10)
(V
G0
−V
BE0
) + (γ −α)V
t0
− K V
t0
+ V
REF
TC
4
T
0
R
4
= 250 × 10
3
× 0.153 = 3825 Ω
CMOS Analog Circuit Design (2
nd
Ed.) Homework Solutions: 9/21/2002 48
I
REF
=
V
REF
R
4
+ 2 I
1
= 4 × 10
6
+
1.262
3825
= 333.9 × 10
6
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 51
CHAPTER 5 – HOMEWORK SOLUTIONS
Problem 5.101
Assume that M2 in Fig. 5.12 is replaced by a 10kΩ resistor. Use the graphical technique
illustrated in this figure to obtain a voltage transfer function of M1 with a 10kΩ load
resistor. What is the maximum and minimum output voltages if the input is taken from
0V to 5V?
Solution
A computer generated plot of this problem is shown below.
0
1
2
3
4
5
0 1 2 3 4 5
V
o
u
t
(
V
)
V
in
(V)
V
in
V
out
+5V
10kΩ
Μ1
2µm
1µm
Fig. S5.101
The maximum output is obviously equal to 5V. The minimum output requires the
following calculation assuming that M1 is in the active region.
110x10
6
·2[(50.7)v
out
– 0.5v
out
2
] =
5 v
out
10kΩ
4.3 v
out
 v
out
2
=
5v
out
2.22
→ v
out
2
– 9.5 v
out
+ 4.504 = 0
This gives,
v
out
(min) = 4.25±4.2945 = 0.5V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 52
Problem 5.102
Using the largesignal model parameters of Table 3.12, use
Eqs. (1) and (5) to calculate the values of v
OUT
(max) and
v
OUT
(min). Compare with the results shown on Fig. 5.12 on
the voltage transfer function curve.
Solution
From Eq. (5.11), (max)
out
V can be calculated as
V V V
out DD Tp
(max) − = 4.3 V
From Eq. (5.15), (min)
out
V can be calculated as
( )
1
1
(min)
2
β
β
+
−
− −
T DD
T DD out
V V
V V V
V
out
(min) .
.
− −
− ( )
+
( )( )
( )( )
5 0 7
5 0 7
1
50 1
110 5
= 0.183 V
Problem 5.103
What value of β
1
/β
2
will give a voltage swing of 70% of V
DD
if V
T
is 20% of V
DD
? What is the smallsignal voltage gain
corresponding to this value of β
1
/β
2
?
Solution
Given
DD T
V V 2 . 0 and ( )
DD out out
V V V 7 . 0 (min) (max) −
From Eq. (5.11) and (5.15)
( )
1
2
1
(min) (max)
β
β
+
−
−
T DD
out out
V V
V V
or,
( )
1
2
1
2 . 0
7 . 0
β
β
+
−
DD DD
DD
V V
V → 1
8
7
2
1
2
+

.
`
}

.
`
}
β
β
→
β
β
2
1
= 0.306
The smallsignal voltage gain can be given by A
g
g
v
m
m
≅ − −
1
2
1
2
β
β
= 1.8 V/V
M2
M1
v
IN
v
OUT
I
D
5V
+

+

W
2
L
2
=
1µm
1µm
W
1
L
1
=
2µm
1µm
Fig. S5.102
M2
M1
v
IN
v
OUT
I
D
5V
+

+

W
2
L
2
= β
2
W
1
L
1
= β
1
Fig. S5.103
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 53
Problem 5.104
What value of V
in
will give a current in the active load
inverter of 100µA if W
1
/L
1
= 5µm/1µm and W
2
/L
2
=
2µm/1µm? For this value of V
in
, what is the smallsignal
voltage gain and output resistance?
Solution
Assuming
1
M is operated in saturation
I K
W
L
V V
D N
in T
1
1
2
2

.
`
}
− ( )

.
`
}
'
or, 100 110 5
0 7
2
2
µ µ ( )( )
− ( )

.
`
}
V
in
.
→ V
in
= 1.303V
The smallsignal gain can be given by A
g
g
K
K
W
L
L
W
v
m
m
N
P
≅ − −
( )
( )

.
`
}

.
`
}
1
2 1 2
'
'
= 2.345 V/V
The output resistance can be given by R
g
out
m
≅
1
2
= 7.07 k Ω
Problem 5.105
Repeat Ex. 5.11 if the drain current in M1 and M2 is 50µA.
Solution
From Eqs. (5.11) and (5.15) we get
v
OUT
(max) = 4.3V
v
OUT
(min) = 5 – 0.7 
50.7
1 + (50·1/110·2)
= 0.418 V
From Eq. (5.17) we get,
v
out
v
in
= 
g
m1
g
ds1
+g
ds2
+g
m2
=
148.3
2.0 + 2.5+ 70.71
= 1.972 V/V
From Eq. (5.18) we get,
R
out
=
1
g
ds1
+g
ds2
+g
m2
=
10
6
2.0 + 2.5 + 70.71
= 13.296 k Ω
The zero is at,
z
1
=
g
m1
C
gd1
=
148.3µS
0.5ff
= 2.966x10
11
rads/sec → 47.2 GHz
The pole is at,
p
1
= ω
3dB
=
1
R
out
(Cbd1+C
bd2
+C
gs2
+C
L
)
=
1
(13.296kΩ)(1.0225pF)
= 73.555x10
6
rads/sec. → 11.71 MHz
M2
M1
v
IN
v
OUT
I
D
5V
+

+

W
2
L
2
=
2µm
1µm
W
1
L
1
=
5µm
1µm
Fig. S5.104
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 54
Problem 5.106
Assume that W/L ratios of Fig. P5.16 are W
1
/L
1
=
2µm/1µm and W
2
/L
2
= W
3
/L
3
= W
4
/L
4
=
1µm/1µm. Find the dc value of V
in
that will give a
dc current in M1 of 110µA. Calculate the small
signal voltage gain and output resistance of Fig.
P5.16 using the parameters of Table 3.12.
Solution
Assuming all transistors are in saturation and ideal
current mirroring
I K
W
L
V V
D N
in T
1
1
2
2

.
`
}
− ( )

.
`
}
'
or, 110 110 2
0 7
2
2
µ µ ( )( )
− ( )

.
`
}
V
in
.
→ V
in
= 1.7V
The smallsignal voltage gain can be given by
A
g
g
K
K
W
L
L
W
I
I
V
m
m
N
P
D
D
≅ − −

.
`
}

.
`
}

.
`
}
1
2 1 2
1
2
'
'
= 6.95 V/V
where, I I
D D 3 4
100 µA, and I
D2
10 µA.
The output resistance can be given by
R
g
out
m
≅
1
2
= 31.6 k Ω
M2
M1
v
IN
v
OUT
+

+

M3
V
DD
M4
100µA
Figure P5.16
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 55
Problem 5.107
Find the smallsignal voltage gain and the 3dB frequency in Hertz for the activeload
inverter, the current source inverter and the pushpull inverter if W
1
= 2µm, L
1
= 1µm,
W
2
= 1µm, L
2
= 1µm and the dc current is 50µA. Assume that C
gd1
= 4fF, C
bd1
= 10fF,
C
gd2
= 4fF, C
bd2
= 10fF and C
L
= 1pF.
V
DD
M2
M1
v
IN
v
OUT
I
D
M2
M1
v
IN
v
OUT
I
D
M2
M1
v
IN
v
OUT
I
D
V
GG2
Active
PMOS Load
Inverter
Current
Source Load
Inverter
Push
pull
Inverter
Figure 5.11 Various types of inverting CMOS amplifiers.
Solution
1. Active load inverter
The output resistance can be given by
R
g
out
m
≅
1 1
2 50 1 50
2
( )( )( ) µ µ
= 14.14 k Ω
The total output capacitance can be given by
C C C C C C
out L gs bd gd bd
+ + + +
2 2 1 1
= 1.029 pF
The –3 dB frequency can be given by
f
R C
dB
out out
−
3
1
2π
= 10.9 MHz
2. Currentsource inverter
The output resistance can be given by
R
g g I
out
ds ds D N P
≅
+
+
1 1
1 2
( ) λ λ
= 222.22 k Ω
The total output capacitance can be given by
C C C C C C
out L gd bd gd bd
+ + + +
2 2 1 1
= 1.028 pF
The –3 dB frequency can be given by
f
R C
dB
out out
−
3
1
2π
= 0.697 MHz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 56
Problem 5.107  Continued
3. Pushpull inverter
The output resistance can be given by
R
g g I
out
ds ds D N P
≅
+
+
1 1
1 2
( ) λ λ
= 222.22 k Ω
The total output capacitance can be given by
C C C C C C
out L gd bd gd bd
+ + + +
2 2 1 1
= 1.028 pF
The –3 dB frequency can be given by
f
R C
dB
out out
−
3
1
2π
= 0.697 MHz
Problem 5.108
What is the smallsignal voltage gain of a currentsink
inverter with W
1
2µm, L
1
1µm, W
2
L
2
1 µm at I
D
0.1, 5 and 100 µA? Assume that the parameters of the
devices are given by Table 3.12.
1. 1 . 0
D
I
A µ
g
I
n V m
m
D
p t
1
1
0 1
2 5 26
( )
( )( )
.
.
µ
= 1.538 µS
A
g
g g
g
I
v
m
ds ds
m
D N P
−
+ ( )
−
+ ( )
1
1 2
1
λ λ
=  170.9 V/V
2. 5
D
I
A µ
g K
W
L
I
m P D 1
1
1
2 31 62

.
`
}
'
. = 31.62 µS
A
g
g g
g
I
v
m
ds ds
m
D N P
−
+ ( )
−
+ ( )
1
1 2
1
λ λ
=  70.27 V/V
3.
100
D
I
A µ
g K
W
L
I
m P D 1
1
1
2 141 42

.
`
}
'
.
S µ
A
g
g g
g
I
v
m
ds ds
m
D N P
−
+ ( )
−
+ ( )
1
1 2
1
λ λ
= 15.71 V/V
M2
M1
v
IN
v
OUT
I
D
5V
+

+

W
2
L
2
=
2µm
1µm
W
1
L
1
=
2µm
1µm
2.5V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 57
Problem 5.109
A CMOS amplifier is shown. Assume M1 and M2 operate in
the saturation region. a.) What value of V
GG
gives 100µA
through M1 and M2? b.) What is the DC value of v
IN
? c.)
What is the small signal voltage gain, v
out
/v
in
, for this
amplifier? d.) What is the 3dB frequency in Hz of this
amplifier if C
gd
= C
gd
= 5fF, C
bs
= C
bd
= 30fF, and C
L
=
500fF?
Solution
a)
2 2 dsat T GG
V V V +
V V
I
K W L
GG T
D
N
+
( )
2
2
2
2
'
= 2.05 V
b) V V V
I
K W L
in DD T
D
P
− −
( )
1
1
1
2
'
= 3.406 V
c) A
v
v
g
g g
v
out
in
m
ds ds
−
+ ( )
1
1 2
= 24.85 V/V
d) f
g g
C C C C C
dB
ds ds
gd gd bd bd L
−
+ ( )
+ + + + ( )
3
1 2
1 2 1 2
2π
= 2.51 MHz.
V
DD
v
in
v
out
V
GG
M1
M2
5µm/1µm
1µm/1µm
Figure P5.19
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 58
Problem 5.110
A currentsource load amplifier is shown. (a.) If C
BDN
=C
BDP
= 100fF, C
GDN
=C
GDP
= 50fF, C
GSN
= C
GSP
=
100fF, and C
L
= 1pF, find the 3dB frequency in Hertz.
(b.) If Boltzmann’s constant is 1.38x10
23
Joules/°K, find
the equivalent input thermal noise voltage of this amplifier
at room temperature (ignore bulk effects, η = 0).
Solutions
(a.) The 3dB frequency is equivalent to the magnitude of
the output pole which is given as
ω
3dB
=
1
R
out
C
out
where R
out
=
1
g
ds1
+g
ds2
=
1
100µA(0.04+0.05)
=
1
9x10
6
= 111kΩ
C
out
= C
gd1
+C
bd1
+C
gd2
+C
bd2
+C
L
= 0.05 + 0.05 + 0.1 + 0.1 +1 pF = 1.3pF
∴ ω
3dB
=
1
0.111MΩ·1.3pF
= 6.923x10
6
rads/sec. → f
3dB
= 1.102 MHz
(b.) The noise voltage at the output can be written as
e
no
2
= e
n1
2
.

}
`
g
m1
g
ds1
+g
ds2
2
+ e
n2
2
.

}
`
g
m2
g
ds1
+g
ds2
2
Reflecting this noise voltage back to the input gives the equivalent input noise as,
e
ni
2
= e
n1
2
]
]
]
1 +
.

}
`
g
m2
g
m1
2
.

}
`
e
n2
e
n1
2
= e
n1
2
]
]
]
]
1 +
.

}
`
g
m2
g
m1
2
.

}
`
8kT
3g
m2
8kT
3g
m1
= e
n1
2
.

}
`
1 +
g
m2
g
m1
where
g
m1
=
2I
D
K
N
W
1
L
1
= 469µS, g
m2
=
2I
D
K
P
W
2
L
2
= 316µS,
and e
n1
2
=
8kT
3g
m1
=
8·1.38x10
23
·300
3·469x10
6
= 2.354x10
17
V
2
/Hz
e
ni
2
= 2.354x10
17
·1.6738 = 3.94x10
17
V
2
/Hz → e
ni
= 6.277nV/ Hz
M1
M2 M3
V
DD
v
in
v
out
100µA
All W/L's
equal 10
Fig. P5.110
C
L
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 59
Problem 5.111
Six inverters are shown. Assume that K
N
' = 2K
P
' and that λ
N
= λ
P
, and that the dc bias
current through each inverter is equal. Qualitatively select, without using extensive
calculations, which inverter(s) has/have (a.) the largest ac small signal voltage gain, (b.)
the lowest ac small signal voltage gain, (c.) the highest ac output resistance, and (d.) the
lowest ac output resistance. Assume all devices are in saturation.
M2
M1
v
IN
v
OUT
Circuit 1
v
IN
v
OUT
M2
M1
Circuit 2 Circuit 3
v
OUT
M1
v
IN
M2
v
IN
v
OUT
M2
M1
Circuit 4
M2
M1
v
IN
v
OUT
V
BP
v
IN
M2
M1
V
BN
v
OUT
Circuit 5 Circuit 6
V
DD
Figure P5.111
Solution
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6
g
m g
mN
= 2 g
mP
g
mP g
mN
= 2 g
mP
g
mP g
mN
= 2 g
mP
g
mP
R
out
≈
1
g
mN
+g
mbN
0.707
g
mP
+g
mbP
≈
1
g
mP
+g
mbP
≈
1
g
mP
≈
1
g
mN
≈
0.707
g
mP
1
g
dsN
+g
dsP
=
1
g
dsP
(1+ 2)
1
g
dsN
+g
dsP
=
1
g
dsP
(1+ 2)
Gain
g
mP
g
mP
+g
mbP
g
mP
g
mP
+g
mbP
2
1
2
2 g
mP
g
dsP
(1+ 2)
g
mP
g
dsP
(1+ 2)
(a.) Circuit 5 has the highest gain.
(b.) Circuit 4 has the lowest gain (assuming normal values of g
m
/g
mb
).
(c.) Circuits 5 and 6 have the highest output resistance.
(d.) Circuit 1 has the lowest output resistance.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 510
Problem 5.112
Derive the expression given in Eq. (5.129) for the CMOS
pushpull inverter of Fig. 5.18. If C
gd1
C
gd2
5fF, C
bd1
C
bd2
50fF, C
L
10 pF, and I
D
200 µA, find the
smallsignal voltage gain and the −3 dB frequency if W
1
/L
1
W
2
/L
2
5 of the CMOS pushpull inverter of Fig. 5.18.
Solution
The effective transconductance can be given by
g g g I K
W
L
K
W
L
m eff m m D N P ,
' '
+

.
`
}
+

.
`
}
]
]
]
1 2
1 2
2
The output conductance can be given by
( ) ( )
2 1 2 1
λ λ + +
D ds ds out
I g g g
Thus, the smallsignal gain becomes
out
eff m
v
g
g
A
,
−
A
I
K
W
L
K
W
L
v
D
N P
−

.
`
}
+

.
`
}
+ ( )
]
]
]
]
]
2
1 2
1 2
' '
λ λ
Eq. (5.129)
For 200
D
I
A µ
63 . 43 −
v
A = 43.63 V/V
The total capacitance at the output node is
C C C C C C
total gd gd bd bd L
+ + + +
( )
1 2 1 2
= 10.11 pF.
Thus, the –3 dB frequency is
f
g
C
dB
out
total
−
3
2π
= 283.36 kHz.
M2
M1
v
IN
v
OUT
I
D
5V
+

+

W
2
L
2
=
2µm
1µm
W
1
L
1
=
1µm
1µm
Fig.P 5.112
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 511
Problem 5.113
For the activeresistor load inverter, the currentsource load inverter, and the pushpull
inverter compare the active channel area assuming the length is 1µm if the gain is to be
−1000 at a current of I
D
0.1 µA and the PMOS transistor has a W/L of 1.
V
DD
M2
M1
v
IN
v
OUT
I
D
M2
M1
v
IN
v
OUT
I
D
M2
M1
v
IN
v
OUT
I
D
V
GG2
Active
PMOS Load
Inverter
Current
Source Load
Inverter
Push
pull
Inverter
Figure 5.11 Various types of inverting CMOS amplifiers.
Soluton
Given, 10
D
I A µ , and 100 −
v
A V/V
a) Activeresistor load inverter
2
1
m
m
v
g
g
A − ≅ →
( )
) 1 (
100
’
1
’
P
N
K
L W K
→
W
1
L
1
= 4546
Active area = 4546·1 + 5·1 = 4551 µm
2
b) Currentsource load inverter
( )
2 1
1
ds ds
m
v
g g
g
A
+
− →
( )
( )
2
2 1
1
’
2
100
λ λ +
D
N
I
L W K
→
W
1
L
1
= 3.64
Active area = 3.64·1 + 5·1 = 8.64 µm
2
c) Pushpull inverter
( )
( )
2 1
2 1
ds ds
m m
v
g g
g g
A
+
+
− →
( ) ( )
( )
2
2 1
’
1
’
1 / 1 2 2
100
λ λ +
+
D
P N
I
K L W K
→
W
1
L
1
= 1.55
Active area = 1.55·1 + 5·1 = 4.55 µm
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 512
Problem 5.114
For the CMOS pushpull inverter shown, find the small signal
voltage gain, A
v
, the output resistance, R
out
, and the 3dB
frequency, f
3dB
if I
D
= 200µA, W
1
/L
1
= W
2
/L
2
= 5, C
gd1
=
C
gd2
= 5fF, C
bd1
= C
bd2
= 30fF, and C
L
= 10pF.
Solution
The smallsignal model for this problem is shown below.
g
m1
v
in
r
ds1
g
m2
v
in
r
ds2
+

v
in
+

v
out
C
out
C
M
i
out
Fig. S5.114
Summing the currents at the output (ignoring the capacitors) gives,
g
m1
v
in
+ g
ds1
v
out
+ g
m2
v
in
+ g
ds2
v
out
= 0
Solving for the voltage gain gives,
v
out
v
in
= 
g
m1
+ g
m2
g
ds1
+ g
ds2
= 
2
W
1
L
1
I
D
K
N
+ 2
W
2
L
2
I
D
K
P
I
D
(λ
N
+λ
P
)
= 
2
I
D
W
1
L
1
K
N
+
W
2
L
2
K
P
λ
N
+λ
P
v
out
v
in
= A
v
= 
2
200x10
6
5·110x10
6
+ 5·50x10
6
0.05 + 0.04
=  (100)(0.436) =  43.63V/V
∴ A
v
=  43.63V/V
The output resistance is found by setting v
in
= 0 and solving for v
out
/i
out
.
R
out
is simply expressed as,
R
out
=
1
g
ds1
+ g
ds2
=
1
I
D
(λ
N
+ λ
P
)
=
1
200x10
6
(0.05+0.04)
= 55.55kΩ
∴ R
out
= 55.55k Ω
From Eq. (5.126) we can solve for the –3dB frequency as
ω
3dB
= ω
1
g
ds1
+ g
ds2
C
gd1
+ C
gd2
+ C
bd1
+ C
bd2
+ C
L
=
1
R
out
(C
gd1
+ C
gd2
+ C
bd1
+ C
bd2
+ C
L
)
=
1
55.55x10
3
( 5fF + 5fF + 30fF + 30fF + 10pF )
≈
1
55.55x10
3
·10x10
12
= 1.8x10
6
rad/s
∴ ω
3dB
= 1.8x10
6
rad/s → f
3dB
= 286.5 kHz
V
DD
V
SS
v
OUT
v
IN
M2
M1
Fig. P5.114
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 513
Problem 5.201
Use the parameters of Table 3.12 to calculate the smallsignal, differentialin,
differentialout transconductance g
md
and voltage gain A
v
for the nchannel input,
differential amplifier when I
SS
100 µA and W
1
/L
1
W
2
/L
2
W
3
/L
3
W
4
/L
4
1
assuming that all channel lengths are equal and have a value of 1µm. Repeat if W
1
/L
1
W
2
/L
2
10W
3
/L
3
10W
4
/L
4
10.
Solution
Referring to Fig. 5.25 and given that
a)
W
L
W
L
W
L
W
L

.
`
}

.
`
}

.
`
}

.
`
}
1 2 3 4
1
Differentialin differentialout transconductance is given by
g g g K
W
L
I
md m m N SS

.
`
}
1 2
1
'
= 104.8 µS
Smallsignal voltage gain is given by
A
g
g g
g
I
v
m
ds ds
m
SS
+ ( )
+ ( )
2
2 4
2
2 4
2
λ λ
= 23.31 V/V
b)
W
L
W
L
W
L
W
L

.
`
}

.
`
}

.
`
}

.
`
}
1 2 3 4
10 10 10
g g g
md m m
1 2
= 331.4 µS
A
g
g g
v
m
ds ds
+ ( )
2
2 4
= 36.82 V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 514
Problem 5.202
Repeat the previous problem for the pchannel input, differential amplifier.
Solution
Referring to Fig. 5.27 and given that
(a.)
W
L
W
L
W
L
W
L

.
`
}

.
`
}

.
`
}

.
`
}
1 2 3 4
1
Differentialin differentialout transconductance is given by
g g g K
W
L
I
md m m P SS

.
`
}
1 2
1
'
= 70.71 µS
Smallsignal voltage gain is given by
A
g
g g
g
I
v
m
ds ds
m
SS
+ ( )
+ ( )
2
2 4
2
2 4
2
λ λ
= 15.7 V/V
(b.)
W
L
W
L
W
L
W
L

.
`
}

.
`
}

.
`
}

.
`
}
1 2 3 4
10 10 10
g g g
md m m
1 2
= 223.6 µS
A
g
g g
v
m
ds ds
+ ( )
2
2 4
= 24.84 V/V
Problem 5.203
Develop the expressions for V
IC
(max) and V
IC
(min) for the pchannel input differential
amplifier of Fig. 5.27.
Solution
The maximum input commonmode input is given by
( )
5 1 1
(max)
dsat dsat T DD IC
V V V V V + + −
or, V V V
I
K W L
I
K W L
IC DD T
DD
P
DD
P
(max)
' '
− +
( )
+
( )

.
`
}
1
1 5
2
The minimum input commonmode input is given by
3 3 1
(min)
dsat T T SS IC
V V V V V + + −
or, V V V V
I
K W L
IC SS T T
DD
N
(min)
'
− + +
( )
1 3
3
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 515
Problem 5.204
Find the maximum input common mode voltage, v
IC
(max) and the minimum input
common mode voltage, v
IC
(min) of the nchannel input, differential amplifier of Fig. 5.2
5. Assume all transistors have a W/L of 10µm/1µm, are in saturation and I
SS
= 10µA.
What is the input common mode voltage range for this amplifier?
Solution
The maximum input commonmode input is given by
3 3 1
(max)
dsat T T DD IC
V V V V V − − +
or, V V V V
I
K W L
IC DD T T
SS
P
(max)
'
+ − −
( )
1 3
3
= 4.86 V
The minimum input commonmode input is given by
5 1 1
(min)
dsat dsat T SS IC
V V V V V + + +
or, V V V
I
K W L
I
K W L
IC SS T
SS
N
SS
N
(min)
' '
+ +
( )
+
( )
1
1 5
2
= 0.93 V
So, the input commonmode range becomes
ICMR V V
IC IC
− (max) (min)= 3.93 V
Problem 5.205
Find the small signal voltage gain, v
o
/v
i
, of the circuit in the previous problem if v
in
= v
1
 v
2
. If a 10pF capacitor is connected to the output to ground, what is the 3dB frequency
for V
io
(jω)/V
IN
(jω) in Hertz? (Neglect any device capacitance.)
Solution
Smallsignal voltage gain is given by
A
g
g g
g
I
v
m
ds ds
m
SS
+ ( )
+ ( )
2
2 4
2
2 4
2
λ λ
= 233.1 V/V
The –3 dB frequency is given by
f
g g
C
I
C
dB
ds ds
L
SS
L
−
≅
+ ( )
+ ( )
3
2 4 2 4
2 4 π
λ λ
π
= 7.16 kHz.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 516
Problem 5.206
For the CMOS differential amplifier of Fig. 5.25, find the small signal voltage gain,
v
out
/v
in
, and the output resistance, R
out
, if I
SS
= 10µA, V
DD
= 2.5V and v
in
= v
gs1
v
gs2
. If
the gates of M1 and M2 are connected together, find the minimum and maximum
common mode input voltage if all transistors must remain in saturation (ignore bulk
effects).
Solution
Smallsignal model for calculations:
gm3 rds3
1
rds1
gm1
v
gs1
rds2
gm2
v
gs2
i
3
i
3
+

+

+
v
in
v
gs1
v
gs2

rds4
+

v
out
i
out
Fig. S5.206
R
out
=
1
g
ds2
+ g
ds4
=
1
(0.04 + 0.05)5µA
= 2.22 M Ω
v
out
.

}
`
g
m1
g
m3
r
p1
1 + g
m3
r
p1
v
gs1
− g
m2
v
gs2
R
out
≈ (g
m1
v
gs1
– g
m2
v
gs2
)R
out
= g
m1
R
out
v
in
∴
v
out
v
in
= g
m1
R
out
= g
m2
R
out
, g
m1
= g
m2
= 2·110·5·2) µS = 46.9 µS
v
out
v
in
= 46.9µS·2.22MΩ = 104.1 V/V
Common mode input range:
V
icm
(max) = V
DD
– V
SG3
+ V
TN
= 2.5 
.

}
`
2·5
50·2
+0.7 + 0.7 = 2.5  0.3162 = 2.184 V
V
icm
(min) = 0+V
DS5
(sat)+V
GS1
=
2·10
110·2
.

}
`
2·5
110·2
+0.7 = 0.3015+0.9132
= 1.2147 V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 517
Problem 5.207
Find the value of the unloaded differentialtransconductance gain, g
md
, and the unloaded
differentialvoltage gain, A
v
, for the pchannel input differential amplifier of Fig. 5.27
when I
SS
10 microamperes and I
SS
1 microampere. Use the transistor parameters of
Table 3.12.
Solution
Assuming all transistors have W/L = 1
a) Given, 10
SS
I A µ
g K
W
L
I
md P SS

.
`
}
'
1
= 22.36 µS A
g
g g
g
I
v
md
ds ds
md
SS
+ ( )
+ ( )
2 4 2 4
2
λ λ
= 49.69 V/V
b) Given, 1
SS
I A µ
g K
W
L
I
md P SS

.
`
}
'
1
= 7.07 µS A
g
g g
g
I
v
md
ds ds
md
SS
+ ( )
+ ( )
2 4 2 4
2
λ λ
= 157.11 V/V
Problem 5.208
What is the slew rate of the differential amplifier in the previous problem if a 100 pF
capacitor is attached to the output?
Solution
Slew rate can be given as
L
SS
C
I
SR
For 10
SS
I
A µ
and 100
L
C pF
SR
I
C
SS
L
= 0.1 V/µs
For 1
SS
I
A µ
and 100
L
C pF
SR
I
C
SS
L
= 0.01 V/µs
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 518
Problem 5.209
Assume that the current mirror of Fig. 5.25 has an output current that is 5% larger than
the input current. Find the small signal commonmode voltage gain assuming that I
SS
is
100µA and the W/L ratios are 2µm/1µm for M1, M2 and M5 and 1µm/1µm for M3 and
M4.
Solution
Given that
3 4
) 05 . 1 (
D D
I I or,
1 2
) 05 . 1 (
D D
I I
This mismatch in currents in the differential input pair will result in an input offset
voltage.
Now,
SS D D
I I I +
2 1
So,
SS D
I I ) 49 . 0 (
1
≅ and
SS D
I I ) 51 . 0 (
2
≅
To calculate the commonmode voltage gain, let us assume a small signal voltage
s
v applied to both the gates of the differential input pair.
The smallsignal output current
out
i is given by
( )
2 4 D D out
i i i −
where,
i
g
g
g v
D
ds
m
m s 4
5
3
4
0 5
≅

.
`
}
.
( )
s ds D
v g i
5 2
5 . 0 ≅
So,
i i i g
g
g
v
out D D ds
m
m
s
− ( ) ( ) −

.
`
}
4 2 5
4
3
0 5 1 .
The output conductance can be given as
4 ds out
g g ≅ as
2
M and
5
M form a cascode structure.
Thus,
v
i
g
g
g
g
g
v
out
out
out
ds
ds
m
m
s
≅ −

.
`
}
5
4
4
3
2
1
or,
v
v
g
g
g
g
out
s
ds
ds
m
m
−

.
`
}
5
4
4
3
2
1
or,
v
v
I
I
I
I
out
s
SS
SS
D
D
( )
( )
−

.
`
}
λ
λ
5
4
4
3
1
or,
v
v
out
s
0 02 . V/V
Thus, the smallsignal commonmode gain is approximately 0.02 V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 519
Problem 5.210
Use the parameters of Table 3.12 to calculate the differentialintosingleendedoutput
voltage gain of Fig. 5.29. Assume that I
SS
is 50 microamperes.
Solution
Let, the aspect ratio of all the transistors be 1.
The smallsignal differentialin singleended out voltage gain is given by
A
g
g
K
K
W
L
W
L
v
m
m
N
P
( )
( )
1
3
1
3
2 4
'
'
= 0.74 V/V
Problem 5.211
Perform a smallsignal analysis of Fig. 5.210 that does not ignore r
ds1
. Compare your
results with Eq. (5.227).
Solution
Referring to Fig. 5.210
Applying KVL
v v g v r
v v v
r
r
ic gs m gs ds
o ic gs
ds
ds
− ( ) +
− − ( )

.
`
}
1 1 1 5
1
1
5
2 2
or,
( ) { ¦ ( ) ( )
5 1 5 1 1 5 1 1
2 2 1 2
ds ds ic ds o ds m ds ds gs
r r v r v r g r r v + + + +
(1)
Also, applying KCL
−
+

.
`
}
+
− − ( )

.
`
}
v
g
r
g v
v v v
r
o
m
ds
m gs
o ic gs
ds 1
3
3
1 1
1
1
or,
( ) { ¦
( )
1 1
1 3
1
1
1
ds m
ds m o ic
gs
r g
r g v v
v
+
+ −
(2)
Putting Eq. (2) in Eq. (1), and assuming 1
1 1
>>
ds m
r g
( ) { ¦
( )
( ) ( ) ( ) ( )
5 1 5 1 1 5
1 1
1 3
2 2 1 2
1
1
ds ds ic ds o ds m ds
ds m
ds m o ic
r r v r v r g r
r g
r g v v
+ + +
+
+ −
or, ( )
1 5 1 3
2
ds ic ds ds m o
r v r r g v −
or,
( )
5 3
2
1
ds m ic
o
r g v
v
−
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 520
Problem 5.212
Find the expressions for the maximum and minimum input voltages, v
G1
(max) and
v
G1
(min) for the nchannel differential amplifier with enhancement loads shown in Fig.
5.29.
Solution
5 1 1 1
(min)
dsat dsat T G
V V V V + +
or,
( ) ( )
5
’
1
’
1 1
2
(min)
L W K
I
L W K
I
V V
N
SS
N
SS
T G
+ +
3 3 1 1
(max)
dsat T T DD G
V V V V V + − +
or,
( )
3
’
3 1 1
(max)
L W K
I
V V V V
P
SS
T T DD G
+ − +
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 521
Problem 5.213
If all the devices in the differential amplifier of Fig. 5.29 are saturated, find the worst
case input offset voltage, V
OS
, if V
Ti
 1 ± 0.01 volts and β
i
10
5
± 5 × 10
7
amperes/volt
2
. Assume that
β
1
β
2
10β
3
10β
4
and
∆β
1
β
1
∆β
2
β
2
∆β
3
β
3
∆β
4
β
4
Carefully state any assumptions that you make in working this problem.
Solution
Referring to the figure
1 1 1 dsat T GS
V V V +
or,
1
1
1 1
2
β
D
T GS
I
V V +
2 2 2 dsat T GS
V V V +
or,
2
2
2 2
2
β
D
T GS
I
V V +
The inputoffset voltage can de defined as
2 1 GS GS OS
V V V −
or,
2
1
1
1
2 1
2 2
β β
D D
T T OS
I I
V V V − + −
Considering the transistors
3
M and
4
M , mismatches in these two transistors would
cause an offset voltage between the output nodes. But, if it is assumed that this offset
voltage between the output nodes is small as compared to the draintosource voltages of
the transistors
1
M and
2
M , then
2 1 DS DS
V V ≅
Thus, it is assumed here that
I I I
D D
2 1
So, the inputoffset voltage becomes
2 1
2 1
2 2
β β
I I
V V V
T T OS
− + −
Assuming 50 I
A µ
, the worstcase input offset voltage can be given by
V
OS
− ( ) + −
]
]
]
1 01 0 99
2 50
0 95 10
2 50
1 05 10
. .
( )
. ( )
( )
. ( )
µ
µ
µ
µ
or, V
OS
(max) = 0.18 V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 522
Problem 5.214
Repeat Example 5.21 for a pchannel input, differential amplifier.
Solution
The best way to do this problem is to use the equations for the nchannel, sourcecoupled
pair with opposite type transistor parameters and then subtract the result from 5V.
Eq. (5.215) gives
V
IC
(max) 4 −
.

}
`
2·50µA
99µA/V
2
·1
+ 0.85 + 0.55 4 – 1.855 + 0.55 = 2.695 volts
Subtracting from 5V gives
V
IC
(min) 5 − 2.695 2.305 V
and Eq. (5.217) gives
V
IC
(min) 0 + 0.2 +
.

}
`
2·50µA
45µA/V
2
·5
+0.85 0.2 + 1.517 = 1.717 volts
Subtracting from 5 V gives,
V
IC
(max) 5 − 1.717 3.282 V
Therefore, the worstcase input commonmode range is 0.978V with a nominal 5V power
supply.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 523
Problem 5.215
Five different CMOS differential amplifier circuits are shown in Fig. P5.1215. Use the
intuitive approach of finding the small signal current caused by the application of a small
signal input, v
in
, and write by inspection the approximate small signal output resistance,
R
out
, seen looking back into each amplifier and the approximate small signal, differential
voltage gain, v
out
/v
in
. Your answers should be in terms of g
mi
and g
dsi
, i = 1 through 8.
(If you have to work out the details by small signal model analysis, this problem will take
too much time.)
Circuit 1 Circuit 2 Circuit 3 Circuit 4
V
BP
Circuit 5
V
DD
Figure P5.215
M8 M7
M1
v
IN
M2
v
OUT
I
SS
M8 M7
M1
v
IN
M2
v
OUT
I
SS
M8 M7
M1
v
IN
M2
v
OUT
I
SS
M8 M7
M6 M5
M1
M2
v
OUT
I
SS
V
BN
M8 M7
M6 M5
M1
M2
v
OUT
I
SS
M3 M4
Solution
Assume g
m1
= g
m2
otherwise multiply the gain of circuits 1 and 2 by
g
m2
g
m1
+g
m2
.
Circuit R
out
v
out
/v
in
1
1
g
ds2
+g
m8
+g
ds8
g
m1
g
m2
(g
m1
+g
m2
)(g
ds8
+g
m8
+g
ds8
)
=
0.5g
m2
g
ds2
+g
m8
+g
ds8
2
1
g
ds2
+g
ds8
g
m1
g
m2
(g
m1
+g
m2
)(g
ds2
+g
ds8
)
=
0.5g
m2
g
ds2
+g
ds8
3
1
g
ds2
+g
ds8
g
m1
+g
m2
2(g
ds2
+g
ds8
)
4
1
g
ds2˚
+
g
ds6
g
ds8
g
m6
=
g
m6
g
ds6
g
ds8
+g
m6
g
ds2
(g
m1
+g
m2
)
˚
g
m6
2(g
m6
g
ds2
+g
ds6
g
ds8
)
5
g
m4
g
m6
g
ds2
g
m6
g
ds4˚
+g
m6
g
ds4
g
ds8
(g
m1
+g
m2
)g
m4
g
m6
2(g
ds2
g
m6
g
ds4˚
+g
m6
g
ds4
g
ds8
)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 524
Problem 5.216
If the equivalent inputnoise voltage of each transistor of the differential amplifier of Fig.
5.25 is 1nV/ Hz find the equivalent input noise voltage for this amplifier if W
1
/L
1
W
2
/L
2
2 µm/1 µm, W
3
/L
3
W
4
/L
4
1 µm/1 µm and I
SS
50 µA. What is the
equivalent output noise current under these conditions?
Solution
From Equation. (5.239)
e e e
g
g
e e
eq n n
m
m
n n
2
1
2
2
2 3
1
2
3
2
4
2
+ +

.
`
}
+ ( )
or, e e
g
g
e
eq n
m
m
n
2 2 3
1
2
2
2 1 2 455 +

.
`
}

.
`
}
.
Given
1
n
e Hz nV /
Thus,
e
eq.
= 1.567 nV/ Hz
The equivalent output noise current is given by
2 2
1
2
eq m to
e g i
or, i
to
= 164 fA/ Hz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 525
Problem 5.217
Use the smallsignal model of the differential amplifier using a current mirror load given
in Fig. 5.28(a) and solve for the ac voltage at the sources of M1 and M2 when a
differential input signal, v
id
, is applied. What is the reason that this voltage is not zero?
Solution
Neglecting the current source
3
i in the figure, let us assume that
2
2 1
id
g g
v
v v −
Applying nodal analysis, we will get the following three equations
( ) ( )
3 1 3 1 1 1 1 1 D ds m g m s ds m
v g g v g v g g + + +
(1)
( ) ( )
out ds ds g m s ds m
v g g v g v g g
4 2 2 2 1 2 2
+ + +
(2)
( )
out ds D ds g m g m s ds ds ds m m
v g v g v g v g v g g g g g
2 3 1 2 2 1 1 1 5 2 1 2 1
+ + + − + + +
(3)
Now, assuming
ds m
g g >> ,
2 1 m m
g g ,
2 1 ds ds
g g , and
2
2 1
id
g g
v
v v −
( )
5 2 1 2 1
2 3 1
1
ds ds ds m m
out ds D ds
s
g g g g g
v g v g
v
− + + +
+
or,
( )
5 1 1
2 3 1
1
2 2
ds ds m
out ds D ds
s
g g g
v g v g
v
− +
+
Substituting from Equations (1) and (2), we get
v
g
g
g
g g
g
g
g
v
s
m
ds
m
m ds
m
m
ds
id 1
1
1
3
1 1
1
3
5
0 25
0 75 2
−

.
`
}
+ −

.
`
}
−

.
`
}
.
.
The value of
1 s
v is nonzero because the loads (M3 and M4) seen by the input transistors
(M1 and M2) at their drains are different.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 526
Problem 5.218
The circuit shown Fig. P5.218
called a foldedcurrent mirror
differential amplifier and is
useful for low values of power
supply. Assume that all W/L
values of each transistor is 100.
a.) Find the maximum input
common mode vol t age,
v
IC
(max) and the minimum
input common mode voltage,
v
IC
(min). Keep all transistors
in saturation for this problem.
b.) What is the input common
mode voltage range, ICMR?
c.) Find the small signal voltage gain, v
o
/v
in
, if v
in
= v
1
 v
2
.
d.) If a 10 pF capacitor is connected to the output to ground, what is the 3dB frequency
for V
o
(jω)/V
in
(jω) in Hertz? (Neglect any device capacitance.)
Solution
a.) v
1
(max) = V
DD
 V
DS6
(sat) + V
TN
= 1.5 
200
50·100
+ 0.7 = 1.5 – 0.2 + 0.7
∴ v
1
(max) = 2V
v
1
(min) = 0 + V
DS5
(sat) + V
GS1
(50µA) =
2·100
110·100
+
.

}
`
2·50
110·100
+ 0.7
= 0.1348 + 0953 + 0.7 = 0.9302V ⇒ v
1
(min) = 0.9302V
b.) ICMR = v
1
(max)  v
1
(min) = 1.0698V
c.) Using intuitive analysis approach gives:
i
d1
= g
m1
.

}
`
v
in
2
⇒ i
d3
= g
m1
.

}
`
v
in
2
⇒ i
d4
=g
m1
.

}
`
v
in
2
Also,
i
d2
= g
m2
.

}
`
v
in
2
. ∴ v
out
= R
out
(i
d2
+ i
d4
)
However, R
out
= r
ds2
r
ds4
r
ds7
=
1
g
ds2
+g
ds4
+g
ds7
⇒
v
out
v
in
=
g
m1
g
ds2
+g
ds4
+g
ds7
g
m1
= 2·50·110·100 = 1049µS, g
ds2
= g
ds4
= 0.04·50 = 2µS
and g
ds7
= 0.05·100 = 5µS
∴
v
out
v
in
=
1049
7
= 149.8V/V
d.) ω
3dB
=
1
R
out
10pF
=
7x10
6
10x10
12
= 0.7x10
6
→ ∴ f
3dB
= 111.4kHz
M1 M2
M6 M7
M5
M3
M4
v
out
+1.5V
100µA
M8 M9
M10
v
1
v
2
Fig. P5.218
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 527
Problem 5.219
Find an expression for the
equivalent input noise voltage
of Fig. P5.218, v
eq
2
, in terms
of the small signal model
parameters and the individual
equivalent input noise voltages,
v
ni
2
, of each of the
transistors (i = 1 through 7).
Assume M1 and M2, M3 and
M4, and M6 and M7 are
matched.
Solution
Equivalent noise circuit:
v
1
M1 M2
M6 M7
M4
v
out
V
DD
V
SS
*
e
n6
2
*
e
n1
2
*
e
n2
2
v
1
*
e
n7
2
*
e
n3
2
M3 *
e
n4
2
S99FES6
e
2
out
= (g
m1
2
e
2
n1
+ g
m2
2
e
2
n2
+ g
m3
2
e
2
n3
+ g
m4
2
e
2
n4
+ g
m5
2
e
2
n6
+ g
m6
2
e
2
n7
)R
out
2
e
2
eq
=
e
2
out
(g
m1
R
out
)
2
= e
2
n1
+ e
2
n2
+
.

}
`
g
m1
g
m3
2
( e
2
n3
+ e
2
n4
)+
.

}
`
g
m1
g
m6
2
( e
2
n6
+ e
2
n7
)
If M1 through M2 are matched then g
m1
= g
m3
and we get
e
2
eq
= 4 e
2
n1
+ 2
.

}
`
g
m1
g
m6
2
e
2
n6
M1 M2
M6 M7
M5
M3
M4
v
out
+1.5V
100µA
M8 M9
M10
v
1
v
2
Fig. P5.218
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 528
Problem 5.220
Find the small signal transfer
function V
3
(s)/V
in
(s) of Fig. P5.2
20, where V
in
= V
1
V
2
, for the
capacitors shown in algebraic
form (in terms of the small signal
model parameters and
capacitance). Evaluate the low
frequency gain and all zeros and
poles if I = 200µA and C
1
= C
2
=
C
3
= C
4
= 1pF. Let all W/L = 10.
Solution
Smallsignal model:L
Σi
A
= 0: (G
out
= g
ds1
+ g
ds5
)
0.5g
m1
v
in
+ sC
1
v
3
+ G
out
v
3
+ g
m5
v
6
= 0
Σi
B
= 0: sC
2
v
6
+ g
m6
v
6
= 0.5g
m3
v
in
= 0 → v
6
=
.

}
` 0.5g
m3
sC
2
+ g
m6
v
6
g
m1
v
in
2
r
ds1
r
ds5
C
1
g
m5
v
6
1
g
m6 r
ds3
r
ds6
C
2
g
m3
v
in
2
v
3
v
6
A B
From the first equation we get,
v
3
(sC
1
+ G
out
) + g
m5
.

}
` 0.5g
m3
sC
2
+ g
m6
v
in
+ 0.5g
m1
v
in
= 0
Solving for v
3
gives,
v
3
v
in
=
.

}
` 0.5g
m1
sC
1
+ G
out
.

}
` sC
2
+ g
m5
+ g
m6
sC
2
+ g
m6
When s → 0,
v
3
v
in
=
g
m1
g
ds1
+ g
ds5
g
mN
= 2·50µA·110x10
6
·10 = 331.6µS, g
mP
= 2·50µA·50x10
6
·10 = 223.6µS,
r
dsN
=
1
0.04·50x10
6
= 0.5MΩ, and r
dsP
=
1
0.05·50x10
6
= 0.4MΩ
∴
v
3
v
in
=  g
mN
·R
out
= (331.6)(0.50.4) = 73.69 V/V
Poles are at,
p
1
=
1
R
out
C
1
=
1
22.22kΩ·1pF
= 4.5x10
6
rad/s & p
2
=
g
m6
C
2
=
223.6µS
1pF
= 223.6 x10
6
rad/s
A zero is at, z
1
=
(g
m5
+ g
m6
)
C
2
=
(223.6µS + 223.6µS)
1pF
= 447.2 x10
6
rad/s
V
Bias
v
1
v
2
v
1
v
3
v
4
V
DD
M1
M2 M3
M4
M5 M6 M7 M8
M9
I
C
1
C
2
C
3
C
4
Fig. P5.220
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 529
Problem 5.221
For the differentialin, differentialout amplifier of Fig. 5.213, assume that all W/L
values are equal and that each transistor has approximately the same current flowing
through it. If all transistors are in the saturation region, find an algebraic expression for
the voltage gain, v
out
/v
in
, and the differential output resistance, R
out
, where v
out
= v
3
v
4
and v
in
= v
1
v
2
. R
out
is the resistance seen between the output terminals.
Solution
( )
( ) ( )
3 1
1
2 1
4 3
ds ds
m
in
out
g g
g
v v
v v
v
v
+
−
−
−
or,
( )
( )
2
3 1
1
’
2
λ λ +
−
BIAS
N
in
out
I
L
W
K
v
v
Considering differential output voltage swing, the output resistance can be given by
( ) ( )
4 2 3 1
1 1
ds ds ds ds
out
g g g g
R
+
+
+
or,
( ) ( )
3 1 3 1
2 2
λ λ +
+
BIAS ds ds
out
I g g
R
Problem 5.222
Derive the maximum and minimum input common mode voltage for Fig. 5.215
assuming all transistors remain in saturation. What is the minimum power supply
voltage, V
DD
, that will give zero common input voltage range?
Solution
The minimum input commonmode voltage is given by
5 1 1
(min)
dsat dsat T IC
V V V V + +
The maximum input commonmode voltage is given by
3 1
(max)
dsat T DD IC
V V V V − +
Assuming all the
dsat
V voltages to be the same, the minimum supply voltage for zero
input common mode can be given by
0 (min) (max) −
IC IC
V V
or, ( ) ( ) 0
5 1 1 3 1
+ + − − +
dsat dsat T dsat T DD
V V V V V V
or, V
DD
≈ 3V
ds
(sat)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 530
Problem 5.223
Find the slew rate, SR, of the differential amplifier shown
where the output is differential (ignore commonmode
stability problems). Repeat this analysis if the two current
sources, 0.5I
SS
, are replaced by resistors of R
L
.
Solution
a.) Slew rate of the differential output amplifier with
constant current source loads.
Under large signal swing conditions, the maximum
current that can be carried by each of the two transistors
1
M and
2
M is
SS
I . Due to the presence of constant
current sources as loads, the maximum charging or
discharging current through
L
C would be
SS
I 5 . 0 . Thus,
the slew rate can be given by
SR =
I
SS
2C
L
b.) Slew rate of the differential output amplifier with resistive loads.
In presence of resistive loads, the maximum charging or discharging current through
L
C would be
SS
I . Thus, the slew rate can be given by
SR =
I
SS
C
L
V
DD
V
SS
M1 M2
C
L
+ 
v
OUT
I
SS
0.5I
SS
0.5I
SS
Fig. P5.223
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 531
Problem 5.224
If all the devices in the differential amplifier shown in Fig. 5.25 are saturated, find the
worstcase inputoffset voltage V
OS
using the parameters of Table 3.12. Assume that
10(W
4
/L
4
10(W
3
/L
3
) W
2
/L
2
W
1
/L
1
10 µm/10 µm. State and justify any
assumptions used in working this problem.
Solution
The offset voltage between the input terminals is given by
2 1 GS GS os
V V V −
The drain current equations are
( )
2
1 1
1
1
2
T GS D
V V I −
β
( )
2
2 2
2
2
2
T GS D
V V I −
β
or,
( )
2
2
1
1
1 2 2 1
2 2
β β
D D
T T GS GS os
I I
V V V V V − + − −
Mismatches would cause I
D1
≠ I
D2
. But, to simplify the problem, it can be assumed that
SS D D
I I I 5 . 0
2 1
. Under this assumption and considering the mismatches in
T
V and
β
only, the worstcase inputoffset voltage (from Table 3.12) can be given by
β β 1 . 1 9 . 0
3 . 0
SS SS
os
I I
V − +
Assuming
100
SS
I
A µ
( )( ) ( )( ) 10 / 10 110 1 . 1
100
10 / 10 110 9 . 0
100
3 . 0
µ
µ
µ
µ
− +
os
V = 0.48 V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 532
Problem 5.301
Calculate the smallsignal voltage gain for the cascode
amplifier of Fig. 5.32 assuming that the dc value of v
IN
is
selected to keep all transistors in saturation. Compare this
value with the slope of the voltage transfer function given
in this figure.
Solution
The smallsignal voltage gain can be approximated as
3
1
ds
m
v
g
g
A − ≅
or,
( )
2
3 3
1
’
2
λ
D
N
v
I
L W K
A − ≅
I
D
is calculated from M3 as,
I
D
=
K
P
'W
2
2L
2
(V
SG3
V
TP
)
2
= 50·(2.70.7)
2
µA = 200µA
∴ A
v
=
2K
N
'(W
1
/L
1
)
I
D
λ
N
2
=
2·50·2
200·0.05·0.05
= 20 V/V
From the transfer characteristics, the smallsignal gain is approximately 10 V/V.
M2
M1
v
IN
v
OUT
I
D
5V
+

+

W
3
L
3
=
2µm
1µm
W
1
L
1
=
2µm
1µm
2.3V
3.4V
W
2
L
2
=
2µm
1µm
M3
Fig. P5.32
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 533
Problem 5.302
Show how to derive Eq. (5.36) from Eqs. (5.33) through (5.35). Hint: Assume that
V
GG2
V
T2
is greater than v
DS1
and express Eq. (5.34) as i
D2
≈ β
2
(V
GG2
V
T2
)v
DS2
. Solve
for v
OUT
as v
DS1
+ v
DS2
and simplify accordingly.
Solution
From Eqs. (5.33) through (5.35)
( )
1 1 1 1 ds T DD D
V V V I − ≅ β
( )( )
1 2 1 2 2 2 ds out T ds GG D
V V V V V I − − − ≅ β
( )
2
3 3 3 3
5 . 0
T GG DD D
V V V I − − β
Assuming, when
in
V is taken to
DD
V , the magnitudes of
1 ds
V and
out
V are small.
Equating
3 1 D D
I I
( ) ( )
2
3 3 3 1 1 1
5 . 0
T GG DD ds T DD
V V V V V V − − − β β
or,
( )
( )
1 1
2
3 3 3
1
5 . 0
T DD
T GG DD
ds
V V
V V V
V
−
− −
β
β
(1)
Equating
2 1 D D
I I
( ) ( )( )
1 2 1 2 2 1 1 1 ds out T ds GG ds T DD
V V V V V V V V − − − − β β
or, ( ) ( )( )
1 2 2 1 1 ds out T GG ds T DD
V V V V V V V − − −
or,
( )
( )
2 1 2
2 2
1
T T GG DD
T GG out
ds
V V V V
V V V
V
− − +
−
(2)
From Eqs. (1) and (2), the minimum output voltage is given by
V V V V
V V V V
out
DD GG T
DD T GG T
(min) − −
( )
−
( )
+
−
( )
]
]
]
β
β
3
1
3 3
2
1 2 2
2
1 1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 534
Problem 5.203
Redrive Eq. (5.36) accounting for the channel modulation where pertinent.
Solution
From Eqs. (5.33) through (5.35)
( )
1 1 1 1 ds T DD D
V V V I − ≅ β
( )( )
1 2 1 2 2 2 ds out T ds GG D
V V V V V I − − − ≅ β
( ) ( ) ( )
out DD T GG DD D
V V V V V I − + − −
3
2
3 3 3 3
1 5 . 0 λ β
Assuming, when
in
V is taken to
DD
V , the magnitudes of
1 ds
V and
out
V are small.
Equating
3 1 D D
I I
( ) ( ) ( ) ( )
out DD T GG DD ds T DD
V V V V V V V V − + − − −
3
2
3 3 3 1 1 1
1 5 . 0 λ β β
or,
( ) ( ) ( )
( )
1 1
3
2
3 3 3
1
1 5 . 0
T DD
out DD T GG DD
ds
V V
V V V V V
V
−
− + − −
β
λ β
(1)
Equating
2 1 D D
I I
( ) ( )( )
1 2 1 2 2 1 1 1 ds out T ds GG ds T DD
V V V V V V V V − − − − β β
or, ( ) ( )( )
1 2 2 1 1 ds out T GG ds T DD
V V V V V V V − − −
or,
( )
( )
2 1 2
2 2
1
T T GG DD
T GG out
ds
V V V V
V V V
V
− − +
−
(2)
From Eqs. (1) and (2), assuming
DD out DD
V V V ≅ − , the minimum output voltage is
given by
V V V V
V V V V
V
out
DD GG T
DD T GG T
DD
(min) − −
( )
−
( )
+
−
( )
]
]
]
+
( )
β
β
λ
3
1
3 3
2
1 2 2
3
2
1 1
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 535
Problem 5.304
Show that the small signal input resistance looking in the source
of M2 of the cascode amplifier of Fig. 5.31 is equal to r
ds
if the
simple current source, M3 is replaced by a cascode current
source.
Solution
The effective resistance of the cascoded PMOS transistors is
represented by
3 D
R and it is given by
4 3 3 3 ds ds m D
r r g R ≅
Referring to the smallsignal model in the figure
v g v
v v
r
R
m
x
x
ds
D 1 2
1
2
3
+
−
( )
]
]
]
or,
( )
( )
x
ds D
D ds m
v
r R
R r g
v
2 3
3 2 2
1
1
+
+
(1)
Now
( )
1 2
1
2
ds
x
ds
x
x m x
r
v
r
v v
v g i +
−
+
1 2 1 2 2
) ( v g v g g g i
ds x ds ds m x
− + +
1 2 2
v g v g i
ds x m x
− ≅
Replacing
1
v from Eq. (1) and assuming
2 3 ds D
r R >>
( ) [ ]
3
3 2 2 3 2
D
D m ds D m
x x
R
R g r R g
v i
− +
≅
or,
2 2
3
2
ds m
D
x
x
S
r g
R
i
v
R ≅
or,
2 2
4 3 3
2
ds m
ds ds m
S
r g
r r g
R = r
ds
V
DD
M
4
V
GG4
M
3
V
GG3
V
out
R
D3
R
S2
V
GG2
V
in
V
SS
M
1
M
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 536
Problem 5.305
Show how by adding a dc current source from V
DD
to the drain of M1 in Fig. 5.31 that the small
signal voltage gain can be increased. Derive an
expression similar to that of Eq. (11) in terms of
I
D1
and I
D4
where I
D4
is the current of the added
dc current source. If I
D2
10 µA, what value for
this current source would increase the voltage gain
by a factor of 10. How is the output resistance
affected?
Solution
Assuming all the transistors are in saturation
4 2 1 D D D
I I I +
3
1
ds
m
v
g
g
A − ≅
or,
( )
2
3
2
2
4 2
1
’
2
λ
D
D D N
v
I
I I
L
W
K
A
+
}
`
.

− ≅
or,
2
4
1
D
D
vo v
I
I
A A + ≅
where,
2
3 2
1
’
2
λ
D
N
vo
I
L
W
K
A
}
`
.

− is the gain in absence of the current source
4 D
I
Thus,
2
4
1
D
D
vo
v
I
I
A
A
+
The smallsignal voltage gain can be increased by making
2 4 D D
I I >> . In order to
achieve
10
vo
v
A
A
→
2
4
1 10
D
D
I
I
+
or,
990 99
2 4
D D
I I
A µ
The output resistance can be given by
[ ]
3 1 2 2

ds ds ds m out
r r r g R ≅
The value of
1 ds
r decreases due to increased current through
1
M
, thus decreasing the
overall output resistance.
V
DD
M
3
V
GG3
V
out
V
GG2
V
in
V
SS
M
1
M
2
I
D4
Fig. S5.305
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 537
Problem 5.306
Assume that the dc current in each transistor in
Fig. P5.36 is 100µA. If all transistor have a W/L
of 10µm/1µm, find the small signal voltage gain,
v
out
/v
in
and the small signal output resistance,
R
out
, if all transistors are in the saturated region.
Solution
This circuit is a folded cascode amplifier. The
small signal analysis is best done by the
schematic analysis approach. In words, v
i n
creates a current flowing into the drain of M1 of
g
m1
v
in
. This current flows through M4 from
drain to source back around to M1. The output
voltage is simply this current times R
out
. The
details are:
v
out
= g
m1
R
out
v
in
R
out
≈ [r
ds6
(g
m5
r
ds5
)][(r
ds1
r
ds2
r
ds3
)(g
m4
r
ds4
)]
The various small signal parameters are:
g
mN
= 2·110·100·10 = 469µS, g
mP
= 2·50·100·10 = 316.2µS
r
dsN
=
25V
100µA
= 0.25MΩ and r
dsP
=
20V
100µA
= 0.2MΩ
∴ R
out
≈ 29.31MΩ(0.0667MΩ)(63.2) = 29.31MΩ4.216MΩ = 3.686MΩ
R
out
= 3.686MΩ
v
out
v
in
= (469µS)(3.686MΩ) = 1,729 V/V
+5V
V
P1
V
N2
V
N1 M1
M2
M3
V
P2 M4
M5
M6
v
out
v
in
R
out
Fig. P5.36
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 538
Problem 5.307
Six versions of a cascode amplifier are shown below. Assume that K'
N
= 2K'
P
, λ
P
= 2λ
N
,
all W/L ratios of all devices are equal, and that all bias currents in each device are equal.
Identify which circuit or circuits have the following characteristics: (a.) highest small
signal voltage gain, (b.) lowest small signal voltage gain, (c.) the highest output
resistance, (d.) the lowest output resistance, (e.) the lowest power dissipation, (f.) the
highest V
out
(max), (g.) the lowest V
out
(max), (h.) the highest V
out
(min), (i.) the lowest
V
out
(min), and (j.) the highest 3dB frequency.
v
OUT
v
IN
v
OUT
v
IN
v
OUT
v
IN
v
OUT
v
IN
v
OUT
v
IN
v
OUT
v
OUT
v
IN
Circuit 1
V
BP1
V
BP2
V
DD
V
BN2
V
BN1
Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6
Figure P5.37
Solution
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6
g
m
g
mN
g
mP
g
mN
g
mP 2 g
mN
2 g
mP
R
out ≈ r
dsP
≈ r
dsN
R* R*
≈ r
dsP
≈ r
dsN
R* = (g
mP
·r
dsP
2
)(g
mN
·r
dsN
2
) Note that g
mN
= 2 g
mP
and r
dsN
= 2r
dsP
e.) Circuit 3 has the highest gain.
f.) Circuit 1 has the lowest gain.
g.) Circuits 3 and 4 have the highest output resistance.
h.) Circuits 1 and 5 have the lowest output resistance.
i.) Circuits 14 have the lowest power dissipation.
j.) Circuits 1 and 5 have the highest V
out
(max).
k.) Circuit 4 has the worst (lowest) V
out
(max).
l.) Circuits 2 and 6 have the best (lowest) V
out
(min).
m.) Circuit 3 has the worst (highest) V
out
(min).
n.) Circuits 1 and 5 have the highest –3dB frequency because of lowest R
out
.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 539
Problem 5.308
All W/L ratios of each transistor in the
amplifier shown in Fig. P5.38 are 10µm/1µm.
Find the numerical value of the small signal
voltage gain, v
out
/v
in
, and the output resistance,
R
out
.
Solution
The output resistance can be given as
[ ]
4 3 3 1 2 2

ds ds m ds ds m out
r r g r r g R ≅
Neglecting body effects
469
2 1
m m
g g S µ
316
4 3
m m
g g
S µ
4
2 1
ds ds
g g
S µ
5
4 3
ds ds
g g
S µ
Thus, [ ] M M R
out
64 . 12  31 . 29 ≅
or, R
out
≈ 8.838 M Ω
The smallsignal voltage gain is given as
v
v
g R
out
in
m out
−
1
= 41.42 V/V
R
out
v
out
v
in
M1
M2
M3
M4
M5
M6
M7
M8
V
DD
100µA
Figure P5.38
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 540
Problem 5.309
Use the Miller simplification described in Appendix A on the capacitor C
2
of Fig. 5.3
5(b) and derive an expression for the pole, p
1
, assuming that the reactance of C
2
at the
frequency of interest is greater than R
3
. Compare your result with Eq. (5.332).
V
in
/R
s
R
1 C
1
(1A
v
)C
2
V
1
g
m1
V
1
C
3
A
v
(A
v
1)
C
2
R
3
V
out
sC
2
<<R
3
V
in
/R
s
R
1
C
1
(1A
v
)C
2
V
1
g
m1
V
1
C
3
R
3
V
out
Fig. S5.309
Solution
Given that in the frequency of interest, the reactance of C
2
is greater than 1
3
/ R
or, 2
1
2
3
πfC
R
>>
Referring to the figure
V s
V s
R
R
s C A C
in
S v
1
1
1 2
1
1
( )
( )
+ + + ( ) ( )
]
]
]
(1)
where, A g R
v m
1 3
Also, V s
g V s
R
sC
g V s
sC
o
m m
( )
( ) ( )
−
+

.
`
}
≅
−
1 1
3
3
1 1
3
1
or, V s
g
R
sC
V s
R
R
s C A C
o
m in
S v
( )
( )
−
+

.
`
}
+ + + ( ) ( )
]
]
]
1
3
3
1
1 2
1 1
1
(2)
The dominant pole in Eq. (2) can be expressed as
p
R A C C R A C
v v
1
1 2 1 1 2
1 1
−
+ ( )
≅
−
( )
or, p
1
=
1
g
m1
R
1
R
3
C
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 541
Problem 5.310
Consider the currentsource load inverter of Fig. 5.15 and the simple cascode amplifier
of Fig. 5.31. If the W/L ratio for M2 is 1 µm/1 µm and for M1 is 3 µm/1 µm of Fig. 5.1
5, and W
3
/L
3
1 µm/1 µm, W
2
/L
2
W
1
/L
1
3 µm/1 µm for Fig. 5.31, compare the
minimum outputvoltage swing, v
OUT
(min) of both amplifiers if V
GG2
0 V and V
GG3
2.5 V when V
DD
−V
SS
5 V.
Solution
a) Current source load inverter
When
DD in
V V , it can be assumed that
1
M operates in the triode region and
2
M is in saturation. Thus,
( )( ) ( )
2
2 2 2 1 1
5 . 0 (min)
T SG SS out T SS DD
V V V V V V V − − − − β β
or,
( )
( )
SS
T SS DD
T SG
out
V
V V V
V V
V +
− −
−
1 1
2
2 2 2
5 . 0
(min)
β
β
Assuming, 5
2
SG
V V
V
out
(min) = 4.85 V
b) Simple cascode amplifier
2 1
(min)
dsat dsat SS out
V V V V + +
or,
( ) ( )
2
’
2
1
’
1
2 2
(min)
L W K
I
L W K
I
V V
N
D
N
D
SS out
+ +
Now,
( ) 81
2
2
3 3
3
3
− −
T GG DD D
V V V I
β
A µ
Thus, V
out
(min) = 3.6 V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 542
Problem 5.311
Use nodal analysis techniques on the cascode amplifier of Fig. 5.36(b) to find v
out
/v
in
.
Verify the result with Eq. (5.337) of Sec. 5.3.
Solution
Nodal analysis of cascode amplifier
Applying KCL
( )
1 2 1 2 1 2 1 1 1
v v g v g v g v g v g
out ds mbs m ds in m
− + + +
or,
out ds ds mbs m ds in m
v g v g g g g v g
2 1 2 2 2 1 1
) ( + + + +
or,
( )
) (
2 2 2 1
1 2
1
ds mbs m ds
in m out ds
g g g g
v g v g
v
+ + +
−
(1)
Again, applying KCL
( ) 0
4 3 4 3 4 3 4 4
+ + − + v g v g v v g v g
mbs m out ds ds
or,
( )
out
mbs ds ds m
ds
v
g g g g
g
v
3 4 3 3
3
4
+ + +
(2)
Also,
( ) ( ) ( ) ( ) 0
1 2 1 2 2 4 3 4 3 3
− + + + − + +
out ds mbs m out ds mbs m
v v g v g g v v g v g g
or, ( ) ( ) ( )
out ds ds ds mbs m ds mbs m
v g g v g g g v g g g
4 3 1 2 2 2 4 3 3 3
+ + + + + + (3)
Using Eqs. (1) through (3) and neglecting body effect, it can be shown that
( )
4 3 2 2 1 3
3 2 1
ds ds m ds ds m
m m m
v
g g g g g g
g g g
A
+
−
or,
}
`
.

+
−
3
4 3
2
2 1
1
m
ds ds
m
ds ds
m
v
g
g g
g
g g
g
A
or,
( )
( ) ( )
}
`
.

+
−
3
’
3
4 3
2
’
2
2 1
1
’
1
2 2
2
L W K L W K
I
L W K
A
D
v
λ λ λ λ
Eq. (5.337)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 543
Problem 5.312
Find the numerical value of the small signal
voltage gain, v
out
/v
in
, for the circuit of Fig.
P5.312. Assume that all devices are saturated
and use the parameters of Table 3.12. Assume
that the dc voltage drop across M7 keeps M1 in
saturation.
Solution
I I
D D 3 2
20 µA
I
D3
220 µA
Now,
g
m1
440 µS and r
ds1
113 64 . kΩ
g
m2
132 67 . µS and r
ds2
1 25 . kΩ
r
ds3
1 MΩ
Thus,
R r g r r
out ds m ds ds
[ ]
3 2 2 1

or, R M M
out
[ ] 1 18 8 950  . kΩ
So,
A g R
v m out
−
1
= 418 V/V
20µA
4/1
4/1 40/1
4/1
M1
M2
M3
M4 M5 M6
M7
4/1
4/1
v
out
v
in
V
DD
Fig. P5.312
1/1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 544
Problem 5.313
A cascoded differential amplifier is shown in
Fig. P5.313.
(a) Assume all transistors are in saturation
and find an algebraic expression for the small
signal voltage gain, v
out
/v
in
.
(b) Sketch how would you implement V
Bias
?
(Use a minimum number of transistors.)
(c.) Suppose that I
7
+I
8
≠ I
9
. What would be
the effect on this circuit and how would you
solve it? Show a schematic of your solution.
You should have roughly the same gain and
the same output resistance.
Solution
a ) The effective transconductance is
given by
g
g
m eff
m
,
1
2
The output resistance of the cascoded output is given by
R
g g
g
g g
g
out
ds ds
m
ds ds
m
+
]
]
]
]
]
1
2 4
4
6 8
6
Thus, the smallsignal voltage gain is given by
A
g
g g
g
g g
g
v
m
ds ds
m
ds ds
m
+
]
]
]
]
]
0 5
1
2 4
4
6 8
6
.
b) The magnitude of V
BIAS
should be at least V V
GS dsat
+ . One way to implement V
BIAS
is shown in Fig. 6.51(b) of the text.
c) If the currents were not equal, the voltages at the drains of M3M5 and M4M6
will near V
DD
or near the sources of M1 and M2. Either, M5M8 or M1M4 will
not be saturated. The best way to solve this problem is through the use of
common mode feedback. This is illustrated in Fig. 5.215 of the text.
I
v
out
M12
M11
V
SS
V
DD
+

v
in
M1
M2
+

V
Bias
M3
M4
M5
M6
M7
M8
M9
M10
I
9
I
7
I
8
Fig. P5.313
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 545
Problem 5.314
Design a cascode CMOS amplifier using Fig. 5.37 for the following specifications. V
DD
= 5V, P
diss
≤ 0.5mW, A
v
 ≥ 100V/V, v
OUT
(max) = 3.5V, v
OUT
(min) = 1.5V, and slew
rate of greater than 5V/µs for a 5pF capacitor load. Verify your design by simulation.
Solution
1.) The slew rate should be at least 5 V/µs driving a 5 pF load. So, the load current
should be at least 25 µA.
Let,
I I I
D D D 3 2 1
25 µA
2.) The maximum output voltage swing should be at least 3.5 V
Let, V
dsat 3
1 5 . V
W
L
I
K V
D
P dsat

.
`
}
3
3
3
2
2
0 44
'
.
So, let us choose
W
L
W
L

.
`
}

.
`
}
3 4
1
3.) The smallsignal voltage gain should be at least 100
A g r
v m ds
≅ −
1 3
or,
W
L
A I
K
v D
N

.
`
}
( )
1
3
2
1
2
2 84
λ
'
.
So, let us choose
W
L

.
`
}
1
3
V
dsat1
0 39 . V
4.) The minimum output voltage swing should be greater than 1.5 V
V V V
out dsat dsat
(min) +
1 2
or, V V V
dsat out dsat 2 1
1 11 − (min) . V
or,
W
L
I
K V
D
N dsat

.
`
}
2
2
2
2
2
0 37
'
.
So, let us choose
W
L

.
`
}
2
1
5.) The bias voltage V
GG2
can be calculated as
V V V V
GG T dsat dsat 2 1 1 2
1 76 + + . V
6.) The power dissipation is given by
P I V
diss D DD
3
0 125 . mW
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 546
Problem 5.401
Assume that i
o
= A
i
(i
p
i
n
) of the current
amplifier shown in Fig. P5.41. Find v
out
/v
in
and compare with Eq. (5.43).
Solution
Referring to the figure, 0
p
i .
So, i A i i Ai
o i p n i n
−
( )
−
Now, v i R
in
1 1
v i R
o
−
2 2
or, v i i R
o n
− ( )
1 2
→ v
v
R
i
A
R
o
in o
i
+

.
`
}
1
2
or, v
v
R
v
R
A
R
o
in
o
i
+
−

.
`
}

.
`
}
1
2
2
→
v
v
R
R
A
o
in
i
+

.
`
}
2
1
1
1
Eq. (5.43)
Problem 5.402
The simple current mirror of Fig. 5.43 is to be used as a current amplifier. If the W/L of
M1 is 1µm/1µm, design the W/L ratio of M2 to give a gain of 10. If the value of I
1
is
100µA, find the input and output resistance assuming the current sources I
1
and I
2
are
ideal. What is the actual value of the current gain when the input current is 50µA?
Solution
The current gain can be expressed as
A
W L
W L
i
( )
( )
2
1
For A
i
10, W
2
10 µm and L
2
1 µm.
If I
1
100 µA, then I
2
1000 µA.
The input resistance is
R
g
in
m
1
1
= 6.74 k Ω
The output resistance is
R
I
out
N D
1
2
λ
= 25 k Ω
When I
1
50 µA, then I
2
500 µA and the current gain ( A
i
) is still 10.
v
s
R
1
R
2
i
n
i
o
Current
Amplifier
A
i
v
o
i
1
i
2
Figure P5.41
i
p
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 547
Problem 5.403
The capacitances of M1 and M2 in Fig. P.43
are C
gs1
=C
gs2
=20fF, C
gd1
=C
gd2
=5fF, and
C
bd1
=C
bd2
=10fF. Find the low frequency
current gain, i
out
/i
in
, the input resistance seen
by i
in
, the output resistance looking into the
drain of M2, and the 3dB frequency in Hz.
Solution
i
in
g
ds1
g
m1 C
1
g
m1
V
1
+

V
1
i
out
S99E2S3
(a.) Smallsignal model is shown.
Note that
C
1
=C
bd1
+ C
gs2
+ C
gd2
+ C
gs1
= 55fF,
g
m1
=g
m2
= 2K
N
·
W
1
L
1
I
1
= 2·110·5·100 = 332µS
and
g
ds1
= λ
N
I
1
= 0.04·100µA = 4µS
The current gain is, i
out
= g
m2
.

}
`
i
in˚
g
m1
+g
ds1
+sC
1
The low frequency current gain is
A
i
(0) =
g
m2
g
m1
+g
ds1
=
332
336
= 0.988⇒ A
i
(0) = 0.988
R
in
=
1
g
m1
+g
ds1
=
1
336µS
= 2.796kΩ ⇒ R
in
= 2796Ω
R
out
= 1/g
ds2
= 1/g
ds1
= 250kΩ ⇒ R
out
= 250kΩ
ω
3dB
=
g
m1
+g
ds1
C
1
=
332µS+4µS
55fF
= 6.11x10
9
⇒ f
3dB
= 973MHz
V
DD
V
DD
i
in
i
out
M1
M2
Fig. P5.43
100µA 100µA
R
L
=0
5µm/1µm
5µm
1µm
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 548
Problem 5.404
Derive an expression for the smallsignal
input resistance of the current amplifier
of Fig. 5.45(a). Assume that the current
sink, I
3
, has a small signal resistance of
r
ds4
in your derivation.
Solution
Referring to the figure
x s
v v
3
( )
x
ds ds
m
d g
v
g g
g
v v
4 3
3
3 1
+
≅
3 1 d d x
i i i +
or,
x m g m x
v g v g i
3 1 1
+
or,
( )
x m x
ds ds
m
m x
v g v
g g
g
g i
3
4 3
3
1
+
+
or,
( )
3 1
4 3
m m
ds ds
x
x
in
g g
g g
i
v
R
+
≅
Problem 5.405
Show how to make the current accuracy of Fig. 5.45(a) better by modifying the circuit
so that V
DS1
= V
DS2
.
Solution
Referring to the figure, M3M6 form a
differential amplifier. If it is assumed that the small
signal gain of this differential amplifier is large
enough, then the bias voltages at the gates of M3 and
M4 would almost be equal (because in presence of
large gain, the differential input ports would act as null
ports). Thus, the drain bias voltages of M1 and M2
would almost be identical causing very good
mirroring.
It is also important to note that the bias voltage
at the drain of M4 could be very large as gate bias
voltages for M1 and M2. One can use a PMOS
differential amplifier in place of the shown NMOS
differential amplifier to overcome this problem.
V
x
i
x
M
1
M
2
r
ds4
M
3
V
GG3
I
1
I
2
V
DD
M
1
M
2
I
1
I
2
V
DD
I
3
M
3
M
4
M
5
M
6
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 549
Problem 5.406
Show how to use the improved highswing current mirror of Sec. 4.4 to implement Fig.
5.47(a). Design the current amplifier so that the input resistance is 1kΩ and the dc bias
current flowing into the input is 100µA (when no input current signal is applied) and the
dc voltage at the input is 1.0V.
Solution
The highswing cascode current
mi r r or , constituting the
transistors M1 through M4, is
shown in the figure. The overall
figure shows a differential current
amplifier. To design the high
swing cascode current mirror, it is
desired that
1
in
R kΩ
or, 1
1
m
g µS
or,
W
L
W
L

.
`
}

.
`
}
1 2
45 5 .
Let us assume
W
L
W
L

.
`
}

.
`
}
3 4
45 5 .
Then, ignoring bulk effects
V V V V
BIAS T dsat dsat
+ +
3 3 1
1 1 . V
V
Bias
=
V
T
+
2V
ON
2I I I
V
DD
i
1
i
2
i
2
i
1
i
2
i
1
i
2
i
out
M1 M2
M3 M4
M5 M6
M7 M8
Fig. S5.406
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 550
Problem 5.407
Show how to use the regulated cascode mirror of Sec. 4.4 to implement a singleended
input current amplifier. Calculate an algebraic expression for the small signal input and
output resistance of your current amplifier.
Solution
i
in
M
4 M
2
i
out
M
3
M
1
v
s3
v
g3
v
gs3
=(g
m1
r
ds1
)v
s3
+

r
ds2
v
s3
g
m3
v
gs3
r
ds3
v
x
i
x
Referring to the figure, the current gain of the regulated cascode mirror can be expressed
as
A
i
i
W L
W L
i
out
in
≅
( )
( )
2
4
The input resistance is given by
R
g
in
m
1
4
The output resistance can be calculated as follows:
v g r v
g m ds s 3 1 1 3
−( ) (1)
Now, i g v
v v
r
x m gs
x s
ds
+
− ( )
3 3
3
3
or, i g g r v
v v
r
x m m ds s
x s
ds
− ( ) +
− ( )
3 1 1 3
3
3
(2)
Also, v i r
s x ds 3 2
(3)
Using Eqs. (2) and (3), it can be shown that
v i g r g r r
x x m ds m ds ds
( )
1 1 3 3 2
or, R
v
i
g r g r r
out
x
x
m ds m ds ds
( )
1 1 3 3 2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 551
Problem 5.408
Find the exact expression for the small signal
input resistance of the circuit shown when the
output is shortcircuited. Assume all transistors
have identical W/L ratios, are in saturation and
ignore the bulk effects. Simplify your expression
by assuming that g
m
=100g
ds
and that all
transistors are identical. Sketch a plot of i
out
as a
function of i
in
.
Solution
A small signal model for this problem is:
g
m4
v
gs4
r
ds4
r
ds2
+

v
gs3
R
in
r
ds3
+

v
gs4

+
i
t
v
t
D2=G3=S4 D4
D3=G4
S2=S3
g
m3
v
gs3
i
t
= (g
ds2
+g
ds4
)v
t
 g
m4
v
gs4
But, v
gs4
= g
m3
r
ds3
v
gs3
 v
t
and
v
gs3
= v
t
∴ i
t
= (g
ds2
+g
ds4
)v
t + gm4
(1+g
m3
r
ds3
)v
t
Thus, R
in
is
R
in
=
v
t
i
t
=
1
g
ds2
+g
ds4
+g
m4
+ g
m3
g
m4
r
ds3
≈
1
g
m3
g
m4
r
ds3
Sketching i
out
as a function of i
in
:
Note that i
D4
= I + i
out
and i
D4
+ i
in
= i
D2
= i
D1
= I
Therefore, I + i
out
= I  i
in
⇒ i
out
=  i
in
V
DD
i
out
i
in
I I I
R
in
M1 M2
M3
M4
Figure P5.48
i
out
i
in
1
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 552
Problem 5.409
Find the exact small signal expression for R
in
for
the circuit in Fig. P5.49. Assume V
DC
causes the
current flow through M1 and M2 to be identical.
Assume M1 and M2 are identical transistors and
that the small signal r
ds
of M5 can be ignored (do
not neglect r
ds1
and r
ds2
).
Solution
The smallsignal model is shown below.
We may write that,
v
in
= v
d1
= (i
in
– g
m1
v
gs1
)r
ds1
+ (i
in
+ g
m2
v
gs2
) r
ds2
but v
gs1
=  v
s1
and v
gs2
= v
g2
– v
s2
v
in
g
m1
v
gs1
r
ds1
+

v
d1
D1
i
in
g
m2
v
gs2
r
ds2
r
ds3
g
m2
v
d1
r
ds4
g
m4
v
d1
+

v
g2 S1=S2
G1=D2
G2 = D3 = D4
Fig. S5.49
∴ v
in
= i
in
r
ds1
+ g
m1
v
s1
r
ds1
+ i
in
r
ds2
+ g
m2
v
g2
r
ds2
 g
m2
v
s2
r
ds2
= i
in
r
ds1
+ i
in
r
ds2
+ g
m2
v
g2
r
ds2
= i
in
(r
ds1
+ r
ds2
)  g
m2
r
ds2
.

}
` g
m3
+ g
m4
g
ds3
+ g
ds4
v
in
∴ v
in
=
(r
ds1
+ r
ds2
)i
in
1 +
g
m2
r
ds2
(g
m3
+ g
m4
)
g
ds3
+ g
ds4
→ R
in
=
v
in
i
in
=
(r
ds1
+ r
ds2
)
1 +
g
m2
r
ds2
(g
m3
+ g
m4
)
g
ds3
+ g
ds4
or R
in
=
r
ds1
+ r
ds2
1 + g
m2
r
ds2
(g
m3
+ g
m4
)r
ds3
r
ds4
+

DC
V
b2
V
b1
V
DD
V
DD
M5
M1 M2
+

v
in
R
in
M3
M4
V
Fig. 5.49
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 553
Problem 5.410
A CMOS current amplifier is shown.
Find the small signal values of the
current gain, A
i
= i
out
/i
in
, input
resistance, R
in
, and output resistance,
R
out
. For R
out
, assume that g
ds2
/g
m6
is
equal to g
ds1
/g
m5
. Use the parameters
of Table 3.13.
Solution
Since this is a new circuit, use the
small signal model approach. The
model for this problem is given below.
i
out
= (g
m7
v
1
+ g
m8
v
2
)
= 
g
m7
i
1
g
m5

g
m8
i
2
g
m6
= 
g
m7
g
m5
(i
1
+i
2
) =
g
m7
g
m5
i
in
→ A
i
=
i
out
i
in
= 10
g
m2
v
in
r
ds2
g
m1
v
in
r
ds1
g
m7
v
1
v
1
v
2
1
g
m5
1
g
m6 g
m8
v
2 r
ds7
r
ds8
i
out
i
in
+

v
in
S98FES6
i
1
i
2
R
out
=
1
g
ds7
+g
ds8
=
1
(500µA)(0.04+0.05)
=
1
45µS
= 22.2kΩ
R
in
:
i
in
= g
m1
v
in
+ g
m2
v
in
+ g
ds1
(v
in
v
1
) + g
ds2
(v
in
v
2
)
= (g
m1
+g
m2
+g
ds1
+g
ds2
)v
in

g
ds1
i
1
g
m5

g
ds2
i
2
g
m6
= (g
m1
+g
m2
+g
ds1
+g
ds2
)v
in

g
ds1
g
m5
i
in
∴ R
in
=
v
in
i
in
=
1 +
g
ds1
g
m5
g
m1
+g
m2
+g
ds1
+g
ds2
, g
m1
= 2K
N
·10·50 = 331.7µS, g
ds1
= 2µS
g
m2
= 2K
P
·10·50 = 223.6µS, g
ds1
= 2.5µS, and g
m5
= g
m2
Thus, R
in
=
1 + 0.0112
331.7+223.6+2+2.5
= 1.8kΩ
+2V
50µA
50µA
M1
M2
M3
M4
M5
M6
M7
M8
i
in
i
out
10/1
10/1
10/1
10/1
10/1
10/1
100/1
100/1
S98FEP6 2V
R
in
R
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 554
Problem 5.411
Find the exact algebraic expression (ignoring bulk effects)
for the following characteristics of the amplifier shown.
Express your answers in terms of g
m
’s and r
ds
’s in the form
of the ratio of two polynomials.
(a.) The small signal voltage gain, A
v
= v
out
/v
in
., and current
gain, A
i
= i
out
/i
in
.
(b.) The small signal input resistance, R
in
.
∴ The small signal output resistance, R
out
.
Solution
(a.) Smallsignal model is shown below. Summing currents
at the output node gives:
g
m2
v
in
+ g
ds2
(v
in
v
out
) = g
ds3
v
out
or
v
out
v
in
=
g
m2
+g
ds2
g
ds2
+g
ds3
=
r
ds3
+g
m2
r
ds2
r
ds3
r
ds2
+r
ds3
+

v
in
i
in
r
ds1
r
ds2
r
ds3
g
m2
v
gs2
+

v
out
i
out
v
gs2
= v
in
+

v
in
i
in
r
ds1
r
ds2
r
ds3
g
m2
v
in
+

v
out
i
out
S98E2S3
R
i
(b.) The input resistance is best done by finding R and putting it in parallel with r
ds1
.
v
in
= (ig
m2
v
in
)r
ds2
+ ir
ds3
→ R =
v
in
i
=
r
ds2
+r
ds3
1+g
m2
r
ds2
∴ R
in
= r
ds1
R = r
ds1

.

}
`
r
ds2
+r
ds3
1+g
m2
r
ds2
→ R
in
=
r
ds1
(r
ds2
+r
ds3
)
r
ds1
+r
ds2
+r
ds3
+g
m2
r
ds2
r
ds1
(c.) R
out
= r
ds2
r
ds3
=
r
ds2
r
ds3
r
ds2
+r
ds3
V
DD
M3
R
out
v
out
R
in
v
in
100µA
M2
M1 M4
M5
M6
Figure P5.411
i
out
i
in
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 555
Problem 5.412
Find the exact expression for the small signal input
resistance of the circuit shown. Assume all
transistors have identical W/L ratios, are in
saturation and ignore the bulk effects. Simplify
your expression by assuming that g
m
=100g
ds
and
that all transistors are identical. Sketch a plot of
i
out
as a function of i
in
.
Solutions
A small signal model for this problem is:
g
m4
v
gs4
r
ds4
r
ds2
+

v
gs3
R
in
r
ds3
+

v
gs4

+
i
t
v
t
D2=G3=S4 D4
D3=G4
S2=S3
g
m3
v
gs3
i
t
= (g
ds2
+g
ds4
)v
t
 g
m4
v
gs4
But, v
gs4
= g
m3
r
ds3
v
gs3
 v
t
and
v
gs3
= v
t
∴ i
t
= (g
ds2
+g
ds4
)v
t + gm4
(1+g
m3
r
ds3
)v
t
Thus, R
in
is
R
in
=
v
t
i
t
=
1
g
ds2
+g
ds4
+g
m4
+ g
m3
g
m4
r
ds3
≈
1
g
m3
g
m4
r
ds3
Sketching i
out
as a function of i
in
:
Note that i
D4
= I + i
out
and i
D4
+ i
in
= i
D2
= i
D1
= I
Therefore, I + i
out
= I  i
in
⇒ i
out
=  i
in
M1
M2
M3
M4
i
out
V
DD
I I I
i
in
R
in
Figure P5.412
i
out
i
in
1
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 556
Problem 5.501
Use the values of Table 3.12 and design the W/L ratios of M1 and M2 of Fig. 5.51 so
that a voltage swing of ±3 volts and a slew rate of 5 volts/µs is achieved if R
L
10 kΩ
and C
L
1 nF. Assume that V
DD
−V
SS
5 volts and V
GG2
2 volts.
Solution
I
K W
L
V V V
D
P
DD GG T 2
2
2 2
2
2

.
`
}
− − ( )
'
For positive swing of the output voltage, the slew rate should be at least +5 V/µs.
SR
I
C
D
L
2
Thus, I I SR C
out D L
( )
2
5 mA
Now,
W
L
I
K V V V
D
P DD GG T

.
`
}
− − ( ) 2
2
2 2
2
2
'
→
W
L

.
`
}
≅
2
38/1
Also, for the output voltage to swing to +3 V, the load current into R
L
will be 0.3 mA.
Since I
D2
is greater than 0.3 mA, the output voltage would be greater than +3 V.
For negative output voltage swing
I SR C
out L
( ) 5 mA
I I I
D out D 1 2
10 − + mA
or,
W
L
I
K V V V
D
N DD SS T

.
`
}
− − ( ) 1
1
1
2
2
'
→
W
L

.
`
}
≅
1
2 1 . 3/1
For V
out
(min) −3 V, I
out
−0 3 . mA. Since I I I
D out D 1 2
> − + , the output will be able to
swing down to –3 V.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 557
Problem 5.502
Find the W/L of M1 for the source follower of Fig. 5.53a when V
DD
−V
SS
5 V, V
OUT
1 V, and W
2
/L
2
1 that will source 1 mA of output current. Use the parameters of
Table 3.12.
Solution
Given, V
out
1 V and V
SS
−5 V
So, V
GS2
6 V
I
K W
L
V V
D
N
GS T 2
2
2 2
2
2

.
`
}
− ( )
'
→ I
D2
1 55 . mA
Thus, I I I
D D out 1 2
+ = 2.55 mA
Due to body effects, the threshold voltage of M
1
can be given by
V V V V
T T out SS 1 0 1
+ − γ = 1.68 V
Now,
W
L
I
K V V V
D
N DD out T

.
`
}
− − ( ) 1
1
1
2
2
'
= 8.6/1
Problem 5.503
Find the smallsignal voltage gain and output resistance of the source follower of Fig.
5.53b. Assume that V
DD
−V
SS
5 V, V
OUT
1 V, I
D
50 µA, and the W/L ratios of
both M1 and M2 are 20 µm/10 µm. Use the parameters of Table 3.12 where pertinent.
Solution
The smallsignal voltage gain is given by
A
g
g g g
v
m
m ds ds
+ + ( )
1
1 1 2
V V V V
T T out SS 1 0 1
+ − γ → V
T1
1 68 . V
g K
W
L
I
m N D 1
1
1
2

.
`
}
'
→ g
m1
148 µS
g g
ds ds 1 2
4 5 + . µS
∴ A
v
= 0.943 V/V
The output resistance is given by
R
g g g
out
m ds ds
+ + ( )
1
1 1 2
= 6.37 k Ω
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 558
Problem 5.504
An output amplifier is shown. Assume that v
IN
can
vary from 2.5V to +2.5V. Let K
P
’ = 50µA/V
2
, V
TP
= 0.7V, and λ
P
= 0.05V
1
. Ignore bulk effects.
a.) Find the maximum value of v
OUT
, v
OUT
(max).
b.) Find the minimum value of v
OUT
, v
OUT
(min).
c.) Find the positive slew rate, SR
+
when v
OUT
= 0V
in volts/microseconds.
d.) Find the negative slew rate, SR

when v
OUT
= 0V
in volts/microseconds.
e.) Find the small signal output resistance (excluding the 10kΩ resistor) when v
OUT
=
0V.
Solution
∴ When v
IN
= +2.5V, the transistor is shut off and v
OUT
(max) = 200µA·10k Ω =
+2V
∴ When v
IN
= 2.5V, the transistor is in saturation (drain = gate) and the minimum
output voltage under steadystate is,
v
OUT
= 10kΩ(I
D
200µA) = 10kΩ
]
]
] 50·300
2
(v
OUT
+2.50.7)
2
 200µA
v
OUT
= 75(v
OUT
+1.8)
2
+2 → v
OUT
2
+3.6133v
OUT
+ 3.21333 = 0
∴ v
OUT
= 
3.61333
2
±
(3.61333)
2
 4·3.21333
2
1.80667 ± 0.22519
It can be shown that the correct choice is v
OUT
(min) = 1.80667 + 0.22519 = 1.5815V
c.) The positive slew rate is SR
+
=
200µA
50pF
= +4V/µs → SR
+
= +4V/µs
d.) The negative slew rate is found as follows. With v
OUT
= 0V, the drain current is
I
D
= 7.5mA/V
2
(2.50.7)
2
= 24.3mA
Therefore, the sourcing current is 24.3mA0.2mA = 24.1mA which gives a negative slew
rate of SR

=
24.1mA
50pF
=  482V/µs → SR

=  482V/µs
e.) The output resistance, R
out
, is approximately equal to 1/g
m
. Therefore,
R
out
≈
1
g
m
=
L
2K
P
I
D
W
=
1
2·50·200·300
= 408.2Ω → R
out
≈ 408 Ω
300/1
200µA
v
IN 50pF
10kΩ
v
OUT
+2.5V
2.5V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 559
Problem 5.505
An output amplifier is shown. Assume that
v
IN
can vary from 2.5V to +2.5V. Ignore
bulk effects. Use the parameters shown
below.
a.) Find the maximum value of v
OUT
,
v
OUT
(max).
b.) Find the minimum value of v
OUT
,
v
OUT
(min).
c.) Find the positive slew rate, SR
+
when
v
OUT
= 0V in volts/microseconds.
d.) Find the negative slew rate, SR

when
v
OUT
= 0V in volts/microseconds.
e.) Find the small signal output resistance when v
OUT
= 0V.
Solution
(a.) When v
IN
= 2.5V, the transistor shuts off and v
OUT
(max) = 200µA·10kΩ = +2V
(b.) Assume v
IN
= 2.5V. Therefore, the transistor is in saturation and the minimum
output voltage under steadystate is,
v
OUT
= 10kΩ(I
D
200µA) = 10kΩ
.

}
` 110x10
6
·300
2
(v
OUT
+2.50.7)
2
200µA
or
v
OUT
= 165(v
OUT
+1.8)
2
+ 2V → v
OUT
2
+ 3.6061 v
OUT
+ 3.228 = 0
∴ v
OUT
= 
3.6061
2
±
(3.6061)
2
 4·3.228
2
= 1.8030 ± 0.1516
It can be shown that the correct choice is v
OUT
= 1.8030 + 0.1516 = 1.6514V
Thus v
OUT
(min) = 1.6514V
(c.) The positive slew rate is SR
+
=
200µA
50pF
= +4V/µs
(d.) The negative slew rate is found as follows. With v
OUT
= 0V, the drain current is
I
D
=
110x10
6
·300
2
(2.50.7)
2
= 53.46mA
Therefore, the sourcing current is 53.46mA  0.2mA = 53.44mA which gives a negative
slew rate of SR

= 
53.44mA
50pF
= 1069V/µs
(e.) The output resistance, R
out
, is approximately equal to 1/g
m
. Therefore,
R
out
=
1
g
m
=
L
2KI
D
W
=
10
6
2·110·300·200
= 275.24Ω
300µm
200µA
v
IN
50pF 10kΩ
v
OUT
+2.5V
2.5V
Figure P5.55
1µm
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 560
Problem 5.506
For the circuit shown in Fig. P5.56, find the small signal voltage
gain, v
out
/v
in
and the small signal output resistance, R
out
. Assume
that the dc value of v
OUT
is 0V and that the dc current through
M1 and M2 is 200µA.
Solution
(Unfortunately the gatesource voltage is given on the schematic
which causes a conflict with the problem statement of 200µA of
current. We will use the 200µA in the solution.)
The smallsignal model for this problem is shown below.
+
v
out

i
out
g
m1
v
gs1
+  v
gs1
g
mb1
v
bs1
r
ds1
r
ds2
Fig. S5.56
g
m1
= 2·110·200·10 µS = 663.3µS, g
mb1
=
663.3µS(0.4)
2 0.7 + 5
= 55.57µS,
g
ds1
= g
ds2
= 0.04·200µA = 8µS
Summing currents at the output,
v
out
(g
ds1
+ g
ds2
) = g
m1
v
gs1
+ g
mb1
v
bs1
= g
m1
v
in
 g
m1
v
out
 g
mb1
v
out
(e.)
v
out
v
in
=
g
m1
g
m1
+ g
mb1
+ g
ds1
+ g
ds2
=
663.3
663.3 + 55.57 + 8 + 8
= 0.9026 V/V
R
out
=
v
out
i
out
=
1
g
m1
+ g
mb1
+ g
ds1
+ g
ds2
=
1
663.3 + 55.57 + 8 + 8
= 1361 Ω
+5V
3V
5V
5V
v
in
R
out
v
out
M2
M1
10/1
10/1
Fig. P5.56
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 561
Problem 5.507
Develop an expression for the efficiency of the source follower of Fig. 5.53b in terms of
the maximum symmetrical peakoutput voltage swing. Ignore the effects of the bulk
source voltage. What is the maximum possible efficiency?
Solution
Efficiency (η) is expressed as
η
max
sup
( )

.
`
}
− ( )
P
P
V peak
R
V V I
RL
ply
out
L
DD SS Q
2
2
The maximum output voltage swing is
V V V
out DD T
(max) ≅ −
1
The minimum output voltage swing is
V V
out SS
(min) ≅
Assuming symmetrical maximum positive and negative output swings
V peak V V
out DD T
( ) ≅ −
1
The quiescent current can be expressed as
I
V V
R
Q
out out
L
− ( ) (max) (min)
2
or, I
V V V
R
Q
DD SS T
L
− − ( )
1
2
Thus,
η
max
( )

.
`
}
− ( )
− ( )
− ( ) − − ( )
V peak
R
V V I
V V
V V V V V
out
L
DD SS Q
DD T
DD SS DD SS T
2
1
2
1
2
Assuming V V
DD SS
− 5 V gives η
max
≈ 20%
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 562
Problem 5.508
Find the pole and zero location of the source followers of Fig. 5.53a and Fig. 5.53b if
C
gs1
C
gd2
5fF and C
bs1
C
bd2
30fF and C
L
1 pF. Assume the device parameters
of Table 3.12, I
D
100 µA, W
1
/L
1
W
2
/L
2
10 µm/10 µm, and V
SB
5 volts.
Solution
v
gs
+

R
L2
=(g
m2
+g
ds2
+g
L
)
1
v
out
g
m1
v
gs
r
ds1
v
in
C
gs1
C
gd1
C
L
a.) Referring to the figure
The location of the zero of the follower is given by
z
g
C
m
gs
−
1
1
= 14.9 GHz
The location of the pole of the follower is given by
p
g g g g g
C C C C C
m m ds ds L
gs gs bd bd L
− + + + + ( )
+ + + + ( )
1 2 1 2
1 2 1 2
= 140.8 MHz
b.) Referring to the figure
The location of the zero of the follower is given by
z
g
C
m
gs
−
1
1
= 14.9 GHz
The location of the pole of the follower is given by
p
g g g g
C C C C C
m ds ds L
gs gs bd bd L
− + + + ( )
+ + + + ( )
1 1 2
1 2 1 2
= 71.1 MHz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 563
Problem 5.509
Six versions of a source follower are shown below. Assume that K'
N
= 2K'
P
, λ
P
= 2λ
N
,
all W/L ratios of all devices are equal, and that all bias currents in each device are equal.
Neglect bulk effects in this problem and assume no external load resistor. Identify which
circuit or circuits have the following characteristics: (a.) highest smallsignal voltage
gain, (b.) lowest smallsignal voltage gain, (c.) the highest output resistance, (d.) the
lowest output resistance, (e.) the highest v
out
(max) and (f.) the lowest v
out
(max).
v
in
v
out
V
DD
V
SS
M1
M2
v
in
v
out
M2
M1
v
in
v
out
M1
M2
v
in
v
out
M1
M2
v
in
v
out
M1
M2
V
BN
v
in
v
out
M1
V
BP
M2
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5 Circuit 6
FS02E1P1
Solution
(a.) and (b.)  Voltage gain. Small signal model:
The voltage gain is found as:
v
out
v
in
=
g
m
g
m
+G
L
where G
L
is the load conductance. Therefore we get:
Circuit 1 2 3 4 5 6
v
out
v
in
g
mN
g
mN
+g
mN
g
mP
g
mP
+g
mP
g
mN
g
mN
+g
mP
g
mP
g
mP
+g
mN
g
mN
g
mN
+g
dsN
+g
dsP
g
mP
g
mP
+g
dsN
+g
dsP
But g
mN
= 2 g
mP
and g
dsN
= 0.5g
dsP
, therefore
Circuit 1 2 3 4 5 6
v
out
v
in
1
2
1
2
0.5858 0.4142
g
mP
g
mP
+(g
dsP
+g
dsN
)/ 2
g
mP
g
mP
+g
dsP
+g
dsN
Thus, circuit 5 has the highest gain and circuit 4 the lowest gain
(c.) and (d.)  Output resistance.
The denominators of the first table show the following:
Ckt.6 has the highest output resistance and Ckt. 1 the lowest output resistance.
(e.) Assuming no current has to be provided by the output, circuits 2, 4, and 6 can pull
the output to V
DD
. ∴ Circuits 2, 4 and 6 have the highest output swing.
(f.) Assuming no current has to be provided by the output, circuits 1, 3, and 5 can pull
the output to ground. ∴ Circuits 1, 3 and 5 have lowest output swing.
Summary
(a.) Ckt. 5 has the highest voltage gain (d.) Ckt. 1 has the lowest output resistance
(b.) Ckt. 4 has the lowest voltage gain (e.) Ckts. 2,4 and 6 have the highest output
(c.) Ckt. 6 has the highest output resistance (f.) Ckts. 1,3 and 5 have the lowest output
G
L
g
m
v
in g
m
v
out
+

v
out v
in
+

CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 564
Problem 5.510
Show that a class B, pushpull amplifier has a
maximum efficiency of 78.5% for a sinusoidal
signal.
Solution
Referring to the figure, assuming there is no
crossover distortion, the efficiency can be given
by
η
π
− ( )

.
`
}
V peak
R
V V
V peak
R
out
L
DD SS
out
L
( )
( )
2
2
For maximum efficiency, it can be assumed
that the output swing is symmetrical and the
peak output voltage can be given by
V peak V V
out DD SS
( ) −
Thus, η
π
− ( )

.
`
}
V
R
V V
V
R
DD
L
DD SS
DD
L
2
2
2
or, η
π
4
= 78.5%
V
DD
v
IN
v
OUT
i
OUT
M1
M2
V
DD
V
Bias
V
Bias
R
L
V
SS
V
SS Fig. S5.510A
t
v
in
t
v
out
v
out(peak)
t
i
d1
v
out(peak)
/R
L
t
i
d2
v
out(peak)
/R
L
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 565
Problem 5.511
Assume the parameters of Table 3.12 are valid
for the transistors of Fig. 5.55a. Design V
Bias
so
that M1 and M2 are working in classB
operation, i.e., M1 starts to turn on when M2
starts to turn off.
Solution
V V V V
GS in BIAS out 1
+ − ( )
V V V V
GS in BIAS out 2
− − ( )
In Class B operation, when M
1
starts to turn on
and M
2
starts to turn off, the drain currents can be written as
I I I
D D out 1 2
+
or,
K W
L
V V
K W
L
V V
V
R
N
GS T
P
SG T
out
L
' '
2 2
1
1 1
2
2
2 2
2

.
`
}
− ( )

.
`
}
− ( ) +
Assuming, when V
in
0, V
out
0, we get
K W
L
V V
K W
L
V V
N
BIAS T
P
BIAS T
' '
2 2
1
1
2
2
2
2

.
`
}
− ( )

.
`
}
− ( )
or,
V V
V V
K
K
W
L
L
W
BIAS T
BIAS T
P
N
−
−

.
`
}

.
`
}

.
`
}
1
2 2 1
'
'
or, V
V
K
K
W
L
L
W
V
K
K
W
L
L
W
BIAS
T
P
N
T
P
N
−

.
`
}

.
`
}
]
]
]
−

.
`
}

.
`
}
]
]
]
1
2 1
2
2 1
1
'
'
'
'
V
DD
v
IN
v
OUT
i
OUT
M1
M2
V
DD
V
Bias
V
Bias
R
L
V
SS
V
SS Fig. S5.510A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 566
Problem 5.512
Find an expression for the maximum and minimum output voltage swing for Fig. 5.55a.
Solution
To calculate the maximum output voltage swing, it can be assumed that the input is taken
to V
DD
. Thus,
V V V V V V
GS T DD BIAS out T 1 1 1
− + − − ( ) (max)
and, V V V
DS DD out 1
− ( ) (max)
So, V V V V V
DS GS T BIAS T 1 1 1 1
− − ( ) − ( )
Thus, if V V
BIAS T
≥
1
, V V V
DS GS T 1 1 1
≥ − ( ) and M
1
will be in saturation.
Now, I I
D L 1
or,
K W
L
V V V V
V
R
N
DD BIAS out T
out
L
'
(max)
(max)
2
1
1
2 
.
`
}
+ − − ( )
or, V V V V Y
out DD BIAS T
(max) + − ( ) +
1
where, Y
R K W L
R K W L
V V V
R K W L
L N
L N
DD BIAS T
L N
( )
−
( ) ( )
+
+ − ( )
( ) ( )
1 1 2
1
1
2
1
1
'
'
'
To calculate the minimum output voltage swing
I I
D L 2
−
or,
K W
L
V V V V
V
R
P
SS BIAS out T
out
L
'
(min)
(min)
2
2
2
2

.
`
}
− − + ( ) −
or, V V V V Z
out SS BIAS T
(min) − + ( ) −
2
where, Z
R K W L
R K W L
V V V
R K W L
L P
L P
SS BIAS T
L P
( )
−
( ) ( )
−
− + ( )
( ) ( )
1 1
2
2
2
2
2
2
'
'
'
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 567
Problem 5.513
Repeat the previous problem for Fig.
5.58.
Solution
Assuming M
2
operate in triode region
when V V
in SS
, the maximum output
voltage swing can be calculated as
follows:
I I
D out 2
or,
K
W
L
V V V V V V
V
R
P SS DD TR T out DD
out
L
'
(max)
(max) 
.
`
}
− + + ( ) − ( )
2
2 2
or, V
V
K
W
L
R V V V V
out
DD
P L SS DD TR T
(max)
'
+

.
`
}
− + + ( )

.
`
}
]
]
]
]
]
1
1
2
2 2
Assuming M
1
operate in triode region when V V
in DD
, the minimum output voltage
swing can be calculated as follows:
I I
D out 1
−
or, K
W
L
V V V V V V
V
R
N SS DD TR T out SS
out
L
'
(min)
(min) 
.
`
}
− + − − ( ) − ( )
−
1
1 1
or, V
V
K
W
L
R V V V V
out
SS
N L SS DD TR T
(min)
'
+

.
`
}
− + − − ( )

.
`
}
]
]
]
]
]
1
1
1
1 1
C
L
R
L
v
IN
v
OUT
i
OUT
V
DD
V
TR2
V
TR1
M2
M1
Figure 5.58 Pushpull inverting CMOS amplifier.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 568
Problem 5.514
Given the pushpull inverting CMOS amplifier shown in Fig. 5.514, show how short
circuit protection can be added to this amplifier. Note that R
1
could be replaced with an
active load if desired.
Solution
V
SS
I
SC
V
SS
V
DD
V
DD
I
SC
V
out
V
SS
V
DD
V
BIAS
V
in
M
1
M
3
M
2
M
4
M
5
M
6
M
7
M
8
M
9
V
SS
The current source
SC
I in the figure represents the short circuit current whose value can
be set as desired. The current through the transistors M2 and M3 need to be regulated for
short circuit protection. The currents carried by M2 and M3 are mirrored into M4 and M9
respectively. When the current tends to increase in M2, the current in M4 would also
increase. This would tend to increase the voltage at the drain of M5, but it will decrease
the current in M5. Since the current carried by M4 and M5 are same, the gate bias of M4
as well as M2 cannot increase beyond a point where they both carry the maximum limit
of the current as set by the short circuit current source. Similarly, the diodeconnected
transistor M9 would limit the gate bias of M3, thus limiting the output sinking current.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 569
Problem 5.515
If R
1
R
2
of Fig. 5.512, find an expression for the smallsignal output resistance R
out
.
Repeat including the influence of R
L
on the output resistance.
Solution
v v
R
R R
v
g g x 1 2
1
1 2
+ ( )
or, v v v
g g x 1 2
0 5 .
i g v
d m x 1 1
0 5 .
and, i g v
d m x 2 2
0 5 .
Now, i i i
x d d
+
1 2
or, i g g v
x m m x
+ ( ) 0 5
1 2
.
So, the output resistance becomes
R
v
i g g
out
x
x m m
+ ( )
2
1 2
In presence of load R
L
( ), the output resistance will become
R
g g
R
out
m m
L
+ ( )
]
]
]
[ ]
2
1 2

The presence of the load resistance R
L
( ) will tend to decrease the output resistance.
V
DD
V
SS
V
x
i
x
i
d1
i
d2
R
1
R
2
V
x
R
1
(R
1
+R
2
)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 570
Problem 5.516
Develop a table that expresses the dependence of the smallsignal voltage gain, output
resistance, and the dominant pole as a function of dc drain current for the differential
amplifier of Fig. 5.21, the cascode amplifier of Fig. 5.31, the highoutputresistance
cascode of Fig. 5.36, the inverter of Fig. 5.51, and the source follower of Fig. 5.53b.
Solution
Differential
Amplifier
Cascode
Amplifier
HighGain
Cascode
Amp.
Inverting
Amplifer
Source
Follower
Circuit
V
Bias
M1 M2
M3 M4
V
DD
M5
+
v
out
v
i

FigS5.205
+
v
in

+
v
out

M2
M1
M3
V
DD
V
GG3
V
GG2
Figure 5.31
V
DD
V
GG4
V
GG3
V
GG2
v
in
v
o
R
out
M3
M4
M2
M1
Fig. 5.36(a)
V
DD
M2
M1
v
IN
v
OUT
I
D
V
GG2
Figure 5.11
VDD
vIN
vOUT
iOUT
M1
M2
VGG2
Fig. 5.53(b)
VSS
VSS
A
v
2
λ
Ν
+λ
P
K
N
'W
2I
D
L
1

2K
N
'W
1
L
1
I
D
λ
P
2
See Eq. (5.3
37)
Gain ∝ I
D
1
2
λ
Ν
+λ
P
K
N
'W
2I
D
L
1
Error!
R
out
∝
1
I
D
∝
1
I
D
∝
1
I
D
1.5
∝
1
I
D
∝
1
I
D
p
1

∝ I
D
∝ I
D
∝ I
D
1.5
∝ I
D
∝ I
D
0.5
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 571
Problem 5.601
Propose an implementation of the VCCS of Fig. 5.62(b).
Solution
V
Bias
M1 M2
M3 M4
V
DD
M5
+
i
o
v
i

FigS5.601
Problem 5.602
Propose an implementation of the VCVS of Fig. 5.63(b).
Solution
V
Bias
M1 M2
M3 M4
V
DD
M5
+
v
o
v
i

FigS5.602
M6
M7
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 572
Problem 5.603
Propose an implementation of the CCCS of Fig. 5.64(b).
Solution
I
I
2I
V
DD
V
DD
V
DD
i
1
i
2
i
2
i
o
i
1
i
2
M1 M2 M3 M4
Fig. S5.603
Problem 5.604
Propose an implementation of the CCVS of Fig. 5.65(b).
Solution
I
I
2I
V
DD
V
DD
V
DD
i
1
i
2
i
2
i
1
i
2
M1 M2 M3 M4
Fig. S5.604
v
o
M6
M7
V
DD
V
Bias
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 61
CHAPTER 6 – HOMEWORK SOLUTIONS
Problem 6.101
Use the null port concept to find the voltage transfer
function of the noninverting voltage amplifier shown in
Fig. P6.11.
Solution
Let,
1
v
and
2
v
be the voltages at the noninverting and
inverting terminals respectively. Using the Nullport
concept and assuming that the lower negative rail is at
ground
in
v v v
2 1
Applying KCL
( ) ( )
1
2
2
2
R
v
R
v v
out
−
→
( ) ( )
1 2
R
v
R
v v
in in out
−
or,
}
`
.

+
}
`
.

1
2
1
R
R
v
v
in
out
Problem 6.102
Show that if the voltage gain of an op amp approaches infinity that the differential input
becomes a null port. Assume that the output is returned to the input by means of negative
feedback.
Solution
Referring to the figure, in
the presence of negative
series feedback, the
differential input can be
written as
out S in
fv v v −
and,
in v out
v A v
So,
in v S in
v fA v v −
or,
( )
v
S
in
fA
v
v
+
1
For a finite value of the negative feedback factor
( ) f
, if the value of openloop differential
gain
( )
v
A
tends to become infinite, then the value of the differential input voltage
( )
in
v
would tend to become zero and become a null port.
+

+

+

v
in
v
out
R
2
R
1
Figure P6.11
V
in
R
s
R
in
V
i
fV
out
A
v
V
i
R
o
V
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 62
Problem 6.103
Show that the controlled source of Fig. 6.15 designated as v
1
/CMRR is in fact a suitable
model for the commonmode behavior of the op amp.
+

v
2
v
1
v
1
CMRR
V
OS
R
icm
R
icm
i
n
2
v
n
2
I
B1
I
B2
C
id
R
id
R
out v
out
Ideal Op Amp
Figure 6.15 A model for a nonideal op amp showing some of the nonideal
linear characteristics.
*
Solution
Referring to the figure, considering only the source representing the commonmode
behavior,
CMRR v /
1 , the following analysis is carried out
The commonmode input, cm
v
, is given by
2 1
v v v
cm
Thus, the differential input is
CMRR
v
v v v
id
1
2 1
+ −
or,
CMRR
v
v
id
1
The output voltage is given by
id vd out
v A v
and, the commonmode rejection ratio is given by
cm
vd
A
A
CMRR
where,
vd
A
and
cm
A
are the differential and commonmode gains respectively.
Thus,
( )( )
}
`
.

CMRR
v
A CMRR v A v
cm id vd out
1
or,
( )
1
v A v
cm out
→
( )
cm cm out
v A v
This expression proves that the source
CMRR v /
1
represents the commonmode behavior
of the op amp.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 63
Problem 6.104
Show how to incorporate the PSRR effects of the op amp into the model of the nonideal
effects of the op amp given in Fig. 6.15.
Solution
Referring to the figure, the sources (
+
PSRR v
dd
/
) and (
−
PSRR v
ss
/
) would model the
positive PSRR and negative PSRR respectively.
+

v
2
v
1
v
1
CMRR
V
OS
R
icm
R
icm
i
n
2
v
n
2
I
B1
I
B2
C
id
R
id
R
out v
out
Ideal Op Amp
*
v
dd
PSRR
+
v
ss
PSRR

Problem 6.105
Replace the current mirror load of Fig. 6.18 with two separate current mirror and show
how to recombine these currents in an output stage to get a pushpull output. How can you
increase the gain of the configuration equivalent to a twostage op amp?
Solution
Referring to the figure, if the aspect ratios of M3 through M6 are same and that of M7 and
M8 are equal, then the smallsignal gain of this configuration becomes equivalent to a two
stage op amp. The smallsignal gain of this configuration is given by
( )
( )( )
}
`
.

+ +
+
8 6 4 2
5 6 2
ds ds ds ds
m m m
v
g g g g
g g g
A
V
SS
V
DD
V
out
M
1
M
2
M
3
M
4
M
5
M
7 M
8
M
6
M
5
V
BIAS
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 64
Problem 6.106
Replace the I→I stage of Fig. 6.19 with a current mirror load. How would you increase
the gain of this configuration to make it equivalent to a twostage op amp?
Solution
In the figure, the transistor M4 is a diodeconnected transistor.
V
SS
V
DD
M1 M2
M6
M4
M3
M5
M7
M10
M12
M11
M13
V
Bias
V
Bias
V
Bias
+

v
in
v
out
V→I I→I I→V
M8
M9
Fig. S6.16
The gain in the above circuit is already at the level of a twostage op amp. The gain could
easily be increased by making the W/L ratio of M7 to M4 and M6 to M5 greater than one.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 65
Problem 6.201
Develop the expression for the dominant pole in Eq. (6.210) and the output pole in Eq.
(6.211) from the transfer function of Eq. (6.29).
Solution
The transfer function is given by Equation (6.29). Assuming the dominant pole and the
output pole are wide apart, the dominant pole,
1
p
, can be calculated as the root of the
polynomial
( ) ( ) { ¦ [ ] 0 1 + + + + +
C II I mII C II II C I I
C R R g C C R C C R s
where, the effect due to the
2
s
term is neglected assuming the dominant pole is a low
frequency pole.
( ) ( ) { ¦
C II I mII C II II C I I
C R R g C C R C C R
p
+ + + +
−
1
1
Considering the most dominant term
{ ¦
C II I mII
C R R g
p
1
1
−
≅
To compute the output pole (which is assumed to be at high frequency), the polynomial
with the
s
and
2
s
terms are considered.
( ) ( ) { ¦ ( ) { ¦ [ ] 0
2
+ + + + + + +
II C C I II I II I C II I mII C II II C I I
C C C C C C R R s C R R g C C R C C R s
or,
( ) ( ) { ¦
( ) { ¦
II C C I II I II I
C II I mII C II II C I I
C C C C C C R R
C R R g C C R C C R
p
+ +
+ + + + −
2
or,
{ ¦
( ) { ¦
II C II I
C II I mII
C C R R
C R R g
p
−
≅
2
or,
{ ¦
{ ¦
II
mII
C
g
p
−
≅
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 66
Problem 6.202
Fig. 6.27 uses asymptotic plots to illustrate the difference between an uncompensated and
compensated op amp. What is the approximate value of the real phase margin using the
actual curves and not the asymptotic approximations?
Solution
Assume that the openloop gain can be expressed as
L(jω) =
A
v0
.

}
`
s
p
1
+1
.

}
`
s
GB
+1
where p
1
is the dominant pole
The magnitude and phase shift of the openloop gain can be expressed as,
 L(jω) =
A
v0
.

}
` ω
p
1
2
+1
.

}
` ω
GB
2
+1
Arg[L(jω)] = ±180°  tan
1
(ω/p
1
)  tan
1
(ω/GB)
At frequencies near GB, we can simplify these expression as,
 L(jω) ≈
GB
ω
.

}
` ω
GB
2
+1
Arg[L(jω)] = ±180°  90°  tan
1
(ω/GB) = 90°  tan
1
(ω/GB)
The unity gain frequency is found as,
GB
ω
ο
.

}
` ω
ο
GB
2
+1
=1 → (ω
ο
/GB)
4
+ (ω
ο
/GB)
2
1 = 0
(ω
ο
/GB)
2
= 0.5 ± 0.5 1+4 = 0.6180 → ω
ο
= 0.7862GB
The phase margin becomes,
Arg[L(jω
ο
)] = 90°  tan
1
(ω
ο
/GB) = 90°  tan
1
(0.7862)
= 90°  38.173° = 51.83°
∴ The actual phase margin is 51.83° compared to 45° estimated from the Bode plot.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 67
Problem 6.203
Derive the relationship for GB given in Eq. (6.217) of Sec. 6.2.
Solution
The small signal voltage gains of the two stages can be given by
I m v
R g A
1 1
II m v
R g A
2 2
And, the overall smallsignal voltage gain is given by
II m I m v
R g R g A
2 1
Assuming the dominant pole is much smaller than the output pole, and the Gainbandwidth
frequency is smaller than the output pole, the overall transfer function of the op amp can be
approximated by a single dominant pole, 1
p
.
}
`
.

+
1
1
) (
p
s
A
s A
v
v
where,
{ ¦
C II I mII
C R R g
p
1
1
−
≅
or,
}
`
.

+
1
1
) (
p
j
A
j A
v
v
ω
ω
It can be seen that at 1
p A
v
≅ ω
,
( ) 1 ω j A
v
So, the Gainbandwidth frequency, GB
ω
, is given by
ω
GB v
mI
C
A p
g
C
≅
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 68
Problem 6.204
For an op amp model with two poles and one RHP zero, prove that if the zero is 10 times
larger than GB, then in order to achieve a 45° phase margin, the second pole must be
placed at least 1.22 times higher than GB.
Solution
Given,
) ( 10 GB z
The transfer function is given by
}
`
.

+
}
`
.

+
}
`
.

−
2 1
1 1
1
) (
p
s
p
s
z
s
A
s A
v
v
The phase margin, PM, can be written as
}
`
.

}
`
.

+
}
`
.

+
}
`
.

−
− − −
z
GB
p
GB
p
GB
PM
1
2
1
1
1
tan tan tan 180
o
or,
}
`
.

+
}
`
.

+ −
− o o o o
7 . 5 tan 90 180 45
2
1
p
GB
→
o
3 . 39 tan
2
1
}
`
.

−
p
GB
or,
) ( 22 . 1
2
GB p
Problem 6.205
For an op amp model with three poles and no zero, prove that if the highest pole is 10 times
GB, then in order to achieve 60° phase margin, the second pole must be placed at least 2.2
times GB.
Solution
The transfer function is given by
}
`
.

+
}
`
.

+
}
`
.

+
3 2 1
1 1 1
) (
p
s
p
s
p
s
A
s A
v
v
The phase margin, PM, can be written as
}
`
.

}
`
.

+
}
`
.

+
}
`
.

−
− − −
3
1
2
1
1
1
tan tan tan 180
p
GB
p
GB
p
GB
PM
o
or,
}
`
.

+
}
`
.

+ −
− o o o o
7 . 5 tan 90 180 60
2
1
p
GB
→
o
3 . 24 tan
2
1
}
`
.

−
p
GB
or,
) ( 2 . 2
2
GB p
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 69
Problem 6.206
Derive the relationships given in Eqs. (6.234) through (6.237) in Sec. 6.2.
Solution
The transfer function is given by Equations (6.232) through (6.236). Now, the
denominator of Equation (6.232) cannot be factorized readily. So, the roots of this
polynomial can be determined intuitively. The zero can be calculated as
0 1
¹
¹
¹
`
¹
¹
¹
¹
´
¹
}
`
.

− −
C z
mII
C
C R
g
C
s
or,
}
`
.

−
−
mII
Z C
g
R C
z
1
1
The dominant pole, 1
p
, is given by
( ) ( ) { ¦ [ ] 0 1 + + + + + +
C Z C II I mII C II II C I I
C R C R R g C C R C C R s
where, the effect due to the
2
s
and higher order terms are neglected assuming the dominant
pole is a low frequency pole.
( ) ( ) { ¦
C Z C II I mII C II II C I I
C R C R R g C C R C C R
p
+ + + + +
−
1
1
Considering the most dominant term
{ ¦
C II I mII
C R R g
p
1
1
−
≅
To compute the output pole (which is assumed to be at high frequency), the polynomial
with the
s
and
2
s
terms from Equations (6.234) and (6.235) are considered.
or,
( ) ( ) { ¦
( ) ( ) { ¦
II II I I C Z II C C I II I II I
C Z C II I mII C II II C I I
C R C R C R C C C C C C R R
C R C R R g C C R C C R
p
+ + + +
+ + + + + −
2
or,
{ ¦
( ) { ¦
II C II I
C II I mII
C C R R
C R R g
p
−
≅
2
or,
{ ¦
{ ¦
II
mII
C
g
p
−
≅
2
To compute the third pole,
4
p
, the polynomial with the
2
s
and
3
s
terms from Equations
(6.235) and (6.236) are considered.
or,
( ) ( ) { ¦
C II I Z II I
II II I I C Z II C C I II I II I
C C C R R R
C R C R C R C C C C C C R R
p
+ + + + −
4
or,
{ ¦
C II I Z II I
C II II I
C C C R R R
C C R R
p
−
≅
4
or,
I Z
C R
p
1
4
−
≅
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 610
Problem 6.207
Physically explain why the RHP zero occurs in the Miller compensation scheme illustrated
in the op amp of Fig. 6.28. Why does the RHP zero have a stronger influence on a CMOS
op amp than on a similar type BJT op amp?
Solution
Referring to the figure and considering the
transistor
6
M
, there are two paths from the
input (gate) to the output (drain): inverting
and noninverting.
The signal current in the inverting path is
given by
6 6 g m inv
v g i
The signal current in the noninverting path
is given by
( )
C out g inv non
sC v v i −
− 6
The zero is created when
inv non inv
i i
−
and
0
out
i
or,
( )
C out g g m
sC v v v g −
6 6 6
or,
( )
C
C m
g
out
sC
sC g
v
v + −
6
6
Thus, the RHP zero is given by the numerator
( )
C m
sC g + −
6 .
The RHP zero has a stronger (degrading) influence in MOS than in BJT as
BJT m MOS m
g g
, ,
<
and, the RHP zero is closer to the Gainbandwidth frequency thus decreasing the phase
margin.
M
6
C
c
V
1
V
out
i
noninv
i
inv
V
DD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 611
Problem 6.208
A twostage, Millercompensated CMOS op amp has a RHP zero at 20GB, a dominant
pole due to the Miller compensation, a second pole at p
2
and a mirror pole at 3GB. (a) If
GB is 1MHz, find the location of p
2
corresponding to a 45° phase margin. (b) Assume
that in part (a) that p
2
 = 2GB and a nulling resistor is used to cancel p
2
. What is the new
phase margin assuming that GB = 1MHz? (c) Using the conditions of (b), what is the
phase margin if C
L
is increased by a factor of 4?
Solution
a.) Since the magnitude of the op amp is unity at GB, then let ω = GB to evaluate the
phase.
Phase margin= PM = 180°  tan
1
.

}
`
GB
p
1

 tan
1
.

}
`
GB
p
2

 tan
1
.

}
`
GB
p
3

 tan
1
.

}
`
GB
z
1

But, p
1
= GB/A
o
, p
3
= 3GB and z
1
= 20GB which gives
PM = 45° = 180°  tan
1
(A
o
)  tan
1
.

}
`
GB
p
2

 tan
1
(0.33) tan
1
(0.05)
45° ≈ 90°  tan
1
.

}
`
GB
p
2

 tan
1
(0.33) tan
1
(0.05) = 90°  tan
1
.

}
`
GB
p
2

 18.26°  2.86°
∴ tan
1
.

}
`
GB
p
2

= 45°  18.26°  2.86° = 23.48° →
GB
p
2

= tan(23.84°) = 0.442
p
2
=  2.26·GB = 14.2x10
6
rads/sec
b.) The only roots now are p
1
and p
3
. Thus,
PM = 180°  90°  tan
1
(0.33) = 90°  18.3° = 71.7°
c.) In this case, z
1
is at 2GB and p
2
moves to 0.5GB. Thus the phase margin is now,
PM = 90°  tan
1
(2) + tan
1
(0.5)  tan
1
(0.33) = 90°63.43°+26.57°18.3° = 34.4°
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 612
Problem 6.209
Derive Eq. (6.253).
Solution
A
V
i
C
c
g
mII
v
i
V
out
C
II
R
II
Referring to the figure, applying KCL
− − ( ) + +

.
`
}
Av s v s sC g v s sC
R
v s
i out C mII i II
II
out
( ) ( ) ( ) ( )
1
or, sAC g v s sC
R
sC v s
C mII i II
II
C out
+ ( ) − + +

.
`
}
( ) ( )
1
or,
v s
v s
sAC g
sC
R
sC
out
i
C mII
II
II
C
( )
( )
−
+ ( )
+ +

.
`
}
1
or,
v s
v s
AC
C C
s
g
AC
s
R C C
out
i
C
C II
mII
C
II C II
( )
( )
−
+ ( )
+

.
`
}
+
+ ( )

.
`
}
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 613
Problem 6.210
For the twostage op amp of Fig. 6.28, find W
1
/L
1
, W
6
/L
6
, and C
c
if GB 1 MHz, p
2

5 GB, z 3 GB and C
L
C
2
20 pF. Use the parameter values of Table 3.12 and
consider only the twopole model of the op amp. The bias current in M5 is 40 µA and in
M7 is 320 µA.
Solution
Given
GB 1 MHz.
p GB
2
5
z GB 3
C C
L
2
20 pF
Now, p
g
C
m
2
6
2
or,
g
m6
628 3 . µS
or,
W
L
g
K I
m
P D

.
`
}
≅
6
6
2
6
2
12 33
'
.
RHP zero is given by
z
g
C
m
C
6
or, C
g
z
C
m
6
33 3 . pF
Finally, Gainbandwidth is given by
GB
g
C
m
C
1
or, g
m1
209 4 . µS
or,
W
L
g
K I
m
N D

.
`
}
≅
1
1
2
1
2
10
'

+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+

C
c
C
1
C
2
C
3
Figure 6.28 A twostage op amp with various parasitic and
circuit capacitances shown.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 614
Problem 6.211
In Fig. 6.213, assume that R
I
150 kΩ, R
II
100 kΩ, g
mII
500 µS, C
I
1 pF, C
II
5
pF, and C
c
30 pF. Find the value of R
z
and the locations of all roots for (a) the case
where the zero is moved to infinity and (b) the case where the zero cancels the next highest
pole.
Solution
(a.) Zero at infinity.
R
z
=
1
g
mII
=
1
500µS
R
z
2kΩ
Check pole due to R
z
.
p
4
−1
R
z
C
I
=
1
2kΩ·1pF
= 500x10
6
rps or 79.58 MHz
The pole at p
2
is
p
2
≅
−g
mII
C
c
C
I
C
II
+ C
c
C
I
+ C
c
C
II
≅
−g
mII
C
II
=
500µS
5pF
= 100x10
6
rps or 15.9 MHz
Therefore, p
2
is the next highest pole.
(b.) Zero at p
2
.
R
z
.

}
` C
c
+ C
II
C
c
(1/g
mII
) =
.

}
`
30+5
30
1
500µS
= 2.33kΩ
R
z
2. 33kΩ
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 615
Problem 6.301
Express all of the relationships given in Eqs. (6.31) through (6.39) of Sec. 6.3 in terms
of the largesignal model parameters and the dc values of drain current.
Solution
C
C
I
SR
5
(6.31)
( )
( )
2
1
1
’
1
2
N P
N
v
I
L W K
A
λ λ +
−
(6.32)
( )
( )
2
6
6
’
2
2
N P
P
v
I
L W K
A
λ λ +
−
(6.33)
( )
C
N
C
I L W K
GB
1
1
’
2
(6.34)
( )
L
p
C
I L W K
p
6
6
’
2
2
−
(6.35)
( )
C
p
C
I L W K
z
6
6
’
1
2
(6.36)
Positive CMR
( )
(min) (max) (max)
1 03
3
’
5
T T
P
DD in
V V
L W K
I
V V + − −
(6.37)
Negative CMR
( ) ( )
(max)
2
(min)
1
5
’
5
1
’
5
T
N N
SS in
V
L W K
I
L W K
I
V V + + +
(6.38)
V
DS
(sat) =
2I
DS
β
(6.39)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 616
Problem 6.302
Develop the relationship given in step 5 of Table 6.32.
Solution
Referring to the figure,
3
p
is generated at the drain of
3
M
.
Resistance looking into the drain of
3
M
is given by
( )
3 1 3 3
1 1
m ds ds m
III
g g g g
R ≅
+ +
The total capacitance at the drain of 3
M
is given by
( )
3 1 1 3 4 3
2
gs gd bd bd gs gs III
C C C C C C C ≅ + + + +
Thus, the pole at the drain of 3
M
is given by
III III
C R
p
1
3
−
or,
3
3
3
2
gs
m
C
g
p
−
Now, if
GB
C
g
gs
m
10
2
3
3
>
, then the contribution due to this pole on the phase margin is less
than
o
7 . 5
, i.e., this pole can be neglected.
Problem 6.303
Show that the relationship between the W/L ratios of Fig. 6.31 which guarantees that
V
SG4
V
SG6
is given by S
6
/S
4
= 2(S
7
/S
5
) where S
i
W
i
/L
i
.
Solution
Let us assume that
6 4 SG SG
V V
(1)
or,
6 6 4 4 dsat T dsat T
V V V V + +
→
6 4 T T
V V
So,
6 4 dsat dsat
V V
→
( ) ( )
6
’
6
4
’
4
2 2
L W K
I
L W K
I
P P
or,
( )
( )
4
7
4
6
4
6
I
I
I
I
L W
L W
→
( )
( )
5
7
4
6
2
I
I
L W
L W
Since,
7 5 GS GS
V V
, we have
( )
( )
( )
( )
5
7
4
6
2
L W
L W
L W
L W
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 617
Problem 6.304
Draw a schematic of the op amp similar to Fig. 6.31 but using pchannel input devices.
Assuming that same bias currents flow in each circuit, list all characteristics of these two
circuits that might be different and tell which is better or worse than the other and by what
amount (if possible).
Solution
In working this problem we shall assume that K
N
’>K
P
’.
M5
M7
M1 M2
M3 M4
+5V
5V
M6
+

V
Bias
v
out
C
c
v
in
M5
M7
M1 M2
M3 M4
+5V
5V
M6
V
Bias
v
out
+

C
c
v
in
Circuit 1 Circuit 2 Fig. S6.304
Characteristic Circuit 1 Circuit 2
Noise Worse but not by much because
the first stage gain is higher.
Better but degraded by the lower
first stage gain
Phase margin Poorer (g
mI
larger but g
mII
is
smaller)
Better
Gainbandwidth Larger (GB = g
mI
/C
c
) Smaller
V
icm
(max.) Larger Smaller
V
icm
(min.) Smaller Larger
Sourcing output
current
Large Constrained
Sinking output
current
Constrained Large
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 618
Problem 6.305
Use the op amp designed in Ex. 6.31 and assume that the input transistors, M1 and M2
have their bulks connected to 2.5V. How will this influence the performance of the op
amp designed in Ex. 6.31? Use the W/L values of Ex. 6.31 for this problem. Wherever
the performance is changed, calculate the new value of performance and compare with the
old.
Solution
Referring to the design in Example. 6.31, it can be shown that the threshold voltages of
the input transistors
1
M
and
2
M
are increased due to body effect
( ) 0 ≠
BS
V
5 2 1 DS BS BS
V V V −
Let us assume that
1
5
DS
V
V. Then,
( ) φ φ γ 2 2
1 0 2 1
− + +
SB N T T T
V V V V
or,
89 . 0
2 1
T T
V V
V
Assuming that the bias currents in the various branches remain the same, the smallsignal
m
g
and ds
g
values will remain the same. Considering all the performance specifications
of the op amp, only the ICMR will be effected.
The maximum input commonmode voltage can be given by
( )
3
’
3
3 1
2
(max) (min) (max)
L W K
I
V V V V
P
T T DD in
− − +
or,
81 . 1 2 . 0 ) 15 . 0 89 . 0 ( 55 . 0 5 . 2 (max) − + − +
in
V
V
The original value of
(max)
in
V
was 2 V.
The minimum input commonmode voltage can be given by
( ) ( )
5
’
5
1
’
1
1
2 2
(max) (min)
L W K
I
L W K
I
V V V
N N
T SS in
+ + +
or,
81 . 0 35 . 0 3 . 0 15 . 0 89 . 0 5 . 2 (min) − + + + + −
in
V
V
The original value of
(min)
in
V
was 1 V.
The new value of ICMR is 2.62 V as compared to 3 V.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 619
Problem 6.306
Repeat Ex. 6.31 for a p
channel input, twostage
op amp. Choose the same
currents for the firststage
and secondstage as in Ex.
6.31.
Solution
Following the steps
of Ex. 6.31 we have the
following:
C
c
= 3pF, I
5
= 30µA,
(W/L)
3
30 x 10
 6
(110x10
6
)[2.5 − 2 − .85 + 0.55]
2
= 6.82 → W
3
= W
4
= 7µm
Next, we find that g
m1
= (5x10
6
)(2π)(3x10
12
) = 94.25µS which gives
(W/L)
1
= (W/L)
2
g
m1
2
2K’
N
I
1
=
(94.25)
2
2·50·15
= 5.92 → W
1
= W
2
= 6µm
Calculating V
SD5
(sat) we get
V
DS5
(−1) − (−2.5) −
30x10
6
50x10
6
·3
 .85 = 0.203V
∴ (W/L)
5
2(30 x 10
6
)
(50 x 10
6
)(0.203)
2
= 29.1 → W
5
= 29µm
Next, we find g
m4
≈ 150µS which gives
S
6
= S
4
g
m6
g
m4
= 7·
942.5
150
= 43.4 ≈ 43 → W
6
= 43µm
The output stage current is,
I
6
(942.5 x 10
6
)
2
(2)(110 x 10
6
)(43)
= 93µA
∴ (W/L)
7
= (W/L)
5
.

}
`
93µA
20µA
= 29(93/30) = 89.9 → W
7
= 90µm
The gain and power dissipation are identical with that in Ex. 6.31.

+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+

C
c
C
L
FigS6.306
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 620
Problem 6.307
For the pchannel input, CMOS op amp of Fig. P6.37, calculate the openloop, low
frequency differential gain, the output resistance, the power consumption, the power
supply rejection ratio at DC, the input commonmode range, the outputvoltage swing, the
slew rate, the commonmode rejection ratio, and the unitygain bandwidth for a load
capacitance of 20 pF. Assume the model parameters of Table 3.12. Design the W/L ratios
of M9 and M10 to give a resistance of 1/g
m6
and use the simulation program SPICE to find
the phase margin and the 1% settling time for no load and for a 20 pF load.
Solution
Bias current calculation:
ss dd S ON T
V V R I V V − + + .
8 8 8 or, V
I
K
I R
T
p
s 8
8
8
2
3
5 + −
.
.
.
/
. (1)
Solving for 8
I
quadratically gives, I
8
=_ 36µA , I
5
=_ 36µA , and I
7
=_ 60µA
Using the formula,
I
L
W
K g
m
. . 2
/
and
I g
ds
λ
we get,
S g
m
µ 60
2
,
S g
ds
µ 9 . 0
2
,
S g
ds
µ 72 . 0
4
(2)
S g
m
µ 363
6
,
S g
ds
µ 3
6
,
S g
ds
µ 4 . 2
7
(3)
Smallsignal openloop gain:
The smallsignal voltage gain can be expressed as,
37
) (
4 2
2
1
−
+
−
ds ds
m
V
g g
g
A
and
67
) (
7 6
6
2
−
+
−
ds ds
m
V
g g
g
A
Thus, total openloop gain is, A
v
= A
v1
·A
v2
= 2489V/V (3)
Output resistance:
Ω
+
K
g g
R
ds ds
out
185
) (
1
7 6
(5)
Power dissipation:
W W P
diss
µ µ 660 ) 60 36 36 ( 5 + +
(6)
ICMR:
V V V V V
ON ON T in
51 . 0 5 . 2
5 1 1 max ,
− − −
(7)
V V V V V
ON T T in
21 . 2 5 . 2
3 3 1 min ,
− + + − −
(8)
Output voltage swing:
V V V
ON
81 . 1 5 . 2
7 max , 0
−
(9)
Slew Rate:
Slew rate under no load condition can be given as
s V
C
I
SR
C
µ / 6
5
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 621
Problem 6.37  Continued
In presence of a load capacitor of 20 pF, slew rate would be,
SR = min
]
]
I
5
C
c
,
I
7
C
L
CMRR:
Under perfectly balanced condition where
2 1
I I
, if a small signal commonmode
variation occurs at the two input terminals, the small signal currents
4 3 2 1
i i i i
and the
differential output current at node (7) is zero. So, ideally, commonmode gain would be
zero and the value for CMRR would be infinity.
GBW:
Let us design M9 and M10 first. Both these transistors would operate in triode region and
will carry zero dc current. Thus,
0
10 9
≅
ds ds
V V
. The equation of drain current in triode
region is given as,
( )
DS T GS D
V V V
L
W
K I .
/
− ≅
.
The on resistance of the MOS transistor in triode region of operation would be,
( )
T GS ON
V V
L
W
K R −
/
.
It is intended to make the effective resistance of M9 and M10 equal to
6
1
m
g
.
So, K’
9
.

}
`
W
9
L
9
(V
GS9
V
T9
) + K’
10
.

}
`
W
10
L
10
(V
GS10
V
T10
) = g
m6
(11)
V V V V V
ON T D D
51 . 1 5 . 2
3 3 3 4
− + + −
Thus,
V V
GS
4
9
≅
and
V V
GS
1
10
− ≅
.
Putting the appropriate values in (11), we can solve for the aspect ratios of M9 and M10.
One of the solutions could be,
K’
9
.

}
`
W
9
L
9
=
1
1
and K’
10
.

}
`
W
10
L
10
= very small (12)
The dominant pole could be calculated as,
( )
. 16 . 1
. . . 2
1
2 4
1
KHz
C A
g g
p
C V
ds ds
−
+ −
π
And the load pole would be,
. 8 . 2
. . 2
6
2
MHz
C
g
p
L
m
−
−
π
for a 20 pF load.
It can be noted that in this problem, the product of the openloop gain and the
dominant pole is approximately equal to the load pole. Thus, the gain bandwidth is
approximately equal to 2.8 MHz and the phase margin would be close to 45 degrees.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 622
Problem 6.308
Design the values of W and L for each transistor of the CMOS op amp in Fig. P6.38 to
achieve a differential voltage gain of 4000. Assume that K'
N
110 µA/V
2
, K'
P
50
µA/V
2
, V
TN
−V
TP
0.7 V, and λ
N
λ
P
0.01 V
1
. Also, assume that the minimum
device dimension is 2 µm and choose the smallest devices possible. Design C
c
and R
z
to
give GB 1 MHz and to eliminate the influence of the RHP zero. How much load
capacitance should this op amp be capable of driving without suffering a degradation in the
phase margin? What is the slew rate of this op amp? Assume V
DD
−V
SS
2.5V and R
B
100 kΩ.
Solution
Given
4000
v
A
V/V
1 GB
MHz and
∞
1
z
For
50
5
I
A µ
, let us assume
40
8
I
A µ
Thus,
1
8
GS
V
V
or,
( )
2
16 2
2
8 8
’
8
8
≅
−
}
`
.

T GS N
V V K
I
L
W
m
m
µ
µ
or,
2
20
4
5
8 5
}
`
.

}
`
.

L
W
L
W
m
m
µ
µ
and,
2
40
7
}
`
.

L
W
m
m
µ
µ
Also, let us assume that
5 . 1
4 3
SG SG
V V
V
or,
( )
2
3 2
2
3 3
’
3
4 3
−
}
`
.

}
`
.

T SG P
V V K
I
L
W
L
W
m
m
µ
µ
The aspect ratio of
6
M
can be calculated as
4 5 7 6
2
}
`
.

}
`
.

}
`
.

}
`
.

L
W
W
L
L
W
L
W
→
2
12
6
}
`
.

L
W
m
m
µ
µ
or,
245
6
m
g
S µ
In order to eliminate the RHP zero
4
1
6
≅
m
Z
g
R
Ω K
Now,
( )
2
7 5
6 1
2
N P
m m
v
I I
g g
A
λ λ +
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 623
Problem 6.308  Continued
or,
( )
6
2
7 5
1
2
m
N P v
m
g
I I A
g
λ λ +
or,
16
1
m
g
S µ
or,
5
’
2
1
1
I K
g
L
W
N
m
}
`
.

→
00145 . 0
1
}
`
.

L
W
Let us assume a more realistic value as
2
2
2 1
}
`
.

}
`
.

L
W
L
W
m
m
µ
µ
This will give
2 . 74
1
m
g
S µ
and
9090
v
A
V/V
Now,
2 . 74
1
GB
g
C
m
C pF
The phase margin can be approximated as
]
]
]
}
`
.

+
}
`
.

−
− −
2
1
1
1
tan tan 180
p
GB
p
GB
PM
o
Considering the worstcase phase margin to be 60 degrees
]
]
]
}
`
.

+ −
−
(min)
tan 90 180 60
2
1
p
GB
o o o
or,
732 . 1 732 . 1 (min)
2
GB p
MHz.
or,
5 . 141
(min)
(max)
2
6
p
g
C
m
L
pF
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 624
Problem 6.309
Use the electrical model parameters of the previous problem to design W
3
, L
3
, W
4
, L
4
,
W
5
, L
5
, C
c
, and R
z
of Fig. P6.38 if the dc currents are increased by a factor of two and if
W
1
L
1
W
2
L
2
2 µm to obtain a lowfrequency, differentialvoltage gain of 5000
and a GB of 1 MHz. All devices should be in saturation under normal operating conditions
and the effect of the RHP should be canceled. How much load capacitance should this op
amp be able to drive before suffering a degradation in the phase margin? What is the slew
rate of this op amp?
Solution
Given
W L W L
1 1 2 2
2 µm
Referring to the solution of P6.38
g
m1
104 8 . µS
or, C
g
GB
C
m
1
105 pF
Also,
g
A I I
g
m
v P N
m
6
5 7
2
1
2
190 8
+ ( )
λ λ
. µS
or,
W
L
g
K I
m
P

.
`
}
6
6
2
7
7 2
2
'
.
m
m
µ
µ
and, R
g
Z
m
≅
1
5 24
6
.
Ω K
Now,
W
L
W
L
W
L
L
W
W
L

.
`
}

.
`
}

.
`
}

.
`
}

.
`
}
≅
3 4 6 7 5
0 5
2
2
.
m
m
µ
µ
Assuming V
GS5
1 V
W
L
I
K V V
N GS T

.
`
}
− ( )
≅
5
5
5 5
2
2 40
2
'
m
m
µ
µ
Slew rate can be expressed as
SR
I
C
C
≅
5
1 V s / µ
Considering the worstcase phase margin to be 60 degrees
]
]
]
}
`
.

+ −
−
(min)
tan 90 180 60
2
1
p
GB
o o o
or,
732 . 1 732 . 1 (min)
2
GB p
MHz.
or, C
g
p
L
m
(max)
(min)
6
2
110 pF
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 625
Problem 6.310
For the op amp shown in Fig.
P6.310, assume all transistors are
operating in the saturation region
and find (a.) the dc value of I
5
, I
7
and I
8
, (b.) the low frequency
differential voltage gain, A
vd
(0),
(c.) the GB in Hz, (d.) the
positive and negative slew rates,
(e.) the power dissipation, and (f.)
the phase margin assuming that the
openloop unity gain is 1MHz.
Solution
(a.)
5V =
2·I
8
K
P
· 1
+ 0.7 +
2·I
8
K
N
·1
+ 0.7 ⇒ 3.6 = I
8
.

}
`
1
25
+
1
55
⇒ I
8
= 10.75µA
∴ I
8
= 10. 75µA, I
5
= 2I
8
= 21. 5µA, and I
7
= 10I
8
= 107. 5µA
(b.) A
v
(0) = g
m1
(r
ds2
r
ds4
)g
m6
(r
ds6
r
ds7
)
g
m1
= 2·K
N
·10·I
8
= 153.8µS , g
m6
= 2·K
P
·10·I
7
= 327.9µS ,
r
ds2
=
25
10.75
= 2.33MΩ,
r
ds4
=
20
10.75
= 1.86MΩ, r
ds6
=
20
107.5
= 0.186MΩ , and r
ds7
=
25
107.5
= 0.233MΩ .
∴ A
v
(0) = (153.8µS)(1.034MΩ)(327.9µS)(0.1034MΩ) = 5395 V/V
(c.) GB =
g
m1
C
c
=
153. 8µS
5pF
= 30.76Mradians/sec = 4.90MHz
(d.) Due to C
c
: SR =
I
5
C
c
=
21.5µA
5pF
= 4.3 V/µs
Due to C
L
: SR =
I
7
I
5
C
L
=
86µA
20pF
= 4.3V/µs ∴  SR = 4. 3V/µs
(e.) Power Dissipation = 5(I
8
+I
5
+I
7
) = 5(139.75µA) = 0.699mW
(f.) Phase margin = 180°  tan
1
.

}
`
GB
GB/A
v
(0)
 tan
1
.

}
`
GB
p
2
 tan
1
.

}
`
GB
z
p
2
=
g
m6
C
L
= 16.395x10
6
rads/sec and z =
g
m6
C
c
= 65.6x10
6
rads/sec
∴ Phase margin = 90°  tan
1
.

}
`
6.28
16.395
 tan
1
.

}
`
6.28
65.6
= 63. 6°
M1 M2
M3 M4
M5
M6
M7 M8
+2.5V
2.5V
v
in
C
c
=5pF
20pF
1/1 2/1 10/1
10/1
10/1
10/1
10/1 10/1
v
o
1/1
I
8
I
5
I
7
+

Figure P6.310
M9
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 626
Problem 6.311
A simple CMOS op amp is shown. Use
the following model parameters and find
the numerical value of the small signal
differential voltage gain, v
out
/v
in
, output
resistance, R
out
, the dominant pole, p
1
,
the unitygainbandwidth, GB, the slew
rate, SR, and the dc power dissipation.
K
N
’=24µA/V
2
, K
P
’ = 8µA/V
2
, V
TN
= 
V
TP
= 0.75V, λ
N
= 0.01V
1
and λ
P
=
0.02V
1
.
Solution
Small signal differential voltage gain: By intuitive analysis methods,
v
o1
v
in
=
0.5g
m1
g
ds1
+ g
ds3
and
v
out
v
o1
=
g
m4
g
ds4
+ g
ds5
→
v
out
v
in
=
0.5g
m1
g
m4
(g
ds1
+g
ds3
)(g
ds4
+g
ds5
)
g
m1
=
2K
N
W
1
I
D1
L
1
= 24·2·4·10 x10
6
= 43.82µS
g
ds1
= λ
N
I
D1
= 0.01·10µA = 0.1µS, g
ds3
= λ
P
I
D3
= 0.02·10µA = 0.2µS
g
m4
=
2K
P
W
4
I
D4
L
4
= 2·8·10·100 x10
6
= 126.5µS
g
ds4
= λ
P
I
D4
= 0.02·100µA = 2µS, g
ds5
= λ
N
I
D5
= 0.01·100µA = 1µS
∴
v
out
v
in
=
0.5·43.82·126.5
(0.1+0.2)(1+2)
= 3,079V/V
Output resistance:
R
out
=
1
g
ds4
+g
ds5
=
10
6
1+2
= 333kΩ
Dominant pole, p
1
:
p
1
 =
1
R
1
C
1
where R
1
=
1
g
ds1
+g
ds3
=
10
6
0.1+0.2
= 3.33MΩ
and C
1
= C
c
(1+A
v2
) = 5pF
.

}
`
1 +
g
m4
g
ds4
+g
ds5
= 5
.

}
`
1+
126.5
3
= 215.8pF
∴ p
1
 =
10
6
3.33·2.15.8
= 1,391 rads/sec → p
1
 = 1,391 rads/sec = 221Hz
GB =
0.5·g
m1
C
c
=
0.5·43.82x10
6
5x10
12
= 4.382Mrads/s GB=4.382 Mrads/sec=0.697MHz
SR =
I
D 6
C
c
=
10µA
5pF
= 2V/ µs P
diss
= 10V(140µA) = 1.4mW
+

vin
M1
M2
M5
M3
vout
M4
M6
M7
M8
10/1
5/1 1/1 1/1
2/1
20µA
4/1
4/1
1/1
+5V
5V
5pF
10µA
v
o1
10µA
100µA
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 627
Problem 6.312
On a loglog plot with the vertical axis having a range of 10
3
to 10
+3
and the horizontal
axis having a range of 1 µA to 100 µA, plot the lowfrequency gain A
v
(0), the unitygain
bandwidth GB, the power dissipation P
diss
, the slew rate SR, the output resistance R
out
,
the magnitude of the dominant pole p
1
, and the magnitude of the RHP zero z, all
normalized to their respective values at I
B
1 µA as a function of I
B
from 1 µA to 100 µA
for the standard twostage CMOS op amp. Assume the current in M5 is k
1
I
B
and the
output current (M6) is k
2
I
B
.
Solution
GB =
g
mI
C
c
∝ I
Bias
P
diss
= (V
DD
+V
SS
)(1+K
1
+K
2
)I
Bias
∝ I
bias
SR =
K
1
I
Bias
C
c
∝ I
Bias
R
out
=
1
2λK
2
I
Bias
∝
1
I
Bias
p
1
 =
1
g
mII
R
I
R
II
C
c
∝
I
Bias
2
I
Bias
∝ I
Bias
1.5
z =
g
mII
C
c
∝ I
Bias
Illustration of the I
bias
dependence →
Plot is done for normalized bias current.

+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
I
Bias
Fig. 6.304D
K
1
I
Bias
K
2
I
Bias
10
3
10
2
10
0
10
1
10
1
10
2
10
3
1 10 100
I
Bias
I
Bias
(ref)
p
1

P
diss and SR
GB and z
A
o
and R
out
Fig. 16005
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 628
Problem 6.313
Develop the
expression similar to
Eq. (6.332) for the
W/L ratio of M6A in
Fig. P6.313 that will
cause the righthalf
plane zero to cancel
the output pole.
Repeat Ex. 6.32
using the circuit of
Fig. P6.313 using
the values of the
transistors in Ex.
6.31.
Solution
R
g
K W L I
Z
m B
P
B
( )
1 1
2 6
6
8
'
Now, z p
1 2
or,
−
− ( )
− 1
1
6
6
C R g
g
C
C Z m A
m A
L
→
−
− ( )
− 1
1 1
6 6
6
C g g
g
C
C m B m A
m A
L
or,
W
L
W
L
I
I
C C
C
A A
C L
C

.
`
}

.
`
}
+ 
.
`
}
6 6
8
7
2
(1)
Referring to Example 6.31
W
L
W
L
A

.
`
}

.
`
}
6 6
94 and, I I I I
8 9 10 11
15 µA
From Equation (1)
W
L
B

.
`
}
≅
6
31 7 32 .
or, g
m B 6
218 µS
g
m A 6
945 µS
R
g
Z
m B
1
4 59
6
. KΩ
z
C R g
C Z m A
1
6
1
1
15
−
− ( )
− MHz.
p
g
C
m A
L
2
6
15
−
− MHz.

+
v
in
M1 M2
M3 M4
M5
M6A
M7
v
out
V
DD
V
SS
V
Bias
+

C
c
C
L
M11 M10
M6B
M8 M9
Figure P6.313 Nulling resistor implemented by a MOS diode.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 629
Problem 6.314
Use the intuitive approach presented in Sec. 5.2 to calculate the smallsignal differential
voltage gain of the twostage op amp of Fig. 6.31.
Solution
Referring to the figure, the smallsignal currents in the first stage can be given by
i i i g
v
d d d m
in
4 3 1 1
2
−
and, i g
v
d m
in
2 2
2
So, i i i g g
v
out d d m m
in
1 4 2 1 2
2
− − + ( )
or, i g v
out m in 1 1
−( )
The smallsignal output conductance of the first stage is
g g g
out ds ds 1 2 4
+
Thus, the smallsignal gain of the first stage becomes
A
g
g g
v
m
ds ds
1
1
2 4
−
+ ( )
Considering the second gain stage, the gain can be given by
A
g
g g
v
m
ds ds
2
6
6 7
−
+ ( )
Thus, the overall smallsignal voltage gain becomes
A A A
g g
g g g g
v v v
m m
ds ds ds ds
+ ( ) + ( )
1 2
1 6
2 4 6 7
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 630
Problem 6.315
A CMOS op amp capable of operating from 1.5V power supply is shown. All device
lengths are 1µm and are to operate in the saturation region. Design all of the W values of
every transistor of this op amp to meet the following specifications.
Slew rate = ±10V/µs V
out
(max) = 1.25V V
out
(min) = 0.75V
V
ic
(min) = 1V V
ic
(max) = 2V GB = 10MHz
Phase margin = 60° when the output pole = 2GB and the RHP zero = 10GB.
Keep the mirror pole ≥ 10GB (C
ox
= 0.5fF/µm
2
).
Your design should meet or exceed these specifications. Ignore bulk effects in this
problem and summarize your W values to the nearest micron, the value of C
c
(pF), and
I(µA) in the following table. Use the following model parameters: K
N
’=24µA/V
2
, K
P
’ =
8µA/V
2
, V
TN
=  V
TP
= 0.75V, λ
N
= 0.01V
1
and λ
P
= 0.02V
1
.
M1 M2
M6
M7
M5
M3 M4
v
out
+1.5V
M8
M9
M10
v
1
v
2
I
10I
C
c
10pF
I I
I
I
1.5I 1.5I
M11 M12
Solution
1.) p
2
=2GB ⇒ g
m6
/C
L
=2g
m1
/C
c
and z=10GB ⇒ g
m6
=10g
m1
. ∴ C
c
= C
L
/5 = 2pF
2.) I = C
c
·SR = (2x10
11
)·10
7
= 20µA ∴ I = 20µA
3.) GB = g
m1
/C
c
⇒ g
m1
= 20πx10
6
·2x10
12
= 40πx10
6
= 125.67µS
W
1
L
1
=
W
2
L
2
=
g
m1
2
2K
N
(I/2)
=
(125.67x10
6
)
2
2·24x10
6
·10x10
6
= 32.9 ⇒ W1 = W
2
= 33µm
4.) V
ic
(min) = V
DS5
(sat.)+V
GS1
(10µA) = 1V→V
DS5
(sat.) = 1
2·10
24·33
0.75 = 0.0908
V
DS5
(sat) = 0.0908 =
2·I
K
N
S
5
→ W
5
=
2·20
24·(0.0908)
2
= 201.9µm W
5
= 202µm
5.) V
ic
(max) = V
DD
V
SD11
(sat)+V
TN
= 1.5V
SD11
(sat)+0.75 = 2V→V
SD11
(sat) = 0.25V
V
SD11
(sat) ≤
2·1.5I
K
P
·S
11
→ S
11
= W
11
≥
2·30
(0.25)
2
·8
= 120 →
W
11
=W
12
≥120µm
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 631
Problem 6.315  Continued
6.) Choose S
3
(S
4
) by satisfying V
ic
(max) specification then check mirror pole.
V
ic
(max) ≥ V
GS3
(20µA) + V
TN
→ V
GS3
(20µA) = 1.25V ≥
2·I
K
N
·S
3
+ 0.75V
S
3
= S
4
=
2·20
(0.5)
2
·24
= 6.67 ⇒ W
3
= W
4
= 7µm
7.) Check mirror pole (p
3
= g
m3
/C
Mirror
).
p
3
=
g
m3
C
Mirror
=
g
m3
2·0.667·W
3
·L
3
·C
ox
=
2·24·6.67·20x10
6
2·0.667·6.67·0.5x10
15
= 17.98x10
9
which is much greater than 10GB (0.0628x10
9
). Therefore, W
3
and W
4
are OK.
8.) g
m6
= 10g
m1
= 1256.7µS
a.) g
m6
= 2K
N
S
6
10I ⇒ W
6
= 164.5µm
b.) V
out
(min) = 0.5 ⇒ V
DS6
(sat) = 0.5 =
2·10I
K
N
S
6
⇒ W
6
= 66.67µm
Therefore, use W
6
= 165µm
Note: For proper mirroring, S
4
=
I
4
I
6
S
6
= 8.25µm which is close enough to 7µm.
9.) Use the V
out
(max) specification to design W
7
.
V
out
(max) = 0.25V ≥ V
DS7
(sat) =
2·200µA
8x10
6
·S
7
∴ S
7
≥
400µA
8x10
6
(0.25)
2
⇒ W
7
= 800µm
10.) Now to achieve the proper currents from the current source I gives,
S
9
= S
10
=
S
7
10
= 80 → W
9
= W
10
= 80µm
and
S
11
= S
12
=
1.5·S
7
10
= 120 → W
11
= W
12
= 120µm. We saw in step 5 that W
11
and W
12
had to be greater than 120µm to satisfy V
ic
(max). ∴ W
11
=W
12
=120µm
11.) P
diss
= 15I·1.5V = 300µA·1.5V = 450µW
C
c
I W1=W2 W3=W4 W5=W8 W6 W7 W9=W10 W11=W12 P
diss
2pF 20µA 33µm 7µm 202µm 165µm 800µm 80µm 120µm 450µW
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 632
Problem 6.316
A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small
signal output resistance, R
out
, and from this value estimate the 3dB bandwidth if a 50pF
capacitor is attached to the output. What is the maximum and minimum output voltage if a
1kΩ resistor is attached to the output? What is the quiescent power dissipation of this
circuit? Use the following model parameters: K
N
’=24µA/V
2
, K
P
’ = 8µA/V
2
, V
TN
=  V
TP
= 0.75V, λ
N
= 0.01V
1
and λ
P
= 0.02V

1.

+
v
out
C
c
v
in
M1
M3 M4
M5
M6
M7
V
DD
= 2.5V
V
SS
= 2.5V
M2
M9
M8
20
30
1
2
3 4
17
M10
7
6
5
4/2
4/2
5/1 5/1
8/1
20/1
16/1
1/5
10/1
1/1
+

v
in
v
out
1.5V
1.5V
v
out
t
Figure P6.316
Solution
Considering the Miller compensation path, the value of the nulling resistor implemented by
M
10
is given by
R
K W L V V V
Z
N DD S T
( ) − − ( )
1
10
10 10
'
(1)
The zero created at the output is given by
z
C R g
C Z m
1
6
1
1
−
− ( )
(2)
a.) When the output swings high, the voltage at the source of M
10
goes low assuming the
compensation capacitor tends to get shortcircuited. Thus, V V V
DD S T
− − ( )
10 10
increases
causing a decrease in the value of R
Z
. Also, as the voltage at the gate of M
6
goes down,
the current in M
6
decreases causing a decrease in value of g
m6
. Referring to Equation (2), a
decrease in both R
Z
and g
m6
would tend to place the zero in the right half plane and it
would degrade the phase margin causing the op amp to oscillate.
b.) When the output swings low, the voltage at the gate of M
6
and the source of M
10
goes
up. This decreases V V V
DD S T
− − ( )
10 10
causing an increase in R
Z
. Also, as the voltage at the
gate of M
6
increases, the current through M
6
increases causing and increase in g
m6
. Thus,
from Equation (2), an increase in R
Z
and g
m6
would create a LHP zero which would make
the op amp more stable.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 633
Problem 6.401
Sketch the asymptotic frequency response of PSRR
+
and PSRR

of the twostage op amp
designed in Example 6.31.
Solution
Referring to Example 6.31, for the positive PSRR, the poles and zeros are
( )
361
) 0 (
6
1
II v
ds
G A
g GB
p
Hz.
5
1
GB z
MHz.
15
2 2
p z
MHz.
For the negative PSRR, the poles and zeros are
( )
6 . 71
1
1
m
I
g
G GB
p
KHz.
5
1
GB z
MHz.
15
2 2
p z
MHz.
The magnitude of the positive and negative PSRR is shown below.
20
0
20
40
60
80
10 100 1000 10
4
10
5
10
6
10
7
10
8
M
a
g
n
i
t
u
d
e
(
d
B
)
Frequency (Hz)
PSRR
+
PSRR

CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 634
Problem 6.402
Find the low frequency PSRR
and all roots of the positive and
negative power supply rejection
ratio performance for the two
stage op amp of Fig. P6.39.
Solution
Referring to the figure
( ) ( )
9
’
8
8
’
8
9 8
2 2
L W K
I
L W K
I
V V V V
P N
T T SS DD
+ + + −
or,
60
8
I
A µ
Now,
3 . 363
1
m
g S µ
,
4 . 2
2
ds
g S µ
,
3
4
ds
g S µ
,
6 . 774
6
m
g S µ
,
30
6
ds
g S µ
and
24
7
ds
g
S µ
∴
3 . 67
1
v
A
and
3 . 14
2
v
A
For the positive PSRR, the low frequency PSRR is
1737
) 0 (
6
+
ds
II v
g
G A
PSRR
and poles and zeros are
( )
66 . 6
) 0 (
6
1
II v
ds
G A
g GB
p
KHz,
6 . 11
1
GB z
MHz. and
2 . 6
2 2
p z
MHz.
For the negative PSRR, the low frequency PSRR is given by
2171
) 0 (
7
−
ds
II v
g
G A
PSRR
and the poles and zeros are
( )
4 . 172
1
1
m
I
g
G GB
p
KHz,
6 . 11
1
GB z
MHz and
2 . 6
2 2
p z
MHz.
M1 M2
M3 M4
M5
M6
M7 M8
+1.5V
1.5V
v
in
C
c
=5pF
20pF
1/1 2/1 10/1
10/1
100/1
10/1
10/1 10/1
v
o
1/1
I
8
I
5
I
7
+

Figure P6.310
M9
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 635
Problem 6.403
Repeat the analysis of the positive PSRR of Fig. 6.42 if the Miller compensation circuitry
of Fig. 6.215(a) is used. Compare the low frequency magnitude and roots with those of
the positive PSRR for Fig. 6.42.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 636
Problem 6.404
In Fig. P6.44, find v
out
/v
ground
and identify the lowfrequency gain and the roots. This
represents the case where a noisy ac ground can influence the noise performance of the
twostage op amp.
M1
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+

C
c
C
L
M2
Figure P6.44
v
ground
Solution
Let, v v
v
dd ss
ground
−
2
and, v
5
be the smallsignal ac voltage at the drain of M
5
.
Applying nodal analysis
g v v g v g v v g v g v v r v
m out m ss ds dd m ds ds 2 5 5 2 5 1 5 1 1 5 5 5
− ( ) + + − ( ) − + − ( ) ( )
or, v
g v g v g v
g g
m out ds dd m ss
m m
5
2 2 5
1 2
+ + ( )
+ ( )
(1)
Now,
g v v g v v g v g v v g v v sC v v
m out ds dd m ds dd ds C out 2 5 2 5 1 5 3 1 1 1 5 1
− ( ) + − ( ) + + − ( ) ( ) − ( ) + − ( ) ( )
or, g sC v g g v g g sC v
m C out ds ds dd ds ds C 2 2 3 1 3 1
+ ( ) + + ( ) + + ( ) (2)
Also,
sC v v g v g v v g v v sC v g v v
C out m ss ds out dd ds out ss L out m dd 1 7 6 7 6 1
− ( ) + ( ) − ( ) + − ( ) + + − ( ) ( )
Using v v
dd ss
− , we get
g g g g v g g s C C v g sC v
m m ds ds dd ds ds C L out m C 6 7 6 7 6 7 6 1
− + − ( ) + + + ( ) ( ) + − ( ) (3)
Using Equations (2) and (3) gives the low frequency PSRR as
v
v
g g
G g g g
out
ground
mI mII
I ds ds m
− − ( )
]
]
]
−
2
6 7 7
1
The zero is
z
G g g g
C G g g g g
I ds ds m
C I m m ds ds
1
6 7 7
6 7 6 7
≅ −
− − ( )
+ − + − ( )
The two poles are same as given by the zeros of Equation (6.414) in the text.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 637
Problem 6.405
Repeat the analysis of Fig.
6.42 and Fig. 6.44 for the
pchannel input, twostage
op amp shown in Fig. P6.4
5.
Solution
TBD
v
out
C
c
C
L
M1
M3 M4
M5
M6
M7
V
DD
V
SS
V
Bias
+

M2
Figure P6.45
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 638
Problem 6.501
Assume that in Fig. 6.51(a) that the currents in M1 and M2 are 50µA and the W/L values
of the NMOS transistors are 10 and of the PMOS transistors are 5. What is the value of
V
Bias
that will cause the drainsource voltage of M1 and M2 to be equal to V
ds
(sat)? Design
the value of R. to keep the sourcedrain voltage of M3 and M4 equal to V
sd
(sat). Find an
expression for the smallsignal voltage gain of v
o1
/v
in
for Fig. 6.51(a).
Solution
1 , 1 , 1 , M dsat MC dsat MC T BIAS
V V V V + +
or,
1
’
1
1
’
1
1 ,
2 2
}
`
.

+
}
`
.

+
L
W
K
I
L
W
K
I
V V
N
C
N
MC T BIAS
Ignoring bulk effects
V
BIAS
= 1.3V
Now,
3 3 , 3 , 3 , dsat C dsat C T C G
V V V V + +
3 3 3 dsat T G
V V V +
And, 3 , 3 3 , C dsat G C G
V V V IR −
or, R
IK
W
L
P
C

.
`
}
2
3
'
=
12.65k Ω
The output impedance is given by
[ ] [ ]
2 2 , 2 , 4 4 , 4 ,

ds C ds C m ds C ds C m out
r r g r r g R
38 . 19
out
R
Ω M
The smallsignal voltage gain is given by
A
v
= g
m,C2
R
out
= 6248 V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 639
Problem 6.502
If the W/L values of M1, M2, MC1 and MC2 in Fig. 6.51(b) are 10 and the currents in
M1 and M2 are 50µA, find the W/L values of MB1 through MB5 that will cause the drain
source voltage of M1 and M2 to be equal to V
ds
(sat). Assume that MB3 = MB4 and the
current through MB5 is 5µA. What will be the current flowing through M5?
Solution
Let,
5
5
B
I
A µ
1 1 , 1 , 5 , 5 , dsat C dsat C T B dsat B T
V V V V V + + +
or,
( ) ( ) ( )
1
’
1
1
’
1
1 ,
5
’
5
5 ,
2 2 2
L W K
I
L W K
I
V
L W K
I
V
N
C
N
C T
B
N
B
B T
+ + +
Ignoring bulk effects, and assuming
50
1
I
A µ
4
1
5
}
`
.

B
L
W
The aspect ratios of the transistors MB1 through MB4 can be chosen (assumed) to be 1.
The total current through M5 is 110 µA .
Problem 6.503
In Fig. 6.51(a), find the smallsignal impedance to ac ground looking into the sources of
MC2 and MC4 assuming there is no capacitance attached to the output. Assume the
capacitance to ground at these nodes is 0.2pF. What is the value of the poles at the sources
of MC3 and MC4? Repeat if a capacitor of 10pF is attached to the output.
Solution
Let, 1
C
and L
C
be the capacitances at the source of MC2 (and MC4) and the output
respectively. The impedance looking between the drain of M4 and Vdd (ac ground), 4
Z
,
be
( )
1 4
4
1
sC g
Z
ds
+
The impedance looking between the drain of MC4 and Vdd (ac ground),
4 C
Z
, be
( )
]
]
]
]
+
+
L
C m
C ds ds
C
sC
g
g sC g
Z
4 ,
4 , 1 4
4
1
Thus, the impedance looking between the source of MC2 and Vdd (ac ground),
2 ,C S
Z
,
can be expressed as
]
]
]
]
]
]
]
+
+
1 2 , 2 ,
4 2 ,
2 ,
1

1 sC r g
Z r
Z
C ds C m
C C ds
C S
or,
]
]
]
]
]
]
]
≅
1 2 , 2 ,
4
2 ,
1

sC r g
Z
Z
C ds C m
C
C S
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 640
Problem 6.503  Continued
or,
( )
]
]
]
]
]
]
]
+ +
+
1
2 ,
2 ,
2 , 4 ,
4 , 1 4 2 ,
2 ,
1
sC C
g
g
s
g g
g sC g g
Z
L
C ds
C m
C ds C m
C ds ds C m
C S
or,
]
]
]
]
]
]
]
]
}
`
.

}
`
.

+ + +
1
2 , 4 ,
4 , 2 ,
2 ,
2 ,
2 , 4 ,
4 , 4 2 ,
2 ,
1
1
C
g g
g g
C
g
g
s
g g
g g g
Z
C ds C m
C ds C m
L
C ds
C m
C ds C m
C ds ds C m
C S
Similarly, the impedance looking from the source of MC4 to ac ground, 4 ,C S
Z
, can be
expressed as
]
]
]
]
]
]
]
]
}
`
.

}
`
.

+ + +
1
4 , 2 ,
2 , 4 ,
4 ,
4 ,
4 , 2 ,
2 , 2 4 ,
4 ,
1
1
C
g g
g g
C
g
g
s
g g
g g g
Z
C ds C m
C ds C m
L
C ds
C m
C ds C m
C ds ds C m
C S
Referring to problem 6.53, we have
1 . 158
4 4 ,
m C m
g g
S µ
7 . 331
2 2 ,
m C m
g g
S µ
5 . 2
4 4 ,
ds C ds
g g
S µ
2
2 2 ,
ds C ds
g g
S µ
When
0
L
C
( )]
]
]
]
× + ×
− − 12 6
2 ,
10 72 . 0 10 6 . 6
1
s
Z
C S
Ω
( )]
]
]
]
× + ×
− − 12 6
4 ,
10 27 . 0 10 76 . 0
1
s
Z
C S
Ω
When
10
L
C
pF
( )]
]
]
]
× + ×
− − 12 6
2 ,
10 1659 10 6 . 6
1
s
Z
C S
Ω
( )]
]
]
]
× + ×
− − 12 6
4 ,
10 7 . 632 10 76 . 0
1
s
Z
C S
Ω
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 641
Problem 6.504
Repeat Example 6.51 to find new values of W
1
and W
2
which will give a voltage gain of
10,000.
Solution
From Example 6.51
25
out
R
Ω M
Thus, for
000 , 10
v
A
400
1
out
v
m
R
A
g
S µ
or,
1
5 . 14
2
1
’
2
1
2 1
}
`
.

}
`
.

I K
g
L
W
L
W
N
m
Problem 6.505
Find the differentialvoltage gain of Fig. 6.51(a) where the output is taken at the drains of
MC2 and MC4, W
1
/L
1
W
2
/L
2
10 µm/1 µm, W
C1
/L
C1
W
C2
/L
C2
W
C3
/L
C3
W
C4
/L
C4
= 1 µm/1 µm, W
3
/L
3
W
4
/L
4
1 µm/1 µm, and I
5
100 µA. Use the model
parameters of Table 3.12 . Ignore the bulk effects.
Solution
100
5
I
A µ
67 . 331
2 1
m m
g g
S µ
8 . 104
2 ,
C m
g
S µ
7 . 70
4 ,
C m
g
S µ
400
4 4 ,
ds C ds
r r
Ω K
500
2 2 ,
ds C ds
r r
Ω K
The output impedance is given by
[ ] [ ]
4 4 , 4 , 2 2 , 2 ,

ds C ds C m ds C ds C m out
r r g r r g R
or,
[ ] [ ] Ω M M M R
out
9 . 7 3 . 11  2 . 26
So, A g R V V
v
m
out
− −
2
2620 /
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 642
Problem 6.506
A CMOS op amp that uses a 5V power supply is shown. All transistor lengths are
1µm and operate in the saturation region. Design all of the W values of every transistor of
this op amp to meet the following specifications. Use the following model parameters:
K
N
’=110µA/V
2
, K
P
’=50µA/V
2
, V
TN
=0.7V, V
TP
=0.7V, λ
N
=0.04V
1
and λ
P
=0.05V
1
.
Slew rate = ±10V/µs V
out
(max) = 4V V
out
(min) = 1V
V
ic
(min) = 1.5V V
ic
(max) = 4V GB = 10MHz
Your design should meet or exceed these specifications. Ignore bulk effects and
summarize your W values to the nearest micron, the bias current, I
5
(µA), the power
dissipation, the differential voltage gain, A
vd
, and V
BP
and V
BN
in the following table.
Assume that V
bias
is whatever value necessary to give I
5
.
W1=W2 W3=W4=W6
=W7=W8
W9=W10
=W11
W5
I
5
(µA) A
vd
V
BP
V
BN
P
diss
89.75 40 18.2 13.75 250µA 17,338V/V 3.3V 1.7V 2.5mW
M1 M2
M3 M4
M5
M6
M7
M8
M9 M10
M11
25pF
v
out
V
DD
= 5V
v
1
v
2
V
BP
V
BN
V
Bias
I
5
I
9
I
10
S01FEP2
Solution
Since W3 =W4 =W6 =W7 =W8 and W9 =W10 =W11, then I
5
is the current available to
charge the 25pF load capacitor. Therefore,
I
5
= C
dv
OUT
dt
= 25pF(10V/µs) = 250µA
Note that normally, I
10
= I
9
= 125µA. However, for the following calculations we will
use I
6
or I
10
equal to 250µA for the following v
OUT
(max/min) calculations.
v
OUT
(max) = 4V ⇒ 0.5 =
2I
5
K
P
'(W6/L6)
=
2I
5
K
P
'(W6/L6)
W 6 = W 7 = 40 = W 3 = W 4 = W 8
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 643
Problem 6.507
Verify Eqs. (6.54) through (6.58) of Sec. 6.5 for the twostage op amp of Fig. 6.53
having a cascode second stage. If the second stage bias current is 50 µA and W
6
/L
6
W
C6
/L
C6
W
C7
/L
C7
W
7
/L
7
1 µm/1 µm, what is the output resistance of this
amplifier using the parameters of Table 3.12?
Solution
From intuitive analysis, it can be shown that
A
g
g g
v
m
ds ds
1
1
2 4
−
+ ( )
For the second gain stage, the output resistance of the cascode stage can be given by
R g r r g r r
II m C ds C ds m C ds C ds
[ ] [ ]
, , , ,

6 6 6 7 7 7
or, A g R
v m II 2 6
−
Thus, A A A
g g
g g g r r g r r
v v v
m m
ds ds m C ds C ds m C ds C ds
+ ( ) [ ] [ ] { ¦
1 2
1 6
2 4 6 6 6 7 7 7 , , , ,

For, I
7
50
A µ
R M M
II
[ ] [ ] 11 3 26 2 7 9 .  . . MΩ
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 644
Problem 6.508
Verify Eqs. (6.59) through (6.511) of Sec. 6.5 assuming that M3 = M4 = M6 = M8 and
M9 = M10 = M11 = M12 and give an expression for the overall differentialvoltage gain of
Fig. 6.54.
Solution
Solving the circuit intuitively
The effective transconductance of the first stage
g
g
mI
m
1
2
The effective conductance of the first stage
g g
I m
3
The effective transconductance of the second stage
g g g
mII m m
+ ( )
6 11
The effective conductance of the second stage
g
g g
g
g g
g
II
ds ds
m
ds ds
m
+
6 7
7
11 12
12
Now,
A
g
g
v
m
m
1
1
3
2
−
A
g g
g g
g
g g
g
v
m m
ds ds
m
ds ds
m
2
6 11
6 7
7
11 12
12
−
+ ( )
+
]
]
]
or, A
g g g
g
g g
g
g g
g
v
m m m
m
ds ds
m
ds ds
m
+ ( )
+
]
]
]
1 6 11
3
6 7
7
11 12
12
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 645
Problem 6.509
An internally
compensated, cascode
op amp is shown in
Fig. P6.5.9. (a)
Derive an expression
for the commonmode
input range. (b) Find
W
1
/L
1
, W
2
/L
2
, W
3
/L
3
,
and W
4
/L
4
when I
BIAS
is 80 µA and the input
CMR is −3.5 V to 3.5
V. Use K'
N
25
µA/V
2
, K'
p
11
µA/V
2
and V
T
 0.8
to 1.0 V.
Solution
The minimum input
commonmode voltage can be given by
V V V V V
in SS T dsat dsat
(min) (max) + − −
1 1 7
V V V
I
K W L
I
K W L
in SS T
N N
(min) (max)
' '
+ −
( )
−
( )
1
7
1
7
7
2
(1)
The maximum input commonmode voltage can be given by
V V V V V V
in DD T T dsat dsat
(max) (min) (max) + − − −
1 5 3 5
V V V V
I
K W L
I
K W L
in DD T T
P P
(max) (min) (max)
' '
+ − −
( )
−
( )
1 5
7
3
7
5
(2)
The input commonmode range is given by
ICMR V V
in in
− (max) (min)
which can be derived from Equations (1) and (2).
Given I
7
40 µA, V
in
(min) . −2 5 V and W L ( )
7
3, from Equation (1)
W
L
W
L
m
m

.
`
}

.
`
}
µ
µ
1 2
64
10
Also, for I
7
40 µA, V
in
(max) . 3 5 V and assuming W L ( )
5
6, from Equation (2)
W
L
W
L
m
m

.
`
}

.
`
}
µ
µ
3 4
135
10
v
in
M1
M5 M6
M7
M8
M9
v
out
V
DD
= 5V
V
SS
= 5V
C
c
C
L

+
M2
M3
M4
M10
M11
M12
I
Bias
I
7
60/10
60/10
30/10
Figure P6.59
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 646
Problem 6.510
Develop an expression for
the smallsignal differential
voltage gain and output
resistance of the cascode op
amp of Fig. P6.59.
Solution
The output resistance of the
first gain stage is
6 1 ds out
r R ≅
So,
6 1 1 1 1 ds m out m v
r g R g A − −
The output resistance of the second gain stage is
( )
9 8
2
1
ds ds
out
g g
R
+
So,
( )
9 8
8
2 8 2
ds ds
m
out m v
g g
g
R g A
+
− −
The overall smallsignal gain is
2 1 v v v
A A A
or,
( )
9 8 6
8 1
ds ds ds
m m
v
g g g
g g
A
+
or,
( ) ( )
( )
2 2
9 7
8 1
’ ’
8
P N P
P N
v
I I
L W L W K K
A
λ λ λ +
The smallsignal output resistance is given by
( )
9 8
2
1
ds ds
out out
g g
R R
+
v
in
M1
M5 M6
M7
M8
M9
v
out
V
DD
= 5V
V
SS
= 5V
C
c
C
L

+
M2
M3
M4
M10
M11
M12
I
Bias
I
7
60/10
60/10
30/10
Figure P6.59
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 647
Problem 6.511
Verify the upper input common mode range of Ex. 6.52, step 6.) for the actual value of S
3
= S
4
of 40.
Solution
The maximum input commonmode voltage is given by
3 3 1
(max) (min) (max)
dsat T T DD in
V V V V V − − +
or,
( )
3
’
3
3 1
2
(max) (min) (max)
L W K
I
V V V V
P
T T DD in
− − +
or, V V
in
(max) . 1 98
Problem 6.512
Repeat Example 6.52 if the differential input pair are PMOS transistors (i.e. all NMOS
transistors become PMOS and all PMOS transistors become NMOS and the power supplies
are reversed).
M
5
M
1
M
2
V
BIAS
V
DD
V
SS
M
3
M
4
M
8
M
10
M
9
R
1
M
13
M
14
R
2
M
6
M
7
M
15 M
11
M
12
V
out
C
L
Solution
To satisfy the slew rate
250
11 12 7 6
I I I I
A µ
and let
100
5
I
A µ
The maximum output voltage is 1.5 V
5 . 0
7 6
dsat dsat
V V
V →
40
10 9 7 6
S S S S
Similarly, considering the minimum output voltage as –1.5 V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 648
Problem 6.512  Continued
5 . 0
12 11
dsat dsat
V V
V →
2 . 18
15 14 12 11
S S S S
The value of R1 and R2 can be calculated as
2
8
7
1
I
V
R
dsat
Ω K
and,
2
15
12
2
I
V
R
dsat
Ω K
Now,
( )
8 6
3
1
2
m m II
v m
m
g g kR
A g
g
+
and,
5 . 2
4
6
S
S
k
and
11 ≅
II
R
Ω M
Thus,
9 . 107
1
m
g
S µ
Also,
( )
149
2
8 6
3
1
+
m m
m
m
g g k
GB g
g
S µ
So, let us choose
149
1
m
g
S µ
. →
4 . 4
2 1
S S
But for this value of
4 . 4
2 1
S S
, from the expression of maximum input common
mode voltage, we will get
025 . 0
5
dsat
V
V which is too small. So let us choose
20
2 1
S S
This, from the expression of
(max)
in
V
, will give
7 . 27
5
S
Or,
6 . 34 25 . 1
5 13
S S
and,
40 5 . 2
3 8
S S
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 649
Problem 6.513
A CMOS op amp that uses a 5V
power supply is shown. All
transistor lengths are 1µm and
operate in the saturation region.
Design all of the W values of
every transistor of this op amp
to meet the following
specifications: Slew rate =
±10V/µs, V
out
(max) = 4V,
V
out
(min) = 1V, V
ic
(min) =
1.5V, V
ic
(max) = 4V and GB =
10MHz.
Your design should
meet or exceed these
specifications. Ignore bulk
effects and summarize your W
values to the nearest micron, the
bias current, I
5
(µA), the power
dissipation, the differential
voltage gain, A
vd
, and V
BP
and V
BN
in the table shown.
Solution
1.) I
5
= C
L
·SR = 250µA
2.) g
m1
= GB·C
L
·= 20πx106·25pF = 1,570.8µS ⇒
W
1
L
1
=
(1.570x10
3
)
2
2·110·125x10
6
= 90
3.) W3=W4=W6=W7=W8 =
2I
D
K’(V
DS
(sat))
2
=
2·250
50·0.25
= 40 (assumed I
D
of 250µA
worst case)
4.) W9=W10=W11 =
2I
D
K’(V
DS
(sat))
2
=
2·250
110·0.25
= 18 (assumed I
D
of 250µA worst case)
5.) V
icm
(min) = V
DS5
(sat) + V
GS1
→ V
DS5
(sat) = 1.5  (0.159+0.7) = 0.6411V
∴ W5 =
2I
D
K’(V
DS
(sat))
2
=
2·250
110·0.6411
2
= 11
6.) A
vd
= g
m1
R
out
g
mN
= 704µS, r
dsN
= 0.2MΩ, g
mP
= 707µS, r
dsN
= 0.16MΩ
R
out
≈ g
mN
· r
dsN
2
 g
mP
· r
dsP
2
= 28.14MΩ18.1ΜΩ 11ΜΩ
∴ A
vd
= 1.57mS·11MΩ = 17,329V/V
7.) V
BP
= 5V
DSP
(sat) + V
GSP
(sat) = 50.5+0.5+0.7 = 3.3V
V
BN
= V
DSP
(sat) + V
GSP
(sat) = 0.5+0.5+0.7 = 1.7V
8.) P
diss
= 5(250µA + 250µA) = 2.5mW
W1=W2 W3=W4=W6
=W7=W8
W9=W10
=W11
W5 I
5
(µA) A
vd
V
BP
V
BN
P
diss
90 40 18 11 250µA 17,324V/V 3.3V 1.7V 2.5mW
M1 M2
M3 M4
M5
M6
M7
M8
M9 M10
M11
25pF
v
out
V
DD
= 5V
v
1
v
2
V
BP
V
BN
V
Bias
I
5
I
9
I
10
Figure P6.513
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 650
Problem 6.514
Repeat Example 6.53 if the differential input pair are PMOS transistors (i.e. all NMOS
transistors become PMOS and all PMOS transistors become NMOS and the power supplies
are reversed).
M
3
M
1
M
2
V
BIAS
V
DD
V
SS
M
4
M
10
M
8
R
2
M
12
M
13
R
1
M
11
M
9
M
14 M
5
M
7
V
out
C
L
M
6
Solution
100
3
I
A µ
and,
125
5 4
I I
A µ
Given,
2 (max)
out
V
V →
25 . 0
11 9
dsat dsat
V V
V
Considering worstcase peak sourcing current of 125
A µ
80
11 10 9 8
S S S S
Given,
2 (min) −
out
V
V →
25 . 0
5 7
dsat dsat
V V
V
Considering worstcase peak sinking current of 125
A µ
125
5
I
A µ
and
25
7
I
A µ
3 . 7
13 7 6
S S S
And,
4 . 36
14 5 4
S S S
2
14
7
1
I
V
R
dsat
Ω K
and
2
10
9
2
I
V
R
dsat
Ω K
From gainbandwidth
( )
79
3
’
2 2
2 1
I K
C GB
S S
P
L
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 651
Problem 6.514  Continued
Considering
1 (max)
in
V
V
43 . 0
3
dsat
V
V →
6 . 21
3
S
The minimum input commonmode voltage is
8 . 2 (min) (min)
4 1
− + −
dsat T SS in
V V V V
V
Finally,
27 25 . 1
3 12
S S
The smallsignal gain is
( )
( )
II mI v
R g
k
k
A
2 2
2
+
+
( )
( )
7 7
4 2 9
ds m
ds ds
r g
g g R
k
+
where,
55
9
R
Ω M
3 . 628
mI
g
S µ
,
347
7
m
g
S µ
,
3
7
ds
g
S µ
,
5
4
ds
g
S µ
,
5 . 2
2
ds
g
S µ
So,
96 . 3 k
12
II
R
Ω M
or,
4364
v
A
V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 652
Problem 6.515
This problem deals
with the op amp
shown in Fig.
P6.515. All
device lengths are
1µm, the slew rate
is ±10V/µs, the GB
is 10MHz, the
maximum output
voltage is +2V, the
minimum output
voltage is 2V, and
the input common
mode range is from
1V to +2V.
Design all W values
of all transistors in
this op amp. Your
design must meet or
exceed the specifications. When calculating the maximum or minimum output voltages,
divide the voltage drop across series transistors equally. Ignore bulk effects in this
problem. When you have completed your design, find the value of the small signal
differential voltage gain, A
vd
= v
out
/v
id
, where v
id
= v
1
v
2
and the small signal output
resistance, R
out
.
Solution
1.) The slew rate will specify I. ∴ I = C·SR = 10
11
·10
7
= 10
4
= 100µA.
2.) Use GB to define W
1
and W
2
.
GB =
g
m1
C
→ g
m1
= GB·C = 2πx10
7
·10
11
= 628µS
∴ W
1
=
g
m1
2
2K
N
(0.5I)
=
(628)
2
2·110·50
= 35.85 ⇒ W
1
= W
2
= 36µm
3.) Design W
15
to give V
T
+2V
ON
bias for M6 and M7. V
ON
= 0.5V will meet the desired
maximum output voltage specification. Therefore,
V
SG15
= V
ON15
+ V
T
 = 2(0.5V) + V
T
 → V
ON15
= 1V =
2I
K
P
W
15
∴ W
15
=
2I
K
P
V
ON15
2
=
2·100
50·1
2
= 4µm ⇒ W
15
= 4µm
4.) Design W
3
, W
4,
W
6
and W
7
to have a saturation voltage of 0.5V with 1.5I current.
W
3
=W
4
=W
6
=W
7
=
2(1.5I)
K
P
V
ON
2
=
2·150
50·0.5
2
= 24µm ⇒ W
3
= W
4
= W
6
= W
7
= 24µm
+3V
3V
I
I
I
0.5I 0.5I
1.5I
1.5I
I
I
I
v
out
10pF
v
1
v
2
M1
M2
M3 M4
M5
M6 M7
M8 M9
M10 M11 M12
M13
M15
M14
Figure P6.515
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 653
Problem 6.515 – Continued
5.) Next design W
8
, W
9,
W
10
and W
11
to meet the minimum output voltage specification.
Note that we have not taken advantage of smallest minimum output voltage because a
normal cascode current mirror is used which has a minimum voltage across it of V
T
+
2V
ON
. Therefore, setting V
T
+ 2V
ON
= 1V gives V
ON
= 0.15V. Using worst case
current, we choose 1.5I. Therefore,
W
8
=W
9
=W
10
=W
11
=
2(1.5I)
K
N
V
ON
2
=
2·150
110·0.15
2
= 121µm ⇒ W
8
= W
9
= W
10
= W
11
=
121µm
6.) Check the maximum ICM voltage.
V
ic
(max) = V
DD
+ V
SD3
(sat) + V
TN
= 3V – 0.5 + 0.7 = 3.2V which exceeds spec.
7.) Use the minimum ICM voltage to design W
5
.
V
ic
(min) = V
SS
+ V
DS5
(sat) + V
GS1
= 3 + V
DS5
(sat) +
.

}
` 2·50
110·36
+0.7 = 1V
∴ V
DS5
(sat) = 1.141 →W
5
=
2I
K
N
V
DS5
(sat)
2
= 1.39µm = 1.4µm
Also, let W
12
=W
13
=W
5
⇒ W
12
= W
13
= W
5
= 1.4µm
8.) W
14
is designed as
W
14
= W
3
I
14
I
3
= 24µm
I
1.5I
= 16µm ⇒ W
14
= 16µm
Now, calculate the op amp smallsignal performance.
R
out
≈ r
ds11
g
m9
r
ds9
g
m7
r
ds7
(r
ds2
r
ds4
)
g
m9
= 2K
N
·I·W
9
= 1632µS, r
ds9
= r
ds11
=
25V
100µA
= 0.25MΩ,
g
m7
= 2K
P
·I·W
7
= 490µS, r
ds7
=
20V
100µA
= 0.2MΩ, r
d2
=
25V
50µA
= 0.5MΩ
r
ds4
=
20V
150µA
= 0.1333MΩ ∴ R
out
≈ 102ΜΩ10.31ΜΩ 9.3682ΜΩ
A
vd
=
.

}
`
2+k
2+2k
g
m1
R
out,
k =
102MΩ
(r
ds2
r
ds4
)g
m7
r
ds7
= 9.888, g
m1
= K
N
·I·W
1
= 629µS
∴ A
vd
= (0.5459)(629µS)(9.3682MΩ) = 3,217V/V ⇒ A
vd
= 3,217V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 654
Problem 6.516
The small signal resistances looking into the sources of M6 and M7 of Fig. P6.515 will be
different based on what we learned for the cascode amplifier of Chapter 5. Assume that the
capacitance from each of these nodes (sources of M6 and M7) are identical and determine
the influence of these poles on the smallsignal differential frequency response.
Solution
The resistance looking from the output to Vss is
11 9 9 9 ds ds m D
r r g R ≅
The resistance looking at the source of M7 is
( )
( )
7 7
9 7
1
ds m
D ds
B
r g
R r
R
+
+
or,
( )
( )
7 7
11 9 9
ds m
ds ds m
B
r g
r r g
R ≅
(1)
The resistance looking from the drain of M8 to V
ss
is
10 8
8
1 1
m m
D
g g
R +
The resistance looking at the source of M6 is
( )
( )
6 6
8 6
1
ds m
D ds
A
r g
R r
R
+
+
→
6
1
m
B
g
R ≅
(2)
The poles at the sources of M6 and M7 are
C
g
C R
p
m
A
A
6
1
− ≅ −
and
C r C R
p
ds B
B
1 1
− ≅ −
Both of these poles will appear as output poles in the overall voltage transfer function.
Problem 6.601
How large could the offset voltage in Fig. 6.61 be before this method of measuring the
openloop response would be useless if the openloop gain is 5000 V/V and the power
supplies are ±2.5V?
Solution
Given,
5 −
SS DD
V V
V, and
5000
v
A
V/V
Therefore, the offset voltage should be less than
( )
v
SS DD
os
A
V V
V
−
<
or,
1 <
os
V
mV
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 655
Problem 6.602
Develop the closedloop frequency response for op amp circuit shown which is used to
measure the openloop frequency reasponse. Sketch the closedloop frequency response of
the magnitude of V
out
/V
in
if the low frequency gain is 4000 V/V, the GB = 1MHz, R =
10MΩ, and C = 10µF. (Ignore R
L
and C
L
)
v
IN
v
OUT
V
DD
V
SS
R
L C
L
R
C
S01E2P2
Solution
The openloop transfer function of the op amp is,
A
v
(s) =
GB
s +(GB/A
v
(0))
=
2πx10
6
s +500π
The closedloop transfer function of the op amp can be expressed as,
v
OUT
= A
v
(s)
]
]
.

}
`
1/sC
R+(1/sC)
v
OUT
+v
IN
= A
v
(s)
]
]
.

}
`
1/RC
s+(1/RC)
v
OUT
+v
IN
∴
v
OUT
v
I N
=
[s +(1/RC)]A
v
(s)
s +(1/RC)+A
v
(s)/RC
=
[s +(1/RC)]
s +(1/RC)
A
v
(s)
+1/RC
=
(s+0.01)
s +0.01
A
v
(s)
+0. 01
Substituting, A
v
(s) gives,
v
OUT
v
I N
=
2πx10
6
s 2πx10
4
(s+0.01)(s+500π)+2πx10
4
=
2πx10
6
s 2πx10
4
s
2
+500πs +2πx10
4
=
2πx10
6
(s +0.01)
(s+41.07)(s+1529.72)
The magnitude of the closedloop frequency response is plotted below.
20
0
20
40
60
80
0.001 0.1 10 1000 10
5
10
7
M
a
g
n
i
t
u
d
e
,
d
B
Radian Frequency (radians/sec)
A
v
(jω)
V
out
(jω)
V
in
(jω)
S01E2S2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 656
Problem 6.603
Show how to modify Fig. 6.66 in order to measure the openloop frequency response of
the op amp under test and describe the procedure to be followed.
Solution
From the figure, let us change the
SET
v
associated with the top op amp. Change in this
voltage would cause a change in
I
v
at the input of the DUT.
Let, for
1 SET
v
V
out
I
A
v
v
1
1
And, for 2 SET
v
V
out
I
A
v
v
2
2
or,
( )
( )
( )
( )
os
out
os os
out out
I I
out out
V
v
v
v v
v v
v v
v v
A
∆
∆
−
−
−
−
1000 1000
2 1
2 1
2 1
2 1
Thus, by measuring the values of out
v ∆
and os
v ∆
while changing SET
v
can help in
finding the value of the openloop gain.
Problem 6.604
A circuit is shown which is used to
measure the CMRR and PSRR of an
op amp. Prove that the CMRR can be
given as
CMRR =
1000 v
icm
v
os
Solution
The definition of the commonmode
rejection ratio is
CMRR =
¹
¹
¹
¹
¹
¹
A
vd
A
cm
=
v
out
v
id
v
out
v
icm
However, in the above circuit the value of v
out
is the same so that we get
CMRR =
v
icm
v
id
But v
id
= v
i
and v
os
≈ 1000v
i
= 1000v
id
⇒ v
id
=
v
os
1000
Substituting in the previous expression gives, CMRR =
v
icm
v
os
1000
=
1000 v
icm
v
os
v
os
v
OUT
V
DD
V
SS
R
L
C
L
+

+

100kΩ
100kΩ
10kΩ
10Ω
v
icm
v
i
S99FEP7
v
icm
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 657
Problem 6.605
Sketch a circuit configuration suitable for simulating the following op amp characteristics:
(a) slew rate, (b) transient response, (c) input CMR, (d) output voltage swing. Repeat for
the measurement of the above op amp characteristics. What changes are made and why?
Solution
V
in
V
out
R
L C
L
V
DD
V
SS
V
in
V
out
R
L C
L
V
DD
V
SS
Slew rate, Transient response, and ICMR measurements
Output voltage swing measurement
The measurement of ICMR, Slew rate, and largesignal transient response can be
measured using the buffer configuration as shown in the figure. The input applied is a rail
torail step signal, which can be used to measure the maximum and minimum input swing,
the slew rate, rise and settling time. The same configuration can be used to measure the
performance in simulation. This buffer configuration can also be used to measure the small
signal transient performance. The applied input should be a small signal applied over the
nominal input commonmode bias voltage, and it can be used to measure the overshoot.
The maximum and minimum output voltage swing can be measured using the openloop
configuration of the op amp as shown in the figure. The input applied is a railtorail step
signal, which will overdrive the output to its maximum and minimum swing voltage levels.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 658
Problem 6.606
Using two identical op amps, show how to use SPICE in order to obtain a voltage which is
proportional to CMRR rather than the inverse relationship given in Sec. 6.6.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 659
Problem 6.607
Repeat the above problem for PSRR.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 660
Problem 6.608
Use SPICE to simulate the op amp of Example 6.52. The differentialfrequency response,
power dissipation, phase margin, commonmode input range, outputvoltage range, slew
rate, and settling time are to be simulated with a load capacitance of 20 pF. Use the model
parameters of Table 3.12.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 661
Problem 6.609
Use SPICE to simulate the op amp of Example 6.53. The differential frequency response,
power dissipation, phase margin, input commonmode range, outputvoltage range, slew
rate, and settling time are to be simulated with a load capacitance of 20pF. Use the model
parameters of Table 3.12.
Solution

+
v
in
M1 M2
V
Bias
+

V
DD
R
1
M3
M4
M5
M6
M7
M8 M9
M10 M11
R
2
M14
M15
v
out
C
L
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
Figure 6.57 (b)
The following is the SPICE source file for figure 6.57.
* Problem 6.69 SPICE simulation
*
*Voltage gain and phase margin
*VDD 3 0 DC 2.5
*VSS 0 4 DC 2.5
*VIN 30 0 DC 0 AC 1.0
*EIN+ 1 0 30 0 1
*EIN 2 0 30 0 1
*Output voltage swing
*VDD 3 0 DC 2.5
*VSS 0 4 DC 2.5
*VIN+ 40 0 DC 0 AC 1.0
*VIN 2 0 0
*Reg1 40 1 10K
*Reg2 5 1 100K
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 662
Problem 6.609  Continued
*ICMR
*VDD 3 0 DC 2.5
*VSS 0 4 DC 2.5
*VIN+ 1 0 DC 0 AC 1.0
*PSRR+
*VDD 3 0 DC 2.5 AC 1.0
*VSS 0 4 DC 2.5
*PSRR
VDD 3 0 DC 2.5
VSS 0 4 DC 2.5 AC 1.0
VIN+ 1 0 DC 0
*Slew Rate
*VDD 3 0 DC 2.5
*VSS 0 4 DC 2.5
*VIN+ 1 0 PWL(0 1 10N 1 20N 1 2U 1 2.0001U 1 4U 1 4.0001U 1 6U 1 6.0001u
+ 1 8U 1 8.0001U 1 10U 1)
*General
*X1 1 2 3 4 5 OPAMP
*Unity gain configuration
X1 1 5 3 4 5 OPAMP
.SUBCKT OPAMP 1 2 3 4 5
M1 8 1 6 4 NPN W=35.9u L=1u
M2 9 2 6 4 NPN W=35.9u L=1u
M3 6 7 4 4 NPN W=20u L=1u
M4 8 11 3 3 PNP W=80u L=1u
M5 9 11 3 3 PNP W=80u L=1u
M6 13 12 8 8 PNP W=80u L=1u
M7 5 12 9 9 PNP W=80u L=1u
M8 14 13 15 4 NPN W=36.36u L=1u
M9 5 13 16 4 NPN W=36.36u L=1u
M10 15 14 4 4 NPN W=36.36u L=1u
M11 16 14 4 4 NPN W=36.36u L=1u
M12 12 7 4 4 NPN W=25u L=1u
M13 11 12 10 10 PNP W=80u L=1u
M14 10 11 3 3 PNP W=80u L=1u
R1 11 12 2K
R2 13 14 2K
VBIAS 0 7 1.29
.MODEL NPN NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL PNP PMOS VTO=0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.ENDS
*Load cap
CL 5 0 20PF
.OP
.OPTION GMIN=1e6
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 663
Problem 6.609  Continued
.DC VIN+ 2.5 2.5 0.1
.PRINT DC V(5)
.TRAN 0.05u 10u
.PRINT TRAN V(5) V(1)
.AC DEC 10 1 100MEG
.PRINT AC VDB(5) VP(5)
.PROBE
.END
The simulation results are shown.
Result 1. Voltage gain and phase margin
Result 2. Output voltage swing range
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 664
Problem 6.609  Continued
Result 3. Input commonmode range
Result 4. Positive power supply rejection ratio
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 665
Problem 6.609  Continued
Result 5. Negative power supply rejection ratio
Result 6. Slew rate
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 666
Problem 6.609  Continued
Result 7. Settling time
From the output file of the SPICE simulation, total power dissipation is 6mW. The
following is a part of the output file.
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) 1.0000 ( 3) 2.5000 ( 4) 2.5000 ( 5) 1.0004
( X1.6) 2.0477 ( X1.7) 1.2900 ( X1.8) 1.5876 ( X1.9) 1.5874
(X1.10) 1.7094 (X1.11) 1.3594 (X1.12) .5508 (X1.13) .9291
(X1.14) 1.4451 (X1.15) 2.0731 (X1.16) 2.0706
VOLTAGE SOURCE CURRENTS
NAME CURRENT
VDD 1.218E03
VSS 1.218E03
VIN+ 0.000E+00
X1.VBIAS 0.000E+00
TOTAL POWER DISSIPATION 6.09E03 WATTS
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 667
Problem 6.610
A possible scheme for simulating the CMRR
of an op amp is shown. Find the value of
V
ou
t/V
in
and show that it is approximately
equal to 1/CMRR. What problems might
result in the actual implementation of this
circuit to measure CMRR?
Solution
The model for this circuit is shown. We can
write that
V
out
= A
vd
(V
1
V
2
) + A
cm
V
cm
= A
vd
V
out
+ A
cm
V
cm
Thus,
V
out
(1+A
vd
) = A
cm
V
cm
or
V
out
V
cm
=
A
cm
1+A
vd
≈
A
cm
A
vd
=
1
CMRR
The potential problem with this method is that PSRR
+
is not equal to PSRR

. This can be
seen by moving the V
cm
through the power supplies so it appears as power supply ripple
as shown below. This method depends on the fact that the positive and negative power
supply ripple will cancel each other.
v
out
V
DD
V
SS
V
1
V
2
S02E2S4B
V
cm
V
cm
+

v
out
V
DD
V
SS
+

V
1
V
2
V
cm
S02E2P4
V
out
V
1
V
2
A
vd
(V
1
V
2
)
A
cm
V
cm
S02E2S4A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 668
Problem 6.611
Explain why the positive overshoot of the simulated positive step response of the op amp
shown in Fig. 6.620(b) is smaller than the negative overshoot for the negative step
response. Use the op amp values given in Ex. 6.31 and the information given in Tables
6.61 and 6.63.
Solution
Consider the following circuit and waveform:
M6
M7
v
out
V
DD
= 2.5V
V
SS
= 2.5V
C
c
C
L
V
Bias
95µA
94/1
i
6
i
CL
0.1V
0.1V
0.1µs 0.1µs
t
Fig. 6.622
i
Cc
During the rise time, i
CL
= C
L
(dv
out
/dt )= 10pF(0.2V/0.1µs) = 20µA and i
Cc
= 3pf(2V/µs)
= 6µA
∴ i
6
= 95µA + 20µA + 6µA = 121µA ⇒ g
m6
= 1066µS (nominal was 942.5µS)
During the fall time, i
CL
= C
L
(dv
out
/dt )= 10pF(0.2V/0.1µs) = 20µA
and i
Cc
= 3pf(2V/µs) = 6µA
∴ i
6
= 95µA  20µA  6µA = 69µA ⇒ g
m6
= 805µS
The dominant pole is p
1
≈ (R
I
g
m6
R
II
C
c
)
1
where R
I
= 0.694MΩ, R
II
= 122.5kΩ
and C
c
= 3pF.
∴ p
1
(95µA) = 4,160 rads/sec, p
1
(121µA) = 3,678 rads/sec, and p
1
(69µA) = 4,870 rads/sec.
Thus, the phase margin is less during the fall time than the rise time.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 669
Problem 6.701
Develop a macromodel for the op amp of Fig. 6.12 which models the low frequency gain
A
v
(0), the unitygain bandwidth GB, the output resistance R
out
, and the outputvoltage
swing limits V
OH
and V
OL
. Your macromodel should be compatible with SPICE and
should contain only resistors, capacitors, controlled sources, independent sources, and
diodes.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 670
Problem 6.702
Develop a macromodel for the op amp of Fig. 6.12 that models the lowfrequency gain
A
v
(0), the unitygain bandwidth GB, the output resistance R
out
, and the slew rate SR.
Your macromodel should be compatible with SPICE and should contain only resistors,
capacitors, controlled sources, independent sources, and diodes.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 671
Problem 6.703
Develop a macromodel for the op amp shown in Fig. P6.73 that has the following
properties:
a.) A
vd
(s) =
A
vd
(0)
.

}
`
s
z
1
 1
.

}
`
s
p
1
+ 1
.

}
`
s
p
2
+ 1
where A
vd
(0) = 10
4
,z
1
= 10
6
rads/sec., p
1
= 10
2
rads/sec, and p
2
= 10
7
rads/sec.
b.) R
id
= 1MΩ.
c.) R
o
= 100Ω.
d.) CMRR(0) = 80dB.
Show a schematic diagram of your macromodel and identify the elements that define the
model parameters A
vd
(0), z
1
, p
1
, p
2
, R
id
, R
o
, and CMRR(0). Your macromodel should
have a minimum number of nodes.
Solution
The following macromodel is used to solve this problem.
1
R
1
(V
1
V
2
)
R
1
R
1
C
1
2R
o
V
1
2
0.5R
id
0.5R
id
A
vd
(0)
4
R
2
(V
1
V
2)
R
2
C
2
kA
vd
(0)
5
V
4
3
R
o
V
5
2R
o
V
2
R
o
Fig. S6.703
Verifying the macromodel by solving for V
3
gives,
V
3
= V
5
+ 0.5(V
1
+V
2
) =
.

}
`
R
2
sR
2
C
2
+1
]
]
V
4
R
2

kA
vd
(0)
R
2
(V
1
V
2
) + V
icm
=
.

}
`
A
vd
(0)
sR
2
C
2
+1
]
]
V
id
sR
1
C
1
+1
 kV
i d
+ V
icm
=
A
vd
(0)
( sR
1
C
1
+1)(sR
2
C
2
+1)
(1ksR
1
C
1
k)V
id
+
V
icm
Choose R
1
= 10kΩ → C
1
=1µF, R
2
= 1Ω → C
1
=0.1µF, R
o
= 100Ω, and R
id
= 1MΩ and
solve for k. (note that the polarity of k was defined in the above macromodel to make k
positive).
1ksR
1
C
1
k = 0 → z =
1
R
1
C
1.

}
`
1
k
 1 → 10
6
= 10
2
(
1
k
1) → k ≈10
4
With these choices, the transconductance values of all controlled sources are unity except
for the ones connected to the output node, node 3.
+

1
2
3
i
O
v
O
Figure P6.73
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 672
Problem 6.704
Develop a macromodel suitable for SPICE of a differential, current amplifier of Fig. P6.74
having the following specifications:
i
OUT
= A
i
(s)[i
1
 i
2
]
where
A
i
(s) =
GB
s+ωωω ω
a
=
10
6
s+100
R
in1
= R
in2
= 10Ω
R
out
= 100kΩ
and
Maxdi
OUT
/dt = 10A/µs.
Your macromodel may use only passive components, dependent and independent sources,
and diodes (i.e., no switches). Give a schematic for your macromodel and relate each
component to the parameters of the macromodel. (The parameters are in bold.) Minimize
the number of nodes where possible.
Solution
A realization is shown below along with the pertinent relationships.
1 4
V
I1
=0V
2 5
V
I2
=0V
R
in1
=10Ω
i
1
R
in2
=10Ω
i
2
10
4
R
1
I
VI1
10
4
R
1
I
VI2
R
1
6 7
C
1
D1
D2
8
9
D1
D2
I
SR
R
o
V
6,7
3
R
o
=
100kΩ
Fig. S6.704
i
OUT
i
C1
=
dv
6,7
dt
C
1
→ I
SR
= 10
7
C
1
Choose C
1
= 0.1µF ⇒ I
S R
= 1A
Therefore,
1
R
1
C
1
= 100 → R
1
=
1
100·C
1
=
10
7
10
2
= 100kΩ → R
1
= 100k Ω
Note that the voltage rate limit becomes a current rate limit because i
OUT
= v
6,7
Current
Amplifier
i
1
i
2
i
OUT
R
in1
R
in2
R
out
Figure P6.74
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 71
CHAPTER 7 – HOMEWORK SOLUTIONS
Problem 7.101
Assume that V
DD
= V
SS
and I
17
and I
20
in Fig. 7.12 are 100µA. Design W
18
/L
18
and
W
19
/L
19
to get V
SG18
= V
GS19
= 1.5V. Design W
21
/L
21
and W
22
/L
22
so that the
quiescent current in M21 and M22 is also 100µA.
Solution
Assuming
5 . 2 −
SS DD
V V
V, and
0
o
V
V
Due to bulk effects,
( ) φ φ γ 2 2
0
− + +
SB T T
V V V
Thus,
89 . 0
19
T
V
V, and
95 . 0
18
T
V
V
Now,
( )
18
’
18
18 18
2
L W K
I
V V
P
T SG
+
or,
5 . 13
18
}
`
.

L
W
And,
( )
19
’
19
19 19
2
L W K
I
V V
N
T SG
+
or,
9 . 4
19
}
`
.

L
W
Since
0
o
V
V,
08 . 1
21
T
V
V, and
23 . 1
22
T
V
V
( )
21
’
21
21 21
2
L W K
I
V V
N
T SG
+
or,
3 . 10
21
}
`
.

L
W
And,
( )
22
’
22
22 22
2
L W K
I
V V
P
T SG
+
or,
55
22
}
`
.

L
W
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 72
Problem 7.102
Calculate the value of V
A
and V
B
in Fig. 7.12 and therefore the value of V
C
.
Solution
The first trip point
A
V
is defined as the input for which
5
M
trips (or turns on). If it is
assumed that the smallsignal gain of the inverters (
3 1
M M −
and
4 2
M M −
) is large, then
it can be assumed that
5
M
will trip when
3 1
M M −
are in saturation.
Thus,
( )
3 3
1
3
1 1 T SG T GS A
V V V V V − +
β
β
→ V
A
= 0.9 V
Similarly, it can be assumed that 6
M
will trip when 4 2
M M −
are in saturation.
Thus,
( )
4 4
2
4
2 2 T SG T GS B
V V V V V − +
β
β
or, V
A
= 1.0 V
So, V V V
C B A
− = 0.1V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 73
Problem 7.103
Assume that K'
N
47 µA/V
2
, K'
P
17 µA/V
2
, V
TN
0.7 V, V
TP
−0.9 V, γ
N
0.85
V
1/2
, γ
P
0.25 V
1/2
, 2φ
F
 0.62 V, λ
N
0.05 V
1
, and λ
P
0.04 V
1
. Use SPICE to
simulate Fig. 7.12 and obtain the simulated equivalent of Fig. 7.13.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 74
Problem 7.104
Use SPICE to plot the total harmonic distortion (THD) of the output stage of Fig. 7.15 as
a function of the RMS output voltage at 1 kHz for an inputstage bias current of 20 µA.
Use the SPICE model parameters given in the previous problem.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 75
Problem 7.105
An MOS output stage is shown in Fig. P7.15. Draw a
smallsignal model and calculate the ac voltage gain at low
frequency. Assume that bulk effects can be neglected.
Solution
Referring to the figure
out gs
v v
2
, and
in gs
v v
1
Applying nodal analysis
( ) 0
2 1 4 1 2
+ + +
out m in m gs ds ds
v g v g v g g
(1)
And,
( ) 0
4 3 4 4
+ +
out ds m gs m
v g g v g
(2)
From Equations (1) and (2)
( )( ) ( )
2 1 4 3 4 2
4 1
ds ds ds m m m
m m
in
out
g g g g g g
g g
v
v
+ + −
−
v
gs1
=v
in
+

g
m1
v
gs1
r
ds1
r
ds2 g
m2
v
gs2
1/g
m3
r
ds4
+

v
gs4
g
m4
v
gs4
+

v
out
= v
gs4
Fig. S7.105A
Problem 7.106
Find the value of the smallsignal output resistance of Fig. 7.19 if the W values of M1 and
M2 are increased from 10µm to 10µm. Use the model parameters of Table 3.12. What is
the 3dB frequency of this buffer if C
L
= 10pF?
Solution
The loopgain of the negative feedback loop is given by
( )
( )
7 6 4
8 6 2
2
ds ds m
m m m
g g g
g g g
LG
+
+
−
or,
164 − LG
The output resistance can be expressed as
( )
LG
g g
R
ds ds
out
−
+
−
1
1
7 6
or,
3 . 67
out
R
Ω
The –3 dB frequency point is
L out
dB
C R
f
π 2
1
3
−
or, f
3dB
= 236 MHz
v
in
M1
M2
M5
M6
v
out
V
DD
V
SS
Figure P7.15
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 76
Problem 7.107
A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small
signal output resistance, R
out
, and from this value estimate the 3dB bandwidth if a 50pF
capacitor is attached to the output. What is the maximum and minimum output voltage if a
1kΩ resistor is attached to the output? What is the quiescent power dissipation of this
circuit? Use the following model parameters: K
N
’=110µA/V
2
, K
P
’ = 50µA/V
2
, V
TN
=
V
TP
= 0.7V, λ
N
= 0.04V
1
and λ
P
= 0.05V
1
.
Solution
Use feedback concepts to calculate the output resistance, R
out
.
R
out
=
R
o
1LG
where R
o
is the output resistance with the feedback open and LG is the loop gain.
R
o
=
1
g
ds6
+g
ds7
=
1
(λ
N
+λ
P
)I
6
=
10
6
0.09·500
= 22.22kΩ
The loop gain is,
LG =
v
out
’
v
out
= 
1
2
]
]
g
m2
g
m6
g
m4
+
g
m1
g
m9
g
m7
R
o
g
m1
= g
m2
= 2·110·50·10 = 331.67µS, g
m3
= g
m4
= 2·50·50·10 = 223.6µS,
g
m6
= 2·50·100·500 = 2236µS and g
m7
= 2·110·500·100 = 3316.7µS
∴ LG =
v
out
’
v
out
= 
1
2
]
]
331.67·2236
223.6
+
331.67·3316.7
331.67
= 73.68V/V
R
out
=
R
o
1LG
=
22.22kΩ
1+73.68
= 294.5 Ω
f
3dB
=
1
2π·R
out
·50pF
=
1
2π·294.5·50pF
= 10.81MHz
To get the maximum swing, we must check two limits. First, the saturation voltages of M6
and M7.
V
ds6
(sat) =
2·1000
50·100
= 0.6325V and V
ds7
(sat) =
2·1000
110·100
= 0.4264V
Second, the maximum current available to the 1kΩ resistor is ±1mA which means that the
output swing can only be ±1V. Therefore, maximum/minimum output = ±1V .
P
diss
= 6V(650µA) = 3.9mW
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 77
Problem 7.108
What type of BJT is available with a bulk CMOS pwell technology? A bulk CMOS nwell
technology?
Solution
In a bulk CMOS pwell technology, npn BJTs (both substrate and lateral) are available.
In a bulk CMOS nwell technology, pnp BJTs (both substrate and lateral) are available.
Problem 7.109
Assume that Q10 of Fig. 7.111 is connected directly to the drains of M6 and M7 and that
M8 and M9 are not present. Give an expression for the smallsignal output resistance and
compare this with Eq. (9). If the current in Q10M11 is 500µA, the current in M6 and M7
is 100µA, and ß
F
= 100, use the parameters of Table 3.12 assuming 1µm channel lengths
and calculate this resistance at room temperature.
Solution
M7
M6
Q10
M11
C
c
R
L
C
L
Vdd
Vss
V
out
The output resistance is
( )( )
7 6 10
1
1 1
ds ds F m
out
g g g
R
+ +
+ ≅
β
From Equation (7.19)
( )
9 10
1
1 1
m F m
out
g g
R
β +
+ ≅
Here,
23 . 19
10
m
g
µS and
9
7 6
+
ds ds
g g
S µ
Thus, R
out
= 1152 Ω
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 78
Problem 7.110
Find the dominant roots of the MOS follower and the BJT follower for the buffered, class
A op amp of Ex. 7.12. Use the capacitances of Table 3.21. Compare these root
locations with the fact that GB = 5MHz? Assume the capacitances of the BJT are C
π
=
10pf and C
µ
= 1pF.
Solution
The model of just the output buffer of Ex. 7.12 is shown.
v
i
v
o
V
DD
V
SS
M8
Q10
M9
M11
C
L
R
L
g
m9
(V
i
V
1
)
R
1
C
1
g
m10
(V
1
V
o
)
R
2
C
2
C
π
r
π
V
1 V
o
R
1
= r
ds8
r
ds9 R
2
= r
ds11
r
o10
R
L
C
1
= C
gd8
+C
bd8
+C
gs9
+C
bs9
+C
µ10
C
2
= C
L
Fig. S7.110
90µA
10µA
100µA
146/1
10/1
1467/1
1000µA
100pF
500Ω
The nodal equations can be written as,
g
m9
V
i
= (g
m9
+ G
1
+ g
π10
+ sC
π10
+ sC
1
)V
1
– (g
π10
+ sC
π10
)V
o
0 = –( g
m10
+ g
π10
+ sC
π10
)V
1
+ (g
m10
+ G
2
+ g
π10
+ sC
π10
+ sC
2
)V
o
Solving for V
o
/V
i
gives,
V
o
V
i
=
g
m9
(g
m10
+ g
π10
+ sC
π10
)
(g
π10
+ sC
π10
)(g
m9
+ G
1
+ G
2
+ sC
1
+ sC
2
) + (g
m10
+ G
2
+ sC
2
)(g
m9
+ G
1
+ sC
1
)
V
o
V
i
=
g
m9
(g
m10
+ g
π10
+ sC
π10
)
a
0
+ sa
1
+ s
2
a
2
where
a
0
= g
m9
g
π10
+ g
π10
G
1
+ g
πππ π111 1000 0
G
2
+ g
m9
g
m111 1000 0
+ g
m10
G
1
+ g
m9
G
222 2
+ G
1
G
2
a
1
= g
m9
C
π10
+G
1
C
π10
+G
2
C
πππ π111 1000 0
+g
π10
C
1
+g
πππ π111 1000 0
C
2
+g
m10
C
1
+G
2
C
1
+g
m9
C
222 2
+G
1
C
2
a
2
= C
π10
C
1
+ C
πππ π111 1000 0
C
2
+ C
1
C
2
The numerical value of the small signal parameters are:
g
m10
=
1mA
25.9mV
= 38.6mS, G
2
= 2mS, g
π10
= 386µS, g
m9
= 2·50·10·90 =
300µS, G
1
= g
ds8
+ g
ds9
= 0.05·100µA + 0.05·90µA = 9.5µS
C
2
= 100pF, C
π10
= 10pF, C
1
= C
gs9
+ C
bs9
+ C
bd8
+ C
gd8
+ C
µ10
C
gs9
= C
ov
+0.667C
ox
W
9
L
9
= (220x10
12
)(10x10
6
)
+0.667(24.7x10
4
)(10x10
12
) = 18.7fF
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 79
Problem 7.110 – Continued
C
bs9
= 560x10
6
(30x10
12
)+350x10
12
(26x10
6
) = 25.9fF
(Assumed area=3µmx10µm = 30µm and perimeter is 3µm+10µm+3µm+10µm = 26µm)
C
bd8
= 560x10
6
(438x10
12
)+350x10
12
(298x10
6
) = 349fF
C
gd8
= C
ov
= (220x10
12
)(146x10
6
) = 32.1fF
∴ C
1
= 18.7fF + 25.9fF + 349fF + 32.1fF + 1000fF = 1.43pF
(We have ignored any reverse bias influence on pn junction capacitors.)
The dominant terms of a
0 ,
a
1
, and a
2
based on these values are shown in boldface above.
∴
V
o
V
i
≈
g
m9
(g
m10
+ g
π10
+ sC
π10
)
g
m9
g
m10
+ g
π10
G
2
+s(G
2
C
π10
+g
π10
C
2
+g
m10
C
1
+g
m9
C
2
)+s
2
C
2
C
π10
V
o
V
i
=
g
m9
g
m10
g
m9
g
m10
+ g
π10
G
2
]
]
]
] 1 +
sC
π1 0
g
m10
1 + s
.

}
`
G
2
C
π10
+g
π10
C
2
+g
m10
C
1
+g
m9
C
2
g
m9
g
m10
+ g
π10
G
2
+ s
2
C
2
C
π10
g
m9
g
m10
+ g
π10
G
2
Assuming negative real axis roots widely spaced gives,
p
1
= 
1
a
=
(g
m9
g
m10
+ g
π10
G
2
)
G
2
C
π10
+g
π10
C
2
+g
m10
C
1
+g
m9
C
2
= 
1.235x10
5
1.465 x10
13
= 84.3 x10
6
rads/sec.
13.4MHz
p
2
= 
a
b
=
(G
2
C
π10
+g
π10
C
2
+g
m10
C
1
+g
m9
C
2
)
C
2
C
π10
= 
1.465 x10
13
100x10
12
·10x10
12
= 146.5 x10
6
rads/sec. → 23.32MHz
z
1
= 
g
m10
C
π10
= 
38.6x10
3
10 x10
12
= 3.86 x10
9
rads/sec. → 614MHz
We see that neither p
1
or p
2
is greater than 10GB if GB = 5MHz so they will deteriorate the
phase margin of the amplifier of Ex. 7.12.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 710
Problem 7.111
Given the op
amp in Fig. P7.1
11, find the
quiescent currents
flowing in the op
amp, the small
signal voltage
gain, ignoring any
loading produced
by the output
stage and the
smallsignal
output resistance.
Assume K'
N
25
µA/V
2
and K'
P
10 µA/V
2
and λ
0.04 V
1
for both
types of MOSFETs. Assume the the BJT has a current gain of β
F
= 100.
Solution
The quiescent currents flowing in the op amp are shown on the above schematic.
The smallsignal model parameters for the MOSFETs are:
g
m1
= g
m2
= 2·25·4·60 = 109.5µS and g
m6
= 2·10·7·40 = 74.8µS
r
ds2
= r
ds4
=
25x10
6
60
= 0.4167MΩ, r
ds6
= r
ds7
=
25x10
6
40
= 0.625MΩ
and r
ds9
=
25x10
6
200
= 0.125MΩ For the two BJT’s, g
m1
=
2x10
6
26x10
3
= 7.7µS,
r
π1
=
101
7.7µS
= 1.308MΩ, g
m2
=
200x10
6
26x10
3
= 7.7mS and r
π2
=
101
7.7mS
= 13.08kΩ
The smallsignal voltage gain is A
v
= g
m1
R
I
g
m6
R
II
A
buff
where
R
I
= 0.4167MΩ0.4167MΩ 0.2083ΜΩ and R
II
= 0.625MΩ0.615MΩ = 0.3125MΩ.
A
buff
=
(1+β
F
)
2
r
ds9
r
π1
+(1+β
F
)[r
π2
+(1+β
F
)r
ds9
]
=
101
2
0.125MΩ
1.3MΩ+101[13.08kΩ+101·0.125MΩ]
= 0.998
∴ A
v
= 109.5µS·0.2083MΩ·74.8µS·0.3125MΩ·0.998 = 532.2V/V
R
out
= r
ds9

]
]
] (r
π1
+R
II
)/(1+β
F
)+r
π2
1+β
F
= 0.125MΩ
]
] (0.3125MΩ+1.208MΩ)/101+13.08kΩ
101
= 0.125MΩ288 = 287.4 Ω

+
v
in
M1
M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
20µA
8
2
8
2
10
2
10
2
14
2
4
2
12
2
2
2
M8
Q1
Q2
M9
20
2
All W/L values in microns
Figure P7.111  Solution
120µA
60µA
60µA
40µA
200µA
2µA
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 711
Problem 7.21
Find the GB of a twostage op amp using Miller compensation using a nulling resistor that
has 60° phase margin where the second pole is 10x10
6
rads/sec and two higher poles both
at 100x10
6
rads/sec. Assume that the RHP zero is used to cancel the second pole and that
the load capacitance stays constant. If the input transconductance is 500µA/V, what is the
value of C
c
?
Solution
The resulting higherorder poles are two at 100x10
6
radians/sec. The resulting phase
margin expression is,
PM = 180°  tan
1
(A
v
(0))  2tan
1
.

}
`
GB
10
7
= 90°  2tan
1
.

}
`
GB
10
7
= 60°
∴ 30° = 2tan
1
.

}
`
GB
10
7
→
.

}
`
GB
10
7
= tan(15°) = 0.2679
GB = 2.679x10
7
=
g
m1
C
c
→ C
c
=
500x10
6
26.79x10
7
= 18.66pF
Problem 7.202
For an op amp where the second pole is smaller than any larger poles by a factor of 10, we
can set the second pole at 2.2GB to get 60° phase margin. Use the pole locations
determined in Example 7.22 and find the constant multiplying GB if p
6
for 60° phase
margin.
Solution
Referring to Example (7.22)
966 . 0
6
− p
Grad/sec
346 . 1 −
A
p
Grad/sec
346 . 1 −
B
p
Grad/sec
149 . 3
8
− p
Grad/sec
149 . 3
9
− p
Grad/sec
5 . 3
10
− p
Grad/sec
For a phase margin of
o
60
, the contributions due to all the poles on the phase margin can
be given as
o
30 tan tan 2 tan 2 tan
10
1
8
1 1
6
1
}
`
.

+
}
`
.

+
}
`
.

+
}
`
.

− − − −
p
GB
p
GB
p
GB
p
GB
A
Solving for the value of gainbandwidth, we get
35 23 . 0
6
≅ p GB
MHz.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 712
Problem 7.203
What will be the phase margin of Ex. 7.22 if C
L
= 10pF?
Solution
The value of the output resistance from Example (7.22) is
4 . 19
out
R
Ω M
Thus, the dominant pole is
2 . 8
1
1
−
L out
C R
p
KHz.
The gainbandwidth is given by
61 ) 2 . 8 )( 7464 ( ) 0 (
1
K p A GB
v MHz.
Considering the location of the various poles from Example (7.22), the phase margin
becomes
]
]
]
]
¹
¹
¹
`
¹
¹
¹
¹
´
¹
}
`
.

+
}
`
.

+
}
`
.

+
}
`
.

− −
− − − −
10
1
8
1 1
6
1
tan tan 2 tan 2 tan 90 180
p
GB
p
GB
p
GB
p
GB
PM
A
o o
or,
{ ¦ [ ]
o o o o o o
2 . 6 14 32 7 . 21 90 180 + + + − − PM
or,
o
16 PM
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 713
Problem 7.204
Use the technique of Ex. 7.22 to extend the GB of the cascode op amp of Ex. 6.52 as
much as possible that will maintain 60° phase margin. What is the minimum value of C
L
for the maximum GB?
Solution
Assuming all channel lengths to be 1
m µ
, the total capacitance at the source of M7 is
6 6 7 7 7 bd gd bd gs
C C C C C + + +
→
186 51 9 51 75
7
+ + + C
fF
707
7
m
g
S µ
Thus, the pole at the source of M7 is
605
7
7
7
− −
C
g
p
m
S MHz.
The total capacitance at the source of M12 is
11 11 12 12 12 bd gd bd gs
C C C C C + + +
→
96 29 4 29 34
12
+ + + C
fF
707
12
m
g
S µ
Thus, the pole at the source of M12 is
1170
12
12
12
− −
C
g
p
m
S MHz.
The total capacitance at the drain of M4 is
2 2 4 6 4 4 bd gd bd gs gs
C C C C C C + + + +
→
161 19 3 21 75 43
4
+ + + + C
fF
283
4
m
g
S µ
Thus, the pole at the drain of M4 is
280
4
4
4
− −
C
g
p
m
D MHz.
The total capacitance at the drain of M8 is
12 10 8 8 8 gs gs bd gd
C C C C C + + +
→
128 34 34 51 9
8
+ + + C
fF
4 . 3
1
10
2
+
m
g
R
Ω K
Thus, the pole at the drain of M8 is
366
1
1
8
10
2
8
−
}
`
.

+
−
C
g
R
p
m
D
MHz.
For a phase margin of
o
60
, we have
]
]
]
]
¹
¹
¹
`
¹
¹
¹
¹
´
¹
}
`
.

+
}
`
.

+
}
`
.

+
}
`
.

− −
− − − −
8
1
4
1
12
1
7
1
tan tan tan tan 90 180
D D S S
p
GB
p
GB
p
GB
p
GB
PM
o o
Solving the above equation
65 ≅ GB
MHz and
6925
v
A
V/V
Thus,
39 . 9
1
p
KHz, and C
L
≥ 1.54 pF
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 714
Problem 7.205
For the voltage amplifier using a current mirror shown in Fig. 7.211, design the currents
in M1, M2, M5 and M6 and the W/L ratios to give an output resistance which is at least
1MΩ and an input resistance which is less than 1kΩ. (This would allow a voltage gain of 
10 to be achieved using R
1
= 10kΩ and R
2
= 1MΩ.
Solution
( )
2 6
1
ds ds
out
g g
R
+
Let,
10
6 2
I I
A µ
or,
( )
1 . 1
1
2 6
+
ds ds
out
g g
R
Ω M
Given,
10
1
R
Ω K
,
1000
2
R
Ω K
, and
10 −
v
A
And,
( )
0 1
0 2
1 A R
A R
A
v
+
−
Thus,
9
1
1
2
0
I
I
A
or,
10
6 2
I I
A µ
and
90
5 1
I I
A µ
1
1
1
m
in
g
R
Ω K
or,
5 . 50
1
}
`
.

L
W
, and
6 . 5
2
}
`
.

L
W
and,
5 . 50
5
}
`
.

L
W
, and
6 . 5
6
}
`
.

L
W
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 715
Problem 7.206
In Ex. 7.23, calculate the value of the input pole of the current amplifier and compare with
the magnitude of the output pole.
Solution
Assuming all channel lengths to be 1
m µ
.
In this problem,
1 . 0
0
A
,
20
2
S
,
200
1
S
,
100
2
I
A µ
, and
1000
1
I
A µ
63 . 6
1
m
g
mS
Thus,
451
1
1
3
+
m
in
g
R R
Ω
The input capacitance is
4 3 4 3 5 5 gd gd gs gs bd gd in
C C C C C C C + + + + +
or,
758 4 . 4 44 38 375 253 44 + + + + +
in
C
fF
The input pole is given by
466
1
− −
in in
in
C R
p
MHz which is compared to 50 MHz for the output pole.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 716
Problem 7.207
Add a second input to the voltage amplifier of Fig. 7.212 using another R
1
resistor
connected from this input to the input of the current amplifier. Using the configuration of
Fig. P7.27, calculate the input resistance, output resistance, and 3dB frequency of this
circuit. Assume the values for Fig. 7.212 as developed in Ex. 7.23 but let the twoR
1
resistors each be 1000Ω.
Solution
R
1
R
1
R
1
(A
v
1)/A
v
R
1
R
1
/(1A
v
)
V
in
V
in
V
out
V
out
A
v
A
v
Referring to the figure, the Miller resistance, 1
R
, between the input and the output can be
broken as shown.
Here,
1
1
R
Ω K
,
110
2
R
Ω K
, and
3 . 0
3
R
Ω K
The input resistance can be written as
]
]
]
]
}
`
.

+
]
]
]
−
+
1
3
1
1
1

1
m v
in
g
R
A
R
R R
→ ]
]
]
}
`
.

+
]
]
]
+
+
m
K
K R
in
63 . 6
1
300 
10 1
1
1
or, R
in
= 1076 Ω
The output resistance can be written as
( )
v
v
m
out
A
A R
g
R
1

1
1
12
−
→ R
out
= 636 Ω
The –3 dB frequency, the pole created at the drains of M4 and M6, is given by
f
R C
o
dB −
3
2
1
2π
where,
110
2
R
Ω K
, and
105
o
C
pF.
So, f
3dB
= 13.87 MHz .
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 717
Problem 7.208
Replace R
1
in Fig. 7.212 with a differential amplifier using a current mirror load. Design
the differential transconductance, g
m
, so that it is equal to 1/R
1
.
Solution
M
14
M
3
M
1
M
5
M
7
M
16
M
15
M
13
M
17
V
BIAS
V
SS
V
in
R
3
i
1 R
2
V
dd
Referring to the figure, the output current of the input transconductor, 1
i
, is given by
in m
v g i
13 1
Comparing with the expression
1
1
R
v
i
in
, we get
13
1
1
m
g
R
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 718
Problem 7.301
Compare the differential output op amps of Fig. 7.33, 7.35, 7.36, 7.37, 7.38 and 7.3
10 from the viewpoint of (a.) noise, (b.) PSRR, (c.) ICMR [V
ic
(max) and V
ic
(min)], (d.)
OCMR [V
o
)max) and V
o
(min)], (e.) SR assuming all input differential currents are
identical, and (f.) power dissipation if all current of the input differential amplifiers are
identical and power supplies are equal.
Solution
Assume that all differential amplifiers have the same bias current of I
SS
.
v
i1 M1 M2
M3 M4
M5
M6 M7
V
DD
V
SS
V
BN
+

C
c
M9
C
c
V
BP
+

v
i2
v
o1
v
o2
R
z
R
z
M8
Figure 7.33 Twostage, Miller, differentialin, differentialout op amp.
vi1
M1 M2
M3 M4
M5
M6
M7
VDD
VSS
VBN
+

Cc
M9
Cc
VBP
+

vi2
vo1 vo2
Rz Rz
M8
Figure 7.36 Twostage, Miller, differentialin, differentialout op amp
with a pushpull output stage.
M10 M12
M13
M14
V
DD
V
SS
V
Bias
R
2
M22
M23
R
1
M19
M20
M1 M2
M3 M4
M5 M6
M7 M8
M9 M10
M11
M12
M13
M14
M15 M16
M17
M18
M21
v
o1
v
i1 v
i2
v
o2
Figure 7.38 Unfolded cascode op amp with differentialoutputs.
V
DD
V
SS
R
1
M14
R
2
M8
M10
V
Bias
v
i1
v
i2 v
o1
v
o2
M1 M2
M3
M4 M5
M7 M6
M9
M11
M12
M13
M15
M16
M17
Figure 7.35 Differential output, foldedcascode op amp.
V
DD
V
SS
R1
M16
M8
M10
VBias
vi1 vi2
vo1
vo2 M1 M2
M3
M4 M5
M7
M6
M9
M11
M14 M15
M12 M13
Figure 7.37 Twostage, differential output, foldedcascode op amp.
Cc Rz Cc Rz
M17
M18
M19
M20
M1M2
M3 M4
M5 M6
M7
V
DD
V
SS
V
Bias
+

R1
M24
M25
R2
M27
M28
M8 M9 M10
M11 M12
M13
M14
M15
M16
M17 M18
M19 M20
M21 M22
M26
M23
vo2
vi2
vi1
vo1
Figure 7.310 Class AB, differential output op amp using a crosscoupled
differential input stage.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 719
Problem 7.301 – Continued
Fig. 7.33 Fig. 7.35 Fig. 7.36 Fig. 7.37 Fig. 7.38 Fig. 7.310
Noise Good Poor Good Poor Okay Poor
PSRR Poor Good Poor Good Good Good
ICMR
V
ic
(max)
V
ic
(min)
V
DD
V
ON
V
SS
+
2V
ON
+V
T
V
DD
+V
T
V
SS
+
2V
ON
+V
T
V
DD
V
ON
V
SS
+
2V
ON
+V
T
V
DD
+V
T
V
SS
+
2V
ON
+V
T
V
DD
V
ON
V
SS
+
2V
ON
+V
T
V
DD
V
ON
V
SS
+
3V
ON
+2V
T
OCMR
V
o
(max)
V
o
(min)
V
DD
V
ON
V
SS
+V
ON
V
DD
2V
ON
V
SS
+2V
ON
V
DD
V
ON
V
SS
+V
ON
V
DD
V
ON
V
SS
+V
ON
V
DD
2V
ON
V
SS
+2V
ON
V
DD
2V
ON
V
SS
+2V
ON
SR I
SS
/C
c
I
SS
/C
L
I
SS
/C
c
I
SS
/C
L
I
SS
/C
L
I
SS
/C
L
Problem 7.302
Prove that the load seen by the differential outputs of the op amps in Fig. 7.34 are
identical. What would be the singleended equivalent loads if C
L
was replaced with a
resistor, R
L
?
Solution
+

+

+

+

+

v
in
v
in
v
in
v
in
v
in
C
L
2C
L
2C
L
2C
L
2C
L
v
od
v
od
R
L
R
L
/2
R
L
/2
v
od
v
od
v
od
Referring to the figure, when a capacitive load of
L
C
is driven differentially, the load
capacitor can be broken into two capacitors in series, each with a magnitude of
L
C 2
. The
mid point of the connection of these two capacitors is ac ground as the output signal swings
differentially. In case of a resistive load
L
R
, it can be broken into two resistive loads in
series, each resistor being
2 /
L
R
.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 720
Problem 7.303
Two differential output op amps are shown in Fig. P7.33. (a.) Show how to compensate
these op amps. (b.) If all dc currents through all transistors is 50µA and all W/L values
are 10µm/1µm, use the parameters of Table 3.12 and find the differentialin, differential
out smallsignal voltage gain.

+
v
in
M1
M2
M3 M4
M5
v
out
V
DD
V
SS
V
Bias
+

V
Bias
+

M6
M7
M8
M9
M10
+

V
DD
V
SS
V
Bias
+

V
Bias
+

v
out

v
in
+
v
in

v
out
+
(a.) (b.)
Fig. S7.33
R
z
R
z
C
c
C
c
R
z
C
c
R
z
C
c
Solution
a) The compensation of both the op amps are shown in the figure.
b) The smallsignal voltage gain of Figure P7.33(a) is given by
( )( )
9 6 3 1
6 1
ds ds ds ds
m m
v
g g g g
g g
A
+ +
or,
( )( )
( )( ) µ µ
µ µ
5 . 4 5 . 4
224 332
v
A
or, A
v
= 3673 V/V
The smallsignal voltage gain of Figure P7.33(b) is given by
( )
( )( )
9 6 3 1
9 6 1
ds ds ds ds
m m m
v
g g g g
g g g
A
+ +
+
or,
( )( )
( )( ) µ µ
µ µ
5 . 4 5 . 4
556 332
v
A
or, A
v
= 9117 V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 721
Problem 7.304
Comparatively evaluate the performance of the two differential output op amps of Fig.
P7.33 with the differential output op amps of Fig. 7.33, 7.35, 7.36, 7.37, 7.38 and
7.310. Include the differentialin, differentialout voltage gain, the noise, and the PSRR.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 722
Problem 7.305
Fig. P7.35 shows a differentialin, differentialout op amp. Develop an expression for the
smallsignal, differentialin, differentialout voltage gain and the smallsignal output
resistance.

+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+

C
c
+

C
c
M8
M9
Figure P7.35
Solution
The smallsignal differential voltage gain can be found by simply connecting the sources of
M1 and M2 to ac ground and solving for the singleended output assuming the full input is
applied singleended.
∴ A
vdd
=
g
m1
g
m3.

}
`
g
m8
g
ds8
+g
ds9
R
out
=
.

}
`
1
g
ds8
+g
ds9
+
1
g
ds6
+g
ds7
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 723
Problem 7.306
Use the commonmode output stabilization circuit of Fig. 7.313 to stabilize the differential
output op amp of Fig. 7.33 to ground assuming that the power supplies are split around
ground (V
DD
= V
SS
). Design a correction circuit that will function properly.
Solution
V
DD
V
SS
V
ocm
V
BN
V
BP
M
1
M
2
M
5
M
6
M
3
M
4
M
11
M
9
M
7
M
12
M
10
M
8
V
o1 V
o2
v
i1
M1 M2
M3 M4
M5
M6
M7
V
DD
V
SS
V
BN
+

C
c
M9
C
c
V
BP
+

v
i2
v
o1
v
o2
R
z
R
z
M8
Referring to the figure of the commonmode stabilizing circuit, the commonmode voltage
at the output nodes v
o1
and v
o2
will be held close to the commonmode voltage V
ocm
due to
negative feedback. If these two output nodes swing differential, the drain of M5 will not
change and thus, the commonmode feedback circuit is nonfunctional. When the common
mode voltage at these two output nodes tend to change in the same direction, the negative
feedback loop of M1M5M6M7M9 and M2M5M6M8M10 will reduce the variations
at v
o1
and v
o2,
respectively.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 724
Problem 7.307
(a.) If all transistors in Fig. 7.312 have a dc current of 50µA and a W/L of 10µm/1µm,
find the gain of the common mode feedback loop. (b.) If the output of this amplifier is
cascoded, then repeat part (a.).
Solution
v
i1
M1 M2
M3 M4
M5
M6
M7
V
DD
V
SS
V
BN
+

C
c
M9
C
c
V
BP
+

v
i2
v
o1
v
o2
R
z
R
z
M8
Figure 7.312 Twostage, Miller, differentialin, differentialout op amp
with commonmode stabilization.
M10 M11
The loop gain of the commonmode feedback loop is,
CMFB Loop gain ≈ 
g
m10
g
ds9
= g
m10
r
ds9
or 
g
m11
g
ds8
= g
m11
r
ds8
With I
D
= 50µA and W/L = 10µm/1µm, g
m10
=
2K
P
’WI
D
L
= 2·50·10·50)
= 223.6µS,
r
dsN
=
1
λ
N
I
D
=
25
50µA
= 0.5MΩ and r
dsP
=
1
λ
P
I
D
=
20
50µA
= 0.4MΩ
∴ CMFB Loop gain ≈ −g
m10
r
ds9
= 223.6(0.5) = 111.8V/V
If the output is cascoded, the gain becomes,
CMFB Loop gain with cascoding ≈ −
g
m10
g
ds9
g
m
(cascode)r
ds
(cascode)
= g
m10
{[r
ds9
g
m
(cascode)r
ds
(cascode)][g
m7
r
ds7
(r
ds10
r
ds10
]}
g
mP
=
2K
N
’WI
D
L
= 2·110·10·50) = 331.67µS
= (223.6)[(0.5·331.67·0.5)(223.6)(0.4)(0.2)] = 223.6(14.7) = 3,290 V/V
∴ CMFB Loop gain with cascoding ≈ 3.290V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 725
Problem 7.308
Show how to use the common feedback circuit of Fig. 5.215 to stabilize the common
mode output voltage of Fig. 7.35. What would be the approximate gain of the common
mode feedback loop (in terms of g
m
and r
ds
) and how would you compensate the common
mode feedback loop?
Solution
V
DD
V
SS
MC
2
MC
1
MC
7
MC
4
MC
6
MC
3
MC
5
R
1
R
1
V
ICM
R
CM1
R
CM2
M
4
M
6
M
8
M
10
M
5
M
7
M
9
M
11
M
1
M
2
M
3
V
B1
V
B2
v
i1
v
i2
v
o1
v
o2
Referring to the figure, the loop gain of the commonmode feedback loop can be given by
LG
g g
g
g g
g
g g
g
m C m
m C
ds ds
m
ds ds
m
+
¹
´
¹
¹
`
¹
,
,
2 4
5
4 6
4
8 10
10
2
The compensation of the commonmode feedback loop can be done using the output load
capacitor (singleended load capacitors to ac ground). The dominant pole of this loop
would be caused at the output nodes by the large output resistance given by
R
g g
g
g g
g
out
ds ds
m
ds ds
m
+
¹
´
¹
¹
`
¹
1
4 6
4
8 10
10
Considering the differential output load capacitance to be
L
C
, the dominant pole of the
commonmode feedback loop can be expressed as
p
R C
out L
1
1
2
( )
The other poles, at the source and drain of MC3, and the source of M6, can be assumed to
be large as these nodes are low impedance nodes.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 726
Problem 7.401
Calculate the gain, GB, SR and P
diss
for the folded cascode op amp of Fig. 6.57b if V
DD
= V
SS
= 1.5V, the current in the differential amplifier pair is 50nA each and the current in
the sources, M4 and M5, is 150nA. Assume the transistors are all 10µm/1µm, the load
capacitor is 2pF and that n
1
is 2.5 for NMOS and 1.5 for PMOS.
Figure 6.57 (a) Simplified version of an Nchannel input, folded cascode op amp.
(b) Practical version (a).

+
v
in
M1 M2
I
1
I
2
Cascode
Current
Mirror
M6 M7
V
B
V
DD
V
SS
v
out
(a)
(b)
R
B

+
v
in
M1 M2
M4 M5
M6
M11
v
out
V
DD
V
SS
V
Bias
+

C
L
R
2
M7
M8 M9
M10
M3
I
3
I
4
I
5
I
6 I
7
I
1
I
2
R
1
M13
M14
M12
R
A
A
B
R
9
Solution
g
m1
= g
m2
=
I
D
n
1
(kT/q)
=
50nA
2.5·25.9mV
= 0.772µS and r
ds1
= r
ds2
=
1
I
D
λ
N
= 500MΩ
g
m4
= g
m5
=
I
D
n
1
(kT/q)
=
150nA
1.5·25.9mV
= 3.861µS and r
ds4
= r
ds5
=
1
I
D
λ
N
= 133MΩ
g
m6
= g
m7
=
I
D
n
1
(kT/q)
=
100nA
1.5·25.9mV
= 2.574µS and r
ds6
= r
ds5
=
1
I
D
λ
N
= 200MΩ
g
m8
= g
m9
= g
m10
= g
m11
=
I
D
n
1
(kT/q)
=
100nA
2.5·25.9mV
= 1.544µS
and r
ds8
= r
ds9
= r
ds10
= r
ds11
=
1
I
D
λ
N
= 250MΩ
Gain: A
v
(0) = g
m1
R
out
,
R
out
≈ r
ds11
g
m9
r
ds9
[g
m7
r
ds7
(r
ds5
r
ds2
)] = 96.5GΩ34.23GΩ = 25.269GΩ
∴ A
v
(0) = 0.772µS·25.269GΩ = 19,508 V/V
GB = g
m1
/C
L
= 386krads/sec = 61.43kHz (this assumes all other poles are greater than
GB which is the case if C
L
makes R
B
approximately the same as R
A
at ω = GB.)
SR = 100nA/2pF = 0.05V/µs P
diss
= 3V·(3·150nA) = 1.35µW
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 727
Problem 7.402
Calculate the gain, GB, SR and P
diss
for the op amp of Fig. 7.43 where I
5
= 100nA, all
transistor widths (M1M11) are 10µm and lengths 1µm, and V
DD
= V
SS
= 1.5V. If the
saturation voltage is 0.1V, design the W/L values of M12M15 that achieves maximum and
minimum output swing assuming the transistors M12 and M15 have 50nA. Assume that
I
DO
= 2nA, n
p
= 1.5, n
n
= 2.5 and V
t
= 25mV.
Solution
(Solution incomplete)
The smallsignal gain can be expressed as
A
g
g
g
g
g g R
v
m
m
m
m
m m out

.
`
}
+
]
]
]
1
3
8
9
7 6
2
or, A g R
v m out
1
The output resistance is given by
R
g
g g
g
g g
out
m
ds ds
m
ds ds
]
]
]
]
]
]
10
10 6
11
11 7

or, R
out
96 GΩ
Thus,
A g R
v m out
1
73 846 , V/V
Assuming C
c
1 pF
The dominant pole is
p
R C
out c
1
1
1 66 − . Hz.
Thus, the gainbandwidth becomes
GB A p
v
( ) . 0 122 5
1
KHz.
The power dissipation is 0.9 µW .
V V V n V
I
W L I
SG dsat dsat p t
D
10 6 10
10
10
0
0 236 + +
( )

.
`
}
ln . V
V V V n V
I
W L I
GS dsat dsat n t
D
11 7 11
11
11
0
0 26 + +
( )

.
`
}
ln . V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 728
Problem 7.403
Derive Eq. (17). If A = 2, at what value of v
in
/nV
t
will i
out
= 5I
5
or 5I
b
if b=1 ?
Solution
Start with the following relationships:
i
1
+ i
2
= I
5
+ A(i
2
 i
1
) Eq. (15)
and
i
2
i
1
= exp
.

}
`
v
in
nV
t
Eq. (16)
Defining i
out
= b(i
2
 i
1
) solve for i
2
and I
1
.
i
1
+ i
1
exp
.

}
`
v
in
nV
t
= I
5
+ Ai
1
exp
.

}
`
v
in
nV
t
 Ai
1
or i
1
[(1+A) +(1A) exp
.

}
`
v
in
nV
t
] = I
5
→ i
1
=
I
5
(1+A) +(1A) exp
.

}
`
v
in
nV
t
Similarly for i
2
,
i
1
=
I
5
exp
.

}
`
v
in
nV
t
(1+A) +(1A) exp
.

}
`
v
in
nV
t
∴ i
out
= b(i
2
 I
1
) = i
out
= (i
2
 I
1
) =
I
5
.

}
`
exp
.

}
`
v
in
nV
t
1
(1+A) +(1A) exp
.

}
`
v
in
nV
t
Eq.
(17)
Setting i
out
= 5I
5
and solving for
v
in
nV
t
gives,
5[3 exp
.

}
`
v
in
nV
t
] = exp
.

}
`
v
in
nV
t
1 → 16 = 6 exp
.

}
`
v
in
nV
t
→ exp
.

}
`
v
in
nV
t
=
2.667
∴
v
in
nV
t
= ln(2.667) = 0.9808
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 729
Problem 7.404
Design the current boosting mirror of Fig. 7.46a to achieve 100µA output when M2 is
saturated. Assume that i
1
= 10µA and W
1
/L
1
= 10. Find W
2
/L
2
and the value of V
DS2
where i
2
= 10µA.
Solution
Given, S
1
=10, I
1
= 10 µA, and I
1
= 100 µA when M2 is saturated. Thus,
S
2
=100
And, V
dsat1
= V
dsat2
= 0.135 V
Now, in the active region of operation for M2
I K S V V
V
D N dsat ds
ds
−
]
]
]
'
2 2
2
2
or, 10 100 100 0 135
2
2
µ µ ( ) −
]
]
]
. V
V
ds
ds
or, V mV
ds
≅ 7
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 730
Problem 7.405
In the op amp of Fig. 7.47, the current boosting idea illustrated in Fig. 7.46 suffers from
the problem that as the gate of M15 or M16 is increased to achieve current boosting, the
gatesource drop of these transistors increases and prevents the v
DS
of the boosting
transistor (M11 and M12) from reaching saturation. Show how to solve this problem and
confirm your solution with simulation.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 731
Problem 7.501
For the transistor amplifier in Fig. P7.51, what is the equivalent input
noise voltage due to thermal noise? Assume the transistor has a dc
drain current of 20 µA, W/L 150 µm/10 µm, K'
N
25 µA/V
2
, and
R
D
is 100 Kilohms.
Solution
122
m
g
S µ
and,
2 . 12 − − ≅
D m v
R g A
The equivalent input thermal noise is
2
2
4
3
8
v
D
m
eq
A
KTR
g
KT
e +
or,
18 2
10 1 . 102
−
×
eq
e
Hz V /
2
or, V
eq
(rms) ≈ 10nV/ Hz
Problem 7.502
Repeat Ex. 7.51 with W
1
= W
2
= 500µm and L
1
= L
2
= 0.5µm to decrease the noise by a
factor of 10.
Solution
5 . 0 / 500
1
S
,
20 / 100
3
S
Flicker noise
22
10 36 . 7
−
×
N
B
( )
2
Vm
and
22
10 02 . 2
−
×
P
B
( )
2
Vm
f L fW
B
e
P
n
13
1 1
2
1
10 08 . 8
−
×
Hz V /
2
So,
]
]
]
]
}
`
.

}
`
.

+
2
3
1
’
’
2
1
2
1 2
L
L
B K
B K
e e
P P
N N
n eq
→
f
e
eq
12
2
10 624 . 1
−
×
Hz V /
2
Thermal noise
17
1
2
1
10 49 . 0
3
8
−
×
m
n
g
KT
e
Hz V /
2
]
]
]
]
+
3 1
’
1 3
’
2
1
2
1 2
L W K
L W K
e e
P
N
n eq
→
17 2
10 08 . 1
−
×
eq
e
Hz V /
2
The corner frequency,
4 . 150
c
f
KHz
Considering a 100 KHz. Bandwidth
( ) ( )
5 17 5 12 2
10 10 08 . 1 10 ln 10 624 . 1 ) (
− −
× + × rms V
eq
→
45 . 4 ) ( rms V
eq
V µ
V
DD
R
D
20µA
Figure P7.51
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 732
Problem 7.503
Interchange all nchannel and pchannel transistors in Fig. 7.51 and using the W/L values
designed in Example 7.51, find the input equivalent 1/f noise, the input equivalent thermal
noise, the noise corner frequency and the rms noise in a 1Hz to 100kHz bandwidth.
Solution
The flicker noise is
22
10 36 . 7
−
×
N
B
( )
2
Vm
and
22
10 02 . 2
−
×
P
B
( )
2
Vm
f L fW
B
e
N
n
12
1 1
2
1
10 36 . 7
−
×
Hz V /
2
So,
]
]
]
]
}
`
.

}
`
.

+
2
3
1
’
’
2
1
2
1 2
L
L
B K
B K
e e
N N
P P
n eq →
f
e
eq
12
2
10 72 . 14
−
×
Hz V /
2
The thermal noise is
17
1
2
1
10 05 . 1
3
8
−
×
m
n
g
KT
e
Hz V /
2
]
]
]
]
+
3 1
’
1 3
’
2
1
2
1 2
L W K
L W K
e e
N
P
n eq → e
2
eq
= 2.42x1017 V
2
/Hz
The corner frequency is f
c
= 608 KHz .
Considering a 100 KHz. Bandwidth
V
2
eq
(rms) = 14.72x10
12
ln(10
5
) + 2.42x10
17
ln(10
5
) → V
eq
(rms) = 13.1 nV/ Hz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 733
Problem 7.504
Find the input equivalent rms noise voltage of the op amp designed in Ex. 6.31 of a
bandwidth of 1Hz to 100kHz.
Solution
The input referred noise is given by
]
]
]
]
}
`
.

+
}
`
.

+
2
6
2
1
2
3
2
1
3 2
1
2
1
2 2
n
v
n
m
m
n eq
e
A
e
g
g
e e
Flicker noise
]
]
]
]
}
`
.

+
}
`
.

}
`
.

+
2
6
2
1
2
3
2
3
1
’
’
2
1
2
1
2 2
n
v
n
N N
P P
n eq
e
A
e
L
L
B K
B K
e e
f
e
n
10
2
1
10 45 . 2
−
×
Hz V /
2
f
e
n
11
2
3
10 35 . 1
−
×
Hz V /
2
f
e
n
12
2
6
10 15 . 2
−
×
Hz V /
2
5 . 68
1
−
v
A
Thus,
f
e
eq
10
2
10 9 . 4
−
×
Hz V /
2
Thermal noise
16 2
1
10 11 . 1
−
×
n
e
Hz V /
2
17 2
3
10 395 . 7
−
×
n
e
Hz V /
2
17 2
6
10 17 . 1
−
×
n
e
Hz V /
2
or,
16 2
10 58 . 5
−
×
eq
e
Hz V /
2
The corner frequency is
884
c
f
KHz
Considering a 100 KHz bandwidth
( ) ( )
5 16 5 10 2
10 10 58 . 5 10 ln 10 9 . 4 ) (
− −
× + × rms V
eq
→V
eq
(rms) = 75.5 µV/ Hz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 734
Problem 7.505
Find the equivalent rms noise voltage of the op amp designed in Example 6.52 over a
bandwidth of 1Hz to 100kHz. Use the values for KF of Example 7.51.
Solution
The circuit for this
amplifier is
shown.
The W/L ratios in
microns are:
S
1
= S
2
= 12/1
S
3
= S
4
= 16/1
S
5
= 7/1
S
5
= 8.75/1
S
6
= S
7
= S
8
=
S
14
= S
15
= 40/1
S
9
= S
10
= S
11
=
S
12
= 18.2/1
Find the short
circuit noise current at the output, i
2
to
, due to each noisecontributing transistor in the
circuit (we will not includeM7, M9, M12 and M14 because they are cascodes and their
effective g
m
is small. The result is,
i
2
to
= 2g
2
m1
e
2
n1
.

}
` g
2
m8
g
2
m3
+ 2g
2
m8
e
2
n3
+ 2g
2
m8
e
2
n8
+ + 2g
2
m11
e
2
n10
where we have assumed that g
m1
=g
m2
, g
m3
=g
m4
, g
m6
=g
m8
, and g
m10
=g
m11
and
e
n1
=e
n2
, e
n3
=e
n4
, e
n6
=e
n8
, and e
n10
=e
n11
. Dividing i
2
to
by the transconductance gain
gives
e
2
eq
=
i
2
to
g
2
m1
g
2
m8
/g
2
m3
= 2e
2
n1
+ 2
.

}
` g
2
m3
g
2
m1
e
2
n3
+ 2
.

}
` g
2
m3
g
2
m1
e
2
n8
+ 2
.

}
` g
2
m3
g
2
m11
g
2
m1
g
2
m8
e
2
n10
The values of the various parameters are:
g
m1
= 251µS, g
m3
= 282.5µS, g
m8
= 707µS, and g
m11
= 707µS.
∴ e
2
eq
= 2e
2
n1
]
]
]
1 + 1.266
.

}
` e
2
n3
e
2
n1
+
e
2
n8
e
2
n1
+
e
2
n10
e
2
n1
e
eq
M1 M2
M3
M4
M5
M6
M11
i
to
V
DD
V
SS
V
Bias
+

R
1
M9
M10
R
2
M14
M15
M8
M12
M7
M13
2
*
2
Fig. S7.505
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 735
Problem 7.505 – Continued
1/f Noise:
Using the results of Ex. 7.51 we get B
N
= 7.36x10
22
(V·m)
2
and B
p
= 2.02x10
22
(V·m)
2
e
2
n1
=
B
N
fW
1
L
1
=
7.36x10
22
f·12x10
12
=
6.133x10
11
f
V
2
/Hz
e
2
n3
e
2
n1
=
B
P
·f·W
1
L
1
B
N
·f·W
3
L
3
=
B
P
·W
1
L
1
B
N
·W
3
L
3
=
2.02·12
7.36·16
= 0.2058
e
2
n8
e
2
n1
=
B
P
·f·W
1
L
1
B
N
·f·W
8
L
3
=
B
P
·W
1
L
1
B
N
·W
3
L
3
=
2.02·12
7.36·40
= 0.0823
e
2
n10
e
2
n1
=
B
N
·f·W
1
L
1
B
N
·f·W
10
L
10
=
B
P
·W
1
L
1
B
N
·W
3
L
3
=
12
18.2
= 0.6593
∴ e
2
eq
= 2
6.133x10
11
f
[1+1.266(0.2058+0.0823+0.6593)] = 2
6.133x10
11
f
2.1995
e
2
eq
=
2.1995x10
10
f
V
2
/Hz
Thermal noise:
e
2
n1
=
8kT
3g
m1
=
8·1.38x10
23
·300
3·251x10
6
= 4.398x10
17
V
2
/Hz
e
2
n3
e
2
n1
=
g
m1
g
m3
=
251
282.4
= 0.8888 and
e
2
n8
e
2
n1
=
e
2
n10
e
2
n1
=
g
m1
g
m8
=
251
707
= 0.0.355
The corner frequency is f
c
= 2.698x10
10
/2.66x10
16
= 1.01x10
6
Hz. Therefore in a 1Hz
to 100kHz band, the noise is 1/f. Solving for the rms value gives,
V
2
eq
(rms) = ⌡
⌠
1
100,000
2.698x10
10
f
df = 2.698x10
10
[ln(100,000) – ln(1)]
= 3.1062x10
9
V
2
(rms)
∴ V
eq
(rms) = 55.73µV( rms)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 736
Problem 7.601
If the W and L of all transistor in Fig. 7.63 are 100µm and 1µm, respectively, find the
lowest supply voltage that gives a zero value of ICMR if the dc current in M5 is 100µA.
Solution
100
5
I
µA, and
W
L

.
`
}
100
V V V V
IC DD T dsat
(max) (min) + −
1 3
and, V V V V
IC dsat T dsat
(min) (max) + +
1 1 5
The input commonmode range is
ICMR V V
IC IC
− (max) (min)
For ICMR=0
V V V V V V
DD dsat dsat dsat T T
+ + + −
1 5 3 1 1
(max) (min)
or, V
I
K S
I
K S
I
K S
V V
DD
N N P
T T
+ + + −
2 2 2
1
1
5
5
3
3
1 1 ' ' '
(max) (min) → V
DD
= 0.671 V
Problem 7.602
Repeat Problem 1 if M1 and M2 are natural MOSFETs with a V
T
= 0.1V and the other
MOSFET parameters are given in Table 3.12.
Solution
1 . 0
1
T
V
V,
100
5
I
µA, and
W
L

.
`
}
100
Let, the variation in the threshold voltage be
% 20 ±
or,
02 . 0
1
± ∆
T
V
V
V V V V
IC DD T dsat
(max) (min) + −
1 3
and, V V V V
IC dsat T dsat
(min) (max) + +
1 1 5
The input commonmode range is
ICMR V V
IC IC
− (max) (min)
For ICMR=0
V V V V V V
DD dsat dsat dsat T T
+ + + −
1 5 3 1 1
(max) (min)
or, V
I
K S
I
K S
I
K S
V V
DD
N N P
T T
+ + + −
2 2 2
1
1
5
5
3
3
1 1 ' ' '
(max) (min) → V
DD
= 0.411 V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 737
Problem 7.603
Repeat Problem 1 if M1 and M2 are depletion MOSFETs with a V
T
= 1V and the other
MOSFET parameters are given in Table 3.12.
Solution
1
1
−
T
V
V,
100
5
I
µA, and
W
L

.
`
}
100
Let, the variation in the threshold voltage be
% 20 ±
or,
2 . 0
1
m ∆
T
V
V
V V V V
IC DD T dsat
(max) (min) + −
1 3
and, V V V V
IC dsat T dsat
(min) (max) + +
1 1 5
The input commonmode range is
ICMR V V
IC IC
− (max) (min)
For ICMR=0
V V V V V V
DD dsat dsat dsat T T
+ + + −
1 5 3 1 1
(max) (min)
or, V
I
K S
I
K S
I
K S
V V
DD
N N P
T T
+ + + −
2 2 2
1
1
5
5
3
3
1 1 ' ' '
(max) (min) → V
DD
= 0.711 V
Problem 7.604
Find the values of Vonn and Vonp of Fig. 7.64 if the W and L values of all transistors are
10µm and 1µm, respectively and the bias currents in MN5 and MP5 are 100µA each.
Solution
1 , 1 5 ,
(max)
N dsat TN N dsat
V V V Vonn + +
or,
302 . 0 85 . 0 426 . 0 + + Vonn
→ V
onn
= 1.578 V
Let us assume that
5 . 2
DD
V
V
(max)
1 , 5 , 1 , P T P dsat P dsat DD
V V V V Vonp − − −
→ V
onp
= 0.57 V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 738
Problem 7.605
Two nchannel sourcecoupled pairs, one using regular transistors and the other with
depletion transistors having a V
T
= 1Vare connected with their gates common and the
sources taken to individual current sinks. The transistors are modeled by Table 3.12
except the threshold is 1V for the depeletion transistors. Design the combined source
coupled pairs to achieve railtorail for a 0V to 2V power supply. Try to keep the
equivalent input transconductance constant over the ICMR. Show how to recombine the
drain currents from each sourcecoupled pair in order to drive a secondstage singleended.
Solution
V
DD
V
SS
V
BN
+ +  
V
BP
V
T
=0.7 V
T
=1.0
M
1
M
2
M
5
M
3
M
4
MD
1
MD
2
MD
3
MD
4
MD
5
V
DD
V
SS
V
BN
+

V
BP
V
T
=0.7 V
T
=1.0
M
1
M
2
M
5
M
3
M
4
MD
1
MD
2
MD
5
+
Considering the differential amplifier consisting of M1M5, the range of the input common
mode can be given by
V V V V
IC DD T dsat
(max) + −
1 3
and V V V V V
IC SS T dsat dsat
(min) + + +
1 1 5
(1)
Now, considering the differential amplifier consisting of MD1MD5, the range of the input
common mode can be given by
V V V V
IC DD T D dsat D
(max)
, ,
+ −
1 3
and V V V V V
IC SS T D dsat D dsat D
(min)
, , ,
+ + +
1 1 5
(2)
Let us assume that the saturation voltage (V
dsat
) of each of the transistors is equal to 0.1 V,
and let V
DD
2 V
Then, from Equation (1), for the transistors M1M5
V
IC
(max) . 2 6 V and V
IC
(min) . 0 9 V
From Equation (2), for the transistors MD1MD5
V
ic
(max) = 0.9 V and V
ic
(min) = 0.8 V
Since, the commonmode input range of both stages overlap, they can be joined as shown
in the figure and will provide a constant g
m
across the railtorail input range of 02 V.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 739
Problem 7.606
Show how to create current mirrors by appropriately modifying the circuits in Sec. 4.4 that
will have excellent matching and a V
MIN
(in) = V
ON
and V
MIN
(out) = V
ON.
Solution
i
in
M1
M2
M3
V
DD
I
B
M4
M5
M6
M7
i
out
I
1
I
B
I
B
I
2
or
i
in
M1
M2
M3
V
DD
I
B1
M4
M5
M6
M7
i
out
I
1
I
B2
I
2 I
B1
I
B2
Fig. 7.613A
Problem 7.607
Show how to modify Fig. 7.616 to compensate for the temperature range to the left of
where the two characteristics cross.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 740
Problem 7.608
For the op amp of Ex. 7.61, find the output and higher order poles and increase the GB as
much as possible and still maintain 60° phase margin. Assume that L1+L2+L3 = 2µm in
order to calculate the bulksource/drain depletion capacitors (assume zero voltage bias).
What is the new value of GB and the value of C
c
?
Solution
Referring to the Figure 7.617 and Example 7.61, the dominant pole is caused at the drain
of M9. The second pole ( p
2
) is caused at the output by the load capacitor. The magnitude
of this pole is given by
p
g
C
m
L
2
14
20
−
− MHz.
To increase the gain bandwidth, let us design the nulling resistor ( R
Z
) in such a way that
the LHP zero created by this resistor will cancel the load pole. The value of C
c
2 pF.
Thus, R
g C p
Z
m c
+
1 1
2
4 77
14 2
π
. KΩ
We can see that the pole at the source of M6 is
p
6
1 2 − . GHz.
The third pole ( p
3
) at the output is caused by the nulling resistor and is given by
p
R C
Z gs
3
14
1
2
101 ≅
−
−
π
MHz.
In order to maintain a phase margin of 60
o
, the gain bandwidth can be calculated as
tan
−

.
`
}
1
3
30
GB
p
o
→ GB 58 MHz.
or, g GB C
m c 1
729 ( )
S µ
→
W
L
W
L

.
`
}

.
`
}
1 2
241 6 .
Considering the minimum input commonmode range
V
dsat 5
0 22 . V →
W
L

.
`
}
5
7 5 .
Considering the maximum input commonmode range
W
L
W
L

.
`
}

.
`
}
3 4
19 2 .
Rest of the transistor sizes are the same as calculated in Example 7.61. But, the small
signal voltage gain is 18,000 V/V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 741
Problem 7.609
Replace M8 and M9 of Fig. 7.617 with a high swing cascode current mirror of Fig. 4.37
and repeat Ex. 7.61.
Solution
Referring to the figure and Example 7.61
V
GS8
1 5 . V → V
dsat 8
0 8 . V →
W
L
W
L

.
`
}

.
`
}
≅
8 9
0 57 1 .
Let us assume V
BIAS
2 V. Then,
V
dsat17
0 5 . V →
W
L
W
L

.
`
}
+

.
`
}
17 18
1 45 .
The output resistance seen at the drain of M7 is
R
g g
g
g g g
g
out
ds ds
m
ds ds ds
m
1
18 9
18
7 4 2
7
1
50
+
+ ( )
¹
´
¹
¹
`
¹
MΩ
Thus, the overall smallsignal gain becomes 2 8 10
5
. × V/V.
The gain bandwidth is 10 MHz. The load pole is at 20 MHz. Referring to the figure, the
extra pole that would affect the phase margin the most is created at the source of M18. The
resistance seen at the source of M18 can be given by
R
r
g
g g g
g r
r
S
ds
m
ds ds ds
m ds
ds 18
18
7
7 4 2
18 18
9
1
+
+ ( )
¹
´
¹
¹
`
¹
+ ( )
]
]
]
]
]
]
[ ]  → R K M
S18
844 1 25 504 [ ] [ ]  . KΩ
The pole at the source of M18 is
p
R C C C C
S gs bd gd bd
18
18 18 18 9 9
1
−
+ + +
( )
→ p
K
18
15
1
504 9 10
35
−
( ) × ( )
−
−
MHz
It can be seen that this pole p
18
would degrade the phase margin by 16
o
. Thus to maintain a
60
o
phase margin with a gain bandwidth of 10 MHz, let us use nulling resistor
compensation to cancel this pole. The value of R
z
can be given by
R
g C p
Z
m c
+
1 1
2
3 07
14 18
π
. KΩ
The pole due to the introduction of R
z
is
p
R C
Z gs
4
14
1
157
−
− MHz
This pole is large enough to affect the phase margin. Though the pole at the source of M18
has been eliminated using the nulling resistor compensation technique, the pole at the
source of M7 could be dominant enough to degrade the phase margin.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 81
CHAPTER 8 – HOMEWORK SOLUTIONS
Problem 8.101
Give the equivalent figures for Figs. 8.12, 8.14, 8.16 and 8.19 for an inverting
comparator.
Solution
The figures for the inverting comparator are shown below.
V
OH
V
OL
V
o
v
p
v
n
V
o
v
p
v
n
V
OL
V
OH
V
IH
V
IL
V
o
v
p
v
n
V
OL
V
OH
V
IH
V
IL
V
OS
V
o
t
V
OL
V
OH
V
in
t
V
IH
V
IL
t
p
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 82
Problem 8.102
Use the macromodel techniques of Sec. 6.6 to model a comparator having a dc gain of
10,000 V/V, and offset voltage of 10mV, V
OH
= 1V, V
OL
= 0V, a dominant pole at 1000
radians/sec. and a slew rate of 1V/µs. Verify your macromodel by using it to simulate Ex.
8.11.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 83
Problem 8.103
Draw the firstorder time response of an inverting comparator with a 20 µs propagation
delay. The input is described by the following equation
v
in
0 for t < 5 µs
v
in
5(t − 5 µs) for 5 µs < t < 7 µs
v
in
10 for t > 7 µs
Solution
The input and the output response of the inverting comparator are shown in the figure.
V
o
t
V
OL
V
OH
V
in
t
V
IH
=10
V
IL
=0
t
p
=20
5 6 7
0.5(V
OH
+V
OL
)
0.5(V
IH
+V
IL
)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 84
Problem 8.104
Repeat Ex. 8.11 if the pole of the comparator is 10
5
radians/sec rather than 10
3
radians/sec.
Solution
The pole location is
100 −
c
ω
Krad/s
100
1 . 0
10
(min)
m
m
V
V
k
in
in
The propagation delay is given by
}
`
.

−
1 2
2
ln
1
k
k
t
c
p
ω
or,
1 . 50
p
t
ns (1)
Considering the maximum slew rate, the propagation delay can be expressed as
SR
V V
t
OL OH
p
2
’
−
or,
500
’
p
t
ns (2)
From Equations (1) and (2), the propagation delay is
t
p
= 500 ns
Problem 8.105
What value of V
in
in Ex. 8.11 will give a slewing response?
Solution
The comparator will start to slew when the propagation delay of the comparator is
dominated by its maximum slew rate (and not by the comparator’s smallsignal propagation
delay).
}
`
.

−
>
−
1 2
2
ln
1
2 k
k
SR
V V
c
OL OH
ω
or,
( )
SR
V V
k
k
OL OH c
2 1 2
2
ln
−
<
}
`
.

−
ω
Solving for k, we get
5 . 1000 > k
or, V
in
> 100.05 mV
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 85
Problem 8.201
Repeat Ex. 8.21 for the twostage comparator of Fig. 8.25.
Solution
The output swing levels are
( )
( )
]
]
]
]
− −
− − − − −
2
6 6
7
6
(min)
2
1 1 (min)
TP G DD
TP G DD DD OH
V V V
I
V V V V V
β
or,
( )
( ) ]
]
]
]
− −
− − − − −
2
7 . 0 0 5 . 2 ) 38 )( 50 (
) 234 ( 2
1 1 7 . 0 0 5 . 2 5 . 2
OH
V
or, V
OH
= 2.43 V
V
OL
= V
SS
= 2.5 V
The minimum input resolution is
v
OL OH
in
A
V V
V
−
(min)
and,
( )
3300
2
6 1
2 1
+
N P
m m
v
I I
g g
A
λ λ
or, V
in
(min) = 1.5 mV
The pole locations are
p
1
=
g
ds2
+ g
ds4
C
I
= 1.074 MHz
p
2
=
g
ds6
+ g
ds7
C
II
= 0.67 MHz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 86
Problem 8.202
If the poles of a twostage comparator are both equal to 10
7
radians/sec., find the
maximum slope and the time it occurs if the magnitude of the input step is 10V
in
(min) and
V
OH
V
OL
= 1V. What must be the SR of this comparator to avoid slewing?
Solution
The response to a step response to the above comparator can be written as,
v
out
’ = 1 – e
tn
–t
n
e
tn
where v
out
’ =
v
out
A
v
(0)V
in
and t
n
= tp
1
To find the maximum slope, differentiate twice and set to zero.
dv
out
’
dt
n
= e
tn
+ t
n
e
tn
 e
tn
= t
n
e
tn
d
2
v
out
’
dt
n
2
= t
n
e
tn
+ e
tn
= 0 ⇒ (1t
n
)e
tn
= 0 ⇒ t
n
(max) = tp
1
= 1
∴ t
n
(max) = 1sec and t(max) =
t
n
p
1

=
1
10
7
= 0.1µs
dv
out
’(max)
dt
n
= e
1
= 0.3679 V/sec or
dv
out
’(max)
dt
n
= 3.679V/µs
dv
out
’(max)
dt
= 10(V
OH
V
OL
)·
dv
out
’(max)
dt
n
= 36.79V/µs
∴ Therefore, the slew rate of the comparator should be greater than 36.79V/µs to avoid
slewing.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 87
Problem 8.203
Repeat Ex. 8.23 if p
1
= 5x10
6
radians/sec. and p
2
= 10x10
6
radians/sec.
Solution
Given
5
1
− p
Mrad/s, and
10
2
− p
Mrad/s
So,
2
1
2
p
p
m
When
m V
in
10
576 . 15
(min)
in
in
V
V
k
and,
8 . 35
1
1
mk p
t
p ns
When
m V
in
100
(assuming no slewing)
76 . 155
(min)
in
in
V
V
k
and,
3 . 11
1
1
mk p
t
p ns
When
1
in
V
(assuming no slewing)
6 . 1557
(min)
in
in
V
V
k
and,
58 . 3
1
1
mk p
t
p ns
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 88
Problem 8.204
For Fig. 8.25, find all of the possible initial states listed in Table 8.21 of the first stage
output voltage and the comparator output voltage.
Solution
Condition:
0 , ,
2 1 2 1
> < > I I I V V
SS G G
5 . 2 1315 . 2
1
< <
o
V
, and
5 . 2
2
−
o
V
Condition:
0 , ,
2 1 2 1
>> I I I V V
SS G G
5 . 2
1
o
V
, and
5 . 2
2
−
o
V
Condition: SS G G
I I I V V < > <
2 1 2 1
, 0 ,
3 . 0
2 1 2
+ < <
S o S
V V V
, and
( ) 7 . 0 5 . 2
123 . 0
5 . 2
1
2
− −
−
o
o
V
V
Condition: SS G G
I I I V V <<
2 1 2 1
, 0 ,
5 . 2
1
−
o
V
, and
47 . 2
2
o
V
Condition: SS G G
I I I V V < > >
2 1 1 2
, 0 ,
3 . 0
2 1 2
+ < <
S o S
V V V
, and
( ) 7 . 0 5 . 2
123 . 0
5 . 2
1
2
− −
−
o
o
V
V
Condition: SS G G
I I I V V >>
2 1 1 2
, 0 ,
5 . 2
1
−
o
V
, and
47 . 2
2
o
V
Condition:
0 , ,
2 1 1 2
> < < I I I V V
SS G G
5 . 2 1315 . 2
1
< <
o
V
, and
5 . 2
2
−
o
V
Condition:
0 , ,
2 1 1 2
<< I I I V V
SS G G
5 . 2
1
o
V
, and
5 . 2
2
−
o
V
Problem 8.205
Calculate the trip voltage for the comparator shown in Fig. 8.24. Use the parameters given
in Table 3.12. Also, (W/L)
2
100 and (W/L)
1
10. V
BIAS
1V, V
SS
0V, and V
DD
4 V.
Solution
Given,
1
BIAS
V
,
4
DD
V
,
0
SS
V
,
100
7
S
, and
10
7
S
The trip point is given by
( )
7
6
’
7
’
6 T SS BIAS
P
N
T DD TRP
V V V
S K
S K
V V V − − − −
or,
89 . 1
TRP
V
V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 89
Problem 8.206
Using Problem 8.25, compute the worstcase variations of the trip voltage assuming a
±10% variation on V
T
, K', V
DD
, and V
BIAS
.
Solution
The trip point is given by
( )
7
6
’
7
’
6 T SS BIAS
P
N
T DD TRP
V V V
S K
S K
V V V − − − −
The maximum trip point can be given by
( )
7
6
’
7
’
6
1 . 1 9 . 0
1 . 1
9 . 0
9 . 0 1 . 1 (max)
T SS BIAS
P
N
T DD TRP
V V V
S K
S K
V V V − − − −
or, V
TRP
(max) = 3.22 V
The minimum trip point can be given by
( )
7
6
’
7
’
6
9 . 0 1 . 1
9 . 0
1 . 1
1 . 1 9 . 0 (min)
T SS BIAS
P
N
T DD TRP
V V V
S K
S K
V V V − − − −
or, V
TRP
(min) = 0.39 V
Problem 8.207
Sketch the output response of the circuit in Problem 5, given a step input that goes from 4
to 1 volts. Assume a 10 pF capacitive load. Also assume the input has been at 4 volts for a
very long time. What is the delay time from the step input to when the output changes
logical (CMOS) states?
Solution
Let us assume
5
OH
V
V and
0
OL
V
V
The trip point of the second stage is
3.965 V.
When the input makes a transition
from 4 V to 1,
( )
( )
4 . 26
30
0 965 . 3
2 . 0
1
−
µ
p t
ro
nsand
( )
( )
8 . 106
234
5 . 2
10
,
µ
p t
out f
ns
Thus, the total propagation delay is 133.2 ns. This is also the time it takes to change the
output logical states.
time
5
4
1
0
v
in
v
out
2.5
T T+133.2ns
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 810
Problem 8.208
Repeat Ex. 8.25 with v
G2
constant and the waveform of Fig. 8.26 applied to v
G1
.
Solution
Output fall time, t
r
:
The initial states are v
o1
≈ 2.5V and v
out
≈ 2.5V. The reasoning for v
o1
is
interesting and should be understood. When V
G1
= 2.5V and V
G2
= 0V, the current in
M1 is zero. This means the current is also zero in M4. Therefore, v
o1
goes very negative
and as M2 acts like a switch with V
DS
≈0. Since the only current for M3 comes through
M2 and from C
I
, the voltage across M3 eventually collapses and I
3
becomes zero which
causes v
o1
≈ 2.5V.
From Example 8.25, the trip point of the second stage is 1.465V, therefore the rise
time of the first stage is,
t
r1
= 0.2pF
.

}
`
1.465+2.5
30µA
= 26.4ns
The fall time of the second stage is found in Example 8.25 and is t
f2
= 53.4ns. The total
output fall time is
∴ t
r
= t
r1
+ t
f2
= 79.8ns
Output rise time, t
r
:
The initial states for this analysis are v
o1
≈ 2.5V and v
out
≈ 2.5V.
The input stage fall time is,
t
f1
= 0.2pF
.

}
`
2.51.465
30µA
= 6.9ns
The output stage rise time is found by determining the best guess for V
G6
. Since
V
G6
is going from 1.465 to –2.5V, let us approximate V
G6
as
V
G6
≈ 0.5(1.4652.5) = 0.5175 ⇒ V
SG6
= 2.5(0.5175) = 3.0175V
∴ I
6
=
1
2
K
P'
.

}
`
W
6
L
6
(V
SG6
V
TP
)
2
= 0.5·50x10
6
·38(3.01750.7)
2
= 5102µA
t
r2
= 5pF
.

}
`
2.5
5102µA234µA
= 2.6ns
The total output rise time is,
∴ t
r
= t
f1
+ t
r2
= 9.5ns
The propagation time delay of the comparator is,
t
p
= t
r
+ t
r
= 44.7ns
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 811
Problem 8.209
Repeat Ex. 8.35 using the twostage op amp designed in Ex. 6.31 if the compensation
capacitor is removed.
Solution
Let us assume the initial states as
5 . 2
2
−
G
V
V
5 . 2
1
o
V
V
5 . 2 −
out
V
V
and,
2 . 0
I
C
pF
For the rising edge of the input,
5 . 2
2
G
V
V
V V V
I
K S
TRP DD T
P
2 6
7
6
2
− +

.
`
}
'
→
6 . 1
2
TRP
V
V
Thus, t p
V
fo1
0 2
0 9
30
6 ( )
( )
( )
.
.
µ
ns
The minimum value of 6 G
V
is
1
2 6
− − ≅
GS G
V V
V
Average value of 6 G
V
is
3 . 0
2
6 . 1 1
6
+ −
G
V
V
Thus,
( )
2
6 6
6
’
6
2
T SG
P
V V
S K
I −
→
2875 . 5
6
I
mA
So,
( )
( ) ( )
( )
36 . 2
5 . 5287
5 . 2 6 . 1
5
,
− −
µ
p t
out r ns
Thus, total propagation delay for the rising input is
36 . 8
1
p
t
ns
For the falling edge of the input,
5 . 2
2
−
G
V
V
( )
( ) ( )
( )
3 . 27
30
5 . 2 6 . 1
2 . 0
1
− −
µ
p t
ro
ns
and,
( )
( )
( )
6 . 131
95
5 . 2
5
,
µ
p t
out f
ns
Thus, total propagation delay for the falling input is
9 . 158
2
p
t
ns
The average propagation delay is 83.63 ns .
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 812
Problem 8.210
Repeat Ex. 8.26 if the propagation time is t
p
= 25ns.
Solution
Given,
25
p
t
ns
Let,
10 , 1 k m
or,
65 . 12
1
2 1
mk t
p p
p
Mrad/s
( )
752
2
7 6
+
N P
II
C p
I I
λ λ
A µ
or,
( )
120
2
2
6
’
6
6
}
`
.

dsat P
V K
I
L
W
and,
( )
55
2
2
7
’
7
7
}
`
.

dsat N
V K
I
L
W
Now,
4 . 44
2
v
A
, and for
4000
v
A
, we have
11 . 90
1
v
A
In order to satisfy the propagation delay from the first stage, let us assume
40
1
I
A µ
The corresponding propagation delay of the first stage becomes
( )
10
2
2
1
−
I
V V C
t
OL OH I
p ns
Now,
( )
1 1 1
I A g
N P v m
λ λ +
or,
4 . 324
1
m
g
S µ
or,
12
2 1
}
`
.

}
`
.

L
W
L
W
Also,
25 . 1 (min) −
IC
V
V, and
946 . 0
1
GS
V
V.
Thus,
304 . 0
5
dsat
V
V
or,
16
5
}
`
.

L
W
Assuming a V
SG3
= 1.2V gives,
W
3
L
3
=
W
4
L
4
=
40
50(1.20.7)
2
≈ 4
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 813
Problem 8.211
Design a comparator given the following requirements: P
diss
< 2 mW, V
DD
3 V, V
SS
0
V C
load
3 pF, t
prop
< 1 µs, input CMR 1.5 − 2.5 V, A
v0
> 2200, and output voltage
swing within 1.5 volts of either rail. Use Tables 3.12 and 3.31 with the following
exceptions: λ 0.04 for a 5 µm device length.
Solution
The ICMR is given as 1.52.5 V. Let us assume that
3
2 1
}
`
.

}
`
.

L
W
L
W
and
30
5
I
A µ
Considering the minimum input commonmode range
5 1 1
(max) (min)
dsat dsat T SS IC
V V V V V + + +
or,
35 . 0
5
dsat
V
V →
5 . 4
1
}
`
.

L
W
Considering the maximum input commonmode range
3 3 1
(max) (min) (max)
dsat T T DD IC
V V V V V − − +
or,
2 . 0
5
dsat
V
V →
15
4 3
}
`
.

}
`
.

L
W
L
W
Let us assume
5 . 31
7
}
`
.

L
W
and
210
7
I
A µ
From proper mirroring of the bias currents, we get
210
6
}
`
.

L
W
The value of
348
6
≅
gs
C
fF. Thus, let us assume
5 . 0
I
C
pF.
The smallsignal gain for this comparator is 8189 V/V.
The total power dissipation is 0.81 mW.
The trip point of the second stage is
1 . 2
2
TRP
V
V
For the rising edge of the input, referring to the procedure in Example 8.25, the
propagation delay can be calculated as
15
1
fo
t
ns,
4 . 2
,
out r
t
ns, and the total propagation delay
4 . 17
1
p
t
ns
For the falling edge of the input, the propagation delay can be found as
35
1
ro
t
ns,
4 . 21
,
out f
t
ns, and the total propagation delay
4 . 56
2
p
t
ns
The average propagation delay is 36.9 ns, which is well below 1000 ns.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 814
Problem 8.301
Assume that the dc current in M5 of Fig. 8.31 is 100µA. If W
6
/L
6
= 5(W
4
/L
4
) and
W
10
/L
10
= 5(W
3
/L
3
), what is the propagation time delay of this comparator if C
L
= 10pF
and V
DD
= V
SS
= 2V?
Solution
The quiescent bias currents are
250
7 6
I I
A µ
Under largesignal swing conditions, the maximum sourcing and sinking currents are
500 (max)
6
I
A µ
500 (max)
7
I
A µ
Thus, the propagation delay can be given by
( )
L
SS DD
L p
I
V V
C t
−
5 . 0
or,
( )
) 500 (
2 5 . 0
) 10 (
µ
p t
p
or, t
p
= 20 ns
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 815
Problem 8.302
If the foldedcascode op amp shown having a smallsignal voltage gain of 7464V/V is used
as a comparator, find the dominant pole if C
L
= 5pF. If the input step is 10mV, determine
whether the response is linear or slewing and find the propagation delay time. Assume the
parameters of the NMOS transistors are K
N
’=110V/µA
2
, V
TN
= 0.7V, λ
N
=0.04V
1
and for
the PMOS transistors are K
P
’=110V/µA
2
, V
TP
= 0.7V, λ
P
=0.04V
1
.

+
v
in
M1 M2
M4 M5
M6
M11
v
out
V
Bias
+

C
L
R
2
=
2kΩ
M7
M8 M9
M10
M3
I
3
=
100µA
I
5
=
125µA
I
6 I
7
I
1
I
2
I
4
=
125µA
36µm
1µm
80µm/1µm
80µm/1µm
I
9
36µm/1µm
36µm/1µm
V
Bias
+

2.5V
36µm
36µm/1µm
1µm
80µm/1µm
80µm/1µm
1.3V
2.5V
S02FEP1
Solution
V
OH
and V
OL
can be found from many approaches. The easiest is simply to assume
that V
OH
and V
OL
are 2.5V and –2.5V, respectively. However, no matter what the input,
the values of V
OH
and V
OL
will be in the following range,
(V
DD
2V
ON
)< V
OH
< V
DD
and V
DD
< V
OH
< (V
SS
+2V
ON
)
The reasoning is as follows, suppose V
in
>0. This gives I
1
>I
2
which gives I
6
<I
7
which
gives I
9
<I
7
. V
out
will increase until I
7
equals I
9
. The only way this can happen is for M5
and M7 to leave saturation. The same reasoning holds for V
in
<0.
Therefore assuming that V
OH
and V
OL
are 2.5V and –2.5V, respectively, we get
V
in
(min) =
5V
7464
= 0.67mV → k =
10mV
0.67mV
= 14.93
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 816
Problem 8.302 – Continued
The foldedcascode op amp as a comparator can be modeled by a single dominant pole.
This pole is found as,
p
1
=
1
R
out
C
L
where R
out
≈ g
m9
r
ds9
r
ds11
[g
m7
r
ds7
(r
ds2
r
ds5
)]
g
m9
= 2·75·110·36 =771µS, g
ds9
=g
ds11
=75x10
6
·0.04 = 3µS, g
ds2
=50x10
6
(0.04)=2µS
g
m7
= 2·75·50·80 =775µS, g
ds5
=125x10
6
·0.05 = 6.25µS, g
ds7
=50x10
6
(0.05)=3.75µS
g
m9
r
ds9
r
ds11
= (771µS)
.

}
`
1
3µS
.

}
`
1
3µS
= 85.67MΩ
g
m7
r
ds7
(r
ds2
r
ds5
≈ (775µS)
.

}
`
1
3.75µS
.

}
`
1
2µS

1
6.25µS
= 25.05MΩ ,
R
out
≈ 85.67ΜΩ25.05ΜΩ 19.4ΜΩ
The dominant pole is found as, p
1
=
1
R
out
C
L
=
1
19.4x10
6
5pF
= 10,318 rps
The time constant is τ
1
= 96.9µs.
For a dominant pole system, the step response is, v
out
(t) = A
vd
(1e
t/τ
1
)V
in
The slope is the largest at t = 0. Evaluating this slope gives,
dv
out
dt
=
A
vd
τ
1
e
t/τ
1
V
in
For t = 0, the slope is
A
vd
τ
1
V
in
=
7464
96.9µs
(10mV) = 0.77V/µs
The slew rate of this op amp/comparator is SR =
I
3
C
L
=
100µA
5pF
= 20V/µs
Therefore, the comparator does not slew and its propagation delay time is found from the
linear response as,
t
P
= τ
1
ln
.

}
`
2k
2k1
= 96.9µs·ln
.

}
`
2·14.93
2·14.931
=( 96.9µs)(0.0341) = 3.3µs
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 817
Problem 8.303
Find the open loop gain of Fig. 8.33 if the twostage op amp is the same as Ex. 6.31
without the compensation and W
10
/L
10
= 10(W
8
/L
8
)= 100(W
6
/L
6
), W
9
/L
9
=
(K
P’
/K
N’
)(W
8
/L
8
), W
11
/L
11
= (K
P’
/K
N’
)(W
10
/L
10
) and the quiescent current in M8 and
M9 is 100µA and in M10 and M11 is 500µA. What is the propagation time delay if C
II
=
100pF and the step input is large enough to cause slewing?
Figure 8.33 Increasing the capacitive drive of a twostage, openloop comparator.

+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+

C
II
M8
M9
M10
M11
Solution
From Ex. 6.31, we know that the smallsignal gain to the input of the M8M9 inverter is
7696 V/V. The gain of the M8M9 and M10M11 pushpull inverters are given as,
A
v8,9
= 
g
m8
+ g
m9
g
ds8
+ g
ds9
and A
v10,11
= 
g
m10
+ g
m12
g
ds10
+ g
ds12
Since W
6
/L
6
= 94 then W
8
/L
8
= 940 and W
9
/L
9
= (50/110)940 = 427.
Now, g
m8
= g
m9
= 2·50·940·100 µS = 3,066µS, g
ds8
= 0.04·100µS = 4µS and g
ds9
=
0.05·100µS = 5µS.
∴ A
v8,9
= 
3,066 + 3,066
4+5
= 681.3 V/V
Since W
6
/L
6
= 94W
10
/L
10
= 9400 and W
11
/L
11
= (50/110)9400 = 4270.
Now, g
m10
= g
m12
= 2·50·9400·500 µS = 21.68mS, g
ds10
= 0.04·500µS = 20µS and
g
ds9
= 0.05·500µS = 25µS.
∴ A
v10,11
= 
21.68x2x10
3
20+25
= 963.5 V/V ⇒ Total gain = 7696·681·963 = 5.052x10
9
V/V
t
p
= C
∆V
o
I
where I =
K
P
W
10
2L
10
(V
SG10
V
TP
)
2
= 235x10
3
(50.7)
2
= 4.345A
∴ t
p
= 100x10
12
.

}
`
2.5V
4.345A
= 57.5 x10
12
sec.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 818
Problem 8.304
Fig. P8.34 shows a circuit
called a clamped comparator.
Use the parameters of Table 3.1
2 and calculate the gain of this
comparator. What is the positive
and negative slew rate of this
comparator if the load
capacitance is 5 pF?
Solution
20
7
I
A µ
10
2 1
I I
A µ
5
6 5
I I
A µ
So,
5
4 3
I I
A µ
80
8
I
A µ
The smallsignal voltage gain is
( )
9 8 4
8 2
2
ds ds m
m m
v
g g g
g g
A
+
or,
83
v
A
V/V
The negative slew rate is
SR

= 
I
9
C
L
= 16V/µs
To calculate the positive slew rate
4
’
4
4 8
(max) 2
(min)
S K
I
V V
P
T SG
+
or,
25 . 1
) 2 )( 50 (
) 15 ( 2
7 . 0 (min)
8
+
µ
µ
SG
V
V
So,
242 (max)
8
I
A µ
or, SR
+
=
I
8
(max)
C
L
= 48.4V/µs
V
DD
V
SS
20µA
4
4
M1
M2
M3 M4
M5 M6
M7
M8
M9
M10
M11
1
4
1
4
4
2
4
2
10
2
10
2
64
2
8
2 2
2
2
2
v
1
v
2
v
out
Fig. P8.34
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 819
Problem 8.401
If the comparator used in Fig. 8.41 has a dominant pole at 10
4
radians/sec and a gain of
10
3
, how long does it take C
AZ
to charge to 99% of its final value, V
OS
? What is the final
value that the capacitor, C
AZ
, will charge to if left in the configuration of Fig. 8.41(b) for
a long time?
Solution
The output voltage for the circuit shown can be expressed as,
V
out
(s) = (V
OS
– V
out
(s))
.

}
`
A
v
(0)
1+
s
p
1

This can be solved for the transfer V
out
(s)/V
OS
as follows,
V
out
(s)
V
OS
(s)
=
A
v
(0)
1+
s
p
1

1+
A
v
(0)
1+
s
p
1

=
A
v
(0)
1+ A
v
(0)+
s
p
1

=
A
v
(0)p
1

s +(1+ A
v
(0)) p
1

Assuming V
OS
(s) is a step function then,
V
out
(s) = 
V
OS
s
.

}
`
A
v
(0)p
1

s +(1+ A
v
(0)) p
1

= 
A
v
(0)V
OS
1+A
v
(0)
]
]
1
s

1
s+(1+A
v
(0)p
1
)
Taking the inverse Laplace transform gives,
v
out
(t) = 
A
v
(0)V
OS
1+A
v
(0)
[ ]
1  e
[1+Av(0)]p1t
Let v
out
(t) = 0.99V
OS
and solve for the time T.
v
out
(t) = 0.99V
OS
= 
1000V
OS
1000+1
[1 – e
1001·10
4
T
]
1
1001
1000
·
99
100
= 0.0090 = e
1001·10
4
T
⇒ 110.99 = e
1001·10
4
T
∴ T = 0.9990x10
7
ln(110.99) = 0.47µs
As t → ∞, v
out
(t) → 
1000V
OS
1000+1
= 0.999 V
OS
V
OS
v
OUT
+

C
AZ
S8.41
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 820
Problem 8.402
Use the circuit of Fig. 8.49 and design a hysteresis characteristic that has V
TRP

= 0V and
V
TRP
+
= 1V if V
OH
= 2V and V
OL
= 0V. Let R
1
= 100kΩ.
Solution
Given, V
TRP
+
1 V
V
TRP
−
0 V
V
OH
2 V
V
OL
0 V
and, R
1
100 KΩ
Now, V
R R
R
V
R
R
V
TRP REF OL
+
+ 
.
`
}
−
1 2
2
1
2
or,
R R
R
V
REF
1 2
2
1
+ 
.
`
}
(1)
Also, V
R R
R
V
R
R
V
TRP REF OH
−
+ 
.
`
}
−
1 2
2
1
2
or,
R R
R
V
R
R
REF
1 2
2
1
2
2
+ 
.
`
}
From Equation (1)
R
R
1
2
2 1
or, R R
2 1
2 200 KΩ
and, V
REF
2
3
V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 821
Problem 8.403
Repeat Problem 8.42 for Fig. 8.410.
Solution
Given, V
TRP
+
1 V
V
TRP
−
0 V
V
OH
2 V
V
OL
0 V
and, R
1
100 KΩ
Now, REF OL TRP
V
R R
R
V
R R
R
V
}
`
.

+
+
}
`
.

+
−
2 1
2
2 1
2
or,
0
REF
V
V
Also, REF OH TRP
V
R R
R
V
R R
R
V
}
`
.

+
+
}
`
.

+
+
2 1
2
2 1
2
or, OH TRP
V
R R
R
V
}
`
.

+
+
2 1
2
or,
100
2 1
R R
Ω K
Problem 8.404
Assume that all transistors in Fig. 8.411 are operating in the saturation mode. What is the
gain of the positive feedback loop, M6M7 using the W/L values and currents of Ex. 8.4
2?
Solution
The loopgain in the positive feedback loop can be expressed as
LG
g g
g g g g g g g g
m m
m ds ds ds m ds ds ds
+ + + ( ) + + + ( )
6 7
4 4 2 6 3 1 3 7
Now, S S S S
1 2 6 7
10 , and S S
3 4
2
I
5
20 µA
So, I
3
10
6
µA, and I
6
50
6
µA
And, g
m6
91 3 . µS
g
m7
91 3 . µS
g
m3
18 3 . µS
g
m4
18 3 . µS
So, LG = 22.6
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 822
Problem 8.405
Repeat Ex. 8.41 to design V
TRP
+
=  V
TRP

= 0.5V.
Solution
Given,
5 . 0
+
TRP
V
V
5 . 0 −
−
TRP
V
V
2
OH
V
V
2 −
OL
V
V
Now, REF OL TRP
V
R R
R
V
R R
R
V
}
`
.

+
+
}
`
.

+
−
2 1
2
2 1
2
or, REF
V
R R
R
R R
R
}
`
.

+
+ −
}
`
.

+
−
2 1
2
2 1
2
) 2 ( 5 . 0
(1)
Also, REF OH TRP
V
R R
R
V
R R
R
V
}
`
.

+
+
}
`
.

+
+
2 1
2
2 1
2
or, REF
V
R R
R
R R
R
}
`
.

+
+
}
`
.

+
2 1
2
2 1
2
) 2 ( 5 . 0
(2)
Solving Equations (1) and (2), we get
2 1
3R R
, and
0
REF
V
V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 823
Problem 8.406
Repeat Ex. 8.42 if i
5
= 50µA. Confirm using a simulator.
Solution
50
5
I
A µ
5
2 1
S S
,
10
7 6
S S
, and
2
4 3
S S
To calculate the positive trip point
33 . 8
6
50
3
I
A µ
67 . 41 33 . 8 50
1 5 2
− − I I I
A µ
874 . 0
2
1
’
1
1 1
+
S K
I
V V
N
T GS V
089 . 1
2
2
’
2
2 2
+
S K
I
V V
N
T GS V
or, V
+
TRP
= V
GS2
– V
GS1
= 0.215V
Based on a similar analysis, the negative trip point will be
33 . 8
6
50
4
I
A µ
67 . 41
1
I
A µ
874 . 0
2
GS
V
V
089 . 1
1
GS
V
V
V

TRP
= V
GS2
– V
GS1
= 0.215V
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 824
Problem 8.501
List the advantages and disadvantages of the switched capacitor comparator of Fig. 8.51
over an openloop comparator having the same gain and frequency response.
Solution
Advantages Disadvantages
Fig. 8.51
Can remove input offset voltage
Positive terminal on ground
eliminates need for good ICMR
Requires switches
Charge feedthrough
Must be stable in autozero mode
Openloop
Comparator
Stability not of concern
Continuous time operation
Requires good ICMR
Can’t remove input offset voltage
Problem 8.502
If the current and W/L values of the two latches in Fig. 8.53 are identical, which latch will
be faster? Why?
Solution
The closed loop gain of the NMOS latch can be given by
( )
2
’
2
2
N
N
ds
m
vn
I
L W K
g
g
A
λ
}
`
.

The closed loop gain of the PMOS latch can be given by
( )
2
’
2
2
P
P
ds
m
vp
I
L W K
g
g
A
λ
}
`
.

It can be seen that
4375 . 3
vp
vn
A
A
Thus, the NMOS latch would be faster (as it has larger smallsignal loop gain).
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 825
Problem 8.503
Repeat Ex. 8.51 if ∆V
out
= 0.5V(V
OH
V
OL
).
Solution
The propagation delay of the latch can be expressed as
}
`
.

∆
∆
in
out
L p
V
V
t ln τ
where,
108
L
τ
ns
or,
}
`
.

∆
−
in
OL OH
L p
V
V V
t
2
ln τ
When
) ( 01 . 0
OL OH in
V V V − ∆
t
p
= τ
L
ln
.

}
`
V
OH
 V
OL
2∆V
in
= 422 ns
When
) ( 1 . 0
OL OH in
V V V − ∆
t
p
= τ
L
ln
.

}
`
V
OH
 V
OL
2∆V
in
= 174 ns
Problem 8.504
Repeat Ex. 8.51 if the dc latch current is 50µA.
Solution
332
m
g
S µ
2
ds
g
S µ
So, the latch gain is
166
v
A
V/V
The latch time constant is given by
48
2
67 . 0
’
3
I K
WL
C
N
ox L
τ
ns
When,
) ( 01 . 0
OL OH in
V V V −
t
p
= τ
L
ln
.

}
`
V
OH
 V
OL
2∆V
in
= 188 ns
When,
) ( 1 . 0
OL OH in
V V V −
t
p
= τ
L
ln
.

}
`
V
OH
 V
OL
2∆V
in
= 76.8 ns
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 826
Problem 8.505
Redevelop the expression for ∆V
out
/∆V
i
for the
circuit of Fig. P8.55 where ∆v
out
= v
o2
 v
o1
and
∆V
i
= v
i1
 v
i2
.
Solution
Referring to the figure and applying nodal
analysis
0
1 3 2 3 1 1 1 1
+ + +
o ds o m o ds i m
v g v g v g v g
or,
( ) 0
2 3 1 3 1 1 1
+ + +
o m o ds ds i m
v g v g g v g
(1)
Similarly, applying nodal analysis
( ) 0
1 4 2 4 2 2 2
+ + +
o m o ds ds i m
v g v g g v g
(2)
Subtracting Equation (2) from Equation (1), we get
( ) ( )( )
1 2 3 1 3 2 1 1 o o ds ds m i i m
v v g g g v v g − + + − −
or,
( )
( ) ( )
3 1 3
1
2 1
1 2
ds ds m
m
i i
o o
g g g
g
v v
v v
+ + −
−
−
Problem 8.506
Compare the dynamic latch of Fig. 8.58 with the NMOS and PMOS latches of Fig. 8.53.
Solution
Advantages Disadvantages
Fig. 8.53 Work with smaller power supply Class A output – can’t source and
sink with the same currentslow
Fig. 8.58 Pushpull is good for sinking and
sourcing a lot of current fast
Needs larger power supply
V
DD
M3
M4
M1 M2
v
i1 v
i2
v
o1 v
o2
I
Bias
Figure P8.55
rds
3
g
m
3
v
o2
g
m
1
v
i
1
g
m
2
v
i2
rds
2 rds
1 v
i1
v
o1 v
o2
g
m
4
v
o1 rds
4
v
i2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 827
Problem 8.507
Use the worst case values of the transistor parameters in Table 3.12 and calculate the
worst case voltage offset for the NMOS latch of Fig. 8.53(a).
Solution
The offset voltage can be expressed as
2 2 1 1 1 2 dsat T dsat T o o OS
V V V V V V V − − + −
or,
]
]
]
]
− + ∆
2
’
2
2
1
’
1
1
2 2
2
S K
I
S K
I
V V
T OS
Assuming,
10
2 1
I I
A µ
, and
10
2 1
S S
]
]
]
− +
) 10 )( 110 ( 1 . 1
) 10 ( 2
) 10 )( 110 ( 9 . 0
) 10 ( 2
) 15 . 0 ( 2
µ
µ
µ
µ
OS
V
or,
314 . 0
OS
V
V
Problem 8.601
Assume an op amp has a low frequency gain of 1000 V/V and a dominant pole at 10
4
radians/sec. Compare the 3dB bandwidths of the configurations in Fig. P8.61(a) and (b)
using this op amp.
Solution
Given,
1000 ) 0 (
v
A
, and
10
1
p
Krad/s
Thus, the gainbandwidth frequency is
10 ) 0 (
1
p A GB
v Mrad/s
a) The closedloop gain is (25). Thus, the –3 dB bandwidth becomes
400
25
3
−
GB
dB
ω
Krad/s
b) The closedloop gain of each gain stage is (5). Thus, the –3 dB bandwidth
becomes
2000
5
3
−
GB
dB
ω
Krad/s
There would be two poles at 2 Mrad/s at the output; each being created by a single
gain stage.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 828
Problem 8.602
What is the gain and 3dB bandwidth (in Hz) of Fig.
P8.62 if C
L
= 1pF? Ignore reverse bias voltage
effects on the pn junctions and assume the bulk
source and bulkdrain areas are given by W x5µm.
Solution
6 . 6
3
’
1
’
3
1
S K
S K
g
g
A
P
N
m
m
v
V/V
The singleended output resistance is
R
g
o
m
1
14 14
3
. KΩ
The pole frequency at the output is given by
p
R C C C C C
o L gs bd gd bd
1
3 3 1 1
1
2
−
+ + + +
( )
or, p
R C C
o L bd
1
1
1
2
≅ −
+ ( )
or, p
1
5 15 − . MHz → f
3dB
= 5.15 MHz
C
L
v
out
v
in
M3 M4
M1 M2
50µA
3V
2
1
40
2
1
1
40
1 +

+ 
Fig. P8.62
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 829
Problem 8.603
What is the gain and 3dB bandwidth (in Hz) of Fig. P8.63 if C
L
= 1pF? Ignore reverse
bias voltage effects on the pn junctions and assume the bulksource and bulkdrain areas
are given by W x5µm. The W/L ratios for M1 and M2 are 10µm/1µm and for the
remaining PMOS transistors the W/L ratios are all 2µm/1µm.
3V
M1 M2
M3 M4
M5 M6
M7
M8
20µA
50µA
20µA
C
L

v
out
+
v
in
+

Fig. P8.63
Solution
A smallsignal model which
can be used to solve this
problem is shown.
The voltage gain and the
–3dB bandwidth can be
expressed as,
v
out
v
in
= g
m
R
o
and ω
3dB
=
1
(C
L
+0.5C
o
)2R
o
The various values in the above relationships are:
g
m
= 2·K
N
(W
1
/L
1
)I
D1
= 2·110·10·25 µS = 234.5µS
R
o
≈
1
g
m3
r
ds1
r
ds3
r
ds5
, g
m3
= 2·K
P
(W
1
/L
1
)I
D3
= 2·50·2·5 µS = 31.62µS
r
ds1
=
1
0.04·25µA
= 1MΩ, r
ds3
=
1
0.05·5µA
= 4MΩ and r
ds5
=
1
0.04·20µA
= 0.8MΩ
∴ R
o
= 31.623kΩ1MΩ4MΩ0.8MΩ= 29.31kΩ
C
o
≈ C
gs3
+C
bd1
+C
bd3
+C
bd5
C
gs3
= CGSO·W
5
+0.67·C
ox
·W
5
·L
5
= 220x10
12
F/m·2x10
6
m+0.67·24.7x10
4
F/m
2
·2x10
12
m
2
= 3.73fF
C
bd1
= CJ·AS+CJSW·PS =770x10
6
F/m
2
·50x10
12
m
2
+ 380x10
12
F/m·30x10
6
m
= 38.5fF + 11.4fF = 49.9fF
C
bd3
=C
bd5
= 560x10
6
F/m
2
·10x10
12
m
2
+ 350x10
12
F/m·14x10
6
m = 10.5fF
∴ C
o
=74.6fF → ω
3dB
=
1
(1.073pF)58.62kΩ
=16.445x10
6
rads/sec
Finally, f
3dB
= 2.62MHz and A
v
= 6.873V/V
C
L
 +
v
out
g
m
v
in
2
g
m
v
in
2
C
o
R
o
R
o
C
o
S8.63
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 830
Problem 8.604
Assume that a comparator consists of an amplifier cascaded with a latch. Assume the
amplifier has a gain of 5V/V and a 3dB bandwidth of 1/τ
L
, where τ
L
is the latch time
constant and is equal to 10ns. Find the propagation time delay for the overall configuration
if the applied input voltage is 0.05(V
OH
V
OL
) and the voltage applied to the latch from the
amplifier is (a) ∆V
i
= 0.05(V
OH
V
OL
), (b) ∆V
i
= 0.1(V
OH
V
OL
), (c) ∆V
i
= 0.15(V
OH

V
OL
) and (d) ∆V
i
= 0.2(V
OH
V
OL
). Assume that the latch is enabled as soon as the output
of the amplifier is equal to 0.05(V
OH
V
OL
). From your results, what value of ∆V
i
would
give minimum propagation time delay?
Solution
The transfer function of the amplifier is A
v
(s) =
A
v
(0)
sτ
L
+1
The output voltage of the amplifier is v
o
(t) = A
v
(0)[1e
t/τL
]∆V
i
Let ∆V
i
= x·(V
OH
V
OL
), therefore the delay of the amplifier can be found as
x(V
OH
V
OL
) = A
v
(0)[1e
t1/τL
]0.05(V
OH
V
OL
) = 5[1e
t1/τL
]0.05(V
OH
V
OL
)
or
x = 0.25[1e
t1/τL
] → t
1
= τ
L
ln
.

}
`
1
14x
The delay of the latch can be found as
t
2
= τ
L
ln
.

}
`
V
OH
V
OL
2x(V
OH
V
OL
)
= τ
L
ln
.

}
`
1
2x
The propagation time delay of the comparator can be expressed in terms of x as,
t
p
= t
1
+t
2
= τ
L
ln
.

}
`
1
14x
+ τ
L
ln
.

}
`
1
2x
= τ
L
ln
.

}
`
1
2x8x
2
Thus,
x = 0.05 = 1/20 ⇒ τ
p
= t
1
+ t
2
= 2.23ns+2.30ns = 25.26ns
x = 0.1 = 1/10 ⇒ τ
p
= t
1
+ t
2
= 5.11ns+16.09ns = 21.20ns
x = 0.15 ⇒ τ
p
= t
1
+ t
2
= 9.16ns+12.04ns = 21.20ns
x = 0.2 = 1/5 ⇒ τ
p
= t
1
+ t
2
= 16.09ns+9.16ns = 25.26ns
Note that differentiating t
p
with respect to x and setting to zero gives
x
min
= 1/8 = 0.125
Therefore, minimum delay of 20.08ns is achieved when x = 1/8.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 831
Problem 8.6 05
Assume that a comparator consists of two identical amplifiers cascaded with a latch.
Assume the amplifier has the characteristics given in the previous problem. What would be
the normalized propagation time delay if the applied input voltage is 0.05(V
OH
V
OL
) and
the voltage applied to the latch is ∆V
i
= 0.1(V
OH
V
OL
)?
Solution
The transfer function of the amplifiers is A
v
(s) =
.

}
`
A
v
(0)
sτ
L
+1
2
=
.

}
`
5
sτ
L
+1
2
The output voltage of the amplifiers is
V
o
(s) =
25
τ
L
2
(s +1/τ
L
)
2
·
0.05(V
OH
V
OL
)
s
=
1.25(V
OH
V
OL
)
τ
L
2
]
]
]
a
s
+
b
s+(1/τ
L
)
+
c
(s+(1/τ
L
))
2
or H(s) =
1
s(s+(1/τ
L
))
2
=
a
s
+
b
s+(1/τ
L
)
+
c
(s+(1/τ
L
))
2
Solving for a, b, and c, by partial fraction expansion gives
a = sH(s)

s=0
= τ
L
2
, c = [s+(1/τ
L
)]
2
·H(s)

s=1/τ
L
= τ
L
and
d
da
]
]
1
s
= a[s+(1/τ
L
)]
2
+ b[s+(1/τ
L
)] + c ⇒ 
1
s
2
= 2a[s+(1/τ
L
)] + b
∴ Let s=1/τ
L
to get b = τ
L
2
V
o
(s) = 1.25(V
OH
V
OL
)
]
]
]
1
s

1
s+(1/τ
L
)

τ
L
[s+(1/τ
L
)]
2
Taking the inverse Laplace transform gives,
v
o
(t) = 1.25(V
OH
V
OL
)
]
]
]
1 e
t/τL

t
τ
L
e
t/τL
Setting v
o
(t) = 0.05(V
OH
V
OL
) and solving for the amplifier delay, t
1
, gives
t
1
τ
L
= ln
]
]
]
1.25
1.2
+
1. 25
1.2
t
1
τ
L
= ln
]
]
]
1.041667
.

}
`
1+
t
1
τ
L
Solving iteratively gives t
1
/τ
L
= 0.313 ⇒ t
1
= 3.13ns
The latch delay time, t
2
is found as
t
2
= τ
L
ln
.

}
`
V
OH
V
OL
2x0.1(V
OH
V
OL
)
= 10ns ln(5) = 16.095ns
∴ t
comparator
= t
1
+ t
2
= 19.226ns
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 832
Problem 8.606
Repeat Problem 5 if there are three identical amplifiers cascaded with a latch. What would
be the normalized propagation time delay if the applied input voltage is 0.05(V
OH
V
OL
) and
the voltage applied to the latch is ∆V
i
= 0.2(V
OH
V
OL
)?
Solution
The combined transfer function of the three, cascaded amplifier stage can be given as
A s
A
s
p
v
v
( )
+

.
`
}
3
3
1
In response to a step input, the output response of the three, cascaded amplifier stages can
be approximated as
v t A v e
oa v in
t
L
( ) − ( )
− 3
1 3
τ
The normalized propagation delay of the three, cascaded amplifier stages can be given by
t
v
A v
p
oa
v in
1
3
3
1
'
ln
−

.
`
}
The normalized propagation delay of the latch can be given by
t
V V
v
p
OH OL
oa
2
2
'
ln
− 
.
`
}
When v V V
in OH OL
− ( ) 0 05 . , and v V V
oa OH OL
− ( ) 0 1 . , the total normalized propagation
delay is
t t t
p p p
' ' '
. . . + +
1 2
1 115 1 609 2 724
When v V V
in OH OL
− ( ) 0 05 . , and v V V
oa OH OL
− ( ) 0 2 . , the total normalized propagation
delay is
t t t
p p p
' ' '
. . . + +
1 2
1 131 0 916 2 047
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 833
Problem 8.607
A comparator consists of an amplifier cascaded with a latch as shown in Figure P8.67.
The amplifier has a voltage gain of 10 V/V and f
3dB
= 100 MHz and the latch has a time
constant of 10 ns. The maximum and minimum voltage swings of the amplifier and latch
are V
OH
and V
OL
. When should the latch be enabled after the application of a step input
to the amplifier of 0.05(V
OH
– V
OL
) to get minimum overall propagation time delay? What
is the value of the minimum propagation time delay? It may be useful to recall that the
propagation time delay of the latch is given as t
p
= τ
L
ln
.

}
`
V
OH
– V
OL
2v
il
where v
il
is the
latch input (∆V
i
of the text).
v
in
= 0.05(V
OH
V
OL
)
v
out
Amplifier
A
v
(0)=10V/V
f
3dB
=100MHz
Latch
τ
L
=10ns
Comparator
v
oa
v
il
Enable
t=0
S02FEP2
Solution
The solution is based on the figure shown.
We note that,
v
oa
(t) = 10[1e
ω3dBt
]0.05(V
OH
V
OL
).
If we define the input voltage to the latch as,
v
il
= x·(V
OH
V
OL
)
then we can solve for t
1
and t
2
as follows:
x·(V
OH
V
OL
) = 10[1e
ω3dBt1
]0.05(V
OH
V
OL
) → x = 0.5[1e
ω3dBt1
]
This gives,
t
1
=
1
ω
3dB
ln
.

}
`
1
12x
From the propagation time delay of the latch we get,
t
2
= τ
L
ln
.

}
`
V
OH
V
OL
2v
il
= τ
L
ln
.

}
`
1
2x
∴ t
p
= t
1
+ t
2
=
1
ω
3dB
ln
.

}
`
1
12x
+ τ
L
ln
.

}
`
1
2x
→
dt
p
dx
0 gives x =
π
1+2π
= 0.4313
t
1
=
10ns
2π
ln (1+2π) = 1.592ns·1.9856 = 3.16ns and t
2
= 10ns ln
.

}
` 1+2π
2π
= 1.477ns
∴ t
p
= t
1
+ t
2
= 3.16ns + 1.477ns = 4.637ns
V
OH
V
OL
Amplifier
Latch
t
1
x(V
OH
V
OL
)
t
2
t
S01E3S1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 91
CHAPTER 9 – HOMEWORK SOLUTIONS
Problem 9.101
Develop the equivalent resistance expression in Table 9.11 for the series switched
capacitor resistor emulation circuit.
Solution
The series switched capacitor is shown for reference purposes.
The average current flowing into the lefthand port can be
written as,
i
1
(average) =
1
T
⌡
⌠
0
T
i
1
(t)dt =
1
T
.

}
`
⌡
⌠
0
T/2
i
1
(t)dt + ⌡
⌠
T/2
T
i
1
(t)dt
or in terms of charge,
i
1
(average) =
1
T
⌡
⌠
0
T/2
dq
1
(t) +
1
T
⌡
⌠
T/2
T
dq
1
(t) =
q
1
(T)  q
1
(T/2)
T
By following through the sequence of switching, we see that,
q
1
(T/2) = 0 and q
1
(T) = C[v
1
(T) – v
2
(T)]
∴ i
1
(average) =
C[v
1
(T) – v
2
(T)]
T
≈
C[V
1
– V
2
]
T
The average current of a series resistance, R, can be expressed as
i
1
(average) =
[V
1
– V
2
]
R
Equating the average currents gives
R =
T
C
v (t)
1
v (t)
2
1 2
C
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 92
Problem 9.102
Develop the equivalent resistance expression for the bilinear switched capacitor
resistor equivalent circuit shown below assuming that the clock frequency is much larger
than the frequency of the signal.
1
v (t) v (t)
2
1 2
C
1 2
Solution
φ
1
phase, 0<t<0.5T: φ
2
phase, 0.5T<t<T:
i
Av
=
1
T
⌡
⌠
0
T
i(t)dt =
2
T
⌡
⌠
0.5T
T
i(t)dt =
2
T
⌡
⌠
0.5T
T
dq(t) =
2
T
2C(v
1
v
2
) =
4C
T
(v
1
v
2
)
∴ R
eq
=
(v
1
v
2
)
i
Av
=
T
4C
⇒ R
eq
=
T
4C
Problem 9.103
What is the accuracy of a time constant implemented with a resistor and capacitor having a
tolerance of 10% and 5%, respectively. What is the accuracy of a time constant
implemented by a switched capacitor resistor emulation and a capacitor if the tolerances of
the capacitors are 5% and the relative tolerance is 0.5%. Assume that the clock frequency
is perfectly accurate.
Solution
Continuous time accuracy:
dτ
C
τ
C
=
dR
1
R
1
+
dC
2
C
2
= 10%+5% = 15%
Discretetime accuracy:
dτ
D
τ
D
=
dC
2
C
2

dC
1
C
1

df
c
f
c
= 0.5%
+
v
1
v
2


+
v
2
v
1

+
+
v
1
v
2


+
v
2
v
1

+
S00H6P1B
C C
v
1
v
2
+
v
1
v
2


+
v
2
v
1

+
S00H6P1A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 93
Problem 9.104
Repeat Example 9.13 using a series switched capacitor resistor emulation.
Solution
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 94
Problem 9.105
Find the zdomain transfer function for the circuit shown in Fig. 9.1
5. Let α = C
2
/C
1
and find an expression for the discrete time
frequency response following the methods of Ex. 9.14. Design (find
α) a firstorder, highpass circuit having a 3dB frequency of 1kHz
following the methods of Ex. 9.15. Assume that the clock
frequency is 100kHz. Plot the frequency response for the resulting
discrete time circuit and compare with a firstorder, highpass,
continuous time circuit.
Solution
φ
1
φ
2
C
1
C
2
+

v
in
+

v
out
Figure P9.15
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 95
Problem 9.201
Fig. P9.21 shows two inverting summing amplifiers. Compare the closedloop frequency
response of these two summing amplifiers if the op amp is modeled by A
vd
(0) = 10,000
and GB = 1MHz.
+

R R
R
v
1
v
2
v
o
(a.)
+

R R
R
v
1
v
2
v
o
R
v
3
(b.)
Figure P9.21 (a.) 2input inverting summer. (b.) 3input inverting summer.
Solution
A model for calculating the closedloop frequency response is shown.
Solving for the output voltage,
V
out
= A
.

}
`
R
(n+2)R
V
out
+
R
(n+2)R
V
1
V
out
.

}
`
1+
AR
(n+2)R
= 
AR
(n+2)R
V
1
∴
V
out
V
1
=

A
(n+2)
1+
A
n+2
=

1
n+2
1
A
+
1
n+2
We know that A(s) =
A
vd
(0)
1+
s
ω
a
≈
A
vd
(0)ω
a
s
=
GB
s
Substituting gives,
V
out
V
1
=

1
n+2
s
GB
+
1
n+2
=

GB
n+2
s +
GB
n+2n
= A
o
ω
3dB
s + ω
3dB
∴ ω
3dB
=
GB
n+2
and A
o
= 1
For n = 1, f
3dB
= GB /3 = 0.33MHz and for n = 2, f
3dB
= GB /4 = 0.250MHz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 96
Problem 9.202
Two switchedcapacitor summing amplifiers are shown. Find the value of the –3dB
frequency of the closedloop frequency response, v
o
/v
1
, with the remaining inputs shorted,
of these two summing amplifiers if the op amp is modeled by A
vd
(0) = 10,000 and GB =
1MHz.
+

C
C
C
v
1
v
2
v
o
+

C
C
C
v
1
v
2
v
o
C
v
3
S02E2P3A
Solution
A model for calculating the closedloop frequency response is
shown.
Solving for the output voltage,
V
out
= A
.

}
`
C
(n+2)C
V
out
+
C
(n+2)C
V
1
V
out
.

}
`
1+
AC
(n+2)C
= 
AC
(n+2)C
V
1
∴
V
out
V
1
=

A
(n+2)
1+
A
n+2
=

1
n+2
1
A
+
1
n+2
We know that A(s) =
A
vd
(0)
1+
s
ω
a
≈
A
vd
(0)ω
a
s
=
GB
s
Substituting gives,
V
out
V
1
=

1
n+2
s
GB
+
1
n+2
=

GB
n+2
s +
GB
n+2n
= A
o
ω
3dB
s + ω
3dB
∴ ω
3dB
=
GB
n+2
and A
o
= 1
For n = 1, f
3dB
= GB /3 = 0.33MHz and for n = 2, f
3dB
= GB /4 = 0.250MHz
V
1
V
out
C
nC
C
+

V
i
A
v
V
i
S02E2S3
n = 1 or 2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 97
Problem 9.203
Find the zdomain transfer function for H
ee
(z) for
the switched capacitor circuit shown.
Solution
In phase φ
2
, the circuit is simply a charge
amplifier whose transfer function is given as
H
ee
(z) =
V
e
out
(z)
V
e
in
(z)
= 
C
1
C
2
Problem 9.204
Verify the transresistance of Fig. 9.26a.
Solution
Positive transresistance realization:
R
T
=
v
1
(t)
i
2
(t)
=
v
1
i
2
(average)
If we assume v
1
(t) is ≈ constant over one period of the clock, then we can write
i
2
(average) =
1
T
⌡
⌠
T/2
T
i
2
(t)dt =
q
2
(T)  q
2
(T/2)
T
=
Cv
C
(T)  Cv
C
(T/2)
T
=
Cv
1
T
Substituting this expression into the one above shows that R
T
= T/ C
v
out
v
in
C
2
+

C
1
φ
1
φ
1
φ
2
S02E2P3
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 98
Problem 9.205
The switched capacitor circuit shown
uses a twophase, nonoverlapping
clock. (1.) Find the zdomain
expression for H
oe
(z). (2.) If C
1
=
10C
2
, plot the magnitude and phase
response of the switched capacitor
circuit from 0 Hz to the clock frequency
(f
c
). Assume that the op amp is ideal
for this problem.
Solution
(1.) This circuit is a noninverting
amplifier with a minimum number of
switches.
φ
1
: t = ( n 1)T
v
o
C1
(n1) = v
o
in
(n1) and v
o
C2
(n1) = 0
φ
2
: t = ( n 0.5)T
v
e
out
(n0.5) = 
C
1
C
2
]
]
v
o
in
(n1) =
C
1
C
2
v
o
in
(n1)
∴ V
e
out
(z) =
C
1
C
2
z
1/2
v
o
in
(z) → H
oe
(z) =
C
1
C
2
z
1/2
= 10 z
1/2
(2.) H
oe
(e
jωT
) = 10e
jωT/2
= 10e
j2πf/2f
c
= 10e
jπf/f
c
Plotting this transfer function gives,
H
oe
(e
jwT
)
10
5
0
0
f
c
/2
f
c
f
f
Phase of
H
oe
(e
jwT
)
0°
90°
180°
Fig. S9.205

+
+

v
in
v
out
φ
1
φ
1
φ
1
φ
2
φ
2
φ
2
C
2
C
1
φ2 φ2 φ2 φ1 φ1 φ1
n
3
2
n
1
2
n+
1
2
n+
3
2
n+1 n1
n
t
T
Figure P9.25
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 99
Problem 9.206
Find H
oe
(z) (=V
out
e
(z)/V
in
o
(z)) of the switched capacitor
circuit shown in Fig. P9.26. Replace z by e
jωT
and
identify the magnitude and phase response of this
circuit. Assume C
1
= C
2
. Sketch the magnitude and
phase response on a linearlinear plot from f=0 to f=f
c
.
What is the magnitude and phase at f = 0.5f
c
?
Solution
φ
1
, t=(n1)T: φ
2
, t=(n0.5)T:
Circuit: Circuit:
Writing the output,
v
out
e
(n0.5)) = v
out
e
(n1.5)) +
C
1
C
2
v
in
o
(n1)) → V
out
e
(z)) = z
1
V
out
e
(z) +
C
1
C
2
z
0.5
V
in
o
(z))
∴ H
oe
(z) =
V
out
e
(z)
V
in
o
(z)
=
(C
1
/C
2
)z
0.5
1z
1
Replacing z by e
jωT
gives H
oe
(e
jωT
) =
(C
1
/C
2
)e
jωT/2
1e
jωT
x
e
jωT/2
e
jωT/ 2
=
(C
1
/C
2
)
e
jωT/2
e
jωT
H
oe
(e
jωT
) =
(C
1
/C
2
)
2jsin(ωT/2)
x
ωΤ
ωΤ
=
C
1
jωC
2
f
ωΤ/2
sin(ωΤ/2)
(note there is no phase error)
If C
1
= C
2
, then H
oe
(e
jωT
) =
f
c
j2πf
πf/f
c
sin(πf/f
c
)
Sketch of frequency response:
f/f
c

H
oe
(e
j2πf/fc
)
1/2π
1
0.5 0.5
10.5π
1
Phase shift is a constant
90°.
+

φ
1
C
2
φ
1 φ
2
φ
2
C
1
v
out
v
in
n
3
2
n
1
2
n+
1
2
n1 n n+1
t
T
Figure P9.26
φ
1
φ
1
φ
2
φ
2
φ
2
+

C
2
C
1
3
2
v
in
(n1)T
S01E2S4B
o
v
out
(n )T
e
v
out
(n )T
e
1
2
+

C
2
C
1
3
2
v
in
(n1)T
S01E2S4A
o
v
in
(n1)T
o
v
out
(n )T
e
+ 
+ 
v
out
(n1)T
o
1.0
0.5
0
f
f
c
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
1
2π
1
2π
H
oe
(e
jwT
)
S01E2S4C
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 910
Problem 9.207
(a.) Find H
oo
(z) for the switched
capacitor circuit shown. Ignore the fact
that the op amp is open loop during the
φ
1
phase and assume that the output is
sampled during φ
2
and held during φ
1
.
Note that some switches are shared
between the two switched capacitors.
(b.) Sketch the magnitude and phase of
the sampled data frequency response
from 0 to the clock frequency in Hertz.
Solution:
φ
1
(n0.5):
During this phase, the 10C capacitor is charged to v
in
o
(n0.5) and the output is sampled
and held.
φ
2
(n):
Model for calculating v
out
e
(n),
∴ v
out
e
(n) = 10v
in
o
(n0.5)
Since the output is sampled and held during the
next phase period, we can write
v
out
o
(n+0.5) = v
out
e
(n) = 10v
in
o
(n0.5) → V
out
o
(z) = 10z
1
V
in
o
(z)
or H
oo
(z) = 10z
1
b.)
0 f
c
f
10
0
Magnitude
0 f
c
f
0°
360°
Phase
F97E2S5A
+

φ
1
φ
1
φ
2
φ
2
φ
1
φ
2
C
10C
v
in
v
out
t/T
n1.5 n1 n0.5 n n+0.5
φ
2
φ
1
φ
2
φ
1
F97E2P5
+

10C C v
out
(n)
e
v
in
(n0.5)
o
F97E2S5
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 911
Problem 9.208
In the circuit shown, the capacitor C
1
has been
charged to a voltage of V
in
(v
in
>0). Assuming
that C
2
is uncharged, find an expression for the
output voltage, V
out
, after the φ
1
clock is
applied. Assume that rise and fall times of the φ
1
clock are slow enough so that the channel of the
NMOS transistor switch tracks the gate voltage.
The on and off voltages of φ
1
are 10V and 0V,
respectively. Evaluate the dc offset at the output
if the various parameters for this problem are V
T
= 1V, C
gs
= C
gd
= 100fF, C
1
= 5pF, and C
2
= 1pF.
Solution
Since the problem does not give the value of V
in
or the slope of the gate voltage, we shall
assume that the contribution to the feedthrough due to the channel can be neglected.
Therefore, the output voltage after the switch opens up can be expressed as,
V
o
= 
C
1
C
2
V
in

.

}
`
C
gd
C
gd
+ C
1
(V
T
) = 5V
in

1
11
= 5V
in

1
11
The dc offset is 1/11V or 91mV .
A closer look at the problem reveals
that there will also be feedthrough during the
turnon part of the φ
1
clock which should be
considered. However, if we are going to
consider this then we should also consider
how C
1
was charged. It is most likely the
complete circuit looks like the one shown.
When φ
2
is turned off, the voltage
across C
1
is,
V
C1
(φ
2
off) = V
in

.

}
`
C
gd
C
gd
+ C
1
(V
in
+V
T
) = V
in

1
11
V
in

1
11
When φ
1
turns on, the voltage across C
1
is,
V
C1
(φ
1
on) = V
C1
(φ
2
off) +
.

}
`
C
gd
C
gd
+ C
1
(V
T
) = V
in

1
11
V
in

1
11
+
1
11
= V
in

1
11
V
in
Finally, when φ
1
turns off, the voltage across C
1
is,
V
C1
(φ
1
off) = 5V
C1
(φ
1
on) 
.

}
`
C
gd
C
gd
+ C
1
(V
T
) = 5V
in

5
11
V
in

1
11
= 
51
11
V
in

1
11
The dc offset is still the same as above.
+

+

V
O
φ
1
C
2
C
1
V
in
Figure P9.28
+

φ
2
φ
1
C
1
C
2
V
in
V
o
Fig. S9.208
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 912
Problem 9.209
A switchedcapacitor amplifier
is shown. What is the
maximum clock frequency that
would permit the ideal output
voltage to be reached to within
1% if the op amp has a dc gain
of 10,000 and a single dominant
pole at 100 rads/sec.? Assume
ideal switches.
Solution
Model at t=0
+
for the φ
2
phase:
where A =
10
4
s
100
+1
≈
10
6
s
if ω >> 100.
V
o
(s) = AV
i
(s) = A
]
]
+
V
1
(s)
2

V
o
(s)
2
→ V
o
(s)
]
]
1+
A
2
=
A
2
V
1
(a)
∴ V
o
(s) =
A
2
1+
A
2
V
1
(a) =
1
2
1
A
+
1
2
V
1
(a) ≈
1
2
s
10
6
+
1
2
V
1
(a) =
0.5x10
6
s+0.5x10
6
V
1
(a)
v
o
(t) = L
1
]
]
] 0.5x10
6
s+0.5x10
6
·
V
1
s
=
A
s
+
B
s+0.5x10
6
A =
0.5x10
6
s+0.5x10
6
V
1

s=0
= V
1
and
B =
0.5x10
6
s
V
1

s=0.5x10
6
= V
1
∴ v
o
(t) = V
1
[1e
0.5x10
6
t
]
Let t = T correspond to v
o
(T) = 0.99V
1
∴ 0.99V
1
= V
1
[1e
0.5x10
6
T
] → 100 = e
0.5x10
6
T
ln(100) = 0.5x10
6
T → T = 2x10
6
ln(100) = 9.21µs
Assuming a square wave, T would be half the period so the minimum clock frequency
would be
f
clock
(min) =
2
T
= 54.287kHz
+

φ
1
φ
1
φ
2
φ
2 v
1
(t)v
1
(t)
v
2
(t)
cCCCC C
φ
1
Figure P9.29
v
1
(t)
φ
v
2
(t) C
C
+

v
i
Av
i
v
1
C C
+

v
o
S9.212
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 913
Problem 9.210
The switched capacitor circuit in Fig. 9.29 is an amplifier that avoids shorting the output
of the op amp to ground during the φ
1
phase period. Use the clock scheme shown along
with the timing and find the zdomain transfer function, H
oo
(z). Sketch the magnitude and
phase shift of this amplifier from zero frequency to the clock frequency, f
c
.
+

φ
1
φ
2
C
2
C
2
φ
1
φ
1
φ
2
φ
2
C
1
v
out
v
in
n
3
2
n
1
2
n+
1
2
n1 n n+1
t
T
Fig. P9.213
Solution
φ
1
: ( n 1) ≤ t / T < ( n 0.5)
v
o
c1
(n1) = v
o
in
(n1) and v
o
c2
(n1) = v
o
out
(n1)
φ
2
: ( n 0.5) ≤ t / T < ( n )
v
e
out
(n0.5) = v
o
out
(n1) +
C
1
C
2
v
o
in
(n1) 
C
2
C
2
v
o
out
(n1)
or
v
e
out
(n0.5) =
C
1
C
2
v
o
in
(n1)
φ
1
: ( n ) ≤ t / T < ( n +0.5)
v
o
out
(n) = v
e
out
(n1) =
C
1
C
2
v
o
in
(n1) → V
o
out
(z) =z
1
C
1
C
2
V
o
in
(z) → H
oo
(z) =
C
1
C
2
z
 1
Substitituting z
1
by e
jωT
gives
H
oo
(e
jωT
) =
C
1
C
2
e
jωT
The magnitude and phase response is given below.
0
0
f
c
f
Magnitude
C
1
/C
2 0
0
f
c
Phase Shift
360°
2
C
+

2
C
1
C
+ 
+ 
v
out
(n1)
o
v
out
(n1)
o
v
out
(n1)
e
+

v
in
(n1)
o
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 914
Problem 9.211
(a.) Give a schematic drawing of a switched capacitor realization of a voltage amplifier
having a gain of H
oo
= +10V/V using a twophase nonoverlapping clock. Assume that the
input is sampled on the φ
1
and held during φ
2
. Use op amps, capacitors, and switches with
φ
1
or φ
2
indicating the phase the switch is closed.
(b.) Give a schematic of the circuit in (a.) that reduces the number of switches to a
minimum number with the circuit working correctly. Assume the op amp is ideal.
(c.) Convert the circuit of (a.) to a differential implementation using the
differentialin, differentialout op amp shown in Fig. P9.211.
Solution
a.)
+

φ
1
φ
2
φ
2
φ
2
φ
1
10C
C
v
out
v
in
b.)
+

φ
1
φ
2
φ
2
10C
C
v
out
v
in
c.)
φ
1
φ
2
φ
2
φ
2
φ
1
10C
C
v
out
v
in
+

+

+

+

φ
2
φ
1
φ
2
10C
C
F97E2S4
+

+

Figure P9.211
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 915
Problem 9.301
Over what frequency range will the integrator of Ex. 9.31 have a ±1° phase error?
Solution
Assuming the integrator frequency response can be represented as shown below.
90°
0°
Arg[V
out
(jω)/V
in
(jω)]
log
10
ω
ω
I
A
vd
(0)
GB
180°
45°
135°
ω
I
10A
vd
(0)
10ω
I
A
vd
(0)
GB
10
10GB
V
out
(jω)/V
in
(jω)
ω
I log
10
ω
0 dB
GB
A
vd
(0) dB
Eq. (3)
Eq. (2)
Eq. (1)
ω
I
A
vd
(0)
ω
x1
=
ω
x2
=
The integrator phase error on the low side of the useful band is given as,
Error = 90°  tan
1
.

}
` ω
L
ω
I
/A
vd
(0)
= 1° → ω
L
= 57.29
ω
I
A
vd
(0)
The integrator phase error on the high side of the useful band is given as,
Error = tan
1
.

}
` ω
H
GB
= 1° → ω
H
=
GB
57.29
If A
vd
(0), ω
I
, and GB are given, the useful range is from ω
L
to ω
H
.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 916
Problem 9.302
Show how Eq. (9.312) is developed from
Fig. 9.34(b.).
Solution
Fig. 9.34(b.)
1
2
2
C
v
out in
v
v
C2
+ 
1
2
1
C
v
C1
(t)
+

S1
S2 S3
S4
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 917
Problem 9.3 03
Find the H
eo
(jωT) transfer function for the
inverting integrator of Fig. 9.34b and compare
with the H
ee
(jωT) transfer function.
Solution
Fig. 9.34(b.)
1
2
2
C
v
out in
v
v
C2
+ 
1
2
1
C
v
C1
(t)
+

S1
S2 S3
S4
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 918
Problem 9.304
An inverting, switchedcapacitor integrator
is shown. If the gain of the op amp is A
o
,
find the zdomain transfer function of this
integrator. Identify the ideal part of the
transfer function and the part due to the
finite op amp gain, A
o
. Find an expression
for the excess phase due to A
o
.
Solution
Let us use charge conservation to solve the
problem.
C
2
v
C2
(nT) = C
2
v
C2
[(n1)T] – C
1
[v
in
(n1)T + v
o
(nT)/A
o
]
or
V
C2
(z) = z
1
V
C2
(z) 
C
1
C
2
z
1
V
in
(z) 
C
1
C
2
V
o
(z)
A
o
V
C2
(z)[1 z
1
] = α z
1
V
in
(z)  α
V
o
(z)
A
o
, where α =
C
1
C
2
V
C2
(z) =
α z
1
1 z
1
V
in
(z) 
α/A
o
1 z
1
V
o
(z)
∴ V
o
(z) = V
C2
(z) 
V
o
(z)
A
o
=
α z
1
1 z
1
V
in
(z) 
α/A
o
1 z
1
V
o
(z) 
V
o
(z)
A
o
x
1 z
1
1 z
1
V
o
(z)
]
]
]
1 z
1
+
α
A
o
+
1 z
 1
A
o
= α z
1
V
in
(z)
∴ H(z) =
V
o
(z)
V
in
(z)
=
α z
 1
1 z
1
+
1+α  z
 1
A
o
=
.

}
` α z
 1
1 z
1
.

}
`
1
1+
1+α  z
1
A
o
(1 z
1
)
The first bracket is the ideal term and the second bracket is the term due to A
o
.
To evaluate the excess phase due to A
o
we replace z by e
jωT
.
H(e
jωT
) =
1
1+
1+α  z
1
A
o
(1 z
1
)
=
1
1+
(1+α) e
jωT/2
A
o
(e
jωT/2
 e
jωT/2
)
+
e
jωT/2
A
o
(e
jωT/2
 e
jωT/2
)
=
1
1  j
.

}
` 1+α
2A
o
.

}
` cos(ωT/2) + jsin(ωT/2)
sin(ωT/2)
+
j
2A
o
.

}
` cos(ωT/2) + jsin(ωT/2)
sin(ωT/2)
=
1
1 +
2+α
A
o
 j
α
2A
o
cot(ωT/2)
→ Arg[H(e
jωT
)] = tan
1
]
]
]
]
α
2A
o
cot(ωT/2)
1 +
2+α
A
o
∴ Excess phase = tan
1
]
]
] α cot(ωT/2)
2A
o
+ 4 + 2α
≈ tan
1
]
]
] α
2A
o
tan(ωT/2)
≈ 
α
2A
o
tan(ωT/2)

+
+

V
O
φ
1
φ
2
C
2
C
1 V
in
Figure P9.34
+

A
o
v
o
+

v
C2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 919
Problem 9.305
For the switchedcapacitor circuit shown
find V
o
OUT
(z) as a function of V
o
1
(z),
V
o
2
(z) , and V
o
3
(z) assuming the clock is a
twophase, nonoverlapping clock.
Assume that the clock frequency is much
greater than the signal bandwidth and find
an approximate expression for V
out
(s) in
terms of V
1
(s), V
2
(s), and V
3
(s). Assume
that the inputs are sampled and held where
necessary.
Solution
φ
1
, t = (n1)T: Model:
φ
2
, t = (n0.5)T: Model:
v
e
out
(n0.5) = v
o
out
(n1) 
C
1
C
2
v
e
2
(n0.5)

C
1
C
2
v
o
1
(n1) +
C
1
C
2
v
o
3
(n1)
φ
1
, t = (n)T:
v
o
out
(n) = v
o
out
(n1) 
C
1
C
2
v
e
2
(n0.5) +
C
1
C
2
v
o
1
(n1) 
C
1
C
2
v
o
3
(n1)
∴ V
o
out
(z) = z
1
V
o
out
(n1)  z
0.5
C
1
C
2
V
e
2
(z) + z
1
C
1
C
2
V
o
1
(z)  z
1
C
1
C
2
V
o
3
(z)
Replacing V
e
2
(z) by z
0.5
V
o
2
(z) gives
V
o
out
(z) = z
1
V
o
out
(n1)  z
1
C
1
C
2
V
o
2
(z) + z
1
C
1
C
2
V
o
1
(z)  z
1
C
1
C
2
V
o
3
(z)
V
o
out
(z) = 
z
1
1z
1
[V
o
1
(z) + V
o
2
(z) + V
o
3
(z)]
Replacing 1 z
1
by sT and z
1
by 1 gives,
V
o
out
(s) = 
1
sT
[V
o
1
(s) + V
o
2
(s) + V
o
3
(s)]
∴ V
o
out
(s) =
1
sT
[V
o
1
(s)  V
o
2
(s)  V
o
3
(s) ]
φ2 φ2 φ2 φ1 φ1 φ1
n
3
2
n
1
2
n+
1
2
n+
3
2
n+1 n1
n
t
T

+
+

v
out
φ
1
φ
1
φ
2
φ
2
C1 C
2
A1 +

+

v
1
v
2
v
3
S02E2P4

+
v
1
(n1)
C
1 o
v
3
(n1)
o
+

v
out
(n1)
o
C
2
v
out
(n1)
o

+
S02E2S4A

+
v
2
(n0.5)
C
1 e
v
3
(n1)
o
+

v
out
(n0.5)
e
C
2
v
out
(n1)
o

+
S02E2S4B
v
1
(n1)
o

 +
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 920
Problem 9.306
The switched capacitor circuit shown uses a twophase, nonoverlapping clock. (1.) Find
the zdomain expression for H
oo
(z). (2.) Replace z by e
jωT
and plot the magnitude and
phase of this switched capacitor circuit from 0 Hz to the clock frequency, f
c
, if C
1
= C
3
and
C
2
= C
4
. Assume that the op amps are ideal for this problem. (3.) What is the
multiplicative magnitude error and additive phase error at f
c
/2?
+

φ
2
φ
2
φ
1
φ
1
C
3
C
4
v
out
+

φ
2
φ
1
φ
2
φ
1
C
1
C
2
v
o1
v
in
n1.5 n1 n0.5 n+0.5 n n+1 n+1.5
t
T
φ
2
φ
1 φ
2
φ
2
φ
1 φ
2
φ
1
S02FEP1
Solution
(1.) φ
1
(n1≤t/T<n0.5):
q
o
C1
(n1) = C
1
v
o
in
(n1) and q
o
C2
(n1) = C
2
v
o
o1
(n1)
φ
2
(n0.5≤t/T<n):
q
e
C2
(n0.5) = q
o
C2
(n1) + q
o
C1
(n1) and q
e
C4
(n0.5) = C
4
v
e
out
(n0.5)
φ
1
(n≤t/T<n+0.5):
q
o
C2
(n) = q
e
C2
(n0.5) = q
o
C2
(n1) + q
o
C1
(n1)
v
o
o1
(n) = v
o
o1
(n1) +
C
1
C
2
v
o
in
(n1) → V
o
o1
(z) = z
1
V
o
o1
(z) +
C
1
C
2
V
o
in
(z)
∴ V
o
o1
(z) =
C
1
/C
2
z1
V
o
in
(z)
Also, q
o
C3
(n) = C
3
v
o
o1
(n) and q
o
C4
(n) = q
e
C4
(n0.5)  q
o
C3
(n)
q
o
C4
(n) = q
o
C4
(n1)  q
o
C3
(n) → V
o
out
(z) = z
1
V
o
o1
(z) 
C
3
C
4
V
o
o1
(z)
∴ V
o
out
(z) =
(C
3
/C
4
)z
1
z1
V
o
in
(z)
∴ V
o
out
(z) =
.

}
`
(C
3
/C
4
)z
1
z1
.

}
`
C
1
/C
2
z1
V
o
in
(z) → H
oo
(z) =
V
o
out
V
o
in
= 
.

}
`
C
1
C
3
C
2
C
4
z
(z1)
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 921
Problem 9.306 – Continued
∴ H
oo
(e
jωT
) = 
.

}
`
C
1
C
3
C
2
C
4
e
jωT
(e
jωT
1)
2
= 
.

}
`
C
1
C
3
C
2
C
4
1
(e
jωT/2
 e
jωT/2
)
2
= 
.

}
`
C
1
C
3
C
2
C
4
1
(2j sin(ωT/2))
2
= 
.

}
`
C
1
C
3
C
2
C
4
.

}
` (ωT/2)
jωT sin(ωT/2)
2
=
.

}
`
C
1
jωTC
2
ωT/2
sin(ωT/2)
.

}
`
C
3
jωTC
4
ωT/2
sin(ωT/2)
=
.

}
` ω
o1
jω .

}
` ω
o2
jω .

}
` (ωT/2)
sin(ωT/2)
2
=
.

}
` ω
o
jω
2
.

}
` (ωT/2)
sin(ωT/2)
2
If C
1
= C
3
and C
2
= C
4
, ω
o1
= C
1
/(TC
2
), and ω
o2
= C
3
/(TC
4
).
The frequency response is plotted below.
0
0
f
c
1
0.5f
c
f
o
f
c
f
o
H
oo
(e
jωT
)
0°
f
c
0.5f
c
f
f
Phase
Phase of H
oo
(e
jωT
)
S02FES1
∴ The magnitude error =
.

}
` (ωT/2)
sin(ωT/2)
2
=
.

}
` (π/2)
sin(π/2)
2
=
π
2
4
= 2.467
Phase error = 0°
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 922
Problem 9.307
Find H
oo
(z) (=V
out
o
(z) /V
in
o
(z) ) of the switched capacitor circuit shown. Replace z by e
jωt
and identify the magnitude and phase response of this circuit. Assume C
1
/C
2
= π/25.
Sketch the exact magnitude and phase response on a linearlinear plot from f=0 to f=f
c
.
What is the magnitude and phase at f = 0.5f
c
? Assume that the op amp is ideal.
Solutions
φ
2
; (n0.5)<t/T <n
At t =0
+
we have the following model:
We can write,
v
e
out
(n0.5) = v
o
out
(n1) 
C
1
C
2
v
o
in
(n1)
But v
e
out
(n) = v
e
out
(n0.5) = v
o
out
(n1) 
C
1
C
2
v
o
in
(n1)
∴ V
o
out
(z) = z
1
V
o
out
(z) 
C
1
C
2
z
1
V
o
in
(z) → H
oo
(z) =
C
1
C
2
z
1
1z
1
H
oo
(e
jωT
) = 
C
1
C
2
.

}
` e
jωT
1e
jωT
e
jωT/2
e
jωT/ 2
= 
C
1
C
2
e
jωT/2
e
jωT/2
 e
jωT/ 2
= 
C
1
C
2
e
jωT/2
2j sin(ωΤ/2)
x
ωT
ωT
=
.

}
`

C
1
jC
2
ωT .

}
` ωT/2
sin(ωT/2)
( )
e
jωT/2
=
.

}
`

ω
o
jω .

}
` ωT/2
sin(ωT/2)
( )
e
jωT/2
For f = 0.5f
c
we get
ωΤ
2
=
2πf
c
2·2f
c
=
π
2
and ω
ο
=
C
1
C
2
T
=
π
25
f
c
∴ H
oo
(e
jπ
) =
.

}
`
f
c
/50
f
c
/ 2
.

}
` π/2
sin(π/2)
=
1
25
π
2
= 0.06283 and Arg[H
oo
(e
jπ
)] = +90°90° = 0°
Plots:
100
50
0
50
100
0 0.2 0.4 0.6 0.8 1
D
e
g
r
e
e
s
f/f
c
0
0.2
0.4
0.6
0.8
1
0 0.2 0.4 0.6 0.8 1
M
a
g
n
i
t
u
d
e
f/f
c Prob. 9.37
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 923
Problem 9.308
The switched capacitor circuit shown
uses a twophase, nonoverlapping
clock. (1.) Find the zdomain
expression for H
ee
(z). (2.) If C
2
=
0.2πC
1
, plot the magnitude and phase
response of the switched capacitor
circuit from 0 rps to the clock
frequency (ω
c
). Assume that the op
amp is ideal for this problem. It may
be useful to remember that Eulers
formula is e
±jx
= cos(x)±jsin(x).
Solution
φ
1
: t =( n 1) T
The capacitor, C
1
, simply holds the
voltage, v
e
in
(n1.5) and C
2
= 0V.
φ
2
: t =( n 0.5) T
The model for this phase is given.
The equation for this phase can be written as,
v
e
out
(n0.5) = 
C
1
C
2
v
e
in
(n0.5) +
C
1
C
2
v
e
in
(n1.5)
Converting to the zdomain gives,
z
1/2
V
e
out
(z) = 
C
1
C
2
z
1/2
V
e
in
(z) +
C
1
C
2
z
3/2
V
e
in
(z) → V
e
out
(z) = 
C
1
C
2
V
e
in
(z) +
C
1
C
2
z
1
V
e
in
(z)
∴
V
e
out
(z)
V
e
in
(z)
= 
C
1
C
2
(1z
1
) →
V
e
out
(jω)
V
e
in
(jω)
= H
ee
(jω) = 
C
1
C
2
(1e
jωT
)x
e
jωΤ/2
e
jωΤ/2
H
ee
(jω) =
5
π
.

}
` e
jωΤ/2
 e
jωΤ/2
e
jωΤ/2
=
5
π
[j2sin(ωT/2)] e
jωΤ/2
=
10
π
jωT
2
.

}
` sin(ωT/2)
ωT/2
e
jωΤ/2
H
ee
(jω) = j
10f
f
c
.

}
` sin(ωT/2)
ωT/2
e
jωΤ/2
Plotting gives,
φ2 φ2 φ2 φ1 φ1 φ1
n
3
2
n
1
2
n+
1
2
n+
3
2
n+1 n1
n
t
T

+
+

v
IN
v
OUT
φ
1 1
φ
2
φ
φ
2
C
2
C
1
φ
1
φ
2
Figure P9.38
+

v
in
(n0.5)
e
v
in
(n1.5)
o
C
1
C
2
v
out
(n0.5)
e
Fig. S9.308
0
f
c
f
1
2
3
4
5
0
2/π
0 0.1f
c 0.5f
c
f
c
f
90°
90°
0.1f
c 0.5f
c
M
a
g
n
i
t
u
d
e
P
h
a
s
e
Fig. S9.308A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 924
Problem 9.309
Find the zdomain transfer function, H
oo
(z), for
the circuit shown. Assume that C
2
= C
3
= C
4
=
C
5
. Also, assume that the input is sampled
during φ
1
and held through φ
2
. Next, let the
clock frequency be much greater than the signal
frequency and find an expression for H
oo
(jω).
What kind of circuit is this?
Solution
φ
1
: n 1<( t/T )≤ n 0.5
v
C4
o
(n0.5) = v
out
o
(n0.5)
v
out
o
(n0.5) = 
C
1
C
3
v
in
o
(n0.5) 
C
2
C
3
v
o1
(n0.5) = v
out
e
(n1)
φ
2
: n 0.5<( t/T ) ≤ n
v
o1
e
(n) = v
o1
o
(n0.5) 
C
4
C
5
v
out
e
(n) and v
out
e
(n) = 
C
2
C
3
v
o1
e
(n) 
C
1
C
3
v
in
e
(n)
∴ v
out
e
(n) = 
C
2
C
3
]
]
]
v
o1
o
(n0.5) 
C
4
C
5
v
out
e
(n) 
C
1
C
3
v
in
e
(n)
φ
1
: n <( t/T )≤ n +0.5
v
out
o
(n+0.5) = 
C
1
C
3
v
in
o
(n+0.5) 
C
2
C
3
v
o1
o
(n+0.5) → V
out
o
(z) = 
C
1
C
3
V
in
o
(z) 
C
2
C
3
V
o1
o
(z)
but, v
o1
o
(n+0.5) = v
o1
e
(n) = v
o1
o
(n0.5) +
C
4
C
5
v
out
o
(n0.5)
V
o1
o
(z) = z
1
V
o1
o
(z) 
C
4
C
5
V
out
o
(z) → V
o1
o
(z)[1z
1
] = 
C
4
C
5
V
out
o
(z)
Substituting into the above expression for V
out
o
(z) gives
V
out
o
(z) = 
C
1
C
3
V
in
o
(z) +
C
2
C
3
.

}
`
C
4
C
5
1
1z
1
V
out
o
(z) → H
oo
(z) =
C
1
/C
3
1 (
C
2
C
4
C
3
C
5
)
1
1z
1
If C
2
C
4
= C
3
C
5
, then H
oo
(z) =
C
1
C
3
]
]
] 1z
1
z
1
→ H
oo
(s) ≈
C
1
C
3
]
]
1(1sT)
1
=
C
1
C
3
sT
(This is a lot easier with zdomain models.)
∴ H
oo
(jω) ≈
jω
C
3
/C
1
T
=
jω
ω
D
where ω
D
=
C
3
TC
1
This circuit is a noninverting switched capacitor differentiator.
+

+

C
5
φ
1
C
2
C
1
C
3
C
4
v
out
(t)
φ
1
φ
2
φ
2
v
in
(t)
v
o1
(t)
n
3
2
n1 n
1
2
n n+
1
2
t
T
φ
1
φ
2
φ
2
φ
1
F97FEP2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 925
Problem 9.401
Repeat Ex. 9.41 for the positive switched capacitor transresistance circuit of Fig. 9.43.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 926
Problem 9.402
Use the zdomain models to verify Eqs. (9.219) and (9.223) of Sec. 9.2 for Fig. 9.2
4(b.).
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 927
Problem 9.403
Repeat Ex. 9.45 assuming that the op amp is ideal (gain = ∞). Compare with the results
of Ex. 9.45 (Hint: use Fig. 9.48b).
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 928
Problem 9.404
Repeat Ex. 9.45 assuming the op amp gain is 100V/V. Compare with the results of Ex.
9.45.
Solution
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 929
Problem 9.405
Repeat Ex. 9.45 for the inverting switched capacitor integrator in Fig. 9.34(b).
1
2
2
C
v
out in
v
v
C2
+ 
1
2
1
C
v
C1
(t)
+

S9.25
Solution
The zdomain model for this circuit is shown below.
+

V
o
i
+

V
e
i
+

V
o
o
+

V
e
o
C
2

C
2
z

1
/
2
C
2
z

1
/
2

C
2
z

1
/
2
C
2
z

1
/
2
10
6
V
3
10
6
V
4
5
0
6
3
0
4
1
0
2 C
2
C
1
S9.45B
ω
I
=
1
R
1
C
2
=
f
c
C
1
C
2
⇒
C
1
C
2
=
2πf
I
f
c
=
2π(10kHz)
100kHz
=
π
5
= 0.62832
∴ Let C
2
= 1F and C
1
= 0.62832F
SPICE Input File
Problem 9.45 Solution
R24 2 5 1.592
X43PC2 4 3 43 DELAY
G43 4 3 43 0 1
R35 3 5 1.0
X56PC2 5 6 56 DELAY
G56 5 6 56 0 1
R46 4 6 1.0
X36NC2 3 6 36 DELAY
G36 6 3 36 0 1
X45NC2 4 5 45 DELAY
G45 5 4 45 0 1
EODD 6 0 4 0 1E6
EVEN 5 0 3 0 1E6
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5U
RDO 3 0 1K
.ENDS DELAY
.AC LIN 99 1K 99K
.PRINT AC V(6) VP(6) V(5) VP(5)
.PROBE
.END
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 930
Problem 9.405  Continued
Plot of the results is below.
0
1
2
3
4
5
M
a
g
n
i
t
u
d
e
0
20 40 60 80 100
Frequency (kHz)
H (e
jωT
) and
οο
H (e
jωT
)
ee
Ideal
200
150
100
50
0
50
100
150
200
P
h
a
s
e
(
D
e
g
r
e
e
s
)
0
20 40 60 80 100
Frequency (kHz)
Arg[H (e
jωT
)]
οο
Arg[H (e
jωT
)]
εε
Solution 9.45
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 931
Problem 9.501
Develop Eq. (9.56) for the inverting low pass circuit obtained from Fig. 9.15(a.) by
reversing the phases of the leftmost two switches. Verify Eq. (9.57).
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 932
Problem 9.502
Use SPICE to simulate the results of Ex. 9.51.
Solution
The SPICE model for this problem is given as
+

V
o
i
+

V
e
i
C
1
C
1
z

1
/
2

C
1
z

1
/
2
C
1
z

1
/
2
C
1
+

V
o
o
+

V
e
o
C

C
z

1
/
2
C
z

1
/
2

C
z

1
/
2
C
z

1
/
2
10
6
V
3
10
6
V
4
5
0
6
3
0
4
1
0
2 C
C
2
Fig. S9.502
The SPICE input file is:
PROBLEM 9.52 SOLUTION
VIN 1 0 DC 0 AC 1
R10C1 1 0 1.592
X10PC1 1 0 10 DELAY
G10 1 0 10 0 0.6283
X14NC1 1 4 14 DELAY
G14 4 1 14 0 0.6283
R40C1 4 0 1.592
X40PC1 4 0 40 DELAY
G40 4 0 40 0 0.6283
X43PC2 4 3 43 DELAY
G43 4 3 43 0 1
R35 3 5 1.0
X56PC2 5 6 56 DELAY
G56 5 6 56 0 1
R46 4 6 1.0
X36NC2 3 6 36 DELAY
G36 6 3 36 0 1
X45NC2 4 5 45 DELAY
G45 5 4 45 0 1
*R35C2 3 5 15.9155
R46C2 4 6 15.9155
EVEN 6 0 4 0 1E6
EODD 5 0 3 0 1E6
********************
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5U
RDO 3 0 1K
.ENDS DELAY
********************
.AC LIN 1000 1 100K
.PRINT AC V(6) VP(6) V(5) VP(5) VDB(5) VDB(6)
.PROBE
.END
20
15
10
5
0
5
10
15
20
10 100 1000 10
4
10
5
M
a
g
i
n
i
t
d
e
d
B
Frequency (Hz)
Continuous
Time Circuit
Fig. S9.502A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 933
Problem 9.503
Repeat Ex. 9.51 for a firstorder, lowpass circuit with a low frequency gain of +1 and a 
3dB frequency of 5kHz.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 934
Problem 9.504
Design a switched capacitor realization for a firstorder , lowpass circuit with a low
frequency gain of 10 and a 3dB frequency of 1kHz using a clock of 100kHz.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 935
Problem 9.505
Design a switched capacitor realization for a firstorder , highpass circuit with a high
frequency gain of 10 and a 3dB frequency of 1kHz using a clock of 100kHz.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 936
Problem 9.506
Repeat Ex. 9.52 for a treble boost circuit having 0dB gain from dc to 1kHz and an
increase of gain at +20dB/dec. from 1kHz to 10kHz with a gain of +20dB from 10kHz and
above (the mirror of the response of Fig. 9.57 around 1kHz).
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 937
Problem 9.507
The switched capacitor circuit
shown uses a twophase,
nonoverlapping clock. (1.) Find
the zdomain expression for
H
oo
(z). (2.) Plot the magnitude
and phase response of the switched
capacitor circuit from 0 rps to the
clock frequency (ω
c
). Assume that
the op amp is ideal for this
problem. It may be useful to
remember that Eulers formula is
e
±jx
= cos(x)±jsin(x).
Solution
φ
1
, (n1)≤t/T<(n0.5):
φ
2
, (n0.5)≤t/T<(n):
From the equivalent circuit shown, we can write,
v
e
2
(n0.5) = v
o
2
(n1) 
C
2
C
3
v
e
2
(n0.5) +
C
1
C
3
v
o
1
(n1)
But, v
o
2
(n) = v
e
2
(n0.5) =
v
o
2
(n1) 
C
2
C
3
v
o
2
(n) +
C
1
C
3
v
o
1
(n1)
which gives,
V
2
(z) = z
1
V
2
(z) 
C
2
C
3
V
2
(z) +
C
1
C
3
z
1
V
1
(z)
∴
V
2
(z)
V
1
(z)
= H
oo
(z) =
(C
1
/C
3
)z
1
1 + (C
2
/C
3
)  z
 1
→ H
oo
(e
jωT
) =
(C
1
/C
3
)e
jωT
1 + (C
2
/C
3
)  e
jωT
H
oo
(e
jωT
) =
0.2
(1.1 cosωT)
2
+ sin
2
ωT
and Arg[H
oo
(e
jωT
)] = ωT – tan1
.

}
` sinωT
1.1cosωT
Replace ωT by 2πf/f
c
and plot as a function of f/f
c
to get the following plots.
+

φ
2
φ
1
C
2
φ
2
φ
1
φ
1
φ
2
C
1
φ
2
φ
1
+

v
in
v
out
C
3
n+1/2 n n1/2 n1 n3/2
t/T
φ
2
φ
1
φ
2
φ
1
Figure P9.57
C
1
+

v
1
(n1)
o
v
1
(n1)
o
+

v
2
(n1)
o
C
2
+ 
v
2
(n1)
o
Fig. S9.57A
+

v
1
(n1)
o
C
1
C
3
C
2
v
2
(n1)
o
v
2
(n0.5)
e
Fig. S9.57B
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 938
Problem 9.508
The switched capacitor circuit shown uses a twophase, nonoverlapping clock. (a.) Find
the zdomain expression for H
oo
(z). (b.) Use your expression for H
oo
(z) to design the
values of C
1
and C
2
to achieve a realization to
H(s) =
10,000
s+1000
if the clock frequency is 100kHz and C
3
= 10pF. Assume that the op amp is ideal.
Solution
(a.) Converting the problem into a
summing integrator gives:
φ
1
: ( n 1.5) ≤ t/T <( n 1)
v
o
C1
(n1.5) = v
o
in
(n1.5), v
o
C2
(n1.5) = 0
and v
o
C3
(n1.5) =v
o
out
(n1.5)
φ
2
: ( n 1) ≤ t/T <( n 0.5)
The eq. circuit at t = 0+ is shown. ∴
v
e
out
(n1) =
C
1
C
3
v
o
in
(n1.5) 
C
2
C
3
v
o
out
(n0.5) + v
o
out
(n1.5)
φ
1
: ( n 0.5) ≤ t/T <( n )
v
o
out
(n0.5) = v
e
out
(n1) =
C
1
C
3
v
o
in
(n1.5) 
C
2
C
3
v
o
out
(n0.5) + v
o
out
(n1.5)
Transforming to the zdomain gives, V
o
out
(z) = z
1
C
1
C
3
V
o
in
(z) 
C
2
C
3
V
o
out
(z) + z
1
V
o
out
(z)
Solving for H
oo
(z) gives, H
oo
(z) =
V
o
out
(z)
V
o
in
(z)
=
z
1
C
1
C
2
+C
3
C
3
z
1
=
C
1
z(C
2
+C
3
)  C
3
(b.) Assume that f<<f
c
and let z ≈ 1+sT. Substituting into the above gives
H
oo
(s) ≈
C
1
(1+sT)[C
2
+C
3
] C
3
=
C
1
C
2
+C
3
C
3
+sT(C
2
+C
3
)
=
C
1
/ C
2
sT(C
2
+C
3
)/C
2
+ 1
Equating this result with the H(s) in the problem statement gives
C
1
C
2
=10, 1+
C
3
C
2
=
f
c
1000
⇒ C
2
=C
3
/99=10pF/99=0.101pF and C
1
=10C
2
=1.01pF
+

φ
2
φ
1
C
2
φ
2
φ
1
φ
1
φ
2
C
1
φ
2
φ
1
+

v
in
v
out
C
3
= 10pF
+

v
in
+

C
1
+

C
3
v
in
o
(n3/2)
C
2
+

v
out
e
(n1)
+

v
out
o
(n3/2)
v
out
e
(n1)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 939
Problem 9.509
Find H
oo
(z) of the switched
capacitor circuit shown.
Replace z by e
jωT
and identify
the magnitude and phase
response of this circuit.
Solution
φ
2
, (n0.5)≤t/T<(n):
With the φ
2
switches closed,
the model is shown below.
+

v
1
(n1)
o
C
1
C
3
v
2
(n0.5)
e
Fig. S9.59A
The output is given as,
v
e
2
(n0.5) =+
C
1
C
3
v
o
1
(n1)
φ
1
, (n)≤t/T<(n+0.5):
The model for this case is shown. The output is written
as,
v
o
2
(n) = +
C
3
C
2
v
e
2
(n0.5) = +
C
3
C
2
·
C
1
C
3
v
o
1
(n1) =
C
1
C
2
v
o
1
(n1)
∴ V
o
2
(z) =
C
1
C
3
z
1
V
o
1
(z) →
V
o
2
(z)
V
o
1
(z)
= H
oo
(z) =
C
1
C
2
z
1
H
oo
(e
jωT
) =
C
1
C
2
= 1 0 and Arg[H
oo
(e
jωT
)] = ωT
Comment: Note that this configuration is an amplifier that avoids taking the output of the
op amp to zero when the feedback capacitor is shorted out. Therefore, slew rate limitation
of the op amp is avoided.
+

φ
1
φ
1
φ
1
φ
2
φ
2
φ
2
1
φ
φ
2
C
2
=
1pF
v
1
(t)
v
2
(t)
φ2 φ2 φ2 φ1 φ1 φ1
n
3
2
n
1
2
n+
1
2
n+
3
2
n+1 n1
n
t
T
φ
2
1
φ
C
3
= 1pF
C
1
=
10pF
Figure P9.59
+

v
2
(n0.5)
e
C
3
C
2
v
2
(n)
o
Fig. S9.59B
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 940
Problem 9.510
The switched capacitor circuit
shown is used to realize an
audio bassboost circuit. Find
H(e
jωT
) =
V
out
(e
jωT
)
V
in
(e
jωT
)
assuming that f
c
>> f
signal
. If
C
2
= C
4
= 1000pF and f
c
=
10kHz, find the value of C
1
and C
3
to implement the
following transfer function.
V
out
(s)
V
in
(s)
= 10
.

}
`
s
100
+ 1
s
10
+ 1
Solution
Write the circuit as the
following summing integrator
and replacing with zdomain models gives:
v
in
v
out C
1
+

φ
1
φ
1
φ
2 φ
2
C
3
φ
1
φ
1
φ
2 φ
2
C
4
C
1
v
in
v
out
+

C
4
(1z
1
)
C
2
(1z
1
)
C
1
C
3
V
in
(z)
V
in
(z)
V
out
(z)
V
out
(z)
Summing currents gives,
C
2
(1z
1
)V
in
(z) + C
1
V
in
(z) + C
3
V
out
(z) + C
4
(1z
1
)V
out
(z) = 0
Transforming to the sdomain by 1z
1
≈ sT gives,
sT C
2
V
in
(s) + C
1
V
in
(s) + C
3
V
out
(s) + sT C
4
V
out
(s) = 0
∴ H(s) =
V
out
(s)
V
in
(s)
= 
.

}
`
sT C
2
+C
1
sT C
4
+C
3
= 
.

}
`
C
1
C
3
.

}
`
sT C
2
C
1
+1
sT C
4
C
3
+1
= 10
.

}
`
s
100
+1
s
10
+1
Therefore,
C
1
C
3
= 10 ,
C
1
TC
2
= 100 and
C
3
TC
4
= 10
∴ C
1
=
100C
2
f
c
=
100·1000pF
10,000
= 10pF and C
3
= 1pF
+

φ
1
φ
1
φ
2
φ
2
1
φ
φ
2
φ2 φ2 φ2 φ1 φ1 φ1
n
3
2
n
1
2
n+
1
2
n+
3
2
n+1 n1
n
t
T
1
φ
φ
2
v
in
(t)
v
out
(t)
C
1
C
3
C
2
=1000pF C
4
=1000pF
Figure P9.510
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 941
Problem 9.601
Combine Figs. 9.62a and 9.62b to form a continuous time biquad circuit. Replace the
negative resistor with an inverting op amp and find the sdomain frequency response.
Compare your answer with Eq. (9.61).
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 942
Problem 9.602
(a.) Use the lowQ switched capacitor biquad circuit shown to design the capacitor ratios
of a lowpass secondorder filter with a pole frequency of 1kHz, Q = 5 and a gain at dc of
10 if the clock frequency is 100kHz. What is the total capacitance in terms of C
u
?
(b.) Find the clock frequency, f
c
, that keeps all capacitor ratios less than 10:1. What is the
total capacitance in terms of C
u
for this case?
+

V
1
(z)
C
1
V
in
(z)
e
φ
1
φ
1
φ
1
φ
2
φ
2
α
2
C
1
α
1
C
1
φ
2
+

C
2
φ
2
α
6
C
2
α
4
C
2
φ
2
α
5
C
2
φ
1
V
out
(z)
e
α
3
C
2
e
φ
1
Design Eqs: α
1
=
K
0
T
ω
o
, α
2
= α
5
 = ω
o
T, α
3
= K
2
, α
4
= K
1
T, and α
6
=
ω
o
T
Q
.
Solution
(a.) H(s) =
10ω
o
2
s
2
+
ω
o
Q
s + ω
o
2
⇒ K
o
= 10ω
o
2
, K
1
= K
2
= 0, ω
o
= 2000π, and Q = 5
∴ α
1
=
10ω
o
2
T
ω
ο
= 10ω
o
T , α
2
= α
5
 = ω
o
T, α
3
= α
4
= 0, and α
6
=
ω
o
T
Q
=
ω
o
T
5
ω
o
T =
2πf
o
f
c
=
2π
100
= 0.06283 ⇒ α
1
= 0.6283, α
2
=α
5
 0.06283, α
6
=0.01256
Total capacitance =
1
0.6283
+
1
0.06283
+ 2 +
1
0.01256
+
1
0.06283
= 115.45C
u
(b.)
ω
ο
5f
c
= 0.1 ⇒ f
c
= 2ω
o
= 4000π = 12. 566kHz
Now, α
1
= 5, α
2
= α
5
 = 0.5, and a
6
= 0.1
Total capacitance = 5 +
1
. 5
+ 1 +
1
0.1
+
1
0.5
+ 1 = 21C
u
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 943
Problem 9.603
A TowThomas continuous time filter is shown. Give a discretetime realization of this
filter using straysinsensitive integrators. If the clock frequency is much greater than the
filter frequencies, find the coefficients, a
i
and b
i
, of the following zdomain transfer
function in terms of the capacitors of the discretetime realization.
H(z) =
a
0
+ a
1
z
1
+ a
2
z
 2
b
0
+ b
1
z
1
+ b
2
z
 2
Solution
The development of a
discretetime
realization of the Tow
Thomas continuous
time filter is shown to
the right.
Using zdomain
analysis, we can solve
for the desired transfer
function and find the
coefficients.
V
out
(z) =
1
1  z
 1
]
]
C
R4
C
1
z
1
V
in
(z) 
C
R1
C
1
z
1
V
out
(z) +
C
R3
C
1
z
1
V
2
(z) and V
2
(z) = 
C
R2
/C
2
1  z
 1
V
out
(z)
∴ V
out
(z) =
1
1  z
 1
]
]
]
C
R4
C
1
z
1
V
in
(z) 
C
R1
C
1
z
1
V
out
(z) +
C
R2
C
R3
C
1
C
2
z
1
1  z
 1
V
out
(z)
V
out
(z)
]
]
(1  z
1
)
2

C
R1
C
1
(1  z
1
) +
C
R2
C
R3
C
1
C
2
z
1
(1  z
1
) = z
1
(1  z
1
)
C
R4
C
1
V
in
(z)
H(z) =
V
out
(z)
V
in
(z)
=
(z
1
 z
2
)
C
R4
C
1
1 + 2z
1
+ z
2
+
C
R1
C
1

C
R1
C
1
z
1
+
C
R2
C
R3
C
1
C
2
z
1

C
R2
C
R3
C
1
C
2
z
2
Equating coefficients gives,
a
0
= 0, a
1
=
C
R4
C
1
, a
2
= 
C
R4
C
1
, b
0
= 1 +
C
R1
C
1
, b
1
= 2 
C
R1
C
1
+
C
R2
C
R3
C
1
C
2
and b
2
= 1
C
R2
C
R3
C
1
C
2
+

+

+

v
in
R
4
R
1
R R R
2
R
3
C
2
C
1
v
out
Fig.S9.63
+

C
R4
C
1
φ
1
φ
1
φ
2
φ
2
V
2
φ
1
φ
2
φ
2
φ
1
C
R1
C
R3
v
out
+

C
R2
φ
2
φ
1
φ
1
φ
2
C
2 V
in
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 944
Problem 9.604
Find the zdomain transfer function H(z) = V
out
(z)/V
in
(z) in the form of
H(z) =
a
2
z
2
+ a
1
z + a
0
b
2
z
2
+ b
1
z + b
0
for the switched capacitor circuit shown below. Evaluate the a
i
's and b
i
's in terms of the
capacitors. Next, assume that ωT << 1 and find H(s). What type of secondorder circuit is
this?
+

Vin
φ
2
φ
1
1
φ 2
φ
1
φ
φ
2
C
1 C
A
Vout
φ
2
φ
1
φ
2
φ
1
C
3 C
B
C
2
C
4
A1 A2
Figure P9.64
Solution
V
1
(z) =
.

}
`
z
z1
C
1
C
A
V
in
(z) 
.

}
`
z
z1
C
2
C
A
V
out
(z) 
C
4
C
A
V
out
(z) and V
out
(z) =
.

}
`
1
z1
C
3
C
A
V
1
(z)
Where V
1
(z) is the output of the first integrator. If α
1A
= C
1
/C
A
, α
3B
= C
3
/C
B
, α
2A
=
C
2
/C
A
, and α
4A
= C
4
/C
A
then we can write the following.
V
out
(z) =
.

}
` α
3B
z1
]
]
]

α
1A
z
z1
V
in
(z) 
α
2A
z
z1
V
out
(z)  α
4A
V
out
(z)
∴ V
out
(z)
]
]
]
1 +
α
2A
α
3B
z
(z1)
2
+
α
3B
α
4A
z
z1
=
α
1A
α
3B
z
(z1)
2
V
in
(z)
H(z) =
V
out
(z)
V
in
(z)
=
α
1A
α
3B
z
(z1)
2
+α
2A
α
3B
z+(z1)α
3B
α
4A
=
α
1A
α
3B
z
z
2
+(α
2A
α
3B
+α
3B
α
4A
2)z +(1α
3B
α
4A
)
If ωT= sT<<1, then z ≈ 1 unless there are terms like (z1) in which case z1 ≈ sT.
Therefore,
H(s) ≈
α
1A
α
3B
s
2
T
2
+sTα
3B
α
4A
+α
2A
α
3B
=

α
1A
α
3B
T
2
s
2
+s
α
3B
α
4A
T
+α
2A
α
3B
=

C
1
C
3
C
A
C
B
1
T
2
s
2
+s
C
3
C
4
C
B
C
A
1
T
+
C
2
C
3
C
A
C
B
This circuit is a secondorder bandpass transfer function.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 945
Problem 9.605
Find the zdomain transfer function H(z) = V
out
(z)/V
in
(z) in the form of
H(z) = 
]
]
] a
2
z
2
+ a
1
z + a
0
z
2
+ b
1
z + b
0
for the switched capacitor circuit shown below. Evaluate the a
i
's and b
i
's in terms
of the capacitors. Next, assume that ωT << 1 and find H(s). What type of circuit is this?
+

Vin
φ
2
φ2
φ
1
C
4
C
1
C
A
Vout
φ
2
φ
1
φ
2
φ
1
C
2 C
B
C
3
A1 A2
C
5
V
A
φ
2
φ
1
φ
1
Solution
For the output voltage of the first integrator, V
A
, we can write,
V
A
= f
1
(V
A
,V
in
,V
out
) =
C
1
C
A
.

}
`
z
z1
V
in

C
5
C
A
.

}
`
z
z1
V
out

C
4
C
A
V
out
Similarily for the output voltage of the second integrator, V
out
, we can write,
V
out
= f
2
(V
A
,V
in
) =
C
2
C
B
.

}
`
1
z1
V
A

C
3
C
B
V
in
Combining equations gives,
V
out
=
z
(z1)
2
.

}
`
C
2
C
5
C
A
C
B
V
out

z
(z1)
2
.

}
`
C
1
C
2
C
A
C
B
V
in

1
z1
.

}
`
C
2
C
4
C
A
C
B
V
out

C
3
C
B
V
in
V
out
]
]
]
1 +
z
(z1)
2.

}
`
C
2
C
5
C
A
C
B
+
1
z1
.

}
`
C
2
C
4
C
A
C
B
= 
]
]
] z
(z1)
2.

}
`
C
1
C
2
C
A
C
B

C
3
C
B
V
in
V
out
]
]
(z1)
2
+ (z1)
.

}
`
C
2
C
4
C
A
C
B
+ z
.

}
`
C
2
C
5
C
A
C
B
= 
]
]
(z1)
2
C
3
C
B
+ z
.

}
`
C
1
C
2
C
A
C
B
V
in
∴
V
out
(z)
V
in
(z)
=

]
]
C
3
C
B
z
2
+
.

}
`
C
1
C
2
C
A
C
B
 2
C
3
C
B
z +
C
3
C
B
z
2
+
.

}
`
C
2
(C
4
+C
5
)
C
A
C
B
 2 z +
.

}
`
1 
C
2
C
4
C
A
C
B
= 
]
]
] a
2
z
2
+a
1
z+a
0
z
2
+b
1
z+b
0
Thus,
a
2
=C
3
/C
B
, a
1
=
C
1
C
2
C
A
C
B

2C
3
C
B
, a
0
=C
3
/C
B
, b
1
=
C
2
(C
4
+C
5
)
C
A
C
B
 2 and b
0
=1
C
2
C
4
C
A
C
B
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 946
Problem 9.606
Find the zdomain transfer function H(z) = V
out
(z)/V
in
(z) in the form of
H(z) = 
]
]
] a
2
z
2
+ a
1
z + a
0
z
2
+ b
1
z + b
0
for the switched capacitor circuit shown below. Evaluate the a
i
's and b
i
's in terms of the
capacitors. Next, assume that ωT << 1 and find H(s). What type of circuit is this? What
is the pole frequency, ω
o
, and pole Q?
+

+

v
in
φ
1
φ
2
φ
1
φ
1
φ
1
φ
1
φ
2
φ
2
φ
2
φ
2
G
C
D
A
E
B
v
out v'
Solution
V’(z) = 
.

}
`
G
D
z
z1
V
in
(z) 
.

}
`
C
D
z
z1
V
out
(z) 
.

}
`
E
D
V
out
(z)
V
out
(z) =
A
B
V’
z1
=
A
B
z
z1
]
]

.

}
`
G
D
z
z1
V
in
(z) 
.

}
`
C
D
z
z1
V
out
(z) 
.

}
`
E
D
V
out
(z)
= 
AG
BD
z
(z1)
2
V
in
(z) 
AC
BD
z
(z1)
2
V
out
(z) 
AE
BD
V
out
(z)
z1
V
out
(z)
]
]
1 +
AE
BD
1
z1
+
A C
BD
z
(z1)
2
= 
AG
BD
z
(z1)
2
V
in
(z)
∴
V
out
(z)
V
in
(z)
=

AG
BD
z
(z1)
2
+
AE
BD
(z1)+
AC
BD
z
→
V
out
(z)
V
in
(z)
=

AG
BD
z
z
2
+
.

}
`
AE
BD
+
AC
BD
2 z+
.

}
`
1
AE
BD
Thus, a
2˚
= a
0
= 0, a
1
=
A G
BD
, b
1
=
A E
BE
+
A C
BD
 2, and b
0
= 1 
A E
BD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 947
Problem 9.607
The switched capacitor circuit shown below realizes the following zdomain transfer
function
H(z) = 
.

}
` a
2
z
2
+ a
1
z + a
0
b
2
z
2
+ b
1
z + 1
where
C
6
=a
2
/b
2
, C
5
=(a
2
a
0
)/b
2
C
3
, C
1
=
a
0
+a
1
+a
2
b
2
C
3
, C
4
=
1(b
0
/b
2
)
C
3
and C
2
C
3
=
1+b
1
+b
2
b
2
. Design
a switched capacitor realization for the function
H(s) =
10
6
s
2
+ 100s + 10
6
where the clock frequency is 10 kHz. Use the bilinear transformation, s =
(2/T)[(z1)/(z+1)], to map H(s) to H(z). Choose C
2
= C
3
and assume that C
A
= C
B
= 1.
+

Vin
φ
2
φ
1
1
φ 2
φ
1
φ
φ
2
C
6
C
1 C
A
Vout
φ
2
φ
1
φ
2
φ
1
C
3 C
B
C
5
C
2
C
4
A1 A2
C
1
"
Figure P9.67
C
1
"
Solution
Apply the bilinear transformation
s =
2
T
.

}
`
z  1
z+1
= 2x10
4
.

}
`
z  1
z+1
to H(s) to get,
H(z) =
10
6
4x10
8
.

}
`
z  1
z+1
2
+200x10
4
.

}
`
z  1
z+1
.

}
`
z+1
z+1
+10
6
.

}
`
z+1
z+1
2
=
10
6
(z
2
+2z+1)
4x10
8
(z
2
2z+1)+2x10
6
(z
2
1)+10
6
(z
2
+2z+1)
=
(10
6
z
2
+2x10
6
z+10
6
)
(4x10
8
+2x10
6
+10
6
)z
2
+(8x10
8
+2x10
6
)z+(4x10
8
2x10
6
+10
6
)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 948
Problem 9.607  Continued
=
(10
6
z
2
+2x10
6
z+10
6
)
4.03x10
8
z
2
7.98x10
8
z+3.99x10
8
=
(0.002506z
2
+0.005013z+0.002506)
1.010025z
2
2.0000z+1
Now equating to the coefficients,
C
6
=
a
2
b
2
=
0.002506
1.010025
= 0.002481, C
5
=
a
2
a
0
b
2
C
3
= 0,
C
2
C
3
=
1+b
1
+b
2
b
2
=
1+(2)+1.010025
1.010025
= 0.009925 ⇒ C
2
=C
3
= 0.099627
C
1
=
a
0
+b
1
+b
2
b
2
C
3
=
0.002506+0.005013+0.002506
1.010025·0.0099627
= 0.099633
C
4
=
1+(b
0
/b
2
)
C
3
=
1(1/1.010025)
0.099627
= 0.099627
∴ C
1
=0.099633, C
2
=C
3
=0.099627, C
4
=0.099627, C
5
=0, C
6
= 0.002481
C
max
/C
min
= 1/0.002625 = 403.06
Normalize all capacitors by 0.002625 to get
ΣC
µ
= [(403.6)2+(37.953)2+37.953+37.955+1] = 958.9 C
µ
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 949
Problem 9.701
Find the minimum order of a Butterworth and Chebyshev filter approximation to a filter
with the specifications of T
PB
= 3dB, T
SB
= 40dB, and Ω
n
= 2.0.
Solution
For the Butterworth approximation, use Eq. (9.77) and for the Chebyshev approximation
use Eq. (9.712), both with ε = 1. The results are shown below.
Ν T
SB
(dB) = 10log
10
(1+2
2N
) T
SB
(dB) = 10log
10
[1+cosh
2
(Ncosh
1
2)]
1 6.99 dB 6.99 dB
2 12.30 dB 16.99 dB
3 18.13 dB 28.31 dB
4 24.10 dB 39.74 dB
5 30.11 dB 51.17 dB
6 36.12 dB
7 42.14 dB
The minimum order for the Butterworth is 7 while the minimum order for the Chebyshev i
5 and in many cases 4 would work.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 950
Problem 9.702
Find the transfer function of a fifthorder, Butterworth filter approximation expressed as
products of first and secondorder terms. Find the pole frequency, ω
p
and the Q for each
secondorder term.
Solution
From Table 9.71 we get,
T(s) =
1
(s+1)(s
2
+0.61804s+1)(s
2
+1.84776s+1)
The pole frequency and Q for a general second order term of (s
2
+a
1
s+1) is
ω
p
= 1 and Q =
1
a
1
For both second order terms, the pole frequency is 1 radian/sec.
For the first secondorder term, the Q = 1.61804.
For the second, secondorder term, the Q = 0.541196.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 951
Problem 9.703
Redesign the second stage of Ex. 9.75 using the highQ biquad and find the total
capacitance required for this stage. Compare with the example.
Solution
T
n2
(s
n
) =
0.9883
s
n
2
+ 0.1789s
n
+ 0.9883
⇒ ω
n2
= 0.9941 and Q
2
= 5.557
For the lowpass highQ biquad, K
1
= K
2
= 0 ⇒ α
32
= α
62
= 0 and K
0
= ω
n2
2
∴ α
22
= α
52
 = ω
n2
T
n
= 0.9941
ω
PB
f
c
= 0.3123
α
12
=
ω
n2
2
T
n
ω
n2
= ω
n2
T
n
= 0.3123
α
42
=
1
Q
= 0.1800
Schematic of the secondstage:
+

V
1
(z)
C
12
V
in
(z)
e
φ
1
φ
1
φ
2
φ
2
α
22
C
12
α
12
C
12
φ
2
+

C
22
φ
2
α
42
C
2
φ
2
α
25
C
22
φ
1
V
out
(z)
e e
Figure S9.703
φ
1
φ
1
Total capacitance is:
ΣC =
.

}
`
1 +
2(0.3123)
0.1880
+
1
0.1800
+
.

}
`
1 +
1
0.3123
= 10.027+4.202 = 14.229 C
µ
Note that this value is 17.32 when a lowQ stage is used.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 952
Problem 9.704
Design a cascaded, switched capacitor, 5thorder, lowpass filter using the cascaded
approach based on the following lowpass, normalized prototype transfer function.
H
lpn
(s
n
) =
1
(s
n
+1)(s
n
2
+0.61804s
n
+1)(s
n
2
+1.61804s
n
+1)
The passband of the filter is to 1000Hz. Use a clock frequency of 100kHz and design each
stage giving the capacitor ratios as a function of the integrating capacitor (the unswitched
feedback capacitor around the op amp), the maximum capacitor ratio, and the units of
normalized capacitance, C
u
. Give a schematic of your realization connecting your lowest Q
stages first. Use SPICE to plot the frequency response (magnitude and phase) of your
design and the ideal continuous time filter.
Solution
Stage 1, FirstOrder Stage (Use Fig. 9.51):
T
1
(s
n
) =
α
11
/α
21
(s
n
T
n
/α
21
) +1
=
1
s
n
+1
⇒ α
11
= α
21
and α
21
= T
n
α
11
= α
21
= T
n
=
ω
PB
f
c
=
2000π
100,000
= 0.06283
C
max
C
min
=
1
0.06283
= 15.92 and ΣC = 2 +
1
0.06283
= 19.92 C
µ
Stage 2, Secondorder Stage (Use LowQ Lowpass Biquad):
T
2
(s
n
) =
1
s
n
2
+1.61804s
n
+1
⇒ ω
n2
= 1 rad/sec and Q
2
= 0.61804
From the lowQ biquad relationships, K
1
= K
2
= 0 ⇒ α
32
= α
42
= 0
α
22
= α
52
 = ω
n
T
n
= 0.06283 and α
62
=
ω
n
T
n
Q
2
=
0.06283
0.61804
= 0.1017
C
max
C
min
=
1
0.1017
= 9.837
and ΣC =
.

}
`
2 +
1
0.06283
+
.

}
`
1
0.06283
+
0.1017
0.06283
+1 = 36.45 C
µ
Stage 3, Secondorder Stage (Use LowQ Lowpass Biquad):
T
3
(s
n
) =
1
s
n
2
+0.61804s
n
+1
⇒ ω
n2
= 1 rad/sec and Q
2
= 1.6180
From the lowQ biquad relationships, K
1
= K
2
= 0 ⇒ α
33
= α
43
= 0
α
23
= α
53
 = ω
n
T
n
= 0.06283 and α
62
=
ω
n
T
n
Q
2
=
0.06283
1.6180
= 0.0391
C
max
C
min
=
1
0.0391
= 25.59
and ΣC =
.

}
`
2 +
1
0.06283
+
.

}
`
1
0.0391
+
0. 06283
0.0391
+1 = 46.10 C
µ
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 953
Problem 9.704 – Continued
Schematic:
+

φ
1
φ
1
φ
2
φ
2
α
11
C
11 φ
1
φ
2
α
21
C
11
C
11
φ
2
φ
1
φ
1
φ
2
α
12
C
12
+

C
12
φ
1
φ
1
φ
2
φ
2
α
52
C
22
+

C
22 φ
2
φ
1
α
62
C
22
α
22
C
22
φ
2
φ
1
φ
1
φ
2
α
13
C
13
+

C
13
φ
1
φ
1
φ
2
φ
2
α
53
C
23
+

C
23 φ
2
φ
1
α
63
C
23
α
23
C
23
V
out
V
in
Fig. S9.74A
SPICE File:
*** HW9 PROBLEM2 (Problem 9.74) ***
*** Node 21 and 22 are outputs
VIN 1 0 DC 0 AC 1
*** STAGE1 ***
XNC11 1 2 3 4 NC1
XUSCP11 3 4 5 6 USCP
XPC21 5 6 3 4 PC1
XAMP11 3 4 5 6 AMP
*** STAGE2 ***
XPC12 5 6 7 8 PC1
XUSCP12 7 8 9 10 USCP
XPC22 7 8 13 14 PC1
XAMP12 7 8 9 10 AMP
XNC52 9 10 11 12 NC1
XUSCP22 11 12 13 14 USCP
XPC62 11 12 13 14 PC2
XAMP22 11 12 13 14 AMP
*** STAGE3 ***
XPC13 13 14 15 16 PC1
XPC23 15 16 21 22 PC1
XUSCP43 15 16 21 22 USCP1
XUSCP13 15 16 17 18 USCP
XAMP13 15 16 17 18 AMP
XNC53 17 18 19 20 NC1
XUSCP23 19 20 21 22 USCP
XAMP23 19 20 21 22 AMP
*** SUB CIRCUITS ***
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5US
RDO 3 0 1K
.ENDS DELAY
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 954
Problem 9.705
Repeat Problem 9.73 for a 5thorder, highpass filter having the same passband frequency.
Use SPICE to plot the frequency response (magnitude and phase) of your design and the
ideal continuous time filter.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 955
Problem 9.706
Repeat Problem 9.73 for a 5thorder, bandpass filter having center frequency of 1000Hz
and a 3dB bandwidth of 500Hz. Use SPICE to plot the frequency response (magnitude
and phase) of your design and the ideal continuous time filter.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 956
Problem 9.707
Design a switched capacitor 6thorder, bandpass filter using the cascaded approach and
based on the following lowpass, normalized prototype transfer function.
H
lpn
(s
n
) =
2
(s
n
+1)(s
n
2
+2s
n
+2)
The center frequency of the bandpass filter is to be 1000Hz with a bandwidth of 100Hz.
Use a clock frequency of 100kHz. Design each stage given the capacitor ratios as a
function of the integrating capacitor (the unswitched feedback capacitor around the op
amp), the maximum capacitor ratio and the units of normalized capacitance, C
u
. Give a
schematic of your realization connecting your lowest Q stages first. Use SPICE to plot the
frequency response (magnitude and phase) of your design and the ideal continuous time
filter.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 957
Problem 9.708
Design a switched capacitor, thirdorder, highpass filter based on the lowpass normalized
prototype transfer function of Problem 9.77. The cutoff frequency (f
PB
), is to be
1000Hz. Design each stage given the capacitor ratios as a function of the integrating
capacitor (the unswitched feedback capacitor around the op amp), the maximum capacitor
ratio and the units of normalized capacitance, C
u
. Give a schematic of your realization
connecting your lowest Q stages first. Use SPICE to plot the frequency response
(magnitude and phase) of your design and the ideal continuous time filter.
Solution
TBD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 958
Problem 9.709
Design a switched capacitor, thirdorder, highpass filter based on the following
lowpass, normalized prototype transfer function.
H
lpn
(s
n
) =
0.5(s
n
2
+4)
(s
n
+1)(s
n
2
+2s
n
+2)
The cutoff frequency (f
PB
), is to be 1000Hz. Use a clock frequency of 100kHz. Design
each stage given the capacitor ratios as a function of the integrating capacitor (the
unswitched feedback capacitor around the op amp), the maximum capacitor ratio and the
units of normalized capacitance, C
u
. Give a schematic of your realization connecting your
lowest Q stages first. Use the lowQ biquad given below for the secondorder stage. The
approximate sdomain transfer function for the lowQ biquad is,
H
ee
(s
n
) =

]
]
]
α
3
s
n
2
+
s
n
α
4
T
n
+
α
1
α
5
T
n
2
s
n
2
+
s
n
α
6
T
n
+
α
2
α
5
T
n
2
+

V
1
(z)
C
1
Low Q, switched capacitor, biquad realization.
V
in
(z)
e
φ
1
φ
1
φ
1
φ
2
φ
2
α
2
C
1
α
1
C
1
φ
2
+

C
2
φ
2
α
6
C
2
α
4
C
2
φ
2
α
5
C
2
φ
1
V
out
(z)
e
α
3
C
2
e
φ
1
Solution
Perform a normalized lowpass to normalized highpass transformation:
H
hpn
(s
n
) =
0.5
.

}
`
1
s
n
2
+4
.

}
`
1
s
n
+1
.

}
`
1
s
n
2
+
2
s
n
+2
=
0.5s
n
(4s
n
2
+1)
(s
n
+1)(1+2s
n
+2s
n
2
)
=
.

}
`
s
n
s
n
+1
.

}
` s
n
2
+0.25
s
n
2
+s
n
+0.5
Firstorder stage design:
Equating currents at the inverting input of the op
amp gives,
α
11
(1z
1
)V
e
in
(z) + α
21
V
e
o1
(z) + (1z
1
)V
e
o1
(z) = 0
Solving for the H
ee
(z) tranfer function gives,
+

V
in
φ
2
V
o1
α
11
C
11
C
11
φ
1
φ
1
φ
2
α
21
C
11
S01E3S1A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 959
Problem 9.709  Continued
H
ee
(z) =
V
e
o1
(z)
V
e
in
(z)
 =
α
11
(1z
1
)
α
21
+ (1z
1
)
→ H
ee
(s
n
) ≈
V
e
o1
(s
n
)
V
e
in
(s
n
)
 =
α
11
s
n
T
n
α
21
+s
n
T
n
=
α
11
s
n
s
n
+
α
21
T
n
Equating with the normalized highpass transfer function gives,
α
11
= 1 and α
21
= T
n
=
ω
PB
f
c
=
2000π
100,000
= 0.06283
ΣC
µ
=
2
0.06283
+ 1 = 32.832C
µ
Next, consider the secondorder stage design:
Equating H
ee
(s) with
.

}
` s
n
2
+0.25
s
n
2
+s
n
+0.5
gives,
α
32
= 1 , α
42
= 0 , α
12
α
52
= 0.25T
n
2
, α
62
=T
n
=
2000π
100,000
= 0.06823 and α
22
α
52
=
T
n
2
2
Let α
22
= α
52
, then α
22
= α
52
=
T
n
2
=
ω
PB
2f
c
=
2000π
2 100,000
= 0.04443
Therefore, α
12
=
T
n
2
4α
52
=
2T
n
4
= 0.02221
ΣC
µ
=
]
]
.

}
`
1+
0.04443
0.2221
+
1
0.02221
+
.

}
`
1+
0.06283
0.04443
+
2
0.04443
= 48.025+47.4287
Total ΣC
µ
= 32.832 + 48.025 + 47.429 = 127.84 C
µ
C
max
/C
min
= 1/0.02221 = 45.025
Filter schematic:
+

V
in
φ
2
V
o1
α
11
C
11
C
11
φ
1
φ
1
φ
2
α
21
C
11
S01E3S1B
+

V
1
(z)
C
12
φ
1
φ
1
φ
2
φ
2
α
22
C
12
α
12
C
12
φ
2
+

C
22
φ
2
α
62
C
22
φ
2
α
52
C
22
φ
1
V
out
(z)
e
α
32
C
22
e
φ
1
φ
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 960
Problem 9.709 – Continued
.SUBCKT NC1 1 2 3 4
RNC1 1 0 15.916
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.06283
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.06283
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.06283
RNC2 4 0 15.916
.ENDS NC1
.SUBCKT PC1 1 2 3 4
RPC1 2 4 15.916
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 9.8328
.ENDS PC2
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT USCP1 1 2 3 4
R1 1 3 1.6181
R2 2 4 1.6181
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 0.6180
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 0.6180
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 0.6180
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 0.6180
.ENDS USCP1
.SUBCKT AMP 1 2 3 4
EODD 0 3 1 0 1E6
EVEN 0 4 2 0 1E6
.ENDS AMP
*** ANALYSIS ***
.AC DEC 1000 10 99K
.PROBE
.END
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 961
Problem 9.710
Write the minimum set of state equations for each of the circuits shown below. Use
voltage analogs of current (R=1Ω). The state equations should be in the form of the state
variable equal to other state variables, including itself.
Solution
(a) V
1
=
1
s
n
C
1n
]
]
V
in
R
0n

V
1
R
0n
 V
2
'
V
2
’ =
1
s
n
L
2n
(V
1
 V
out
)
V
out
=
1
s
n
C
3n
]
]
V
2
' 
V
out
R
4n

V
1
R
0n
∴ V
1
’ =
1
s
n
L
1bn
+
1
s
n
C
1n
[ V
1
–
V
out
]
=
s
n
L
1bn
s
n
2
+ 1
[ V
1
– V
out
]
V
out
=
1
s
n
C
2bn
+
1
s
n
L
2bn
.

}
`
V
1
’
V
out
R
4n
=
s
n
C
2bn
s
n
2
+ 1
.

}
`
V
1
’
V
out
R
4n
∴ The simplest way to work this one is make the following transformation (see pp.
228230 of Switched Capacitor Circuits, P.E. Allen and E.S. Sanchez, Van
Nostrand Reinhold,1984).
V
in
R
0n
C
1n
V
out
C
3n
R
3n
+

L
2n
C
2n
V
in
R
0n
C
2n
C
1n
+C
2n
V
out
L
2n
C
2n
C
2n
+C
3n
V
1
V
out
+

R
3n
C
1n
+C
2n
C
2n
+C
3n
V
1
I
2
Fig. S9.710C
V
1
=
1
s
n
(C
1n
+ C
2n
)
]
]
V
in
R
0n

V
1
R
0n
 V
2
' +
C
2n
C
1n
+ C
2n
V
out
V
2
’ =
1
s
n
L
2n
(V
1
 V
out
)
V
out
=
1
s
n
(C
2n
+ C
3n
)
]
]
V
2
' 
V
out
R
3n
+
C
2n
C
2n
+ C
3n
V
out
V
in
V
out
R
0n
C
1n
C
3n
L
2n
R
4n
+

Fig. S9.710A
+

V
1
I
2
V
in
V
out
C
1bn
L
1bn
R
3n
+

Fig. S9.710B
I
1
C
2bn
L
2bn
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 962
Problem 9.711
Give a continuous time and switched capacitor implementation of the following state
equations. Use minimum number of components and show the values of the capacitors
and the phasing of each switch (φ
1
and φ
2
). Give capacitor values in terms of the
parameters of the state equations and Ω
n
and f
c
for the switched capacitor implementations.
1.) V
1
=
1
sK
[ ]
α
1
V
1
+ α
2
V
2
 α
3
V
3
2.) V
1
=
s
s
2
+1
[ ]
α
1
V
1
+ α
2
V
2
 α
3
V
3
∴ V
1
=
1
sK[ ]
α
1
V
1
+ α
2
V
2
+ α
3
V
3
Solution
1.)
R
1
=1/α
1
+

a
1
C C
φ
2
φ
1
φ
2
V
1
+

C = K
V
1
+

V
1
V
2
V
3
R
2
=1/α
2
R
3
=1/α
3
R R
V
1
a
2
C
φ
1
φ
2
V
2
a
3
C
φ
2
φ
1
V
3
φ
1
a
1
=
α
1
T
n
K
a
2
=
α
2
T
n
K
a
3
=
α
3
T
n
K
Fig. S9.711A
2.)
R
1
=1/α
1
+

C = 1
V
1
+

V
1
V
2
V
3
R
2
=1/α
2
R
3
=
1/α
3
R R
Fig. S9.711B
+

+

C = 1
R
R
R=1
R=1
a
1
C
φ
2
φ
1
φ
2
V
1
a
2
C
φ
1
φ
2
V
2
a
3
C
φ
2
φ
1
V
3
φ
1
+

+

φ
2
φ
1
φ
2
φ
1
φ
2
φ
1
φ
1
φ
2
T
n
C
T
n
C
C = 1
C = 1
a
1
= α
1
T
n
a
2
= α
2
T
n
a
3
= α
3
T
n
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 963
Problem 9.711  Continued
3.)
R
1
=1/α
1
+

C = K
V
1
+

V
1
V
2
V
3
R
2
=1/α
2
C
3
=
1/α
3
R R
Fig. S9.711C
+

R R
+

a
1
C
C
φ
2
V
1
V
1
a
2
C
φ
1
φ
2
V
2
a
3
C
φ
2
φ
1
V
3
φ
1
a
1
=
α
1
T
n
K
a
2
=
α
2
T
n
K
a
3
= α
3
+

C
C
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 964
Problem 9.712
Find a switched capacitor, realization of
the lowpass normalized RLC ladder
filter shown. The cutoff frequency of
the lowpass filter is 1000Hz and the
clock frequency is 100kHz. Give the
value of all capacitors in terms of the
integrating capacitor of each stage and
show the correct phasing of switches.
What is the C
max
/C
min
and the total units of capacitance for this filter? Use SPICE to plot
the frequency response (magnitude and phase) of your design and the ideal continuous time
filter.
Solution
The state equations are:
V
s
= I
1
R
on
+sL
1n
I
1
+V
2
→ I
1
=
1
sL
1n
.

}
`
V
s

RI
1
R
on
R
V
2
→ V
1
’=
R
sL
1n
.

}
`
V
s

V
1
'R
on
R
V
2
I
1
 I
3
= sC
2n
V
2
→ V
1
’
V
3
’ = sRC
2n
V
2
→ V
2
=
1
sRC
2n
(V
1
’
V
3
’)
V
2
= sL
3n
I
3
+
I
3
R
4n
→ I
3
=
1
sL
3n
(V
2
 I
3
R
4n
) → V
3
’ =
R
sL
3n
.

}
`
V
2

R
4n
R
V
3
'
But, V
out
= I
3
R
4n
= V
3
’
R
4n
R
→ V
3
’ =
R
R
4n
V
out
→ V
out
=
R
4n
sL
3n
(V
2
V
out
)
Normalized realizations:
V
1
’ ≈
1
sT
n
[α
11
V
s
 α
21
V
1
’  α
31
V
2
]
Comparing with the first state equation:
α
11
T
n
=
R
L
1n
→ α
11
=
RT
n
L
1n
=
RΩ
n
f
c
L
1n
=
1·2000π
10
5
·1
α
11
= π/50 = 0.0628 = α
21
α
31
T
n
=
R
on
L
1n
→ α
31
=
R
on
Ω
n
f
c
L
1n
= α
11
= 0.0628
V
2
≈
1
sT
n
[α
12
V
1
’  α
22
V
out
]
Comparing with the second state equation:
α
12
T
n
=
1
RC
2n
→ α
12
=
T
n
RC
2n
=
Ω
n
Rf
c
C
2n
=
1·2000π
1·2·10
5
α
12
= π/100 = 0.0314 = α
22
R
0n
=1Ω L
1n
=1H
R
4n
=1Ω
C
2n
= 2F
+

V
in
(s
n
) V
out
(s
n
)
L
3n
=2H
Figure P9.712
V
1
'
Fig. S9.712B
+

V
2
C
1
V
s
φ
2
φ
1
φ
1
φ
2
φ
1
α
21
C
1
α
11
C
1
φ
2
φ
1
α
31
C
1
φ
2
V
1
'
V
1
'
Fig. S9.712C
+

V
out
C
2
φ
2
φ
1
φ
1
φ
2
φ
1
α
22
C
2
α
12
C
2
φ
2
V
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 965
Problem 9.712 – Continued
V
out
≈
1
sT
n
[α
13
V
2
 α
23
V
out
]
Comparing with the third state equation:
α
13
T
n
=
1
R
4n
L
3n
α
13
=
T
n
R
4n
L
3n
=
Ω
n
R
4n
f
c
L
3n
=
1·2000π
1·10
5
α
13
= π/50 = 0.0628 = α
23
Connect the above three circuits together to get the resulting filter.
The C
max
/C
min
= 1/α
12
= 31.83 . The units of capacitances normalized to each integrating
capacitor is 3 + (1/0.0628) = 18.91 for the first stage, 2 + (1/0.0314) = 33.83 for the
second stage and 2 + (1/0.0628) = 17.91for the third stage. The total units of capacitance
for this filter is 70.66 units .
The SPICE simulation file for this filter is shown below.
SPICE File for Problem 9.712
*** Node 13 and 14 are Switched Cap outputs
*** Node 23 is RLC ladder network output
VIN 1 0 DC 0 AC 1
*** V1' STAGE ***
XNC11 1 2 3 4 NC1
XPC21 9 10 3 4 PC1
XPC31 5 6 3 4 PC1
XUSCP1 3 4 5 6 USCP
XAMP1 3 4 5 6 AMP
*** V2 STAGE ***
XNC12 5 6 7 8 NC2
XPC22 13 14 7 8 PC2
XUSCP2 7 8 9 10 USCP
XAMP2 7 8 9 10 AMP
*** VOUT STAGE ***
XNC13 9 10 11 12 NC1
XPC23 13 14 11 12 PC1
XUSCP3 11 12 13 14 USCP
XAMP3 11 12 13 14 AMP
*** RLC LADDER NETWORK ***
R1 1 21 50
L1 21 22 7.9577E3
C2 22 0 6.3662E6
L3 22 23 7.9577E3
R2 23 0 50
**************************
*** SUB CIRCUITS ***
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC1 1 2 3 4
RNC1 1 0 15.9155
V
2
Fig. S9.712D
+

V
out
C
3
φ
2
φ
1
φ
1
φ
2
φ
1
α
23
C
3
α
13
C
3
φ
2
V
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 966
Problem 9.712 – Continued
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.062832
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.062832
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.062832
RNC2 4 0 15.9155
.ENDS NC1
.SUBCKT NC2 1 2 3 4
RNC1 1 0 31.831
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.031416
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.031416
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.031416
RNC2 4 0 31.831
.ENDS NC2
.SUBCKT PC1 1 2 3 4
RPC1 2 4 15.9155
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 31.831
.ENDS PC2
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT AMP 1 2 3 4
EODD 0 3 1 0 1E6
EVEN 0 4 2 0 1E6
.ENDS AMP
*** ANALYSIS ***
.AC DEC 100 10 199K
.PRINT AC VDB(13) VDB(14) VDB(23) VP(13) VP(14) VP(23)
.END
140
120
100
80
60
40
20
0
100 1000 10k 100k
Frequency (Hz)
M
a
g
n
i
t
u
d
e
d
B
Switched
Capacitor
Continuous
Time
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 967
Problem 9.713
Design a switched capacitor realization
of the lowpass prototype filter shown
in Fig. 9.713 assuming a clock
frequency of 100 kHz. The passband
frequency is 1000Hz. Express each
capacitor in terms of the integrating
capacitor C. Be sure to show the
phasing of the switches using φ
1
and φ
2
notation. What is the total capacitance in terms of
a unit capacitance, C
u
? What is C
max
/C
min
? Use SPICE to plot the frequency response
(magnitude and phase) of your design and the ideal continuous time filter.
Solution
The state equations are:
V
in
= I
1
R
on
+sL
1n
I
1
+V
out
→ V
1
’=
R
sL
1n
.

}
`
V
i n

V
1
'R
on
R
V
out
I
1

V
out
R
3n
= sC
2n
V
out
→ V
out
=
1
sRC
2n
(V
1
’

R
R
3n
V
out
)
The normalized realizations for these equations are:
V
1
’ ≈
1
sT
n
[α
11
V
in
 α
21
V
1
’  α
31
V
out
]
Comparing with the first state equation:
α
11
T
n
=
R
L
1n
→ α
11
=
RT
n
L
1n
=
RΩ
n
f
c
L
1n
=
1·2000π
10
5
· 2
α
11
= 0.04443 = α
21
α
31
T
n
=
R
on
L
1n
→ α
31
=
R
on
Ω
n
f
c
L
1n
= α
11
=
0.04443
V
out
≈
1
sT
n
[α
12
V
1
’  α
22
V
out
]
Comparing with the second state equation:
α
12
T
n
=
1
RC
2n
→ α
12
=
T
n
RC
2n
=
Ω
n
Rf
c
C
2n
=
1·2000π
1·10
5
· 2
α
12
= 0.04443 = α
22
Connect the above two circuits together to get the resulting filter.
+

+

V
in
(s
n
)
V
out
(s
n
)
R
3n
=1Ω
R
0n
=1Ω
L
1n
= 2H
C
2n
=
2F
I
1
Fig. S9.713A
V
1
'
Fig. S9.713B
+

V
out
C
1
V
in
φ
2
φ
1
φ
1
φ
2
φ
1
α
21
C
1
α
11
C
1
φ
2
φ
1
α
31
C
1
φ
2
V
1
'
V
1
'
Fig. S9.713C
+

V
out
C
2
φ
2
φ
1
φ
1
φ
2
φ
1
α
22
C
2
α
12
C
2
φ
2
V
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 968
Problem 9.713 – Continued
The C
max
/C
min
= 1/α
12
= 22.508 . The units of capacitances normalized to each integrating
capacitor is 3 + (1/0.04443) = 25.51 for the first stage and 2 + (1/0.0314) = 24.51 for the
second stage. The total units of capacitance for this filter is 50.158 units .
The SPICE simulation file for this filter is shown below.
SPICE File for Problem 9.713
*** Node 9 and 10 are Switched Cap outputs
*** Node 22 is RLC ladder network output
VIN 1 0 DC 0 AC 1
*** V1' STAGE ***
XNC11 1 2 3 4 NC1
XPC21 5 6 3 4 PC1
XPC31 9 10 3 4 PC1
XUSCP1 3 4 5 6 USCP
XAMP1 3 4 5 6 AMP
*** VOUT STAGE ***
XNC12 5 6 7 8 NC2
XPC22 9 10 7 8 PC2
XUSCP2 7 8 9 10 USCP
XAMP2 7 8 9 10 AMP
*** RLC LADDER NETWORK ***
R1 1 21 50
L1 21 22 11.254E3
C2 22 0 4.50158E6
R2 22 0 50
**************************
*** SUB CIRCUITS ***
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC1 1 2 3 4
RNC1 1 0 22.5079
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.04443
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.04443
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.04443
RNC2 4 0 22.5079
.ENDS NC1
.SUBCKT NC2 1 2 3 4
RNC1 1 0 22.5079
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.04443
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.04443
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.04443
RNC2 4 0 22.5079
.ENDS NC2
.SUBCKT PC1 1 2 3 4
RPC1 2 4 22.5079
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 22.5079
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 969
Problem 9.713
.ENDS PC2
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT AMP 1 2 3 4
EODD 0 3 1 0 1E6
EVEN 0 4 2 0 1E6
.ENDS AMP
*** ANALYSIS ***
.AC DEC 20 10 199K
.PRINT AC VDB(9) VDB(10) VDB(23) VP(9) VP(10) VP(23)
.END
100
80
60
40
20
0
100 1000 10k 100k
Frequency (Hz)
M
a
g
n
i
t
u
d
e
d
B
Switched
Capacitor
Continuous
Time
Fig. S9.713D
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 970
Problem 9.714
Design a switched capacitor realization of the lowpass prototype filter shown
assuming a clock frequency of 100 kHz. The passband frequency is 1000Hz. Express
each capacitor in terms of the integrating capacitor C. Be sure to show the phasing of the
switches using φ
1
and φ
2
notation. What is the total capacitance in terms of a unit
capacitance, C
u
? What is C
max
/C
min
?
Solution
First normalize T by Ω
n
=2000π to get T
n
=Ω
n
T = 2000π /100,000 = 0.06283
The state equations are:
V
in
= (I
2
+sC
1n
V
1
)R
0n
+ V
1
→ V
1
=
1
sR
0n
C
1n
]
]
V
i n
 V
1

R
0n
R
V
2
'
and
V
1
= I
2
sL
2n
+I
2
R
3n
→ V
1
=
sL
2n
R
+
R
3n
R
V
2
'
→ V
2
’
=
R
sL
2n
]
]
V
1

R
3n
R
V
2
'
Since V
2
’ = V
out
, we can write
V
out
=
R
sL
2n
]
]
V
1

R
3n
R
V
out
Realization of the first state equation:
V
1
(z) =
.

}
`
1
z
n
1
[α
11
V
in
 α
21
V
2
’
 α
31
V
1
]
Let z
n
≈ 1+s
n
T
n
to get
V
1
(s) =
1
s
n
T
n
[α
11
V
in
(s
n
) α
21
V
2
’
(s
n
) α
31
V
1
(s
n
)]
∴ α
11
=
RT
n
R
0n
C
1n
=
Ω
n
f
c
C
1n
=
2000π
2 10
5
= 0.0444
Since, R = R
0n
, then α
21
= α
31
= α
11
= 0.4444
Realization of the second state equation:
V
out
(z) =
.

}
`
1
z
n
1
[α
12
V
1
 α
22
V
2
’
]
Let z
n
≈ 1+s
n
T
n
to get
V
out
(s) =
1
s
n
T
n
[α
12
V
1
(s
n
) α
22
V
2
’
(s
n
)]
∴ α
12
=
T
n
L
2n
=
Ω
n
f
c
L
2n
=
2000π
2 10
5
= 0.0444
α
12
= α
22
= 0.4444
+

φ
1
α
11
C
1
φ
2
C
1
φ
2
V
in
V
1
φ
2
α
12
C
1
φ
1
V
2
'
φ
2
α
31
C
1
φ
1
V
1
φ
1
S01E3S2B
+

φ
1
α
12
C
2
φ
2
C
2
φ
2
V
2
'=V
out
φ
2
α
22
C
2
φ
1
V
2
'
V
1
φ
1
S01E3S2C
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 971
Problem 9.714 – Continued
C
max
C
min
=
1
0.0444
= 22.508
ΣC = [(22.508+3) + (22.508+2)]C
µ
= 50.0158 C
µ
Realization:
+

φ
1
φ
2
φ
2
V
in
V
1
+

φ
1
φ
2
25.508C
µ
φ
2
V
out
φ
2
C
µ
φ
1
φ
1
S01E3S2D
φ
2
φ
1
C
µ
C
µ
C
µ
C
µ 25.508C
µ
φ
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 972
Problem 9.715
Design a switched capacitor realization of the lowpass prototype filter shown below
assuming a clock frequency of 100 kHz. The passband frequency is 1000Hz. Express
each capacitor in terms of the integrating capacitor C. Be sure to show the phasing of the
switches using φ
1
and φ
2
notation. What is the total capacitance in terms of a unit
capacitance, C
u
? What is largest C
max
/C
min
? Use SPICE to plot the frequency response
(magnitude and phase) of your design and the ideal continuous time filter.
Solution
The state equations are:
V
in
= sL
1n
I
1
+ V
2
→ I
1
=
1
sL
1n
(V
in
 V
2
) → V
1
’ =
R
sL
1n
(V
i n
 V
2
)
V
2
=
1
sC
2n
(I
1
– I
3
) → V
2
=
1
sRC
2n
(V
1
’ –V
3
’) →
V
2
=
1
sRC
2n
.

}
`
V
1
' 
R
R
4n
V
2
I
3
=
1
sL
3n
(V
2
 V
out
) → V
out
= I
3
R
4n
→ V
out
=
R
4n
sL
3n
(V
2
 V
out
)
The normalized realizations for these equations are:
V
1
’ ≈
1
sT
n
[α
11
V
in
 α
21
V
2
]
Comparing with the first state equation:
α
11
T
n
=
R
L
1n
→ α
11
=
RT
n
L
1n
=
RΩ
n
f
c
L
1n
=
1·2000π
10
5
·0.5
α
11
= 0.125664 = α
21
V
out
≈
1
sT
n
[α
12
V
1
’  α
22
V
out
]
Comparing with the second state equation:
α
12
T
n
=
1
RC
2n
→ α
12
=
T
n
RC
2n
=
Ω
n
Rf
c
C
2n
=
2000π
10
5
·(4/3)
α
12
= 0.047124 = α
22
V
2
Fig. S9.715B
+

C
1
V
in
φ
2
φ
1
φ
1
φ
2
φ
1
α
21
C
1
α
11
C
1
φ
2
V
1
'
V
1
'
Fig. S9.715C
+

V
out
C
2
φ
2
φ
1
φ
1
φ
2
φ
1
α
22
C
2
α
12
C
2
φ
2
V
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 973
Problem 9.715 – Continued
V
out
≈
1
sT
n
[α
13
V
2
 α
23
V
out
]
Comparing with the third state equation:
α
13
T
n
=
1
R
4n
L
3n
α
13
=
T
n
R
4n
L
3n
=
Ω
n
R
4n
f
c
L
3n
=
2000π
10
5
(3/2)
α
13
= 0.041888 = α
23
Connect the above three circuits together to get the resulting filter.
The C
max
/C
min
= 1/α
13
= 23.87 . The units of capacitances normalized to each integrating
capacitor is 2 + (1/0.126) = 9.936 for the first stage, 2 + (1/0.0471) = 23.231 for the
second stage and 2 + (1/0.0419) = 25.8671for the third stage. The total units of
capacitance for this filter is 59.03 units .
The SPICE simulation file for this filter is shown below.
SPICE File for Problem 9.715
*** Node 13 and 14 are Switched Cap outputs
*** Node 22 is RLC ladder network output
VIN 1 0 DC 0 AC 1
*** V1' STAGE ***
XNC11 1 2 3 4 NC1
XPC21 9 10 3 4 PC1
XUSCP1 3 4 5 6 USCP
XAMP1 3 4 5 6 AMP
*** V2 STAGE ***
XNC12 5 6 7 8 NC2
XPC22 13 14 7 8 PC2
XUSCP2 7 8 9 10 USCP
XAMP2 7 8 9 10 AMP
*** VOUT STAGE ***
XNC13 9 10 11 12 NC3
XPC23 17 18 11 12 PC3
XUSCP3 11 12 13 14 USCP
XAMP3 11 12 13 14 AMP
*** RLC LADDER NETWORK ***
L1 1 21 3.9789E3
C2 21 0 4.2441E6
L3 21 22 11.9366E3
R4 22 0 50
**************************
*** SUB CIRCUITS ***
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC1 1 2 3 4
RNC1 1 0 7.957729
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.125664
V
2
Fig. S9.715D
+

V
out
C
3
φ
2
φ
1
φ
1
φ
2
φ
1
α
23
C
3
α
13
C
3
φ
2
V
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 974
Problem 9.715 – Continued
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.125664
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.125664
RNC2 4 0 7.957729
.ENDS NC1
.SUBCKT NC2 1 2 3 4
RNC1 1 0 21.2206
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.047124
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.047124
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.047124
RNC2 4 0 21.2206
.ENDS NC2
.SUBCKT NC3 1 2 3 4
RNC1 1 0 23.8732
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.041888
XNC2 1 4 14 DELAY
GNC2 4 1 14 0.041888
XNC3 4 0 40 DELAY
GNC3 4 0 40 0.041888
RNC2 4 0 23.8732
.ENDS NC3
.SUBCKT PC1 1 2 3 4
RPC1 2 4 7.957729
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 21.2206
.ENDS PC2
.SUBCKT PC3 1 2 3 4
RPC1 2 4 23.8732
.ENDS PC3
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT AMP 1 2 3 4
EODD 0 3 1 0 1E6
EVEN 0 4 2 0 1E6
.ENDS AMP
*** ANALYSIS ***
.AC DEC 20 10 200K
.PRINT AC VDB(13) VDB(14) VDB(22)
+VP(13) VP(14) VP(22)
.END
100 1000 10k 100k
Frequency (Hz)
M
a
g
n
i
t
u
d
e
d
B
Switched
Capacitor
Continuous
Time
Fig. S9.715E
120
100
80
60
40
20
0
20
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 975
Problem 9.716
Design a switched capacitor realization of the lowpass prototype filter shown below
assuming a clock frequency of 100 kHz. The passband frequency is 1000Hz. Express
each capacitor in terms of the integrating capacitor C (the capacitor connected from op amp
output to inverting input). Be sure to show the phasing of the switches using φ
1
and φ
2
notation. What is the total capacitance in
terms of a unit capacitance, C
u
? What is
largest C
max
/C
min
?
Solution
Normalize T = 1/f
c
by Ω
n
= 2000π
to get T
n
= Ω
n
T.
State Equations:
1.)
V
in
 V
1
R
0n
= sC
1n
V
1
+ I
2
⇒ V
1
=
1
sC
1n
(
V
in
R
0n

V
1
R
0n
I
2
) =
1
sC
1n
R
0n
.

}
`
V
in
V
1

R
0n
V
2
'
R
or V
1
=
1
sC
1n
R
0n
.

}
`
V
in
V
1

R
0n
V
2
'
R
where V
2
' = RI
2
2.) I
2
=
1
sL
2n
(V
1
 V
out
) ⇒ V
2
' =
R
sL
2n
(V
1
 V
out
)
3.) I
2
= sC
3n
V
out
+
V
out
R
4n
⇒ V
out
=
1
sC
3n
.

}
`
I
2

V
out
R
4n
⇒ V
out
=
1
sC
3n
R
.

}
`
V
2
' 
RV
out
R
4n
Realizations (Assume R = R
0n
= R
4n
):
1.)
V
1
=
1
z
n
1
[α
11
V
in
 α
11
z
n
V
2
'  α
11
z
n
V
1
]
Assume sT
n
<<1 and let z
n
≈ 1+sT
n
to get
V
1
(s) ≈
α
11
sT
n
(V
in
 V
2
'  V
1
)
∴ α
11
=
T
n
C
1n
R
0n
=
2000π
10
5
·1
= 0.0628
+

+

V
in V
out
R
4n
=1Ω
2n
L = 2H R
0n
=1Ω
1n C
=1F
3n
C
=1F
+

V
1
I
2
φ
2
φ
1
φ
2
φ
1
C
C
A1
φ
1
φ
2
φ
1
φ
2
1
α
11 1
C α
11 1
C α
11 1
V
in
V
2
'
V
1
V
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 976
Problem 9.716 – Continued
2.)
V
2
' =
1
z
n
1
[α
12
V
1
 α
12
z
n
V
out
]
Assume sT
n
<<1 and let z
n
≈ 1+sT
n
to get
V
1
(s) ≈
α
12
sT
n
(V
1
 V
out
)
∴ α
12
=
RT
n
L
2n
=
2000π
10
5
·2
= 0.0314
3.)
V
out
=
1
z
n
1
[α
13
V
2
'  α
13
z
n
V
out
]
Assume sT
n
<<1 and let z
n
≈ 1+sT
n
to get
V
out
(s) ≈
α
13
sT
n
(V
2
' V
out
)
∴ α
12
=
T
n
RC
3n
=
2000π
10
5
·1
= 0.0628
Final Realization is given as:
φ
2
φ
1
φ
2
φ
1
A1
φ
2
φ
1
C
u
Vin
V
1
15.91C
u
C
u
φ
2
φ
1
φ
2
φ
1
A2
φ
2
φ
1
C
u 31.83C
u
C
u
φ
2
φ
1
φ
2
φ
1
A3
φ
2
φ
1
C
u
V
out
15.91C
u
C
u
V
2
'
C
u
The total capacitance is 70.65C
u
where C
u
is a unit capacitance. The largest C
max
/C
min
ratio is 31.83.
φ
2
φ
1
φ
2
φ
1
C
C
A2
φ
1
φ
2
2
α
12 2
C α
12 2
V
1
V
2
'
V
out
φ
2
φ
1
φ
2
φ
1
C
C
A3
φ
1
φ
2
3
α
13 3
C α
13 3
V
2
V
out
V
out
'
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 977
Problem 9.717
Design a switched capacitor
realization of the lowpass
prototype filter shown below
assuming a clock frequency of
200 kHz. The passband
frequency is 1000Hz. Express
each capacitor in terms of the
integrating capacitor C (the
capacitor connected from op amp output to inverting input). Be sure to show the phasing
of the switches using φ
1
and φ
2
notation. What is the total capacitance in terms of a unit
capacitance, C
u
? What is largest C
max
/C
min
?
Solution
First we must normalize the clock period, T, by Ω
n
= 2000π to get T
n
= Ω
n
T = Ω
n
/f
c
.
The state equations for the bold variables above are:
1.) V
in
= R
0n
I
1
+ sL
1
I
1
+ V
2
=
R
0n
R
V‘
1
+
sL
1
R
V‘
1
+ V
2
→ V‘
1
=
R
sL
1n
.

}
`
V
i n

R
0n
R
V‘
1
 V
2
2.) V
2
=
1
sRC
2n
( )
V‘
1
 V‘
3
3.) V‘
3
=
R
sL
3n
( )
V
2
 V
out
4.) I
3
= sC
4n
V
out
+
V
out
R
5n
→ V
out
=
1
sRC
4n
.

}
`
V‘
3

R
R
5n
V
out
Realizing each of these four state equations is done as follows:
1.) V‘
1
(z
n
) =
1
z
n
 1
[α
11
V
in
 α
11
z
n
V
2
 α
11
z
n
V‘
1
]
V‘
1
(s) ≈
α
11
sT
n
[V
in
 V
2
 V‘
1
]
∴ α
11
=
T
n
R
L
1n
=
2000π
10
5
·1
= 0.0314
2.) V
2
(z
n
) =
1
z
n
 1
[α
21
V‘
1
 α
21
z
n
V‘
3
]
V
2
(s) ≈
α
21
sT
n
[V‘
1
 V‘
3
]
∴ α
21
=
T
n
RC
2n
=
2000π
10
5
·2
= 0.0159
FigS9.717
V
in
(s)
R
0n
=1Ω L
1n
=1Η
C
2n
=
2F
L
3n
=2Η
C
4n
=
1F
R
5n
=
1Ω
+

V
out
(s)
+

φ
1
φ
2
α
11
C
1
φ
2
C
1
φ
2
α
11
C
1
φ
1
φ
2
α
11
C
1
φ
1
φ
1
V
in
V'
1
V
2
V'
1
+

φ
1
φ
2
α
21
C
2
φ
2
C
2
φ
2
α
21
C
2
φ
1
V'
1
V'
3
V
2
φ
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 978
Problem 9.717  Continued
3.) V‘
3
(z
n
) =
1
z
n
 1
[α
31
V
2
 α
31
z
n
V
out
]
V‘
3
(s) ≈
α
31
sT
n
[V
2
 V
out
]
∴ α
31
=
T
n
R
L
3n
=
2000π
10
5
·2
= 0.0159
4.) V
out
(z
n
) =
1
z
n
 1
[α
41
V‘
3
 α
41
z
n
V
out
]
V
out
(s) ≈
α
41
sT
n
[V‘
3
 V
out
]
∴ α
41
=
T
n
RC
4n
=
2000π
10
5
·1
= 0.0314
The actual filter realization is obtained by
connecting the above four circuits as indicated by their terminal voltages.
Total capacitance:
For each stage, make the smallest capacitor equal to C
u
and sum capacitors.
Stage 1: 3C
u
+ (C
u
/0.0314) = 31.8C
u
+ 3C
u
= 34.8C
u
Stage 2: 2C
u
+ (C
u
/0.0159) = 63.7C
u
+ 2C
u
= 65.7C
u
Stage 3: 2C
u
+ (C
u
/0.0159) = 63.7C
u
+ 2C
u
= 65.7C
u
Stage 4: 2C
u
+ (C
u
/0.0314) = 31.8C
u
+ 2C
u
= 33.8C
u
Total capacitance = 200C
u
C
max
C
min
= 63.7
SPICE File:
*** HW9 PROBLEM3 (Problem 9.717) ***
*** Node 17 and 18 are Switched Cap outputs
*** Node 23 is RLC ladder network output
VIN 1 0 DC 0 AC 1
*** V1' STAGE ***
XNC11 1 2 3 4 NC1
XPC21 9 10 3 4 PC1
XPC31 5 6 3 4 PC1
XUSCP1 3 4 5 6 USCP
XAMP1 3 4 5 6 AMP
*** V2 STAGE ***
XNC12 5 6 7 8 NC2
XPC22 13 14 7 8 PC2
+

φ
1
φ
2
α
31
C
3
φ
2
C
3
φ
2
α
31
C
3
φ
1
V
out
V
2
φ
1
V'
3
+

φ
1
φ
2
α
41
C
4
φ
2
C
4
φ
2
α
41
C
4
φ
1
V
out
φ
1
V'
3
V
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 979
Problem 9.717 – Continued
XUSCP2 7 8 9 10 USCP
XAMP2 7 8 9 10 AMP
*** V3' STAGE ***
XNC13 9 10 11 12 NC2
XPC23 17 18 11 12 PC2
XUSCP3 11 12 13 14 USCP
XAMP3 11 12 13 14 AMP
*** VOUT STAGE ***
XNC14 13 14 15 16 NC1
XPC24 17 18 15 16 PC1
XUSCP4 15 16 17 18 USCP
XAMP4 15 16 17 18 AMP
*** RLC LADDER NETWORK ***
R1 1 21 50
L1 21 22 7.9577E3
C2 22 0 6.3662E6
L3 22 23 15.9155E3
C4 23 0 3.1831E6
R2 23 0 50
**************************
*** SUB CIRCUITS ***
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=2.5US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC1 1 2 3 4
RNC1 1 0 31.8269
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.03142
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.03142
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.03142
RNC2 4 0 31.8269
.ENDS NC1
.SUBCKT NC2 1 2 3 4
RNC1 1 0 63.6537
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.01571
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.01571
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.01571
RNC2 4 0 63.6537
.ENDS NC2
.SUBCKT PC1 1 2 3 4
RPC1 2 4 31.8269
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 63.6537
.ENDS PC2
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT AMP 1 2 3 4
EODD 0 3 1 0 1E6
EVEN 0 4 2 0 1E6
.ENDS AMP
*** ANALYSIS ***
.AC DEC 1000 10 199K
.PROBE
.END
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 980
Problem 9.718
Use the lowpass, normalized prototype filter of Fig. P9.714 to develop a switched
capacitor, ladder realization for a bandpass filter which has a center frequency of 1000Hz, a
bandwidth of 500Hz, and a clock frequency of 100kHz. Give a schematic diagram
showing all values of capacitances in terms of the integrating capacitor and the phasing of
all switches. Use straysinsensitive integrators. Use SPICE to plot the frequency response
(magnitude and phase) of your design and the ideal continuous time filter.
Solution
1.) Normalize by s =
.

}
` ω
r
BW
p =
1000
500
p = 2p
2.) Transform the normalized circuit to bandpass using the transformation,
s = p +
1
p
The resulting circuit is shown.
3.) The state equations for this bandpass
circuit can be written as follows.
V
1
=
s
2RC
1n
s
2
+1
]
]
R
R
on
(V
in
V
1
)V
2
'
where V
2
’ = I
2
·R and R = 1.
V
out
=
R
3n
R
V
2
’ =
R
3n
R
.

}
`
sR
2L
2n
s
2
+1
(V
1
V
out
) =
.

}
`
sR
3n
2L
2n
s
2
+1
(V
1
V
out
)
4.) The SC realization of each secondorder block is given as,
φ
1
φ
1
φ
2
φ
2
+

α
1j
C
j C
j
φ
2
φ
1
φ
1
φ
2
V
j
φ
2
φ
1
φ
1
φ
2
+

C
j
α
2j
C
j
α
3j
C
j
φ
2
φ
1
α
4j
C
j
V
1
V
2
Fig. S9.718D
R
3n
=1Ω
V
s
R
on
= 1Ω
2L
2n 2L
2n
1
2C
1n
1
2C
1n
I
2
V
1
V
out
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 981
Problem 9.718 – Continued
If f
clock
>>f
r
, then V
j
(s) of the above realization can be written as,
V
j
(s) ≈
.

}
`
s
s
2
+
α
1j
α
2j
T
n
2
]
]
] α
3j
T
n
V
1

α
4j
T
n
V
2
where T
n
= Ω
n
T = ω
r
T
5.) Comparing the state equations with the above transfer function gives,
j = 1 or V
1
: α
11
α
21
= T
n
2
→ α
11
= α
21
= T
n
= ω
r
T =
ω
r
f
clock
=
2πx10
3
10
5
= 0.02 π
α
31
= α
41
= α
51
=
T
n
R
on
2C
1n
=
ω
r
T
2 2
=
2πx10
3
2 2x10
5
= 0.0071 π
j = 2 or V
out
: α
12
α
22
= T
n
2
→ α
12
= α
22
= T
n
= ω
r
T =
ω
r
f
clock
=
2πx10
3
10
5
= 0.02 π
α
32
= α
42
=
T
n
R
on
2L
2n
=
ω
r
T
2 2
=
2πx10
3
2 2x10
5
= 0.0071 π
6.) Filter realization:
α
11
= α
21
= 0.02π= 0.0628
C
j
= C
1
φ
1
φ
1
φ
2
φ
2
α
12
= α
22
= 0.02π= 0.0628
C
j
= C
2
φ
1
φ
2
0.0222143C
1
φ
1
φ
2
φ
1
φ
2
φ
2
φ
1
φ
1
φ
2
V
s
V
out
0.022214C
1
0.022214C
1
0.022214C
2
0.022214C
2
Fig. S9.718E
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 982
Problem 9.718 – Continued
7.) To create the SPICE input file, the above figure needs to be expanded which is
done below.
+

α
31
C
1
C
1
φ
1
φ
1
φ
2
φ
2
V
1
α
11
C
1
φ
1
φ
2
α
51
C
1
φ
1
φ
2
α
41
C
1
φ
1
φ
2
V
2
V
in
V
out
V
1
+

C
1
φ
1
φ
1
φ
2
φ
2
V
2
V
1
α
21
C
1
+

α
32
C
1
C
2
φ
1
φ
1
φ
2
φ
2
α
12
C
1
φ
1
φ
2
α
42
C
1
φ
1
φ
2
V
4
V
out
V
out
V
1
+

C
2
φ
1
φ
1
φ
2
φ
2
V
4
α
22
C
2
V
out
Fig. S9.718F
8.) The SPICE simulation file for this filter is shown below.
SPICE File for Problem 9.718
*** Node 13 and 14 are Switched Cap outputs
*** Node 23 is RLC ladder network output
VIN 1 0 DC 0 AC 1
*** V1 STAGE ***
XPC11 9 10 3 4 PC2
XNC31 1 2 3 4 NC1
XPC41 5 6 3 4 PC1
XPC51 13 14 3 4 PC1
XUSCP1 3 4 5 6 USCP
XAMP1 3 4 5 6 AMP
*** V2 STAGE ***
XNC21 5 6 7 8 NC2
XUSCP2 7 8 9 10 USCP
XAMP2 7 8 9 10 AMP
*** VOUT STAGE ***
XPC12 17 18 11 12 PC2
XNC32 5 6 11 12 NC1
XPC42 13 14 11 12 PC1
XUSCP3 11 12 13 14 USCP
XAMP3 11 12 13 14 AMP
*** V4 STAGE ***
XNC22 13 14 15 16 NC2
XUSCP4 15 16 17 18 USCP
XAMP4 15 16 17 18 AMP
*** RLC LADDER NETWORK ***
R0 1 21 50
C1 21 0 9.0032E6
L1 21 0 2.8135E3
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 983
Problem 9.718 – Continued
L2 21 22 22.5079E3
C2 22 23 1.125395E6
R3 23 0 50
*** SUB CIRCUITS ***
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC1 1 2 3 4
RNC1 1 0 45.015816
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.022214
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.022214
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.022214
RNC2 4 0 45.015816
.ENDS NC1
.SUBCKT NC2 1 2 3 4
RNC1 1 0 15.91549
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.062832
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.062832
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.062832
RNC2 4 0 15.91549
.ENDS NC2
.SUBCKT PC1 1 2 3 4
RPC1 2 4 45.015816
.ENDS PC1
.SUBCKT PC2 1 2 3 4
RPC1 2 4 15.91549
.ENDS PC2
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT AMP 1 2 3 4
EODD 0 3 1 0 1E6
EVEN 0 4 2 0 1E6
.ENDS AMP
*** ANALYSIS ***
.AC DEC 20 100 100K
.PRINT AC VDB(17) VDB(18) VDB(23) VP(17) VP(17) VP(23)
.END
100 1000 10k 100k
Frequency (Hz)
M
a
g
n
i
t
u
d
e
d
B
Switched
Capacitor
Continuous Time
Fig. S9.718E
80
70
60
50
40
30
20
10
0
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 984
Problem 9.719
Use the lowpass, normalized
prototype filter of Fig. P9.713 to
develop a switchedcapacitor, ladder
realization for a bandpass filter which
has a center frequency of 1000Hz, a
bandwidth of 500Hz, and a clock
frequency of 100kHz. Give a
schematic diagram showing all values of capacitances in terms of the integrating capacitor
and the phasing of all switches. Use straysinsensitive integrators. Use SPICE to plot the
frequency response (magnitude and phase) of your design and the ideal continuous time
filter.
Solution
TBD
+

+

V
in
(s
n
)
V
out
(s
n
)
R
3n
=1Ω
R
0n
=1Ω
L
1n
= 2H
C
2n
=
2F
Figure P9.713
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 985
Problem 9.720
Use the lowpass, normalized prototype filter shown to develop a switchedcapacitor,
ladder realization for a bandpass filter which has a center frequency of 1000Hz, a
bandwidth of 100Hz, and a clock frequency of 100kHz. Give a schematic diagram
showing all values of capacitances in terms of the integrating capacitor and the phasing of
all switches. Use straysinsensitive integrators. Use SPICE to plot the frequency response
(magnitude and phase) of your design and the ideal continuous time filter.
R
on
=1Ω
L
2n
=2H
C
1n
=
1F
C
3n
=
1F
R
4n
=
1Ω
V
in
(s)
V
out
(s)
+

R
1
R
1
V
1
V
2
R
4
R
2 R
3
R R
C
1
C
2
V

o
V
+
o
TowThomas
Bandpass Filter
R
4
R
1
C
1
V
1
V
+
o
s
R
4
( )
s
2
+ +
1
C
1
s
R
4
R
2
R
3
C
1
C
2
=
V
1
V

o
= 
+

+

Solution
The bandpass normalized filter is
shown using the values of f
r
=
1000 Hz and BW = 100 Hz to
scale the elements by 10. The
state variables and the input
voltage are shown in bold.
The state equations are:
1.)
V
in
 V
1
R
0n
= I
2
+ (sC
1bn
+
1
sL
1bn
) V
1
→
V
in
R
0n

V‘
2
R
=
.

}
`
1
R
0n
+sC
1bn
+
1
sL
1bn
V
1
or V
1
=
s
C
1bn
R
s
2
+
s
R
0n
C
1bn
+
1
L
1bn
C
1bn
.

}
`
V‘
2

V
in
R
0n
=
0.1s
s
2
+0.1s+1
(V‘
2
 V
in
)
2.)
I
2
=
V‘
2
R
=
V
2
 V
out
sL
2bn
+
1
sC
2bn
=
s
L
2bn
s
2
+
1
L
2bn
C
2bn
(V
1
 V
out
) → V‘
2
=
0.05s
s
2
+ 1
(V
1
 V
out
)
3.) V
out
=
V‘
2
R
sC
3bn
+
1
sL
3bn
+
1
R
4n
=
0.1V‘
2
s
2
+ 0. 01s + 1
R
on
=1Ω
L
2bn
=20H
C
1bn
=
10F
R
4n
=
1Ω
V
in
(s) V
out
(s)
L
1bn
=
0.1H
C
2bn
=
0.05F
C
3bn
=
10F
L
3bn
=
0.1H
V
1
I
2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 986
Problem 9.720  Continued
Now we need to design each TowThomas bandpass circuit. If R
2
= R
3
= 1Ω and C
1
= C
2
= 1F of the TowThomas circuit then the transfer function becomes,
V
+
o
V
1
=
s
R
i1
s
2˚˚
+
s
R
i4
+ 1
where i corresponds to the ith stage
Therefore the design of each stage is:
Stage 1: R
11
= 10Ω, R
14
= 10Ω, R
12
= R
13
=1Ω, and C
11
= C
12
= 1F
Stage 2: R
21
= 20Ω, R
24
= ∞, R
22
= R
23
=1Ω, and C
21
= C
22
= 1F
Stage 3: R
31
= 10Ω, R
34
= 10Ω, R
32
= R
33
=1Ω, and C
31
= C
32
= 1F
Next, denormalizing by 2000π and impedance denormalizing by 10
5
gives,
+

R
11
R
11 V
in R
14
R
12
R
13
R
R
C
11
C
12
+

+

+

R
21
R
21
R
22
R
23
R
R
C
21
C
22
+

+

+

R
31
R
34
R
32
R
33
R
R
C
31
C
32
+

+

V
out
where
R = R
11
= R
14
= 1MΩ, R
12
= R
13
= 100kΩ, and C
11
= C
12
= 1. 59nF
R = R
21
= 2MΩ, R
24
= ∞, R
22
= R
23
= 100kΩ, and C
21
= C
22
= 1. 59nF
and
R = R
31
= R
32
= 1MΩ, R
32
= R
3
= 100kΩ, and C
31
= C
32
= 1. 59nF
SPICE File:
*** HW9 PROBLEM4 (Problem 9.720) ***
*** Node 13 and 14 are Switched Cap outputs
*** Node 23 is RLC ladder network output
VIN 1 0 DC 0 AC 1
*** V1 STAGE ***
XNC41 1 2 3 4 NC41
XPC411 9 10 3 4 PC41
XPC412 5 6 3 4 PC41
XLQBQ1 3 4 5 6 LQBIQUAD
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 987
Problem 9.720 – Continued
*** V2' STAGE ***
XNC42 5 6 7 8 NC42
XPC421 13 14 7 8 PC42
XLQBQ2 7 8 9 10 LQBIQUAD
*** VOUT STAGE ***
XNC43 9 10 11 12 NC41
XPC431 13 14 11 12 PC41
XLQBQ3 11 12 13 14 LQBIQUAD
*** RLC LADDER NETWORK ***
R1 1 21 50
C11 21 0 3.1831E5
L11 21 0 7.9577E4
L21 21 22 0.1592
C21 22 23 1.5915E7
C31 23 0 3.1831E5
L31 23 0 7.9577E4
R2 23 0 50
**************************
*** SUB CIRCUITS ***
.SUBCKT DELAY 1 2 3
ED 4 0 1 2 1
TD 4 0 3 0 ZO=1K TD=5US
RDO 3 0 1K
.ENDS DELAY
.SUBCKT NC5 1 2 3 4
RNC1 1 0 15.916
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.06283
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.06283
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.06283
RNC2 4 0 15.916
.ENDS NC5
.SUBCKT NC41 1 2 3 4
RNC1 1 0 159.1596
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.006283
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.006283
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.006283
RNC2 4 0 159.1596
.ENDS NC41
.SUBCKT NC42 1 2 3 4
RNC1 1 0 318.2686
XNC1 1 0 10 DELAY
GNC1 1 0 10 0 0.003142
XNC2 1 4 14 DELAY
GNC2 4 1 14 0 0.003142
XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.003142
RNC2 4 0 318.2686
.ENDS NC42
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 988
Problem 9.720 – Continued
.SUBCKT PC2 1 2 3 4
RPC1 2 4 15.916
.ENDS PC2
.SUBCKT PC41 1 2 3 4
RPC1 2 4 159.1596
.ENDS PC41
.SUBCKT PC42 1 2 3 4
RPC1 2 4 318.2686
.ENDS PC42
.SUBCKT USCP 1 2 3 4
R1 1 3 1
R2 2 4 1
XUSC1 1 2 12 DELAY
GUSC1 1 2 12 0 1
XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1
XUSC3 3 2 32 DELAY
GUSC3 2 3 32 0 1
XUSC4 3 4 34 DELAY
GUSC4 3 4 34 0 1
.ENDS USCP
.SUBCKT AMP 1 2 3 4
EODD 0 3 1 0 1E6
EVEN 0 4 2 0 1E6
.ENDS AMP
.SUBCKT LQBIQUAD 5 6 7 8
XPC2 7 8 1 2 PC2
XUSCP1 1 2 3 4 USCP
XAMP1 1 2 3 4 AMP
XNC5 3 4 5 6 NC5
XUSCP2 5 6 7 8 USCP
XAMP2 5 6 7 8 AMP
.ENDS LQBIQUAD
*** ANALYSIS ***
.AC DEC 1000 10 99K
.PROBE
.END
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 989
Problem 9.721
Use the lowpass, normalized prototype filter
shown to develop a switchedcapacitor,
ladder realization for a bandpass filter which
has a center frequency of 1000Hz, a
bandwidth of 100Hz, and a clock frequency
of 100kHz. Give a schematic diagram
showing all values of capacitances in terms of
the integrating capacitor and the phasing of all
switches. Use straysinsensitive integrators.
Use SPICE to plot the frequency response (magnitude and phase) of your design and the
ideal continuous time filter.
Solution
TBD
Figure P9.721
R
on
=1Ω
L
1n
=1H
C
2n
=
2F
R
4n
=
1Ω
V
in
(s)
V
out
(s)
L
3n
=1H
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 990
Problem 9.722
A secondorder, lowpass, Sallen and Key
active filter is shown along with the transfer
function in terms of the components of the
filter.
a.) Define n = R
3
/R
1
and m = C
4
/C
2
and
let R
1
= R and C
2
= C. Develop the design
equations for Q and ω
o
if K = 1.
b.) Use these equations to
design for a secondorder,
lowpass, Butterworth anti
aliasing filter with a
bandpass frequency of
10kHz. Let R
1
= R =
10kΩ and find the value of
C
2
, R
3
, and C
4
.
Solution
a.) The expressions for Q and ω
o
are
ω
o
=
1
R
1
R
3
C
2
C
4
and
ω
o
Q
=
1
R
3
C
4
+
1
R
1
C
2
+
1
R
3
C
2

K
R
3
C
4
If K = 1, then ω
o
=
1
R
1
R
3
C
2
C
4
and
1
Q
=
R
3
C
4
R
1
C
2
+
R
1
C
4
R
3
C
2
.
Define n =
R
3
R
1
and m =
C
4
C
2
and let R
1
= R and C
2
= C. Therefore,
ω
o
2
=
1
mn(R
1
C
2
)
2
⇒ ω
o
=
1
mnR
1
C
2
=
1
mnRC
and
1
Q
= mn +
m
n
= mn
.

}
`
1+
1
n
b.) A normalized Butterworth secondorder lowpass function is
V
out
V
in
=
1
s
2
+ 2s+1
⇒ ω
ο
= 1 rad/sec and Q = 0.707
Let R
1
= R = 1Ω and C
2
= C = 1F. ∴ mn = 1 and 2 = 1·
.

}
`
1+
1
n
= 1+
1
n
From the above, n =
1
21
= 2.4142 and m =
1
2.4142
= 0.4142
∴ R
3
= 2.4142Ω and C
4
= 0.4142F
Denormalizing by 10
4
Ω and 20,000π (rads/sec) gives
R
1
= 10kΩ, R
3
= 24.142kΩ, C
1
= 1.59nF and C
4
= 0. 659nF
V
in K V
out
C
4
C
2
R
3
R
1
V
out
V
in
=
K
R
1
R
3
C
2
C
4
s
2
+s
]
]
1
R
3
C
4
+
1
R
1
C
2
+
1
R
3
C
2

K
R
3
C
4
+
1
R
1
R
3
C
2
C
4
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 991
Problem 9.723
The circuit shown is to be
analyzed to determine its
capability to realize a second
order transfer function with
complex conjugate poles. Find
the transfer function of the circuit
and determine and verify the
answers to the following
questions:
1.) Is the circuit lowpass, bandpass, highpass, or other?
2.) Find H
o
, ω
o
, and Q in terms of R
1
, C
2
, R
3
, and C
4
.
3.) What elements would you adjust to independently tune Q and ω
o
?
Solution
a.) V
out
=
.

}
`
(1/sC
4
)
R
3
+(1/sC
4
)
V
1
=
V
1
sR
3
C
4
+1
V
1
=
.

}
`
R
1
R
1
+(1/sC
2
)
V
out
+
.

}
`
(1/sC
2
)
R
1
+(1/sC
2
)
V
in
=
sR
1
C
2
V
out
sC
2
R
1
+1
+
V
in
sC
2
R
1
+1
∴ V
out
=
.

}
`
1
sR
3
C
4
+1
.

}
`
sR
1
C
2
V
out
sC
2
R
1
+1
+
V
in
sC
2
R
1
+1
V
out
(sR
3
C
4
+1)(sR
1
C
2
+ 1) = sR
1
C
2
V
out
+ V
in
V
out
[s
2
R
1
R
3
C
2
C
4
+ sR
1
C
2
+ sR
3
C
4
 sR
1
C
2
+
1] = V
in
∴
V
out
V
in
=
1
s
2
R
1
R
3
C
2
C
4
+sR
3
C
4
+1
=
1
R
1
R
3
C
2
C
4
s
2
+
s
R
1
C
2
+
1
R
1
R
3
C
2
C
4
=
H
o
ω
ο
2
s
2
+
.

}
` ω
o
Q
s + ω
ο
∴ Filter is lowpass .
b.) From the previous results, H
o
= 1, ω
o
=
1
R
1
R
3
C
2
C
4
, and Q = ω
o
R
1
C
2
=
R
1
C
2
R
3
C
4
c.) To tune ω
o
but not Q, adjust the product of R
1
R
3
(C
2
C
4
) keeping the ratio R
1
/R
3
(C
2
/C
4
) constant.
To tune Q but not ω
o
, adjust the ratio R
1
/R
3
(C
2
/C
4
) keeping the product of R
1
R
3
(C
2
C
4
)
constant.
+1 +1
V
in
(s) V
out
(s)
2
4
3 1
C
R
C
R
Figure P9.723
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 101
CHAPTER 10 – HOMEWORK SOLUTIONS
Problem 10.101
Plot the analog output versus the digital word input for a threebit D/A converter that has ±1
LSB DNL and ±1 LSB INL. Assume an arbitrary analog fullscale value.
Solution
Below is a characteristic of a 3bit DAC. The shaded area is not permitted in order to
maintain ±1 LSB INL.
000 001 010 011 100 101 110 111
1
8
0
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
A
n
a
l
o
g
I
n
p
u
t
V
o
l
t
a
g
e
Digital Output Code
Ideal 3bit Characteristic
Actual 3bit Characteristic
+1 LSB
INL
1 LSB
INL
+1 LSB
DNL
1 LSB
DNL
S10.101
Problem 10.102
Repeat the above problem for ±1.5 LSB DNL and ±0.5 LSB integral linearity.
Solution
The shaded area is not permitted in order to maintain ±0.5 LSB INL. Note that the DNL
cannot exceed ±1 LSB.
000 001 010 011 100 101 110 111
1
8
0
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
A
n
a
l
o
g
I
n
p
u
t
V
o
l
t
a
g
e
Digital Output Code
Ideal 3bit Characteristic
Actual 3bit Characteristic
+0.5 LSB
INL
0.5 LSB
INL
+1 LSB
DNL
1 LSB
DNL
S10.102
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 102
Problem 10.103
Repeat Prob. 1, for ±0.5 LSB differential linearity and ±1.5 LSB integral linearity.
Solution
The shaded area is not permitted in order to maintain ±1.5 LSB INL.
000 001 010 011 100 101 110 111
1
8
0
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
A
n
a
l
o
g
I
n
p
u
t
V
o
l
t
a
g
e
Digital Output Code
Ideal 3bit Characteristic
Actual 3bit Characteristic
+1.5 LSB
INL
1.5 LSB
INL
+0.5 LSB
DNL
0.5 LSB
DNL
S10.103
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 103
Problem 10.104
The transfer characteristics of an ideal and actual 4bit digitalanalog converter are shown in
Fig. P10.14. Find the ±INL and ±DNL in terms of LSBs. Is the converter monotonic or
not?
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0/16
1/16
2/16
3/16
4/16
5/16
6/16
7/16
8/16
9/16
10/16
11/16
12/16
13/16
14/16
15/16
16/16
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b1
b2
b3
b4
A
n
a
l
o
g
O
u
t
p
u
t
(
N
o
r
m
a
l
i
z
e
d
t
o
F
u
l
l
S
c
a
l
e
)
Digital Input Code
Infinite resolution
DAC characteristic
Ideal 4bit DAC
characteristic
Actual 4bit DAC
characteristic
+1LSB
INL
1.5LSB
INL
+1.5LSB
DNL
2LSB
DNL
S10.104
Solution
INL: +1LSB, 2.5LSB, DNL: +1.5LSB, 2LSB, the converter is not monotonic.
Problem 10.105
A 1V peaktopeak sinusoidal signal is applied to an ideal 10 bit DAC which has a V
REF
of
5V. Find the SNR of the digitized analog output signal.).
Solution
A 1V peak sinusoideal signal is applied to an ideal 10 bit DAC which has a V
REF
of 5V.
Find the SNR of the digitized analog output signal.
Solution
The SNR
max
= 6.02dB/bit x 10bits + 1.76dB = 61.96dB
The maximum output signal is 2.5V peak. Therefore, the 1V peak signal is 7.96dB smaller
to give a SNR of the digitized analog output as 61.967.96 = 54dB
∴ SNR = 54dB
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 104
Problem 10.106
How much noise voltage in rms volts can a 1V reference voltage have and not cause errors
in a 14bit D/A converter? What must be the fractional temperature coefficient (ppm/°C) for
the reference voltage of this D/A converter over the temperature range of 0°C to 100°C?
Solution
The rms equivalent of a 1V reference voltage is
1
2 2
V. Multiplying by
1
2
14
gives
Rms noise =
1
2 2·2
14
= 21.6µV(rms) → Rms noise = 21.6µV
To be within ±0.5LSB, the voltage change must be less than or equal to 2
15
.
∴ ppm/C° =
∆V
V
∆Τ
=
2
15
1
100C°
=
1
2·16,384·100
= 0.3052pppm/C° → 0.3052ppm/C°
Problem 10.107
If the quantization level of an analogtodigital converter is ∆, prove that the rms
quantization noise is given as ∆/ 12.
Solution
Assume the quantizer signal appears as follows.
q(x)
x
∆/2
−∆/2
1 0 1
Fig. S10.107
The rms value of q(x) is
1
T
⌡
⌠
0
T
q
2
(x)dx where q(x) = 0.5∆x and T = 2.
∴ rms value of q(x) =
1
2⌡
1
⌠
1
1
∆
2
4
x
2
dx =
∆
2
8
x
3
3
1
1
=
∆
2
8
.

}
`
1
3
+
1
3
=
∆
12
rms value of q(x) = ∆ / 12
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 105
Problem 10.201
Find I
o
in terms of I
1
, I
2
, I
3
, and I
4
for the circuit shown.
Solution
I
OUT
= I
0
I
1
sees R to the right and R to the left so that I
OUT
=
I
1
2
.
I
2
requires the use of Norton’s theorem to see the results.
I
2
I
OUT
R
R
2R
2R
2R
I
2
I
OUT
R
R
2R
R
I
2
I
OUT
R
2R 2R
2
I
2
I
OUT
R
2
R
S10.201A
∴ I
OUT
=
I
2
4
Repeating the above process for I
8
will give I
OUT
= I
OUT
=
I
3
8
R
R R R
2R 2R
I
OUT
I
0
I
1
I
2 I
3
Figure P10.21
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 106
Problem 10.202
A digitalanalog converter uses the binary weighted
current sinks shown. b
1
is the MSB and b
N
is the
LSB.
a.) For each individual current sink, find the
tolerance in ±percent necessary to keep INL less than
±0.5LSB if N = 4 assuming all other bits are ideal.
b.) Considering the influence of all current sinks,
what is the worst case tolerances in ±percent for each sink?
Solution
a.) An LSB =
I
2
N
, therefore each sink must have the accuracy of ±0.5 LSB =
±I
2
N+1
=
I
32
.
I/2:
I
2
±
I
2
N+1
=
I
2
±
I
32
=
I
2
.

}
`
1 ±
1
16
⇒
Tolerance of
I
2
=
± 1
16
1
x100% =
±100
16
% = ±6. 25%
I/4:
I
4
±
I
32
=
I
4
.

}
`
1 ±
1
8
⇒ Tolerance of
I
4
=
± 1
8
1
x100% =
±100
8
% = ±12. 5%
Similarly, the tolerance of I/8 and I/16 are ±25% and ±50%, respectively.
The tolerance of the ith current sink =
2
iN
2
x100%
b.) In this case, assume that all errors add for a worst case approach. Let this error be x.
Therefore we can write,
.

}
`
I
2
+ x +
.

}
`
I
4
+ x +
.

}
`
I
8
+ x +
.

}
`
I
16
+ x ≤
.

}
`
I
2
+
I
4
+
I
8
+
I
16
+
I
32
or
.

}
`
I
2
+
I
4
+
I
8
+
I
16
+ 4x ≤
.

}
`
I
2
+
I
4
+
I
8
+
I
16
+
I
32
⇒ x =
I
4·32
=
I
128
Thus the tolerances of part a.) are all decreased by a factor of 4 to give ±1.5625%,
±3.125%, ±6.25%, and ±12.5% for I/2, I/4, I/8, and I/16, respectively.
I
2
⇒ ±1. 5625%,
I
4
⇒ ±3. 125%,
I
8
⇒ ±6. 25% and
I
16
⇒ ±12. 5%
The tolerance of the ith current sink =
2
iN
2N
x100%
I
2
I
4
I
2
N
b
N
b
2 b
1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 107
Problem 10.203
A 4bit, binary weighted, voltage scaling
digitaltoanalog converter is shown. (a.)
If R
0
= 7R/8, R
1
= 2R, R
2
= 4R, R
3
= 8R,
R
4
= 16R, and V
OS
= 0V, sketch the
digitalanalog transfer curve on the plot on
the next page. (b.) If R
0
= R, R
1
= 2R, R
2
= 4R, R
3
= 8R, R
4
= 16R, and V
OS
=
(1/15)V
REF
, sketch the digitalanalog
transfer curve on the plot shown. (c.) If R
0
= R, R
1
= 2R, R
2
= 16R/3, R
3
= 32R/5, R
4
=
16R, and V
OS
= 0V, sketch the digitalanalog transfer curve on the previous transfer curve.
For this case, what is the value of DNL and INL? Is this D/A converter monotonic or
not?
Solutions
(a.) v
out
= R
0
.

}
`
b
1
R
1
+
b
2
R
2
+
b
3
R
3
+
b
4
R
4
V
REF
=
7
8.

}
`
b
1
2
+
b
2
4
+
b
3
8
+
b
4
16
V
REF
v
out
=
.

}
`
7
16
+
7
24
+
7
64
+
7
128
V
REF
=
7
8
x ideal characteristic
(b.) The equivalent circuit is given as shown.
R
eq
=
R
b
1
2
+
b
2
4
+
b
3
8
+
b
4
16
v
out
=
R
0
R
eq
.
(V
REF
+V
OS
) + V
OS
v
out
=
.

}
`
b
1
2
+
b
2
4
+
b
3
8
+
b
4
16
(V
REF
V
OS
) + V
OS
v
out
=
.

}
`
b
1
2
+
b
2
4
+
b
3
8
+
b
4
16 .

}
`
16V
REF
15
+
V
REF
15
∴ Gain error of 1/16 and offset of V
REF
/15.
(c.) v
out
= R
0
.

}
`
b
1
R
1
+
b
2
R
2
+
b
3
R
3
+
b
4
R
4
V
REF
=
.

}
`
b
1
2
+
3b
2
16
+
5b
3
32
+
b
4
16
V
REF
=
.

}
`
16b
1
32
+
12b
2
32
+
5b
3
32
+
2b
4
32
V
REF
→ Used to generate the plot on the next page
∴ INL = +0.5LSB and 1.0LS B DNL = +0.5LSB and 1.5LSB
This DAC is not monotonic.
+

R
1
b
1
R
2
b
2
R
3
b
3
R
4
b
4
+

V
OS
v
out
V
REF
R
0
+

V
REF V
OS
R
eq. R
v
out
F98E2S2B
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 108
Problem 10.23  Continued
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Digital Input Code
A
n
a
l
o
g
O
u
t
p
u
t
V
o
l
t
a
g
e
N
o
r
m
a
l
i
z
e
d
t
o
V
R
E
F
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1 1
1
0 0 0 0
1 1 1
1
0
0
0
1 0
1 1
1 1 1 1 1 1 1 1
1
0
0
0
0
0
1
0 0
0
1 1
1 1 1 1
1
0
0
0
1 0
1 1
Part (a.)
Part (b.)
Part (c.)
Ideal Finite
Resolution
Characteristic
INL = 1.0LSB
INL =
+0.5LSB
DNL =
+0.5LSB
DNL =
1.5LSB
16
16
+
1
15
1
15
F98E2S2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 109
Problem 10.204
A 4bit digitaltoanalog converter characteristic using the DAC of Fig. P10.23 is shown
in Fig. P10.24. (a.) Find the DNL and the INL of this converter. (b.) What are the
values of R
1
through R
4
, that correspond to this inputoutput characteristic? Find these
values in terms of R
0
.
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b0
b1
b2
b3
Digital Input Code
0/16
1/16
2/16
3/16
4/16
5/16
6/16
7/16
8/16
9/16
10/16
11/16
12/16
13/16
14/16
15/16
16/16
A
n
a
l
o
g
O
u
t
p
u
t
(
N
o
r
m
a
l
i
z
e
d
t
o
F
u
l
l
S
c
a
l
e
)
Ideal DAC
Characteristic
Ideal 4bit DAC
characteristic
Actual 4bit DAC
characteristic
Figure P10.24
Solution
(a.) INL = +0.5LSB and –2.0 LSB, DNL = +0.5LSB and –1.5LSB.
(b.) Note that v
OUT
can be written as,
v
OUT
= R
0
]
]
b
0
R
1
+
b
1
R
2
+
b
2
R
3
+
b
3
R
4
V
REF
For 0001,  v
OUT
 =
V
REF
16
→ R
4
= 16 R
0
. For 0010,  v
OUT
 =
5V
REF
32
→ R
3
=
32
5
R
0
.
For 0100,  v
OUT
 =
3V
REF
16
→ R
2
=
16
3
R
0
. For 1000,  v
OUT
 =
V
REF
2
→ R
1
= 2 R
0
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1010
Problem 10.205
For the DAC of Fig. P10.23, design the values of R
1
through R
4
in terms of R
0
to achieve
an ideal 4bit DAC. What value of input offset voltage, V
OS
, normalized to V
REF
will
cause an error? If the op amp has a differential voltage gain of
A
vd
(s) =
10
6
s˚+˚100
at what frequency or rate of conversion will an error in conversion occur due to the
frequency response of the op amp? Assume that the rate of application of digital words to
be converted is equivalent to the application of a sinusoidal signal of equivalent frequency.
Solution
The values of the resistors are R
1
= 2R
0
, R
2
= 4R
0
, R
3
= 8R
0
, and R
4
= 16R
0
.
A model for the input offset voltage influence on the DAC is shown. The output voltage is,
v
OUT
= 
R
R
EQ.
V
REF
+
.

}
`
R +R
EQ.
R
EQ.
V
OS
We see that the largest influence of V
OS
is when R
EQ.
is minimum which is R
1
R
2
R
3
R
4
= (16/15)R.
∴
.

}
`
1 +
1 5
16
V
OS
≤ 0.5LSB =
1
32
V
REF
V
OS
V
REF
≤
.

}
`
1
32
.

}
`
16
31
=
1
62
= 0.01613
For the maximum conversion rate, the worst case
occurs when the loop gain is smallest. The loop gain is given as
LG = 
.

}
`
R
EQ.
R +R
EQ.
A
vd
Which is minimum when R
EQ.
= (16/15)R. The ideal output normalized toV
REF
is,
v
OUT
(ideal)
V
REF
= 
.

}
`
R
R
EQ.
= 
15
16
The actual output normalized toV
REF
is,
v
OUT
(actual)
V
REF
=

A
vd
R
R +R
EQ.
1+
A
vd
R
EQ.
R +R
EQ.
=

1 5
31
1
A
vd
+
1 6
31
=

1 5
31
s
10
6
+
1 6
31
where we have assumed that ω >> 100 rads/sec which gives A
vd
(s) ≈ 10
6
/s.
An error occurs when
¹
¹
¹
¹
v
OUT
(actual)
V
REF
≥
15
16

1
32
=
29
32
(Actual is always less than ideal)
15
31
.

}
` ω
max
10
6
2
+
.

}
`
16
31
2
≥
29
32
→
.

}
`
16
31
2
+
.

}
`
ω
max
10
6
2
≤
.

}
`
15
31
2
.

}
`
32
29
2
ω
max
10
6
≤
.

}
`
15
31
x
3 2
29
2

.

}
`
16
31
2
= 0.1367
v
OUT
R
EQ.
+

V
OS
V
REF
R
Fig. S10.205
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1011
Problem 10.205 Continued
∴ ω
max
≤ 0.1367x10
6
rads/sec. → f
max
≤ 21.76 kHz
Note that 21.76 kHz is much greater than 15.9 Hz (100 rads/sec.) so that the
approximation used for A
vd
(s) is valid.
Problem 10.206
An 8bit current DAC is shown. Assume that the full scale range is 1V. (a.) Find the value
of I if R = 1kΩ. (b.) Assume that all aspects of the DAC are ideal except for the op amp.
If the differential voltage gain of the op amp has a single pole frequency response with a dc
gain of 10
5
. Find the unity gainbandwidth, GB, in Hz that gives a worst case conversion
time of 2µs. (c.) Again assume that all aspects of the DAC are ideal except for the op amp.
The op amp is ideal except for a finite slew rate. Find the minimum slew rate, SR, in V/µs
that gives a worst case conversion time of 2µs.
+

I
I
2
I
4
I
128
v
out
R
F97E1P3
Solution
(a.) FSR = 2I·R = 1V ⇒ I = 1V/2kΩ = 500µA ∴ I = 500µA
(b.) Model for part b.
I
eq
= all bits switched
to the op amp input.
The worst case occurs
when all bits are
switched to the op
amp.
∴ V
out
= A
v
V
i
= A
v
[RI
eq
 V
out
] ⇒ V
out
(1+A
v
) = A
v
RI
eq
⇒ V
out
=
RI
eq
1
A
v
+ 1
or V
out
(s) =
RI
eq
s
GB
+ 1
Assuming a step input gives V
out
(s) =
.

}
`
RI
eq
s
GB
+ 1
1
s
∴ L
1
[V
out
(s)] = v
out
(t) = RI
eq
[1  e
GB·t
] µ(t)
Error(t) = RI
eq
 v
out
(t) ⇒ Error(T) = e
GB·T
= 1/2
8+1
= 1/512 ⇒ e
GB·T
= 512
If T= 2µs, then GB is given as GB = 0.5x10
6
ln(512) = 3.119x10
6
∴ GB= 0.496MHz
(c.) Slew Rate:
Want ∆V/∆T = 1V/2µs = 0.5V/µs assuming a ∆V ≈ 1V. ∴ SR = 0. 5V/ µs
+

I
eq
R
v
out
I
eq
R
v
out

+
V
i A
v
V
i
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1012
Problem 10.207
What is the necessary relative accuracy of resistor ratios in order for a voltagescaling DAC
to have a 8bit resolution?
Solution
Since the voltage scaling DAC has very small DNL errors, let the 8bit accuracy
requirement be determined by the INL error.
INL = 2
N1
∆R
R
≤ 0.5 →
∆R
R
≤
1
2
2
2
N
=
1
2
N
=
1
256
∴
∆ R
R
≤ 0. 39%
Problem 10.208
If the binary controlled switch b
1
of Fig. P10.23 is closed at t =0, find the time it takes the
output to achieve its final stage (V
REF
/2) by assuming that this time is 4 times the time
constant of this circuit. The differential voltage gain of the op amp is given as
A
vd
(s) =
10
6
s + 10
.
Solution
The model show will be used for this solution.
The transfer function for this problem can be
written as,
V
out
(s)
V
in
(s)
= 
.

}
`
R
0
R
1
R
1
A
vd
(s)
R
1
+R
0
1 +
R
1
A
vd
(s)
R
1
+R
0
= 0.5
1
1.5
A
vd
(s)
+1
≈ 0.5
1
1.5s
GB
+1
=  0.5
.

}
` 0.667x10
6
s+0.667x10
6
For a step input of magnitude V
REF
, we can write,
V
out
(s) = 0.5
.

}
` 0.667x10
6
s+0.667x10
6
V
REF
s
= 0.5
]
]
1
s

1
s+0.667x10
6
V
REF
The inverse Laplace transform gives,
v
out
(t) = 0.5[1e
0.667x10
6
t
]V
REF
The time constant of this circuit is 1/(0.667x10
6
) = 1.5µs which means that it will take 6µs
for the DAC to convert the switch change to the output voltage.
∴ Time for conversion = 6µs.
v
out
V
REF
R
1
= 2R
0
+

t = 0
+
R
0
Fig. S10.208
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1013
Problem 10.209
What is the necessary relative accuracy of capacitor ratios in order for a chargescaling
DAC to have 11bit resolution?
Solution
Perfect DNL will be impossible to achieve so let us use INL to answer the question and see
what the DNL is based on the INL.
INL = 2
N1
∆C
C
≤ 0.5 →
∆C
C
≤
1
2
2
2
N
=
1
2
N
=
1
2048
∴
∆ C
C
≤ 0. 0488% The corresponding DNL = (2
N
1)
∆C
C
≈ ±1LSB
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1014
Problem 10.210
For the charge scaling DAC of Fig. 10.210, investigate the influence of a load capacitor,
C
L
, connected in parallel with the terminating capacitor. (a.) Find an expression for v
OUT
as a function of C, C
L
, the digital bits, b
i
, and V
REF
. (b.) What kind of static error does
C
L
introduce? (c.) What is the largest value of C
L
/C possible before an error is introduced
in this DAC?
Solution
+

V
REF
φ
1
C
2 2
N2
2
N1
C
4
C C C
2
N1
C
φ
2
S
0
φ
2
φ
2
φ
2
φ
2
S
1
S
2
S
N2
S
N1
v
OUT
Terminating
Capacitor
Fig. S10.210
C
L
(a.) Charge conservation gives,
C
Total
v
OUT
=
.

}
`
b
0
C + b
1
C
2
+ b
2
C
4
+ · · · + b
N 2
C
2
N2
+ b
N 1
C
2
N1
V
REF
where C
Total
= 2C + C
L
.
v
OUT
=
.

}
`
C
2C + C
L
.

}
`
b
0
+
b
1
2
+
b
2
4
+ · · · +
b
N 2
2
N2
+
b
N 1
2
N1
V
REF
∴ v
OUT
=
.

}
`
1
1 +
C
L
2C
.

}
`
b
0
2
+
b
1
4
+
b
2
8
+ · · · +
b
N 2
2
N1
+
b
N 1
2
N
V
REF
(b.) If C
L
<< 2C, then v
OUT
≈
.

}
`
1 
C
L
2C
.

}
`
b
0
2
+
b
1
4
+
b
2
8
+ · · · +
b
N 2
2
N1
+
b
N 1
2
N
V
REF
which introduces a gain error.
(c.) From the previous result, the error term can be written as,
C
L
2C
.

}
`
b
0
2
+
b
1
4
+
b
2
8
+ · · · +
b
N 2
2
N1
+
b
N 1
2
N
V
REF
≤
1
2
V
REF
2
N
= 0.5 LSB
C
L
C
≤
1
2
N
.

}
`
b
0
2
+
b
1
4
+
b
2
8
+ · · · +
b
N 2
2
N1
+
b
N 1
2
N
≈
1
2
N
when all bits are 1 and N > 1.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1015
Problem 10.211
Express the output of the D/A converter shown in Fig. P10.211 during the φ
2
period as a
function of the digital bits, b
i
, the capacitors, and the reference voltage, V
REF
. If the op
amp has an offset of V
OS
, how is this expression for the output changed? What kind of
error will the op amp offset cause?
Solution
V
OS
= 0:
b
0
= 1: v
OUT
= 
C
x
2
n
C
V
REF
v
OUT
= 
.

}
`
∑
n
i=1
b
i
2
n
2
i
C
2
n
C
V
REF
→ v
OUT
= 
.

}
`
∑
n
i =1
b
i
2
i
V
REF
(b
0
= 1)
b
0
= 0: Reverse φ
1
and φ
2
to get,
v
OUT
= +
.

}
`
∑
n
i =1
b
i
2
i
V
REF
(b
0
= 0)
v
OUT
V
REF
+

φ
1
C
x
2
n
C
φ
2
Fig. S10.211B
φ
1
φ
2
φ
1
φ
2

+
φ
1
v
OUT
2
n
C
b
n b
n
C 2C
+

b
n1 b
n1
b
2
b
2
b
1 b
1
2
n2
C 2
n1
C
b
0
b
0
b
0
b
0
V
REF
Figure s10.211A
Σ b
i
2
ni
C = C
x
n
i=1
+

V
OS
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1016
Problem 10.211 – Continued
V
OS
≠ 0:
At φ
2
we have,
From this circuit, we can write that,
C
x
(V
REF
V
OS
) = 2
n
C(V
OS
– V
OS
–
v
OUT
)
or
v
OUT
= 
C
x
2
n
C
(V
REF
– V
OS
)
∴ v
OUT
= 
.

}
`
∑
n
i =1
b
i
2
i
(V
REF
– V
OS
) (b
0
= 1)
and
v
OUT
= +
.

}
`
∑
n
i =1
b
i
2
i
(V
REF
– V
OS
) (b
0
= 0)
V
OS
causes a gain error.
v
OUT
V
REF
+

C
x
2
n
C
Fig. S10.211C
+

V
OS
+ 
V
OS
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1017
Problem 10.212
Develop the equivalent circuit of Fig. 10.211 from Fig. 10.210.
Solution
For each individual capacitor connected only to V
REF
we can write,
V
out
= V
REF
C
2C
, V
out
= V
REF
C
4C
, V
out
= V
REF
C
8C
, …..
Note that the numerator consists only of the capacitances connected to V
REF
. If these
capacitors sum up to C
eq
. then the remaining capacitors must be 2C  C
eq
. Therefore, we
have,
C
eq
V
REF V
out
+

2CC
eq
S10.212
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1018
Problem 10.213
If the tolerance of the capacitors in the 8bit, binaryweighted array shown in Fig. P10.2
13 is ±0.5%, what would be the worst case DNL in units of LSBs and at what transition
does it occur?
V
REF
+

128
C
128
C
b
8
φ
1
φ
2
64
C
b
7
φ
2
32
C
b
6
φ
2
16
C
b
5
φ
2
8
C
b
4
φ
2
4
C
b
3
φ
2
2
C
b
2
φ
2
C
b
1
φ
2
v
OUT
Figure P10.213
Solution
The worst case DNL occurs at the transition form 01111111 to 10000000.
+DNL:
Ideally, v
OUT
=
C
eq
2CC
eq
+ C
eq
V
REF
. The worst case is found by assuming that
all of the C
eq
capacitors are maximu and the 2CC
eq
capacitors are minimum. However, for
the above transition, the maximum, worst case positive step can be written as
Max. step = v
OUT
(10000000) – v
OUT
(01111111) = V
REF
]
]
1.005
2

0. 995
2
.

}
`
1
1
128
=
V
REF
2
]
]
1.005  0.995
.

}
`
1
1
128
=
V
REF
2
[1.005 – 0.995(0.9922)]V
REF
= 0.008887V
REF
An LSB = V
REF
/256 = 0.003906V
REF
∴ +DNL =
0.008887
0.003906
 1 = 2. 275  1 = 1. 275 LSB
DNL:
For this case, let the C
eq
capacitors be minimum and the 2CC
eq
capacitors be
maximum. Following the same development as above gives,
Min. step = v
OUT
(10000000) – v
OUT
(01111111) = V
REF
]
]
0.995
2

1. 005
2
.

}
`
1
1
128
=
V
REF
2
]
]
0.995  1.005
.

}
`
1
1
128
=
V
REF
2
[0.995 – 1.005(0.9922)]V
REF
= 0.001074V
REF
∴ DNL =
0.001074
0.003906
 1 = 0. 2750  1 = 1. 275 LSB
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1019
Problem 10.214
A binary weighted DAC using a
charge amplifier is shown. At the
beginning of the digital to analog
conversion, all capacitors are discharged.
If a bit is 1, the capacitor is connected to
V
REF
and if the bit is 0 the capacitor is
connected to ground.
a.) Design C
X
to get
v
OUT
=
.

}
`
b
1
2
+
b
2
4
+ · · · +
b
N
2
N
V
REF
.
b.) Identify the switches by b
i
where i = 1 is the MSB and i = N is the LSB.
c.) Find the maximum component spread (largest value/smallest value) for the capacitors.
d.) Is this DAC fast or slow? Why?
e.) Can this DAC be nonmonotonic?
f.) If the relative accuracy of the capacitors are 0.2% (regardless of capacitor sizes) what is
the maximum value of N for ideal operation?
Solution
a.) Solving for v
OUT
gives
v
OUT
=
.

}
` C
C
X
+
2C
C
X
+ · · · +
2
N 1
C
C
X
V
REF
, therefore C
X
= 2
N
C which gives
v
OUT
=
.

}
`
1
2
N
+
1
2
N1
+ · · · +
1
2
V
REF
b.) See schematic for switch identification.
c.) The maximum component spread is C
X
/C which is Max. component spread = 2
N˚
d.) This DAC should be fast because there are no floating nodes.
e.) Yes, the DAC can be nonmonotonic.
f.) Let C
eq
be all capacitors connected to V
REF
. ∴
v
out
V
REF
= 
C
eq
C
x
.
For the worst case, let C
eq
be C
eq
+ ∆C
eq
and C
x
be C
x
 ∆C
x
which gives
v
out
’
V
REF
= 
C
eq
+∆C
eq
C
x
∆C
x
= 
C
eq
C
x
.

}
` 1+∆C
eq
/C
eq
1∆C
x
/C
x
= 
C
eq
C
x
.

}
`
1+0.002
10.002
= 
C
eq
C
x
.

}
`
501
499
∴
¹
¹
¹
¹
¹
¹
v
out
V
REF

v
out
’
V
REF
=
¹
¹
¹
¹
¹
¹

C
eq
C
x
+
.

}
`
501
499
C
eq
C
x
=
2
499
C
eq
C
x
≤
1
2
N+1
The largest value of C
eq
/C
x
is (2
N
1)/2
N
. ∴
2
499
≤
2
N
(2
N
1)(2
N
+1)
=
1
2
N
⇒ N = 7
(Note that N is almost equal to 8.)
+

C
X
C
2C
2
N1
C
V
REF
v
OUT
F97E1P2
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1020
Problem 10.215
A binary weighted DAC using The circuit shown is an equivalent for the
operation of a DAC. The op amp differential voltage gain, A
vd
(s) is modeled as
A
vd
(s) =
A
vd
(0) ω
a
s + ω
a
=
GB
s + ω
a
.
a.) If ω
a
goes to infinity so that A
vd
(s) ≈ A
vd
(0), what is the minimum value of A
vd
(0) that
will cause a ±0.5 LSB error for an 8bit DAC?
b.) If A
vd
(0) is larger than the value found in a.), what is the minimum conversion time for
an 8bit DAC which gives a ±0.5 LSB error if GB = 1Mhz?
Solution
a.) Model for the circuit:
v
i
=
.

}
`
C
C+C
v
REF
+
.

}
`
C
C+C
v
OUT
and
v
OUT
= Av
i
∴ v
OUT
=
A
2
v
OUT

A
2
v
REF
⇒
v
OUT
v
REF
=
A
2
1 +
A
2
Setting the actual gain to 1±0.5LSB gives
0.5A
1+0.5A
= 
.

}
`
1 
1
2
.

}
`
1
256
=
511
512
⇒ 
512A
2
= 511 
511A
2
⇒
A
2
= 511 ⇒
A = 1022
b.) If A
vd
(s) ≈ GB/s, then the sdomain transfer function can be written as
V
out
(s)
V
REF
=
GB/2
s + GB/ 2
=
ω
H
s + ω
H
⇒ ω
H
=
2π·10
6
2
= π·10
6
The time domain output can be written as
v
out
(t) = 1[1  e
ω
H
t
]V
REF
Setting v
out
(t) = 1±0.5LSB and solving for the time, T, at which this occurs gives
1 + e
ω
H
T
= 1 +
1
512
⇒ e
ωHT
= 512 ⇒ ω
H
T = ln(512) ⇒ T =
6.283
3.1416x10
6
or
T = 1. 9857µs
+

v
i
C C
v
OUT
v
IN
Av
i
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1021
Problem 10.216
A chargescaling DAC is shown in Fig. P10.216 that uses a C2C ladder. All capacitors
are discharged during the φ
1
phase. (a.) What value of C
F
is required to make this DAC
work correctly? (b.) Write an expression for v
OUT
during φ
2
in terms of the bits, b
i
, and
the reference voltage, V
REF
. (c.) Discuss at least two advantages and two disadvantages
of this DAC compared to other types of DACs.
Solution
+

C
2C
C
2C
C
2C
C
C
φ
1
C
F
V
REF b
0
b
1
b
2
b
3
φ
1
φ
1
φ
1
φ
1
φ
2
v
OUT
V
REF
V
REF
/2 V
REF
/4 V
REF
/8
Fig. S10.216
(a.) C
F
= 2C
(b.) v
OUT
=
.

}
`
b
0
2
V
REF
+
.

}
`
b
1
2
V
REF
2
+
.

}
`
b
2
2
V
REF
4
+
.

}
`
b
3
2
V
REF
8
v
OUT
=
.

}
`
b
0
2
+
b
1
4
+
b
2
8
+
b
3
16
V
REF
(c.) Advantages:
1.) Smaller area than binaryweighted DAC.
2.) Better accuracy because the components differ by only 2:1.
3.) Autozeros the offset of the op amp.
Disadvantages:
1.) Has floating nodes and is sensitive to parasitics.
2.) Parasitic capacitances at the floating nodes will deteriorate the accuracy.
3.) Can be nonmonotonic.
4.) Requires a twophase, nonoverlapping clock.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1022
Problem 10.301
The DAC of Fig. 10.31 has m = 2 and k = 2. If the divisor has an incorrect value of 2, express
the ±INL and the ±DNL in terms of LSBs and determine whether or not the DAC is monotonic.
Repeat if the divisor is 6.
Solution
The general form for the output of this DAC is,
v
OUT
V
REF
=
b
0
2
+
b
1
4
+
b
2
2k
+
b
3
4k
k = 2:
v
OUT
V
REF
=
b
0
2
+
b
1
4
+
b
2
4
+
b
3
8
The result is:
B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL
0 0 0 0 0.00000 0.00000   0.00000 0.00000
0 0 0 1 0.06250 0.12500 0.00000 1.00000 0.00000 1.00000
0 0 1 0 0.12500 0.25000 0.00000 1.00000 0.00000 2.00000
0 0 1 1 0.18750 0.37500 0.00000 1.00000 0.00000 3.00000
0 1 0 0 0.25000 0.25000 0.00000 3.00000 0.00000 0.00000
0 1 0 1 0.31250 0.37500 0.00000 1.00000 0.00000 1.00000
0 1 1 0 0.37500 0.50000 0.00000 1.00000 0.00000 2.00000
0 1 1 1 0.43750 0.62500 0.00000 1.00000 0.00000 3.00000
1 0 0 0 0.50000 0.50000 0.00000 3.00000 0.00000 0.00000
1 0 0 1 0.56250 0.62500 0.00000 1.00000 0.00000 1.00000
1 0 1 0 0.62500 0.75000 0.00000 1.00000 0.00000 2.00000
1 0 1 1 0.68750 0.87500 0.00000 1.00000 0.00000 3.00000
1 1 0 0 0.75000 0.75000 0.00000 3.00000 0.00000 0.00000
1 1 0 1 0.81250 0.87500 0.00000 1.00000 0.00000 1.00000
1 1 1 0 0.87500 1.00000 0.00000 1.00000 0.00000 2.00000
1 1 1 1 0.93750 1.12500 0.00000 1.00000 0.00000 3.00000
∴ INL = +3 LSB and 0 LSB . DNL = +1 LSB and –3 LSB . Nonmontonic because DNL <
1 LSB .
k = 6:
v
OUT
V
REF
=
b
0
2
+
b
1
4
+
b
2
12
+
b
3
24
The result is on the next page:
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1023
Problem 10.301 – Continued
B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL
0 0 0 0 0.00000 0.00000   0.00000 0.00000
0 0 0 1 0.06250 0.04167 0.00000 0.33333 0.00000 0.33333
0 0 1 0 0.12500 0.08333 0.00000 0.33333 0.00000 0.66667
0 0 1 1 0.18750 0.12500 0.00000 0.33333 0.00000 1.00000
0 1 0 0 0.25000 0.25000 0.00000 1.00000 0.00000 0.00000
0 1 0 1 0.31250 0.29167 0.00000 0.33333 0.00000 0.33333
0 1 1 0 0.37500 0.33333 0.00000 0.33333 0.00000 0.66667
0 1 1 1 0.43750 0.37500 0.00000 0.33333 0.00000 1.00000
1 0 0 0 0.50000 0.50000 0.00000 1.00000 0.00000 0.00000
1 0 0 1 0.56250 0.54167 0.00000 0.33333 0.00000 0.33333
1 0 1 0 0.62500 0.58333 0.00000 0.33333 0.00000 0.66667
1 0 1 1 0.68750 0.62500 0.00000 0.33333 0.00000 1.00000
1 1 0 0 0.75000 0.75000 0.00000 1.00000 0.00000 0.00000
1 1 0 1 0.81250 0.79167 0.00000 0.33333 0.00000 0.33333
1 1 1 0 0.87500 0.83333 0.00000 0.33333 0.00000 0.66667
1 1 1 1 0.93750 0.87500 0.00000 0.33333 0.00000 1.00000
∴ INL = +0 LSB and 1 LSB . DNL = +1 LSB and –0.333 LSB . Montonic because DNL
> 0.333 LSB .
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1024
Problem 10.302
Repeat Problem 10.31 if the divisor is 3 and 5.
Solution
k=3: v
OUT
=
.

}
`
b
0
2
+
b
1
4
V
REF
+
.

}
`
b
2
2
+
b
3
4
V
REF
3
=
]
]
b
0
2
+
b
1
4
+
b
2
6
+
b
3
12
V
REF
B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL
0 0 0 0 0.00000 0.00000   0.00000 0.00000
0 0 0 1 0.06250 0.08333 0.00000 0.33333 0.00000 0.33333
0 0 1 0 0.12500 0.16667 0.00000 0.33333 0.00000 0.66667
0 0 1 1 0.18750 0.25000 0.00000 0.33333 0.00000 1.00000
0 1 0 0 0.25000 0.25000 0.00000 1.00000 0.00000 0.00000
0 1 0 1 0.31250 0.33333 0.00000 0.33333 0.00000 0.33333
0 1 1 0 0.37500 0.41667 0.00000 0.33333 0.00000 0.66667
0 1 1 1 0.43750 0.50000 0.00000 0.33333 0.00000 1.00000
1 0 0 0 0.50000 0.50000 0.00000 1.00000 0.00000 0.00000
1 0 0 1 0.56250 0.58333 0.00000 0.33333 0.00000 0.33333
1 0 1 0 0.62500 0.66667 0.00000 0.33333 0.00000 0.66667
1 0 1 1 0.68750 0.75000 0.00000 0.33333 0.00000 1.00000
1 1 0 0 0.75000 0.75000 0.00000 1.00000 0.00000 0.00000
1 1 0 1 0.81250 0.83333 0.00000 0.33333 0.00000 0.33333
1 1 1 0 0.87500 0.91667 0.00000 0.33333 0.00000 0.66667
1 1 1 1 0.93750 1.00000 0.00000 0.33333 0.00000 1.00000
From the above table, INL = +1LSB and –0LSB, DNL = +0.33LSB and –1LSB. The DAC is
on the threshold of nonmonotonicity.
k=5: v
OUT
=
.

}
`
b
0
2
+
b
1
4
V
REF
+
.

}
`
b
2
2
+
b
3
4
V
REF
5
=
]
]
b
0
2
+
b
1
4
+
b
2
10
+
b
3
20
V
REF
B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL
0 0 0 0 0.00000 0.00000   0.00000 0.00000
0 0 0 1 0.06250 0.05000 0.00000 0.20000 0.00000 0.20000
0 0 1 0 0.12500 0.10000 0.00000 0.20000 0.00000 0.40000
0 0 1 1 0.18750 0.15000 0.00000 0.20000 0.00000 0.60000
0 1 0 0 0.25000 0.25000 0.00000 0.60000 0.00000 0.00000
0 1 0 1 0.31250 0.30000 0.00000 0.20000 0.00000 0.20000
0 1 1 0 0.37500 0.35000 0.00000 0.20000 0.00000 0.40000
0 1 1 1 0.43750 0.40000 0.00000 0.20000 0.00000 0.60000
1 0 0 0 0.50000 0.50000 0.00000 0.60000 0.00000 0.00000
1 0 0 1 0.56250 0.55000 0.00000 0.20000 0.00000 0.20000
1 0 1 0 0.62500 0.60000 0.00000 0.20000 0.00000 0.40000
1 0 1 1 0.68750 0.65000 0.00000 0.20000 0.00000 0.60000
1 1 0 0 0.75000 0.75000 0.00000 0.60000 0.00000 0.00000
1 1 0 1 0.81250 0.80000 0.00000 0.20000 0.00000 0.20000
1 1 1 0 0.87500 0.85000 0.00000 0.20000 0.00000 0.40000
1 1 1 1 0.93750 0.90000 0.00000 0.20000 0.00000 0.60000
From the above table, INL = +0LSB and –0.6LSB, DNL = +0.6LSB and –0.2LSB. The DAC
is monotonic.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1025
Problem 10.303
Repeat Problem 1 if the divisor is correct (4) and the V
REF
for the MSB subDAC is 0.75V
REF
and the V
REF
for the LSB subDAC is 1.25V
REF
.)
Soluiton
The analog output can be written as,
v
OUT
=
.

}
`
b
0
2
+
b
1
4
3V
REF
4
+
.

}
`
b
2
2
+
b
3
4
5V
REF
4
=
]
]
3b
0
8
+
3b
1
16
+
5b
2
32
+
5b
3
64
V
REF
B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL
0 0 0 0 0.00000 0.00000   0.00000 0.00000
0 0 0 1 0.06250 0.07813 0.00000 0.25000 0.00000 0.25000
0 0 1 0 0.12500 0.15625 0.00000 0.25000 0.00000 0.50000
0 0 1 1 0.18750 0.23438 0.00000 0.25000 0.00000 0.75000
0 1 0 0 0.25000 0.18750 0.00000 1.75000 0.00000 1.00000
0 1 0 1 0.31250 0.26563 0.00000 0.25000 0.00000 0.75000
0 1 1 0 0.37500 0.34375 0.00000 0.25000 0.00000 0.50000
0 1 1 1 0.43750 0.42188 0.00000 0.25000 0.00000 0.25000
1 0 0 0 0.50000 0.37500 0.00000 1.75000 0.00000 2.00000
1 0 0 1 0.56250 0.45313 0.00000 0.25000 0.00000 1.75000
1 0 1 0 0.62500 0.53125 0.00000 0.25000 0.00000 1.50000
1 0 1 1 0.68750 0.60938 0.00000 0.25000 0.00000 1.25000
1 1 0 0 0.75000 0.56250 0.00000 1.75000 0.00000 3.00000
1 1 0 1 0.81250 0.64063 0.00000 0.25000 0.00000 2.75000
1 1 1 0 0.87500 0.71875 0.00000 0.25000 0.00000 2.50000
1 1 1 1 0.93750 0.79688 0.00000 0.25000 0.00000 2.25000
From the above table, INL = +0.75LSB and –3LSB, DNL = +0.25LSB and –1.75LSB. The
DAC is not monotonicity.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1026
Problem 10.304
Find the worst case tolerance of x (∆x/x)
in % that will not cause a conversion error
for the DAC shown. Assume that all
aspects of the DAC are ideal except for x.
(Note: that the divisor is 1/x so that x is
less than 1.)
Solution
The tolerance is only influenced by the
bits of the LSB DAC. The ideal and
actual outputs are given as,
v
out
(ideal) = x
]
]
b
4
2
+
b
5
4
+
b
6
8
v
out
(actual) = (x ± ∆x)
]
]
b
4
2
+
b
5
4
+
b
6
8
∴ Worst case error = v
out
(actual)  v
out
(ideal) ≤ 1/2
7
⇒ ∆x
]
]
b
4
2
+
b
5
4
+
b
6
8
≤
1
2
7
=
1
128
The tolerance is decreased if all LSB bits are 1. Therefore,
∆x
.

}
`
7
8
≤
1
128
⇒ ∆x ≤
8
7
1
128
=
1
112
Therefore, the factor x can be expressed as,
x ± ∆x =
1
8
±
1
112
=
14
112
±
1
112
The tolerance of x is expressed as
Tolerance of x =
±∆x
x
=
± 1
14
= ±7. 143%
3bit
MSB
DAC
3bit
LSB
DAC
V
REF
= 1V
V
REF
= 1V
Σ
+
+
v
OUT
b
1
b
3
b
4
b
6
1
x
Fig. F97E1P1
b
2
b
5
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1027
Problem 10.305
The DAC of Fig. 10.32 has m = 3 and k = 3. Find
(a.) the ideal value of the divisor of V
REF
designated
as x. (b.) Find the largest value of x that causes a
1LSB DNL. (c.) Find the smallest value of x that
causes a 2LSB DNL.
Solution
a.) v
OUT
= V
REF
]
]
b
0
2
+
b
1
4
+
b
2
2k
+
b
3
4k
k = 4 for ideal behavior.
b.) Let v
OUT
’ = v
OUT
when k ≠ 4. Also note that
±1LSB = 1/16 when v
OUT
is normalized to V
REF
.
∴
v
OUT
’  v
OUT
V
REF
= ±
1
16
]
]
b
0
2
+
b
1
4
+
1
k
.

}
`
b
2
2
+
b
3
4

]
]
b
0
2
+
b
1
4
+
b
2
8
+
b
3
16
=
.

}
`
1
k

1
4
.

}
`
+
b
2
2
+
b
3
4
= ±
1
16
.

}
`
4
k
 1 (2b
2
+ b
3
) = ±1→
4
k
= 1 ±
.

}
`
1
2b
2
+ b
3
=
2b
2
+ b
3
±1
2b
2
+ b
3
∴ k =
4(2b
2
+ b
3
)
2b
2
+ b
3
±1
Try various combinations of b
2
and b
3
:
b
2
= 0 and b
3
= 1 → k =
4
1±1
= 2, ∞
b
2
= 1 and b
3
= 0 → k =
8
2±1
=
8
3
, 8
b
2
= 1 and b
3
= 1 → k =
12
3±1
= 4, 6
The smallest, largest value of k that maintains ±1LSB is 6. ∴ k = 6
(k is ideally 4 and the smallest of the maximum values is 6)
c.) For DNL, the worst case occurs from X011 to X100.
∴
v
OUT
(X100)v
OUT
(X011)
V
REF
/16
–1 = ±2
1
4

.

}
`
1
2k
+
1
4k
=
1
16
±
2
16
→ 4 
12
k
= 1±2 →
12
k
= 3(±2)
k =
12
3(±2)
= 12 or 2.4 ∴ k = 2.4
2bit
MSB
DAC
2bit
LSB
DAC
V
REF
V
REF
/k
Σ
+
+
v
OUT
b
0
b
1
b
2
b
3
Fig. S10.305
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1028
Problem 10.306
Show for the results of Ex. 10.32 that the resulting INL and DNL will be equal to –0.5LSB or
less.
Solution
Consider only the LSBs because the error in the division factor only affects the LSB subDAC.
INL:
The worst case INL occurs when both b
3
and b
4
are on. Therefore,
.

}
`
1
2
+
1
4
.

}
`
6±1
24
=
.

}
`
3
4
.

}
`
6±1
24
=
6±1
32
=
5
32
,
7
32
INL
+
(max) = V
o
(actual)  V
o
(ideal) =
7
32

6
32
=
1
32
= +0.5LSB
INL

(max) = V
o
(actual)  V
o
(ideal) =
5
32

6
32
=
1
32
= 0.5LSB
Therefore, the worst case INL is equal to or less than ±0.5LSB.
DNL:
The worst case DNL occurs when both bits of the LSB subDAC change from 1 to 0.
This corresponds to a change from 0011 to 0100. If the scaling factor is 7/24 corresponding to
the +1/24 tolerance, then
∆V
o
= V
o
(0011) V
o
(0100) =
5
32

1
4
=
5
32

8
32
=
3
32
DNL
+
= ∆V
o

2
32
=
3
32

2
32
=
1
32
= +0.5LSB
If the scaling factor is 5/24 corresponding to the 1/24 tolerance, then
∆V
o
= V
o
(0011) V
o
(0100) =
7
32

1
4
=
7
32

8
32
=
1
32
DNL

= ∆V
o

2
32
=
1
32

2
32
=
1
32
= 0.5LSB
Therefore, the worst case DNL is equal to or less than ±0.5LSB.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1029
Problem 10.307
A 4bit, digitalanalog converter is shown in Fig. P10.37. When a bit is 1, the switch
pertaining to that bit is connected to the op amp negative input terminal, otherwise it is connected
to ground. Identify the switches by the notation b
1
, b
2
, b
3
, or b
4
where b
i
corresponds to the ith
bit and b
1
is the MSB and b
4
is the LSB. Solve for the value of R
x
which will give proper
digitalanalog converter performance.
+

4R
4R
R
2R 4R 2R
V
REF
R
x
v
OUT
MSB LSB
I
0
I
1
I
2 I
3
b
0
b
1
b
2
b
3
V
x
S10.307
Solution
For this circuit to operate properly, I
0
=
V
REF
2R
, I
1
=
I
0
2
, I
2
=
I
0
4
, and I
3
=
I
0
8
.
To achieve this result, V
x
= 
V
REF
4
. The equivalent resistance seen to ground from the right of
R
x
can be expressed as,
R
EQ
= 2R(4R4R) = 2R2R = R
∴ V
x
=
R
R+R
x
(V
REF
) = 
V
REF
4
∴ R
x
= 3R
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1030
Problem 10.308
Assume R
1
=R
5
=2R, R
2
=R
6
=4R, R
3
=R
7
=8R, R
4
=R
8
=16R and that the op amp is ideal. (a.)
Find the value of R
9
and R
10
in terms of R which gives an ideal 8bit digitaltoanalog converter.
(b.) Find the range of values of R
9
in terms of R which keeps the INL ≤ ±0.5LSB. Assume that
R
10
has its ideal value. Clearly state any assumption you make in working this problem. (c.)
Find the range of R
10
in terms of R which keeps the converter monotonic. Assume that R
9
has
its ideal value. Clearly state any assumptions you make in working this problem.
Solution
(a.) R
8
= 16R and R
9
= R
(b.) v
OUT
= V
REF
.

}
`
b
0
2
+
b
1
4
+
b
2
8
+
b
3
16
+
R
R
8
V
REF
.

}
`
b
4
2
+
b
5
4
+
b
6
8
+
b
7
16
The worst case INL occurs when the bits in the MSB subDAC are zero and the bits in the LSB
subDAC are one.
∴ v
OUT
=
R
R
8
V
REF
.

}
`
b
4
2
+
b
5
4
+
b
6
8
+
b
7
16
v
OUT
(ideal) =
1
16
V
REF
.

}
`
b
4
2
+
b
5
4
+
b
6
8
+
b
7
16
∴ INL = v
OUT
 v
OUT
(ideal) =V
REF
.

}
`
b
4
2
+
b
5
4
+
b
6
8
+
b
7
16
.

}
`
R
R
8

1
16
= +
1
2
V
REF
256
512(0.9375)
.

}
`
R
R
8

1
16
= 1 →
R
R
8
= 0.064583 → R
8
= 15.4838R
Also, INL = v
OUT
 v
OUT
(ideal) =V
REF
.

}
`
b
4
2
+
b
5
4
+
b
6
8
+
b
7
16
.

}
`
R
R
8

1
16
= 
1
2
V
REF
256
512(0.9375)
.

}
`
R
R
8

1
16
= 1 →
R
R
8
= 0.060417 → R
8
= 16.5517R
∴ 15. 4838R ≤ R
8
≤ 16.5517R
(c.) Worst case monotonicity occurs when the bits of the LSB subDAC go from 1 to 0.
v
OUT
(LSBs =1) =
V
REF
16
.

}
`
1
2
+
1
4
+
1
8
+
1
16
=
V
REF
16
.

}
`
15
16
v
OUT
(b
3
=1, all others 0) = V
REF
R
R
9
.

}
`
1
16
Nonmonotonicity ⇒ V
REF
R
R
9
.

}
`
1
16
>
V
REF
16
.

}
`
15
16
→ R
9
<
1 5
16
R
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1031
Problem 10.309
Design a tenbit, twostage chargescaling D/A converter similar to Fig. 10.34 using two fivebit
sections with a capacitive attenuator between the stages. Give all capacitances in terms of C,
which is the smallest capacitor of the design.
Solution
The result is shown below.
C
16
b
9
C
8
b
8
C
4
b
7
C
2
b
6
C
b
5
V
REF
2C
32 C
16
C
16
b
4
C
8
b
3
C
4
b
2
C
2
b
1
C
b
0
+

Fig. S10.309
v
out
The design of the connecting capacitor, C
s
, is done as follows,
C
16
=
1
1
C
s
+
1
2C
→
1
C
s
+
1
2C
=
16
C
→
1
C
s
=
32
2C

1
2C
=
31
2C
∴ C
s
=
2C
31
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1032
Problem 10.310
A twostage, chargescaling D/A converter is shown in Fig. P10.310. (a.) Design C
x
in terms
of C, the unit capacitor, to achieve a 6bit, twostage, chargescaling DAC. (b.) If C
x
is in error
by ∆C
x
, find an expression for v
OUT
in terms of C
x
, ∆C
x
, b
i
and V
REF
. (c.) If the expression
for v
OUT
in part (b.) is given as
v
OUT
=
V
REF
8
.

}
`
1˚˚
17∆C
x
100C
x
]
]
]
]
∑
i=1
3
b
i
2
3i
˚+˚
.

}
`
1˚+˚
8∆C
x
10C
x
˚
∑
i=4
6
˚
b
i
2
6i
8
what is the accuracy of C
x
necessary to avoid an error using worst case considerations.
+


+
V
REF
C
b
5
b
4
b
3
v
OUT
(The switch designated by b is connected to V if
the ith bit is "1" and ground if the ith bit is "0".)
i REF
2C 4C
C C 2C 4C
C
x
b
2
b
1
b
0
Fig. S10.310
C
eq
Solution
(a.) The value of C
eq
. must be C. Therefore,
1
C
=
1
C
x
+
1
8C
→
1
C
x
=
7
8C
→ C
x
=
8C
7
(b.) The model for the analysis is found by using Thevenin’s equivalent circuits and is ,
v
r
=
∑
i=0
2
b
i
2
2i
7
V
REF
v
l
=
∑
i=3
5
b
i
2
5i
8
V
REF
v
OUT
=
.

}
`
1
8C
+
1
C
x
+∆C
x
1
8C
+
1
7C
+
1
C
x
+∆C
x
v
r
+
.

}
`
1
7C
1
8C
+
1
7C
+
1
C
x
+∆C
x
v
l
v
OUT
v
l
C
x
+ ∆C
x
8C
v
r
7C
Fig. S10.310B
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1033
Problem 10.310 – Continued
v
OUT
=
.

}
`
1
8C
+
1
C
x
(1+∆C
x
/C
x
)
1
8C
+
1
7C
+
1
C
x
(1+∆C
x
/C
x
)
v
r
+
.

}
`
1
7C
1
8C
+
1
7C
+
1
C
x
(1+∆C
x
/C
x
)
v
l
Let C
x
=
8C
7
and
∆C
x
C
x
= ε
∴ v
OUT
=
.

}
`
1
8C
+
7
8C
.

}
`
1
1+ε
1
8C
+
1
7C
+
7
8C
.

}
`
1
1+ε
v
r
+
.

}
`
1
7C
1
8C
+
1
7C
+
7
8C
.

}
`
1
1+ε
v
l
Assume that
1
1+ε
≈ 1ε to get,
v
OUT
≈
.

}
`
1
8
+
7
8

7ε
8
1
8
+
1
7
+
7
8

7ε
8
v
r
+
.

}
`
1
7
1
8
+
1
7
+
7
8

7ε
8
v
l
=
.

}
`
1 
7ε
8
1 +
1
7

7ε
8
v
r
+
.

}
`
1
7
1 +
1
7

7ε
8
v
l
v
OUT
=
.

}
`
7 
49ε
8
8 
49ε
8
v
r
+
.

}
`
1
8 
49ε
8
v
l
=
7
8
.

}
`
1 
49ε
56
1 
49ε
64
v
r
+
1
8
.

}
`
1 
49ε
64
v
l
v
OUT
=
7
8
.

}
`
1 
49ε
56
1 
49ε
64
.

}
`
v
r
+
v
l
7
.

}
`
1 
49ε
56
≈
7
8
]
]
1 +
.

}
`
49
64

4 9
56
ε
.

}
`
v
r
+
1
7.

}
`
1 +
49ε
56
v
l
v
OUT
=
7
8.

}
`
1
7ε
64
]
]
]
]
∑
i=0
2
b
i
2
2i
7
V
REF
+
1
7.

}
`
1 +
49ε
56
∑
i=3
5
b
i
2
5i
8
V
REF
∴ v
OUT
=
V
REF
8 .

}
`
1
7ε
64
]
]
]
]
∑
i=0
2
b
i
2
2i
+
.

}
`
1 +
7ε
8
∑
i=3
5
b
i
2
5i
8
(c.) The error due to ∆C
x
should be less than ±0.5LSB. Worst case is for all bits 1.
∴
.

}
`

17∆C
x
100C
x
+
8∆ C
x
10C
x
7V
REF
8
≤
V
REF
2
N+1
=
V
REF
128
→
∆ C
x
C
x
≤ 1. 685%
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1034
Problem 10.311
If the op amps in the circuit below have a dc gain of 10
4
and a dominant pole at 100Hz, at what
clock frequency will the effective number of bits (ENOB) = 7bits assuming that the capacitors
and switches are ideal? Use a worst case approach to this problem and assume that time
responses of the LSB and MSB stages add to give the overall conversion time.
V
REF
+

v
OUT
+

C
b
5
φ
2
b
5
C/2
b
6
φ
2
b
6
b
7
φ
2
b
7
b
8
φ
2
b
8
C/4
C/8
+

2C
φ
1
V
REF
+

C
b
1
φ
2
b
1
C/2
b
2
φ
2
b
2
b
3
φ
2
b
3
b
4
φ
2
b
4
C/4
C/8
+

2C
φ
1
C/8
A1 A2
LSB Array MSB Array
v
O1
F97FEP3
Solution
The worst case approach assumes that all capacitors are
switched into the op amp input and that both stages can be
modelled approximately as shown.
With a single pole model for the op amp, it can be shown
that the 3dB frequency is given as follows where C
1
= C
2
gives the lowest 3dB frequency.
ω
H
=
GB·C
2
C
1
+C
2
=
GB
2
= πx10
6
radians/sec
∴ v
out
(t) = (C
1
/C
2
)[1  e
ω
H
t
]V
REF
ENOB of 7 bits ⇒ ±
1
2
V
REF
2
7
= ±
V
REF
2
8
v
out
(T) = V
REF

V
REF
2
8
∴ 1 
1
2
8
= 1  e
ω
H
T
⇒ e
ω
H
T
= 2
8
⇒ T =
8
ω
Η
ln(2) =
8
πx10
6
0.693 = 1.765µs
Double this time for 2 stages to T
clock
= 3.53µs ⇒ f
cl ock
=
1
T
clock
= 283kHz
+

F97FES3
V
REF
t=0
2C 2C
v
out
(t)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1035
Problem 10.312
The DAC shown uses two identical, 2bit DACs to achieve a 4bit D/A converter. Give an
expression for v
OUT
as a function of V
REF
and the bits, b
1
, b
2
, b
3
, and b
4
during the φ
2
phase
period. The switches controlled by the bits are closed if the bit is high and open if the bit is low
during the φ
2
phase period. If k = 2, express the INL (in terms of a ±LSB value) and DNL (in
terms of a ±LSB value) and determine whether the converter is monotonic or not. (You may use
the outputinput plot on the next page if you wish.)
Solution
During the φ
2
phase the DAC can be modeled as:
v
OUT
(φ
2
) =
]
]
.

}
`
b
1
2
+
b
2
4
+
1
k
.

}
`
b
2
2
+
b
4
4
V
REF
If k = 2, then
v
OUT
(φ
2
)
V
REF
=
b
1
2
+
b
2
4
+
b
3
4
+
b
4
8
Input Digital Word Output for k = 4 Output for k = 2
0000 0 0
0001 1/16 2/16
0010 2/16 4/16
0011 3/16 6/16
0100 4/16 4/16
0101 5/16 6/16
0110 6/16 8/16
0111 7/16 10/16
1000 8/16 8/16
1001 9/16 10/16
1010 10/16 12/16
1011 11/16 14/16
1100 12/16 12/16
1101 13/16 14/16
1110 14/16 16/16
1111 15/16 18/16
v
OUT
V
REF
+

b
1
C
2
V
REF
b
2
C
4
V
REF
b
3
C
2
V
REF
b
4
C
4
C
S01E3S3
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1036
Problem 10.312 – Continued
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b1
b2
b3
b4
Digital Input Code
0/16
1/16
2/16
3/16
4/16
5/16
6/16
7/16
8/16
9/16
10/16
11/16
12/16
13/16
14/16
15/16
16/16
A
n
a
l
o
g
O
u
t
p
u
t
(
N
o
r
m
a
l
i
z
e
d
t
o
F
u
l
l
S
c
a
l
e
)
Actual 4bit DAC
Characteristic
Ideal 4bit DAC
characteristic
S01E3S3B
The INL is +3LSB and –0LSB.
The DNL is +1LSB and –3LSB.
Converter is definitely not monotonic.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1037
Problem 10.313
An Nbit DAC consists of a voltage scaling DAC of Mbits and a charge scaling DAC of Kbits
(N=M+K). The accuracy of the resistors in the Mbit voltage scaling DAC is –∆R/R. The
accuracy of the binaryweighted capacitors in the charge scaling DAC is –∆C/C. Assume for
this problem that INL and DNL can be expressed generally as,
INL = Accuracy of component x Maximum weighting factor
DNL = Accuracy of the largest component x Corresponding weighting factor
where the weighting factor for the ith bit is 2
Ni+1
.
(a.) If the MSB bits use the Mbit voltage scaling DAC and the LSB bits use the Kbit charge
scaling DAC, express the INL and DNL of the Nbit DAC in terms of M, K, N, ∆R/R, and
∆C/C. (b.) If the MSB bits use the Kbit charge scaling DAC and the LSB bits use the Mbit
voltage scaling DAC, express the INL and DNL of the Nbit DAC in terms of M, K, N, ∆R/R,
and ∆C/C.
Solution
(a.) In a Mbit voltage scaling DAC, there are 2
M
resistors between V
REF
and ground. The
voltage at the bottom of the ith resistor from the top is v
i
=
(2
M
i)R
(2
M
i)R + i R
V
REF
where the iR
resistors are above v
i
and the 2
M
i resistors are below v
i
. The worst case INL(R) for the voltage
scaling DAC is found at the midpoint where i = 2
M1
and the resistors below are all maximum
positive and the resistors above are all maximum negative. Thus,
INL(R) = v
2
M1(actual)  v
2
M1(ideal) =
2
M1
(R+∆R)V
REF
2
M1
(R+∆R) + 2
M1
(R∆R)

V
REF
2
=
∆R
2R
or I NL(R) =
2
M
2
M
.

}
` ∆R
2R
= 2
M1
∆R
R
LSBs
The worst case DNL(R) for the voltage scaling DAC is found as the maximum step size minus
the ideal step size. Thus,
DNL(R) = v
step
(actual)  v
step
(ideal) =
(R±∆R)V
REF
2
M
R

R
2
M
R
V
REF
=
±∆R
2
M
R
V
REF
or DNL(R) =
.

}
` ±∆R V
REF
2
M
R
2
N
2
N
=
±2
N
2
M
∆R
R
= ±2
K
∆R
R
LSBs
Let us now examine the INL(C) and the DNL(C) of a Kbit binaryweighted capacitor array.
The ideal output for the ith capacitor is given as
v
OUT
(ideal) =
C/2
i1
2C
V
REF
=
V
REF
2
i
.

}
` 2
K
2
K
=
2
K
2
i
LSBs
The actual worscase output for the ith capacitor is given as
v
OUT
(actual) =
(C±∆C)/2
i1
2C
V
REF
=
V
REF
2
i
±
∆C·V
REF
2
i
C
=
2
K
2
i
±
2
K
∆C
2
i
C
LSBs
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1038
Problem 10.313 — Continued
Therefore, the INL due to the binaryweighted capacitor array is
INL(C) = v
OUT
(actual)  v
OUT
(ideal) = ±
2
K
∆C
2
i
C
= ±
2
Ki
∆C
C
LSBs
The worst case occurs for i = 1 which gives I NL(C) = ±
2
K 1
∆C
C
LSBs
Finally, the worst case DNL due to the binaryweighted capacitor array is found as
DNL(C) = v
OUT
(1000….)  v
OUT
(0111….) =
2
K1
∆C
C
+
2
K1
∆C
C
=
2
K
∆C
C
LSBs
The INL when the MSBs use voltage scaling and the LSBs use charge scaling is,
INL = INL(R) + INL(C) = 2
M1
∆R
R
+ 2
N1
∆C
C
where the LSB of the charge scaling DAC is now VREF/2
N
rather than VREF/2
K
.
The DNL when the MSBs use voltage scaling and the LSBs use charge scaling is,
DNL = DNL(R) + DNL(C) = 2
K
∆R
R
+ 2
K
∆C
C
= 2
K
.

}
` ∆R
R
+
∆ C
C
(b.) Fortunately we can use the above results for the case where the MSBs use the chargescaling
DAC and the LSBs use the voltage scaling DAC.
For INL(R) the LSB is now V
REF
/2
N
. Therefore,
INL(R) =
2
N
2
N
.

}
` ∆R
2R
V
REF
= 2
N1
∆R
R
LS Bs
For the INL(C), K is replaced with N to give,
I NL(C) = ±
2
N 1
∆C
C
LSBs
For the DNL(R), the LSB is V
REF
/2
N
so that the DNL(R) for part (b.) becomes
DNL(R) =
±∆R
2
N
R
V
REF
=
±∆R
R
LSBs )
Since the MSB for the chage scaling DAC is now N, the DNL(C) becomes
DNL(C) =
2
N
∆C
C
LS Bs
Combining the above results gives the INL and DNL for the case where the MSBs use the charge
scaling DAC and the LSBs use the voltage DAC. The result is,
I NL = 2
N 1
.

}
` ∆R
R
+
∆C
C
LSBs and
DNL =
.

}
`
2
N1
∆C
C
+
∆ R
R
L S B s
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1039
Problem 10.314
Below are the formulas for INL and DNL for the case where the MSB and LSB arrays of an
digitaltoanalog converter are either voltage or charge scaling. n = m+k, where m is the number
of bits of the MSB array and k is the number of bits of the LSB array and n is the total number of
bits. Find the values of n, m, and k and tell what type of DAC (voltage MSB and charge LSB or
charge MSB and voltage LSB) if ∆R/R = 1% and ∆C/C = 0.1% and both the INL and DNL of
the DAC combination should each be 1LSB or less.
DAC Combination INL (LSBs) DNL (LSBs)
MSB voltage (mbits)
LSB charge (kbits)
2
n1
∆R
R
+ 2
k1
∆C
C
2
k
∆R
R
+ (2
k
1)
∆C
C
MSB charge (mbits)
LSB voltage (kbits)
2
m1
∆R
R
+ 2
n1
∆C
C
∆R
R
+ (2
n
1)
∆C
C
Solution
MSB voltage, LSB charge:
1 ≥ 2
n1
.

}
`
1
100
+ 2
k1
.

}
`
1
1000
⇒ 1000 ≥ 10·2
n1
+ 2
k1
1 ≥ 2
k
.

}
`
1
100
+ (2
k
1)
.

}
`
1
1000
⇒ 1000 ≥ 10·2
k
+ 2
k
1 ⇒
999
11
= 90.8 ≥ 2
k
⇒ k = 6
Substituting this k into the first equation gives
1000  32
10
= 96.8 ≥ 2
n1
⇒ n = 7 which gives m = 1 and k = 6.
MSB charge, LSB voltage:
1 ≥ 2
m1
.

}
`
1
100
+ 2
n1
.

}
`
1
1000
⇒ 1000 ≥ 5·2
m
+ 2
n1
1 ≥
1
100
+ (2
n
1)
.

}
`
1
1000
⇒ 1000 ≥ 10+ 2
n
1 ⇒ 991 ≥ 2
n
⇒ n = 9
Substituting this n into the first equation gives
1000  256
5
= 148.8 ≥ 2
m
⇒ m = 7 which gives n = 9 and k = 2.
Therefore, the DAC combination where the MSBs are charge scaling and the LSBs are voltage
scaling gives the most bits when both INL and DNL are 1LSB. The number of bits is n = 9 with
m = 7 bits of charge scaling for the MSB DAC and k = 2 bits of voltage scaling for the LSB
DAC.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1040
Problem 10.315
The circuit shown is a doubledecoder D/A converter. Find an expression for v
X
in terms of
V
1
, V
2
, and V
REF
when the φ
2
switches are closed. If A=1, B=0, C=1, and D=1, will the
comparator output be high or low if V
analog
= 0.8V
REF
?
φ
1
φ
2
φ
1
φ
2
φ
2
R
R
R
R

+
φ
1
φ
1
φ
2
φ
1
A
B
C
C
D
D
B
B
B
D
D
A
C
C
C
4
C
4
V
Analog
Figure S10.315
V
REF
R
R
R
R
0.75V
REF
0.5V
REF
0.25V
REF
V
2
V
1
v
x
v
OUT
Solution
At φ
2
we have the following equivalent circuit:
Summing the currents to zero gives,
sC(v
Analog
v
x
) + sC(V
1
v
x
) +
sC
4
.

}
`

V
REF
4
 v
x
+
sC
4
(V
2
 v
x
) = 0
or
sCv
Analog
 CV
1
– C
V
REF
16
+ C
V
2
4
= v
x
.

}
`
C+C+
C
4
+
C
4
∴ v
x
=
C
C
total
.

}
`
v
Analog
 V
1
+
V
2
4

V
R E F
16
=
2
5
v
Analog

2
5
V
1
+
V
2
10

V
REF
16
For ABCD = 1011 → v
Analog
 V
1
+
V
2
4

V
REF
16
=
12V
REF
16

12V
REF
16
+
4V
REF
16

V
REF
16
> 0
Since v
x
> 0, the comparator output will be low .
v
Analog
V
2
V
REF
4
v
x
V
1
C
C
C/4
C/4
Fig. S10.315A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1041
Problem 10.316
A 4bit, analogtodigital converter is shown. Clearly explain the operation of this converter for
a complete conversion in a clock periodbyclock period manner, where φ
1
and φ
2
are non
overlapping clocks generated from the square ware with a period of T (i.e. φ
1
occurs in 0 to T/2
and φ
2
in T/2 to T, etc.). What will cause errors in the operation of this analogtodigital
converter?
φ
1
φ
2
R
R
R

+
φ
1
φ
1
φ
2
A
B
B
B
B
A
C
C
V
Analog
V
REF
V
1
v
X
C
C
D
D
D
D
R
4
R
4
R
4
R
4
MSB
LSB
A B C D
φ
1
φ
2
To bit switches
Nonoverlapping
twophase clocks
T
Successive approxi
mation register and
control logic
Square wave
V
2
V
T
Figure S10.316
3
4
V
REF
2
4
V
REF
1
4
V
REF
3
16
V
REF
2
16
V
REF
1
16
V
REF
Solution
Consider the operation during a φ
1
φ
2
cycle. The voltage v
x
can be written in general as,
v
x
=
V
analog
2

V
1
2
+
V
2
2
=
1
2
(V
analog
V
1
+ V
2
)
The operation of the ADC will proceed as follows:
1.) Period 1 (0 ≤ t ≤ T):
SAR closes switches A, B
_
, C
_
, and D
_
(1000) to get
v
x
=
1
2
.

}
`
V
analog

3
8
V
REF
+
1
8
V
REF
=
1
2
.

}
`
V
analog

1
2
V
REF
If v
x
> 0, then A = 1. Otherwise, A = 0 (A
_
=1).
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1042
Problem 10.316 – Continued
2.) Period 2 (T ≤ t ≤ 2T):
a.) A = 1
SAR closes switches A,B , C
_
, and D
_
(1100) to get
v
x
=
1
2
.

}
`
V
analog
 V
REF
+
1
4
V
REF
=
1
2
.

}
`
V
analog

3
4
V
REF
b.) A
_
= 1
SAR closes switches A
_
,B , C
_
, and D
_
(0100) to get
v
x
=
1
2
.

}
`
V
analog

1
2
V
REF
+
1
4
V
REF
=
1
2
.

}
`
V
analog

1
4
V
REF
If v
x
> 0, the B = 1 (X100). Otherwise, B = 0 (B
_
=1) (X000).
3.) Period 3 (2T ≤ t ≤ 3T):
At this point, V
1
, will not change since A and B are known.
The SAR closes the appropriate A and B switches and C and D
_
(XX10) to get
v
x
=
1
2
.

}
`
V
analog
 V
1
+
2
16
V
REF
=
1
2
.

}
`
V
analog
 V
1
+
1
8
V
REF
If v
x
> 0, then C = 1 (XX10). Otherwise, C = 0 (C
_
= 1) (XX00).
4.) Period 4 (3T ≤ t ≤ 4T):
a.) D = 1
SAR closes switches appropriate Aand B switcheds and C, and D (XX11) to get
v
x
=
1
2
.

}
`
V
analog
 V
1
+
1
16
V
REF
b.) D
_
= 1
SAR closes switches appropriate Aand B switcheds and C, and D
_
(XX10) to get
v
x
=
1
2
.

}
`
V
analog
 V
1
+
3
16
V
REF
If v
x
> 0, then D = 1 (XXX1). Otherwise, D = 0 (D
_
= 1) (XXX0).
Sources of error:
1.) Op amp/comparator – gain, GB, SR, settling time (offset not a problem).
2.) Resistor and capacitor matching.
3.) Switch resistance and feedthrough.
4.) Note parasitic capacitances.
5.) Reference accuracy and stability.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1043
Problem 10.401
What is v
C1
in Fig. 10.41 after the following sequence of switch closures? S
4
, S
3
, S
1
, S
2
, S
1
,
S
3
, S
1
, S
2
, and S
1
?
Solution
The plots for v
C1
/V
REF
and v
C2
/V
REF
are given below.
0 1 2 3 4 5 6 7 8
v
C1
/V
REF
t/T
0 1 2 3 4 5 6 7 8
v
C2
/V
REF
t/T
1.0
0.75
0.5
0.25
0
0.625
1.0
0.75
0.5
0.25
0
0.625
Fig. S10.401
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1044
Problem 10.402
Repeat the above problem if C
1
1.05C
2
.
Solution
In the sharing phase, we have the following equivalent circuit:
v
out
(i) = V
C1
C
1
C
1
+C
2
+ V
C2
C
2
C
1
+C
2
=
1.05
2.05
V
C1
+
1
2.05
V
C2
= 0.5122V
C1
+ 0.4878V
C2
Sharing Phase (i) V
C1
(i)/V
REF
V
C2
(i)/V
REF
V
out
(i)/V
REF
1 0 0 0
2 1 0 0.5112
3 0 0.5122 0.2498
4 1 0.2498 0.6340
Thus, at the end of the conversion, the output voltage is 0.6340V
REF
rather than the ideal value
of 0.6250V
REF
.
Problem 10.403
For the serial DAC shown, every time
the switch S
2
opens, it causes the
voltage on C
1
to be decreased by
10%. How many bits can this DAC
convert before an error occurs
assuming worst case conditions and
letting V
REF
= 1V? The analog output is taken across C
2
.
Solution
Worst case is for all 1’s.
i V
C1
(ideal) V
C1
(act.) V
C2
(ideal) V
C2
(act.) V
REF
2
i+1
V
C2
(ideal) 
V
C2
(act.)
OK?
1 1 0.9 0.5 0.45 0.25 0.050 Yes
2 1 0.9 0.75 0.675 0.125 0.0750 Yes
3 1 0.9 0.875 0.7875 0.0625 0.0875 No
Error occurs at the third bit.
Note that the approach is to find the ideal value of V
C2
at the ith bit and then find the range that
V
C2
could have which is ±V
REF
/2
i+1
and still not have an error. If the difference between the
magnitude of the ideal value and actual value of V
C2
exceeds V
REF
/2
i+1
then an error will
occur.
C
1
V
C1
C
2
V
C2
v
out
FigS10.402
V
REF
S
2
S
3
S
1
S
4
C
2 C
1
v
C2
F97E1P4
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1045
Problem 10.404
For the serial, pipeline DAC of Fig. 10.43 find the ideal analog output voltage if V
REF
= 1V
and the input is 10100110 from the MSB to the LSB. If the attenuation factors of 0.5 become
0.55, what is the analog output for this case?
Solution
Ignoring the delay terms,the output of Fig. 10.43 can be written as,
V
out
V
REF
= b
0
+
b
1
2
+
b
2
4
+
b
3
8
+
b
4
16
+
b
5
32
+
b
6
64
+
b
7
128
For 10100110 we get,
V
out
V
REF
(ideal) = 1 
1
2
+
1
4

1
8

1
16
+
1
32
+
1
64

1
128
=
128
128

64
128
+
32
128

16
128

8
128
+
4
128
+
2
128

1
128
=
77
128
= 0.60156
If the attenuation factor is k = 0.55, the output can be reexpressed as,
V
out
V
REF
(actual) = kb
0
+ k
2
b
1
+ k
3
b
2
+ k
4
b
3
+ k
5
b
4
+ k
6
b
5
+ k
7
b
6
+ 8
8
b
7
= +0.55 – 0.3025 + 0.1664 – 0.0915 – 0.0503 + 0.0277 + 0.0152 – 0.00837
= 0.3066
Problem 10.405
Give an implementation of the pipeline DAC of Fig. 10.43 using twophase, switched capacitor
circuits. Give a complete schematic with the capacitor ratios and switch phasing identified.
Solution
All of the stages can be represented by the following block diagram.
v
i
= (0.5v
i+1
± b
i
V
REF
)z
1
which is a summing sample and hold with weighted inputs. A
possible switchedcapacitor realization of the ith stage (and all
stages) is shown below.
+

C 2C
φ
1
φ
2
φ
2
v
i v
i+1
φ
x
φ
y
V
REF
φ
1
φ
1
φ
x
=φ
1
and φ
y
=φ
2
if b
i
=1
φ
x
=φ
2
and φ
y
=φ
1
if b
i
=0
Fig. S10.45B
v
i+1
Σ z
1
±b
i
V
REF
1
2
v
i
Fig. S10.405A
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1046
Problem 10.406
A pipeline DAC is shown. If k
1
= 7/16, k
2
= 5/7, and k
3
= 3/5 write an expression for v
OUT
in
terms of b
i
(i = 1, 2, 3) and V
REF
. Plot the inputoutput characteristic on the curve shown below
and find the largest ±INL and largest ±DNL. Is the DAC monotonic or not?
Digital Word v
OUT
000 0/16
001 3/16
010 5/16
011 8/16
100 7/16
101 10/16
110 12/16
111 15/16
Solution
The output can be written as
v
OUT
= k
1
(b
1
+k
2
(b
2
+k
3
b
3
))V
REF
= [k
1
b
1
+ k
1
k
2
b
2
+ k
1
k
2
k
3
b
3
]V
REF
Using the values given gives
v
OUT
=
]
]
.

}
`
7
16
b
1
+
.

}
`
7
16
.

}
`
5
7
b
2
+
.

}
`
7
16
.

}
`
5
7
.

}
`
3
5
b
3
V
REF
=
]
]
7
16
b
1
+
5
16
b
2
+
3
16
b
3
V
REF
The values for v
OUT
for this DAC are shown beside the plot and have been plotted on the output
input characteristic curve. A summary of the performance is given below.
INL: +1LSB, 0.5LSB DNL: +0.5LSB, 1.5LSB DAC is nonmonotonic
k
3
b
3
Σ
k
2
+1
+1
b
2
Σ
k
1
+1
+1
b
1
+1
V
REF
v
OUT
0/8
1/8
2/8
3/8
4/8
5/8
6/8
7/8
8/8
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0 1
1
1 0
1
1
1
Ideal 3bit DAC
A
n
a
l
o
g
O
u
t
p
u
t
Digital Input
+0.5LSB
DNL
+1LSB INL
Actual 3bit DAC
1.5LSB DNL
0.5LSB INL
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1047
Problem 10.407
A pipeline digitalanalog converter is shown. When b
i
is 1, the switch is connected to V
REF
,
otherwise it is connected to ground. Two of the 0.5 gains on the summing junctions are in error.
Carefully sketch the resulting digitalanalog transfer characteristic on the plot on the next page
and identify the INL with respect to the infinite resolution characteristic shown and DNL. The
INL and DNL should be measured on the analog axis.
z
1
Σ
+1
z
1
Σ
+1
z
1
Σ
+1
z
1
Σ
+

V
REF
b
4
b
3
+
1
2
b
2
+
5
8
b
1
+
3
8
+
1
2
0
v
OUT
Figure S10.47A
Solution
Ignoring the delay terms, we can write the output voltage as,
v
OUT
V
REF
=
.

}
`
.

}
`
.

}
`
b
4
2
+ b
3
5
8
+ b
2
3
8
+ b
1
1
2
=
1
2
b
1
+
3
16
b
2
+
30
256
b
3
+
15
256
b
3
=
128
256
b
1
+
48
256
b
2
+
30
256
b
3
+
15
256
b
3
The performance is summarized in the table below (a plot can be made from the table).
B0 B1 B2 B3 Ideal Actual Ideal DNL Actual DNL Ideal INL Actual INL
0 0 0 0 0.00000 0.00000   0.00000 0.00000
0 0 0 1 0.06250 0.05859 0.00000 0.06250 0.00000 0.06250
0 0 1 0 0.12500 0.11719 0.00000 0.06250 0.00000 0.12500
0 0 1 1 0.18750 0.17578 0.00000 0.06250 0.00000 0.18750
0 1 0 0 0.25000 0.18750 0.00000 0.81250 0.00000 1.00000
0 1 0 1 0.31250 0.24609 0.00000 0.06250 0.00000 1.06250
0 1 1 0 0.37500 0.30469 0.00000 0.06250 0.00000 1.12500
0 1 1 1 0.43750 0.36328 0.00000 0.06250 0.00000 1.18750
1 0 0 0 0.50000 0.50000 0.00000 1.18750 0.00000 0.00000
1 0 0 1 0.56250 0.55859 0.00000 0.06250 0.00000 0.06250
1 0 1 0 0.62500 0.61719 0.00000 0.06250 0.00000 0.12500
1 0 1 1 0.68750 0.67578 0.00000 0.06250 0.00000 0.18750
1 1 0 0 0.75000 0.68750 0.00000 0.81250 0.00000 1.00000
1 1 0 1 0.81250 0.74609 0.00000 0.06250 0.00000 1.06250
1 1 1 0 0.87500 0.80469 0.00000 0.06250 0.00000 1.12500
1 1 1 1 0.93750 0.86328 0.00000 0.06250 0.00000 1.18750
∴ INL = +0 LSBs ,  1.1875 LSBs and DNL = +1.1875 LSBs , 0.8125 LSBs
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1048
Problem 10.408
Show how Eq. (10.42) can be derived from Eq. (10.41). Also show in the block diagram of
Fig. 10.44 how the initial zeroing of the output can be accomplished.
Solution
Eq. (10.41) can be written as
V
out
=
∑
i =1
N
b
i 1
z
i
2
i  1
=
∑
i =1
N
b
i 1
z
i
2
i  1
z
z
=
1
z
∑
i =1
N
b
i  1
2
i 1
z
i  1
=
1
z
∑
i =1
N
b
i  1
2
i 1
z
i  1
=
1
z
∑
i =0
N
b
i
2
i
z
i
=
b
i
z
∑
i =0
N
1
2
i
z
i
where all b
i
have assumed to be identical as stated in the text.
The summation can be recognized as a geometric series (assuming N → ∞) to give
V
out
=
b
i
z
]
]
]
1
1
1
2z
=
b
i
z
1
10.5z
1
The output can initially be zeroed by adding a third switch to ground at the summing junction.
The S/H will sample the 0V and produce V
out
= 0.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1049
Problem 10.409
Assume that the amplifier with a gain of 0.5 in Fig. 10.44 has a gain error of ∆A. What is the
maximum value ∆A can be in Example 10.42 without causing the conversion to be in error?
Solution
Let the amplifier gain be A. Therefore, we can write the output in general as follows.
Bit from LSB to MSB V
out
1 1
0 A1
0
A(A1) + 1 = A
2
– A  1
1
A[A(A1) – 1] + 1 = A
3

A
2
– A + 1
1
A{A[A(A1) – 1] + 1} + 1 = A
4
 A
3

A
2
+ A + 1
The ideal output is V
out
=
19
16
± 0.5LSB LSB =
2V
REF
2
6
=
V
REF
2
5
=
V
REF
32
Assume V
REF
= 1V, therefore
A
4
 A
3

A
2
+ A + 1 ≤
19
16
±
1
32
=
38
32
±
1
32
∴ The ideal output is 1.18750 and must be between 1.15625 and 1.21875.
Below is a plot of the output as a function of A.
0.95
1
1.05
1.1
1.15
1.2
1.25
0 0.2 0.4 0.6 0.8 1
A
V
out
V
REF
FigS10.409
+0.5 LSB Limit
0.5 LSB Limit
A
min
A
max
From this plot, we see that A must lie between 0.205 and 0.590 in order to avoid a ±0.5LSB
error.
∴ 0. 205 ≤ A ≤ 0. 590
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1050
Problem 10.410
Repeat Example 10.42 for the digital word 10101.
Solution
Let the amplifier gain be A. Therefore, we can write the output in general as follows.
Bit from LSB to MSB V
out
1 1
0 A1
1
A(A1) + 1 = A
2
– A + 1
0
A[A(A1) + 1]  1 = A
3

A
2
+ A  1
1
A{A[A(A1) + 1]  1} + 1 = A
4
 A
3
+
A
2
 A + 1
The ideal output is V
out
=
11
16
± 0.5LSB LSB =
2V
REF
2
6
=
V
REF
2
5
=
V
REF
32
Assume V
REF
= 1V, therefore
A
4
 A
3

A
2
+ A + 1 ≤
12
16
±
1
32
=
22
32
±
1
32
∴ The ideal output is 0.6875 and must be between 0.65625 and 0.71875.
Below is a plot of the output as a function of A.
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
0 0.2 0.4 0.6 0.8 1
V
out
V
REF
FigS10.409
+0.5 LSB Limit
0.5 LSB Limit
A
min
A
max
From this plot, we see that A must lie between 0.41 and 0.77 in order to avoid a ±0.5LSB error.
∴ 0. 41 ≤ A ≤ 0. 77
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1051
Problem 10.411
Assume that the iterative algorithmic DAC of Fig. 10.44 is to convert the digital word 11001. If
the gain of the 0.5 amplifier is 0.7, at which bit conversion is an error made?
Σ
Sample
and
hold
+1
+1
1
2
+V
REF
V
REF
v
OUT
b
i
= 1
b
i
= 0
Fig. S10.411
Solution
Conversion
No.
Bit
Converted
Ideal
Result
Max. Ideal Min. Ideal Result for Gain
= 0.7
1 1(LSB) 1 1.5 0.5 1 (OK)
2 0 (1/2) 0.25 0.75 0.30 (OK)
3 0 (5/4) 1.1250 1.375 1.210 (OK)
4 1 (3/8) 0.4375 0.3125 0.1530 (Error)
5 1 (MSB) (19/16) 0.9062 0.8437 
The max. and min. ideal are found by taking the ideal result and adding and substracting half of
the ideal bit for that conversion number.
We note from the table that the error occurs in the 4
th
bit conversion .
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1052
Problem 10.412
An iterative, algorithmic DAC is shown in Fig. P10.412. Assume that the digital word to be
converted is 10011. If V
REF1
=0.9V
REF
and V
REF2
= 0.8V
REF
, at which bit does an error
occur in the conversion of the digital word to an analog output?
+
Σ
Sample
and hold
circuit
A=0.5
+
V
REF1
ith Bit = 1
V
REF2
ith Bit = 0
v
OUT
Solution
Ideally, the output of the ith stage should be,
v
OUT
(i) = 0.5 v
OUT
(i1) ± b
i
V
REF
The ith LSB is given as
V
REF
2
i1
.
In this problem, the output of ith stage is given as,
v
OUT
(i) = 0.5 v
OUT
(i1) + 0.9V
REF
if b
i
= 1
and
v
OUT
(i) = 0.5 v
OUT
(i1)  0.8V
REF
if b
i
= 0
The performance is summarized in the following table where v
OUT
(i) is normalized to V
REF
.
Conversion
No.
0.5 LSB Bit
Converted
v
OUT
(i)
Ideal
Max. Ideal
v
OUT
(i)
Min. Ideal
v
OUT
(i)
Actual
v
OUT
(i)
1 0.5 1 1 1.5 0.5 0.9
2 0.25 1 1.5 1.75 1.25 1.35
3 0.125 0 0.25 0.125 0.375 0.125
4 0.0625 0 1.125 1.0625 1.1875 0.8625
5 0.03125 1 0.4375 0.46875 0.40625 0.4687
5
An error occurs in the 4
th
bit conversion since it lies outside the maximumminimum ideal
v
OUT
(i). Note the 5
th
bit is okay.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1053
Problem 10.501
Plot the transfer characteristic of a 3bit ADC that has the largest possible differential nonlinearity
when the integral nonlinearity is limited to ±1LSB. What is the maximum value of the
differential nonlinearity for this case?)
Solution
A plot is given below showing the upper and lower limits for ±1 LSB INL. The dark line on the
plot shows part of the ADC characteristics that illustrates that the maximum DNL is ±2 LSB.
000
001
010
011
100
101
110
111
1
8
0
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
Analog Input Voltage
D
i
g
i
t
a
l
O
u
t
p
u
t
C
o
d
e
Ideal 3bit Characteristic
Ideal 3bit + 1LSB
Ideal 3bit  1LSB
Fig. S10.501
+2LSB DNL 2LSB DNL
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1054
Problem 10.52
(a.) Find the ±INL and ±DNL for the 3bit ADC shown where the INL and DNL is referenced
to the analog input voltage. (Use the terminology: INLA and DNLA.)
(b.) Find the ±INL and ±DNL for the 3bit ADC shown where the INL and DNL is referenced
to the digital output code. (Use the terminology: INLD and DNLD.)
(c.) Is this ADC monotonic or not?
000
001
010
011
100
101
110
111
1
8
0
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
Analog Input Voltage
D
i
g
i
t
a
l
O
u
t
p
u
t
C
o
d
e
Ideal 3bit Characteristic
Actual 3bit Characteristic
Infinite Resolution Characteristic
0.5 LSB DNLA
1 LSB
DNLA
1 LSB INLD
+1 LSB INLA
2 LSB DNLD
+1 LSB
DNLD
1.5 LSB INLA
+2 LSB INLD
Solutions
(a.) Refer to the characteristics above:
+INLA = 1LSB INLA = 1.5LSB
+DNLA = +0.5LSB DNLA = 1LSB
(b.) Refer to the characteristics above:
+INLD = 2LSB INLD = 1LSB
+DNLD = +1LSB DNLD = 2LSB
(c.) This ADC is not monotonic.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1055
Problem 10.503
Assume that the step response of a sampleandhold circuit is
v
OUT
(t) = V
I
(1  e
tÆBW
)
where V
I
is the magnitude of the input step to the sampleandhold and BW is the bandwidth of
the sampleandhold circuit in radians/sec. and is equal to 2πMradians/sec. Assume a worst case
analysis and find the maximum number of bits this sampleandhold circuit can resolve if the
sampling frequency is 1MHz. (Assume that the sampleandhold circuit has the entire period to
acquire the sample.)
Solution
To avoid an error, the value of v
OUT
(t) should be within ±0.5LSB of V
I
. Since v
OUT
is always
less than V
I
let us state the requirements as
V
I
 v
OUT
(T) ≤
V
REF
2
N+1
∴ V
I
 V
I
(1e
T·BW
) ≤
V
REF
2
N+1
→ V
I
e
T·BW
≤
V
REF
2
N+1
→ 2
N+1
≤
V
I
V
REF
e
T·BW
The worst case value is when V
I
= V
REF
. Thus,
2
N+1
≤ e
2π
= 535.49 → 2
N
≤
535.49
2
= 267.74
∴ N = 8
Problem 10.504
If the aperture jitter of the clock in an ADC is 200ps and the input signal is a 1MHz sinusoid
with a peaktopeak value of V
REF
, what is the number of bits that this ADC can resolve?
Solution
Eq. (10.81) gives ∆t ≤
V
REF
2
N+1
2
2πfV
REF
=
1
2
N+1
πf
= 200ps
2
N
=
1
2·200ps·πMHz
=
10
6
400π
= 756
ln(2
N
) = ln(756) → N =
ln(756)
ln(2)
= 9.63
∴ N = 9bits
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1056
Problem 10.601
What is the conversion time in clock periods if the input to Fig. 10.62 is 0.25 V
REF
? Repeat if
v
in
*
= 0.7V
REF
.
Solution
v
in
* = 0.25V
REF
:
N
out
= N
REF
x0.25 = 0.25N
REF
∴ Clock periods = N
REF
+ 0.25N
REF
= 1.25 N
REF
v
in
* = 0.7V
REF
:
N
out
= N
REF
x0.7 = 0.7N
REF
∴ Clock periods = N
REF
+ 0.7N
REF
= 1.7 N
REF
Problem 10.602
Give a switched capacitor implementation of the positive integrator and the connection of the
input and reference voltage to the integrator via switches 1 and 2 using a twophase clock.
Solution
+

φ
1
φ
1
φ
2
φ
2
KC C
v
in
*
V
REF
Carry Output
(when high, connect to V
REF
)
v
out
FS10.602
From Chapter 9, it can be shown that,
v
out
(t) ≈ K
⌡
⌠v
in
* dt or K
⌡
⌠V
REF
dt
depending on the carrier output.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1057
Problem 10.701
If the sampled, analog input applied to an 8bit successiveapproximation converter is 0.7V
REF
,
find the output digital word.
Solution
Bit Trial Digital Word
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
DV
REF
=
.

}
`
b
0
2
+
b
1
4
+
b
2
8
+
b
3
16
+
b
4
32
+
b
5
64
+
b
6
128
+
b
7
256
V
REF
0.7V
REF
>
DV
REF
?
Decoded
Bit
1 1 0 0 0 0 0 0 0 0.5V
REF
Yes 1
2 1 1 0 0 0 0 0 0 0.75V
REF
No 0
3 1 0 1 0 0 0 0 0 0.625V
REF
Yes 1
4 1 0 1 1 0 0 0 0 0.6875V
REF
Yes 1
5 1 0 1 1 1 0 0 0 0.71875V
REF
No 0
6 1 0 1 1 0 1 0 0 0.703125V
REF
No 0
7 1 0 1 1 0 0 1 0 0.6953125V
REF
Yes 1
8 1 0 1 1 0 0 1 1 0.69921875V
REF
Yes 1
The digital word is 1 0 1 1 0 0 1 1
Problem 10.702
A 4bit, successive approximation ADC
is shown. Assume that V
REF
= 5V. Fill
in the table below when v
in
= 3V.
Clock Period B
1
B
2
B
3
B
4
Guessed
D
1
D
2
D
3
D
4
V
out
Comparator
Output
Actual
D
1
D
2
D
3
D
4
1 1 0 0 0 1 0 0 0 2.5V 1 1 0 0 0
2 0 1 0 0 1 1 0 0 3.75V 0 1 0 0 0
3 0 0 1 0 1 0 1 0 3.125V 0 1 0 0 0
4 0 0 0 1 1 0 0 1 2.8125V 1 1 0 0 1
4bit Shift Register
B
1
B
2
B
3
B
4
D
1
D
2
D
3
D
4
Successive Approximation Register
(If comparator out = 1, keep guess,
if comparator out = 0, change guess.)
4bit DAC
Sample
and hold
V
out
Comparator
Output
V
REF
Clock
In
v
in
F97E2P1
(Each clock causes a 1 to shift right.)
+

CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1058
Problem 10.703
For the successive approximation ADC shown in Fig. 10.77, sketch the voltage across capacitor
C
1
(v
C1
) and C
2
(v
C2
) of Fig. 10.41 if the sampled analog input voltage is 0.6V
REF
. Assume
that S2 and S3 closes in one clock period and S1 closes in the following clock period. Also,
assume that one clock period exists between each successive iteration. What is the digital word
out?
Actual digital word is 1001 .
Solution
v
C1
/V
REF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
0.625
1.000
0.250
0
0.125
0.375
0.825
0.750
0.500
t/T
V
in
*
v
C2
/V
REF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
0.625
1.000
0.250
0
0.125
0.375
0.825
0.750
0.500
t/T
V
in
*
S1 S2 S3 S2 S1 S2 S1 S3 S2 S1 S3 S1 S2 S1
S4 S4
S4
S3 S2 S1 S3 S1 S3 S1 S2 S1 S3
S4
Fig. 10.703
i Guess v
Guess
Actual
0 1 0.5 1
1 11 0.75 1.0
2 101 0.625 100
3 1001 0.5625 1001
+

V
REF
V
REF
+

+

v
C1
v
C2
C1 C2
S2
S3 S1 S4
+

v
in
*
S1
S2
S3
S4
Successive
Approx
imation
Register
plus
control
circuitry
b
0
b
1
b
2
b
3
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1059
Problem 10.704
Assume that the input of Example 10.71 is 0.8V
REF
and find the digital output word to 6 bits.
Solution
b
0
: V
in
(0) = 0.8V
REF
→ b
0
= 1
b
1
: V
in
(1) = 2(0.8V
REF
) – V
REF
= +0.6V
REF
→ b
1
= 1
b
2
: V
in
(2) = 2(0.6V
REF
) – V
REF
= +0.2V
REF
→ b
2
= 1
b
3
: V
in
(3) = 2(0.2V
REF
) – V
REF
= 0.6V
REF
→ b
3
= 0
b
4
: V
in
(4) = 2(0.6V
REF
) + V
REF
= 0.2V
REF
→ b
4
= 0
b
5
: V
in
(5) = 2(0.2V
REF
) + V
REF
= +0.6V
REF
→ b
5
= 1
∴ Digital output word = 1 1 1 0 0 1
Problem 10.705
Assume that the input of Example 10.71 is 0.3215V
REF
and find the digital output word to 8
bits.
Solution
b
0
: V
in
(0) = 0.3215V
REF
→ b
0
= 1
b
1
: V
in
(1) = 2(0.3125V
REF
) – V
REF
= 0.357V
REF
→ b
1
= 0
b
2
: V
in
(2) = 2(0.357V
REF
) + V
REF
= +0.286V
REF
→ b
2
= 1
b
3
: V
in
(3) = 2(0.286V
REF
) – V
REF
= 0.428V
REF
→ b
3
= 0
b
4
: V
in
(4) = 2(0.428V
REF
) + V
REF
= +0.144V
REF
→ b
4
= 1
b
5
: V
in
(5) = 2(0.144V
REF
)  V
REF
= 0.712V
REF
→ b
5
= 0
b
6
: V
in
(6) = 2(0.712V
REF
) + V
REF
= 0.424V
REF
→ b
4
= 0
b
7
: V
in
(7) = 2(0.424V
REF
) + V
REF
= +0.152V
REF
→ b
4
= 1
∴ Digital output word = 1 0 1 0 1 0 0 1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1060
Problem 10.706
Repeat Example 10.71 for 8 bits if the gain of two amplifiers actually have a gain of 2.1.
Solution
v
in
* =
1.50
5.00
V
REF
= 0.3V
REF
b
0
: V
in
(0) = 0.3V
REF
→ b
0
= 1
b
1
: V
in
(1) = 2.1(0.3V
REF
) – V
REF
= 0.37V
REF
→ b
1
= 0
b
2
: V
in
(2) = 2.1(0.37V
REF
) + V
REF
= +0.223V
REF
→ b
2
= 1
b
3
: V
in
(3) = 2.1(+0.223V
REF
)  V
REF
= 0.5317V
REF
→ b
3
= 0
b
4
: V
in
(4) = 2.1(0.5317V
REF
) + V
REF
= 0.0634V
REF
→ b
4
= 0
b
5
: V
in
(5) = 2.1(0.0634V
REF
) + V
REF
= +0.86686V
REF
→ b
5
= 1
b
6
: V
in
(6) = 2.1(+0.86686V
REF
)  V
REF
= +0.820406V
REF
→ b
6
= 1
b
7
: V
in
(7) = 2.1(+0.820406V
REF
)  V
REF
= +0.820406V
REF
→ b
6
= 1
The ideal digital word for Ex. 10.71 is 1 0 1 0 0 1 1 0
We see that the amplifier with a gain of 2.1 causes an error in the 8
th
bit.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1061
Problem 10.707
Assume that V
in
* = 0.7V
REF
is applied to the pipeline algorithmic ADC of Fig. 10.79 with 5
stages. All elements of the converter are ideal except for the multiplier of 2 of the first stage,
given as 2(1+ε). (a.) What is the smallest magnitude of ε that causes an error, assuming that the
comparator offsets, V
OS
, are all zero? (b.) Next, assume that the comparator offsets are all
equal and nonzero. What is the smallest magnitude of the comparator offsets, V
OS
, that causes
an error, assuming that ε is zero?
+ 
Σ z
1
2(1+ε)
±1
V
in
*
V
REF
+ 
Σ
V
i1 2
±1
z
1
+ 
Σ
V
i 2
±1
z
1
+ 
ith stage
MSB LSB
Stage 1 Stage 2 Stage N
z
1
V(1) V(2)
V(i)
+
−
V
OS
+
−
V
OS
+
−
V
OS
+
−
V
OS
Solution
Use the following table to solve this problem.
Stage No. Bit Converted
(MSB→LSB)
V(i)
V(i) with ε(ι)≠0 ε(i)
* V(i) with V
OS
=0
1 1 0.7 0.7  0.7
2 1 0.4
1.4(1+ε)1 = 0.4+1.4ε
0.286 0.4
3 0 0.2
2(0.4+1.4ε)−1 −0.2+2.8ε
0.0714 0.2
4 1 0.6
2(0.2+2.8ε)+1 = 0.6+5.6ε
0.107 0.6
5 1 0.2
2(0.6+5.6ε)−1 0.2+11.2ε
0.0178 0.2
*ε(i) is calculated by setting V(i) with ε ≠ 0 to zero.
From the above table we get the following results:
∴ From the fifth column, we see that the minimum  ε  is 0.0178
(b.) The minimum V
OS
= ±0.2V .
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1062
Problem 10.708
The input to a pipeline algorithmic ADC is 1.5V. If the ADC is ideal and V
REF
= 5V, find the
digital output word up to 8 bits in order of MSB to LSB. If V
REF
= 5.2 and the input is still
1.5V, at what bit does an error occur?
Solution
The iterative relationship of an algorithmic ADC is,
v(i+1) = 2v(i) – b
i
V
REF
where b
i
= 1 if b
i
= “1” and –1 if b
i
= “0”.
Ideal case (V
REF
=5V):
i
v(i) b
i
2v(i) – b
i
V
REF
1 1.5 1 3  5 = 2
2 2 0 4 + 5 = 1
3 1 1 2 – 5 = 3
4 3 0 6 + 5 = 1
5 1 0 2 + 5 = 3
6 3 1 6 – 5 = 1
7 1 1 2 – 5 = 3
8 3 0
Actual case (V
REF
=5.2V):
i
v(i) b
i
2v(i) – b
i
V
REF
1 1.5 1 3 – 5.2 = 2.2
2 2.2 0 4.4 + 5.2 = 0.8
3 0.8 1 1.6 – 5.2 = 3.6
4 3.6 0 7.2 + 5.2 = 2.0
5 2.0 0 4 + 5.2 = 1.2
6 1.2 1 2.4 – 5.2 = 2.8
7 2.8 0 5.6 + 5.2 = 0.6
8 0.6 0
The error occurs at the 7
th
bit.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1063
Problem 10.709
If V
in
*
= 0.1V
REF
, find the digital output of an ideal, 4stage, algorithmic pipeline ADC. Repeat
if the comparators of each stage have a dc voltage offset of 0.1V.
Solution
Ideal:
Stage i V
i1
V
i1
> 0? Bit i
1 0.1 Yes 1
2 0.1x21.0 = 0.8 No 0
3 0.8x2+1.0 = 0.6 No 0
4 0.6x2+1.0 = 0.2 No 0
Offset = 0.1V:
V
i
= 2V
i1
 b
i
V
REF
+ 0.1
Stage i V
i1
V
i1
> 0? Bit i
1 0.1 Yes 1
2 0.1x21.0+0.1 = 0.7 No 0
3 0.7x2+1.0+0.1 = 0.3 No 0
4 0.3x2+1.0+0.1 = +0.5 Yes 1
An error will occur in the 4
th
bit when V
in
*
= 0.1V
REF
and the offset voltage is 0.1V.
Problem 10.710
Continue Example 10.73 out to the 10th bit and find the equivalent analog voltage.
Solution
v
in
* = 0.8V
REF
V
a
(0) = 2(0.8V
REF
) = 1.6V
REF
, 1.6 V
REF
> V
REF
⇒ b
0
= 1
V
a
(1) = 2(1.6V
REF
V
REF
) = 1.2V
REF
, 1.2 V
REF
> V
REF
⇒ b
1
= 1
V
a
(2) = 2(1.2V
REF
V
REF
) = 0.4V
REF
, 0.4 V
REF
< V
REF
⇒ b
2
= 0
V
a
(3) = 2(0.4V
REF
+ 0) = 0.8V
REF
, 0.8 V
REF
< V
REF
⇒ b
3
= 0
(Note the ADC repeats at every 4 bits)
V
a
(4) = 2(0.8V
REF
+ 0) = 1.6V
REF
, 1.6 V
REF
> V
REF
⇒ b
4
= 1
V
a
(5) = 2(1.6V
REF
V
REF
) = 1.2V
REF
, 1.2 V
REF
> V
REF
⇒ b
5
= 1
V
a
(6) = 2(1.2V
REF
V
REF
) = 0.4V
REF
, 0.4 V
REF
< V
REF
⇒ b
6
= 0
V
a
(7) = 2(0.4V
REF
+ 0) = 0.8V
REF
, 0.8 V
REF
< V
REF
⇒ b
7
= 0
Repeats again.
∴ The digital output word is 1 1 0 0 1 1 0 0 1 1 0 0 ……..
The analog equivalent is
V
REF
.

}
`
1
2
+
1
4
+
0
8
+
0
16
+
1
32
+
1
64
+
0
128
+
0
256
+
1
512
+
1
1024
+ · · · ·
= 0.79980469V
REF
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1064
Problem 10.711
Repeat Example 10.73 if the gain of two amplifier actually has a gain of 2.1.
+

S/H
v
b
A
V
REF
V
REF
Σ
+

v
a
> V
REF
⇒ v
c
= V
REF
v
a
< V
REF
⇒ v
c
= 0
v
a
v
in
*
v
c
Solution
(a.) A = 2.0. Assume V
REF
= 1V.
i v
a
(i) v
a
(i) > V
REF
? b
i
v
b
(i)
1 2(0.8)=1.6 Yes 1 0.6
2 2(0.6)=1.2 Yes 1 0.2
3 2(0.2)=0.4 No 0 0.4
4 2(0.4)=0.8 No 0 0.8
5 2(0.8)=1.6 Yes 1 0.6
(b.) A = 2.1. Assume V
REF
= 1V.
i v
a
(i) v
a
(i) > V
REF
? b
i
v
b
(i)
1 2.1(0.8)=1.68 Yes 1 0.68
2 2.1(0.68)=1.428 Yes 1 0.428
3 2.1(0.428)=0.8988 No 0 0.8988
4 2.1(0.8988)=1.88748 Yes 1 0.88748
5 2.1(0.88748)=1.886371 Yes 1 0.886371
An error occurs in the 4
th
bit.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1065
Problem 10.712
An algorithmic ADC is shown below where φ
1
and φ
2
are nonoverlapping clocks. Note that the
conversion begins by connecting v
in
*
to the input of the sample and hold during a φ
2
phase. The
actual conversion begins with the next phase period, φ
1
. The output bit is taken at each
successive φ
2
phase. (a.) What is the 8bit digital output word if v
in
*
= 0.3V
REF
? (b.) What
is the equivalent analog of the digital output word? (c.) What is the largest value of comparator
offset, V
OS
, before an error is caused in part (a.) if V
REF
= 1V?
+

S/H
+

v
in
*
v
C
=1: φ
x
=φ
2
and φ
y
=φ
1
v
C
=0: φ
x
=φ
1
and φ
y
=φ
2
v
C
φ
x
φ
y
V
REF
φ
x
φ
y
C
φ
2
φ
1
2C
C
φ
1
φ
1
φ
2
V
OS
+ 
Bits
Out
φ
2
F97FEP5
Solution
(a.)
Clock Period
Output of S/H
(Normalized to V
REF
)
v
C
> 0? Digital Output
Start 0.3V Yes 
1 (0.3·2)  1 = 0.4V No 0
2 (0.4·2) + 1 = 0.2V Yes 1
3 (0.2·2)  1 = 0.6V No 0
4 (0.6·2) + 1 = 0.2V No 0
5 (0.2·2) + 1 = 0.6V Yes 1
6 (0.6·2) 1 = 0.2V Yes 1
7 (0.2·2)  1 = 0.6V No 0
8 (0.6·2) + 1 = 0.2V No 0
(b.) V
analog
=
.

}
`
1
4
+
1
32
+
1
64
V
REF
= 0.296875V
REF
(c.) In part (a.) the output of the S/H never got smaller than ±0.2V
REF
= ±0.2V.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1066
Problem 10.801
Why are only 2
N
1 comparators required for a Nbit flash A/D converter? Give a logic diagram
for the digital decoding network of Fig. 10.81 which will provide the correct digital output
word.
Solution
(See the solution for Problem 10.22 of the first edition)
Problem 10.802
What are the comparator outputs in order of the upper to lower if V*
in
is 0.6V
REF
for the A/D
converter of Fig. 10.81?
Solution
The comparator outputs in order from the upper to lower of Fig. 10.81 for V*
in
= 0.6V
REF
is
1 1 1 0 0 0 0 .
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1067
Problem 10.803
Figure P10.83 shows a proposed implementation of the conventional 2bit flash analogto
digital converter (digital encoding circuitry not shown) shown on the left with the circuit on the
right. Find the values of C
1
, C
2
, and C
3
in terms of C that will accomplish the function of the
conventional 2bit flash analogtodigital. Compare the performance of the two approaches from
the viewpoints of comparator offset, speed of conversion, and accuracy of conversion assuming
a CMOS integrated circuit implementation.
R
R
R
R
1
2
3
V
IN
*
V
REF
?
V
IN
*
1
2
3
φ
1
φ
1
φ
1
φ
1
φ
2
C
2
C
3
C
1
C
C
C
V
REF
Figure S10.83A
3
4
V
REF
2
4
V
REF
1
4
V
REF
v
1
v
2
v
3
v
1
v
2
v
3
Solution
Operation:
v
oi
V
REF
+

i
C
i
C
φ
1
:
v
oi
V
REF
C
i
C
φ
2
:
V
in
*
+

i
v
i
V
in
*
Fig. S10.803B
v
i
(φ
2
) (V
in
*V
REF
)
.

}
`
C
C+C
i
+
.

}
`
C
i
C+C
i
V
in
* = V
in
*  V
REF
.

}
`
C
C+C
i
For the conventional flash ADC, v
i
= V
in
*
2
N
i
2
N
V
REF
. For N = 2, we get
∴
2
N
i
2
N
=
C
C+C
i
→ C
i
=
.

}
`
i
2
N
i
C For N = 2, we get C
1
= C /3, C
2
= C , and C
3
= 3 C
ADC Comp. Offset Conv. Speed Accuracy Other Aspects
Conv. Flash ADC ≤ ±0.5LSB Fast Poor Equal R’s
Proposed ADC Autozeroed Faster, comp.
is simpler
Better Unequal C’s, No
CMRR problems
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1068
Problem 10.804
Two versions of a 2bit, flash AD converter are shown in Fig. P10.85. Design R
1
, R
2
, and R
3
to make the righthand version be equivalent to the lefthand version of the 2bit flash AD
converter. Compare the performance advantages and disadvantages between the two AD
converters.
R
R
R
R
1
2
3
?
Figure S10.804
3
4
V
REF
2
4
V
REF
1
4
V
REF
E
N
C
O
D
E
R
1
2
3
V
REF
V
REF
E
N
C
O
D
E
R
V
IN
*
V
IN
*
R
1
R
R
2
R
R
3
R
v
1
v
2
v
3
b
0
b
1
b
0
b
1
Conventional Flash ADC Proposed Flash ADC
Solution
For the proposed ADC, the comparators must switch at V
in
* = 0.75V
REF
, 0.5V
REF
and
0.25V
REF
for comparators, 1,2, and 3, respectively.
∴ v
1
=
.

}
`
R
1
R+R
1
V
in
* 
.

}
`
R
R+R
1
V
REF
= 0 → V
in
* =
.

}
`
R
R
1
V
REF
→ R
1
= (4/3)R
v
2
=
.

}
`
R
2
R+R
2
V
in
* 
.

}
`
R
R+R
1
V
REF
= 0 → V
in
* =
.

}
`
R
R
2
V
REF
→ R
2
= 2R
and
v
3
=
.

}
`
R
3
R+R
3
V
in
* 
.

}
`
R
R+R
3
V
REF
= 0 → V
in
* =
.

}
`
R
R
3
V
REF
→ R
3
= 4R
Comparison:
Conventional Flash ADC Proposed Flash ADC
Advantages Less resistor area
Guaranteed monotonic
All resistors are equal
V
in
* does not supply current
Faster V
in
* directly connected
Insensitive to CM effects
Positive input grounded
No high impedance nodes, fast
Disadvantages Sensitive to CM effects
High impedances nodesonly a
disadvantage if V
REF
changes.
More resistor area
Can be nonmonotonic
Resistor spread of 2
N
V
in
* must supply current
More noise because more resistors
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1069
Problem 10.805
Part of a 6bit, flash ADC is shown. The comparators have a dominant pole at 10
3
radians/sec, a
dc gain of 10
4
a slew rate of 3V/µs, and a binary output voltage of 1V and 0V. Assume that the
conversion time is the time required for the comparator to go from its initial state to halfway to is
final state. What is the maximum conversion rate of this ADC if V
REF
= 5V? Assume the
resistor ladder is ideal.
Solution:
The output of the ith comparator can be found by taking the inverse Laplace transform of,
V
out
(s) =
.

}
`
A
o
(s/10
3
) + 1
·
.

}
`
v
in
*V
Ri
s
to get,
v
out
(t) = A
o
(1  e
10
3
t
)(v
in
*  V
Ri
).
The worst case occurs when
v
in
*V
Ri
= 0.5V
LSB
=
V
REF
2
7
=
5
128
∴ 0.5V = 10
4
(1  e
10
3
T
)(5/128) →
64
5·10
4
= 1 e
10
3
T
or, e
10
3
T
= 1 
64
50,000
= 0.99872 → T = 10
3
ln(1.00128) = 2.806µs
∴ Maximum conversion rate =
1
2.806µs
= 0.356x10
6
samples/second
Check the influence of the slew rate on this answer.
SR = 3V/µs →
∆V
∆T
= 3V/µs → ∆V = 3V/µs(2.806µs) = 8.42V > 1V
Therefore, slew rate does not influence the maximum conversion rate.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1070
Problem 10.806
A flash ADC uses op amps as comparators. The power supply to the op amps is +5V and
ground. Assume that the output swing of the op amp is from ground to +5V. The range of the
analog input signal is from 1V to 4V (V
REF
= 3V). The op amps are ideal except that the
output voltage is given as
v
o
= 1000 (v
id
+ V
OS
) + A
cm
v
cm
where v
id
is the differential input voltage to the op amp, A
cm
is the common mode gain of the op
amp, v
cm
is the common mode input voltage to the op amp, and V
OS
is the dc input offset
voltage of the op amp. (a.) If A
cm
= 1V/V and V
OS
= 0V, what is the maximum number of bits
that can be converted by the flash ADC assuming everything else is ideal. Use a worst case
approach. (b.) If A
cm
= 0 and V
OS
= 40mV, what is the maximum number of bits that can be
converted by the flash ADC assuming everything else is ideal. Use a worst case approach.
Solution
(a.) ∆v
o
= 5V = 1000∆v
id
±1v
cm
Choose v
cm
= 4V as the worst case.
∴ ∆v
id
=
5+4
1000
=
9
1000
≤
V
REF
2
N+1
=
3
2
N+1
2
N+1
≤
1000·3
9
→ 2
N
≤
500·3
9
= 167 → N = 7
(b.) ∆v
o
= 5V = 1000∆v
id
±1000·40mV
∆v
id
=
5(±1000·40mV)
1000
= 5mV –(±40mV) = 45mV (worst case)
∴ 45mV ≤
3
2
N+1
→ 2
N
≤
3
45mV
→ 2
N
≤
3000
2·45
= 33.33
∴ N = 5
Problem 10.807
For the interpolating ADC of Fig. 10.83, find the accuracy required for the resistors connected
between V
REF
and ground using a worst case approach. Repeat this analysis for the eight series
interpolating resistors using a worst case approach.
Solution
All of the resistors must have the accuracy of ±0.5LSB. This accuracy is found as
INL = 2
N1
∆R
R
< 0.5
If N = 3, then
2
2
∆R
R
< 0.5 →
∆R
R
<
1
8
= 12.5%
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1071
Problem 10.808
Assume that the input capacitance to the 8 comparators of Fig. 10.86 are equal. Calculate the
relative delays from the output of amplifiers A
1
and A
2
to each of the 8 comparator inputs.
Solution
Solve by finding the equivalent resistance seen from each comparator, R
eq.
(i) This resistance
times the input capacitance, C, to each comparator will be proportional to the delay.
R
eq.
(1) = 0.25R + R3R = 0.25R + 0.75R = R
R
eq.
(2) = 2R2R = R
R
eq.
(3) = 0.25R + R3R = 0.25R + 0.75R = R
R
eq.
(4) = R
Similarly,
R
eq.
(5) = R
R
eq.
(6) = R
R
eq.
(7) = R
R
eq.
(8) = R
Therefore, τ = R
eq.
(i)C are all equal and all delays are equal.
Problem 10.809
What number of comparators are needed for a folding and interpolating ADC that has the number
of coarse bits as n1 = 3 and the number of fine bits as n2 = 4 and uses an interpolation of 4 on
the fine bits? How many comparators would be needed for an equivalent 7bit flash ADC?
Solution
n1 = 3 ⇒ 2
3
1 = 7
n2 = 4 ⇒ 2
4
1 = 15
Therefore, 21 comparators are needed compared with 2
7
1 = 127 for a 7bit flash.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1072
Problem 10.810
Give a schematic for a folder having a singleended output that varies between 1V and 3V, starts
at 1V, ends at 1V and passes through 2V six times.
Solution
See the circuit schematic below.
V
1 V
2
V
6
9V
V
in
+V
REF
V
1
V
2
V
5
V
6
V
out

+
V
out
V
1
V
2
V
3
V
4
V
6 V
5
V
5
V
in
R
R
R
R
0
V
REF
20kΩ 20kΩ
100µA 100µA 100µA 100µA
3V
2V
1V
100µA
Fig.S10.810
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1073
Problem 10.811
A pipeline, ADC is shown in Fig. P10.811. Plot the outputinput characteristic of this ADC
if V
REF1
= 0.75V
REF
, V
REF2
= V
REF
, V
REF3
= 0.75V
REF
, V
REF4
= 1.25V
REF
, and A = 4.
Express the INL and the DNL in terms of a +LSB and a LSB value and determine whether the
converter is monotonic or not. (F93E2P2)
2bit
ADC
V
REF2 V
REF1
Σ
2bit
DAC
+

b
0
b
1
b
2
b
3
A
v
in
(1)
v
in
(2)
v
out
(1)
V
REF4
v
out
(2)
V
REF3
2bit
ADC
2bit
DAC
Solution
Observations:
∴ First stage changes at v
in
(1) = (3/16)V
REF
, (6/16)V
REF
, (9/16)V
REF
and (12/16)V
REF
.
∴ v
out
(1) =
.

}
`
b
0
2
+
b
1
4
V
REF
3.) Second stage changes at v
in
(2) = (3/16)V
REF
, (6/16)V
REF
, (9/16)V
REF
and (12/16)V
REF
.
4.) v
in
(2) = 4[v
in
(1)  v
out
(1)] or v
in
(1) = (1/4) v
in
(2) + v
out
(1)
Value of v
in
(1) where a change
occurs
b
0
b
1
v
out
(1
)
v
in
(2) b
2
b
3
Comments
0 0 0 0 0 0 0 Starting point
(1/4)x(3/16)=0.75/16 0 0 0 3/16 0 1
(1/4)x(6/16)=1.50/16 0 0 0 6/16 1 0
(1/4)x(9/16)=2.25/16 0 0 0 9/16 1 1
3/16 0 1 4/16 4/16 0 0 Stage 1 switches
(1/4)x(3/16)+(4/16)=4.75/16 0 1 4/16 3/16 0 1
(1/4)x(6/16)+(4/16)=5.50/16 0 1 4/16 6/16 1 0
6/16 1 0 8/16 8/16 0 0 Stage 1 switches
(1/4)x(3/16)+(8/16)=8.75/16 1 0 8/16 3/16 0 1
9/16 1 1 12/16 12/16 0 0 Stage 1 switches
(1/4)x(3/16)+(12/16)=12.75/16 1 1 12/16 3/16 0 1
(1/4)x(6/16)+(12/16)=13.50/16 1 1 12/16 6/16 1 0
(1/4)x(9/16)+(12/16)=14.25/16 1 1 12/16 9/16 1 1
Plot is on the next page.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1074
Problem 10.811 Continued
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1 LSB INL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+3 LSB INL
0 LSB DNL
Analog Input Word
D
i
g
i
t
a
l
O
u
t
p
u
t
V
o
l
t
a
g
e
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
16
16
+2.0 LSB DNL
Fig. S10.811A
INL: +3LSB and –1 LSB
DNL: +2LSB and 0LSB
The ADC is monotonic
The ADC has missing codes which are 0111, 1010, and 1011
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1075
Problem 10.812
A pipeline, ADC is shown below. Plot the outputinput characteristic of this ADC if V
REF1
=
V
REF2
= 0.75V
REF
and all else is ideal (V
REF3
= V
REF4
= V
REF
and A = 4). Express the INL
and the DNL in terms of a +LSB and a LSB value and determine whether the converter is
monotonic or not.
2bit
ADC
V
REF2 V
REF1
Σ
2bit
DAC
+

b
1
b
2
b
3
b
4
A
v
in
(1)
v
in
(2)
v
out
(1)
V
REF4
v
out
(2)
V
REF3
2bit
ADC
2bit
DAC
S01FEP1
Solution
The first stage changes when v
in
(1) =
3
16
V
REF
,
6
16
V
REF
,
9
16
V
REF
, and
12
16
V
REF
.
The second stage changes when v
in
(2) =
4
16
V
REF
,
8
16
V
REF
,
12
16
V
REF
, and
16
16
V
REF
.
Therefore,
v
in
(1) b
1
b
2
v
out
(1) v
in
(2) = 4v
in
(1)–4v
out
(1) b
3
b
4
0 0 0 0 0 0 0
1/16 0 0 0 4/16 = 1/4 0 1
2/16 0 0 0 8/16 = 2/4 1 0
3/16 0 1 3/16 12/1612/16 = 0 0 0
4/16 0 1 3/16 16/1612/16 = 4/16 0 1
5/16 0 1 3/16 20/1612/16 = 8/16 1 0
6/16 1 0 6/16 24/1624/16 = 0 0 0
7/16 1 0 6/16 28/1624/16 = 4/16 0 1
8/16 1 0 6/16 32/1624/16= 8/16 1 0
9/16 1 1 9/16 36/1636/16 0 0
10/16 1 1 9/16 40/1636/16 = 4/16 0 1
11/16 1 1 9/16 44/1636/16 = 8/16 1 0
12/16 1 1 9/16 48/1636/16 12/16 1 1
13/16 1 1 9/16 52/1636/16 = 16/16 1 1
14/16 1 1 9/16 56/1636/16 = 20/16 1 1
15/16 1 1 9/16 60/1636/16 = 24/16 1 1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1076
Problem 10.812  Continued
ADC Characteristic Plot:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Analog Input Voltage
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
D
i
g
i
t
a
l
O
u
t
p
u
t
C
o
d
e
Ideal Finite Characteristic
Actual Finite Characteristic
+INL=3LSB
+DNL=1LSB
S01FES1
From the above plot we see that:
+ INL = 3LSB, INL = 0LSB, + DNL = 1LSB and – DNL = 0LSB
(Note that we cannot say that the ADC has –1LSB for –DNL when the ADC saturates.)
The ADC is monotonic.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1077
Problem 10.813
Repeat Problem 11 if (a.) A = 2 and (b.) A = 6 and all other values of the ADC are ideal.
2bit
ADC
V
REF2 V
REF1
Σ
2bit
DAC
+

b
0
b
1
b
2
b
3
A
v
in
(1)
v
in
(2)
v
out
(1)
V
REF4
v
out
(2)
V
REF3
2bit
ADC
2bit
DAC
Solution
(a.) A = 2. Observations:
∴ First stage changes at v
in
(1) = (4/16)V
REF
, (8/16)V
REF
, and (12/16)V
REF
.
∴ v
out
(1) =
.

}
`
b
0
2
+
b
1
4
V
REF
3.) 2nd stage changes at v
in
(2) = (4/16)V
REF
, (8/16)V
REF
, and (12/16)V
REF
.
4.) v
in
(2) = 2[v
in
(1)  v
out
(1)] or v
in
(1) = (1/2) v
in
(2) + v
out
(1)
Value of v
in
(1) where a change
occurs
b
0
b
1
v
out
(1) v
in
(2) b
2
b
3
Comments
0 0 0 0 0 0 0 Starting point
(1/2)x(4/16)=2/16 0 0 0 4/16 0 1
(1/2)x(8/16)=4/16 0 1 4/16 0 0 0 Stage 1 switches
(1/2)x(4/16)+(4/16)=6/16 0 1 4/16 4/16 0 1
(1/2)x(8/16)+(4/16)=8/16 1 0 8/16 0 0 0 Stage 1 switches
(1/2)x(4/16)+(8/16)=10/16 1 0 8/16 4/16 0 1
(1/2)x(8/16)+(8/16)=12/16 1 1 12/16 0 0 0 Stage 1 switches
(1/2)x(4/16)+(12/16)=14/16 1 1 12/16 4/16 0 1
With a gain of 2, the second stage sees v
in
(2) = 2[v
in
(1)  v
out
(1)]. v
in
(2) will never exceed
0.25V
REF
before the first stage output brings v
in
(2) back to zero. As a consequence, b
2
is stuck
at zero. The plot is on the next page. It can seen from the plot that INL =+0LSB and –2LSB ,
DNL = +2LSB and –0LSB. The ADC is monotonic.
(b.) A = 6. v
in
(2) = 6[v
in
(1)  v
out
(1)] or v
in
(1) = (1/6) v
in
(2) + v
out
(1)
Value of v
in
(1) where a change
occurs
b
0
b
1
v
out
(1) v
in
(2) b
2
b
3
Comments
0 0 0 0 0 0 0 Starting point
(1/6)x(4/16)=0.667/16 0 0 0 4/16 0 1
(1/6)x(8/16) = 1.333/16 0 0 0 8/16 1 0
(1/6)x(12/16)=2/16 0 0 0 12/16 1 1
4/16 0 1 4/16 0 0 0 Stage 1 switches
(1/6)x(4/16)+(4/16)=4.667/16 0 1 4/16 4/16 0 1
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1078
Problem 10.813 – Continued
Value of v
in
(1) where a change
occurs
b
0
b
1
v
out
(1) v
in
(2) b
2
b
3
Comments
(1/6)x(8/16)+(4/16)=5.333/16 0 1 4/16 8/16 1 0
(1/6)x(12/16)+(4/16)=6/16 0 1 4/16 12/16 1 1
8/16 1 0 8/16 0 0 0 Stage 1 switches
(1/6)x(4/16)+(8/16)=8.667/16 1 0 8/16 4/16 0 1
(1/6)x(8/16)+(8/16)=9.333/16 1 0 8/16 8/16 1 0
(1/6)x(12/16)+(8/16)=10/16 1 0 8/16 12/16 1 1
12/16 1 1 12/16 0 0 0 Stage 1 switches
(1/6)x(4/16)+(12/16)=12.667/16 1 1 12/16 4/16 0 1
(1/6)x(8/16)+(12/16)=13.333/16 1 1 12/16 8/16 1 0
(1/6)x(12/16)+(12/16)=14/16 1 1 12/16 12/16 1 1
It can seen from the plot below that INL =+1LSB and –0LSB, DNL = ±0LSB. The ADC is
monotonic.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+2 LSB
DNL(A=2)
Analog Input Word
D
i
g
i
t
a
l
O
u
t
p
u
t
V
o
l
t
a
g
e
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
16
16
Fig. S10.813B
2LSB INL(A=2)
+1LSB INL(A=6)
A=6
A=2
A=4
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1079
Problem 10.814
For the pipeline ADC shown, the reference voltage to the DAC of the first stage is V
REF
±
∆V
REF
. If all else is ideal, what is the smallest value of ∆V
REF
that will keep the INLA to
within (a.) ±0.5LSB and (b.) ±1LSB?
2bit
ADC
2bit
DAC
Σ
V
REF
V
REF
±∆V
REF
b
1
b
2
V
in
(1)
V
out
(1)
2bit
ADC
2bit
DAC
V
REF
V
REF
b
3
b
4
V
in
(2)
V
out
(2)
4 4
F98E2P4
Solution
V
out
(1) = Ideal ± Error =
.

}
`
b
1
2
+
b
2
4
V
REF
±
.

}
`
b
1
2
+
b
2
4
∆V
REF
V
out
(2) = V
in
(1)  V
out
(1) = V
in
(1) 
.

}
`
b
1
2
+
b
2
4
V
REF
±
.

}
`
b
1
2
+
b
2
4
∆V
REF
The second stage switches at V
REF
/16, 2V
REF
/16, 3V
REF
/16, and 4V
REF
/16.
Therefore the LSB is V
REF
/16.
(a.) INLA = ±0.5LSB
.

}
`
b
1
2
+
b
2
4
∆V
REF
≤
±V
REF
32
When b
1
and b
2
are both 1 corresponds to the worst case.
∴ ∆V
REF
≤
4
3
±V
REF
32
=
±V
REF
24
(b.) INLA = ±0.5LSB
.

}
`
b
1
2
+
b
2
4
∆V
REF
≤
±V
REF
16
∴ ∆V
REF
≤
4
3
±V
REF
16
=
±V
REF
12
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1080
Problem 10.815
A 4bit ADC consisting of two, 2bit stages (pipes) is shown. Assume that the 2bit
ADC’s and the 2bit DAC function ideally. Also, assume that V
REF
= 1V. The ideal value of the
scaling factor, k, is 4. Find the maximum and minimum value of k that will not cause an error in
the 4bit ADC. Express the tolerance of k in terms of a plus and minus percentage.
2bit
ADC
V
REF
V
REF
Σ
2bit
DAC
+

2bit
ADC
V
REF
b
1
b
2
b
3
b
4
k v
in
(1)
v
in
(2)
v
out
(1)
Solutions
The input to the second ADC is v
in
(2) = k
]
]
v
in
(1) 
.

}
`
b
1
2
+
b
2
4
.
If we designate this voltage as v’
in
(2) when k = 4, then the difference between v
in
(2) and v’
in
(2)
must be less than ±1/8 or the LSB bits will be in error.
Therefore:
v
in
(2)  v’
in
(2) =
¹
¹
¹
¹
k v
i n
(1)  k
.

}
`
b
1
2
+
b
2
4
 4 v
i n
( 1) + 4
.

}
`
b
1
2
+
b
2
4
≤
1
8
If k = 4 + ∆k, then
¹
¹
¹
¹
4 v
in
(1)+∆k v
in
(1)4
.

}
`
b
1
2
+
b
2
4
∆k
.

}
`
b
1
2
+
b
2
4
4 v
in
(1)+4
.

}
`
b
1
2
+
b
2
4
≤
1
8
or
∆k
¹
¹
¹
¹
v
in
(1) 
.

}
`
b
1
2
+
b
2
4
≤
1
8
.
The largest value of
¹
¹
¹
¹
v
in
(1) 
.

}
`
b
1
2
+
b
2
4
is 1/4 for any value of v
in
(1) from 0 to V
REF
.
Therefore,
∆k
4
≤
1
8
⇒ ∆k ≤ 1/2.
Therefore the tolerance of k is
∆k
k
=
±1
2·4
=
± 1
8
⇒ ±12. 5%
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1081
Problem 10.816
The pipeline, analogtodigital converter shown in Fig. P10.816 uses two identical, ideal, two
bit stages to achieve a 4bit analogtodigital converter. Assume that the bits, b
2
and b
3
, have
been mistakenly interchanged inside the secondstage ADC. Plot the outputinput characteristics
of the converter, express the INL and DNL in terms of a +LSB and a LSB, and determine
whether the converter is monotonic or not.
Solution
v
in
(1) b
0
b
1
v
out
(1) v
in
(2) b
2
b
3
0 0 0 0 0 0 0
1/16 0 0 0 1/16 1 0
2/16 0 0 0 2/16 0 1
3/16 0 0 0 3/16 1 1
4/16 0 1 4/16 0 0 0
5/16 0 1 4/16 1/16 1 0
6/16 0 1 4/16 2/16 0 1
7/16 0 1 4/16 3/16 1 1
8/16 1 0 8/16 0 0 0
9/16 1 0 8/16 1/16 1 0
10/16 1 0 8/16 2/16 0 1
11/16 1 0 8/16 3/16 1 1
12/16 1 1 12/16 0 0 0
12/16 1 1 12/16 1/16 1 0
13/16 1 1 12/16 2/16 0 1
14/16 1 1 12/16 3/16 1 1
The plot on the next page shows that the INL = ±1LSB and DNL = +1LSB and –2LSB. The
ADC is not monotonic.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1082
Problem 10.816 – Continued
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1 LSB INL
2LSB DNL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+1 LSB DNL
Analog Input Word
D
i
g
i
t
a
l
O
u
t
p
u
t
V
o
l
t
a
g
e
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
16
16
Fig. S10.816A
+1 LSB INL
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1083
Problem 10.901
A firstorder, deltasigma modulator is shown in Fig. P10.91. Find the magnitude of the output
spectral noise with V
in
(z) = 0 and determine the bandwidth of a 10bit analogtodigital converter
if the sampling frequency, f
s
, is 10 MHz and k = 1. Repeat for k = 0.5.
Solution
k
z1
∆
12
V
out
(z) V
in
(z)
+
+
+

= rms value of
quantization
noise
Figure P10.91
Σ Σ
From the block diagram, we can write,
V
out
(z) =
∆
12
+
k
z1
[V
in
(z)  V
out
(z)]
Solving for V
out
(z) gives,
V
out
(z) =
.

}
`
z1
z1+k
]
]
] ∆
12
+
kV
in
(z)
z1
=
.

}
`
z1
z1+k
∆
12
if V
in
(z) = 0
∴ H(z) =
.

}
`
z1
z1+k
→ H(e
jωT
) =
e
jωT
1
e
jωT
1+k
=
e
jωT/2
 e
jωT/2
e
jωT/2
 e
jωT/2
+ke
jωT/2
H(e
jωT
) =
2j sin(ωT/2)
2j sin(ωT/2) + k[cos(ωT/2)  j cos(ωT/2)]
=
2tan(ωT/2)
(2k)tan(ωT/2)  jk
Find the bandwidth by setting H(e
jωT
)
2
= 0.5.
H(e
jωT
)
2
=
4tan
2
(ωT/2)
(2k)
2
tan
2
(ωT/2) + k
2
= 0.5 → 8 tan
2
(ωT/2) = (2k)
2
tan
2
(ωT/2) + k
2
tan
2
(ωT/2)[8 – (2k)
2
] = k
2
→ ωT/2 = tan
1
]
]
]
k
2
8 – (2k)
2
ω =
2
T
tan
1
]
]
]
k
8  (2k)
2
= 2f
s
tan
1
]
]
]
k
8  (2k)
2
For k = 1,
ω
3dB
= 2f
s
tan
1
]
]
1
4
= 0.927x10
7
rads/ sec → 1.476 MHz
For k = 0.5,
ω
3dB
= 2f
s
tan
1
]
]
]
0.5
8 
9
4
= 0.411x10
7
rads/ sec → 0.654 MHz
Note that the results are independent of the number of bits because H is the noise transfer
function.
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1084
Problem 10.902
The specification for an oversampled analogtodigital converter is 16bits with a bandwidth of
100kHz and a sampling frequency of 10MHz. (a.) What is the minimum number of loops in a
Sodini modulator using a 1bit quantizer (∆=V
REF
/2) that will meet this specification? (b.) If
the Sodini modulator has two loops, what is the minimum number of bits for the quantizer to
meet the specification?
Solution
The general formula for the Lth order Sodini loop is,
n
o
=
∆
12
π
L
2L+1
.

}
`
2f
B
f
s
L+0.5
(a.) ∆(quantizer) = 0.5V
REF
and an LSB =
V
REF
2
16
∴ n
o
= ≤ LSB ⇒
V
REF
2 12
π
L
2L+1
.

}
`
200
10,000
L+0.5
≤
V
REF
2
16
or
2
15
12
π
L
2L+1
.

}
`
1
50
L+0.5
≤ 1 ⇒ L ≥ 3
(b.) ∆(quantizer) =
V
REF
2
b
, where b = no. of bits
∴ n
o
=
V
REF
2
b
π
2
12 5
.

}
`
1
50
2.5
≤
V
REF
2
16
2
b
≥
2
16
π
2
12 5
.

}
`
1
50
2.5
= 4.7237
∴ b = 3
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1085
Problem 10.903
Draw a singleended switched capacitor realization of everything within the dashed box of the
deltasigma modulator. Assume that the output of the 1bit DAC is ±0.5V
REF
. Be sure to show
the phases of the switches (φ
1
and φ
2
).
+

z
1
Σ
+
+
Σ
+

1bit
DAC
Quantizer
y(n)
x(n)
F97FEP6
Solution
Note that the inner loop is equal to
z
1
1z
1
which is a switched capacitor noninverting integrator.
Therefore a possible realization of the dashed box is shown below.
+

+

y(n) = 1: φ
x
=φ
2
and φ
y
=φ
1
y(n) = 0: φ
x
=φ
1
and φ
y
=φ
2
φ
x
φ
y
V
REF
φ
x
φ
y
0.5C
φ
2
φ
1
C
C
φ
1
x(n)
F97FES6
φ
2
y(n)
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1086
Problem 10.904
The modulation noise spectral density of a secondorder, 1bit Σ∆ modulator is given as
N(f) =
4∆
12
2
f
s
sin
2
.

}
` ωτ
4
where ∆ is the signal level out of the 1bit quantizer and f
s
= (1/τ) = the sampling frequency and
is 10MHz. Find the signal bandwidth, f
B
, in Hz if the modulator is to be used in an 18 bit
oversampled ADC. Be sure to state any assumption you use in working this problem.
Solution
The rms noise in the band 0 to f
B
can be found as,
n
o
2
= ⌡
⌠
0
f
B
N(f)
2
df =
16∆
2
12
2
f
s
⌡
1
⌠
0
f
B
sin
4
.

}
` ω
4f
s
df
Assume that
ω
4f
s
=
2πf
4f
s
=
πf
2f
s
<< 1 so that sin
4
.

}
` ω
4f
s
≈
ω
4f
s
∴ n
o
2
=
8
3
∆
2
f
s
⌡
1
⌠
0
f
B
.

}
` 2πf
4f
s
4
df = =
8
3
∆
2
f
s
.

}
`
π
4
16f
s
4
⌡
⌠
0
f
B
f
4
df
=
8
3
∆
2
π
4
16
1
5
.

}
`
f
B
f
s
5
=
8
15
∆
2
π
4
16
.

}
`
f
B
f
s
5
n
o
=
8
15
∆π
2
4
.

}
`
f
B
f
s
5/2
Assume that ∆ ≈ V
REF
. For an 18bit converter, we get
n
o
≤
V
REF
2
18
=
∆
2
18
→
8
15
∆π
2
4
.

}
`
f
B
f
s
5/2
≤
∆
2
18
.

}
`
f
B
f
s
5/2
≤
15
8
4
∆π
2
1
2
18
=
0.555
2
18
= 2.117x10
6
f
B
f
s
≤ 0.005373 → f
B
= 53.74 kHz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1087
Problem 10.905
The noise power in the signal band of zero to f
B
of a Lth order, oversampling ADC is
given as
n
o
=
∆
12
π
L
2L+1
.

}
`
2f
B
f
s
L+0.5
where f
s
is the sampling frequency.
∆ =
V
REF
2
b
and b is the number of bits of the quantizer. Find the minimum oversampling ratio, OSR
(=f
s
/f
B
), for the following cases:
(a.) A 1bit quantizer, thirdorder loop, 16 bit oversampled ADC.
(b.) A 2bit quantizer, thirdorder loop, 16 bit oversampled ADC.
(c.) A 3bit quantizer, secondorder loop, 16 bit oversampled ADC.
Solution
(a.) n
o
=
V
REF
2 12
π
3
7
.

}
`
2f
B
f
s
3.5
≤
V
REF
2
16
→
.

}
`
f
B
f
s
3.5
≤
42
π
3
2
18
= 7.9732x10
7
→
f
B
f
s
≤ 0.0181
∴
f
s
f
B
= OSR ≥ 55. 26
(b.) n
o
=
V
REF
2
2
12
π
3
7
.

}
`
2f
B
f
s
3.5
≤
V
REF
2
16
→
.

}
`
f
B
f
s
3.5
≤
42
π
3
2
17
= 1.5946x10
6
→
f
B
f
s
≤ 0.0221
∴
f
s
f
B
= OSR ≥ 45. 33
(c.) n
o
=
V
REF
2
3
12
π
3
5
.

}
`
2f
B
f
s
2.5
≤
V
REF
2
16
→
.

}
`
f
B
f
s
2.5
≤
30
π
2
2
15
= 1.6936x10
5
→
f
B
f
s
≤ 0.0123
∴
f
s
f
B
= OSR ≥ 81. 00
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1088
Problem 10.906
A secondorder oversampled modulator is shown below. (a.) Find the noise transfer
function, Y(z)/Q(z). (b.) Assume that the quantizer noise spectral density of a 1bit Σ∆
modulator (not necessarily the one shown below) is
N(f) =
2V
REF
12
2
f
s
sin
2
.

}
` ω
2f
s
where f
s
= 10MHz and is the sampling frequency. Find the maximum signal bandwidth, f
B
, in
Hz if the Σ∆ modulator is used in a 16bit oversampled analogtodigital converter.
1z
1
1
Σ
+
+
+ +
+
1z
1
1
+
X(z)
Q(z)
Y(z)
Σ
z
1
1
Σ
S01FES2
z
1
Y(z)
z
1
Y(z)
z
1
Y(z)
1z
1
Solution
(a.) Y(z) = Q(z) + X(z) + z
1
Y(z) +
.

}
`
1
1z
1
]
]
]
z
1
Y(z) 
z
1
Y(z)
1z
1
Y(z) = Q(z) + X(z) + z
1
Y(z) 
z
1
1z
1
Y(z) 
z
1
(1z
1
)
2
Y(z)
Y(z)
]
]
]
1z
1
+
z
1
1z
1
+
z
1
(1z
1
)
2
= Y(z)
]
]
] 12z
1
+ z
2
+ z
1
z
2
+z
1
(1z
1
)
2
= Q(z) + X(z)
∴ Y(z) = (1z
1
)
2
[Q(z) + X(z)] ⇒
Y(z)
Q(z)
= (1z
1
)
2
(b.) n
o
2
= ⌡
⌠
0
f
B
N(f)
2
df =
4V
REF
2
12
2
f
s
⌡
1
⌠
0
f
B
sin
4
.

}
` πf
f
s
df ≈
2V
REF
2
3f
s
⌡
1
⌠
0
f
B
.

}
` πf
f
s
4
df
n
o
2
=
2π
4
V
REF
2
3f
s
5
⌡
⌠
0
f
B
f
4
df =
2π
4
V
REF
2
15f
s
5
f
B
5
=
2π
4
V
REF
2
15
.

}
`
f
B
f
s
5
n
o
=
2
15
V
REF
π
2
.

}
`
f
B
f
s
5
≤
V
REF
2
16
∴
.

}
`
f
B
f
s
5/2
≤
15
2
1
π
2
1
2
16
=
0.2775
2
16
= 4.234x10
6
.

}
`
f
B
f
s
≤ (4.234x10
6
)
2/5
= 0.0072 ⇒ f
B
≤ 70.909kHz
CMOS Analog Circuit Design (2
nd
Ed.) – Homework Solutions Page 1089
Problem 10.907
Find an expression for the output, Y
o
(z), in terms of the input, X(z