Code No: R059210203

Set No. 1

II B.Tech I Semester Regular Examinations, November 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Convert the following to Decimal and then to Binary. (a) 123416 (b) ABCD16 (c) 11228 (d) 17268 (e) 99710 (f) 65410 2. (a) Simplify the following Boolean expressions. i. ii. iii. iv. i. ii. iii. iv. A’C’ + ABC + AC’ to three literals (x’y’ + z)’ + z + xy + wz to three literals A’B(D’ + C’D) + B(A +A’CD) to one literal (A’ + C)(A’ + C’)(A + B + C’D) to four literals [8] B’C’D + (B + C + D)’ + B ’C’D’E AB + (AC)’ + (AB + C) A’B’C’ + A?BC’ + AB’C’ + ABC’ AB + (AC)’ + AB’C [3+3+3+3+2+2] [8]

(b) Obtain the complement of the following Boolean expressions.

3. Apply Branching method to simplify the following function F (A, B, C, D) = M (0, 1, 4, 5, 9, 11, 13, 15, 16, 17, 25, 27, 28, 29, 31)d(20, 21, 22, 30). [16] 4. (a) Realize Full Adder Using two half adders and logic gates. (b) Draw the block diagram of BCD adder using two 4-bit parallel binary adders and logic gates. [4+12] 5. (a) Derive the PLA programming table for the combinational circuit that squares a 3 bit number.

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Code No: R059210203

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(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate the PAL programming table for the circuit. [8+8] Inputs Output x y z A B C D 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 6. (a) Compare synchronous & Asynchronous circuits (b) Design a Mod-6 synchronous counter using J-K flip flops. 7. For the given minimal state - table: (a) Give proper assignment. (b) And design the circuit using D - Flip-flops. Present State qv q1 q2 q3 q4 q5 Next state, out - put q v+1 Z X=0 X=1 X=0 X =1 q2 q1 0 0 q3 q1 0 0 q4 q5 0 0 q4 q1 0 0 q2 q1 1 0 [8+8] [6+10]

8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8] ⋆⋆⋆⋆⋆

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Code No: R059210203

Set No. 2

II B.Tech I Semester Regular Examinations, November 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Perform the following using BCD arithmetic. Verify the result. [2 X 4 = 8] i. 127310 + 958710 ii. 776210 + 383810 (b) Convert the following. i. ii. iii. iv. 97710 = ( )16 65710 = ( )8 75410 = ( )2 100116 = ( )10 [4 X 2 = 8]

2. (a) Convert the following expressions in to sum of products and product of sums [8] i. (AB + C) ( B + C’D) ii. x’ + x(x + y’)(y + z’) (b) Obtain the Dual of the following Boolean expressions. i. ii. iii. iv. (AB’ + AC’)(BC + BC’)(ABC) AB’C + A’BC + ABC (ABC)’(A + B + C)’ A + B’C (A + B + C’) [8]

3. Reduce the following function using six variable K- map F = m(0, 2, 5, 7, 9, 11, 14, 16, 18, 21, 23, 27, 30, 32, 34, 36, 41, 43, 44, 48, 50, 52, 53, 59, 60, 61). [16] 4. (a) Implement the following Boolean function using a 8:1 multiplexer considering ¯ ¯ ¯ ‘C’ as the input and A,B,C as selection lines. f (ABCD) = AB + BD + BC D (b) Draw the Gate level diagram of a Decimal to BCD encoder. 5. Write a brief note on: (a) Architecture of PLDs (b) Capabitation and the limitations of threshold gates. [8+8] [10+6]

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6. (a) Design a clocked sequential circuit for the state diagram shown in figure 6a

Figure 6a (b) Explain about the following: i. Shift counters ii. Gray code counter. [2×3=6]

7. (a) For the given Moore model machine obtain Mealy reduced state - table and hence draw the state diagram 7b. Present Next state Output state Z x=0 x=1 x=2 A0 C0 B1 C2 0 A1 C0 B1 C2 1 A2 C0 B1 C2 2 B0 C1 A0 A1 0 B1 C1 A0 A1 1 B2 C1 A0 A1 2 C0 A2 B2 B0 0 C1 A2 B2 B0 1 C2 A2 B2 B0 2 (b) A clocked sequential circuit with two inputs x and y and a single output Z is defined by the following state ? diagram. Design the circuit using T ? flip-flop. [8+8]

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Code No: R059210203

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Figure 7b 8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8] ⋆⋆⋆⋆⋆

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Code No: R059210203

Set No. 3

II B.Tech I Semester Regular Examinations, November 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Convert the following to Decimal and then to Binary. (a) 231116 (b) A44D16 (c) 74448 (d) 76678 (e) 15810 (f) 72910 [3+3+3+3+2+2]

2. (a) Draw the NAND logic diagram that implements the complement of the following function. [8] F(A,B,C,D) = Σ (0,1,2,3,4,8,9,12) (b) Obtain the complement of the following Boolean expressions. i. AB + A(B + C) + B’(B + D) ii. A + B + A’B’C (c) Obtain the dual of the following Boolean expressions. i. A’B + A’BC’ + A’BCD + A’BC’D’E ii. ABEF + ABE’F’ + A’B’EF [4] [4]

3. Minimize the following function using tabular minimization and verify the same with K-map minimization F= m(0, 1, 6, 7, 8, 9, 13, 14, 15) [8+8] 4. (a) Implement the following multiple output combinational logic using a 4 line to 16 line Decoder. (b) Explain the terms Multiplexing and Demultiplexing. ¯¯ ¯ ¯ ¯¯ ¯¯ ¯ ¯ ¯ ¯ ¯ ¯ Y1 = AB C D + ABCD + ABC D + ABC D + ABC D + ABCD ¯¯ ¯ ¯ ¯¯ ¯ ¯ ¯ Y2 = AB CD + AB C D + AB CD + AB CD ¯ ¯ + ABCD. Y3 = ABCD + ABC D

[10+6]

5. (a) Derive the PLA programming table for the combinational circuit that squares a 3 bit number. 1 of 3

Code No: R059210203

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(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate the PAL programming table for the circuit. [8+8] Inputs Output x y z A B C D 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 6. (a) Compare synchronous & Asynchronous circuits (b) Design a Mod-6 synchronous counter using J-K flip flops. 7. For the minimal state ? table: (a) Give proper Assignment. (b) Design the circuit using D - Flip-Flops. Present State qv A B C D E Next state q v+1 X=0 B,0 C,0 D,0 D,0 B,1 out - put Z X=1 A,0 A,0 E,0 A,0 A,0 [8+8] [6+10]

8. For the ASM chart given 8:

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Code No: R059210203

Set No. 3

Figure 8 (a) Draw the state diagram. (b) Design the control unit using D flip-flops and a decoder. ⋆⋆⋆⋆⋆ [8+8]

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Code No: R059210203

Set No. 4

II B.Tech I Semester Regular Examinations, November 2007 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering, Bio-Medical Engineering, Electronics & Control Engineering, Electronics & Computer Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Convert the following to Decimal and then to Octal. (a) 123416 (b) 12EF16 (c) 101100112 (d) 100011112 (e) 35210 (f) 99910 2. (a) Reduce the following Boolean expressions. i. ii. iii. iv. i. ii. iii. iv. AB’ (C + BD) + A’B’ A’B’C + (A + B + C’)’ + A’B’C’D ABCD + AB(CD)’ + (AB)’CD (A + A’)(AB + ABC’) [8] ABC + A’B + ABC’ (BC’+ A’D)(AB’ + CD’) x’yz + xz xy + x (wz + wz’) [3+3+3+3+2+2] [8]

(b) Obtain the complement of the following Boolean expressions.

3. (a) What are the advantages and disadvantages of the tabular method vis--vis the K-map? [6] (b) Reduce the following function using K-map F = M (1, 4, 5, 6, 7, 8, 9, 14, 15, 22, 23, 24, 25, 28, 29, 30, 31) 4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers. (b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Full adder. [8+8] 5. (a) Given a 32 x 8 Rom chip with an enable input, show the external connection necessary to construct a 128 x 8 Rom with four chips and a decoder. [10]

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(b) Tabulate the PLA programming table for the four Boolean functions listed below A(x,y,z) = ε(1, 2, 4, 6) B(x,y,z) = ε(0, 1, 6, 7) C(x,y,z) = ε(2,6) D(x,y,z) = ε(1, 2, 3, 5, 7). [8+8] 6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter. (b) Compare synchronous & Asynchronous. [10+6]

7. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed. (a) Obtain State - Diagram. (b) Also obtain state - Table. (c) Find equivalence classes using partition method & design the circuit using D - flip-flops. [4+4+8] 8. (a) For the given control state-diagram, draw the equivalent ASM chart. (b) Design the control circuit using multiplexers for the above state diagram 8. [8+8]

Figure 8 ⋆⋆⋆⋆⋆

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