Velagapudi Ramakrishna Siddhartha Engineering College (Autonomous) Department of Electronics and Communication EC363 - VLSI SYSTEM DESIGN LAB
III B Tech Second Semester - EXTERNAL PRACTICAL EXAMINATION Duration: 3 Hrs Maximum Marks: 50 • • • • • • • Answer all the questions. Maximum Marks for each question are mentioned in the braces. For each change of question paper you will be penalized with 5 marks. Think Hardware when coding. Make sure your coding infers your logic diagram (Drawn in design stage)if synthesized in Leonardo spectrum. Deliverables expected are clearly mentioned in your problem statement. Do your Design (Logic Diagram and Truth table) and VHDL Coding on Answer Sheet for the problem statements and show it to the Examiner. You will then be allotted a system to simulate and synthesize your code.
When B=0. Design a 4-bit adder and synthesize the design which should match with the logic diagram drawn in design stage. which counts 3. Synthesize the design optimizing for the area and without area. 5. (10M) (30M)
Problem Statement-4 1. The series should repeat after the last digit and use synchronous active low reset. (30 M) 2. and output Y will follow input A. (10M) 2.Problem Statement-1 1. Output X will be 0. When B=1. 2. Taking clock frequency signal of 1MHz. 12. (30M)
Problem Statement-3 1. Code it in VHDL using structural model? (30M) 2. control input B. and 15. Design a logic circuit with input signal A. Note the results. (10M)
. Design a full adder and Implement using VHDL. (10M)
Problem Statement-2 1. 9. Design 16:1 multiplexer using 4:1 multiplexers and use structural coding in VHDL to realize the components and their functionality (Define 4:1 multiplexer as a component). design a system to achieve a signal whose frequency is 100 KHz with 10% duty cycle. Design a Synchronous counter. Implement in structural model using VHDL. Output X will follow input A. Design a full adder and Implement using VHDL. Design a BCD adder and implement in VHDL model. and outputs X and Y to operate as follows a. and output Y will be 0 b.
(30M) Design three (3) input XOR function using 4:1 multiplexer. . Code it in VHDL using structural model? (30M) 2.Problem Statement-5 1. a logic circuit and an alarm circuit. (10M)
Problem Statement. Design an ALU with atleast any 6 arithmetic and logical operations. (Show the structural design before you are allotted a system). Use structural coding in VHDL to realize the design with 4:1 multiplexer instantiated as component. Synthesize the design and compare the netlist with your logic diagram in the design.7 1.6 1. Both the digital system designed should be opitimized for the delay. money safe and the door in the room. Synthesize the design optimizing it for delay and compare it with the logic diagram you have drawn. Design a Parity Generator for a transmitter. Code it in VHDL. The sensors are placed on a window. (30M) 2. The alarm circuit is activated on intrusion of any of the sensor circuits.
. design a digital system to achieve a signal whose frequency is 10 KHz. Taking clock frequency signal of 1MHz. Design the logic circuit and code it in VHDL? (10M)
Problem Statement . Code it in VHDL and synthesize the design and in the report mention the total number of gates used by your ALU. (10M)
2. An intrusion detection and alarm system consists of three sensors. Design digital clock using structural model and code it in VHDL using behavioral Model. The receiver demands a sequential parity checker which accepts data serially.
Design a Single bit Magnitude Comparator and code it in VHDL in dataflow model. Design and code in VHDL an 8 bit circular shift register using 3-bit counter? (30M) 2. The vending machine displays the cost and the Item number when the corresponding switch is pressed. The price list of the items is given below: Item Number cost (in rupees) 1 5 2 8 3 6 4 9 Design the logic between your Switch in the machine and the Seven Segment Display and code it in dataflow model. (20M)
.Problem Statement.8 1.9 1. Taking clock frequency signal of 1MHz. Design vending machine for VRSEC Canteen with three items capacity. Each item has a switch.10 1. (10M)
Problem Statement. design a digital system to achieve a signal whose frequency is 1 KHz. (10M)
Problem Statement. Design a Decade counter and code it in VHDL. Code it in VHDL using structural model? (30M) 2.
Problem Statement. (30M) 2.12 1.14
. Design and code in structural model a digital clock which has a maximum limit of one hour. (10M)
Problem Statement. (30M) 2. when empty and 9 when full at the last sensor. (10M)
Problem Statement. Assume a fuel tank is designed with the 10 sensors arranged on its wall at regular intervals. Design a demultiplexer and code it in VHDL using dataflow model. Combine the above two in structural to produce a complete system. Design a counter to generate Modulus 4000 and Code it in VHDL.13 1. When the fuel is filled into the tank and the fuel touches each sensor the System you design has to calculate the fuel level and also display the level as 0. Design a full subtractor and code it in VHDL using dataflow model.2. Synthesize the design optimizing for delay. Design a Seven Segment Display and code it in any model. (20M)
Problem Statement. (30M) 2.11 1. The counter has a parallel load capability and can reset to any predefined value using active low Load signal. Design a priority encoder and code it in VHDL using behavioral.
16 1. Taking sensor outputs as inputs to your system design a digital system to give out outputs which are used to turn the green light on when both the tanks are less than one-quarter full (logic high turns the green light ON). Give each system access time of one microsecond). b. As a part of aircraft functional monitoring system. Two identical circuits are working in parallel. A manufacturing plant uses two tanks to store a certain liquid chemical that is required in a manufacturing process.15 1. Design a control circuit to implement this system. (25M)
Problem Statement. There are 8 systems which are trying to use a single resource. A round robin algorithm is to be implemented as arbitration logic to control the access of these systems. Design a selection unit for 6. A green LED display turns on if
.1. (15M) 2. The sensors produces a 5V level when the tanks are more than a one-quarter full. If one of the circuits fails. (15M) 2. In the above circuit design a digital system to make sure at least one of the tanks fall to quarter full level. (30M) 2. As long as both are operating properly. a circuit is required to indicate the status of the landing gears prior to landing. The system should stay active for the access time and LOW at other times. the outputs will be at opposite levels at some time. Design a digital circuit to detect that the failure has occurred in one of the circuits? (10M)
Problem Statement.four bit data paths controlled using 3-bit control word. the sensor puts out a 0V level. Code it in VHDL. Each tank has a sensor that detects when the chemical level drops off to 25% of full. (Round Robin allows an each single system to use the available single resource for a fixed interval of time. Design a 4-bit subtractor using a 4-bit adder? Code 4-bit adder in structural and realize the 4-bit subtractor system using the top component of the 4-bit adder. the outputs are always the same. Synthesize the Design. and output of which turns on the red light (Logic high turns on red light).
5. Design a sequential 4-bit comparator circuit. 1. Design an ALU for bit shifting operations with and without sign extensions. When the landing gear is extended.all the three gears are properly extended when the gear down switch has been activated in preparation for landing. Problem Statement. A red LED display turns ON if any of the gears fail to extend properly prior to landing. (30M) 2. You got an opportunity to travel around the world as part of your work. Code it in VHDL. 4. 3. 2. (30M) 2. Implement a circuit to meet this requirement? (25M)
Problem Statement. Design a normal digital clock and the above circuit should be an added provision to your clock. Design and code in VHDL a parity generator optimized for delay. Remember your digital clock should be a continuous one!!! Synthesize the circuit optimizing it for the delay. Kathmandu (GMT + 05:45) Beijing (GMT + 08:00) Karachi (GMT + 05:00) Brisbane (GMT + 10:00) Singapore (GMT + 08:00)
Remember you are now in India and should finish your design based on Indian timing (GMT + 05:30) and then take off for your trip. Only one output is expected based on the country you’re in. When the landing gear is retracted. its sensor produces a HIGH voltage. Now design a digital clock which should help you when you visit the following places. Synthesize the design and note the components inferred in the netlist.18: 1. its sensor produces a LOW voltage.17
1. From the netlist list the blocks inferred. (10M) (10M)