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Digital Logic Design by Morris Mano 3rd Edition
NUMBER SYSTEM
BeIore starting number system, a short description oI analog & digital systems characteristics are
Worthwhile.
In this lesson, some basic concepts regarding inIormation processing and
representation are clariIied. These include:
1. 'Analog¨ versus 'Digital¨ parameters and systems.
2. Digitization oI '¨ signals.
3. Digital representation oI inIormation.
4. EIIect oI noise on the reliability and choice oI digital system
representation.
Digital versus Analog
· We live in an 'Analog¨ world.
· 'Analog¨ means Continuous
· We use the word 'Analog¨ to express phenomena or parameters that have
smooth gradual change or movement.
· For example, earth`s movement around the sun is continuous or 'Analog¨.
· Temperature is an 'Analog¨ parameter. In making a cup oI tea, the
temperature oI the tea kettle increases gradually or smoothly.
· In an 'Analog¨ system, parameters have a continuous range oI values
iust like a mathematical Iunction which is 'Continuous¨ ; in other words,
the Iunction has no discontinuity points
· The word 'Digital¨, however. means iust the opposite.
· In Digital Systems, parameters have a limited set oI 'Discrete¨ Values
that they can assume.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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Digital Logic Design by Morris Mano 3rd Edition
· In Other words, digital parameters don`t have a 'Continuous¨ range.
· This means that, digital parameters change their values by 'Jumping¨
Irom one allowed value to another.
· As an example, the day oI the month is a parameter that may only assume
one value out oI a set oI limited discrete values ¦1, 2, 3, .., 31}.
· Thus, the day oI the month is a parameter may not assume a value oI 2.5
Ior example, but it rather iumps Irom a value oI 2 to a value oI 3 then to 4
and so on with no intermediate values!!!
To Summarize:
· Analog Systems deal with Continuous Range oI values.
· Digital Systems deal with a Discrete set oI values.
· " Which is easier to design digital systems or analog ones?
· A Digital systems are easier to design since dealing with a limited set oI
values rather than an infinite (or indefinitelv large) continuous range oI
values is signiIicantly simpler.
Digitization/"uantization of Analog Signals
· Since the world around us is analog, and processing oI digital parameters
is much easier, is it is Iairly common to convert analog parameters (or
signals) into a digital Iorm in order to allow Ior eIIicient transmission and
processing oI these parameters (or signals)
· To convert an Analog signal into a digital one, some loss oI accuracy is
inevitable since digital systems can only represent a Iinite discrete set oI
values.
· The process oI conversion is known as Digitization or Quantization.
· Analogtodigitalconverters (ADC) are used to produce a digitized
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Digital Logic Design by Morris Mano 3rd Edition
version oI analog signals.
· Digitaltoanalogconverters (DAC) are used to regenerate analog signals
Irom their digitized Iorm.
· A typical system consists oI an ADC to convert analog signals into digital
ones to be processed by a digital system which produces results in digital
Iorm which is then transIormed back to analog Iorm through a DAC.
· In this course, we will only be studying digital hardware design concepts,
where both the input and output signals are digital signals.
Digitization Example
· As an example, consider digitizing the shown voltage signal assuming that
the digitized version allowed set oI discrete voltages is ¦V1, V2, V3, V4}.
· Analog signal values are mapped to the closest allowed discrete voltage
¦V1, V2, V3, V4} as shown in Figure.
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Digital Logic Design by Morris Mano 3rd Edition
The Resulting Digitized Waveform
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Digital Logic Design by Morris Mano 3rd Edition
nformation Representation
How Do Computers Represent Values (e.g. V1, V2, V3, V4) ?
1. Using Electrical Voltages (Semiconductor Processor, or Memory)
2. Using Magnetism (Hard Disks, Floppies, etc.)
3. Using Optical Means (Laser Disks, e.g. CD`s)
Consider the case where values are represented by voltage signals:
· Each signal represents a digit in some Number Svstem
· II the Decimal Number Svstem is used, each signal should be capable
oI representing one oI 10 possible digits ( 0to9)
· II the Binarv Number Svstem is used, each signal should be capable oI
representing only one oI 2 possible digits ( 0 or 1).
· Digital computers, typically use low power supply voltages to power
internal signals, e.g. 5 volts, 3.3 volts, 2.5 volts, etc.
· The voltage level oI a signal may be anywhere between the 0 voltage
level (Ground) and the power supply voltage level (5 volts, 3.3 volts,
2.5 volts, etc.)
· Thus, Ior a power supply voltage oI 5 volts, internal voltage signals
may have any voltage value between 0 and 5 volts.
· Using a decimal number system would mean that each signal should
be capable oI representing 10 possible digits ( 0to9).
· With 5 volt range signals, the 10 digits oI the decimal system are
represented with each digit having a range oI only 0.5 a volt
· II, however, a binarv number system is used only 2 digits ¦0, 1} need
to be represented by a signal, allowing much higher Voltage range oI
5 volts between the 2 binary digits.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
Digital Logic Design by Morris Mano 3rd Edition
The Noise Factor
· Typically, lots oI noise signals exist in most environments.
· Noise may cause the voltage level oI a signal (which represents some
digit value) to be changed (either higher or lower) which leads to
misinterpretation oI the value this signal represents.
· Good designs should guard against noisy environments to prevent
misinterpretation oI the signal inIormation.
· " Which is more reliable Ior data transmission; binary signals or
decimal signals ?
· A Binary Signals are more reliable.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
Digital Logic Design by Morris Mano 3rd Edition
· " Why?
· A The Larger the gap between voltage levels, the more reliable the
system is. Thus, a signal representing a binary digit will be
transmitted more reliably compared to a signal which represents a
decimal digit.
· For example, with 0.25 volts noise level using a decimal system at 5
volts power supply is totally unreliable
onclusions
· InIormation can be represented either in an analog Iorm or in a digital
Iorm.
· Due to noise, it is more reliable to transmit inIormation in a digital
Iorm rather than an analog one.
· Processing oI digitally represented inIormation is much more reliable,
Ilexible and powerIul.
· Today`s powerIul computers use digital techniques and circuitry.
· Because oI its high reliability and simplicity, the binary representation
oI inIormation is most commonly used.
· The coming lessons in this chapter will discuss how numbers are
represented and manipulated in digital system.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
Digital Logic Design by Morris Mano 3rd Edition
Number Systems
ntroduction & Objectives:
· BeIore the inception oI digital computers, the only number system
that was in common use is the decimal number system ( ¸ ¹·~ » ' ¹=' ' (
which has a total oI 10 digits (0 to 9).
· As discussed in the previous lesson, signals in digital computers may
represent a digit in some number system. It was also Iound that the
binary number system is more reliable to use compared to the more
Iamiliar decimal system
· In this lesson, you will learn:
What is meant by a weighted number system.
Basic Ieatures oI weighted number systems.
Commonly used number systems, e.g. decimal, binary, octal and
hexadecimal.
Important properties oI these systems.
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Digital Logic Design by Morris Mano 3rd Edition
Weighted Number Systems:
· A number D consists oI n digits with each digit has a particular position.
D ÷ dn1 dn2 .. d2 d1 dô
!osition
n1
!osition
2
!osition
1
!osition
0
· Every digit position is associated with a fixed weight.
· II the weight associated with the ith. position is wi, then the value oI D is
given by:
D ÷ dn1 n1 dn2 n2 . d2 2 d1 1 d0 ô
Example of Weighted Number Systems:
· The Decimal number system ( ¸ ¹·~ » ' ¹=' ' ( is a weighted system.
· For Integer decimal numbers, the weight oI the rightmost digit (at position
0) is 1. the weight oI position 1 digit is 10. that oI position 2 digit is 100.
position 3 is 1000. etc.
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Digital Logic Design by Morris Mano 3rd Edition
Thus.
ô ÷ 1. 1 ÷ 10. 2÷100. 3 ÷ 1000. etc
Example Sho how the value oI the decimal number is estimated
First Position Index
Position
Number
Weight
Value
1000
x 1000
2
100
x100
1
10
x10
0
1
x1
First Position
Index (0)
Value 000 00 0
The Radix (Base)
1. For digit position i. most weighted number systems use weights (wi )
that are 54ers 41 s42e c4nstant value called the radix (r) or the
base such that i ri.
2. A number system oI radix r, typically has a set oI r allowed digits
¦0,1, .,(r1)} See the next example
The leItmost digit has the highest weight Most Significant Digit
(MSD) See the next example
4. The rightmost digit has the lowest weight east Significant Digit
(SD) See the next example
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Digital Logic Design by Morris Mano 3rd Edition
Example Decimal Number System
1 Radix (Base) %en
2 Since i ri., then
ô ÷ 100 ÷ 1.
1 ÷ 101 ÷ 10.
2÷ 102 ÷ 100.
3 ÷ 10 ÷ 1000. etc
3. Number of Alloed Digits is Ten ¦0, 1, 2, 3, 4, 5, , , , 9}
Thus:
MSD LSD
÷ x100 x101 x102 x10
÷ x1 x10 x100 x 1000
Position 2 1 0
1000 100 10 1
Weight ÷ 103 ÷ 102 ÷ 101 ÷ 10ô
The Radix Point
onsider a number system of radix r.
A number D oI n integral digits and m fractional digits is
represented as shown
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Digital Logic Design by Morris Mano 3rd Edition
Digits to the leIt oI the radix point (integral digits) have positive
position indices, while digits to the right oI the radix point (Iractional
digits) have negative position indices
Position indices oI digits to the left oI the radix 54int (the
integral part of start with a 0 and are incremented as e move
lefts (dn1dn2.d2d1dô )
Position indices oI digits to the right oI the radix 54int (the fractional
part of are negative starting with 1 and are decremented as e
move rights ( d1d 2.d2)
The weight associated with digit position i is given by i ri
where i is the position index
t= m. m¹1. .. 2. 1. 0. 1. ... n1
The Value oI D is Computed as :
D =
n 1
d i r
i = m
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Digital Logic Design by Morris Mano 3rd Edition
Example
estimated
Show how the value oI the Iollowing decimal number is
D ÷ 2
d1 dô d1 d2 d3
Number 2
Position 1 0 1 2 
101 100 101 102 10
Weight ÷
10
÷
1
÷ ÷ ÷
01 001 0001
2 2
Value x
10
x
1
x x x
01 001 0001
Value 0 2 0 002 000
D ÷ x101 2x100 x101 x102 x10
Notation
et (D)r denotes a number D expressed in a number system oI radix r
Note: n this notation. r will be expressed in decimal
Example:
(29)10 Represents a decimal value oI 29. The radix '10¨ here means ten.
(100)1 is a Hexadecimal number since r '1¨ here means sixteen. This
number is equivalent to a decimal value oI 12.
(100)2 is a Binary number (radix 2, i.e. two) which is equivalent to a
decimal value oI 22 4.
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Digital Logic Design by Morris Mano 3rd Edition
mportant Number Systems
The Decimal System
r 10 (ten #adix is n4t a P4er 41 2
Ten Possible Digits ¦0, 1, 2, 3, 4, 5, , , , 9}
The Binary System
r 2
To Allowed Digits ¦0, 1]
A Binary Digit is reIerred to as Bit
The leItmost bit has the highest weight
(MSB)
The rightmost bit has the lowest weight
Most Significant Bit
east Significant Bit
(SB)
Examples
ind the decimal value of the two Binarv numbers (101)2 and (1.101)2
MSB LSB
( 1 0 1 )2 1x20 ¹ 0x21 ¹ 1x22
1x1 ¹ 0x2 ¹ 1x 4
MSB
( 5 )10
LSB
(1 . 1 0 1 )2 1x20 ¹ 1x21 ¹ 0x22 ¹ 1x23
1 ¹ 0.5 ¹ 0 ¹ 0.125
( 1 . 2 5 )10
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Digital Logic Design by Morris Mano 3rd Edition
Octal System:
r (Eight 23 )
Eight Allowed Digits ¦0, 1, 2, 3, 4, 5, , }
Examples
ind the decimal value of the two Octal numbers (35 ) and (2.4 )
MSD LSD
( 35 ) 5x0 ¹ x1 ¹ 3x2
5x1 ¹ x ¹ 3x4
( 253 )10
MSD LSD
(2.4 ) 2x0 ¹ x1 ¹ 4x2 ¹ x3
(2.949215 )10
exadecimal System:
r 1 (Sixteen 24 )
Sixteen Allowed Digits ¦0to9 and A. B. C. D. E. <
o here. ten,
%irteen,
B Eleven,
E F4urteen &
C %elve,
F Fi1teen.
": Why is the digit Iollowing assigned the character A and not '10¨?
A: What we need is a single digit whose value is ten. but '10¨ is actually
two digits not one.
o Thus, in Hexadecimal system the 2digit number (10)1 actually
represents a value oI sixteen not ten ¦(10)1 ÷ 0x10
1x11÷(1)10]
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Digital Logic Design by Morris Mano 3rd Edition
Examples
ind the decimal value of the two Hexadecimal numbers (9E1)1 and
(3B.C )1
MSD LSD
(9E1)1 1x10 ¹ Ex11 ¹ 9x12
1x1 ¹ 14x1 ¹ 9x25
( 2529 )10
MSD LSD
(3B.C )1 Cx11 ¹ Bx10 ¹ 3x11
12x11 ¹ 11x10 ¹ 3x1
(59.5 )10
mportant Properties
1. The number oI possible digits in any number system with radix r equals
r. (Give examples in decimal. binarv. octal and hexadecimal)
2. The smallest digit is 0 and the largest possible digit has a value (r1)
3. The Largest value that can be expressed in n integral digits is (rn1)
!rove (Hint add 1 to the LSD position of the largest number)
4. The Largest value that can be expressed in m fractional digits is (1r m)
!rove (Hint add 1 to the LSD position of the largest number)
5. The Largest value that can be expressed in n integral digits and m
fractional digits is (rn r m) !rove (Hint add results of properties 3 &4
above)
6. Total number oI values (patterns) representable in n digits is rn
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Digital Logic Design by Morris Mano 3rd Edition
larification (a)
" What is the result oI adding 1 to the largest digit oI some number
system??
A
For the decimal number system, (1)10 ¹ (9)10 (10)10
For the octal number system, (1) ¹ () (10) ()10
For the hex number system, (1)1 ¹ (F)1 (10)1 (1)10
For the binary number system, (1)2 ¹ (1)2 (10)2 (2)10
onclusion Adding 1 to the largest digit in any number system always has
a result oI (10) in that number system.
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Digital Logic Design by Morris Mano 3rd Edition
This is easy to prove since the largest digit in a number system oI
radix r has a value oI (r1). Adding 1 to this value the result is r which
is alwavs equal to (10)r 0x r0 ¹ 1x r1(r)10
larification (b)
" What is the largest value representable in 3integral digits?
A The largest value results when all 3 positions are Iilled with the largest
digit in the number system.

For the decimal system, it is (999)10
For the octal system, it is ()
For the hex system, it is (FFF)1
For the binary system, it is (111)2

larification (c)
" What is the result oI adding 1 to the largest 3digit number?
?
A
For the decimal system, (1)10 ¹ (999)10 (1000)10 (10)10
For the octal system, (1) ¹ () (1000) ()10
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Digital Logic Design by Morris Mano 3rd Edition
For the hex system, (1)1 ¹ (FFF)1 (1000)1 (1)1
For the binary system, (1)2 ¹ (111)2 (1000)2 (2)10
n general. Ior a number system oI radix r. adding 1 to the largest ndigit
number r n
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Digital Logic Design by Morris Mano 3rd Edition
Accordingly. the value oI largest ndigit number r n 1
onclusions
1. In any number system oI radix r, the result oI adding 1 to the largest
ndigit number equals r n.
2. Thus, the value oI the largest ndigit number is equal to (r n 1)
3. Thus, n digits can represent r n diIIerent values (digit combinations)
starting Irom a 0 value up to the largest value oI r n 1.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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Digital Logic Design by Morris Mano 3rd Edition
Appendix A Summary of Number Systems Prop
The Iollowing table summarizes the basic Ieatures oI the Decimal, O
Hexadecimal number systems as well as a number system with a gen
Decimal
10
Octal
Binary
2
ex
m
1
Allowed
Digits
Value oI
an1. a2 a1 a0
a1a2..am
Smallest n
¦09}
an1x10n1 ¹ an2x10n2
¹...¹ a2x102 ¹ a1x101¹
a0 x 100 ¹ a1 x 101 ¹
a2 x102 ¹..¹ amx10m
ai ¦09}
i÷m.... 0, 1, ., n1
000...0
¦0}
an1n1¹.¹
a22¹a11¹a00¹a11¹
a22¹..¹amm
ai ¦0}
000...0
¦01}
an12n1¹.¹
a222¹a121¹a020¹a121¹
a222¹..¹am2m
ai ¦0,1}
000...0
¦09
000.
digit number
Largest n 999..9
digit number 10n 1
Range oI n 0  (10n1)
digit integers
# oI Possible
Combinations
...
n 1
0 (n1)
n
11...1
2n 1
0 (2n1)
2n
FF..
1n
0 (1
1
oI ndigits
Max Value oI
m Fractional
110m 1m 12m 11
Digits
1
Digital Logic Design by Morris Mano 3rd Edition
Appendix B First 1 Binary Numbers & Their Decim
(All P4ssible Binarv C42binati4ns in 4Bit
Decimal Bin Equivelent Decimal Bin Equivele
0
1
2
0000
0001
0010
0011
0100
0101
0110
0111
10
11
12
1
1
1
1000
1001
1010
1011
1100
1101
1110
1111
2
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Digital Logic Design by Morris Mano 3rd Edition
Appendix Decimal Values of the First 10 Po
One Kilo is deIined as 1000.
For example, one Kilogram is 1000 grams. A kilometer is
1000 meters.
In the Binary system, the power oI 2 value closest to 1000 is
210 which equals 1024. This is reIerred to as one Kilo (or in
short 1K) in binary systems.
Thus, one Kilo (or 1K) in Binary systems is not exactly 1000
but rather equals 1024 or 210
Thus, in binary systems 2K 2 x 1024 204, 4K4 x
1024 409, and so on
Similarly, a one Meg (one million) in binary systems is 220
which equals 1,04,5.
1 Kilo ÷ 1K
2K ÷ 20
K ÷ 0
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Digital Logic Design by Morris Mano 3rd Edition
Number Systems Arithmetic
Objectives
In this lesson, we will study basic arithmetic operations in various
number systems with a particular stress on the binary system.
Approach
Arithmetic in the Binary number system (addition, subtraction and
multiplication).
Arithmetic in other number systems
Binary Addition
00÷0
10÷1
01÷1
11÷2
2 is not an alloed
digit in binary
t
1 1 ÷ (10)2
()1ô () 1ô ÷ (ten)1ô
()1ô () 1ô ÷ (10)1ô
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Digital Logic Design by Morris Mano 3rd Edition
Example
Show the result oI adding:
(2)1ô () 1ô
Carrv 1
1st Number 2
2nd Number
Result
Position
eight
Digit 1
Digit 2
i¹1
r(i¹1)
0
w÷ r i
D1
D2
Result
Position
DCarrv
1
DSum
i÷0
eight
Digit 1
w÷ 101 10 w÷ 100 1
Digit 2
Result
1x10
1 2
2x1
Likewise, in case oI the binary system, iI the weight oI the sum bit
is 2i, then the weight oI the carry bit is 2i+1.
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Digital Logic Design by Morris Mano 3rd Edition
Thus, adding 1 ¹ 1 in the binarv system results in a Sum bit oI 0 and
a carry bit oI 1.
The shown table summarizes the Sum and Carrv results Ior binary
addition
Binary Addition Table
arry Sum
Weight
00
01
10
11
Example
21
0
0
0
1
1
20
0
1
1
0
 0x20
 2
arries
5
1
4
1
0
3
1
1
2
1
1
1
1
0
0
1
1
1 0
0
1
0
0
1
1
1
0
1
0
Result of Binary
Addition (SUM)
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Digital Logic Design by Morris Mano 3rd Edition
Binary Subtraction
10÷1
11÷0
00÷0
01÷?
Position
eight
1st Number
2nd Number
Result
Position
eight
1
10
?
1
10
0
1

?
0
1
1st Number
15
2nd Number 
Result
()10 ()10 ÷ ()10 Borro 1
For Binary subtraction
0  1 ÷ 1 Borro 1
In general, the result oI subtracting two digits each oI weight w is
two digits. One is the 'DiIIerence¨ digit and the other is the
'Borrow¨ digit.
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Digital Logic Design by Morris Mano 3rd Edition
The difference digit has the same weight w as the operand digits.
The borro digit is considered negative and has the weight oI the
next iger digit (wr).
Borro Difference
Weight
00
11
10
01
21
0
0
0
1
 1x(21)
20
0
0
1
1
 1x20
 1
" What is 1 1 1 ÷ ?
A The answer is 1 borro 1
Explanation: We perIorm the operation in 2 steps:
11÷0
We then subtract 1 Irom the above result, i.e. 0 1 which is 1
borro 1
" What is 0 1 1 ÷ ?
A The answer is 0 borro 1
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Digital Logic Design by Morris Mano 3rd Edition
Explanation: We perIorm the operation in 2 steps:
0  1÷ 1 borro 1
We then subtract 1 Irom the above result, which yields 0
borro 1
ol #
Subtraction Example
Borros

5
1
4
0
0
3
1
1
2
1
1
1
1
0
0
0
1
0
0
0
0
0
1
1
1
0
1
1

Result of Binary
Subtraction (Difference)
Binary Multiplication (example)
Multiplicand 1 0 1 1
Multiplier
1
1
0
0
1
1
1
x
0 0 0 0
1 0 1 1
1 1 0 1 1 1
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Digital Logic Design by Morris Mano 3rd Edition
Arith With Bases Other Than 10
Example: Base Digit Set÷ ]0. 1. 2. . ]
(2)5 ¹ (3)5 (5)10
(?)5
(10)5
Addition Table
0
0
0
1 2
5 0x50 ¹ 1x51
1
2
1
2
2
3
4
1x50 ¹ 1x51
3
4
4
10
10
11
11
12
13
3x50 ¹ 1x51
Multiplication Table
`
0
0
0
1 2
1x50 ¹ 1x51
1
2
0
0
1
2
4
9 4x50 ¹ 1x51
0
0
3
4
11
13
14
22
31
1 1x50 ¹ 3x51
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Digital Logic Design by Morris Mano 3rd Edition
Number Base onversion
Objectives
Given the representation oI some number (XB) in a number system oI radix
B, this lesson will show how to obtain the representation oI the same
number (X) in another number system oI radix A, i.e. (XA).
onverting Whole (nteger) Numbers
Assuming X to be an Integer,
1. Assume that XB has n digits (bn1.....b2 b1 b0)B ,
where bi is a digit in radix B svstem.
i.e. bi ]0. 1. .. ~B1¨]
2. Assume that XA has m digits (am1.....a2 a1 a0)A
where ai is a digit in radix A svstem.
Knowns
i.e. ai ]0. 1. .. ~A1¨]
÷(bn1...b2 b1 b0)B
B ÷ a21`Am1.. a2`A2 a1`A1 a0`A0
(a21...a2 a1 a0)A
&nknowns
Divisible by A Not Divisible by A
1
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
"0 ÷ "1 Dividing Q0
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Digital Logic Design by Morris Mano 3rd Edition
Where ai ¦0(A1)}
Accordinglv. dividing XB bv A. the remainder will be a0.
In other words, we can write
B ÷ "0Aa0
Where, "0 a21`Am2 . a2`A1 a1`A0
Divisible byAa1
Not Divisible by A
"0 ÷ "1Aa1
"1 ÷ "2Aa2
..........
"m÷"m2Aam2
"m2÷am1 < A (not divisible by A)
÷"m1Aam1
Where "m1 0
This division procedure can be used to convert an integer value Irom
some radix number system to any other radix number system
An important point to remember is the Iirst digit we get using the
division process is a0, then a1, then a2, till am1
2
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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Digital Logic Design by Morris Mano 3rd Edition
In other words, we get the digits oI the integer number starting Irom the
radix point and moving leIts
Example :
onvert () 10 (? )2
Division Step "uotient Remainder
53
2
13
1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
"0 ÷2
"1 ÷1
"2 ÷
" ÷
" ÷1
0
1 ÷ a0
0 ÷ a1
1 ÷ a2
0 ÷ a
1 ÷ a
1 ÷ a
SB
MSB
Stopping Point
Thus ()10÷(110101)2
Since we always divide by the radix, and the quotient is redivided again by
the radix, the solution table may be compacted into 2 columns only as
shown:
Binary Point
51 53
25
12
3
1
0
1
1
0
0
1
1
a0
am
2
13
3
1
0
1
0
1
0
1
1
SB
MSB
3
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Digital Logic Design by Morris Mano 3rd Edition
(1)10÷(110011)2
()10÷(110101)2
Example :
onvert ()10 (? )
Division Step "uotient Remainder
55 ÷ "0 ÷ ÷ a0 SB
94
11
÷
÷
"1 ÷11
"2 ÷1
÷ a1
÷ a2
1 ÷ 0 1 ÷ a MSB
Thus, ()10 ( 1)
The above method can be more compactly coded as Iollows:
11
1
0
1
Example :
Convert (10)10 (? )12
For radix twelve, the allowed digit set is:
¦09, A, B}
4
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Digital Logic Design by Morris Mano 3rd Edition
10 12
133 12 10 A LSB
11 12 1
11 B
MSB
(10)10 ( B1A.)12
onverting Fractions
Assuming X to be a Iraction ( · 1),
1. Assume that XB has n digits
XB (0.b1 b2 b3...bn)B
2. Assume that XA has m digits
XA (0.a1 a2 a3. .am)A
Knowns
Thus, XB (0.b1 b2 b3...bn)B (0.a1 a2 a3. .am)A
&nknowns
XB a1*A1¹a2*A2¹...am*Am
Integer Fraction
XB*A a1 ¹ XB1
5
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Digital Logic Design by Morris Mano 3rd Edition
#epeating.
XB1*A a2 ¹ XB2
........
XBm2*A am1 ¹ XBm1
XBm1*A am
Example :
onvert (01) 10 (? )2
Binary Point
0.31*21.42
0.42*20.924
0.924*21.4
0.4*21.9
0.9*21.392
0.392*20.4
0.4*21.5
(01) 10 ÷ (1011101)2
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Digital Logic Design by Morris Mano 3rd Edition
Example :
onvert (01) 10 (? )
Octal Point
`01 ÷
`0 ÷
`0 ÷ 22
`022 ÷ 21
(01) 10
Example :
÷(02)
onvert (0) 10 (? )12
For radix telve. the alloed digit set is:
]0. A. B]
System Point
12`0 ÷2
12`02 ÷ 0
12`0 0÷
12`0 ÷ 102
÷A
(0) 10
A÷10
(0A )12
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Digital Logic Design by Morris Mano 3rd Edition
MPORTANT NOTE
For a number that has both integral and Iractional parts, conversion is done
separately Ior both parts, and then the result is put together with a system
point in between both parts.
onversion From Bases Other Than 10
Example
(
(
)
)9
(
(
)5
)12
2 Approaches
Perform arith in original base system
(in the above example bases & )
1 onvert to Decimal
2 onvert from Decimal to ne base
(in the above example bases &12)
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Digital Logic Design by Morris Mano 3rd Edition
Binary To Octal onversion
(bn. b b b b2 b1 b0 b1 b2 b b b..)2
(bn. b b b b2 b1 b0 b1 b2 b b b.)2
3
bits
3
bits
3
bits
3
bits
Starting Point
Group of Binary Bits
bi+2 bi+1 bi
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Octal
Equivalent
0
1
2
Example :
onvert (11100101011011011)2 ino Octal
We 1irst 5artiti4n te Binarv nu2ber int4 gr4u5s 41 3 bits
001¸¸110¸¸010¸¸101¸¸101¸¸101¸¸100
1
2
9
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0
1
2
F
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Digital Logic Design by Morris Mano 3rd Edition
001¸¸110¸¸010¸¸101¸¸101¸¸101¸¸100 ÷ (12)
Binary To exadecimal onversion
(bn. b b b b2 b1 b0 b1 b2 b b b..)2
Starting Point
( ? )1
4
bits
4
bits
4
bits
(bn. b b b b2 b1 b0 b1 b2 b b b)2
Group of Binary Bits exadecimal
bi+3 bi+2 bi+1 bi
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
Equivalent
A
B
D
E
1 1 1 1
10
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Digital Logic Design by Morris Mano 3rd Edition
Example :
onvert (11100101011011011)2 into exadecimal
0011¸¸1001¸¸0101¸¸1011¸¸0110
B
÷ (B)1
To onvert Beteen Octal && exadecimal onvert to Binary as an
ntermediate Step
11
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Digital Logic Design by Morris Mano 3rd Edition
Machine Representation of Numbers
Objectives
In this lesson, you will learn how signed numbers (positive or negative)
are represented in digital computers.
You will learn the 2 main methods Ior signed number representation:
a. The signedmagnitude method, and
b. The complement method.
Registers
Digital computers store numbers in special digital electronic devices called
Registers
Registers consist oI a Iixed number n oI storage elements.
Each storage element is capable oI storing one bit oI data (either 0 or 1}.
The register size is the number oI storage bits in this register (n).
Thus, registers are capable oI holding nbit binary numbers
Register size (n) is typically a power oI 2, e.g. , 1, 32, 4, etc.
An nbit register can represent (store) one oI 2n Distinct Jalues.
Numbers stored in registers may be either unsigned or signed numbers. For
example, 1 is an unsigned number but 1 and 1 are signed numbers.
Unsigned Number Representation
MSB LSB
bit n1 bit n2
bit 2 bit 1 bit 0
NBit Register holding an nBit Unsigned Number
A register oI nbits, can store any unsigned number that has nbits or less.
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Digital Logic Design by Morris Mano 3rd Edition
Typically, the rightmost bit oI the register is designated to be the least
signiIicant bit (LSB), while the leftmost bit is designated to be the most
signiIicant bit (MSB).
When representing an integer number , this nbit register can hold values
Irom 0 up to (2n 1).
Example
Show how the value (13)10 (or D in Hexadecimal) is stored in a 4bit register
and in an bit register
MSB LSB MSB LSB
1 1 0 1 0 0 0 0 1 1 0 1
4Bit Register Storing 13 Bit Register Storing 13
Signed Number Representation
The nbits oI the register holding an unsigned number need only represent
the value (magnitude) oI the number. No sign inIormation needs to be
represented in this case.
In the case oI a signed number, the nbits oI the register should represent
both the magnitude oI the number and its sign as well.
Two maior techniques are used to represent signed numbers:
1. Signed Magnitude Representation
2. Complement method
Radix (R`s) Complement (2`s Complement)
Diminished Radix (R1`s) Complement (1`s Complement)
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Digital Logic Design by Morris Mano 3rd Edition
Signed Magnitude Number Representation
MSB LSB
1
Sign
Bit
ive 0
bit n2
¹ive
bit 2
Magnitude
bit 1 bit 0
SignedMagnitude Number Representation
in nBit Register
Independent Representation oI The Sign and The Magnitude
The leItmost bit is used as a Sign Bit.
The Sign Bit :
o 0
o 1
¹ive number
ive number.
The remaining (n1) bits are used to represent the magnitude oI the number.
Thus, the largest representable magnitude. in this method, is (2n11)
Example
Show the signedmagnitude representations oI ¹, , ¹13 and 13 using a 4Bit
register and an Bit register
Solution
For a bit register. the leItmost bit is a sign bit, which leaves 3 bits only to
represent the magnitude.
The largest magnitude representable in 3bits is . Accordingly, we cannot
use a 4bit register to represent ¹13 or 13.
0 1 1 0
1 1 1 0
SignedMagnitude
Representation oI ¹
SignedMagnitude
Representation oI 
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Digital Logic Design by Morris Mano 3rd Edition
For an bit register. the leItmost bit is a sign bit, which leaves bits to
represent the magnitude.
The largest magnitude representable in bits is 12 ( 21).
0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0
SignedMagnitude
Representation oI ¹
SignedMagnitude
Representation oI 
0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1
SignedMagnitude
Representation oI ¹13
Notes
SignedMagnitude
Representation oI 13
1. Signed magnitude method has Two representations Ior 0 ¦¹0 , 0]
nuisance Ior implementation.
2. Signed magnitude method has a symmetric range oI representation ¦(2
n1
1) : (2  1)}
3. Harder to implement addition/subtraction.
a) The sign and magnitude parts have to be processed independentlv.
b) Sign bits of the operands have to be examined to determine the actual
operation (addition or subtraction).
c) Separate circuits are required to perform the addition and subtraction
operations.
4. Multiplication & division are less problematic.
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a
N`)
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Digital Logic Design by Morris Mano 3rd Edition
omplement Representation
Positive numbers (¹N) are represented in exactlv the same way as in signed
magnitude system
Negative numbers (N) are represented by the complement oI N (N`)
Define the Complement N of some number N as.
N` M A where. M ÷ Some Constant
Applying negative sign to a number (N N) is equivalent to
Complementing that number (N
Thus, given the representation oI some number N, the representation oI N
is equivalent to the representation oI the complement N`.
mportant Property:
The Complement oI the Complement oI some number N is the original
number N.
N` ÷MN
( N` )` ÷ M (MN) N
This is a required property to match the negation process since a number
negated twice must yield the original number ¦ (N) N}
Why Use the omplement Method ?
Through the proper choice oI the constant M. the complement operation can be
Iairly simple and quite fast. A simple complement process allows:
i. SimpliIied arithmetic operations since. subtraction can be totally replaced
by addition and complementing.
ii. Lower cost, since no subtractor circuitry will be required and only an
adder is needed.
Complement Arithmetic
Basic Rules
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Digital Logic Design by Morris Mano 3rd Edition
1. Negation is replaced by complementing (  N
2. Subtraction is replaced by addition to the complement.
Thus, (X Y) is replaced by (X ¹ Y' )
hoice of M
The value oI M should be chosen such that:
1. It simpliIies the computation oI the complement oI a number.
2. It results in simpliIied arithmetic operations.
Consider the operation
Z X Y,
where both X and Y are positive numbers
In complement arithmetic, Z is computed by adding X to the
complement oI Y
Z X ¹ Y`
Consider the Iollowing two possible cases:
First case Y > (Negative Result)
The result Z is ive. where
Z ÷ (Y)
Being ive, Z should be represented in the complement form as M(Y)
Using the complement method:
Z
Z
X  Y
X ¹ Y`
÷ (MY)
÷ M  (Y)
Correct Answer in the Complement orm
Thus, in the case oI a negative result. any value oI M may be used.
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Digital Logic Design by Morris Mano 3rd Edition
Second case Y < (Positive Result)
The result Z is ive where.
Z (Y)
Using complement arithmetic we get:
Z Y
Z
Z
X ¹ Y`
÷ (MY)
÷ M (Y)
which is different Irom the expected correct result of (Y)
In this case, a correction step is required Ior the Iinal result.
The choice oI the value oI M aIIects the complexity oI this correction step.
To summarize.
There are two constraints on the choice oI M
1. Simple and Iast complement operation.
2. Elimination or simpliIication oI the correction step.
R`s and (R1)`s Complements
Two complement methods have generally been used.
The two methods diIIer in the choice oI the value oI M.
1. The diminished radix complement method ¦(R1)`s Complement }, and
2. The radix complement method (R`s Complement).
Consider the number . with n integral digits and m Iractional digits,
where
n ntegral Digits 2 ractional Digits
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Digital Logic Design by Morris Mano 3rd Edition
Xn1 Xn2 .... X1 X0 X1 X2 ... Xm
Next, we will show how to compute the (R1)`s and the R`s complements
oI X
The Diminished Radix omplement (R1)`s omplement:
M#1 ÷ r n  r m
where, r n ÷ 1 000.00 . 00.000
(n¹1)th
!osition
n digits m digits
and, r m ÷ 000.00 . 00.001
n !ositions m !ositions
Note that. if X is integer. then m÷0 and r m ÷1.
Thus, r m ÷ 000.00 . 00.001
÷ &nit (one) in Least !osition (ulp)
OR M#1 ÷ r n  ulp
where, ulp ÷ &nit (one) in Least !osition ÷ r m
mportant Notes:
The (R1)`s complement oI X will be denoted by
X
'
r 1
.
(rn  rm) is the largest number representable in n integral digits and m
fractional digits.
X
'
r 1
L X, where L is largest number representable in n integral
digits and m fractional digits
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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'
n
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Digital Logic Design by Morris Mano 3rd Edition
The shown table shows how to compute the (r1)`s complement oI X Ior various
number systems
Number (R1)`s omplement of
System
Decimal
Binary
Octal
omplement
`s
Complement
1`s
Complement
`s
Complement
(`r1)
n m
`9 ÷(10 10 )
÷ .
n m
`1 ÷(2 2 ) 
÷ 11.11111
n m
` ÷(  ) 
÷ ..
nintegral digits
mfractional digits
exadec F`s
n
`F ÷(1 1
m
)
imal Complement
÷ FF.F FF.F
Radix omplement (R`s omplement ):
M# ÷ r n
Note that r n 1ôôô.ôô.ôôô
Notes:
(n¹1)th
!osition
n !ositions
1. The R`s complement oI X will be denoted by
X
'
r
.
2. M# depends only on the number oI integral digits (n), but is independent oI
the number oI Iractional digits (m).
3. X r =
r
n
X
4. X r 1 = (
r
ulp ) X
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Digital Logic Design by Morris Mano 3rd Edition
5. Thus,
r' = r' 1 + ul5 . i.e #s complement #1)s complement ¹
ul5
The shown table summarizes the radix complement computation oI X Ior
various number systems
Number
System
Decimal
Binary
Octal
exa
R`s omplement
10`s Complement
2`s Complement
`s Complement
1`s Complement
omplement
of (`r)
n
`10÷10 
n
`2 ÷2 
n
` ÷ 
n
`1÷1 
decimal
Examples
Find the 9`s and the 10`s complement oI the Iollowing decimal numbers:
a 235
b 295.
Solution:
a X 235 n÷4.
X`9(104 ulp) 235
9999 235 42
X`10104 235 43;
Alternativelv. X`10 X`9 ¹ 0001 43
b X 295. n÷4. m÷3
X`9(104 ulp) 295.
9999.999 295. 104.213
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Digital Logic Design by Morris Mano 3rd Edition
X`10104 295. 104.214;
Alternativelv.
X`10 X`9 ¹ 0000.001 104.214
Example
Find the 1`s and the 2`s complement oI the Iollowing binary numbers:
a 110101010
b 1010011011
c 1010.001
Solution:
a X 110101010 n÷9.
X`1(29 ulp) 110101010
001010101
X`229 110101010
001010110
Alternativelv. X`2 X`1 ¹ ulp
001010110
111111111 110101010
1000000000 110101010
001010101 ¹ 000000001
b X 1010011011 n÷10.
X`1(210 ULP) 101001101
010110010
1111111111 101001101
X`2210 101001101
101001101
010110011
10000000000
Alternativelv. X`2 X`1 ¹ ulp
010110011
010110010¹ 0000000001
c X 1010.001 n÷4. m÷3
X`1(24 ULP) 1010.001
0101.110
X`2 24 1010.001
1111.111 1010.001
10000 1010.001
0101.111
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Digital Logic Design by Morris Mano 3rd Edition
Alternativelv. X`2 X`1 ¹ ulp 0101.110¹ 0000.001
0101.111
mportant Notes:
1. The 1's complement oI a number can be directly obtained by bitwise
complementing oI each bit, i.e. each 1 is replaced by a 0 and each 0 is
replaced by a 1.
Example: X 1 1 0 0 1 0 1 0 0 1
X1' 0 0 1 1 0 1 0 1 1 0
2. The 2's complement oI a number can be visually obtained as Iollows:
Scan the binary number Irom right to leIt.
0's are replaced by 0's till the Iirst 1 is encountered.
The Iirst encountered 1 is replaced by a 1 but Irom this point onwards
each bit is complemented replacing each 1 by a 0 and each 0 by a 1
Example: X 1 1 0 0 1 0 1 0 0
X2' 0 0 1 1 0 1 1 0 0
Example
Find the `s and the `s complement oI the Iollowing octal numbers:
a 0
b 541.3
Solution:
a X 0 n÷4.
X`( 4 ULP) 0
100
X` 4 0
Alternativelv. X` X` ¹ ulp
0
10000 0 1010
100¹ 0001 1010
b X 541.3 n÷3. m÷4
X`(3 ULP) 541.3 . 541.3 23.041
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Digital Logic Design by Morris Mano 3rd Edition
X`3 541.3
Alternativelv. X` X` ¹ ulp
1000 541.3 23.042
23.041¹ 0.001 23.042
Example
Find the F`s and the 1`s complement oI the Iollowing HEX numbers:
a 3FA9
b 9B1.C0
Solution:
a X 3FA9 n÷4.
X`F(1 4 ULP) 3FA9
X`11 4 3FA9
Alternativelv. X`1 X`F ¹ ulp
FFFF 3FA9
10000 3FA9
C05¹ 0001
C05
C05
C05
b X 9B1 C0 n÷3. m÷3
X`F(13 ULP) 9B1 C0 FFF FFF 9B1 C0 4E.3F
X`113 9B1 C0 1000 9B1 C0 4E 390
Alternativelv. X`1 X`F ¹ ulp 4E 3F ¹ 000 001 4E 390
Example
Show how the numbers ¹53 and 53 are represented in bit registers using
signedmagnitude, 1's complement and 2's complement representations.

Signed Magnitude
1's omplement
2's omplement
00110101
00110101
00110101
10110101
11001010
11001011
mportant Notes:
1. In all signed number representation methods, the leItmost bit indicates
the sign oI the number, i.e. it is considered as a sign bit
2. II the sign bit (leItmost) is 1, then the number is negative and iI it is 0
the number is positive.
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Digital Logic Design by Morris Mano 3rd Edition
omparison:
Signed 1's 2's
Magnitude omplement omplement
No of 0`s
Symmetric
argest
ive value
Smallest
ive Value
2
(÷0)
yes
¹(2n11)
 (2n11)
2
(÷0)
yes
¹(2n11)
(2n11)
1
(0)
no
¹(2n11)
 2n1
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Digital Logic Design by Morris Mano 3rd Edition
"uiz:
For the shown 4bit numbers, write the corresponding decimal values in the
indicated representation.
Un
signed
Signed
Magnitude
1's omp
(1`)
2's omp
(2`)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
End of essons Exercises
1. Find the binary representation in signed magnitude, 1's complement, and 2's
complement Ior the Iollowing decimal numbers: ¹13, 13, ¹39, 39, ¹1, 1,
¹3 and 3. For all numbers, show the required representation Ior bit and
bit registers
2. Indicate the decimal value corresponding to all 5bit binary patterns iI the
binary pattern is interpreted as a number in the signed magnitude, 1's
complement, and 2's complement representations.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
2.
3.
4.
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Digital Logic Design by Morris Mano 3rd Edition
omplement Arithmetic
Objectives
In this lesson, you will learn:
How additions and subtractions are perIormed using the complement representation,
What is the OverIlow condition, and
How to perIorm arithmetic shiIts.
Summary of the ast esson
Basic Rules
1. Negation is replaced by complementing (  N N` )
Subtraction is replaced by addition to the complement.
Thus, (X Y) is replaced by (X ¹ Y' )
For some number N. its complement N` is computed as N` M N, where
M r n Ior R`s complement representation, where n is the number oI integral digits oI
the register holding the number.
M (r n ulp) Ior (R1)`s complement representation
The operation Z÷ Y. where both X and Y are positive numbers (computed as Y`)
yields two diIIerent results depending on the relative magnitudes oI X & Y. (Review page
12 of the previous lesson).
a) First case Y > (Negative Result)
The result Z is ive. where
Z ÷ (Y)
Being ive, Z should be represented in the complement form as
Z ÷ M(Y) (1)
Expected
orrect Result
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Digital Logic Design by Morris Mano 3rd Edition
Using the complement method:
Z X ¹ Y`
÷ (MY). ie
omputed
Z ÷ M  (Y) (2)
Result
Correct Answer in the Complement orm
n this case. any value of M gives correct result
Note In this case the result Iits in the ndigits oI the operands. In other words, there is no end
carrv irrespective oI the value oI M.
Second case Y < (Positive Result)
The result Z is ive where.
Z (Y)
Using complement arithmetic we get:
Z X ¹ Y`
÷ (MY)
Z ÷ M (Y)
(3)
omputed Result
which is different Irom the expected correct result of
Z (Y) ()
Expected
orrect Result
In this case, a correction step is required Ior the Iinal result.
The correction step depends on the value oI M.
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Digital Logic Design by Morris Mano 3rd Edition
orrection Step for R`s and (R1)`s omplements
The previous analysis shows that computing Z (Y) using complement arithmetic gives:
The correct complement representation oI the answer iI the result is negative, that is M
 (Y)
Alternativelv. iI the result is positive it gives an answer oI M (Y) which is different
Irom the correct answer of (Y) requiring a correction step.
The correction step depends on the value oI M
For the R`s omplement
Note that M# ÷ r n 1ôôô.ôô.ôôô
(n¹1)th
!osition
n !ositions
Thus, the computed result (M (Y)) is given by
Z ÷ r n (Y)
Since (Y) is positive. the computed Z value ¦r n (Y)] requires (n ¹ 1) integral digits to be
expressed as shown in Figure.
(n¹1)th digit
r n
ndigits holding the value oI (XY)
1 digit n1
digit 2 digit 1 digit 0
(n¹1)digits required to hold computed Z value rn (Y)
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Digital Logic Design by Morris Mano 3rd Edition
In this case, it is clear that Z ÷ r n (Y) consists oI the digit 1 in the (n¹1)th digit position
while the least signiIicant n digits will hold the expected correct result oI (XY).
Since X, Y, and the result Z are stored in registers oI n digits, the correct result (X Y) is simply
obtained by neglecting the 1 in the (n¹1)th digit.
The 1 in the (n¹1)th digit is typically reIerred to as 'end carrv`.
onclusion:
For the R`s complement method;
II the computed result has no end carrv. This result is the correct answer.
ii. In case the computed result has an end carrv. this end carry is DSAC#DED and the
remaining digits represent the correct answer.
For the (R1)`s omplement
M#1 ÷ r n ulp
Thus, the computed result (M (Y)) is given by
Z ÷ (r n ulp) (Y)
For a positive value oI (Y). the computed Z value ¦(r n ulp)¹ (Y)] requires (n ¹ 1)
integral digits Ior its representation.
Again, r n represents a 1 in the (n¹1)th digit position (i.e. an end carry) while the least
signiIicant n digits will hold the value (XYulp).
Since the expected correct answer is (XY), the correct result is obtained by adding a ulp to the
least signiIicant digit position.
" What does the computed result represent in case XY ?
onclusion:
For the (R1)`s complement method;
II the computed result has no end carry. This result is the correct answer.
b. In case the computed result has an end carry, this end carry is added to the least
signiIicant position (i.e., as ulp).
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Digital Logic Design by Morris Mano 3rd Edition
mportant Note:
The previous conclusions are valid irrespective of the signs of X or Y and for both
addition and subtraction operations.
Add/Subtract Procedure
It is desired to compute Z ÷ I Y. where . Y and Z:
(a) are signed numbers represented in one oI the complement representation methods.
(b) have n integral digits including the sign digit.
The procedure Ior computing the value oI Z depends on the used complement representation
method:
R`s omplement Arithmetic
1. II the operation to be perIormed is addition compute Z ÷ Y. otherwise iI it is
subtraction, Z ÷ Y. compute Z ÷ Y` instead.
2. II the result has no end carry, the obtained value is the correct answer.
3. II the result has an end carry, discard it and the value in the remaining digits is the
correct answer.
(R1)`s omplement Arithmetic
1. II the operation to be perIormed is addition compute Z ÷ Y. otherwise iI it is
subtraction, Z ÷ Y. compute Z ÷ Y` instead.
2. II the result has no end carry, the obtained value is the correct answer.
3. II the result has an end carry, this end carry should be added to the least signiIicant digit
(ulp) to obtain the Iinal correct answer.
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Digital Logic Design by Morris Mano 3rd Edition
Examples
RAD OMPEMENT
ompute (MN) and (NM). where M÷(022)10 N÷(0020)10
Both M & N must have the same # of Digits (Pad it ô`s i1 needed.
OMPUTNG (M N)
Regular Subtraction
M 0 2 5 3 2
N  0
0
0
3
9
2
2
5
0
2
omplement Method
Compute (M¹N`)
M 0 2 5 3 2
N`
1
9
0
9
9
2
5
0
2
orrect Result
Discard
End Carry
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Digital Logic Design by Morris Mano 3rd Edition
OMPUTNG (N M)
Regular Subtraction
N 0 0 3 2 5 0
M 

0
0
2
9
5
2
3
2
2
ive sign
omplement Method
Compute (N ¹ M`)
Equivalent Results
The ive Result is
Represented by the
10`s omplement
N 0 0 3 2 5 0
M` 9
9
2
3
0
4
1
No End Carry
This is the 10`s complement representation oI
a ive number, i.e. the result (9301)
represents the number (0922)
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Example : (2`s omp) M÷(01010100)2 N÷(01000100)2
Note: Both M & N are positive bit numbers
OMPUTNG (M N)
Regular Subtraction
M 0 1 0 1 0 1 0 0
N  0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
omplement Method
ompute (MN`)
orrect Result
M
N`
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
0
1
1
0
0
0
0
0
0
0
Sign Bit
Discard
Carry Out
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Digital Logic Design by Morris Mano 3rd Edition
OMPUTNG (N M)
Regular Subtraction
N 0 1 0 0 0 1 0 0
M 

0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
ive sign
Equivalent Results
omplement Method
Compute (N ¹ M`)
The ive Result is
Represented by the
2`s omplement
N 0 1 0 0 0 1 0 0
M` 1
1
0
1
1
1
0
1
1
0
1
0
0
0
0
0
Sign Bit
No End Carry
This is the 2`s complement representation oI a
ive number, i.e. the result (11110000)
represents the number (00010000)
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Digital Logic Design by Morris Mano 3rd Edition
DMNSED / (R1)`s RAD OMPEMENT
ompute (MN) and (NM). where M÷(022)10 N÷(0020)10
Both M & N must have the same # of Digits (Pad it ô`s i1 needed.
OMPUTNG (M N)
Regular Subtraction
M 0 2 5 3 2
N  0
0
0
3
9
2
2
5
0
2
omplement Method
Compute (M¹N`)
M 0 2 5 3 2
orrect Result
N`
1
9
0
9
9
2
4
9
1
End Carry
1
0 9 2 2
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Digital Logic Design by Morris Mano 3rd Edition
OMPUTNG (N M)
Regular Subtraction
N 0 0 3 2 5 0
M 

0
0
2
9
5
2
3
2
2
ive sign
omplement Method
Compute (N ¹ M`)
Equivalent Results
The ive Result is
Represented by the
N 0 0 3 2 5 0
`s omplement
M` 9
9
2
3
0
4
1
No End Carry
This is the 9`s complement representation oI a
ive number, i.e. the result (9301)
represents the number (0922)
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Digital Logic Design by Morris Mano 3rd Edition
Example : (1`s omp) M÷(01010100)2 N÷(01000100)2
Note: Both M & N are positive bit numbers
OMPUTNG (M N)
Regular Subtraction
M 0 1 0 1 0 1 0 0
N  0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
omplement Method
Compute (M¹N`)
Sign Bit
orrect Result
M 0 1 0 1 0 1 0 0
End Carry
N`
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
1
0 0 0 1 0 0 0 0
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Digital Logic Design by Morris Mano 3rd Edition
OMPUTNG (N M)
Regular Subtraction
N 0 1 0 0 0 1 0 0
M 

0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
ive sign
Equivalent Results
omplement Method
Compute (N ¹ M`)
The ive Result is
Represented by the
1`s omplement
N 0 1 0 0 0 1 0 0
M` 1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
1
Sign Bit
No End Carry
This is the 1`s complement representation oI a
ive number, i.e. the result (11101111)
represents the number (00010000)
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Digital Logic Design by Morris Mano 3rd Edition
Overflo ondition
II adding two ndigit unsigned numbers results in an n¹1 digit sum, this represents an
overflow condition.
In digital computers, overIlow represents a problem since register sizes are Iixed,
accordingly a result oI n¹1 bits cannot Iit into an nbit register and the most signiIicant bit
will be lost.
OverIlow condition is a problem whether the added numbers are signed or unsigned.
In case oI signed numbers, overIlow may occur only iI the two numbers being added have
the same sign, i.e. either both numbers are positive or both are negative.
For 2`s complement represented numbers, the sign bit is treated as part of the number and
an end carrv does not necessarilv indicate an overflow.
In 2`s complement system, an overIlow condition always changes the sign oI the result and
gives an erroneous nbit answer. Two cases are possible:
1. Both operands are positive (sign bits0). In this case, an overIlow will result Irom a carry
oI 1 into the sign bit column; causing the sum to be interpreted as a negative number.
2. Both operands are negative (sign bits1). In this case, an overIlow will result when no
carry is received at the sign bit column causing the two sign bits to be added resulting in a
0 in the sign bit column and a carry out in the (n¹1)th. bit position which will be
discarded. This causes the sum to be interpreted as a positive number.
Accordingly, an overIlow condition is detected iI one oI the two Iollowing conditions
occurs:
(a) There is a carry into the sign bit column but no carry out oI that column.
(b) There is a carry out oI the sign bit column but no carry into that column.
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Digital Logic Design by Morris Mano 3rd Edition
Example:
Consider the case oI adding the binary values corresponding to (¹5)10 and (¹) 10 where the
correct result should be (¹11).
Even though the operands (¹5)10 & (¹)10 can be represented in 4bits, the result (¹11)10
cannot be represented in 4bits.
Accordingly, the 4bit result will be erroneous due to 'overIlow¨.
Add (¹5) to (¹) using 4bit registers and 2`s complement representation.
(¹5)10
(¹)10
(0101)2
(0110)2
1
0
0
1
1
1
0
0
1
1
1
0
1
There is a carrv int4 the
sign bit column but no
carrv 4ut of it
Sign Bit
II this overIlow condition is not detected, the resulting sum would be erroneously
interpreted as a negative number (1011) which equals (5)10.
Example:
Add (5) to () using 4bit registers and 2`s complement representation.
(5)10
()10
(1011)2
(1010)2
1
1
1
0
0
0
1
1
1
0
1
0
1
There is a carry out oI
the sign bit column but
no carry into it.
Sign Bit
II this overIlow condition is not detected, the resulting sum would be erroneously
interpreted as a positive number (0101) which equals (¹5)10.
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Digital Logic Design by Morris Mano 3rd Edition
Example:
Using bit registers, show the binarv number representation oI the decimal numbers (3), (3),
(54), and (54) using the Iollowing systems:
Signed magnitude
system
Signed 1`s complement
System
Signed 2`s complement
system


00100101
10100101
00110110
10110110
00100101
11011010
00110110
11001001
00100101
11011011
00110110
11001010
Compute the result oI the Iollowing operations in
the signed 2's c425le2ent system.
() ()
Subtraction is turned into addition to the complement, i.e.
() () () ()`
0 0 1 0 0 1 0 1
¹
1 1 0 0 1 0 1 0
1 1 1 0 1 1 1 1
(1)10
() ()
Subtraction is turned into addition to the complement, i.e.
() () () ()`
1 1 0 1 1 0 1 1
¹
1 1 0 0 1 0 1 0
1 1 0 1 0 0 1 0 1
Discard End
Carry
(01011011)  (91)10
III.
¹
(54) ¹ (3)
0 0 1 1 0 1 1 0
1 1 0 1 1 0 1 1
1 0 0 0 1 0 0 0 1
Discard End
Carry
¹ (1)10
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Digital Logic Design by Morris Mano 3rd Edition
Range Extension of 2`s omplement Numbers
To extend the representation oI some 2`s complement number X Irom nbits to n`bits
where n` ~ n.
1. II is ¹ive
integral part.
2. II is ive
pad with 0`s to the right oI Iractional part and/or to the left oI the
pad with 0`s to the right oI Iractional part and/or with 1`s to the left oI
the integral part.
n Ceneral
Pad with 0`s to the right oI Iractional part and/or extend sign bit to the le1t of the integral
part (Sign Bit Extension).
xn1 xn2 .. x2 x1 x0 x1 x2 .. xm
 Before Extending its Range
Sign Bit
xn1 . xn1 xn1 xn1 xn2 . x2 x1 x0 x1 x2 . xm
0 0 . 0
Sign Extension Pad with 0's
 After Extending its Range
(0`s !added to the #ight of ractional !art and the Sign is Extended to the Left of the
ntegral !art)
Example:
Show how the numbers (¹5)10 and (5)10 are represented in 2`s complemenr using 4bit registers
then extend this representation to bit registers.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
(a)
(b)
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Digital Logic Design by Morris Mano 3rd Edition
Sign Bit
Sign bit extension
0 1 0 1
Extend
To bits
0 0 0 0 0 1 0 1
Sign Bit
()10
Sign bit extension
()10
1 0 1 1
Extend
To bits
1 1 1 1 1 0 1 1
()10
Arithmetic Shifts
Effect of 1Digit Shift
()10
LeIt ShiIt
Right ShiIt
Multiplv by radix r
Divide by radix r
Shifting Unsigned Numbers
ShiItin 0`s (Ior both LeIt & Right ShiIts)
Shifting 2`s omplement Numbers
LeIt ShiIts: 0`s are shiItedin
Right ShiIts: Sign Bit Extended
Example:
ShiIt Right
ShiIt Right
¹1
¹2
¹4
¹
000001
000010
000100
001000
1
2
4

111111
111110
111100
111000
¹1 010000 1 110000
ShiIt LeIt
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Digital Logic Design by Morris Mano 3rd Edition
Binary odes
Objectives
In this lesson, you will study:
1. Several binary codes including
Binary Coded Decimal (BCD),
Error detection codes,
Character codes
2. Coding versus binary conversion.
Binary odes for Decimal Digits
Internally, digital computers operate on binary numbers.
When interIacing to humans, digital processors, e.g. pocket calculators, communication is
decimalbased.
Input is done in decimal then converted to binary Ior internal processing.
For output, the result has to be converted Irom its internal binary representation to a decimal
Iorm.
To be handled by digital processors, the decimal input (output) must be coded in binary in a
digit by digit manner.
For example, to input the decimal number . each digit oI the number is individually
coded and the number is stored as 1001¸0101¸0111
Thus, we need a speciIic code Ior each oI the 10 decimal digits. There is a variety oI such
decimal binary codes.
The shown table gives several common such codes.
One commonly used code is the Binarv Coded Decimal (BCD) code which corresponds to
the Iirst 10 binary representations oI the decimal digits 09.
The BCD code requires 4 bits to represent the 10 decimal digits.
Since 4 bits may have up to 1 diIIerent binary combinations, a total oI combinations will
be unused.
The position weights oI the BCD code are , 4, 2, 1.
Other codes (shown in the table) use position weights oI , 4, 2, 1 and 2, 4, 2, 1.
An example oI a nonweighted code is the excess3 code where digit codes is obtained Irom
their binary equivalent aIter adding 3. Thus the code oI a decimal 0 is 0011, that oI is
1001, etc.
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1
Digit
0 0 0
1 1 1
2 1 0
0 1
0 0
1 1
1 0
0 1
0 0
1 1
0 1
1 0
1 1
S 0 0
0 1
1 0
Digital Logic Design by Morris Mano 3rd Edition
Decimal BD
2 1 2 1 2 2 1 Excess
0 0 0 0 0 0
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 1 1
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
1 1 0 1 1 0 1 0
1 1 1 0 1 0 1 1
1 1 1 1 1 1 0 0
U
N
U
E
D
1 0 1 0 0 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
0 1 0 1 0 0 0 0
0 1 1 0 0 0 0 1
0 1 1 1 0 0 1 0
1 0 0 0 1 1 0 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 1 1
Number onversion versus oding
Converting a decimal number into binary is done by repeated division (multiplication) by 2
Ior integers (Iractions) (see lesson 4).
Coding a decimal number into its BCD code is done by replacing each decimal digit oI the
number by its equivalent 4 bit BCD code.
Example Converting (1)10 into binary, we get 1101. coding the same number into BCD, we
obtain 00010011
Exercise: Convert ()10 into its binary
equivalent value and give its BCD code as
well.
Anser ¦(1011111)2, and 10010101]
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Digital Logic Design by Morris Mano 3rd Edition
ErrorDetection odes
Binary inIormation may be transmitted through some communication medium, e.g. using
wires or wireless media.
A corrupted bit will have its value changed
Irom 0 to 1 or vice versa.
To be able to detect errors at the receiver end, the sender sends an extra bit (parity bit) with
the original binary message.
Binary
Message
SENDER Reciever
Error
Detecting Bit
(!aritv Bit)
A paritv bit is an extra bit included with the nbit binarv message to make the total number
oI 1`s in this message (including the paritv bit) either odd or even.
II the paritv bit makes the total number oI 1`s an odd (even) number, it is called odd (even)
parity.
The table shows the required odd (even) 5aritv Ior a 3bit message.
ThreeBit Message Odd Parity Bit Even Parity Bit
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
P
1
0
0
1
0
1
1
0
P
0
1
1
0
1
0
0
1
At the receiver end, an error is detected iI the message does not match have the proper
parity (odd/even).
Parity bits can detect the occurrence 1, 3, 5 or any odd number oI errors in the transmitted
message.
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1
1
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Digital Logic Design by Morris Mano 3rd Edition
No error is detectable iI the transmitted message has 2 bits in error since the total number oI
1`s will remain even (or odd) as in the original message.
In general, a transmitted message with even number oI errors cannot be detected by the
parity bit.
ErrorDetection odes
Binary inIormation may be transmitted through some communication medium, e.g. using
wires or wireless media.
Noise in the transmission medium may cause the transmitted binary message to be
corrupted by changing a bit Irom 0 to 1 or vice versa.
To be able to detect errors at the receiver end, the sender sends an extra bit (parity bit).
Gray ode
The Gray code consist oI 1 4bit code words to represent the decimal Numbers 0 to 15.
For Gray code, successive code words diIIer by only one bit Irom one to the next as shown
in the table and Iurther illustrated in the Figure.
0000
Gray ode Decimal
Equivalent
1000
0
0001
0 0 0 0 0
1001
14
15 1
2
0011 0 0 0 1
0 0 1 1
1
2
1011
13
3
0010 0 0 1 0
0 1 1 0
1010 12
4
0110
0 1 1 1
0 1 0 1
1110
11
10
5
0111
0 1 0 0
1 1 0 0
1 1 0 1
1111
9
1101
0100
0101
1 1 1 1
1 1 1 0
10
11
1100
haracter odes
AS haracter ode
ASCII code is a bit code. Thus, it represents a total oI 12
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0
12
characters.
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Digital Logic Design by Morris Mano 3rd Edition
Out oI the 12 characters, there are 94 printable characters and 34 control (non printable)
characters.
The printable characters include the upper and lower case letters (2*2), the 10 numerals (09), and
32 special characters, e.g. (, °, $, etc.
For example, 'A¨ is at (41)1, while 'a¨ is at (1) )1.
To convert upper case letters to lower case letters, add (20)1. Thus 'a¨ is at (41)1 ¹ (20)1 (1)1.
The code oI the character '9¨ at position (39)1 is diIIerent Irom the binary number 9 (0001001). To
convert ASCII code oI a numeral to its binary number value, subtract (30)1.
Unicode haracter ode
Unicode is a 1bit character code that accommodates characters oI various languages oI the
world.
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Digital Logic Design by Morris Mano 3rd Edition
Binary ogic and Gates
ntroduction
Our obiective is to learn how to design digital circuits.
These circuits use binarv systems.
Signals in such binary systems may represent only one oI 2 54ssible values
0 or 1
!hvsicallv. these signals are electrical voltage signals
These signals may assume either a high or a o voltage value.
The high voltage value typically equals the voltage oI the power supply (eg
5 volts or 3.3 volts), and the o voltage value is typically 0 volts (or
Ground).
When a signal is at the igh voltage value, we say that the signal has a
Logic 1 value.
When a signal is at the o voltage value, we say that the signal has a Logic 0
value.
Hence, the phvsical value oI a signal is the actual voltage value it carries,
while its Logic value is either 1 (High) or 0 (Low).
Digital circuits process (or manipulate) input binary signals and produce the
required output binary signals as shown in Figure 1
x1 Z1
n Input
Binary Signals
x2
xn
Digital
ircuit
Zm
m Output
Binary Signals
Figure 1 A Digital Circuit with n Input Signals and m Output Signals
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Digital Logic Design by Morris Mano 3rd Edition
Generally, the circuit will have a number oI input signals (say n oI them) as
shown in the Figure x1, x2, up to xn, and a number oI output signals (say m )
Z1, Z2, up to Zm.
The value assumed by the ith output signal Zi depends on the values oI the
input signals x1, x2, up to xn.
In other words, we can say that Zi is a Iunction oI the n input signals x1, x2, up
to xn . Or we can write.
i Fi (x1. x2. ... xn ) for i ÷ 1. 2. 3. ..m
The m output Iunctions (Fi) are Iunctions oI binary signals and produce a
single binary output signal.
Thus, these Iunctions are binary Iunctions and require binary logic algebra Ior
their derivation and manipulation. This binary system algebra is commonly
reIerred to as B44lean lgebra aIter the mathematician George Boole. The
Iunctions are known as Boolean functions while the binary signals are
represented by Boolean variables.
To be able to design a digital circuit, we must learn how to derive the Boolean
Iunction implemented by this circuit.
Notes:
1. The two values oI binary variables may be equivalently reIerred to as 0 and 1
or False (0) and True (1)or as o (0) and igh(1)
2. Whether we use 0 and 1 or False and True or Low and High, all these are
reIerred to as Logic Values.
3. Systems manipulating Binary Logic Signals are commonly reIerred to as
Binary ogic systems
4. Digital circuits implementing a particular Binary (Boolean) Iunction are
commonly known as ogic ircuits
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Digital Logic Design by Morris Mano 3rd Edition
APTER OB1ETVES
earn Binarv L4gic and BOOLEA lgebra
earn o to Map a B44lean Ex5ressi4ns into ogic Circuit
25le2entati4ns
earn o To Manipulate B44lean Ex5ressi4ns and Si25li1v %e2
Elements of Boolean Algebra (Binary ogic)
As in standard algebra, Boolean algebra has 3 main elements:
1. Constants,
2. Variables, and
3. Operators.
ogically
C4nstant Jalues are either 0 or 1Binary 'ariables ¦ 0, 1}
3 !ossible O5erat4rs The AND operator. the OR operator, and the
NOT operator
Physically
onstants
Variables
^ Power Supply Voltage (Logic 1)
^ Ground Voltage (Logic 0)
^ Signals (High 1. o 0)
Operators ^ Electronic Devices (Logic Gates)
1. · AND  Gate
2. · OR  Gate
3. · NOT  Gate (Inverter)
ogic Gates & ogic Operations
The AND Operation
II and Y are two binarv variables. the result oI the operation AND Y is 1
if and onlv if both ÷ 1 and Y ÷ 1. and is 0 otherise
In Boolean expressions, the AND operation is represented either by a 'dot¨ or
by the absence oI an operator. Thus, AND Y is written as .Y or iust Y
This is summarized in the Iollowing table (commonly called truth table).
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Table 1 Truth Table oI the
AND operation
A Y
Table 1 Truth Table oI the
AND operation
A Y
F
F
T
T
Y
F
T
F
T
Y
F
F
F
T
0
0
1
1
Y
0
1
0
1
Y
0
0
0
1
The electronic device which perIorms the AND operation is called the AND
gate Figure 2 shows the symbol oI a 2input AND gate which has two inputs
(X and Y and gives one output Y
AND gate Symbol
Y
Y
Figure 2 TwoInput AND gate
The AND logic can be Iurther illustrated using what is known as the Venn
diagram
AND gates may have more than 2 inputs. Figure 3 shows a 3input AND gate.
3Input AND gate
W
WY
Y
Figure ThreeInput AND gate
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The truth table oI the output variable ZWXY oI the 3input AND gate is
given in Table 2
Table 2 Truth Table oI
3Input AND gate
W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Y
0
1
0
1
0
1
0
1
WY
0
0
0
0
0
0
0
1
Notes
The output oI an AND gate is 1 if and onlv if A its input signals are 1`s,
otherwise it is 0.
A Iunction oI two input binary variables will have a truth table oI 4 rows since
each variable may assume any one oI two possible values (0 or 1).
A Iunction oI three input variables will have a truth table oI rows since each
variable may assume any one oI two possible values (0 or 1).
In general, n input variables have 2n possible combinations. Accordingly, a
Iunction oI n input variables, will have a truth table oI 2n rows.
The OR Operation
II and Y are two binarv variables. the result oI the operation OR Y is 1 if
and onlv if either ÷ 1 or Y ÷ 1 or both & Y are 1`s. but it is 0
otherise
In other words, OR Y is 0 iI and only iI both ÷ 0 and Y ÷ 0. but is 1
otherise
In Boolean expressions, the OR operation is represented by a 'plus¨ sign.
Thus, OR Y is written as +Y
This is summarized in the Table 3.
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Table Truth Table oI the
OR operation
O# Y
0
0
1
1
Y
0
1
0
1
+Y
0
1
1
1
The electronic device which perIorms the OR operation is called the OR gate
Figure 4 shows the symbol oI a 2input OR gate which has two inputs (X and
Y and gives one output +Y
OR gate Symbol
+Y
Y
Figure TwoInput OR gate
The OR logic can be Iurther illustrated using the Venn diagram
OR gates may have more than 2 inputs. Figure 5 shows a 3input OR gate.
3Input OR gate
W
W++Y
Y
Figure ThreeInput OR gate
The truth table oI a 3 input OR gate ZW¹X¹Y is given in Table 4
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Table Truth Table oI
3Input OR gate
W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Y
0
1
0
1
0
1
0
1
WY
0
1
1
1
1
1
1
1
In general, the output oI an OR gate is 1 unless A its input signals are 0`s.
The NOT Operation
NOT is a 'unary¨ operator.
IF NOT , then the value oI will always be the complement oI the value
oI . In other words, iI 0 then 1, and iI 1 then 0.
In Boolean expressions, the NOT operation is represented by either a bar on
top oI the variable (e.g. Z = X ) or a prime (e.g. Z = X ' ).
This is summarized in Table 5.
Table Truth Table oI the
NOT operation
0
1
'
1
0
The electronic device which perIorms the NOT operation is called the NOT
gate. or simply A'E#%E#. Figure 5 shows the inverter symbol.
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Inverter Symbol
Figure An Inverter
II Z = X , Z is commonly reIerred to as the Complement oI X. Alternatively,
we say that Z equals Xcomplemented
The NOT operation can be Iurther illustrated using the Venn diagram
Boolean Algebra
ogic ircuits and Boolean Expressions
A Boolean expression (or a Boolean Iunction) is a combination oI Boolean
variables. ANDoperators. O#operators. and NOT operators.
· Boolean Expressions (Functions) are Iully deIined by their truth tablesEach
Boolean Iunction (expression) can be implemented by a digital logic circuit
which consists oI logic gates.
o Variables oI the Iunction correspond to signals in the logic circuit,
o Operators oI the Iunction are converted into corresponding logic gates
in the logic circuit.
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Example
Consider the expression F = + (Y ) The diagram oI the logic circuit
corresponding to this Iunction is shown in Figure
X
Y
Z
Y
( Y.Z )
F X ¹ Y. Z
Figure Logic Circuit Diagram oI F = + (Y )
The truth table oI this Iunction is shown in Table
Table Truth Table oI F = + (Y )
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
Y`
1
1
0
0
1
1
0
0
Y`Z
0
1
0
0
0
1
0
0
F÷ Y`Z
0
1
0
0
1
1
1
1
Since F is Iunction oI 3 variables (X, Y, Z), the truth table has 23 or
rows.
Basic dentities of Boolean Algebra
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AND dentities
From the truth table oI the AND operation, shown here Ior
reIerence, we can derive some basic identities. These identities
can be easily veriIied by showing that they are valid Ior both
possible values oI X (0 and 1).
A %rut %able
Y Y
0 0 0
0 1 0
1 0 0
1. 0 . X ÷ 0
1 1 1
A %rut %able
0
0
1
1
Y
0
1
0
1
Y
0
0
0
1
2. 1 . X ÷ X
A %rut %able
0
0
1
1
Y
0
1
0
1
Y
0
0
0
1
3. X . X ÷ X
A %rut %able
0
0
1
1
Y
0
1
0
1
Y
0
0
0
1
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4. X . X = 0
A %rut %able
0
0
1
1
Y
0
1
0
1
Y
0
0
0
1
OR dentities
From the truth table oI the OR operation, shown here Ior reIerence, we can derive
some basic identities. These identities can be easily veriIied by showing that they are
valid Ior both possible values oI X (0 and 1).
O# %rut %able
Y +Y
1. 1 ¹ X ÷ 1
0
0
1
1
0
1
0
1
0
1
1
1
2. 0 ¹ X ÷ X
O# %rut %able
0
0
1
1
Y
0
1
0
1
+Y
0
1
1
1
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X¹X÷X
O# %rut %able
0
0
1
1
Y
0
1
0
1
+Y
0
1
1
1
4. X + X = 1
O# %rut %able
0
0
1
1
Y
0
1
0
1
+Y
0
1
1
1
Summary of the basic identity
AND dentities
1. 0 . X ÷ 0
2. 1 . X ÷ X
3. X . X ÷ X
4. X . X = 0
OR dentities
5. 1 ¹ X ÷ 1
6. 0 ¹ X ÷ X
7. X ¹ X ÷ X
. X + X = 1
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Duality Principle
Given a Boolean expression, its dual is obtained by replacing each 1 with a 0,
each 0 with a 1, each AND (.) with an OR (¹), and each OR (¹) with an
AND(.).
The dual oI an identity is also an identity. This is known as the duality
principle.
It can be easily shown that the AND basic identities and the OR basic identities are
duals as shown in Table
Table Duality oI the AND and OR Basic Identities
AND dentities
0÷0
1÷
0
1
1
0
Dual dentities
(OR Udentities)
1÷1
0÷
÷ ÷
÷0
Another mportant dentity
X = X
0
1
÷1
NOT operation
Truth Table
This can be simply proven Irom the truth table oI the NOT
operation as shown.
0
1
1
0
0
1
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Operator Precedence
Given the Boolean expression Y WZ the order oI applying the operators will
aIIect the Iinal value oI the expression.
Y WZ
AND
Hig
Prio
OR
Hig
her
Prio
rity
1. Compute X AND Y
2. Compute W AND Z
3. OR the previousle
computed two values
((X.Y) ¹ (W.Z))
1. Compute Y OR W
2. AND the result with X
3. AND the result with Z
X . (Y ¹ W) . Z
For Boolean Algebra, the precedence rules Ior various operators are given below , in a
decreasing order oI priority:
1 !arentheses
2 Not operator (Complement)
3 AND operator,
4 O# operator
Highest !rioritv
Lowest !rioritv
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Properties of Boolean Algebra
Important properties oI Boolean Algebra are shown in Table
Property Dual Property
ommutative
Distributive
DeMorgan
Extended
DeMorgan
X¹YY¹X
X.(Y ¹ Z) X.Y ¹ X.Z
(X ¹ Y) ` X`.Y`
(A¹B¹C¹ ..¹Z) `
A`.B`.C`...Z`
X.YY.X
X¹(Y.Z) (X¹Y).(X¹Z)
(X.Y) ` X` ¹ Y`
(A.B.C..Z) `
A`¹B`¹C`¹..¹Z`
Generalized
DeMorgan
F(x1,x2,.,xn,0,1,¹,.) `F(x`1,x`2,.,x`n,1,0,.,¹)
Notes
The above properties can be easily proved using truth tables.
The only diIIerence between the dual oI an expression and the complement oI
that expression is that in the dual variables are not complemented while in the
complement expression, all variables are complemented.
Using the above properties, complex Boolean expressions can be manipulated
into a simpler forms resulting in simpler logic circuit implementations.
Simpler expressions are generally implemented by simpler logic circuits
which are both Iaster and less expensive. This represents a great advantage
since cost and speed are prime Iactors in the success and proIitability oI any
product.
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Algebraic Manipulation
The obiective here is to acquire some skills in manipulating Boolean
expressions into simpler Iorms Ior more eIIicient implementations.
Properties oI Boolean algebra will be utilized Ior this purpose.
Example
Proof:
Prove that X ¹ XY X
X ¹ XY X..(1 ¹ Y) X.1 X
Example Prove that X ¹ X`Y X ¹ Y This an important identitv that is
useful in simplifving more complex expressions
Proof: This ill be proved in to ays
(1) X ¹ X`Y (X¹ X`) (X ¹ Y)
÷1
1.(X ¹ Y)
X¹Y
(2) X ¹ X`Y X.1 ¹ X`Y
X.(1¹Y) ¹ X`Y
X ¹ XY ¹ X`Y
X ¹ (XY ¹X`Y)
X ¹ Y(X ¹X` )
÷1
X¹Y
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Example ``onsensus Theory``
Show that XY ¹ X`Z ¹ YZ XY ¹ X`Z
Proof:
S ÷ XY ¹ X`Z ¹ YZ
÷ XY ¹ X`Z ¹ YZ 1
XY ¹ X`Z ¹ YZ (X ¹X`)
XY ¹ X`Z ¹ YZX ¹ YZX`
XY ¹ YZX ¹ X`Z ¹ YZX`
XY(1 ¹ Z) ¹ X`Z(1 ¹ Y)
÷1
÷1 ÷1
XY 1 ¹ X`Z 1 XY ¹ X`Z ÷ S
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Example
SimpliIy the Iollowing Iunction
1 = ( A + B + AB) ( AB + AC + BC )
Solution:
F1 ÷ ( + B + B) ( AB + AC + BC )
Using DeMorgan theorem
( + B + B) A` B (A` ¹ B) A` B ¹ A` B A` B
( AB + AC + BC ) (A` ¹ B`)(A ¹ C` )(B` ¹ C` )
F1 ÷ ( + B + B) ( AB + AC + BC )
÷ A` B (A` ¹ B`)(A ¹ C` )(B` ¹ C` )
Since ÷ ÷. e can rerite the previous expression as follos
F1 ÷ (A`B) (A` B) (A` B) (A` ¹ B)(A ¹ C` )(B` ¹ C` )
÷ (A`B) (A` ¹ B`) (A` B) (A ¹ C` ) (A` B) (B` ¹ C` )
(A`B ¹ 0 ) (0 ¹ A` BC` ) (A`B ¹ A`BC`)
(A`B) (A` BC` ) (A`B)
A` BC`
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Example
SimpliIy the Iollowing Iunction
G ( A + B + C ) . ( AB + C D ) + ACD
Solution:
= ( A + B + C ) .( AB + C D ) + ACD
= ( A + B + C ) + AB.C + D . ACD
= ( A + B + C ) . ACD + AB.C + D .ACD
= ( ACD + ACD B ) + ( ACDB + ACDB)
= ACD + ACDB
= ACD
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Standard & anonical Forms
APTER OB1ETVES
earn Binarv L4gic and BOOLEA lgebraLearn o to Map a B44lean
Ex5ressi4n into ogic Circuit 25le2entati4n earn o To Manipulate
B44lean Ex5ressi4ns and Si25li1v %e2esson OjectivesLearn how
to derive a Boolean expression oI a Iunction deIined by its truth table. The
derived expressions may be in one oI two possible standard Iorms: The Sum
of Minterms or the !roduct of MaxTerms.
Learn how to map these expressions into logic circuit implementations (2
Level Implementations).
MinTerms
Consider a system oI 3 input signals (variables) x, y, & z.
A term which ANDs all input variables, either in the true or complement Iorm,
is called a minterm.
Thus, the considered 3input system has minterms, namely:
x v z , x v z , x v z , x v z , x v z , x v z , x v z & x v z
Each minterm equals 1 at exactly one particular input combination and is
equal to 0 at all other combinations
Thus, Ior example, x v z is always equal to 0 except Ior the input
combination xvz 000, where it is equal to 1.
Accordingly, the minterm x v z is reIerred to as m0.
In general, minterms are designated mi, where i corresponds the input
combination at which this minterm is equal to 1.
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IFF
IFF
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For the 3input system under consideration, the number oI possible input
combinations is 23, or . This means that the system has a total oI minterms
as Iollows:
m0 x v z 1 xvz 000, otherwise it equals 0
m1 x vz 1
m2 x v z 1
m3 x vz 1
m4 x v z 1
m5 x vz 1
m6 xv z 1
m7 xvz 1
IFF
IFF
IFF
IFF
IFF
IFF
xvz 001, otherwise it equals 0
xvz 010, otherwise it equals 0
xvz 011, otherwise it equals 0
xvz 100, otherwise it equals 0
xvz 101, otherwise it equals 0
xvz 110, otherwise it equals 0
xvz 111, otherwise it equals 0
n general.
For ninput variables, the number oI minterms the total number oI possible
input combinations 2n.
A minterm 0 at all input combinations except one where the minterm 1.
MaxTerms
Consider a circuit oI 3 input signals (variables) x, y, & z.
A term which ORs all input variables, either in the true or complement Iorm,
is called a Maxterm.
With 3input variables, the system under consideration has a total oI
Maxterms, namely:
( x + v + z ). ( x + v + z ) . ( x + v + z ) . ( x + v + z ). ( x + v + z ) . ( x + v + z ) . ( x + v + z ) & ( x + v + z )
Each Maxterm equals 0 at exactly one oI the possible input combinations
and is equal to 1 at all other combinations.
For example, ( x + v + z ) equals 1 at all input combinations except Ior the
combination xvz 000, where it is equal to 0.
Accordingly, the Maxterm ( x + v + z ) is reIerred to as M0.
In general, Maxterms are designated Mi, where i corresponds to the input
combination at which this Maxterm is equal to 0.
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IFF
IFF
IFF
IFF
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For the 3input system, the number oI possible input combinations is 23, or .
This means that the system has a total oI Maxterms as Iollows:
M0 ( x + v + z ) 0 IFF
M1 ( x + v + z ) 0
M2 ( x + v + z ) 0
M3 ( x + v + z ) 0 IFF
M4 ( x + v + z ) 0 IFF
M5 ( x + v + z ) 0 IFF
M6 ( x + v + z ) 0
M7 ( x + v + z ) 0
xvz 000, otherwise it equals 1
xvz 001, otherwise it equals 1
xvz 010, otherwise it equals 1
xvz 011, otherwise it equals 1
xvz 100, otherwise it equals 1
xvz 101, otherwise it equals 1
xvz 110, otherwise it equals 1
xvz 111, otherwise it equals 1
n general.
For ninput variables, the number oI Maxterms the total number oI possible
input combinations 2n.
A Maxterm 1 at all input combinations except one where the Maxterm 0.
mprtant Result
Using DeMorgan`s theorem, or truth tables, it can be easily shown that:
M i = 2
i = 0.1. 2. . (2 1)
Expressing Functions as a Su2 41 Minter2s and Product of
Maxterms
Example: Consider the Iunction deIined by the shown truth table
x v z F
Now let`s rewrite the table, with Iew added columns.
A column i indicating the input combination
Four columns oI minterms m2, m4, m5 and m7
One last column ORing the above minterms (m2 ¹ m4 ¹ m5
¹ m7)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
1
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x v z F 22 24 2 2 22+ 24+ 2+ 2
0
1
2
3
4
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
From this table, we can clearly see that F m2 ¹ m4 ¹ m5 ¹ m7
This is logical since F 1, only at input combinations i 2, 4, 5 and
Thus, by ORing minterm m2 (which has a value oI 1 only at input combination
i 2) with minterm m4 (which has a value oI 1 only at input combination i 4)
with minterm m5 (which has a value oI 1 only at input combination i 5) with
minterm m (which has a value oI 1 only at input combination i ) the
resulting Iunction will equal F.
n general, Any Iunction can be expressed by O#ing all minterms (mi)
corresponding to input combinations (i) at which the Iunction has a value oI 1.
The resulting expression is commonly reIerred to as the SUM 41 2inter2s and
is typically expressed as F ÷ (2. . . ). where indicates ORing oI the
indicated minterms. Thus, F ÷ (2. . . ) (m2 ¹ m4 ¹ m5 ¹ m)
Example:
Consider the Iunction oI the previous example.
We will, Iirst, derive the sum oI minterms expression Ior the
x v z F F`
complement Iunction F`.
The truth table oI F` shows that F` equals 1 at i 0. 1. 3 and 6. then,
F` m0 ¹ m1 ¹ m3 ¹ m6. i.e
0
1
2
3
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
0
1
1
0
1
F` ÷ (0. 1. . ).
F ÷ (2. . . )
(1)
(2)
4
5
1
1
1
0
0
1
0
1
0
1
1
0
0
0
1
Obviously, the sum oI minterms expression oI F` contains all 1 1 1 1 0
minterms that do not appear in the sum oI minterms expression oI F.
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Using DeMorgan theorem on equation (2).
F = 2 2 + 2 4 + 25 + 2 = 2 2.2 4.2 5.2 = M 2.M 4.M 5.M
This Iorm is designated as the !roduct of Maxterms and is expressed using the
symbol, which is used to designate product in regular algebra, but is used to designate
ANDing in Boolean algebra.
Thus,
F` ÷ (2. . . ) ÷ M2 M4 M M
From equations (1) and (3) we get,
F` ÷ (0. 1. . ) ÷ (2. . . )
In general, anv function can be expressed both as a sum of minterms and as a product
of maxterms. Consider the derivation oI F back Irom F` given in equation (3):
F = F = 20 + 21 + 23 + 2 = 20 .21.23 . 2 =M 0 . M 1. M 3 . M
F ÷ (2. . . ) ÷ (0. 1. . )
F` ÷ (2. . . ) ÷ (0. 1. . )
onclusions:
Any Iunction can be expressed both as a sum oI minterms ( mi) and as a
product oI maxterms. The product oI maxterms expression ( M) expression
oI F contains all maxterms M ( i) that do not appear in the sum oI
minterms expression oI F.
The sum oI minterms expression oI F` contains all minterms that do not
appear in the sum oI minterms expression oI F.
This is true Ior all complementary Iunctions. Thus, each oI the 2n minterms
will appear either in the sum oI minterms expression oI F or the sum oI
minterms expression oI but not both.
The product oI maxterms expression oI F` contains all maxterms that do
not appear in the product oI maxterms expression oI F.
This is true Ior all complementary Iunctions. Thus, each oI the 2n maxterms
will appear either in the product oI maxterms expression oI F or the product oI
maxterms expression oI but not both.
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Digital Logic Design by Morris Mano 3rd Edition
Example:
Given that F (a. b. c. d) ÷ (0. 1. 2. . . ). derive the product oI maxterms
expression oI F and the 2 standard Iorm expressions oI F`
Since the system has 4 input variables (a, b, c & d)
Maxterms 24 1
F (a. b. c. d) ÷ (0. 1. 2. . . )
1. List all maxterms in
The number oI minterms and
the Product oI
maxterms expression F ÷ (0. 1. 2. . . . . . . . 10. 11. 12. 1. 1. 1)
2. Cross out maxterms
F ÷ (0. 1. 2. . . . . . . . 10. 11. 12. 1. 1. 1)
corresponding to input
combinations oI the
minterms appearing in
the sum oI minterms
expression
F ÷ (. . . . 10. 11. 12. 1. 1. 1)
Similarly. obtain both canonical form expressions for F`
F` ÷ (. . . . 10. 11. 12. 1. 1. 1)
F` ÷ (0. 1. 2. . . )
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Digital Logic Design by Morris Mano 3rd Edition
anonical Forms:
The sum oI minterms and the product oI maxterms Iorms oI Boolean expressions are
known as the canonical Iorms ( '¹· '¹'·Ɗ ( oI a Iunction.
Standard Forms:
A product term is a term with ANDed literals*. Thus, AB, A`B, A`CD are all
product terms.
A minterm is a special case oI a product term where all input variables appear
in the product term either in the true or complement Iorm.
A sum term is a term with ORed literals*. Thus, (A¹B), (A`¹B), (A`¹C¹D) are
all sum terms.
A maxterm is a special case oI a sum term where all input variables, either in
the true or complement Iorm, are ORed together.
Boolean Iunctions can generally be expressed in the Iorm oI a Sum oI
Products (SOP) or in the Iorm oI a Product oI Sums (POS).
The sum oI minterms Iorm is a special case oI the SOP Iorm where all product
terms are minterms.
The product oI maxterms Iorm is a special case oI the POS Iorm where all
sum terms are maxterms.
The SOP and POS Iorms are Standard Iorms Ior representing Boolean
Iunctions.
A Boolean variable in the true or complement forms
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Digital Logic Design by Morris Mano 3rd Edition
Toevel mplementations of Standard Forms
Sum of Products Expression (SOP):
Any SOP expression can be implemented in 2levels oI gates.
The Iirst level consists oI a number oI AND gates which equals the number oI
product terms in the expression. Each AND gate implements one oI the
product terms in the expression.
The second level consists oI a SNLE OR gate whose number oI inputs
equals the number oI product terms in the expression.
Example Implement the Iollowing SOP Iunction
F XZ ¹ Y`Z ¹ X`YZ
Level 1
Z
Y`
Level 2
F
Z
`
Y
Z
Toevel mplementation (F ÷ Z Y`Z `YZ )
evel1: ANDGates ; evel2: One ORGate
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Digital Logic Design by Morris Mano 3rd Edition
Product of Sums Expression (POS):
Any POS expression can be implemented in 2levels oI gates
The Iirst level consists oI a number oI OR gates which equals the number oI
sum terms in the expression, each gate implements one oI the sum terms in the
expression.
The second level consists oI a SNLE AND gate whose number oI inputs
equals the number oI sum terms.
Example Implement the Iollowing SOP Iunction
F (X¹Z )(Y`¹Z)(X`¹Y¹Z )
Level 1
Z
Y`
Level 2
F
Z
`
Y
Z
Toevel mplementation ]F ÷ (Z )(Y`Z)(`YZ )]
evel1: ORGates ; evel2: One ANDGate
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
1.
2.
3.
4.
5.
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Digital Logic Design by Morris Mano 3rd Edition
Practical Aspects Of ogic Gates
ntroduction & Objectives
Logic gates are physically implemented as Integrated Circuits (IC).
Integrated circuits are implemented in several technologies.
Two landmark IC technologies are the TT and the MOS technologies.
Maior physical properties oI a digital IC depend on the implementation technology.
In this lesson, the Iollowing maior properties oI digital IC`s are described:
Allowed physical range oI voltages Ior logic 0 and logic 1,
Gate propagation delay/ speed,
The Ianin and Ianout oI a gate,
The use oI buIIers, and
TriState drivers
Alloed Voltage evels
Practically, logic 0 is represented by a certain
#ANE oI Voltages rather than by a single voltage
level.
Valid Logic 1
Voltages
.In other words, iI the voltage level oI a signal Ialls
in this range, the signal has a logic 0 value.
Invalid Range
Likewise, logic 1 is represented by a diIIerent
#ANE oI valid voltages.
The range oI voltages between the highest logic 0
voltage level and the lowest logic 1 voltage level is
OI Voltages
Valid Logic 0
Voltages
an 'Illegal Joltage #ange`.
No signal is alloed to assume a voltage value in this range
nput & Output Voltage Ranges
Inputs and outputs oI IC`s do not have the same allowed range of voltages neither Ior
logic 0 nor Ior logic 1.
V is the maximum input voltage that considered a Logic 0.
VO is the maximum output voltage that considered a Logic 0.
VO must be lower than V to guard against noise disturbance.
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Why is V > VO ?
Consider the case oI connecting the
output oI gate A to the input oI
another gate B:
The logic 0 output oI A must
be within the range oI
acceptable logic 0 voltages oI gate B inputs.
Voltage level at the input oI B Voltage level at the output oI A ¹ Noise
Voltage
II the highest logic 0 output voltage oI A (VO) is equal to the highest logic 0
input voltage oI B (V), then the noise signal can cause the actual voltage at
the input oI B to Iall in the invalid range oI voltages.
Valid Logic 1
Voltages
Maximum
Tolerable noise
Invalid Range
V
OI Voltages
Valid Logic 0
Output Voltages
VO Valid Logic 0
Input Voltages
Accordingly, VO is designed to be lower than V to allow Ior some noise margin.
The diIIerence (V  VO) is thus known as the noise margin Ior logic 0 (NM0).
V is the minimum input voltage that considered a Logic 1.
VO is the minimum output voltage that considered a Logic 1.
VO must be higher than V to guard against noise signals.
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Digital Logic Design by Morris Mano 3rd Edition
Why is VO > V ?
Allowed Noise
Margin oI 0.4v
A
VOH2.4v
.
..
..
..
VIH2v
B
Consider the case oI connecting the output oI gate A to the input oI another gate B:
The logic 1 output oI A must accepted as logic 1 by the input oI gate B
Thus, the logic 1 output oI A must be within the range oI voltages which are
acceptable as logic 1 input Ior gate B
II the lowest logic 1 output voltage oI A (VO) is equal to the lowest logic 1
input voltage oI B (V), then noise signals can cause the actual voltage at the
input oI B to Iall in the invalid range oI input voltages.
Valid Logic 1
Output Voltages
Maximum
Tolerable noise
V OH
V IH
Valid Logic 1
Input Voltages
Invalid
Range
OI Voltages
Valid Logic 0
Input Voltages
Accordingly, VO is designed to be higher than V to allow Ior some noise margin.
The diIIerence (VO  V) is thus known as the noise margin Ior logic 1 (NM1).
Definition
Noise margin is the maximum noise voltage that can be added to the input signal oI a
digital circuit without causing an undesirable change in the circuit output..
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Digital Logic Design by Morris Mano 3rd Edition
V
V
Valid Logic 1
Voltages
Valid Logic 0
Voltages
NM 1
NM 0
Valid Logic 1
Voltages
Valid Logic 0
Voltages
VO
VO
NPUT VOTAGES OUTPUT VOTAGES
Propagation Delay
Consider the shown inverter with input X and
output Z.
X
ZX
A change in the input (X) Irom 0 to 1
causes the inverter output (Z) to change
X
Z
Irom 1 to 0.
!ropagation
Delav ÷
The change in the output (Z), however is
not instantaneous. Rather, it occurs slightly aIter the input change.
This delav between an input signal change and the corresponding output
signal change is what is known as the propagation delav.
In general,
A signal change on the input oI some IC takes a Iinite amount oI time to
cause a corresponding change on the output.
This Iinite delay time is known as Propagation Delay
Faster circuits are characterized by smaller propagation delays.
Higher perIormance systems require higher speeds (smaller propagation
delays).
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Timing Diagrams
A timing diagram shows the logic values oI signals in a circuit versus
time.
A signal shape versus time is typically reIerred to as aveform.
Example
The Iigure shows the timing diagram oI a 2input AND gate. The gate is
assumed to have a propagation delay oI
X
Y
!ropagation
Delav ÷
Z
The timing diagram shown Figure illustrates the waveIorms oI signals X,
Y, and Z.
Note how the output Z is delayed Irom changes oI the input signals &
Y by the amount oI the gate Propagation Delay
X
Y
Z
t
Time
Fanin imitations
The fanin of a gate is the number oI inputs oI this gate.
Thus, a 4input AND gate is said to have a fanin oI 4.
A physical gate cannot have a large number oI inputs (Ianin).
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2
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·For CMOS technology, the more inputs a gate has the slower it is (larger
propagation delay). For example, a 4input AND gate is slower than a 2
input one.
In CMOS technology, no more than 4input gates are typically built since
more than 4 inputs makes the devices too slow.
TTL gates can have more inputs (e.g, input NAND 430).
Fanout imitations
II the output oI some gate A is
connected to the input oI another gate B.
gate A is said to be driving gate, while
gate B is said to be the load gate.
As the Figure shows, a driver gate
may have more than one load gate.
There is a limit to the number oI gate
inputs that a single output can drive.
The fanout of a gate is the largest
number oI gate inputs this gate can
drive.
For TTL, the fanout limit is based on
Driver Gate
n
Load Gates
CURRENT.
A TTL output can supply a maximum current OL 1 mA (milliamps)
A TTL input requires a current oI IL ÷1mA
Thus, the fanout Ior TTL is 1mA/1. mA 10 loads.
For CMOS, the limit is based on SPEED/propagation delay.
A CMOS input resembles a capacitive load (10 pI  picoIarads).
The more inputs tied to a single output, the higher the capacitive load.
The HIGHER the capacitive load, the SLOWER the propagation delay.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
"
A
"
A
x
Gate
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Digital Logic Design by Morris Mano 3rd Edition
Typically, it is advisable to avoid loads much higher than about loads.
What is meant by the D#JE oI a gate?
It is the 'CURRENT¨ drivingability oI a gate. In other words, it is the
amount oI current the gate can deliver to its load devices.
A gate with highdrive is capable oI driving more load gates than
another with lowdrive.
How to drive a number oI load gates that is larger than the Ianout oI the
driver gate?
In this case, we can use one oI two methods:
1. Use high drive buIIers
2. Use multiple drivers.
Use of ighDrive Buffers:
A buIIer is a single input, single output
BuIIer Symbol
Z÷x
gate where the logic value oI the output
equals that oI the input.
The logic symbol oI the buIIer is shown in the Figure.
The buIIer provides the necessary drive capability which allows driving
larger loads.
Note that the symbol oI the buIIer resembles the inverter symbol except
that it does not have the inverting circle that the inverter symbol has.
The Iigure shows how the buIIer is
used to drive the large load.
High Drive
BuIIer
1
Use of Multiple Drivers:
D
2
The Figure shows the case oI 2 Driver
identical drivers driving the load
gates.
In general, the large number oI load
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
n
Load Gates
n~ fanout (D)
1
2
m
m¹1
n
"
A
"
A
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Digital Logic Design by Morris Mano 3rd Edition
gates is divided among
more than one driver such
that each oI the identical
drivers is driving no more
than the Ianout.
The multiple driver gates
D1
Driver Gate 1
Load Gates
n~ fanout
(D1, D2) are oI identical D2
m¹2
type and should be
Driver Gate 2
connected to the same
input signals
TriState Outputs
Can the outputs oI 2 ICs, or 2 gates, be directly connected?
Generally, Nooooooooooo!!! This is only possible iI special types oI
gates are used.
Why cann`t the outputs oI 2 normal gates be directly connected?
Because this causes a s4rt Circuit that results in huge current Ilow with
a subsequent potential Ior damaging the circuit.
This is obvious since one output may be at logic 1 (High voltage),
while the other output may be at logic 0 (Low voltage).
Furthermore, the common voltage level oI the shorted outputs will
most likely Iall in the invalid range oI voltage levels.
0
1
1
Huge
Current
0
Short Circuit
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"
A
S1
S0
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Digital Logic Design by Morris Mano 3rd Edition
What are the types oI IC output pins that can be directly connected?
These are pins/gates with special output drivers. The two main types are:
OpenCollector outputs this will not be discussed in this course.
Outputs with TriState capability.
Gates ith TriState Outputs
These gates can be in one oI 2 possible states:
1. An enabled state where the output may assume one oI two possible
values:
Logic 0 value (low voltage)
Logic 1 value (high voltage)
2. A disabled state where the gate output is in a the Hiimpedance
(HiZ) state. In this case, the gate output is disconnected (open
circuit) Irom the wire it is driving.
An enable input (E) is used to control the gate into either the enabled or
disabled state.
The enable input (E) may be either active high or active low.
Any gate or IC output may be provided
with tristate capability.
Output State llustrations
A generalized output driver can be simply
modeled using 2 switches S1 and S0 as
shown in Figure.
The output state is deIined by the state oI
the 2 switches (closed open)
II S1 is closed and S0 is open, the output is
high (logic 1) since it is connected to the
power supply (VDD).
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Power Supply
VDD
Output
GND
VDD
GND
GND
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Digital Logic Design by Morris Mano 3rd Edition
Power Supply
II S1 is open and S0 is closed, the output
is low (logic 0) since it is connected to
the ground voltage (0 volt).
S1 Closed
Output High Logic1
S0 Open
II, however, both S1 is and S0 are open,
then the output is neither connected to
ground nor to the power supply. In
this case, the output node is Iloating
or is in the HiImpedance (HiZ)
state.
Power Supply
VDD
S1 Open
Output Low Logic 0
S0 Closed
Examples
a) TriState nverter ith active high
enable
E
Power Supply
VDD
S1 Open
Output HiImpedance
ogic
Symbol
x G1
Z S0 Open
(HiZ)
TriState Inverter
with activehigh enable
GND
Truth
Table
E
1
1
0
0
x
0
1
0
1
Z
1
0
HiZ
HiZ
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Digital Logic Design by Morris Mano 3rd Edition
E 1
Enabled
State
x G1
Z ÷ x
G2
TriState Inverter
with activehigh enable
E ô
Open Circuit
(HiImpedance)
Floating Line
Disconnected
Irom G1
x G1
Z
G2
Dis
abled
TriState Inverter
with activehigh enable
State
E ô
x
Floating Line
Disconnected
Irom G1
G2
In HiZ State G1 is
Open Circuit
(Disconnected Irom
Output line)
b) TriState nverter ith active lo enable
E
ogic
Symbol
x G1
Z
TriState Inverter
with activelow enable
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Digital Logic Design by Morris Mano 3rd Edition
E
x Z
Truth
Table
0
0
1
1
0
1
0
1
1
0
HiZ
HiZ
Eô
Enabled
State
x G1
Z ÷ x
G2
TriState Inverter
with activelow enable
E 1
Open Circuit
(HiImpedance)
Floating Line
Disconnected
Irom G1
Dis
x G1
TriState Inverter
with activelow enable
Z
G2
abled
State
E 1
x
Floating Line
Disconnected
Irom G1
G2
In HiZ State G1 is
Open Circuit
(Disconnected Irom
Output line)
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Digital Logic Design by Morris Mano 3rd Edition
ondition for onnecting Outputs of TriState Gates
Two or more tristate outputs may be connected provided that at most one
oI these outputs is enabled while all others are in the HiZ state.
This avoids conIlict situations where one gate output is high while
another is low.
ircuit Examples
The shown circuit has tristate
inverters with active high enable
inputs.
The outputs oI these 2 inverters
are shorted together as a
common output signal Z
The 2 gates are NEVER enabled
at the same time.
G1 is enabled when E1, while
G2 is enabled when E0
The circuit perIorms the Iunction: = E x + E v
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KMap 1
esson Objectives:
Even though Boolean expressions can be simpliIied by algebraic manipulation, such
an approach lacks clear regular rules Ior each succeeding step and it is diIIicult to
determine whether the si25lest ex5ressi4n has been achieved.
In contrast, Karnaugh map (Kmap) method provides a straightIorward procedure Ior
simpliIying Boolean Iunctions.
Kmaps oI up to 4 variables are very common to use. Maps oI 5 and variables can
be made as well, but are more cumbersome to use.
SimpliIied expressions produced by Kmaps are always either in the SOP or the POS
Iorm.
The map provides the same inIormation contained in a Truth Table but in a diIIerent
Iormat.
The obiectives oI this lesson are to learn:
1. How to build a 2, 3, or 4 variables Kmap.
2. How to obtain a minimized SOP Iunction using Kmaps.
Code Distance:
Let`s Iirst deIine the concept oI Code Distance. The distance between two binary
codewords is the number oI bit positions in which the two codewords have diIIerent
values.
For example, the distance between the code words 1001 and 0001 is 1 while the
distance between the codewords 0011 and 0100 is
This deIinition oI code distance is commonly known as the a22ing distance
between two codes.
ToVariable KMaps:
The 2variable map is a table oI 2 rows by 2 columns. The 2 rows represent the two
values oI the Iirst input variable A, while the two columns represent the two values oI
the second input variable B.
Thus, all entries (squares) in the Iirst row correspond to input variable A0, while
entries (squares) oI the second row correspond to A1.
Likewise, all entries oI the Iirst column correspond to input variable B 0, while
entries oI the second column correspond to B1.
Thus, each map entry (or square) corresponds to a unique value Ior the input variables
A and B.
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For example, the top leIt square corresponds to input combination AB00. In other
words, this square represents minterm m0.
Likewise, the top right square corresponds to input combination AB01, or minterm
m1 and the bottom leIt square corresponds to input combination AB10, or minterm
m2. Finally, the bottom right square corresponds to input combination AB11, or
minterm m3.
In general, each map entry (or square) corresponds to a particular input combination
(or minterm).
Since, Boolean Iunctions oI twovariables have Iour minterms, a 2variable Kmap
can represent any 2variable Iunction by plugging the Iunction value Ior each input
combination in the corresponding square.
DeIinitions/Notations:
Two Kmap squares are considered adjacent iI the input codes they represent have a
Hamming distance of 1.
A Kmap square with a Iunction value of 1 will be reIerred to as a 1Square.
A Kmap square with a Iunction value of 0 will be reIerred to as a ôSquare.
The simpliIication procedure is summarized below:
Step 1: Draw the map according to the number oI input variables oI the Iunction.
Step 2: Fill '1`s¨ in the squares Ior which the Iunction is true.
Step : Form as big group oI adjacent 1squares as possible. There are some rules Ior
this which you will learn with bigger maps.
Step : Find the common literals Ior each group and write the simpliIied expression
in SOP.
Example:
Consider the given truth table oI two variable Iunction. Obtain the simpliIied Iunction
using Kmap.
A
0
0
1
1
B
0
1
0
1
F
0
0
1
1
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First draw a 2variable Kmap. The Iunction F is true when AB` (m2) is true and when
AB (m3) is true, so a 1 is placed inside the square that belongs to m2 and a 1 is placed
inside the square that belongs to m3.
Since both oI the 1squares have diIIerent values Ior variable B but the same value Ior
variable A, which is 1, i.e., wherever A 1 then F 1 thus F A.
This simpliIication is iustiIied by algebraic manipulation as Iollows:
F ÷ m2 m ÷ AB` AB ÷ A (B` B) ÷ A
To understand how combining squares simpliIies Boolean Iunctions, the basic
property possessed by the adjacent squares must be recognized.
In the above example, the two 1squares are adiacent with the same value Ior variable
A (A1) but diIIerent values Ior variable B (one square has B0, while the other has
B1).
This reduction is possible since both squares are adiacent and the net expression is
that oI the common variable (A).
Generally, this is true Ior any 2 codes oI Hamming distance 1 (adiacent). For an n
variable Kmap, let the codes oI two adjacent squares (distance oI 1) have the same
value Ior all variables except the ith variable. Thus,
ode of 1st Square: X 1 .X 2 ......X i 1 . i .X i +1 ......X n
ode of 2nd Square: X 1 .X 2 ......X i 1 . i . X i +1 ......X n
Combining these two squares in a group will eliminate the diIIerent variable i and
the combined expression will be
X 1 .X 2 ......X i 1 .X i +1 ......X n
since:
X 1 .X 2 ......X i 1 . i . X i +1 ...... X n + X 1 .X 2 ......X i 1 . i .X i +1 ......X n
= X 1 .X 2 ......X i 1 .X i +1 ......X n i + i )
= X 1 .X 2 ......X i 1 .X i +1 ......X n
The variable in diIIerence is dropped.
Another Example:
SimpliIy the given Iunction using Kmap method:
F ÷ _ (1. 2. )
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Digital Logic Design by Morris Mano 3rd Edition
In this example:
F ÷ m1 m2 m ÷ m1 m2 (m m)
F ÷ (m1 m) (m2 m) ÷ A B
Rule: A 1square can be member oI more than one group.
II we exchange the places oI A and B. then minterm positions will also change. Thus,
m1 and m2 will be exchanged as well.
In an nvariable map each square is adjacent to 'n¨ other squares, e.g., in a 2variable
map each square is adiacent to two other squares as shown below:
Examples oI nonadiacent squares are shown below:
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Digital Logic Design by Morris Mano 3rd Edition
ThreeVariable KMaps:
There are eight minterms Ior a Boolean Iunction with threevariables. Hence, a three
variable map consists oI squares
All entries (squares) in the Iirst row correspond to input variable A0, while entries
(squares) oI the second row correspond to A1.
Likewise, all entries oI the Iirst column correspond to input variable B 0, C 0, all
entries oI the second column correspond to input variable B 0, C 1, all entries oI
the third column correspond to input variable B 1, C 1, while entries oI the Iourth
column correspond to B1, C 0.
To maintain adiacent columns physically adiacent on the map, the column coordinates
do not Iollow the binary count sequence. This choice yields unit distance between
codes oI one column to the next (00 0111 10), like Grey ode
Variations oI ThreeVariable Map:
The Iigure shows variations oI the threevariable map. Note that the minterm
corresponding to each square can be obtained by substituting the values oI variables
AB in order.
Examples: (see authorare version)
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There are cases where two squares in the map are considered to be adiacent even
though they do not physically touch each other.
In the Iigure oI 3variable map, m0 is adiacent to m2 and m4 is adiacent to m because
the minterms diIIer by only one variable. This can be veriIied algebraically:
m0 m2 ÷ A`B`` A`B` ÷ A`` (B` B) ÷ A``
m m ÷ AB`` AB` ÷ A` (B` B) ÷ A`
Rule: Groups may only consist oI 2. . . 1.. squares (always power oI 2). For
example, groups may not consist oI 3, or 12 squares.
Rule: Members oI a group must have a closed loop adiacency, i.e., Shaped
squares do not Iorm a valid group.
Notes:
1 Each square is adiacent to 3 other squares.
2 One square is represented by a minterm (i.e. a product term containing all 3
literals).
A group oI 2 adiacent squares is represented by a product term containing only 2
literals, i.e., 1 literal is dropped.
A group oI 4 adiacent squares is represented by a product term containing only 1
literal, i.e., 2 literals are dropped.
FourVariable KMaps:
There are 1 minterms Ior a Boolean Iunction with fourvariables Hence, Iour
variable map consists oI 1 squares.
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Notes:
Each square is adjacent to other squares.
One square is represented by a minterm (a product oI all 4literals).
Combining 2 squares drops 1literal
Combining squares drops 2literals
Combining squares drops literals
Examples: (see authorare version)
Rule: The combination oI squares that can be chosen during the simpliIication
process in the nvariable map are as Iollows:
A group oI 2n squares produces a Iunction that always equal to logic 1
A group oI 2n1 squares represents a product term oI one literal
A group oI 2n2 squares represents a product term oI to literals and so on.
One square represents a minterm oI n literals
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KMap 2
esson Objectives:
In this lesson you will learn:
1 The diIIerence between prime implicants and essential prime implicants.
2 How to get a minimized POS Iunction using a Kmap.
How to minimize a combinational circuit that is not completely speciIied (has don't
care conditions).
How to make a 5 and variable Kmap given a truth table or a SOP representation.
DeIinitions/Notations:
A product term oI a Iunction is said to be an implicant
A Prime mplicant (PI) is a product term obtained by combining the maximum
possible number oI adiacent 1squares in the map.
II a minterm is covered only by one prime implicant then this prime implicant is said
to be an Essential Prime mplicant (EPI).
Examples: (see authorare version)
POS Simplification:
Until now we have derived simpliIied Boolean Iunctions Irom the maps in SOP Iorm.
Procedure Ior deriving simpliIied Boolean Iunctions POS is slightly diIIerent. Instead
oI making groups oI 1`s. make the groups oI 0`s
Since the simpliIied expression obtained by making group oI 1`s oI the Iunction (say
F) is always in SOP Iorm. Then the simpliIied Iunction obtained by making group oI
0`s oI the Iunction will be the complement oI the Iunction (i.e., F`) in SOP Iorm.
Applying DeMorgan`s theorem to F` (in SOP) will give F in POS Iorm.
Examples: (see authorare version)
Don`t are onditions:
In some cases, the Iunction is not speciIied Ior certain combinations oI input variables
as 1 or 0.
There are two cases in which it occurs:
1 The input combination never occurs.
2 The input combination occurs but we do not care what the outputs are in response
to these inputs.
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In both cases, the outputs are called as unspecified and the Iunctions having them are
called as incompletely speciIied Iunctions.
In most applications, we simply do not care what value is assumed by the Iunction Ior
unspeciIied minterms.
UnspeciIied minterms oI a Iunction are called as d4n't care c4nditi4ns. They provide
Iurther simpliIication oI the Iunction, and they are denoted by X`s to distinguish them
Irom 1`s and 0`s.
In choosing adiacent squares to simpliIy the Iunction in a map, the don`t care
minterms can be assumed either 1 or 0, depending on which combination gives the
simplest expression.
A don`t care minterm need not be chosen at all iI it does not contribute to produce a
larger implicant.
FiveVariable KMaps:
There are 2 minterms Ior a Boolean Iunction with fivevariables Hence, Five
variable map consists oI 32 squares.
It consists oI 2 Iourvariable maps. Variable A distinguishes between the two maps, as
indicated on the top oI the diagram. The leIthand Iourvariable map represents the 1
squares where A÷0. and the other Iourvariable map represents the squares where
A÷1
Minterms 0 through 1 belong to the Iourvariable map with A÷0 and minterms 1
through 1 belong to the Iourvariable map with A÷1
Each Iourvariable map retains the previously deIined adiacency when taken
separately. In addition, each square in the A0 map is adiacent to the corresponding
square in the A1 map. For example, minterm 4 is adiacent to minterm 20 and
minterm 15 to 31.
The best way to visualize this new rule Ior adiacent squares is to consider the two halI
maps as being one on top oI the other. Any two squares that Iall one over the other are
considered adiacent.
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SixVariable KMaps:
There are 4 minterms Ior a Boolean Iunction with sixvariables. Hence, Sixvariable
map consists oI 4 squares.
By Iollowing the procedure used Ior the Iivevariable map, it is possible to construct a
sixvariable map with 4 Iourvariable maps to obtain the required 4 squares.
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Universal Gates
esson Objectives:
In addition to AND, OR, and NOT gates, other logic gates like NAND and NOR are
also used in the design oI digital circuits.
The NOT circuit inverts the logic sense oI a binary signal.
The small circle (bubble) at the output oI the graphic symbol oI a NOT gate is
Iormally called a negation indicator and designates the logical complement.
The obiectives oI this lesson are to learn about:
1 Universal gates  NAND and NOR.
2 How to implement NOT, AND, and OR gate using NAND gates only.
How to implement NOT, AND, and OR gate using NOR gates only.
Equivalent gates.
Twolevel digital circuit implementations using universal gates only.
Twolevel digital circuit implementations using other gates.
NAND Gate:
The NAND gate represents the complement oI the AND operation. Its name is an
abbreviation oI NOT AND
The graphic symbol Ior the NAND gate consists oI an AND symbol with a bubble on
the output, denoting that a complement operation is perIormed on the output oI the
AND gate.
The truth table and the graphic symbol oI NAND gate is shown in the Iigure.
The truth table clearly shows that the NAND operation is the complement oI the
AND.
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NOR Gate:
The NOR gate represents the complement oI the OR operation. Its name is an
abbreviation oI NOT OR
The graphic symbol Ior the NOR gate consists oI an OR symbol with a bubble on the
output, denoting that a complement operation is perIormed on the output oI the OR
gate.
The truth table and the graphic symbol oI NOR gate is shown in the Iigure.
The truth table clearly shows that the NOR operation is the complement oI the OR.
Universal Gates:
A universal gate is a gate which can implement any Boolean Iunction without need to
use any other gate type.
The NAND and NOR gates are universal gates.
In practice, this is advantageous since NAND and NOR gates are economical and
easier to Iabricate and are the basic gates used in all IC digital logic Iamilies.
In Iact, an AND gate is typically implemented as a NAND gate Iollowed by an
inverter not the other way around!!
Likewise, an OR gate is typically implemented as a NOR gate Iollowed by an inverter
not the other way around!!
NAND Gate is a Universal Gate:
To prove that any Boolean Iunction can be implemented using only NAND gates, we
will show that the AND, OR, and NOT operations can be perIormed using only these
gates.
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mplementing an nverter Using only NAND Gate
The Iigure shows two ways in which a NAND gate can be used as an inverter (NOT
gate)
1 All NAND input pins connect to the input signal A gives an output A`
2 One NAND input pin is connected to the input signal A while all other input pins
are connected to logic 1 The output will be A`
mplementing AND Using only NAND Gates
An AND gate can be replaced by NAND gates as shown in the Iigure (The AND is
replaced by a NAND gate with its output complemented by a NAND gate inverter).
mplementing OR Using only NAND Gates
An OR gate can be replaced by NAND gates as shown in the Iigure (The OR gate is
replaced by a NAND gate with all its inputs complemented by NAND gate inverters).
Thus. the NAND gate is a universal gate since it can implement the AND. OR
and NOT functions
NAND Gate is a Universal Gate:
To prove that any Boolean Iunction can be implemented using only NOR gates, we
will show that the AND, OR, and NOT operations can be perIormed using only these
gates.
mplementing an nverter Using only NOR Gate
The Iigure shows two ways in which a NOR gate can be used as an inverter (NOT
gate)
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1 All NOR input pins connect to the input signal A gives an output A`
2 One NOR input pin is connected to the input signal A while all other input pins are
connected to logic 0 The output will be A`
mplementing OR Using only NOR Gates
An OR gate can be replaced by NOR gates as shown in the Iigure (The OR is
replaced by a NOR gate with its output complemented by a NOR gate inverter)
mplementing AND Using only NOR Gates
An AND gate can be replaced by NOR gates as shown in the Iigure (The AND gate is
replaced by a NOR gate with all its inputs complemented by NOR gate inverters)
Thus. the NOR gate is a universal gate since it can implement the AND. OR and
NOT functions
Equivalent Gates:
The shown Iigure summarizes important cases oI gate equivalence. Note that bubbles
indicate a complement operation (inverter).
A NAND gate is equivalent to an invertedinput OR gate.
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An AND gate is equivalent to an invertedinput NOR gate.
A NOR gate is equivalent to an invertedinput AND gate.
An OR gate is equivalent to an invertedinput NAND gate.
Two NOT gates in series are same as a buIIer because they cancel each other as A``
A.
Toevel mplementations:
We have seen beIore that Boolean Iunctions in either SOP or POS Iorms can be
implemented using 2Level implementations.
For SOP Iorms AND gates will be in the Iirst level and a single OR gate will be in the
second level.
For POS Iorms OR gates will be in the Iirst level and a single AND gate will be in the
second level.
Note that using inverters to complement input variables is not counted as a level.
We will show that SOP Iorms can be implemented using only NAND gates, while
POS Iorms can be implemented using only NOR gates.
This is best explained through examples.
Example 1: Implement the Iollowing SOP Iunction
F ÷ Z Y`Z `YZ
Being an SOP expression, it is implemented in 2levels as shown in the Iigure.
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Introducing two successive inverters at the inputs oI the OR gate results in the shown
equivalent implementation. Since two successive inverters on the same line will not
have an overall eIIect on the logic as it is shown beIore.
(see animation in authorware version)
By associating one oI the inverters with the output oI the Iirst level AND gate and the
other with the input oI the OR gate, it is clear that this implementation is reducible to
2level implementation where both levels are NAND gates as shown in Figure.
Example 2: Implement the Iollowing POS Iunction
F ÷ (Z) (Y`Z) (`YZ)
Being a POS expression, it is implemented in 2levels as shown in the Iigure.
Introducing two successive inverters at the inputs oI the AND gate results in the
shown equivalent implementation. Since two successive inverters on the same line
will not have an overall eIIect on the logic as it is shown beIore.
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(see animation in authorware version)
By associating one oI the inverters with the output oI the Iirst level OR gates and the
other with the input oI the AND gate, it is clear that this implementation is reducible
to 2level implementation where both levels are NOR gates as shown in Figure.
There are some other types oI 2level combinational circuits which are
NANDAND
ANDNOR,
NOROR,
ORNAND
These are explained by examples.
ANDNOR functions:
Example : Implement the Iollowing Iunction
= XZ + Y Z + XYZ or
F = + Y + Y
Since F` is in SOP Iorm, it can be implemented by using NANDNAND circuit.
By complementing the output we can get F. or by using AAA circuit as
shown in the Iigure.
It can also be implemented using AAO# circuit as it is equivalent to NAND
AND circuit as shown in the Iigure. (see animation in authorware version)
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ORNAND functions:
Example : Implement the Iollowing Iunction
= ( X + Z ).(Y + Z ).( X + Y + Z ) or
F = ( + )(Y + )( + Y + )
Since F` is in POS Iorm, it can be implemented by using NORNOR circuit.
By complementing the output we can get F. or by using AO#O# circuit as shown in
the Iigure.
It can also be implemented using O#AA circuit as it is equivalent to NOROR
circuit as shown in the Iigure. (see animation in authorware version)
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OR  NOR Gates
esson Objectives:
In addition to AND, OR, NOT, NAND and NOR gates, exclusiveOR (XOR) and
exclusiveNOR (XNOR) gates are also used in the design oI digital circuits.
These have special Iunctions and applications. These gates are particularly useIul in
arithmetic operations as well as errordetection and correction circuits.
XOR and XNOR gates are usually Iound as 2input gates. No multipleinput
XOR/XNOR gates are available since they are complex to Iabricate with hardware.
The obiectives oI this lesson are to learn about:
1. XOR gates and XNOR gates
2. Their properties oI operation and basic identities
3. Odd Iunction and Even Iunction
4. Parity generation and checking.
OR Gate:
The exclusiveOR (XOR), operator uses the symbol , and it perIorms the Iollowing
logic operation:
Y ÷ Y` ` Y
The graphic symbol and truth table oI XOR gate is shown in the Iigure.
The result is 1 only when either X is equal to 1 or Y is equal to 1, but not when both X
and Y are equal to 1.
NOR Gate:
The exclusiveNOR (XNOR), operator uses the symbol , and it perIorms the Iollowing
logic operation
Y ÷ Y ` Y` ÷ ( Y)`
The graphic symbol and truth table oI XNOR (Equivalence) gate is shown in the Iigure.
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The result is 1 when either both X and Y are 0`s or when both are 1`s. That is why this
gate is oIten reIerred to as the Equivalence gate.
The truth tables clearly show that the exclusiveNOR operation is the complement oI the
exclusiveOR.
This can also be shown by algebraic manipulation as Iollows:
(X Y)` (X Y` ¹ X` Y)`
(X Y`)` (X` Y)` (X` ¹ Y) (X ¹ Y`)
(XY ¹ X`Y`)
X Y
Properties of OR/NOR Operations:
1 ommutativity
A B B A, and
A BB A
2 Associativity
A (B C) (A B) C, and
A (B C) (A B) C
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Basic dentities of OR Operation:
Any oI the Iollowing identities can be proven using either truth tables or algebraically by
replacing the operation by its equivalent Boolean expression:
X 0X
X 1 X`
X X0
X X` 1
X Y` X` Y (X Y)` X Y
The Iigure provides a graphical presentation oI important XOR/XNOR rules and gate
equivalence.
Example:
Show that (A B) ( D) ÷ A B D
Proving the above identity is easier done using graphical equivalence between gates as
speciIied by the previous Iigure.
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The Iollowing Iigure shows a stepbystep approach starting by the logic circuit
corresponding to the leIthandside oI the identity and perIorming equivalent gate
transIormations till a circuit is reached that corresponds to the righthandside oI the
identity.
ODD Function:
As shown in the Kmap, Y Z ÷ 1. FF (if and onlv if) the number oI 1`s in the
input combination is 4dd.
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Likewise, A B D ÷ 1. FF the number oI 1`s in the input combination is 4dd.
In general, an exclusiveOR Iunction oI nvariables is an odd function which has a value
oI 1 FF the number oI 1`s in the input combination is 4dd, otherwise it has a value oI 0.
Since XOR gates are only designed with 2 inputs, the 3input XOR Iunction is
implemented by means oI two 2input XOR gates, as shown in Iigure.
EVEN Function:
The complement oI an odd Iunction is an even 1uncti4n. The even Iunction is equal to 1
when the number oI 1`s in the input combination is even.
The complement oI an odd Iunction (an even 1uncti4n is obtained by replacing the
output gate with an exclusiveNOR gate, as shown in Iigure.
Parity Generation and hecking:
ExclusiveOR Iunctions are very useIul in systems using parity bits Ior errordetection.
A parity bit is used Ior the purpose oI detecting errors during transmission oI binary
inIormation.
A parity bit is an extra bit included with a binary message to make the total number of
1`s in this message (including the parity bit) either odd or even
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The message, including the parity bit, is transmitted and then checked at the receiving
end Ior errors. An error is detected iI the checked parity does not correspond with the one
transmitted.
The circuit that generates the parity bit at the transmitter side is called a paritv generator.
The circuit that checks the parity at the receiver side is called a paritv checker.
As an example, consider a 3bit message to be transmitted together with an even parity
bit. The table shows the trut table 14r te even 5aritv generat4r.
The three bits, . Y. and Z. constitute the message and are the inputs to the even paritv
generator circuit whose output is the parity bit P.
For even parity, whenever the message bits (X, Y& Z) have an odd number oI 1`s, the
parity bit ! must be 1. Otherwise, ! must be 0.
ThereIore, ! can be expressed as a threevariable exclusiveOR Iunction:
P÷ Y Z
The logic diagram Ior the even parity generator circuit is shown in the Iigure.
The 4 bits (X, Y. Z & P are transmitted to their destination, where they are applied to a
paritvchecker circuit to check Ior possible errors in the transmission.
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Since the inIormation was transmitted with even parity, the received Iour bits must have
an even number oI 1`s.
The parity checker generates an error signal (C 1, whenever the received Iour bits have
an odd number oI 1`s.
The table below shows the trut table 14r te even5aritv cecker.
Obviously, the parity checker error output signal C is given by the Iollowing expression:
÷ Y Z P
The logic diagram oI the evenparity checker is shown in the Iigure.
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It is worth noting that the parity generator can also be implemented with the circuit oI this
Iigure iI the input ! is connected to logic0 and the output is marked with P. This is
because Z 0 Z, causing the value oI Z to pass through the gate unchanged.
The advantage oI this is that the same circuit can be used Ior both parity generation and
checking.
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ombinational ogic
esson Objectives
In this lesson, you will learn about
What are combinational circuits
Design procedure oI combinational circuits
Examples oI combinational circuit design
ombinational ircuits
Logic circuit can be classiIied into two types. Combinational circuit, which consists oI
logic gates whose outputs at any time are determined by combining the values oI the
applied inputs using logic operations, and sequential circuits, which will be studied later.
In combinational circuits, the output at any time is a direct Iunction oI the applied external
inputs (Figure 1). In other words,
Z F(X)
That is, the outputs depend only on present inputs. A combinational circuit can be
speciIied by a truth table.
Inputs X
Combinational
circuit
Outputs Z
Figure 1: ombinational ircuit
Design procedure
The design oI a combinational circuit starts Irom the speciIication oI the problem, which
leads to the truth table. Using the output values in the truth table, the logic equation Ior
output Iunction is Iound and simpliIied using K maps, or Algebraic manipulation or
computer base tools. The equation oI the output Iunctions, the corresponding circuit is
Iound. The process is shown in Figure
Circuit SpeciIication
Truth Table
Kmaps, Algebraic Manipulation. Computer based tools
Logic Diagram
Figure 2: Design Procedure
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Let us state these steps Iormally.
1) The Iirst step is to Iind the truth table Irom circuit speciIication. This involves two sub
steps.
The Iirst is to determine the required number oI inputs and outputs Irom the
speciIication or verbal description oI the problem. Then, assign a letter symbol to
each input.
Then, derive the truth table that deIines the required relationship between inputs
and outputs
2) Using the truth table, obtain the simpliIied Boolean expression Ior each output as a
Iunction oI the input variables. The simpliIied equations can then be obtained using
algebraic manipulation, Kmaps, or computerbased tools.
3) Once the simpliIied equations are Iound, the corresponding logic diagram can be
derived.
A practical design must consider constraints such as:
Number oI gates used.
Number oI gate inputs (Fanin).
Maximum number oI gates an output signal can drive (Fanout).
Speed (propagation delay) requirements.
Example 1
Design a combinational circuit that has 3bit input number and a single output (F). The
output signal F is speciIied as Iollows:
F 1 when the input number is less than (3)10
F 0 otherwise.
Implement F using only NAND gates
Let the three inputs be called X, Y, and Z. X is the most signiIicant variable and Z is the
least signiIicant variable. The output F goes high, that is, the output produces logic 1 value
iI the input is less than 011, equivalent to a decimal value oI three. This means that the
output will be logic one Ior input combinations 000, 001, and 010. For other input
combinations, which are 011 upto 111, the output is logic zero (see table 1).
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Dec. #
0
1
2
3
4
5
0
0
0
0
1
1
1
1
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
F
1
1
1
0
0
0
0
0
Table 1: nputs and outputs for example 1
Since SOP expressions are directly implementable as 2Level implementation oI NAND
gates, we consider the 1`s oI the Iunction as shown in the Kmap.
YZ 00 01 11 10
X
0
1
1
0
1
0
0
0
1
0
F = X' Y' + X' Z'
X`
Y`
F
X`
Z`
Figure : NANDNAND implementation for F ÷ ` Y` ` Z`
ode onverters
Code converters are circuits which translate inIormation Irom one binary code to
another.
The inputs to the circuit provide the bit combination belonging to the Iirst code,
while the outputs constitute the corresponding combination belonging to the second
code.
The combinational circuit perIorms the transIormation Irom one code to another.
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Inputs
Code Converter
Outputs
Figure : ode converter
Figure 4 shows the general structure oI a code converter, containing the inputs, the code
converter circuit, and the outputs. Consider, Ior example, a binary BCD to Excess3 code
converter
Example 2: BD to excess ode onverter
In this problem, the input is a BCD codeword. Since this is a 4bit code that represents a
decimal digit (0to9), there will be 4 input bits which will be represented by Iour input
variables A,B,C, and D. Output is a 4bit excess3 code (W, X, Y ,Z)
Having deIined the inputs and outputs, we proceed to build the truth table Ior this code
converter. The truth table, lists the values oI the output (that is the excess3 code) Ior all
possible combinations oI the binary code. Note that, these codes are codes Ior decimal
digits 09. In other words, even though the 4 bits oI the input can represent up to 1
diIIerent combinations, ONLY 10 combinations are used to represent the 10 decimal
digits.
Thus, a total oI input combinations are not likely to occur. Since these inputs will never
occur, we use Don`t cares Ior the corresponding output codes.
BD input Ex output
Decimal #
0
1
2
A
0
0
0
0
0
0
0
1
1
0
B
0
0
0
0
1
1
1
0
0
1
0
0
1
1
0
1
1
0
0
1
D
0
1
0
1
0
0
1
0
1
0
W
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
1
0
Y
1
0
0
1
1
0
1
1
0
0
Z
1
0
1
0
1
1
0
1
0
1
10  1 All other inputs
Table 2: truth table Ior BCD to excess3 code converter
Follo implementation procedure
As the procedure Ior simpliIication oI a Boolean Iunction suggests, we will minimize the
Iour output Iunctions using Kmaps. Thus we will be having Iour Kmaps, one Ior each
output Iunction. Each oI these Kmaps and the circuit are given in Iigure 5
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151
Digital Logic Design by Morris Mano 3rd Edition
A
W
B
X
C
Y
D
Figure : Kmaps and circuit for example 2
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
Z
152
Figure : Design for F.
Digital Logic Design by Morris Mano 3rd Edition
Example : BD to segment display controller
Let`s take another example. We will design a BCD to sevensegment decoder. BeIore
proceeding, let`s Iirst understand what a segment display is?
You might have noticed a digital watch, where the digits Irom 0 to 9 are displayed (see
Iigure ). These digits can be displayed using seven Light emitting diode segments (or
LED`s) arranged to look like digit as shown in the Iigure. By controlling which
segment is ON and which is OFF we can display illuminated patterns that correspond to
the 10 decimal digits 0 to 9. For example, digit can be displayed by illuminating all the
segments.
Figure : Numbers displayed in a digital atch
The obiective is to design a circuit that will take a BCD number as input, and produces the
control signals C0 to C which allow illuminating the corresponding segments in the 
segment display, as shown in Iigure .
cS
c4
c0
c6
c1
c2
c3
c0 c1 c2 c3 c4 cS c6
c0 c1 c2 c3 c4 cS c6
BCD to 7segment
decoder
A B C D
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Digital Logic Design by Morris Mano 3rd Edition
Thus, the input is a 4bit BCD digit A,B,C, and D; A being the most signiIicant while D
being the least signiIicant.
The seven segments, which are actually seven output signals, are numbered C0 to C that
control the illumination oI the segment display.
Each oI the segment is a LightEmitting Diode (LED) which is illuminated iI current
passes through it or dimmed iI no current passes through it. For example, digit zero can be
displayed by illuminating all the segments except segment C. Digit 1 can be displayed by
ONLY illuminating segments C1 and C2.
Having deIined the Iormat oI inputs and outputs, let us Iind out the truth table Ior this
circuit. In the truth table, each input BCD code and its corresponding segment output is
shown. The truth table assumes that a logic1 illuminates a segment while a logic0 turns
the segment oII.
BD input Outputs for segments
Decimal A B D 0 1 2
#
0
1
2
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
10 1 All other inputs 0 0 0 0 0 0 0
Table 3: Truth table Ior BCD to segment display converter
Even though the 4 bits oI the input can represent up to 1 diIIerent combinations, ONLY
10 input combinations representing the 10 decimal digits are considered Valid.
We will design the controller such that the Invalid Input combinations would turnoII all
segments. Thus all segments are turned oII Ior input codes beyond 1001.
Now we are ready to build the seven Kmaps, one Ior each output segment, as shown
below
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1 0 1 1
0 1 0 1
0 0 0 0
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Digital Logic Design by Morris Mano 3rd Edition
AB
CD
00
00
1
01
0
11 10
1 1
AB
CD
00
00
1
01
1
11 10
1 1
01
11
10
0
0
1
1
0
1
1
0
0
1
0
0
01
11
10
1
0
1
0
0
1
1
0
0
0
0
0
C0 A` C ¹ A` B D ¹B` C` D` ¹ A B` C`
C1 A` B` ¹ B` C` ¹ A` C` D` ¹ A` C D
AB
CD
00
01
11
10
00
1
1
0
1
01
1
1
0
1
11 10
1 0
1 1
0 0
0 0
CD
AB 00 01 11 10
00
01
11
10 1 1 0 0
C3 A` C D` ¹ A` B` C ¹ B` C` D` ¹ A B` C` ¹ A` B C` D
C2 A` B ¹ B` C` ¹ A` C` ¹ A` D
AB
CD
00
01
00
1
0
01
0
0
11 10
0 1
0 1
AB
CD
00
01
11
00
1
1
0
01
0
1
0
11 10
0 0
0 1
0 0
11
0 0 0 0
10
1 1 0 0
10
1 0 0 0
C4 A` C D` ¹ B` C` D`
C5 A` B C` ¹ A` C` D` ¹ A` B D` ¹ A B` C`
AB
CD
00
00
0
01
0
11 10
1 1
01
11
10
1
0
1
1
0
1
0
0
0
1
0
0
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C A` C D` ¹ A` B` C¹ A` B C` ¹ A B` C`
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Digital Logic Design by Morris Mano 3rd Edition
Adders  Subtractors
esson Objectives:
The obiectives oI this lesson are to learn about:
1 HalI adder circuit.
2 Full adder circuit.
Binary parallel adder circuit.
HalI subtractor circuit.
Full subtractor circuit.
alf Adder:
A al1 adder is an arithmetic circuit that is used to add two bits. The block
diagram oI HA is shown. It has two inputs and two outputs.
The inputs oI the HA are the 2 bits to be added; the augend, and addend. The output is
the result oI this addition, i.e. a sum bit (S) and a carry bit (C).
INPUTS OUTPUTS
Y S
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
The truth table oI HA is shown. The Boolean Iunctions Ior the two outputs can be
obtained Irom the truth table which are:
S = ( XY + X Y ) = X Y
C = XY
Thus, the HA can be implemented using one XOR gate and one AND gate as shown
in the Figure.
Full Adder:
A 1ull adder F is an arithmetic circuit that is used to add three bits. The block
diagram oI FA is shown. It has three inputs and two outputs.
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Digital Logic Design by Morris Mano 3rd Edition
The inputs oI the FA are the 3 bits to be added; the augend, addend, and carry Irom
previous lower signiIicant position. The output is the result oI this addition, i.e. a sum
bit (S) and a carry bit (C).
INPUTS OUTPUTS
Y Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
The truth table oI FA is shown. The simpliIied Boolean Iunctions Ior the two outputs
can be obtained Irom the truth table, which are:
S = X YZ + XY Z + X Y Z + XYZ
= X Y Z
C = XY + XZ + YZ
The Boolean Iunctions Ior the two outputs can be manipulated to simpliIy the circuit,
as shown below: (see animation in authorare version)
S = X YZ + XY Z + X Y Z + XYZ
= X Y Z
= ( X Y ) Z
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Digital Logic Design by Morris Mano 3rd Edition
C = XY + X Y Z + X YZ
= XY + Z ( X Y + X Y )
= XY + Z ( X Y )
Thus the Iull adder can be implemented using two halI adders and an OR gate as
shown in the Figure.
Binary Parallel Adder:
An nbit adder is a circuit which adds two nbits numbers, say, A and B.
In addition, an nbit adder will have another singlebit input which is added to the two
numbers called the carryin (Cin).
The output oI the nbit adder is an nbit sum (S) and a carryout (Cout) bit. The block
diagram oI the nbit adder is shown.
II all input bits oI the two numbers (A & B) are applied simultaneously in parallel, the
adder is termed a Parallel dder.
Consider the problem oI designing a 4bit binary parallel adder.
The total number oI inputs is 9, since the two numbers have 4bits each in addition to
the Cin bit. Using conventional techniques Ior design would require a truth table oI
29512 rows.
This causes the conventional design procedure to be unacceptable in this case.
Alternatively, the 4bit binary parallel adder can be designed using 4 Iull adders
connected incascade as shown in the Iigure.
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Digital Logic Design by Morris Mano 3rd Edition
That is the carrvout bit oI one Iull adder stage is used as carrvin input to the next
stage.
In general, an nbit binary parallel adder can be built out oI n Iull adders connected in
cascade.
Since a carry oI 1 may appear near the least signiIicant bit oI the adder and yet
propagate through many Iull adders to the most signiIicant bit, iust as a wave ripples
outward Irom a pebble dropped in a pond. That is why this parallel adder is also
called as ri55le carrv adder.
The disadvantage oI the ripplecarry adder is that it can get very slow when one needs
to add many bits.
The propagation delay oI this adder is Iairly long since under worst case conditions,
the carry has to propagate through all the stages as shown in the Iigure by red colored
path
This propagation delay is a limiting Iactor on the adder speed.
The signal Irom the input carry to the output carry propagates through an AND gate
and OR gate, which constitute two gate levels. II there are Iour Iull adders, the output
carry would have 2 x 4 levels Irom C0 to C4.
The total propagation time in this 4bit adder would be the propagation time in one
halI adder (which is the Iirst halI adder) plus eight gate levels.
(see animation in authorare version)
Assuming that all the diIIerent types oI gates have same propagation delay, say %, the
propagation delay oI adder can be generalized as 2n + 1 %, where n is the number oI
stages. In this example, n 4, so the delay is 2 x 4 + 1 % 9%
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Digital Logic Design by Morris Mano 3rd Edition
Since all other arithematic operations are implemented by successive additions, the
time consumed during addition process is very critical.
For Iast applications, a better design is required. The carrvl44kaead adder solves
this problem by calculating the carry signals in advance, based on the input signals.
It is expalined in the next lesson.
Appendix:
alf Subtractor:
A al1 subtract4r is an arithmetic circuit that subtracts two bits and produces their
diIIerence.
The block diagram oI halI subtractor is shown. The circuit has two inputs minuend
(X) and subtrahend (Y) and two output bits, one is the diIIerence bit (D) and the other
is the borrow bit (B).
It perIorms the operation X Y.
It should be noted that the weight oI the output borrow bit is 2, while the weight oI
the output diIIerence bit is ¹1.
INPUTS OUTPUTS
Y B D
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
0
The truth table oI the halI subtractor is shown. The Boolean Iunctions Ior the two
outputs can be obtained directly Irom the truth table as:
D = ( XY + X Y ) = X Y
B = X Y
Full Subtractor:
A 1ull subtract4r is a combinational circuit that perIorms a subtraction between two
bits, taking into account that a 1 may have been borrowed by a lower signiIicant bit.
The block diagram oI Iull subtractor is shown. The circuit has three inputs and two
outputs.
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Digital Logic Design by Morris Mano 3rd Edition
Input variables are minuend (X), subtrahend (Y), and previous borrow (Z); output
variables are diIIerence (D) and output borrow (B).
It perIorms the operation X Y Z.
It should be noted that the weight oI the output borrow bit is 2, while the weight oI
the output diIIerence bit is ¹1.
The truth table oI the Iull subtractor is shown.
NPUTS OUTPUTS
Y Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
B
0
1
1
1
0
0
0
1
D
0
1
1
0
1
0
0
1
The simpliIied Boolean Iunctions Ior the two outputs are:
D = X YZ + XY Z + X Y Z + XYZ
= X Y Z
B = X Y + X Z + YZ
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Digital Logic Design by Morris Mano 3rd Edition
arry ook Ahead Adders
esson Objectives:
The obiectives oI this lesson are to learn about:
1 Carry Look Ahead Adder circuit.
2 Binary Parallel Adder/Subtractor circuit.
BCD adder circuit.
Binary mutiplier circuit.
arry ook Ahead Adder:
In ri55le carrv adders, the carry propagation time is the maior speed limiting Iactor as
seen in the previous lesson.
Most other arithmetic operations, e.g. multiplication and division are implemented using
several add/subtract steps. Thus, improving the speed oI addition will improve the speed
oI all other arithmetic operations.
Accordingly, reducing the carry propagation delay oI adders is oI great importance.
DiIIerent logic design approaches have been employed to overcome the carry
propagation problem.
One widely used approach employs the principle oI carrv l44kaead solves this problem
by calculating the carry signals in advance, based on the input signals.
This type oI adder circuit is called as carrv l44kaead adder CL adder. It is based on
the Iact that a carry signal will be generated in two cases:
(1) when both bits Ai and Bi are 1, or
(2) when one oI the two bits is 1 and the carryin (carry oI the previous stage) is 1.
To understand the carry propagation problem, let`s consider the case oI adding two nbit
numbers and B.
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Digital Logic Design by Morris Mano 3rd Edition
The Figure shows the Iull adder circuit used to add the operand bits in the ith column;
namelv Ai & Bi and the carrv bit coming from the previous column (Ci ).
In this circuit, the 2 internal signals !i and i are given by:
!i = Ai Bi ........(1)
i = Ai B i ........(2)
The output sum and carry can be deIined as :
Si = !i Ci ........()
C i + = i + !i C i ....()
Ci is known as the carrv Cenerate signal since a carry (Ci¹1) is generated whenever i
1, regardless oI the input carry (Ci).
Pi is known as the carrv 5r45agate signal since whenever !i 1, the input carry is
propagated to the output carry, i.e., Ci¹1. Ci (note that whenever !i 1, i 0).
Computing the values oI !i and i only depend on the input operand bits (Ai & Bi) as
clear Irom the Figure and equations.
Thus, these signals settle to their steadvstate value aIter the propagation through their
respective gates.
Computed values oI all the Pi`s are valid one XORgate delay aIter the operands A and B
are made valid.
Computed values oI all the Gi`s are valid one ANDgate delay aIter the operands A and B
are made valid.
The Boolean expression oI the carry outputs oI various stages can be written as Iollows:
1 ÷ G0 P00
2 ÷ G1 P11 ÷ G1 P1 (G0 P00)
÷ G1 P1G0 P1P00
÷ G2 P22 ÷ G2 P2G1 P2P1G0 P2P1P00
÷ G P
÷ G PG2 PP2G1 PP2P1G0 PP2P1P00
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Digital Logic Design by Morris Mano 3rd Edition
In general, the ith. carry output is expressed in the Iorm i Fi (P`s, G`s , 0).
In other words, each carry signal is expressed as a direct SOP Iunction oI 0 rather than
its preceding carry signal.
Since the Boolean expression Ior each output carry is expressed in SOP Iorm, it can be
implemented in twolevel circuits.
The 2level implementation oI the carry signals has a propagation delay oI 2 gates, i.e.,
2t.
The 4bit carry lookahead (CLA) adder consists oI 3 levels oI logic:
First level: Generates all the P & G signals. Four sets oI P & G logic (each consists oI an
XOR gate and an AND gate). Output signals oI this level (P`s & G`s) will be valid aIter
1t.
Second level: The Carry LookAhead (CLA) logic block which consists oI Iour 2level
implementation logic circuits. It generates the carry signals (C1, C2, C3, and C4) as
deIined by the above expressions. Output signals oI this level (C1, C2, C3, and C4) will be
valid aIter 3t.
Third level: Four XOR gates which generate the sum signals (Si) (Si Pi Ci). Output
signals oI this level (S0, S1, S2, and S3) will be valid aIter 4t.
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Digital Logic Design by Morris Mano 3rd Edition
Thus, the 4 Sum signals (S0, S1, S2 & S3) will all be valid aIter a total delay oI 4t
compared to a delay oI (2n¹1) Ior Ripple Carry adders.
For a 4bit adder (n 4), the Ripple Carry adder delay is 9t.
The disadvantage oI the CLA adders is that the carry expressions (and hence logic)
become quite complex Ior more than 4 bits.
Thus, CLA adders are usually implemented as 4bit modules that are used to build larger
size adders.
Binary Parallel Adder/Subtractor:
The addition and subtraction operations can be done using an AdderSubtractor circuit.
The Iigure shows the logic diagram oI a 4bit AdderSubtractor circuit.
B3 A3 B2 A2 B1 A1 B0 A0
M
FA
C3
FA
C2
FA
C1
FA
C0
C4 S3 S2 S1 S0
The circuit has a mode control signal M which determines iI the circuit is to operate as an
adder or a subtractor.
Each XOR gate receives input M and one oI the inputs oI B, i.e., Bi. To understand the
behavior oI XOR gate consider its truth table given below. II one input oI XOR gate is
zero then the output oI XOR will be same as the second input. While iI one input oI
XOR gate is one then the output oI XOR will be complement oI the second input.
A B XOR
0
0
1
1
0
1
0
1
0
1
1
0
(see animation in authorare)
So when M ÷ 0. the output oI XOR gate will be Bi 0 Bi. II the Iull adders receive the
value oI B, and the input carry C0 is 0, the circuit perIorms A plus B
When M ÷ 1. the output oI XOR gate will be Bi 1 Bi. II the Iull adders receive the
value oI B`, and the input carry C0 is 1, the circuit perIorms A plus 1`s complement oI B
plus 1, which is equal to A minus B
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Digital Logic Design by Morris Mano 3rd Edition
BD Adder:
II two BCD digits are added then their sum result will not always be in BCD.
Consider the two given examples.
orrect: Result
is in BCD.
Wrong: Result is
not in BCD.
0110 ÷
0011 ÷
1001 ÷
0101 ÷
0111 ÷
1100 ÷ 12
In the Iirst example, result is in BCD while in the second example it is not in BCD.
Four bits are needed to represent all BCD digits (0 9). But with Iour bits we can
represent up to 1 values (0000 through 1111). The extra six values (1010 through 1111)
are not valid BCD digits.
Whenever the sum result is . it will not be in BCD and will require correction to get a
valid BCD result.
Z3 Z2 Z Z
Correction is done through the addition oI to the result to skip the six invalid values as
shown in the truth table by yello color.
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Digital Logic Design by Morris Mano 3rd Edition
Consider the given examples oI nonBCD sum result and its correction.
NonBD
BD correction
n BD
NonBD
BD correction
n BD
NonBD
BD correction
n BD
0101 ÷
0111 ÷
1100 ÷ 12
0110 ÷
1 0010 ÷ 1 2
1001 ÷
0110 ÷
1111 ÷ 1
0110 ÷
1 0101 ÷ 1
1001 ÷
1001 ÷
1 0010 ÷ 1
0110 ÷
1 1000 ÷ 1
BC adder is a circuit tat adds t4 BC digits in 5arallel and 5r4duces a su2 BC
digit and a carrv 4ut bit.
The maximum sum result oI a BCD input adder can be 19. As maximum number in BCD
is 9 and may be there will be a carry Irom previous stage also, so 9 ¹ 9 ¹ 1 19
The Iollowing truth table shows all the possible sum results when two BCD digits are
added.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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Digital Logic Design by Morris Mano 3rd Edition
0. CO Z3 Z2
Z Z
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
The logic circuit that checks the necessary BCD correction can be derived by detecting
the condition where the resulting binary sum is 01010 through 10011 (decimal 10
through 19).
It can be done by considering the shown truth table, in which the Iunction F is true when
the digit is not a valid BCD digit. It can be simpliIied using a 5variable Kmap.
But detecting values 1010 through 1111 (decimal 10 through 15) can also be done by
using a 4variable Kmap as shown in the Iigure.
Values greater than 1111, i.e., Irom 10000 through 10011 (decimal 1 through 19) can be
detected by the carry out (CO) which equals 1 only Ior these output values. So, F CO
1 Ior these values. Hence, is true when CO is true OR when (Z3 Z2 ¹ Z3 Z1) is true.
Thus, the correction step (adding 0110) is perIormed iI the Iollowing Iunction equals 1:
F CO ¹ Z3 Z2 ¹ Z3 Z1
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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Digital Logic Design by Morris Mano 3rd Edition
The circuit oI the BCD adder will be as shown in the Iigure.
Addend Augend
arry
out
O
bit binary
adder
arry
in
Z Z2 Z1 Z0
Output
carry
Detection
ircuit
0
Correction
Iactor
Addition result
in binary
0
bit binary
adder
S S2 S1 S0
The two BCD digits, together with the input carry, are Iirst added in the top 4bit binary
adder to produce the binary sum. The bottom 4bit binary adder is used to add the
correction Iactor to the binary result oI the top binary adder.
Note:
When the Output carry is equal to zero. the correction Iactor equals zero.
When the Output carry is equal to one. the correction Iactor is 0110.
The output carry generated Irom the bottom binary adder is ignored, since it supplies
inIormation already available at the outputcarry terminal.
A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The
output carry Irom one stage must be connected to the input carry oI the next higherorder
stage.
Binary Multiplier:
Multiplication oI binary numbers is perIormed in the same way as with decimal numbers.
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Digital Logic Design by Morris Mano 3rd Edition
The multiplicand is multiplied by each bit oI the multiplier, starting Irom the least
signiIicant bit.
The result oI each such multiplication Iorms a partial product. Successive partial products
are shiIted one bit to the leIt.
The product is obtained by adding these shiIted partial products.
Example 1: Consider an example oI multiplication oI two numbers, say A and B (2 bits
each), C x B.
The Iirst partial product is Iormed by multiplying the B1Bô by ô The multiplication oI
two bits such as ô and Bô produces a 1 iI both bits are 1; otherwise it produces a 0 like
an AND operation. So the partial products can be implemented with AND gates.
The second partial product is Iormed by multiplying the B1Bô by 1 and is shiIted one
position to the leIt.
(see animation in authorare)
The two partial products are added with two halI adders (HA). Usually there are more
bits in the partial products, and then it will be necessary to use FAs.
The least signiIicant bit oI the product does not have to go through an adder, since it is
Iormed by the output oI the Iirst AND gate as shown in the Figure.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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Digital Logic Design by Morris Mano 3rd Edition
A binary multiplier with more bits can be constructed in a similar manner.
Example 2: Consider the example oI multiplying two numbers, say A (3bit number) and
B (4bit number).
Each bit oI A (the multiplier) is ANDed with each bit oI B (the multipcand) as shown in
the Figure.
The binary output in each level oI AND gates is added in parallel with the partial product
oI the previous level to Iorm a new partial product. The last level produces the Iinal
product.
Since ÷ and ÷ . 12 (1 x AND gates and to bit ((1  1 bit adders are
needed to produce a product oI seven (1 + bits. Its circuit is shown in the Figure.
Note that 0 is applied at the most signiIicant bit oI augend oI Iirst 4bit adder because the
least signiIicant bit oI the product does not have to go through an adder.
Dr. Mohammed YousuI Khan (courtesy: Dr. Muhammad F. Mudawar)
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Digital Logic Design by Morris Mano 3rd Edition
Decoders and Encoders
Lesson Obiectives
In this lesson, we will learn about
4Decoders
4Expansion oI decoders
4Combinational circuit implementation with decoders
4Some examples oI decoders
4Encoders
4Maior limitations oI encoders
4Priority encoders
4Some examples oI ecnoders
Decoders
As its name indicates, a decoder is a circuit component that decodes an input code. Given
a binary code oI nbits, a decoder will tell which code is this out oI the 2n possible codes
(See Figure 1(a)).
n Inputs
nto2n
Decoder
0
1
2n1
Figure 1(a): A typical decoder
Thus, a decoder has n inputs and 2n outputs. Each oI the 2n outputs corresponds to one oI
the possible 2n input combinations.
n Inputs
nto2n
Decoder
2 n Outputs
Enable
Figure 1(b): A typical decoder
Figure 1(b) shows the block diagram oI a typical decoder, which has n input lines, and m
output lines, where m is equal to 2n. The decoder is called nto m decoder. Apart Irom
this, there is also a single line connected to the decoder called enable line. The operations
oI the enable line will be discussed in the Ilowing text.
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In general, output i equals 1 iI and only iI the input binary code has a value oI i.
Thus, each output line equals 1 at only one input combination but is equal to 0 at
all other combinations.
In other words, each decoder output corresponds to a minterm oI the n input
variables.
Thus, the decoder generates all oI the 2n minterms oI n input variables.
Example: 2to decoders
Let us discuss the operation and combinational circuit design oI a decoder by taking the
speciIic example oI a 2to4 decoder. It contains two inputs denoted by A1 and A0 and
Iour outputs denoted by D0, D1, D2, and D3 as shown in Iigure 2. Also note that A1 is the
MSB while A0 is the LSB.
D0 A1A0
A0
A1
2to4
Decoder
D1 A1A0
D2 A1A0
D3 A1A0
Figure 2: A 2to4 decoder without enable
Decimal # nput Output
A1 A0 D0 D1 D2 D
0
1
2
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Table 1: Truth table Ior 2to4 decoder
As we see in the truth table (table 1), Ior each input combination, one output line is
activa ted, that is, the output line corresponding to the input combination becomes 1,
while other lines remain inactive. For example, an input oI 00 at the input will activate
line D0. 01 at the input will activate line D1, and so on.
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Notice that, each output oI the decoder is actually a minterm resulting Irom a
certain combination oI the inputs, that is
4D0 A1 A0, ( minterm m0) which corresponds to input 00
4D1 A1 A0, ( minterm m1) which corresponds to input 01
4D2 A1 A0, ( minterm m2) which corresponds to input 10
4D3 A1 A0, ( minterm m3) which corresponds to input 11
This is depicted in Figures 2 where we see that each input combination will
inovke the corresponding output, where each output is minterm corresponding to
the input combination.
A1
A0
D0 A1A0
D1 A1A0
D2 A1A0
D3 A1A0
Figure 3: Implementation 2to4 decoder
The circuit is implemented with AND gates, as shown in Iigure 3. In this circuit we see
that the logic equation Ior D is A1/ A0/. D0 is A1/ A0, and so on. These are in Iact the
minterms being implemented. Thus, each output oI the decoder generates a minterm
corresponding to the input combination.
The ~enable¨ input in decoders
Generally, decoders have the 'enable¨ input .The enable input perroms no logical
operation, but is only responsible Ior making the decoder ACTIVE or INACTIVE.
4II the enable 'E¨
4is zero, then all outputs are zero regardless oI the input values.
4is one, then the decoder perIorms its normal operation.
For example, consider the 2to4 decoder with the enable input (Figure 4). The enable
input is only responsible Ior making the decoder active or inactive. II Enable E is zero,
then all outputs oI the decoder will be zeros, regardless oI the values oI A1 and A0.
However, iI E is 1, then the decoder will perIorm its normal operation, as is shown in the
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truth table (table 2). In this table we see that as long as E is zero, the outputs D0 to D3
will remain zero, no matter whatever value you provide at the inputs A1 A0, depicted by
two don`t cares. When E becomes 1, then we see the same behavior as we saw in the case
oI 2to4 decoder discussed earlier.
E
A 1
A 0
D 0
D 1
D2
D 3
Figure 4: Implementation 2to4 decoder with enable
Decimal Enable
value
nputs Outputs
E
0
A1
A0
D0
0
D1
0
D2
0
D
0
0
1
2
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Table 2: Truth table oI 2to4 decoder with enable
Example: to decoders
In a three to eight decoder, there are three inputs and eight outputs, as shown in Iigure 5.
A0 is the least signiIicant variable, while A2 is the most signiIicant variable.
The three inputs are decoded into eight outputs. That is, binary values at the input Iorm a
combination, and based on this combination, the corresponding output line is activated.
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D0 A2A1A0
D1 A2A1A0
A0
A1
A2
3to
Decoder
D2 A2A1A0
D3 A2A1A0
D4 A2A1A0
D5 A2A1A0
D A2A1A0
D A2A1A0
Enable
Figure 5: A 3to decoder with enable
Each output represents one minterm .
4For example, Ior input combination A2A1A0 001, output line D1 equals 1 while all
other output lines equal 0`s
4It should be noted that at any given instance oI time, one and only one output line
can be activated. It is also obvious Irom the Iact that only one combination is
possible at the input at a time, so the corresponding output line is activated.
Dec nputs Outputs
A2 A1 A0 D0 D1 D2 D D D D D
0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
Table 3: Truth table oI 3to decoder
Since each input combination represents one minterm, the truth table (table 3) contains
eight output Iunctions, Irom D0 to D seven, where each Iunction represents one and only
one minterm. Thus Iunction D0 is A2/ A1/ A0/. Similarly Iunction D is A A1A0. The
corresponding circuit is given in Figure . In this Iigure, the three inverters provide
complement oI the inputs, and each one oI the AND gates generates one oI the minterms.
It is also possible to add an Enable input to this decoder.
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Figure : Implementation oI a 3to decoder without enable
Decoder Expansion
It is possible to build larger decoders using two or more smaller ones.
For example, a to4 decoder can be designed with Iour 4to1 decoders and one
2to4 line decoder.
Example: Construct a 3to decoder using two 2to4 deocders with enable
inputs.
Figure shows how decoders with enable inputs can be connected to Iorm a larger
decoder. Two 2to4 line decoders are combined to build a 3to line decoder.
4The two least signiIncat bits (i.e. A1 and A0) are connected to both decoders
4Most signiIcant bit (A2) is connected to the enable input oI one decoder.
4The complement oI most signiIicant bit (A2) is connected to the enable oI the
other decoder.
4When A2 0, upper decoder is enabled, while the lower is disabled. Thus, the
outputs oI the upper decoder correspond to minterms D0 through D3.
4When A2 1, upper decoder is disabled, while the lower is enabled. Thus, the
outputs oI the lower decoder correspond to minterms D4 through D.
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Figure : Implementing a 3to decoder with two 2to4 decoders
Decoder design ith NAND gates
Some decoders are constructed with NAND rather than AND gates.
In this case, all decoder outputs will be 1`s except the one corresponding to the input
code which will be 0.
Decimal # nput Output
A1 A0 D0` D1` D2` D`
0
1
2
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
Table 4: Truth table oI 2to4 decoder with NAND gates
This decoder can be constructed without enable, similar to what we have seen in the
design oI decoder with AND gates, without enable. The truth table and corresponding
minters are given in table 4. Notice that the minters are in the complemented Iorm.
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Figure : A 2to4 decoder with Enable constructed with NAND gates.
Decimal Enable
value
nputs Outputs
E`
1
A1
A0
D0`
1
D1`
1
D2`
1
D`
1
0
1
2
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
Table 5: Truth table oI 2to4 decoder with Enable using NAND gates
A 2to4 line decoder with an enable input constructed with NAND gates is shown in
Iigure . The circuit operates with complemented outputs and enable input E` is also
complemented to match the outputs oI the NAND gate decoder. The decoder is enabled
when E` is equal to zero. As indicated by the truth table, only one output can be equal to
zero at any given time, all other outputs being equal to one. The output with the value oI
zero represents the minterm selected by inputs A1 and A0. The circuit is disabled when E`
is equal to one, regardless oI the values oI the other two inputs. When the circuit is
disabled, none oI the outputs are equal to zero, and none oI the minterms are selected.
The corresponding logic equations are also given in table 5.
ombinational circuit implementation using decoder
As known, a decoder provides the 2n minterms oI n input variables
Since any boolean Iunctions can be expressed as a sum oI minterms, one can use a
decoder to implement any Iunction oI n variables.
In this case, the decoder is used to generate the 2n minterms and an additional OR
gate is used to generate the sum oI the required minterms.
In this way, any combinational circuit with n inputs and m outputs can be
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implemented using an nto2n decoder in addition to m OR gates.
Remember, that
The Iunction need not be simpliIied since the decoder implements a Iunction using
the minterms, not product terms.
Any number oI output Iunctions can be implemented using a single decoder,
provided that all those outputs are Iunctions oI the same input variables.
Example: Decoder mplementation of a Full Adder
Let us look at the truth table (table ) Ior the given problem. We have two outputs, called
S, which stands Ior sum, and C, which stands Ior carry. Both sum and carry are Iunctions
oI X, Y, and Z.
Decimal
value
nput Output
Y Z S
0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Table : Truth table oI the Full Adder
The output Iunctions S & C can be expressed in sumoIminterms Iorms as Iollows:
4S (X,Y,Z) m (1,2,4,)
4C (X,Y,Z) m (3,5,,)
Looking at the truth table and the Iunctions in sum oI minterms Iorm, we observe that
there are three inputs, X, Y, and Z that correspond to eight minterms. This implies that a
3to decoder is needed to implement this Iunction. This implementation is given in
Figure 9, where the sum S is implemented by taking minterms 1, 2, 4, and and the OR
gates Iorms the logical sum oI minterm Ior S. Similarly, carry C is implemented by
taking logical sum oI minterms 3, 5, , and Irom the same decoder.
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3to
0
Decoder
1
S
Z
Y
20
21
2
3
X 22
4
5
C
Figure 9: Decoder implementation oI a Full Adder
Encoders
An encoder perIorms the inverse operation oI a decoder, as shown in Figure 10.
It has 2n inputs, and n output lines.
Only one input can be logic 1 at any given time (active input). All other inputs must
be 0`s.
Output lines generate the binary code corresponding to the active input.
2n Inputs
2nton
Encoder
n Outputs
Figure 10: A typical Encoder
Example: Octaltobinary encoder
We will use to3 encoder (Figure 11) Ior this problem, since we have eight inputs, one
Ior each oI the octal digits, and three outputs that generate the corresponding binary
number. Thus, in the truth table, we see eight input variables on the leIt side oI the
vertical lines, and three variables on the right side oI the vertical line (table ).
nputs
E E E E E E2 E1
Outputs
E0 A2 A1 A0
Decimal
ode
0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
Table : Truth table oI Octaltobinary encoder
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E0
Inputs
E1
E2
E3
E4
to
Encoder
A0
A1
3 Outputs
E5 A2
E
E
Figure 11: Octaltobinary encoder
Note that not all input combinations are valid.
Valid combinations are those which have exactly one input equal to logic 1 while all
other inputs are logic 0`s.
Since, the number oI inputs , Kmaps cannot be used to derive the output Boolean
expressions.
The encoder implementation, however, can be directly derived Irom the truth table
4Since A0 1 iI the input octal digit is 1 or 3 or 5 or , then we can write:
A0 E1 ¹ E3 ¹ E5¹ E
4Likewise, A1 E2 ¹ E3 ¹ E¹ E, and similarly
4A2 E4 ¹ E5 ¹ E¹ E
Thus, the encoder can be implemented using three 4 input OR gates.
Major imitation of Encoders
Exactly one input must be active at any given time.
II the number oI active inputs is less than one or more than one, the output will be
incorrect.
For example, iI E3 E 1, the output oI the encoder A2A1A0 111, which implies
incorrect output.
To Problems to Resolve
1. II two or more inputs are active at the same time, whof shouId fhe oufpuf be7
2. An output oI all 0's is generated in 2 cases:
4when all inputs are 0
4when E0 is equal to 1.
ow con fhis ombiquify be resoIved7
S4luti4n %4 Pr4ble2 1:
4Use a !rioritv Encoder which produces the output corresponding to the input with
higher priority.
4Inputs are assigned priorities according to their subscript value; e.g. higher subscript
inputs are assigned higher priority.
4In the previous example, iI E3 E 1, the output corresponding to E will be
produced (A2A1A0 110) since E has higher priority than E3.
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S4luti4n %4 Pr4ble2 2:
4Provide one more output signal J to indicate validitv oI input data.
4J 0 iI none oI the inputs equals 1, otherwise it is 1
Example: to2 Priority Encoders
Sixteen input combinations
Three output variables A1, A0, and V
V is needed to take care oI situation when all inputs are equal to zero.
Inputs Outputs
E
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
E2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
E1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
E0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
A0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
V
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Invalid
Input
Table : Truth table oI 4to2 Priority Encoder
In the truth table (table ), we have sixteen input combinations. In the output, we have
three variables. The variable V is needed to take care oI the situation where all inputs
are zero. In that case V is kept at zero, regardless oI the values oI A and A . This
combination is highlighted green. In all other cases, V is kept at 1, because at least one oI
the inputs is one.
When E0 is 1, the output combination oI A1 and A0 is 00. This combination is highlighted
blue.
Then we have two combinations highlighted yellow. In both these combinations, A1 and
A0 are 01. This is because in both these combinations E1 is 1, regardless oI the value oI
E0, and since E1 has higher subscript, the corresponding output value is 01.
This is Iollowed by Iour input combinations in pink. In these Iour combinations, the
output A1A0 is 10, since E2 is 1 in all these combinations, and E2 has the highest
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precedence compared to E0 and E1. Although E0 and E1 are also having a value oI one in
this set oI Iour combinations, but they do not have the priority.
Finally we have the last eight input combinations, whose output is 11. This is because E3
is the highest priority input, and it is equal to 1. Though the other inputs with smaller
subscripts, namely, E2, E1, and E0 are also having values oI one in some combinations,
but they do not have the priority.
The truth table can be rewritten in a more compact Iorm using don`t care conditions Ior
inputs as shown below in table 9.
Inputs Outputs
E E2 E1 E0 A1 A0 V
1 0 0 0 0 0
2
0
0
0
0
0
1
1
0
0
0 1
1 1
0
1
1
1
1
0 1
1 1
Table 9: Truth table oI 4to2 priority encoder (compact Iorm)
With 4 Input variables, the truth table must have 1 rows, with each row
representing an input combination.
With don`t care input conditions, the number oI rows can be reduced since rows with
don`t care inputs will actually represent more than one input combination.
Thus, Ior example, row # 3 represents 2 combinations since it represents the input
conditions E3 E2E1E00010 and 0011.
Likewise, row # 4 represents 4 combinations since it represents the input conditions
E3E2E1E00100, 0101, 0110 and 0111.
Similarly, row # 5 represents combinations.
Thus, the total number oI input combinations represented by the 5row truth table
1¹ 1¹ 2¹ 4 ¹ 1 input combinations.
Boolean Expressions Ior V, A1 and A0 and the circuit:
See next page:
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Figure 12: Equations and circuit Ior 4to2 priority encoder
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Multiplexers and Demultiplexers
In this lesson, you will learn about:
1.
3.
4.
Multiplexers
Combinational circuit implementation with multiplexers
Demultiplexers
Some examples
Multiplexer
A Multiplexer (see Figure 1) is a combinational circuit that selects one oI the 2n input
signals (D0, D1, D2, .., D2n1) to be passed to the single output line Y.
" How to select the input line (out oI the possible 2n input signals) to be passed to the
output line?
A Selection oI the particular input to be passed to the output is controlled by a set oI n
input signals called 'Select nputs` (S0, S1, S2, ..., Sn1).
Figure 1: Multiplexer
Example 1: 2x1 Mux
A 2x1 Mux has 2 input lines (D0 & D1) , one select input (S), and one output line (Y).
(see Figure 2)
IF S0,
Else (S1)
then Y D0
Y D1
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D0
MUX
Y
D1 S
Figure 2: A 2 1 Multiplexer
Thus, the output signal Y can be expressed as:
Y = S D0 + S D1
Example 2: 4x1 Mux
A 4x1 Mux has 4 input lines (D0, D1, D2, D3), two select inputs (S0 & S1), and one output
line Y. (see Figure 3)
F S1S000, then
F S1S001, then
F S1S010, then
F S1S011, then
Thus, the output signal Y can be expressed as:
minterm minterm minterm minterm
Y D0
Y D1
Y D2
Y D3
m0 m1 m2 m3
Obviously, the input selected to be passed to the output depends on the minterm
expressions oI the select inputs.
Figure : A 1 Multiplexer
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In General,
For MUXes with n select inputs, the output Y is given by
Y ÷ m0D0 m1D1 m2D2 . m2 n1D2n 1
Where mi ith minterm oI the Select nputs
Thus
2 n 1
Y = mi Di
Example : "uad 21 Mux
Given two 4bit numbers A and B, design a multiplexer that selects one oI these 2
numbers based on some select signal S. Obviously, the output (Y) is a 4bit number.
A 0
A 1 Q uad 21
A 2
A 3
B 0
MUX
Y 0
Y 1
Y 2
Y 3
B 1
B 2
B 3
S
Figure : "uad 2 1 Multiplexer
The 4bit output number Y is deIined as Iollows:
Y A F S0, otherise Y B
The circuit is implemented using Iour 2x1 Muxes, where the output oI each oI the Muxes
gives one oI the outputs (Yi).
ombinational ircuit mplementation using Muxes
Problem Statement:
Given a Iunction oI nvariables, show how to use a MUX to implement this Iunction.
This can be accomplished in one oI 2 ways:
Using a Mux with nselect inputs
Using a Mux with n1 select inputs
Method 1: Using a Mux with nselect inputs
n variables need to be connected to n select inputs. For a MUX with n select inputs, the
output Y is given by:
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Y ÷ m0D0 m1D1 m2 D2 m2n1D2n1
Alternatively,
2n 1
Y = mi Di
Where mi i minterm oI the Select nputs
The MUX output expression is a S&M of minterms expression Ior all minterms (mi)
which have their corresponding inputs (Di) equal to 1.
Thus, it is possible to implement any Iunction oI nvariables using a MUX with nselect
inputs by proper assignment oI the input values (Di ¦0 , 1}).
Y(Sn1 ... S1S0) minterms)
Example : Implement the Iunction F (A, B, C) 1, 3, 5, ) (see Figure 5)
Since number oI variables n 3, this requires a Mux with 3 select inputs, i.e. an x1 Mux
The most signiIicant variable A is connected to the most signiIicant select input S2 while
the least signiIicant variable C is connected to the least signiIicant select input S0 , thus:
S2 A, S1 B, and S0 C
For the MUX output expression (sum oI minterms) to include minterm 1 we assign D1 1
Likewise, to include minterms 3, 5, and in the sum oI minterms expression while
excluding minterms 0, 2, 4, and , the Iollowing input (Di) assignments are made
D1 D3 D5 D6 1
D0 D2 D4 D7 0
0
1
0
1
D0
D1
D2
D3
0
1
1
D4
D5
D
Y
F ( A ,B , C ) =
( 1 ,3 ,5 , )
0
D
S 2
S 1
S 0
A B C
Figure : mplementing function ith Mux ith n select inputs
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Method 2: Using a Mux with (n1) select inputs
Any nvariable logic Iunction can be implemented using a Mux with only (n1) select
inputs (e.g 4to1 mux to implement any 3 variable Iunction)
This can be accomplished as Iollows:
Express Iunction in canonical sumoIminterms Iorm.
Choose n1 variables to be connected to the mux select lines.
Construct the truth table oI the Iunction, but grouping the n1 select input variables
together (e.g. by making the n1 select variables as most signiIicant inputs).
The values oI Di (mux input line) will be 0, or 1, or nth variable or complement oI nth
variable oI value oI Iunction F, as will be clariIied by the Iollowing example.
Example : Implement the Iunction F (A, B, C) (1, 2, , ) (see Iigure )
This Iunction can be implemented with a 4to1 line MUX.
A and B are applied to the select line, that is
A ; S1, B ; S0
The truth table oI the Iunction and the implementation are as shown:
Figure : mplementing function ith Mux ith n1 select inputs
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Example : Consider the Iunction F(A,B,C,D)c(1,3,4,11,12,13,14,15)
This Iunction can be implemented with an to1 line MUX (see Figure )
A, B, and C are applied to the select inputs as Iollows:
A ; S2 , B ; S1, C ; S0
The truth table and implementation are shown.
Figure : mplementing function of Example
Demultiplexer
It is a digital Iunction that perIorms inverse oI the multiplexing operation.
It has one input line (E) and transmits it to one oI 2n possible output lines (D0, D1, D2, .,
D2n1). The selection oI the speciIic output is controlled by the bit combination oI n select
inputs.
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D0
D1
D2
D3
D4
Moving
Arm
E
D5
D 2n1
Figure : A demultiplexer
Example : A 1to line Demux
The input E is directed to one oI the outputs, as speciIied by the two select lines S1 and
S0.
D0 E iI S1S0 00 ; D0 S1` S0` E
D1 E iI S1S0 01 ; D1 S1` S0 E
D2 E iI S1S0 10 ; D2 S1 S0` E
D3 E iI S1S0 11 ; D3 S1 S0 E
A careIul inspection oI the Demux circuit shows that it is identical to a 2 to 4 decoder
with enable input.
E A 1
A0
D 0
D 1
D 2
D 3
Figure : A 1to line demultiplexer
For the decoder, the inputs are A1 and A0, and the enable is input E. (see Iigure 9)
For demux, input E provides the data, while other inputs accept the selection variables.
Although the two circuits have diIIerent applications, their logic diagrams are exactly
the same.
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Decimal Enable
value
nputs Outputs
E
0
A1
A0
D0
0
D1
0
D2
0
D
0
0
1
2
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Figure : Table for 1to line demultiplexer
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Magnitude Comparator
In this lesson you will learn about
1.Magnitude comparator
2.How to design a 4bit comparator
DeIinition
A magnitude comparator is a combinational circuit that compares two numbers A & B to
determine whether:
A B, or
A B, or
A · B
Inputs
First nbit number A
Second nbit number B
Outputs
3 output signals (GT, EQ, LT), where:
1. GT 1
2. EQ 1
3. LT 1
IFF A ~ B
IFF A B
IFF A · B
Note: Exactlv One oI these 3 outputs equals 1, while the other 2 outputs are 0`s
4bit magnitude comparator
Inputs: bits (A ; 4bits , B ; 4bits)
A and B are two 4bit numbers
Let A A3A2A1A0 , and
Let B B3B2B1B0
Inputs have 28 (25) possible combinations
Not easy to design using conventional techniques
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The circuit possesses certain amount oI regularity ; can be designed algorithmicallv.
Design oI the EQ output (A B) in 4bit magnitude comparator
DeIine Xi (Ai Bi)¹ (Ai / Bi /)
Thus Xi 1 IFF Ai Bi
Xi 0 IFF Ai Bi
i ÷0. 1. 2 and 3
Condition Ior A B
EQ÷1 (i.e., A÷B) IFF
1. A3B3 (X3 ÷ 1), and
2. A2B2 (X2 ÷ 1), and
3. A1B1 (X1 ÷ 1), and
4. A0B0 (X0 ÷ 1).
Thus, EQ÷1 IFF X3 X2 X1 X0 1. In other words, EQ X3 X2 X1 X0
Design oI the GT output (A B) 4bit magnitude comparator
II A3 ~ B3, then A ~ B (GT1) irrespective oI the relative values oI the other bits oI A &
B. Consider, Ior example, A 1000 and B 0111 where A ~ B.
This can be stated as GT1 iI A B/ ÷1
II A3 B3 (X3 1), we compare the next signiIicant pair oI bits (A2 & B2).
II A2 ~ B2 then A ~ B (GT1) irrespective oI the relative values oI the other bits oI A &
B. Consider, Ior example, A 0100 and B 0011 where A ~ B.
This can be stated as GT1 iI A2 B2/ ÷1
II A3 B3 (X3 1) and A2 B2 (X2 1), we compare the next signiIicant pair oI bits (A1
& B1).
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II A1 ~ B1 then A ~ B (GT1) irrespective oI the relative values oI the remaining bits A0
& B0. Consider, Ior example, A 0010 and B 0001 where A ~ B
This can be stated as GT1 iI 2A1 B1/ ÷1
II A3 B3 (X3 1) and A2 B2 (X2 1) and A1 B1 (X1 1), we compare the next pair
oI bits (A0 & B0).
II A0 ~ B0 then A ~ B (GT1). This can be stated as GT1 iI 21A0B0/÷1
To summarize, GT 1 (A ~ B) IFF:
1. A B/ ÷1. or
2. A2 B2/ ÷1. or
3. 2A1 B1/ ÷ 1. or
4. 21A0B0/ ÷1
In other words, GT ÷ A B/ A2 B2/ 2A1 B1/ 21A0B0/
Design oI the LT output (A · B) 4bit magnitude comparator
In the same manner as above, we can derive the expression oI the LT (A · B) output
T ÷ B A/ B2 A2/ 2B1 A1/ 21B0A0/
The gate implementation oI the three output variables (EQ, GT & LT) is shown in the
Iigure below.
A3
B3
A2
B2
A1
B1
A0
B0
A·B
A~B
AB
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ModiIication to the Design
The hardware in the comparator can be reduced by implementing only two outputs, and
the third output can be obtained using these two outputs.
For example, iI we have the LT and GT outputs, then the EQ output can be obtained by
using only a NOR gate, as shown in the Iigure below.
Thus, when both the GT and LT outputs are zeros, then the 3rd one (i.e. EQ) is a 1`
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MS Design Examples
lesson, you will see some design examples using MSI devices. These examples
are:
Designing a circuit that adds three 4bit numbers.
Design oI a 4to1 Decoder using Iive 2to4 Decoders with enable inputs.
Design oI a circuit that takes 2 unsigned 4bit numbers and outputs the larger oI
both.
Designing a 1bit adder using Iour 4bit adders.
Designing a 3bit excess3 code converter using a Decoder and an Encoder.
Designing a circuit that adds three 4bit numbers
Recall that a 4bit binary adder adds two binary numbers, where each number is oI 4 bits.
For adding three 4bit numbers we have:
Inputs
First 4bit number X X3X2X1X0
Second 4bit number Y Y3Y2Y1Y0
Third 4bit number Z Z3Z2Z1Z0
Outputs
The summation oI X, Y, and Z. How many output lines are exactly needed will be
discussed as we proceed.
To design a circuit using MSI devices that adds three 4bit numbers, we Iirst have to
understand how the addition is done. In this case, the addition will take place in two
steps, that is, we will Iirst add the Iirst two numbers, and the resulting sum will be added
to the third number, thus giving us the complete addition.
Apparently it seems that we will have to use two 4bit adders, and probably some extra
hardware as well. Let us analyze the steps involved in adding three 4bit numbers.
Step 1: Addition oI X and Y
A 4bit adder is required. This addition will result in a sum and a possible carry, as
Iollows:
X3X2X1X0
Y3Y2Y1Y0

C4 S3S2S1S0
Note that the input carry Cin 0 in this 4bit adder
Step 2: Addition oI S and Z
This resulting partial sum (i.e. S3S2S1S0) will be added to the third 4bit number Z3Z2Z1Z0
by using another 4bit adder as Iollows, resulting in a Iinal sum and a possible carry:
S3S2S1S0
Z3Z2Z1Z0

D4 F3F2F1F0
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where F3F2F1F0 represents the Iinal sum oI the three inputs X, Y, and Z. Again, in this
step, the input carry to this second adder will also be zero.
Notice that in Step 1, a carry C4 was generated in bit position 4, while in Step 2, another
carry D4 was generated also in bit position 4. These two carries must be added together
to generate the Iinal Sum bits oI positions 4 and 5 (F and F).
Adding C4 and D4 requires a halI adder. Thus, the output Irom this circuit will be six bits,
namely F5 F4 F3F2F1F0 (See Figure 1)
Figure 1: Circuit Ior adding three 4bit numbers
Design a 4to1 Decoder using Iive 2to4 Decoders with enable inputs
We have seen how can we construct a bigger decoder using smaller decoders, by taking
the speciIic example oI designing a 3to decoder using two 2to4 decoders. Now we
will design a 4to1 decoder using Iive 2to4 decoders.
There are a total oI sixteen possible input combinations, as shown in the table (Figure 2).
These sixteen combinations can be divided into Iour groups, each group containing Iour
combinations. Within each group, A3 and A2 remain constant, while A1 and A0 change
their values. Also, in each group, same combination is repeated Ior A1 and A0 (i.e.
00÷01÷10÷11)
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Figure 2: Combinations with 4 variables
Thus we can use a 2to4 decoder Ior each oI the groups, giving us a total oI Iour
decoders (since we have sixteen outputs; each decoder would give Iour outputs). To each
decoder, A1 and A0 will go as the input.
A IiIth decoder will be used to select which oI the Iour other decoders should be
activated. The inputs to this IiIth decoder will be A3 and A2. Each oI the Iour outputs oI
this decoder will go to each enable oI the other Iour decoders in the 'proper order¨.
This means that line 0 (representing A3A2 00) oI decoder 5` will go to the enable oI
decoder 1`. Line 1 (representing A3A2 01) oI decoder 5` will go to the enable oI
decoder 2` and so on.
Thus a combination oI A3 and A2 will decide which 'group¨ (decoder) to select, while the
combination oI A1 and A0 will decide which output line oI that particular decoder is to be
selected.
Moreover, the enable input oI decoder 5` will be connected to logic switch, which will
provide logic 1 value to activate the decoder.
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Figure 3: Constructing 4to1 decoder using 2to4 decoders
Decoder example: 'Activate¨ line D2. The corresponding input combination that
would activate this line is 0010. Now apply 00 at input oI decoder 5`. This activates line
0` connected to enable oI decoder 1`. Once decoder 1` is activated, inputs at A1A0
10 activate line D2.
Thus we get the eIIect oI a 41 decoder using this design, by applying input
combinations in two steps.
As another example, to 'activate¨ the line D10: The corresponding input combination is
1010. Apply 10 at the input oI decoder 5`. This activates line 2` connected to enable oI
decoder 3`. Once decoder 3` is activated, the inputs at A1A0 10 activate line D10.
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Given two 4bit unsigned numbers A and B, design a circuit which outputs
the larger oI the 2 numbers.
Here we will use Quad 21 Mux, and a 4bit magnitude comparator. Both oI these
devices have been discussed earlier. The circuit is given in the Iigure
Since we are to select one oI the two 4bit numbers A (A3A2A1A0) and B (B3B2B1B0), it
is obvious that we will need a quad 21 Mux.
The inputs to this Mux are the two 4bit numbers A and B.
The select input oI the Mux must be a signal which indicates the relative magnitude oI
the two numbers A and B. This signal may be True iI A·B or iI A~B.
Such signal is easily obtained Irom a 4bit magnitude comparator.
Figure 4: Circuit that outputs the larger oI two numbers
By connecting the select input to the A·B output oI the magnitude comparator, we must
connect A to the 0 input oI the Mux and B to the 1 input oI the Mux . Alternatively, iI we
connect the select input to the A~B output oI the magnitude comparator, we must connect
A to the 1 input oI the Mux and B the 0 input oI the Mux . In either case, the Mux output
will be the larger oI the two numbers
Designing a 1bit adder using Iour 4bit adders
Adds two 1bit numbers X (X0 to X15), and Y (Y0 to Y15) producing a 1bit Sum S (S0
to S15) and a carry out C1 as the most signiIicant position. Thus, Iour 4bit adders are
connected in cascade.
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Each adder takes Iour bits oI each input (X and Y) and generates a 4bit sum and a carry
that is Ied into the next 4bit adder as shown in Figure 5.
Figure 5: A 1bit adder
Designing an Excess3 code converter using a Decoder and an Encoder
In this example, the circuit takes a BCD number as input and generates the corresponding
Ex3 code. The truth table Ior this circuit is given in Iigure .
The outputs 0000, 0001, 0010, 1101, 1110, and 1111 are never generated (Why?)
To design this circuit, a 4to1 decoder and a 1to4 encoder are required. The design is
given in Iigure . In this circuit, the decoder takes 4 bits as inputs, represented by
variables w, x, y, and z. Based on these Iour bits, the corresponding minterm output is
activated. This decoder output then goes to the input oI encoder which is three greater
than the value generated by the decoder.
The encoder then encodes the value and sends the output bits at A, B, C, and D. For
example, suppose 0011 is sent as input. This will activate minterm 3 oI the decoder. This
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output is connected to input oI encoder. Thus the encoder will generate the
corresponding bit combination, which is 0110.
Figure : table Ior BCD to Ex3 conversion
Figure : Circuit Ior BCD to Ex3 conversion
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Sequential ircuits
Objective
In this lesson, you will learn about:
1. Sequential Circuits, Synchronous Sequential Circuits and Memory
Elements.
2. Clocked RS, D, JK, & T latches with their analysis.
3. Characteristic and excitation behavior oI these latches.
ntroduction
This is an introductory lesson on sequential logic circuits.
The general block diagram oI a combinational circuit is shown in Figure 1.
A Combinational logic circuit consists oI input variables (X), logic gates
(Combinational Circuit), and output variables (Z).
Figure 1: General Block Diagram of a ombinational ircuit
Unlike combinational circuits, sequential circuits include memory elements
(See Figure 2).
The memory elements are circuits capable oI storing binary inIormation.
The binary inIormation stored in these memory elements at any given time
deIines the state oI the sequential circuit at that time.
The outputs, Z. oI a sequential circuit depends both on the present inputs, .
and the present state Y (i.e., inIormation stored in the memory elements).
The next state oI the memory elements also depends on the inputs and the
present state Y
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Figure 2: General Block Diagram of a Sequential ircuit
Sequential Adder
To best understand sequential circuits, let`s revisit a known iterative circuit, a
4bit combinational ripple carry adder (See Figure 3).
The combinational circuit oI a 4bit ripple carry adder comprises 4Iull adders.
The inputs to the circuit are a singlebit carrvin (CIN) & two 4bit numbers A
& B. This circuit produces a 4bit sum S & a singlebit carrvout (COUT).
Figure : bit Ripplearry Adder
We can notice that all 4bits oI the sum are not computed at the same instance
oI time. The 1st stage produces the LSB oI the sum, S0, and an intermediate
carry C0 using CIN and the LSB oI A & B (A0, B0).
The 2nd stage, using the intermediate carry C0 along with A1 and B1, produces
the 2nd bit oI the sum, S1. In this way, the intermediate carry propagates
through the stages oI the adder & each stage, on the arrival oI this carry,
produces its corresponding bit oI Iinal sum S.
We observe that only one stage is active during the computation oI the sum.
Based on this observation, we can make an nbit adder using only one stage
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Iulladder as shown in Figure 4.
Figure : bit Sequential Adder
However, we need a singlebit memory element to temporarily store the value
oI the intermediate carry.
Two 4bit memory elements are used to store bitvectors A and B while a
singlebit memory element is used to store the intermediate carry.
As we have only one Iull adder, it will take Iour instances oI time to add the
corresponding bits oI A and B.
We notice here that the sequential adder has one memory element, which
stores the state oI the circuit as carry. These states deIine the condition oI
having a carry or no carry.
In other words, to deIine 2states (0 and 1) in a sequential circuit, we require 1
memory element. In general, Ior an nstate circuit we require 252nmemory
elements.
We also notice that to move Irom one state to another, we need a periodic
signal, which we called the lock. to synchronize the activity.
Synchronous & Asynchronous Sequential ircuits
There are two main types oI sequential circuits. Their classiIication depends
on the timing oI their signals.
Synchronous sequential circuits are systems whose behaviors can be deIined
Irom the knowledge oI their signals at discrete instants oI time.
While the behavior oI asynchronous sequential circuits depends upon the
order in which their input signals change at any instant oI time.
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Synchronous sequential logic systems must employ signals that aIIect the
memory elements only at discrete instants oI time.
To achieve this goal, a timing device called a masterclock generator is used to
generate a periodic train oI Clock pulses.
These clock pulses are distributed throughout the system in such a way that
memory elements are aIIected only with arrival oI the Clock pulse.
Memory Elements
A basic memory element, as shown in Figure 5 (a), is the latch
A latch is a circuit capable oI storing one bit oI inIormation.
The latch circuit consists oI two inverters; with the output oI one connected to
the input oI the other.
The latch circuit has two outputs, one Ior the stored value (Q) and one Ior its
complement (Q').
Figure 5 (b) shows the same latch circuit redrawn to illustrate the two
complementary outputs.
The problem with the latch Iormed by NOT gates is that we can't change the
stored value. For example, iI the output oI inverter B has logic 1, then it will
be latched Iorever; and there is no way to change this value.
Figure : Simple atch
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SR atch
Recall that a NOT gate can alternatively be expressed using NAND and NOR
gates as shown in Figure (a).
Using NOR gates, we can obtain the latch circuit shown in Figure (b).
This latch has two outputs, " and "'. and two inputs S and R
This type oI latches is sometimes called a crosscoupled SR latch or simply
SR latch.
Figure : (a) Alternative forms of NOT gate (b) Basic SR latch ith NOR gates
Table 1: Functional Table of the Basic SR atch ith NOR Gates
S R " "`
1
0
0
0
1
0
0
1
0
1
1
1
0
0
0
0
0
1
1
0
Set State
Reset State
UndeIined
The SR latch has two main states: set and reset (See Table 1).
When output "÷1 and "'÷0. the latch is said to be in the set state; and when
"÷0 and "'÷1. it is in the reset state
When the input S÷0 and R÷0. the SR latch remains in its current state (i.e. set
or reset). In this case, the values oI Q and Q' are latched Iorever.
When the SR latch is in the set state, we can change the state to the
reset state by making R1.
Similarly, the state oI the SR latch can be changed Irom reset to set by making
S1.
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II a 1 is applied to both inputs oI the SR latch, both outputs go to 0.
This produces an undeIined state, because it violates the requirement that the
outputs be complement oI each other.
It also results in an indeterminate next state when both inputs return to 0
simultaneously as shown in the Iigure.
In normal operation, these problems are avoided by making sure that 1's are
not applied to both inputs simultaneously.
SR atch ith NAND Gates
The SR latch with two crosscoupled NAND gates is shown in Figure .
It operates with both inputs normally at 1, unless the state oI the latch has to
be changed (See Table 2).
With both inputs at 1, applying 0 to the S input causes the output Q to go to 1
(i.e. set state)
In the same way, applying 0 to the R input causes the output Q to go to 0 (i.e.
reset state)
The condition that undefined Ior this NAND latch is when both inputs are
equal to 0 at the same time, which causes both outputs Q and Q` to go to 1.
Figure : Basic SR AT ith NAND Gates
Table 2: Functional Table of the Basic SR atch ith NAND Gates
S R " "`
0
1
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
1
1
0
Set State
Reset State
UndeIined
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locked SR atch
The operation oI the basic SR latch can be modiIied by providing an
additional control input (clock) that determines when the state oI the latch can
be changed.
An SR latch with a control input is shown in Figure .
It consists oI the basic SR latch with two additional AND gates.
The control input C acts as an enable signal to the latch (See Table 3).
When ÷0. the S and R inputs have no eIIect on the latch, so the latch will
remain in the same state regardless oI the values oI S and R.
When ÷1. the S and R inputs will have the same eIIect as in the basic SR
latch.
Figure : locked SR atch
Table : Functional Table of locked SR atch
S R
X X
Next State of "
No Change
1
1
1
1
0
0
1
1
0
0
0
1
No Change
Q 0; Reset State
Q 0; Set State
UndeIined
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haracteristic Table of the SR atch
The characteristic (behavior) oI the sequential circuit deIines its logical
property by speciIying the next states when the inputs and the present states
are known. The characteristic oI the RS latch is shown in Table 4.
The characteristic table can also be represented algebraically using what is
known as a characteristic equation
The characteristic equation is derived using the KMap as shown in Figure 9.
X`s mark the two indeterminate states in the map in Figure 9, since their
inputs are never allowed (Recall 'Don`t Cares¨).
Note that the condition S.R 0 must also be included as both S and R cannot
simultaneously be 1.
The characteristic equations are used in the analysis oI sequential circuits.
Table : haracteristic Table of SR atch
"(t) S R "(t 1)
0 0 0 0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Indeterminate
1
0
1
Indeterminate
Figure : haracteristic Equation of the SR atch
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Excitation Table of the SR atch
During the design process we usually know the transition Irom present state to
next state and wish to Iind the latch input conditions that will cause the
required transition.
For this reason, we need a table that lists the required inputs Ior a given
change oI state. Such a table is called an excitation table. and it speciIies the
excitation behavior oI the sequential circuits. These are used in the synthesis
(design) oI sequential circuits, which we shall see later.
The excitation oI the SR latch is given in Table 5.
Table : Excitaion table of the SR latch
"(t) "(t1) S R
0
0
0
1
0 X
1 0
1
1
0
1
0
X
1
0
locked Datch
One way to eliminate the undesirable undeIined state in the SR latch is to
ensure that the inputs S and R are never equal to 1 at the same time.
This is done in the D latch shown in Figure 10.
This latch has only two inputs D (Data) and (Clock). Note that D is applied
directly to the set input S, and its complement is applied to the reset input R.
Figure 10: locked D atch
As long as the clock input ÷ 0. the SR latch has both inputs equal to 0 and it
can`t change its state regardless oI the value oI D (See Table ).
When C is 1, the latch is placed in the set or reset state based on the value oI
D.
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II D ÷ 1. the " output goes to 1
II D ÷ 0. the " output goes to 0
The characteristic table and the characteristic equation oI a D latch are
illustrated in Table and Figure 11 respectively.
Table : Functional Table of the Datch
D Next State of "
0
1
1
X
0
1
No Change
Q 0; Reset State
Q 1; Set State
Table : haracteristic Table of the Datch
"(t) D "(t 1)
0
0
1
1
0
1
0
1
0
1
0
1
Figure 11: haracteristic Equation of the Datch
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locked 1Katch
The clocked JK latch is shown in Figure 12. Note the Ieedback path Irom the
outputs Q and Q` to the AND gates at the input.
JK latch is an improvement over the SR latch in the sense that it does not have
any indeterminate states.
Inputs J and K behave like S and R oI the SR latch. J and K set and clear the
state oI the latch, respectively.
Figure 12: locked 1Katch
The Iunctional table oI the clocked JKLatch is illustrated in Table .
II both J and K are made high (recall that both S and R cannot be made high at
the same time) then the latch switches to its complement state, that is, iI Q1
then it switches to Q0, and vice versa.
Output Q is ANDed with K and C inputs so that the latch is cleared during a
clock pulse only iI Q was previously 1.
Similarly, Q` is ANDed with J and C inputs so that the latch is set with a clock
pulse only iI Q` was previously 1.
The JK latch behaves exactly like the SR latch, except when both J and K are
1.
Characteristic table and characteristic equation oI the JKLatch are shown in
Table and Figure 13 respectively.
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Table : Functional Table of the locked 1Katch
1 K Next State of "
0
1
1
1
X
0
0
1
X
0
1
0
Q
Q
0
1
(No Change)
(No Change)
(#eset State)
(Set State)
1 1 1 Q` (Complement)
Table : haracteristic Table of the 1Katch
"(t)
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
K
0
1
0
1
0
1
0
1
"(t 1)
0
0
1
1
1
0
1
0
Figure 1: haracteristic Equation of the 1Katch
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Excitation table oI the JKLatch are illustrated in Table 9.
When both states, present and the next one are to be 0, then the J input must
remain at 0 and the K input can be either 0 or 1 (i.e., X).
Similarly, when both present state and the next state are 1, the K input must
remain at 0 while J input can be 0 or 1 (i.e., X).
II the latch is to have a transition Irom the 0state to 1state, J must be equal to
1 since the J input sets the latch. However, input K may be either 0 or 1.
Similarly, Ior a 1to0 transition, K must be set to 1 and J can be either 0 or a
1.
Table 10: Excitaion Table of the 1Katch
"(t)
0
0
1
1
"(t1)
0
1
0
1
1
0
1
X
X
K
X
X
1
0
locked Tatch
The T latch is a singleinput version oI the JK latch. It is obtained by tying
both the inputs J and K together as shown in Figure 14. The name comes Irom
the ability oI the latch to 'toggle¨ or change the state.
Figure 1: locked Tatch
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Observe that when T1, regardless oI the present state, the latch toggles or
changes to the complement state when the clock pulse occurs (See Table 11).
Table 11: Functional Table of the locked Tatch
T Next State of "
0
1
1
X
0
1
No Change
No Change
Q
The toggling eIIect can be seen more clearly in the characteristic behavior oI
the TLatch (See Table 12 and Figure 15). Notice that when T 0, the state oI
the latch remains unchanged.
Table 12: haracteristic Table of the Tatch
"(t) T "(t 1)
0
0
1
1
0
1
0
1
0
1
1
0
Figure 1: haracteristic Equation of the Tatch
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The excitation table oI the TLatch is illustrated in Table 12.
Note that when the state oI the latch must remain the same, the requirement is
that T 0. When the state oI the latch has to be complemented, T must equal
1, as summarized in the excitation table.
Table 1: Excitation Table of the Tatch
"(t) "(t 1) T
0
0
1
1
0
1
0
1
0
1
1
0
Problem ith the evel Triggered 1K and T latches
In JK latch, with J 1 and K 1 the state oI the latch toggles. However, iI the
clock signal remains at 1 (while J K 1), the output will go in repeated
transitions; this is an undesirable oscillating eIIect. And when clock goes to 0,
output will be latched to an unknown state.
To avoid this undesirable operation the clock pulse must have pulse duration,
which is shorter than the propagation delay oI the signal through the latch.
This however is not at all acceptable since the operation oI the circuit will then
depend on the width oI the clock pulse and/or the delay through the latch.
For this reason, JK latches are never constructed as discussed above. The
restriction on the pulse width can be eliminated with a masterslave or edge
triggered construction described in the next lesson. The same reasoning
applies to the T latch.
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FlipFlops
Objectives
The obiectives oI this lesson are to study:
1. Latches versus FlipFlops
2. MasterSlave FlipFlops
3. Timing Analysis oI MasterSlave FlipFlops
4. DiIIerent Types oI MasterSlave FlipFlops
5. Propagation Delay
Problem ith atches
A latch is a level sensitive device.
Because oI this the state oI the latch may keep changing in circuits with Ieedback as long
as the clock pulse remains active.
Thus, instead oI having output change once in a clock cycle, the output may change a
number oI times resulting in latching oI unwanted input to the output.
Due to this uncertainty, latches can not be reliably used as storage elements.
Solution to this Problem
To overcome this problem oI undesired toggling, we need to have a mechanism in which
we have higher degree oI control on the output oI the memory element when the clock
pulse changes.
This is achieved by introducing a special clockedge detection logic, such that the state oI
the memory element is switched by a momentary change in the clock pulse (i.e. an edge).
This is eIIective because the clock changes only once during a clock period.
Such a memory element is "edgesensitive", i.e., it changes its state at the rising or Ialling
edge oI a clock.
Edgesensitive memory elements are called FlipFlops.
Figure 1 shows the standard graphic symbols Ior positive and negative edge triggered
FlipFlops.
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Figure 1: Graphic Symbols of EdgeTriggered FlipFlops
MasterSlave FlipFlops
The simplest way to build a IlipIlop is by using two latches in a MasterSlave`
conIiguration as shown in Figure 2.
In this conIiguration, one latch serves as the master receiving the external inputs and the
other as a slave. which takes its inputs Irom the master.
When the clock pulse goes high, inIormation at S and R inputs is transmitted to master.
The slave IlipIlop however remains isolated since its control input C is 0.
Now when the clock pulse returns to 0`, the master gets disabled and blocks the external
inputs to get to its outputs whereas slave gets enabled and passes the latched inIormation
to its outputs.
Figure 2: Block diagram of SR MasterSlave FlipFlop
Timing Analysis of MasterSlave FlipFlop
Now let's view the operation oI the masterslave IlipIlop by analyzing its timing wave
Iorms (See Figure 3).
Consider a masterslave IlipIlop in the clear state (i.e. Y0 and Q0) prior to the
occurrence oI a pulse.
The inputs S1 and R0 are applied. So when the clock goes high, the output oI the
master latch will change to the set state, while the slave latch remains disabled.
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When the clock returns to 0, the master latch is disabled and the slave latch is enabled.
Thus, the data at the slave's input when the clock was high gets latched at the slave's
output.
Figure : Timing ave form of SR MasterSlave FlipFlop
Different Types of MasterSlave FlipFlops
MasterSlave 1KFF
The SR IlipIlop can be modiIied to a JK IlipIlop to eliminate the undesirable condition
that leads to undeIined outputs and indeterminate behavior.
A MasterSlave JK FlipFlop is shown in the Figure 4.
Here, the output gets complemented when both J and K inputs are high.
Figure : 1K MasterSlave FlipFlop
DType PositiveEdgeTriggered FF
The logic diagram oI a positive edge triggered Dtype IlipIlop is shown in the Figure 5.
This IlipIlop takes exactly the Iorm oI a masterslave IlipIlop, with the master a D latch
and the slave an SR latch. Also, an inverter is added to the clock input oI the master latch.
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Because the master latch is a D latch, the IlipIlop exhibits edgetriggered rather than
masterslave (pulsetriggered) behavior.
Figure : DType PositiveEdgeTriggered FF
Propagation Delay
In digital logic, every gate has got some Iinite amount oI delay because oI which the
change in the output is not instantaneous to the change in the input.
In simple terms, the times it takes Ior an input to appear at the output is called the
propagation delay.
In Figure , tP, describes the time it takes Ior an input to cause the output to change
Irom logiclevelhigh to logiclevellow.
Similarly, tP, reIers to the delay associated when an input change causes the output to
change Irom logiclevellow to logiclevelhigh.
The overall delay is average oI these two delays.
Figure : Propagation Delay
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Setup and old Times
For correct operation oI logic gates we need to satisIy some timing constrains regarding
application oI inputs and collecting oI their outputs.
Setup time (Ts) reIers to a constant duration Ior which the inputs must be held prior to the
arrival oI the clock transition (See Figure ).
Once the inputs are properly set, it must be kept Ior some time Ior their proper readingin
by the gate once the transition signal is triggered.
old time (Th) reIers to the duration Ior which the inputs must not change aIter the
arrival oI the transition (See Figure ).
II the setup and hold times are violated, a gate may produce an unknown logic signal at its
output. This condition is called as metastability
Figure : Setup and old Times
Propagation Delay
To set or clear IlipIlops asynchronously (i.e., without the use oI clock and inputs) some
IlipIlops have direct inputs usually called direct preset or direct clear
These inputs are needed to bring the IlipIlops to a known initial state prior to the normal
clocked operation.
A direct preset input, sets the output oI a IlipIlop to some known value, asynchronously,
Ior example logic1 or logic0.
A direct clear switch clears or resets all the IlipIlops to logic value0.
Figure shows the graphical symbol oI a negativeedgetriggered JKIlipIlop with a
direct clear.
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Figure : Negativeedgetriggered 1K FlipFlop ith Asynchronous lear
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Design of Synchronous Sequential ircuits
Objectives
1. Design oI synchronous sequential circuits with an example.
2. Construction oI state diagrams and state tables/
3. Translation oI State transition table into excitation table.
4. Logic diagram construction oI a synchronous sequential circuit
Sequential ircuit Design Steps
The design oI sequential circuit starts with verbal speciIications oI the problem (See
Figure 1).
Figure 1: Sequential ircuit Design Steps
The next step is to derive the state table oI the sequential circuit. A state table
represents the verbal speciIications in a tabular Iorm.
In certain cases state table can be derived directly Irom verbal description oI the
problem.
In other cases, it is easier to Iirst obtain a state diagram Irom the verbal description
and then obtain the state table Irom the state diagram.
A state diagram is a graphical representation oI the sequential circuit.
In the next step, we proceed by simpliIying the state table by minimizing the number
oI states and obtain a reduced state table.
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The states in the reduced state table are then assigned binarycodes. The resulting
table is called output and state transition table.
From the state transition table and using IlipIlop`s excitation tables, IlipIlops input
equations are derived. Furthermore, the output equations can readily be derived as
well.
Finally, the logic diagram oI the sequential circuit is constructed.
An example will be used to illustrate all these concepts.
Sequence Recognizer
A sequence recognizer is to be designed to detect an input sequence oI 1011`. The
sequence recognizer outputs a 1` on the detection oI this input sequence. The
sequential circuit is to be designed using JK and D type IlipIlops.
A sample input/output trace Ior the sequence detector is shown in Table 1.
Table 1: Sample nput/Output Trace
nput
Output
0
0
1
0
1
0
0
0
1
0
0
0
1
0
1
1
0
0
1
0
1
1
1
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
0
0
We will begin solving the problem by Iirst Iorming a state diagram Irom the verbal
description.
A state diagram consists oI circles (which represent the states) and directed arcs that
connect the circles and represent the transitions between states.
In a state diagram:
1. The number oI circles is equal to the number oI states. Every state is given a
label (or a binary encoding) written inside the corresponding circle.
2. The number oI arcs leaving any circle is 2n, where n is the number oI inputs oI
the sequential circuit.
3. The label oI each arc has the notation x/v. where x is the input vector that
causes the state transition, and v is the value oI the output during that present
state.
4. An arc may leave a state and end up in the same or any other state.
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BeIore we begin our design, the Iollowing should be noted.
1. We do not have an idea about how many states the machine will have.
2. The states are used to 'remember¨ something about the history oI past inputs.
For the sequence 1011, in order to be able to produce the output value 1 when
the Iinal 1 in the sequence is received, the circuit must be in a state that
'remembers¨ that the previous three inputs were 101.
3. There can be more than one possible state machine with the same behavior.
Deriving the State Diagram
Let us begin with an initial state (since a state machine must have at least one state)
and denote it with Sô' as shown in Figure 2 (a).
Two arcs leave state Sô' depending on the input (being a 0 or a 1). II the input is a 0,
then we return back to the same state. II the input is a 1, then we have to remember it
(recall that we are trying to detect a sequence oI 1011). We remember that the last
input was a one by changing the state oI the machine to a new state, say S1'. This is
illustrated in Figure 2 (b).
S1' represents a state when the last single bit oI the sequence was one. Outputs Ior
both transitions are zero, since we have not detected what we are looking Ior.
Again in state S1', we have two outgoing arcs. II the input is a 1, then we return to
the same state and iI the input is a 0, then we have to remember it (second number in
the sequence). We can do so by transiting to a new state, say S2'. This is illustrated
in Figure 2 (c).
Note that iI the input applied is 1`, the next state is still S1' and not the initial state
Sô'. This is because we take this input 1 as the Iirst digit oI new sequence. The
output still remains 0 as we have not detected the sequence yet.
State S2' represents detection oI 10` as the last two bits oI the sequence. II now the
input is a 1`, we have detected the third bit in our sequence and need to remember it.
We remember it by transiting to a new state, say S3' as shown in Figure 2 (d). II the
input is 0` in state S2' then it breaks the sequence and we need to start all over
again. This is achieved by transiting to initial state Sô'. The outputs are still 0.
In state S3', we have detected input sequence 101`. Another input 1 completes our
detection sequence as shown in Figure 2 (e). This is signaled by an output 1. However
we transit to state S1' instead oI Sô' since this input 1 can be counted as Iirst 1 oI a
new sequence. Application oI input 0 to state S3' means an input sequence oI 1010.
This implies the last two bits in the sequence were 10 and we transit to a state that
remembers this input sequence, i.e. state S2'. Output remains as zero.
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Figure 2: Deriving the State Diagram of the Sequence Recognizer
Deriving the State Table
A state table represents time sequence oI inputs, outputs, and states in a tabular Iorm.
The state table Ior the previous state diagram is shown in Table 2.
The state table can also be represented in an alternate Iorm as shown in Table 3.
Here the present state and inputs are tabulated as inputs to the combinational circuit.
For every combination oI present state and input, next state column is Iilled Irom the
state table.
The number oI IlipIlops required is equal to 252(number of states).
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Thus, the state machine given in the Iigure will require two IlipIlops 252(4)2. We
assign letters A and B to them.
Table 2: State Table of the Sequence Recognizer
Present
State
Next State
÷0 ÷1
Output
÷0 ÷1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
0
0
0
0
1
Table : Alternative Format of Table 2
nputs of
ombinational ircuit
Present State nput
Next State Output
S0
S0
S1
S1
S2
S2
S3
S3
0
1
0
1
0
1
0
1
S0
S1
S2
S1
S0
S3
S2
S1
0
0
0
0
0
0
0
1
State Assignment
The states in the constructed state diagram have been assigned symbolic names rather
than binary codes.
It is necessary to replace these symbolic names with binary codes in order to proceed
with the design.
In general, iI there are 2 states, then the codes must contain n bits, where 2n > 2, and
each state must be assigned a unique code.
There can be many possible assignments Ior our state machine. One possible
assignment is show in Table 4.
Table : State Assignment
State
S0
S1
S2
S3
ssign2ent
00
01
10
11
The assignment oI state codes to states results in state transition table as shown.
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It is important to mention here that the binary code oI the present state at a given time
t represents the values stored in the IlipIlops; and the nextstate represents the values
oI the IlipIlops one clock period later, at time t+1.
Table : State Transition Table
nputs of
ombinational ircuit
Present State nput
Next State Output
B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
B
0
1
0
1
0
1
0
1
Y
0
0
0
0
0
0
0
1
General Structure of Sequence Recognizer
The speciIications required using JK and D type IlipIlops.
ReIerring to the general structure oI sequential circuit shown in Figure 3, our
synthesized circuit will look like that as shown in the Iigure. Observe the Ieedback
paths.
Figure : General Structure of the Sequenc Recognizer
What remains to be determined is the combinational circuit which speciIies the
external outputs and the IlipIlop inputs.
The state transition table as shown can now be expanded to construct the excitation
table Ior the circuit.
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Since we are designing the sequential circuit using JK and D type IlipIlops, we need
to correlate the required transitions in state transition table with the excitation tables
oI JK and D typeIlipIlops.
The Iunctionality oI the required combinational logic is encapsulated in the excitation
table. Thus, the excitation table is next simpliIied using map or other simpliIication
methods to yield Boolean expressions Ior inputs oI the used IlipIlops as well as the
circuit outputs.
Deriving the Excitation Table
The excitation table (See Table ) describes the behavior oI the combinational portion
oI sequential circuit.
Table : Excitation Table of the Sequence Recognizer
Present
State
n5ut
Fli51l45s
n5uts
B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
B
0
1
0
1
0
1
0
1
Y
0
0
0
0
0
0
0
1
B
0 X 0
0 X 1
1 X 0
0 X 1
X 1 0
X 0 1
X 0 0
X 1 1
For deriving the actual circuitry Ior the combinational circuit, we need to simpliIy the
excitation table in a similar way we used to simpliIy truth tables Ior purely
combinational circuits.
Whereas in combinational circuits, our concern were only circuit outputs; in
sequential circuits, the combinational circuitry is also Ieeding the IlipIlops inputs.
Thus, we need to simpliIy the excitation table Ior both outputs as well as IlipIlops
inputs.
We can simpliIy IlipIlop inputs and output using Kmaps as shown in Figure 4.
Finally the logic diagram oI the sequential circuit can be made as shown in Figure 5.
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Figure : nput Equations of the Sequence Recognizer
Figure : ircuit Diagram of the Sequence Recognizer
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Analysis of locked Sequential ircuits
Objectives
The obiectives oI this lesson are as Iollows:
Analysis oI clocked sequential circuits with an example
State Reduction with an example
State assignment
Design with unused states
Unused state hazards
Figure 1: Sequential ircuit Design Steps
The behavior oI a sequential circuit is determined Irom the inputs, outputs and states oI its
IlipIlops.
Both the outputs and the next state are a Iunction oI the inputs and the present state.
Recall Irom previous lesson that sequential circuit design involves the Ilow as shown.
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Analysis consists oI obtaining a statetable or a statediagram Irom a given sequential circuit
implementation. In other words analysis closes the loop by Iorming statetable Irom a given
circuitimplementation.
We will show the analysis procedure by deriving the state table oI the example circuit we
considered in synthesis. The circuit is shown in Figure.
Figure 2: A locked sequential circuit
The circuit has
Clock input, CP.
One input x
One output v
One clocked JK IlipIlop
One clocked D IlipIlop (the machine can be in maximum oI 4 states)
A State table is representation oI sequence oI inputs, outputs, and IlipIlop states in a tabular
Iorm. Two Iorms oI state tables are shown (In this lesson, the second Iorm will be used).
Figure : State Table: Form 1
Analysis is the generation oI state table Irom the given sequential circuit.
The number oI rows in the state table is equal to 2 (number oI IlipIlops¹ number oI inputs). For the circuit
under consideration, number oI rows 2(2¹1) 2(3)
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Figure : State Table  Form 2
In the present case there are two IlipIlops and one input, thus a total oI rows as shown in
the table.
Figure : State Table
The analysis can start Irom any arbitrary state. Let us start deriving the state table Irom the
initial state 00.
As a Iirst step, the input equations to the IlipIlops and to the combinational circuit must be
obtained Irom the given logic diagram. These equations are:
JA BX`
KA BX ¹ B`X`
DB X
y ABX
The Iirst row oI the statetable is obtained as Iollows:
When input X 0; and present states A 0 and B 0 (as in the Iirst row);
then, using the above equations we get:
y 0, JA 0, KA 1, and DB 0.
The resulting state table is exactly same Irom which we started our design example. Thus
analysis is opposite to design and combined they act as a closed loop.
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State Reduction
The problem oI state reduction is to Iind ways oI reducing the number oI states in a
sequential circuit without altering the inputoutput relationships.
In other words, to reduce the number oI states, redundant states should be eliminated. A
redundant state Si is a state which is equivalent to another state Si.
Two states are said to be equivalent iI, Ior each member oI the set oI inputs, they give exactly
the same output and send the circuit either to the same state or to an equivalent state.
Since m` IlipIlops can describe a state machine oI up to 2m states, reducing the number oI
states may (or may not) result in a reduction in the number oI IlipIlops. For example, iI the
number oI states are reduced Irom to 5, we still need 3 IlipIlops.
However, state reduction will result in more don`t care states. The increased number oI don`t
care states can help obtain a simpliIied circuit Ior the state machine.
Consider the shown state diagram.
Figure : State Diagram
The state reduction proceeds by Iirst tabulating the inIormation oI the state diagram into its
equivalent statetable Iorm (as shown in the table)
The problem oI state reduction requires identiIying equivalent states. Each N states is
replaced by 1 state.
Consider the Iollowing state table.
States g` and e` produce the same outputs, i.e. '1' and 0`, and take the state machine to
same nextstates, a` and I`, on inputs 0` and 1` respectively. Thus, states 'g' and 'e' are
equivalent states.
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We can now remove state g` and replace it with e` as shown.
We next note that the above change has caused the states d` and I` to be equivalent. Thus in
the next step, we remove state I` and replace it with d`.
There are no more equivalent states remaining. The reduced state table results in the
Iollowing reduced state diagram.
Figure : State Table after reduction
States Assignment
When constructing a state diagram, variable names are used Ior states as the Iinal number oI
states is not known a priori.
Once the state diagram is constructed, prior to implementation (using gates and IlipIlops),
we need to perIorm the step oI 'state reduction'.
The step that Iollows state reduction is state assignment. In state assignment, binary patterns
are assigned to state variables.
Figure : Possible state assignments
For a given machine, there are several state assignments possible. DiIIerent state assignments
may result in diIIerent combinational circuits oI varying complexities.
State assignment procedures try to assign binary values to states such that the cost
(complexitv) oI the combinational circuit is reduced. There are several heuristics that attempt
to choose good state assignments (also known as state encoding) that try to reduce the
required combinational logic complexity, and hence cost.
As mentioned earlier, Ior the reduced state machine obtained in the previous example, there
can be a number oI possible assignments. As an example, three diIIerent state assignments
are shown in the table Ior the same machine.
We use adhoc state assignments in this lesson.
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Design ith unused states
There are occasions when a sequential circuit, implemented using m IlipIlops, may not
utilize all the possible 2m states
Figure : Reduced table ith binary assignments
In the previous example oI machine with 5 states, we need three IlipIlops. Let us choose
assignment 1, which is binary assignment Ior our sequential machine example (shown in the
table).
The unspeciIied states can be used as don`tcares and will thereIore help in simpliIying the
logic.
The excitation table oI previous example is shown. There are three states, 000, 110, and 111
that are not listed in the table under present state and input.
Figure 10: Excitation Table
With the inclusion oI input 1 or 0, we obtain six don`tcare minterms: 0, 1, 12, 13, 14, and 15.
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Figure 11: KMaps
The Kmaps oI SA and RA is shown in the Iigure. Other KMaps can be obtained similarly
and the equations derived are shown in the Iigure.
The logic diagram thus obtained is shown in the Iigure.
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Figure 12: ogic Diagram
Figure 1: Equations
Note that the design oI the sequential circuit is dependent on binary codes Ior states. A
diIIerent binary state codes set may have resulted in some diIIerent combinational circuit.
Unused States azard
Sequential circuits with unused states can cause the circuit to produce erroneous behavior.
This may happen when the circuit enters one oI the unused states due to some reason, e.g. due
to poweron, and continues cycling between the invalid states.
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Thus, a circuit that is designed must be careIully analyzed to ensure that it converges to some
valid state.
Consider the circuit oI the previous example that employed three unused states 000, 110 and
111. We will now investigate its behavior iI it enters in any oI these states.
The state diagram (Irom previous example) is shown in the Iigure. We will use the state
diagram to derive next state Irom each oI the unused states and derive the state table.
Figure 1: State Diagram
For instance, the circuit enters unused state 000.
On application oI input 0, ABCx 0000, Irom the equations (Iigure), we see that this
minterm is not included in any Iunction except Ior SC, i.e., the set input oI IlipIlop C and
output y.
Thus the circuit enters the state ABC 001 Irom the unused state 000 when input 0 is
applied.
On the other hand, iI the input applied is 1 then ABCx combination 0001. The maps
indicate that this minterm is included in the Iunctions Ior SB, RC and y.
ThereIore B will be set and C gets cleared.
So the circuit enters next state ABC 010 when input 1 is applied to unused state 000.
Note that both states 001 and 010 are valid states.
Similar analysis is carried out Ior all other unused states and the derived state diagram is
Iormed (shown in the Iigure).
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We note that the circuit converges into one oI the valid states iI it ever Iinds itselI in one oI
the invalid states 000, 110, and 111.
Such a circuit is said to be selIcorrecting, Iree Irom hazards due to unused states.
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Mealy and Moore Type Finite State Machines
Objectives
There are two basic ways to design clocked sequential circuits. These are
using:
1. Mealy Machine, which we have seen so Iar.
2. Moore Machine.
The obiectives oI this lesson are:
1. Study Mealy and Moore machines
2. Comparison oI the two machine types
3. Timing diagram and state machines
Mealy Machine
In a Mealy machine, the outputs are a Iunction oI the present state and the
value oI the inputs as shown in Figure 1.
Accordingly, the outputs may change asynchronously in response to any
change in the inputs.
Figure 1: Mealy Type Machine
Mealy Machine
In a Moore machine the outputs depend only on the present state as shown in
Figure 2.
A combinational logic block maps the inputs and the current state into the
necessary IlipIlop inputs to store the appropriate next state iust like Mealy
machine.
However, the outputs are computed by a combinational logic block whose
inputs are only the IlipIlops state outputs.
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The outputs change synchronously with the state transition triggered by the
active clock edge.
Figure 2: Moore Type Machine
omparison of the To Machine Types
Consider a Iinite state machine that checks Ior a pattern oI 10` and asserts
logic high when it is detected.
The state diagram representations Ior the Mealy and Moore machines are
shown in Figure 3.
The state diagram oI the Mealy machine lists the inputs with their associated
outputs on state transitions arcs.
The value stated on the arrows Ior Mealy machine is oI the Iorm Zi/Xi where
Zi represents input value and Xi represents output value.
A Moore machine produces a unique output Ior every state irrespective oI
inputs.
Accordingly the state diagram oI the Moore machine associates the output
with the state in the Iorm statenotation/outputvalue.
The state transition arrows oI Moore machine are labeled with the input value
that triggers such transition.
Since a Mealy machine associates outputs with transitions, an output sequence
can be generated in Iewer states using Mealy machine as compared to Moore
machine. This was illustrated in the previous example.
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Figure : Mealy and Moore State Diagrams for '10' Sequence Detector
Timing Diagrams
To analyze Mealy and Moore machine timings, consider the Iollowing
problem. A statemachine outputs 1` iI the input is 1` Ior three consecutive
clocks.
Figure : Mealy State Machine for '111' Sequence Detector
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Mealy State Machine
The Mealy machine state diagram is shown in Figure 4.
Note that there is no reset condition in the state machine that employs two Ilip
Ilops. This means that the state machine can enter its unused state 11` on start
up.
To make sure that machine gets resetted to a valid state, we use a Reset`
signal.
The logic diagram Ior this state machine is shown in Figure 5. Note that
negative edge triggered IlipIlops are used.
Figure : Mealy State Machine ircuit mplementation
Timing Diagram Ior the circuit is shown in Figure .
Since the output in Mealy model is a combination oI present state and input
values, an unsynchronized input with triggering clock may result in invalid
output, as in the present case.
Consider the present case where input x` remains high Ior sometime aIter
state AB 10` is reached. This results in False Output`, also known as
Output Glitch`.
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Figure : Timing Diagram for Mealy Model Sequence Detector
Moore State Machine
The Moore machine state diagram Ior 111` sequence detector is shown in
Figure .
The state diagram is converted into its equivalent state table (See Table 1).
The states are next encoded with binary values and we achieve a state
transition table (See Table 2).
Figure : Moore Machine State Diagram
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0
0
1
0
1
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Digital Logic Design by Morris Mano 3rd Edition
Table 1: State Table
Present
Present
Aext State
Aext State
Out5ut
Out5ut
State x 0 x 1
nitial
ot1
ot11
ot111
nitial ot1
nitial ot11
nitial ot111
nitial ot111
Table 2: State Transition Table and Output Table
Present Aext State Out5ut
State
nitial
ot1
ot11
ot111
x 0
nitial
nitial
nitial
nitial
x 1
ot1
ot11
ot111
ot111
0
0
We will use JK and D IlipIlops Ior the Moore circuit implementation. The
excitation tables Ior JK and D IlipIlops (Table 3 & 4) are reIerenced to
tabulate excitation table (See Table 5).
Table : Excitation Table for 1K flipflop
"t
0
0
1
1
"t+1
0
1
0
1
0
1
X
X
X
X
1
0
Table : Excitation Table for D flipflop
"t
0
0
1
1
"t+1
0
1
0
1
0
1
0
1
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Table : Excitation Table for the Moore mplementation
nputs of Outputs of
Comb.Circuits
!resent
State
Next
State
Comb.Circuit
lipflop
nputs
Output
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
B
0
1
0
0
0
1
0
1
0
0
0
1
X
X
X
X
X
X
X
X
1
0
1
0
B
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
SimpliIying Table 5 using maps, we get the Iollowing equations:
o .B
o '
o B + B
o .B
Note that the output is a Iunction oI present state values only.
The circuit diagram Ior Moore machine circuit implementation is shown in
Figure .
The timing diagram Ior Moore machine model is also shown in Figure 9.
There is no Ialse output in a Moore model, since the output depends only on
the state oI the Ilop Ilops, which are synchronized with clock. The outputs
remain valid throughout the logic state in Moore model.
Figure : Moore Machine ircuit mplementation for Sequence Detector
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Figure : Timing Diagram for Moore Model Sequence Detector
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Registers
In this lesson, you will learn about
Registers
Registers with Parallel load
ShiIt registers
ShiIt registers with Parallel Load
Bidirectional ShiIt Registers
Register
A register is a circuit capable oI storing data. In general, an nbit register consists oI n
FFs, together with some other logic that allows simple processing oI the stored data.
All FFs are triggered svnchronouslv by the same clock signal. In other words, new data
are latched into all FFs at the same time.
Figure 1 shows a 4bit register constructed with Iour Dtype FFs. In this Iigure we have:
Inputs D0 to D3
Clock
Clear/
Outputs Q0 to Q3
The Clock input is common to all the Iour D FFs. It triggers all FFs on the rising edge oI
each clock pulse, and the binary data available at the Iour D inputs are latched into the
register.
Figure 1: 4bit register with D IlipIlops
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The Clear/ input is an activelow asvnchronous input which clears the register
content to all 0`s when asserted low, independent oI the clock pulse.
During normal operation, Clear/ must be maintained at logic 1.
The transIer oI new inIormation into a register is reIerred to as Loading
The term Parallel Loading is used iI all the input bits are transIerred into the
register simultaneously, with the common clock pulse.
In most digital systems, a master clock generator supplies clock pulses to all parts oI the
system, iust as the heart that supplies a constant beat to all parts in the human system.
Because oI this Iact, the input values in the register are loaded when a clock pulse arrives.
This implies that, whenever a clock pulse arrives, it would load the register with new
values, thus overwriting the previously stored register data.
Because oI this, a problem arises:
Problem: hat if the contents of the register are to be left unchanged?
A Solution: The Clock may be prevented Irom reaching the clock input oI the FFs oI the
register.
; A separate control signal is used
Another Solution: Inputs D0 to D3 may be prevented Irom changing their values.
; A control signal is needed Ior this
Figure 2: Clock gating
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This control can be provided by implementing the Iollowing Iunction:
Cinputs Load / ¹ Clock
When Load 0 ; Cinputs 1, causing no positive transitions to occur on Cinputs. Thus
contents oI the register remain unchanged.
When Load 1 ; Cinputs Clock, thus the register is clocked normally.
The above phenomenon is known as lock gating (Figure 2).
Problem: DiIIerent stages oI the register will be gated at diIIerent time. This may cause
loading oI wrong inIormation ( known as clock ske)
Solution: Clock gating should be avoided.
Use register with !arallel Load. (Figure 3)
No clock gating is used.
Figure 3: One stage oI Register with Parallel Load
When Load 1, the data on the input Di is transIerred into the D IlipIlop with the next
positive transition oI clock pulse.
When Load 0, the data input is blocked, and output Qi gets a path to the D input oI the
IlipIlop.
hv do we need feedback connection from output to input of D?
Because DFF does not have a 'no change¨ input condition. Having the Ieedback
will cause the next state oI the FF (D input) to be equal to present state oI the FF,
i.e. n4 cange in state.
Note that there is no Clock gating. Load determines whether to accept new inIormation in
the next clock pulse or not.
A 4bit register with parallel load is shown.
Q. Can clocked latches be used instead of s to implement parallelload registers?
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Figure 4: ShiIt Registers
A shiIt register (Figure 4) is capable oI transIerring data Irom each FF to the next in one
or the other direction. Each clock pulse causes data shiIt Irom one FF to its immediate
neighbor.
The conIiguration consists oI a chain oI FFs in cascade, with the output oI one FF
connected to the input oI the next one.
All FFs receive a common pulse, which activates the shiIt operation Irom each stage to
the next.
The serial input SI is the input to the Iirst (leItmost) FF oI the chain.
The serial output SO is the output oI the last (rightmost) FF oI the chain.
The register discussed above is a 'shiIt right¨ (MS to LS shiIting) register. There is also a
'shiIt leIt¨ (LS to MS shiIting) register. (Figure 4)
Q: Can clocked latches be used instead oI FFs to implement shiIt registers?
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Figure 5: One stage oI a shiIt register with parallel load
A shiIt register with parallel load capability can be used to input the data bits in parallel
into the shiIt register and then take the data out in a serial Iashion by applying the shiIt
operation.
Such a register can act as a paralleltoserial converter, where data can be loaded in
parallel and shiIted out serially (bitbybit)
It can also act as a serialtoparallel converter, where data can be shiIted in serially (bit
bybit) and the output made available in parallel aIter shiIting is complete.
Figure 5 shows a typical stage oI a shiIt register with parallel load. There are two control
signals: ShiIt and Load. A table showing the operation oI the register with respect to the
ShiIt and Load inputs is also shown in the Iigure.
II ShiIt 0 and Load 0, red AND gate is enabled, causing the output oI the IlipIlop to
Ieed back to its D input.
A positive transition in the clock loads this input value into the FF;No hange state.
Load condition: II ShiIt 0 and Load 1, the green AND gate is enabled. This causes
the Di input to propagate to its input oI the D IlipIlop.
A positive transition oI the clock pulse transIers the input data into the FFs;
ShiIt condition: II ShiIt 1 while Load 0 or 1, the blue AND gate is enabled, while the
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other two AND gates are disabled.
A positive transition oI the clock pulse causes the shiIt operation. That is, the blue
AND gate takes the input Irom output Qi1 oI previous IlipIlop. This is true Ior all
stages except Ior the Iirst stage, where, instead, serial input SI is provided
Bidirectional Shift Register (BDSR)
Design a 3bit shiIt register which has 4 operating modes. The operating modes are
deIined by the status oI two select lines S1 and S0. The given table speciIies the values oI
S1 and S0 and its corresponding operating mode.
Table 1: Modes oI BDSR
The design uses 3 stages, where each stage consists oI a single multiplexer and a single
DFF.
The output oI each MUX is connected to the input oI corresponding D FF.
The MUX select inputs are connected to S1 and S0 to pass the proper signal to the DFF
input depending on the mode oI operation.
When S1 S0 00, input 0 oI the MUX is selected. This Iorms a path Irom the output oI
the FF into its own input, which causes the same value to be loaded in the D FF when a
clock pulse is applied. This results in the NO CHANGE operation.
When S1 S0 01, input 1 oI the MUX is selected. This Iorms a path Irom the lower
signiIicant to higher signiIicant bit, resulting in the SHIFT LEFT (i.e. LSB to MSB)
operation.
The serial input SI is transIerred into the rightmost bit in this case.
When S1 S0 10, input 2 oI the MUX is selected. This Iorms a path Irom the higher
signiIicant bit to lower signiIicant bit, resulting in SHIFT RIGHT (i.e. MSB to LSB)
operation.
The serial input SI is transIerred into the leItmost bit (i.e. MSB) in this case.
Finally, when S1 S0 11, input 3 oI the MUX is selected. On this input, the binary
inIormation on the parallel input line Di is transIerred into the FF, resulting in
PARALLEL LOAD operation.
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Figure : Bidirectional shiIt register
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ounters
In this lesson, the operation and design oI Synchronous Binary Counters will be studied.
Synchronous Binary ounters (SB)
Description and Operation
In its simplest Iorm, a svnchronous binarv counter (SBC) receives a train oI clock pulses
as input and outputs the pulse count (Qn1 .. Q2 Q1 Q0).
An example is a 3bit counter that counts Irom 000 upto 111. Each counter consists oI a
number oI FFs. (Figure 1)
Figure 1: 3bit SBC
In svnchronous counters, all FFs are triggered by the same input clock.
An nbit counter has ns with 2n distinct states. where each state corresponds to a
particular count.
Accordingly, the possible counts oI an nbit counter are 0 to (2n1). Moreover an nbit
counter has n output bits (Qn1 .. Q2 Q1 Q0).
AIter reaching the maximum count oI (2n1), the Iollowing clock pulse resets the count
back to 0.
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Thus, a 3bit counter counts Irom 0 to and back to 0. In other words, the output count
actually equals (Total of input pulses Modulo 2n).
Accordingly, it is common to identiIy counters by the modulus 2n. For example, a 4bit
counter provides a modulo 1 count, a 3bit counter is a modulo counter, etc.
ReIerring to the 3bit counter mentioned earlier, each stage oI the counter divides the
Irequency by 2, where the last stage divides the Irequency by 2n, n being the number oI
bits. (Figure 2)
Figure 2: 3bit SBC
Thus, iI the Irequency (i.e. no. oI cycles/ sec) oI clock is F, then the Irequency oI output
waveIorm oI Q0 is F/2, Q1 is F/4, and so on. In general, Ior nbit counter, we have F/2n.
Design of Binary ounters (SB)
Design procedure is the same as Ior other synchronous circuits.
A counter may operate without an external input (except Ior the clock pulses!)
In this case, the output oI the counter is taken Irom the outputs oI the IlipIlops without
any additional outputs Irom gates.
Thus, there are no columns Ior the input and outputs in the state table; we only see the
current state and next state.
Example Design a bit SB using 1K flipflops
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The counter has 4 FFs with a total oI 1 states, (0000 to 1111) 4 state variables Q3 Q2
Q1 Q0 are required.
Figure 3: State table Ior the example
Notice that the next state equals the present state plus one.
To design this circuit, we derive the IlipIlop input equations Irom the state transition
table. Recall that to Iind J & K values, we have to use:
The present state,
The next state, and
The JK IlipIlop excitation table.
When the count reaches 1111, it resets back to 0000, and the count cycle is repeated.
Once the J and K values are obtained, the next step is to Iind out the simpliIied input
equations by using Kmaps, as shown in Iigure 4.
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Digital Logic Design by Morris Mano 3rd Edition
Figure 4: Kmaps Ior the example
Notice that the maps Ior JQ0 and KQ0 are not drawn because the values in the table Ior
these two variables either contain 1`s or X`s. This will result in JQ0 KQ0 1
Note that the Boolean equation Ior J input is the same as that oI the K input Ior all the
FFs ; Can use TFFs instead oI JKFFs.
Count Enable Control
In many applications, controlling the counting operation is necessary ; a countenable
(En) is required.
f En 1 then counting oI incoming clock pulses is enabled Else if (En 0), no incoming
clock pulse is counted.
To accommodate the enable control, two approaches are possible.
1. Controlling the clock input oI the counter
2. Controlling FF excitation inputs (JK, T, D, etc.).
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Digital Logic Design by Morris Mano 3rd Edition
lock ontrol
Here, instead oI applying the system clock to the counter directly, the clock is Iirst
ANDed with the En signal.
Even though this approach is simple, it is not recommended to use particularly with
conIigurable logic, e.g. FPGA`s.
FF nput ontrol (Figure )
In this case, the En 0 causes the FF inputs to assume the no change value (SR00,
JK00, T0, or DiQi).
To include En, analyze the stage when JQ1 KQ1 Q0, and then include En. Accordingly,
the FF input equations oI the previous 4bit counter example will be modiIied as Iollows:
JQ0 KQ0 1. EN En
JQ1 KQ1 Q0. En
JQ2 KQ2 Q1.Q0. En
JQ3 KQ3 Q2.Q1.Q0. En
Figure 5: FF input control in counter
Thus, when En 0, all J and K inputs are equal to zero, and the Ilip Ilops remain in the
same state, even in the presence oI clock pulses
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When En 1, the input equations are the same as equations oI the previous example.
A carry output signal (CO) is generated when the counting cycle is complete, as seen in
the timing diagram.
The CO can be used to allow cascading oI two counters while using the same clock Ior
both counters. In that case, the CO Irom the Iirst counter becomes the En Ior the second
counter. For example, two modulo1 counters can be cascaded to Iorm a modulo25
counter.
UpDown Binary Counters
In addition to counting up, a SBC can be made to count down as well.
A control input, S is required to control the direction oI count.
IF S 1, the counter counts up, otherwise it counts down.
FF nput ontrol
Design a Modulo updown counter with control input S, such that iI S 1, the counter
counts up, otherwise it counts down. Show how to provide a count enable input and a
carryout (CO) output. (See Iigures & )
Figure : State diagram Ior FF input control example
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Figure : State table Ior FF input control example
The equations are (see Iigure )
T0 1
T1 Q0. S ¹ Q0. S
T2 Q1.Q0. S ¹ Q1. Q0. S
The carry outputs Ior the next stage are: (see Iigure )
Cup Q2.Q1.Q0 Ior upward counting.
Cdown Q2.Q1.Q0 Ior downward counting.
The equations with En are (see Iigure 9)
T0 En. 1
T1 Q0. S. En ¹ Q0. S. En
T2 Q1.Q0. S. En ¹ Q1. Q0. S. En
The carry outputs Ior the next stage, with En are (see Iigure 9):
Cup Q2.Q1.Q0. En Ior counting up.
Cdown Q2.Q1.Q0. En Ior counting down.
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Figure : Circuit oI updown counter
Figure 9: Circuit oI updown counter with En
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More on ounters
In this lesson, you will learn
some important counter control inputs:
o Parallel Load (Ld)
o Synchronous Clear
o Asynchronous Clear
use oI available counters to build counters oI diIIerent count
ounter ontrol
We have seen how to include a countenable control input to enable/disable counting in
the counter.
Now we show how to include important counter control inputs; namely:
Parallel Load (Ld)
Clear (Synchronous/Asynchronous)
The block diagram oI a 4bit counter with the above capabilities is shown in Figure 1.
Figure 1: A 4bit counter
Let us now discuss the design oI the counter. We will start with a typical stage oI basic
counter, and will add the control signals to this stage in a stepwise approach. A positive
edgetriggered counter will be assumed.
Figure 2 shows a stage oI the basic counter, where we see that the J and K inputs oI Ilip
Ilop at stage 1 are connected to an AND gate with Q0 and Count as inputs.
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Figure 2: a stage oI basic counter
Now let`s add the Load control input to this stage. Thus the operation would become as
shown in Table 1.
Table 1: Operation oI counter with Load signal added
Based on the above table, the stage will be modiIied as shown in Figure 3.
Figure 3: ModiIied stage oI a counter
In this Iigure, when Count 0 and Load 0, J and K inputs in the Ilip Ilop will be equal
to 0 and 0 ; NO CHANGE state is achieved. Notice that AND gate marked with pink
will also be generating an output oI 0.
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When Count 0 or 1 (i.e. don`t care) and Load 1, parallel load operation will take
place. The blue AND gate will propagate D while orange will propagate D/ to J and K
inputs respectively.
When Count 1 and Load 0, the circuit will operate as counter because JK 11. It is
the same behavior with respect to the tradition counter.
Now, the control signal Clear can be added to the stage. We will assume asvnchronous
Clear in the design.
Table 2: Counter Operation with Count, Load, and Clear signals
The stage will be modiIied as given in Figure 4.
Figure 4: Addition oI Clear signal to a counter stage
Designing counters ith available counters
Binary counters with parallel load can be used to design diIIerent modulon counters. For
example, the 4bit parallel load counter discussed in this lesson can be used to design any
counter oI modulo n where 2< n 0 1.
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Design oI decade counter
The binary counter with parallel load can be converted into a synchronous DECADE
counter (without load input) by connecting an external AND gate to it, as shown in
Figure 5.
Figure 5: Decade counter
Connect all the D inputs to Ground (Logic 0). Make Count 1. This will make the circuit
always operating in the counter mode.
The 2input AND gate connected to the Load input oI the counter takes Q0 and Q3 as its
inputs. As long as the Load input (connected to the output oI the AND gate) is 0, the
counter is incremented by one with each clock pulse.
When the output count reaches 9 (1001), the output oI AND gate will equal 1. This puts
the counter in the load mode (Load 1). Thus, the next clock pulse will load the data on
the Dinputs (0000) into the counter instead oI incrementing the count.
Thus the counter counts Irom 0000 (decimal 0) to 1001 (decimal 9) then goes back to
0000 and so on. Modulo 10 counting
Design oI a counter that counts Irom 3 to 12.
The counter discussed above can be made to count Irom 0011 (decimal 3) to 1100
(decimal 12). Only small modiIications are required, which are (see Figure ):
Connect the D inputs to 0011 (i.e. D3D2D1D0 0011). This will make the circuit
start counting Irom 3 whenever 12 has been counted.
Connect the AND gate to Q3 and Q2. Thus, whenever the circuit reaches 12
(1100), Q3 Q2 1, which will make the output oI the AND gate equal to 1,
making Load active, so in the next clock transition the counter does not count, but
is loaded Irom its Iour inputs, with a value oI 0011.
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Figure : Counter Ior 3 to 12 counting
Thus the counter counts Irom 0011 (decimal 3) to 1100 (decimal 12), and back to 0011.
This is also a mod10 counter, since it also counts ten numbers.
Some counters may have the 'Clear¨ control input. With this capability, the counter can
be 'cleared¨ at any time. The 'Clear¨ signal can also be classiIied into two types:
Synchronous and Asynchronous.
The Synchronous lear case
The Synchronous Clear input is activated in svnchronization with the clock pulse.
To explain this behavior, consider a MOD counter that counts Irom 000 (decimal 0) to
101 (decimal 5). The circuit is shown in the Iigure.
In this circuit, once the count oI 5 (101) is detected by the AND gate, the counter is
cleared on the next clock pulse. Thus, the counter counts Irom 0 to 5 back to 0.
Assuming negative edgetriggered FFs, the timing diagram oI this counter is shown in
Figure . Notice the delayed transitions oI the counter outputs (Q`s) aIter the negative
clock edge due to gate propagation delays.
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Figure : Timing diagram Synchronous Clear
The timing diagram clariIies the case oI Q2Q1Q0 101 where the Clear input becomes 1
causing the counter to clear on the next negative clock edge. The point to notice here is
that the eIIect oI change in 'Clear¨ is not immediately applied, but becomes eIIective in
the Iollowing clock pulse, because the 'Clear¨ input is 'Synchronous¨, i.e. it onlv takes
effect at the next active clock edge.
The Asynchronous lear case
II we use asynchronous clear rather than synchronous clear, as soon as the count Q2Q1Q0
reaches 101, 'Clear¨is activated and the FFs are cleared immediately without waiting Ior
the next active clock edge.
This causes the count Q2Q1Q0 101 to switch to 000 aIter a small delay. In other words
the count 101 does not last Ior a Iull clock period as other counts, but rather will appear
Ior a very short duration as a narrow pulse (glitch) as shown in Figure . Thus, it would
appear that the counter counts Irom 0 to 4, that is, Irom 000 to 100.
This happens because 'Clear¨ is 'Asynchronous¨. It does not wait Ior the clock pulse to
come, and does the 'clearing¨ operation immediately.
As a result, the output values become Q2Q1Q0 101 Ior a very short duration oI time,
almost negligible, and then the contents become Q2Q1Q0 000 within the same clock
period.
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Figure : Timing diagram Asynchronous Clear
To have a MOD counter designed using the asynchronous clear, we should detect a
count oI (instead oI 5) and use that to clear the counter asynchronously.
In this case, once the count reaches Q2Q1Q0 110, 'Clear¨ is activated, you will not be
able to observe Q2Q1Q0 110, because it will be Ior very short duration. This is shown in
Figure 9.
It would seem to you that aIter Q2Q1Q0 101, the next state is Q2Q1Q0 000.
Figure 9: Timing diagram
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Ripple and Arbitrary ounters
In this lesson, you will learn about:
Ripple Counters
Counters with arbitrary count sequence
Design oI ripple Counters
Two types oI counters are identiIiable:
Svnchronous counters, which have been discussed earlier, and
#ipple counters.
In ripple counters, IlipIlop output transitions serve as a source Ior triggering other Ilip
Ilops.
In other words, clock inputs oI the IlipIlops are triggered by output transitions oI other
IlipIlops, rather than a common clock signal.
Typically, T IlipIlops are used to build ripple counters since they are capable oI
complementing their content (See Figure 1).
The signal with the pulses to be counted, i.e.'Pulse¨, is connected to the clock input oI
the IlipIlop that holds the SB (FF # 1).
The output oI each FF is connected to the clock input oI the next IlipIlop in sequence.
The IlipIlops are negative edge triggered (bubbled clock inputs).
T1 Ior all FFs (J K 1). This means that each IlipIlop complements its value iI C
input goes through a negative transition (1 0).
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Digital Logic Design by Morris Mano 3rd Edition
Figure 1: A ripple counter
The previous ripple upcounter can be converted into a downcounter in one oI two ways:
Replace the negativeedge triggered FFs by positiveedge triggered FFs, or
Instead oI connecting C input oI FF Qi to the output oI the preceding FF (Qi1)
connect it to the complement output oI that FF (Q/i1).
Advantages oI Ripple Counters:
simple hardware and design.
Disadvantages oI Ripple Counters:
They are asynchronous circuits, and can be unreliable and delay dependent, iI
more logic is added.
Large ripple counters are slow circuits due to the length oI time required Ior the
ripple to occur.
Counters with Arbitrary Count Sequence:
Design a counter that Iollows the count sequence: 0, 1, 2, 4, 5, . This counter can be
designed with any IlipIlop, but let`s use the JK IlipIlop.
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Notice that we have two 'unused¨ states (3 and ), which have to be dealt with (see
Figure 2). These will be marked by don`t cares in the state table (ReIer to the design oI
sequential circuits with unused states discussed earlier). The state diagram oI this counter
is shown in Figure 2.
In this Iigure, the unused states can go to any oI the valid states, and the circuit can
continue to count correctly. One possibility is to take state (111) to 0 (000) and state 3
(011) to 4 (100).
Figure 2: State diagram Ior arbitrary counting sequence
The design approach is similar to that oI synchronous circuits. The state transition table is
built as shown in Figure 3 and the equations Ior all J and K inputs are derived. Notice that
we have used don`t care Ior the unused state (although we could have used 100 as the
next state Ior 011, and 000 as the next state oI 111).
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Figure 3: State table Ior arbitrary counting sequence
The computed J and K input equations are as Iollows:
JA B
JB C
JC B
KA B
KB 1
KC 1
Figure 4: Circuit Ior arbitrary counting sequence
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Semiconductor Memories: RAMs and ROMs
esson Objectives:
In this lesson you will be introduced to:
DiIIerent memory devices like, #M, #OM, P#OM, EP#OM, EEP#OM, etc.
DiIIerent terms like: read, rite, access ti2e, nibble, bvte, bus, 4rd, 4rd lengt,
address, v4latile, n4nv4latile etc.
How to implement combinational and sequential circuits using ROM.
ntroduction:
The smallest unit oI inIormation a digital system can store is a bit, which can be stored in
a 1li51l45 or a 1bit register.
To store m bits oI data, an 2bit register with parallel load capability may be used. Data
available on the 2bit input lines (I0 to Im1) may be stored/written into this register under
control oI the clock by asserting the 'Load¨ control input. The stored 2 bits oI data may
be read Irom the register outputs (O0 to Om1).
The 2 bits oI data stored in a register make up a 4rd. It is simply a number oI bits
operated upon or considered by the hardware as a group. The number oI bits in the word,
2, is called 4rd lengt.
The m inputs oI the register are provided through an mbit input data bus and m outputs
by an mbit output data bus.
A bus is a number oI signal lines, grouped together because oI similarity oI Iunction,
which connect two or more systems or subsystems.
A unit oI bits oI inIormation is reIerred to as a bvte, while 4bits oI inIormation is
reIerred to as a nibble.
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A 2e24rv device can be looked at as consisting oI a number oI equally sized registers
sharing a common set of inputs. and a common set of outputs. as shown in the Figure.
Storing data in a memory register is reIerred to as a memory rite operation and looking
up the contents oI a memory register is reIerred to as a memory read operation.
In case oI a write operation, the input data need to be written into one particular register
in the memory device.
Since the input data lines are common to all registers oI the memory device, only the
selected register should have its l4ad control signal asserted while the other registers
should not.
II the number oI registers is 2n, n lines will be required to select the register to be written
into. The nlines are used as an input to a decoder where the decoder`s 2n outputs may be
used as the l4ad control inputs to the 2n registers.
The load control signal oI a particular register is asserted by a unique combination oI the
nselect lines. This unique combination is considered as the address Ior that particular
register.
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Thus, a memory device can be thought oI as a collection oI addressable registers.
A read or a write operation into the memory device has to speciIy the address oI the
particular register to be read or written into.
The ca5acitv oI the memory is speciIied in terms oI the number oI bits or the number oI
words available in this memory device.
For a memory device with nbit address lines and word (register) size oI 2bits, the
memory has 2n words (storage locations/registers) each having 2 bits Ior a total capacity
oI 2n x 2 bits.
For example, iI n 10 and m , the memory is a ~102 x ¨ bit memory. Alternatively,
it is said that the memory has 1K bytes.
A block diagram oI the memory device is shown in the Iigure. The address inputs are
decoded by address decoder to select one, and only one, oI the memory words
(registers), either Ior reading or writing.
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The # / W# line is a control signal that determines the type oI operation to be
perIormed; a read operation or a write operation.
# / W# = 1 indicates a read operation, while # / W# = 0 indicates a write operation.
To read the memory contents stored in a particular word, the address oI this word is
applied, and logic 1 is applied to the # / W# line that enables the output buIIers oI the
memory.
To rite at a location, the address oI the location to be written is provided at the address
inputs, data is provided at the data inputs, and logic 0 is applied to the # / W# line.
There is a time delay between the application oI an address and the appearance oI
contents at the output, this is called the memory access ti2e. This depends both on the
technology and on the structure used to implement the memory.
Random Access Memory (RAM):
For the shown above memory structure, the access time is independent oI the sequence in
which addresses are applied.
Such a memory is called rand42 access 2e24rv #M. Thus, the contents oI any one
location can be accessed in essentially the same time as can the contents oI any other
location chosen at random.
RAMs are v4latile memories that will only retain the stored data as long as power is ON
but will lose this data when power is turned OFF.
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RAMs are classiIied into two main categories: Static RAM S#M and Dynamic RAM
#M. These will be studied in greater details in Iuture courses.
Read Only Memory (ROM):
Read Only Memory (ROM) is memory whose stored data can only be read but cannot be
rewritten (altered).
It is a device in which 'permanent¨ binary inIormation has been stored.
ROMs are n4nv4latile where stored data are not lost even when power is turned OFF.
The Figure shows a block diagram oI a ROM.
Like RAMS, a ROM has n address inputs and 2 outputs. This corresponds to 2n memory
words each oI m storage bits Ior a total capacity oI 2n x 2 bits.
Unlike RAMs, ROMs do not have data input lines, because they do not have a write
operation.
ROMs are common to use in storing systemlevel programs that should be available at all
times.
The most common example is the PC system BIOS (Basic Input Output System), which
is stored in a ROM called the svstem BOS #OM.
Several classes oI ROMs are in common use. These may be categorized according to
their Iabrication technologies that inIluence the way data are introduced into the ROM.
The process oI storing the desired data into the ROM is reIerred to as #OM
programming.
Types of ROMs:
Following are the diIIerent types oI ROMs.
1 Programming is done by the manuIacturer during the last Iabrication steps according
to the truth table provided by the customer. This type is known as mask programmable
ROMs or simply #OM. Data stored this way can never be altered.
2 ROM is provided with Iuses to allow users to introduce the desired data by electrically
blowing some oI these Iuses. This type is reIerred to as a programmable #OM. or
P#OM. Fuse blowing is irreversible and, once programmed the ROM stored pattern
cannot be altered.
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The ROM uses erasable floatinggate memory cells that allow erasure oI the stored
data by UltraViolet light. In this type, programming is perIormed electricallv by the
user using special hardware programmers. Data, thus stored, can later be erased
globally (all memory bits 1) by exposing the memory array to UVlight. This ROM
type is reIerred to as UVerasable, programmable #OM. or simply EP#OM. The
EPROM IC package is provided with a quartz window to allow UVlight penetration
to the memory array.
"uartz
Windo
loser Vie of
"uartz Windo
When special electrically erasable memory cells are used, the ROM can be electrically
erased at the byte level. Thus individual bytes may be addressed and programmed or
erased as desired. This type is reIerred to as electricallv erasable. programmable
#OM. or EEP#OM or E2P#OM. The E2P#OM technology is an expensive low
capacity technology and is thus not used Ior high density or lowcost applications.
The most recent ROM technology is the flash technology that combines the lowcost
and highdensity advantages oI the UVEPROM technology and the Ilexibility oI
electrical erase oI E2P#OM technology. This technology is electrically erasable but
the erasure is perIormed either globally (the Iull array) or partially on complete sub
arrays (sectors).
ombinational ircuit mplementation Using ROM:
ROM devices can be used to implement complex combinational circuits directly Irom
truth tables without need Ior minimization.
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Digital Logic Design by Morris Mano 3rd Edition
For an ninput, 2output combinational circuit, a 2n x 2 ROM is needed (2n words each
oI 2 storage bits). The designer needs only to speciIy a ROM table that gives the
inIormation stored in each oI the 2n words.
When a combinational circuit is implemented using a ROM, the Iunction may either be
expressed in the sum oI minterms Iorm, or using a truth table.
As an example, the ROM shown in the Iigure may be considered as a combinational
circuit with Iour outputs, each a Iunction oI the Iive input variables.
Outputs Z0 Z3 can be expressed as sum oI minterms as Iollows:
Z0 (A4. A3. A2. A1. A0) ÷ _m (2. 3. 18. 21. 31)
Z1 (A4. A3. A2. A1. A0) ÷ _m (0. 1. 17. 25. 31)
Z2 (A4. A3. A2. A1. A0) ÷ _m (1. 6. 11. 29. 30)
Z3 (A4. A3. A2. A1. A0) ÷ _m (7. 8. 16. 28. 29)
Example 1:
Consider a combinational circuit which is speciIied by the Iollowing two Iunctions:
F1 , Y _2 1, 2, 3
F2 , Y _2 ô, 2
The truth table Ior this circuit is as shown.
In this example, the ROM that implements the two combinational Iunctions must have
two address inputs and two outputs. Thus, its size must be 4 x 2 (since 2n x 2 is the size
oI ROM).
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Digital Logic Design by Morris Mano 3rd Edition
The ROM table Ior this example is as shown.
Example 2:
Design a combinational circuit using a ROM. The circuit accepts a 3bit number and
generates an output binary number that is equal to the square oI the input number.
The Iirst step is to derive the truth table Ior the combinational circuit as shown. Three
inputs and six outputs are needed to accommodate all possible numbers.
By observation, we note that output B0 is always equal to input A0, and output B1 is
always 0. Thus, there is no need to store B0 and B1 in the ROM. We actually need to only
store values oI the Iour outputs (B5 through B2) in the ROM.
The table shown speciIies all the inIormation that needs to be stored in the ROM, and
Iigure shows the required connections oI the combinational circuit. The output B1 is
connected to logic 0 and output B0 is connected to A0 always to get B1 0 and B0 A0.
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Digital Logic Design by Morris Mano 3rd Edition
The minimum size ROM needed must have three inputs and Iour outputs, Ior a total oI
x 4 32 bits.
Synchronous Sequential ircuit mplementation Using ROM:
The block diagram oI a sequential circuit is shown in the Iigure.
Since ROM can implement combinational logic, so this part can be replaced by a ROM
and FlipFlops can be replaced by a register as shown in the Iigure.
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Digital Logic Design by Morris Mano 3rd Edition
Example 3:
Design a sequential circuit whose state transition table is given, using a ROM and a
register.
The nextstate and output inIormation are obtained Irom the table as:
"1+ _2 1, 2, , ô
"2+ _2 4, ô
Y "2, "1, _2 3,
The ROM can be used to implement the combinational circuit and register will provide
the IlipIlops.
The number of address inputs to the ROM is equal to the number oI IlipIlops plus the
number oI external inputs.
The number of outputs oI the ROM is equal to the number oI IlipIlops plus the number
oI external outputs.
In this example, 3 inputs and 3 outputs oI the ROM are required; so its size must be x 3.
The ROM table is identical to the state transition table with Present State and Inputs
speciIying the address oI ROM and Next State and Outputs speciIying the ROM outputs
(stored information). It is shown below:
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Digital Logic Design by Morris Mano 3rd Edition
The next state values must be connected Irom the ROM outputs to the register inputs as
shown in the Iigure below.
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Digital Logic Design by Morris Mano 3rd Edition
Programmable ogic Devices (PDs)
esson Objectives:
In this lesson you will be introduced to some types oI Programmable Logic Devices
(PLDs):
PROM, PAL, PLA, CPLDs, FPGAs, etc.
How to implement digital circuits using PLAs and PALs.
ntroduction:
An IC that contains large numbers oI gates, IlipIlops, etc. that can be configured bv
the user to perIorm diIIerent Iunctions is called a Pr4gra22able L4gic evice
PL.
The internal logic gates and/or connections oI PLDs can be changed/conIigured by a
programming process.
One oI the simplest programming technologies is to use Iuses. In the original state oI
the device, all the Iuses are intact.
Programming the device involves blowing those Iuses along the paths that must be
removed in order to obtain the particular conIiguration oI the desired logic Iunction.
PLDs are typically built with an arrav oI AND gates (ANDarray) and an arrav oI
OR gates (ORarray).
Advantages of PDs:
Problems oI using standard ICs:
Problems oI using standard ICs in logic design are that they require hundreds or
thousands oI these ICs, considerable amount oI circuit board space, a great deal oI
time and cost in inserting, soldering, and testing. Also require keeping a signiIicant
inventory oI ICs.
Advantages oI using PLDs:
Advantages oI using PLDs are less board space, Iaster, lower power requirements
(i.e., smaller power supplies), less costly assembly processes, higher reliability (Iewer
ICs and circuit connections means easier troubleshooting), and availability oI design
soItware.
There are three Iundamental types oI standard PLDs: P#OM, PL, and PL.
A Iourth type oI PLD, which is discussed later, is the C425lex Pr4gra22able L4gic
evice CPL, e.g., Field Pr4gra22able Cate rrav FPC.
A typical PLD may have hundreds to millions oI gates.
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Digital Logic Design by Morris Mano 3rd Edition
In order to show the internal logic diagram Ior such technologies in a concise Iorm, it
is necessary to have special symbols Ior array logic.
Figure shows the conventional and array logic symbols Ior a multiple input AND and
a multiple input OR gate.
Three Fundamental Types of PDs:
The three Iundamental types oI PLDs diIIer in the placement oI programmable
connections in the ANDOR arrays. Figure shows the locations oI the programmable
connections Ior the three types.
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The P#OM Pr4gra22able #ead Onlv Me24rv has a Iixed AND array
(constructed as a decoder) and programmable connections Ior the output OR gates
array. The PROM implements Boolean Iunctions in sumoIminterms Iorm.
The PL Pr4gra22able rrav L4gic device has a programmable AND array
and Iixed connections Ior the OR array.
The PL Pr4gra22able L4gic rrav has programmable connections Ior both
AND and OR arrays. So it is the most Ilexible type oI PLD.
The ROM (Read Only Memory) or PROM (Programmable Read Only
Memory):
The input lines to the AND array are hardwired and the output lines to the OR array
are programmable.
Each AND gate generates one oI the possible AND products (i.e., minterms).
In the previous lesson, you have learnt how to implement a digital circuit using ROM.
The PA (Programmable ogic Array):
In PLAs, instead oI using a decoder as in PROMs, a number (k) oI AND gates is used
where k < 2n, (n is the number oI inputs).
Each oI the AND gates can be programmed to generate a product term oI the input
variables and does not generate all the minterms as in the ROM.
The AND and OR gates inside the PLA are initially Iabricated with the links (Iuses)
among them.
The speciIic Boolean Iunctions are implemented in sum oI products Iorm by opening
appropriate links and leaving the desired connections.
A block diagram oI the PLA is shown in the Iigure. It consists oI n inputs, 2 outputs,
and k product terms.
The product terms constitute a group oI k AND gates each oI 2n inputs.
Links are inserted between all n inputs and their complement values to each oI the
AND gates.
Links are also provided between the outputs oI the AND gates and the inputs oI the
OR gates.
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Since PLA has 24ut5uts, the number oI OR gates is 2.
The output oI each OR gate goes to an XOR gate, where the other input has two sets
oI links, one connected to logic 0 and other to logic 1. It allows the output Iunction to
be generated either in the true Iorm or in the complement Iorm.
The output is inverted when the XOR input is connected to 1 (since X 1 X/). The
output does not change when the XOR input is connected to 0 (since X 0 X).
Thus, the total number oI programmable links is 2n x k + k x 2 + 22.
The size oI the PLA is speciIied by the number oI inputs n, the number oI product
terms k, and the number oI outputs 2, (the number oI sum terms is equal to the
number oI outputs).
Example:
Implement the combinational circuit having the shown truth table, using PLA.
Each product term in the expression requires an AND gate. To minimize the cost, it is
necessary to simpliIy the Iunction to a minimum number oI product terms.
Designing using a PLA, a careIul investigation must be taken in order to reduce the
distinct product terms. Both the true and complement Iorms oI each Iunction should
be simpliIied to see which one can be expressed with Iewer product terms and which
one provides product terms that are common to other Iunctions.
The combination that gives a minimum number oI product terms is:
1 ÷ AB ¹ AC ¹ BC or 1 ÷ (AB ¹ AC ¹ BC)
2 ÷ AB ¹ AC ¹ ABC
This gives only 4 distinct product terms: AB. AC. BC. and ABC.
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So the PLA table will be as Iollows:
For each product term, the inputs are marked with 1, 0, or (dash). II a variable in the
product term appears in its normal Iorm (unprimed), the corresponding input variable
is marked with a 1.
A 1 in the nputs column speciIies a path Irom the corresponding input to the input oI
the AND gate that Iorms the product term.
A 0 in the nputs column speciIies a path Irom the corresponding complemented
input to the input oI the AND gate. A dash speciIies no connection.
The appropriate Iuses are blown and the ones leIt intact Iorm the desired paths. It is
assumed that the open terminals in the AND gate behave like a 1 input.
In the Outputs column, a T (true) speciIies that the other input oI the corresponding
XOR gate can be connected to 0, and a (complement) speciIies a connection to 1.
Note that output F1 is the normal (or true) output even though a (Ior complement) is
marked over it. This is because F1' is generated with ANDOR circuit prior to the
output XOR. The output XOR complements the Iunction 1 to produce the true 1
output as its second input is connected to logic 1.
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The PA (Programmable Array ogic):
The PAL device is a PLD with a Iixed OR array and a programmable AND array.
As only AND gates are programmable, the PAL device is easier to program but it is
not as Ilexible as the PLA.
The device shown in the Iigure has 4 inputs and 4 outputs. Each input has a buIIer
inverter gate, and each output is generated by a Iixed OR gate.
The device has 4 sections, each composed oI a 3wide ANDOR array, meaning that
there are 3 programmable AND gates in each section.
Each AND gate has 10 programmable input connections indicating by 10 vertical
lines intersecting each horizontal line. The horizontal line symbolizes the multiple
input conIiguration oI an AND gate.
One oI the outputs F1 is connected to a buIIerinverter gate and is Ied back into the
inputs oI the AND gates through programmed connections.
(see animation in authorare version)
Designing using a PAL device, the Boolean Iunctions must be simpliIied to Iit into
each section.
The number oI product terms in each section is Iixed and iI the number oI terms in the
Iunction is too large, it may be necessary to use two or more sections to implement
one Boolean Iunction.
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Example:
Implement the Iollowing Boolean Iunctions using the PAL device as shown above:
W, B, C, _22, 12, 13
, B, C, _2, 8, 9, 1ô, 11, 12, 13, 14, 1
Y, B, C, _2ô, 2, 3, 4, , ô, , 8, 1ô, 11, 1
, B, C, _21, 2, 8, 12, 13
SimpliIying the 4 Iunctions to a minimum number oI terms results in the Iollowing
Boolean Iunctions:
÷ ABC ¹ ABCD
X ÷ A ¹ BCD
Y ÷ AB ¹ CD ¹ BD
Z ÷ ABC ¹ ABCD ¹ ACD ¹ ABCD
÷ ¹ACD ¹ ABCD
Note that the Iunction Ior has Iour product terms. The logical sum oI two oI these
terms is equal to W. Thus, by using W, it is possible to reduce the number oI terms Ior
Irom Iour to three, so that the Iunction can Iit into the given PAL device.
The PAL programming table is similar to the table used Ior the PLA, except that only
the inputs oI the AND gates need to be programmed.
The Iigure shows the connection map Ior the PAL device, as speciIied in the
programming table.
(see animation in authorare version)
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Since both W and X have two product terms, third AND gate is not used. II all the
inputs to this AND gate leIt intact, then its output will always be 0, because it receives
both the true and complement oI each input variable i.e., AA` 0
omplex Programmable ogic Devices (PDs):
A CPLD contains a bunch oI PLD blocks whose inputs and outputs are connected
together by a global interconnection matrix.
Thus a CPLD has two levels oI programmability: each PLD block can be
programmed, and then the interconnections between the PLDs can be programmed.
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Field Programmable Gate Arrays (FPGAs):
The FPGA consists oI 3 main structures:
1. Programmable logic structure,
2. Programmable routing structure, and
3. Programmable Input/Output (I/O).
1 Programmable logic structure
The programmable logic structure FPGA consists oI a 2dimensional array oI
conIigurable logic blocks (CLBs).
Each CLB can be conIigured (programmed) to implement anv Boolean Iunction oI its
input variables. Typically CLBs have between 4 input variables. Functions oI larger
number oI variables are implemented using more than one CLB.
In addition, each CLB typically contains 1 or 2 FFs to allow implementation oI
sequential logic.
Large designs are partitioned and mapped to a number oI CLBs with each CLB
conIigured (programmed) to perIorm a particular Iunction.
These CLBs are then connected together to Iully implement the target design.
Connecting the CLBs is done using the FPGA programmable routing structure.
2 Programmable routing structure
To allow Ior Ilexible interconnection oI CLBs, FPGAs have 3 programmable routing
resources:
1. Vertical and horizontal routing channels which consist oI diIIerent length wires
that can be connected together iI needed. These channel run vertically and
horizontally between columns and rows oI CLBs as shown in the Figure.
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2. Connection boxes, which are a set oI programmable links that can connect input
and output pins oI the CLBs to wires oI the vertical or the horizontal routing
channels.
3. Switch boxes, located at the intersection oI the vertical and horizontal channels.
These are a set oI programmable links that can connect wire segments in the
horizontal and vertical channels. (see animation in authorare version)
Programmable /O
These are mainly buIIers that can be conIigured either as input buIIers, output buIIers
or input/output buIIers.
They allow the pins oI the FPGA chip to Iunction either as input pins, output pins or
input/output pins.
Programmable
/Os
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eOE200 essons Errata
Error ocation
Example a on P11 oI U1.
P1 oI U1. 2`s complement
Representation oI 
Example  P1 oI U21. aIter
the downward red lines
Example 2 P oI U2
"uiz on P oI U2. "uestion 2
Error Description
4 0 1000000000 0
11011010
F (A`.B¹ 0) . (0 ¹ A` B C` ). (A`. B ¹ A`.B.C` )
KMap representation oI the Iunction has 1 in in
M1 , But it is located.
The given answer is False
orre
4 010000 0
11011011
F (A`.B¹ 0) . (0 ¹ A` B
(A`.B¹ 0) . (0 ¹ A` B
(A`B). (A`BC`) . (0 ¹
A`BC`
The 1 must be relocated i
0`s done accordingly
Correct answer is TRUE
of
PS: These are the known errors so Iar. II you come across any other error please send Ior a more comprehensive list
P Page, U Unit, L Lesson. Thus P19 oI U1 L5 means Page 19 in lesson 5 oI unit 1.
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