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• High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 32K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 1024 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 2K Byte Internal SRAM – Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad MLF Operating Voltages – 2.7 - 5.5V for ATmega32L – 4.5 - 5.5V for ATmega32 Speed Grades – 0 - 8 MHz for ATmega32L – 0 - 16 MHz for ATmega32 Power Consumption at 1 MHz, 3V, 25°C for ATmega32L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA
8-bit Microcontroller with 32K Bytes In-System Programmable Flash ATmega32 ATmega32L Preliminary
• • • •
Pin Configurations Figure 1. Pinouts ATmega32 PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP) PD6 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2) TQFP/MLF PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 ATmega32(L) 2503F–AVR–12/03 (INT1) (OC1B) (OC1A) (ICP) (OC2) PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 (TCK) PC2 (TMS) PC3 .
Block Diagram PA0 . & TIMING RESET INSTRUCTION DECODER Y Z CONTROL LINES ALU INTERRUPT UNIT INTERNAL CALIBRATED OSCILLATOR AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART + - COMP. the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.PB7 PD0 .PA7 VCC PC0 .PC7 Block Diagram PORTA DRIVERS/BUFFERS PORTC DRIVERS/BUFFERS GND PORTA DIGITAL INTERFACE PORTC DIGITAL INTERFACE AVCC MUX & ADC AREF PROGRAM COUNTER ADC INTERFACE TWI STACK POINTER TIMERS/ COUNTERS OSCILLATOR PROGRAM FLASH SRAM INTERNAL OSCILLATOR XTAL1 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X WATCHDOG TIMER OSCILLATOR XTAL2 MCU CTRL. INTERFACE PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS PB0 .ATmega32(L) Overview The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture.PD7 3 2503F–AVR–12/03 . By executing powerful instructions in a single clock cycle. Figure 2.
SPI port. Port A serves as the analog inputs to the A/D Converter. by a conventional nonvolatile memory programmer. 32 general purpose I/O lines. and interrupt system to continue functioning. 4 ATmega32(L) 2503F–AVR–12/03 . In Standby mode. program debugger/simulators. 32 general purpose working registers. Port A also serves as an 8-bit bi-directional I/O port. disabling all other chip functions until the next External Interrupt or Hardware Reset. The device is manufactured using Atmel’s high density nonvolatile memory technology. allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The boot program can use any interface to download the application program in the Application Flash memory. 2K byte SRAM. a JTAG interface for Boundary-scan. On-chip Debugging support and programming. The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low.The AVR core combines a rich instruction set with 32 general purpose working registers. or by an On-chip Boot program running on the AVR core. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip. a programmable Watchdog Timer with Internal Oscillator.. In Power-save mode. in-circuit emulators. The ATmega32 provides the following features: 32K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities. three flexible Timer/Counters with compare modes. Software in the Boot Flash section will continue to run while the Application Flash section is updated. In Extended Standby mode.PA0) Digital supply voltage. The ATmega32 AVR is supported with a full suite of program and system development tools including: C compilers. Port pins can provide internal pull-up resistors (selected for each bit). macro assemblers. SRAM. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU). 1024 bytes EEPROM. both the main Oscillator and the Asynchronous Timer continue to run. allowing the user to maintain a timer base while the rest of the device is sleeping. a serial programmable USART. an SPI serial port. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC. Ground. The Port A pins are tri-stated when a reset condition becomes active. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface. to minimize switching noise during ADC conversions. they will source current if the internal pull-up resistors are activated. even if the clock is not running. and evaluation kits. if the A/D Converter is not used. and six software selectable power saving modes. providing true Read-While-Write operation. the crystal/resonator Oscillator is running while the rest of the device is sleeping. Two-wire interface. the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The Idle mode stops the CPU while allowing the USART. Timer/Counters. Pin Descriptions VCC GND Port A (PA7. The Power-down mode saves the register contents but freezes the Oscillator. a byte oriented Two-wire Serial Interface. an 8-channel. A/D Converter. This allows very fast start-up combined with low-power consumption. 10-bit ADC with optional differential input stage with programmable gain (TQFP package only). the Asynchronous Timer continues to run. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Internal and External Interrupts.
even if the clock is not running.PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Port D (PD7. Port B also serves the functions of various special features of the ATmega32 as listed on page 55. even if the clock is not running. The Port C pins are tri-stated when a reset condition becomes active. A low level on this pin for longer than the minimum pulse length will generate a reset. Output from the inverting Oscillator amplifier. even if the clock is not running. Port D pins that are externally pulled low will source current if the pull-up resistors are activated. RESET Reset Input. As inputs.. Port C (PC7. Port C also serves the functions of the JTAG interface and other special features of the ATmega32 as listed on page 58. As inputs. the pull-up resistors on pins PC5(TDI).PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Shorter pulses are not guaranteed to generate a reset. The Port D pins are tri-stated when a reset condition becomes active. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. The Port B pins are tri-stated when a reset condition becomes active. XTAL1 XTAL2 AVCC AREF 5 2503F–AVR–12/03 ..ATmega32(L) Port B (PB7.. Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The minimum pulse length is given in Table 15 on page 35. If the JTAG interface is enabled. If the ADC is used. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. The TD0 pin is tri-stated unless TAP states that shift out data are entered. The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. Port B pins that are externally pulled low will source current if the pull-up resistors are activated. AVCC is the supply voltage pin for Port A and the A/D Converter. Port D also serves the functions of various special features of the ATmega32 as listed on page 60. AREF is the analog reference pin for the A/D Converter. It should be externally connected to VCC. even if the ADC is not used.PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. even if the clock is not running. it should be connected to VCC through a low-pass filter. PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
129. 64 38.83. 65. 65 66 80. 110.196. 128 81.216 105 108 109 109 109 109 109 109 110 110 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – – URSEL URSEL – – – – UMSEL – – – – UPM1 – – WDTOE – UPM0 – USBS – – AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 EEAR9 UCPOL EEAR8 TCR2UB WDP0 123 125 125 126 40 162 160 17 17 17 EEPROM Address Register Low Byte EEPROM Data Register – PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPI Data Register SPIF SPIE RXC RXCIE ACD REFS1 ADEN WCOL SPE TXC TXCIE ACBG REFS0 ADSC – DORD UDRE UDRIE ACO ADLAR ADATE – MSTR FE RXEN ACI MUX4 ADIF – CPOL DOR TXEN ACIE MUX3 ADIE – CPHA PE UCSZ2 ACIC MUX2 ADPS2 – SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 – PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 – PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 17 62 62 62 62 62 63 63 63 63 63 63 63 136 136 134 157 158 159 162 197 212 214 215 215 177 USART I/O Data Register USART Baud Rate Register Low Byte ADC Data Register High Byte ADC Data Register Low Byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 177 6 ATmega32(L) 2503F–AVR–12/03 . 111. 226 78 80 28 222 Timer/Counter0 Output Compare Register Timer/Counter0 (8 Bits) Oscillator Calibration Register On-Chip Debug Register ADTS2 COM1A1 ICNC1 ADTS1 COM1A0 ICES1 ADTS0 COM1B1 – – COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10 54. 128 246 175 30.Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31(1) ($51)(1) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20(2) ($40)(2) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) Name SREG SPH SPL OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL OCDR SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR Bit 7 I – SP7 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SE JTD FOC0 Bit 6 T – SP6 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SM2 ISC2 WGM00 Bit 5 H – SP5 INT2 INTF2 TICIE1 ICF1 – TWSTA SM1 – COM01 Bit 4 S – SP4 – – OCIE1A OCF1A RWWSRE TWSTO SM0 JTRF COM00 Bit 3 V SP11 SP3 – – OCIE1B OCF1B BLBSET TWWC ISC11 WDRF WGM01 Bit 2 N SP10 SP2 – – TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02 Bit 1 Z SP9 SP1 IVSEL – OCIE0 OCF0 PGERS – ISC01 EXTRF CS01 Bit 0 C SP8 SP0 IVCE – TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00 Page 8 10 10 80 45.
When the OCDEN Fuse is unprogrammed. Refer to the USART description for details on how to access UBRRH and UCSRC. thus clearing the flag. 2. Note that the CBI and SBI instructions will operate on all bits in the I/O Register. writing a one back into any flag read as set.ATmega32(L) Address $01 ($21) $00 ($20) Name TWSR TWBR Bit 7 TWS7 Bit 6 TWS6 Bit 5 TWS5 Bit 4 TWS4 Bit 3 TWS3 Bit 2 – Bit 1 TWPS1 Bit 0 TWPS0 Page 176 175 Two-wire Serial Interface Bit Rate Register Notes: 1. reserved bits should be written to zero if accessed. For compatibility with future devices. The CBI and SBI instructions work with registers $00 to $1F only. 4. Refer to the debugger specific documentation for details on how to use the OCDR Register. 3. 7 2503F–AVR–12/03 . Some of the Status Flags are cleared by writing a logical one to them. Reserved I/O memory addresses should never be written. the OSCCAL Register is always accessed on this address.
C.Rr . K Rd.V Z.V. k s. Rr Rd. k k k k k k k k k k k k k k k k k k k k Operands Rd. Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg.V Z.N.V.Rr Rd.K Rd ← Rd .H Z. Rr Rd. Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd . Rr Rd.H Z.C Rd ← Rd . Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal.N.H Z.C.K .Rr Rd.N.N.K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← $FF − Rd Rd ← $00 − Rd Rd ← Rd v K Rd ← Rd • ($FF . Rr Rd.V Z.V Z.N.C None None None None None None None I None Z.C.N. N.C.N.S Z.N. Rr Rd. K Rd. b P.H Z. b s.N.H Z.C.N.C. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare.V. Signed Branch if Less Than Zero. Rr Rd Rd Rd.N.V None Z.C Rdh:Rdl ← Rdh:Rdl .N. Rr Rd.C.S Z. b P. K Rd.N. Rr Rd.N.N.K Rd Rd Rd Rd Rd Rd.C.C.K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← $FF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr Flags Z.V.V Z.K Rd.C.V Z.N.H Z.C.N.Rr Rd.V.N.N.V.K Rr.V Z.C.V Z. K Rdl.C. N.C Z.H Z.Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd.V.K Rd.V Z.C Z.C Z.Rr Rd ← Rd .H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 PC ← PC + k + 1 PC ← Z PC ← k PC ← PC + k + 1 PC ← Z PC ← k PC ← Stack PC ← Stack if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 R1:R0 ← (Rd x Rr) << BRANCH INSTRUCTIONS 8 ATmega32(L) 2503F–AVR–12/03 . N. Rr Rd.H Z.N. Rr Rd.V. Rr Rd.V.K Rd.V.V Z.C Z.N.V. b Rr.V.H Z.V Z. Rr Rdl.C Z.
Load Indirect and Pre-Dec. Rd(0) ← 0 Rd(n) ← Rd(n+1).4)←Rd(3.ATmega32(L) Mnemonics BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV Rd. Z+ Rd.Rd(n)← Rd(n+1). Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z). Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc.C←Rd(0) Rd(n) ← Rd(n+1).1. (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr. . Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc.b) ← 0 Rd(n+1) ← Rd(n). (X) ← Rr (Y) ← Rr (Y) ← Rr. X Rd. Rd(7) ← 0 Rd(0)←C. Rr Y. Load Indirect and Pre-Dec.V Z. X ← X + 1 X ← X . Z ← Z+1 Z ← Z . Rr Z+q.. Z Rd.0)←Rd(7. Rr . Rd ← (X) Rd ← (Y) Rd ← (Y). Z+q Rd.Rd(n+1)← Rd(n).N.1. Rr Rr Rd P..Y..Y Rd.Rr Z. Y+ Rd. Z+ Operands k k Rd.N. Store Indirect Store Indirect and Post-Inc. Y ← Y + 1 Y ← Y . b Rd. Load Indirect and Pre-Dec. .X.V Z.. Rr . Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr Stack ← Rr Rd ← Stack I/O(P.1.C. Rr Rd. Rr Description Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc.b Rd Rd Rd Rd Rd Rd s s Rr.C. Z ← Z + 1 Z ← Z .Y+q Rd. n=0. Store Indirect and Pre-Dec. Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr.N. Load Indirect Load Indirect and Post-Inc.. Rr X+. Y Rd. P P.N.V Z. Rr Y+. Store Indirect and Pre-Dec. X+ Rd.1. Z Rd. (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z). Rr Z+. K Rd. Operation if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X). Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc.V None SREG(s) SREG(s) T None C C N N Z Z I I S S V #Clocks 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA TRANSFER INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS CLV SET CLT SEH Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG V←0 T←1 T←0 H←1 V T T H 1 1 1 1 9 2503F–AVR–12/03 .4). Y ← Y + 1 Y ← Y .0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I← 0 S←1 S←0 V←1 Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z.6 Rd(3. -Z Rd. Store Indirect and Pre-Dec. Rr Y+q.b P. Rr -Z. b Rd. k X. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow.N.1. X ← X + 1 X ← X .C.b) ← 1 I/O(P.C←Rd(7) Rd(7)←C.C.Rr k.V Z.1.Rd(7.C.X Rd. Rr Rd.
for WDR/timer) For On-Chip Debug Only 10 ATmega32(L) 2503F–AVR–12/03 . for Sleep function) (see specific descr.Mnemonics Operands Description Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset Break Operation H←0 Flags H None None None None #Clocks 1 1 1 1 N/A CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK (see specific descr.
0 mm body.7 . Thin (1. 0.5 . lead pitch 0. Micro Lead Frame Package (MLF) 11 2503F–AVR–12/03 .ATmega32(L) Ordering Information Speed (MHz) 8 Power Supply 2.600” Wide.5V Ordering Code ATmega32L-8AC ATmega32L-8PC ATmega32L-8MC ATmega32L-8AI ATmega32L-8PI ATmega32L-8MI 16 4.5.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40-pin. 7 x 7 x 1.5V ATmega32-16AC ATmega32-16PC ATmega32-16MI ATmega32-16AI ATmega32-16PI ATmega32-16MC Package 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 44A 40P6 44M1 Operation Range Commercial (0oC to 70oC) Industrial (-40oC to 85oC) Commercial (0oC to 70oC) Industrial (-40oC to 85oC) Package Type 44A 40P6 44M1 44-lead. Plastic Dual Inline Package (PDIP) 44-pad.5.50 mm.
90 0.00 12. 44-lead.30 0.10 0. CA 95131 TITLE 44A. REV.20 0.75 9.05 12.90 11. Variation ACB. 10 x 10 mm Body Size.8 mm Lead Pitch. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.00 10.15 1. 1.10 mm maximum. Allowable protrusion is 0. Lead coplanarity is 0. 44A B R 12 ATmega32(L) 2503F–AVR–12/03 . Dimensions D1 and E1 do not include mold protrusion.0 mm Body Thickness. This package conforms to JEDEC reference MS-026. 0.05 0. 3.20 0.Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose. Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO.10 12.45 NOM – – 1.75 9.00 – – – 0.45 0.25 10.80 TYP MAX 1.75 Note 2 Note 2 NOTE A2 A Notes: 1.09 0. 2.25 mm per side.95 11.00 12.00 10.25 10.
010").526 NOTE Notes: 1. Variation AC.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.875 13.600"/15.559 1. 40P6 B R 13 2503F–AVR–12/03 . Mold Flash or Protrusion shall not exceed 0.25 mm (0.356 1. CA 95131 TITLE 40P6. Dimensions D and E1 do not include mold Flash or Protrusion.041 3.070 15.381 52. B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose.048 0.203 15.826 – 52.970 Note 2 0.556 0. This package conforms to JEDEC reference MS-011.462 0. REV.ATmega32(L) 40P6 D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0. 40-lead (0.494 NOM – – – – – – – – – – 2. 2.240 13.651 3.381 17.578 Note 2 15.540 TYP MAX 4.
75 01/15/03 2325 Orchard Parkway San Jose.50 mm Micro Lead Frame Package (MLF) DRAWING NO.40 5. 44M1 C R 14 ATmega32(L) 2503F–AVR–12/03 .00 0.02 0.05 NOTE 0.35 0.23 7. 7 x 7 x 1.20 7.25 REF MAX 1. L 0.40 Notes: 1. CA 95131 TITLE 44M1. 44-pad. Lead Pitch 0.00 BSC 5.00 BSC 0.20 0.80 – NOM 0.0 mm Body.30 b BOTTOM VIEW e D2 E E2 e 5.55 0.44M1 D Marked Pin# 1 ID E SEATING PLANE TOP VIEW A1 A3 A L D2 Pin #1 Corner SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) E2 SYMBOL A A1 A3 b D MIN 0. JEDEC Standard MO-220.90 0.00 5. 1 (SAW Singulation) VKKD-1.18 0.00 5.50 BSC 5. Fig. REV.
Problem Fix / Workaround Select the Device ID Register of the ATmega32 (Either by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller) to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. A There are no errata for this revision of ATmega32. but the Device ID registered cannot be uploaded in any case. a logic one is scanned into the shift register instead of the TDI input while shifting the Device ID Register. a proposal for solving problems regarding the JTAG instruction IDCODE is presented below.ATmega32(L) Errata ATmega32 Rev.However. Alternative Problem Fix / Workaround If the Device IDs of all devices in the boundary scan chain must be captured simultaneously (for instance if blind interrogation is used). If ATmega32 is the only device in the scan chain. 15 2503F–AVR–12/03 . UpdateDR will still not work for the succeeding devices in the boundary scan chain as long as IDCODE is present in the JTAG Instruction Register. the problem is not visible. but data to preceding devices can. the boundary scan chain can be connected in such way that the ATmega32 is the fist device in the chain. and data to succeeding devices are replaced by all-ones during Update-DR.1. Issue the BYPASS instruction to the ATmega32 to select its Bypass Register while reading the Device ID Registers of preceding devices of the boundary scan chain. Note that the IDCODE instruction is the default instruction selected by the Test-Logic-Reset state of the TAP-controller. IDCODE masks data from TDI input The public but optional JTAG instruction IDCODE is not implemented correctly according to IEEE1149. Note that data to succeeding devices cannot be entered during this scan. Never read data from succeeding devices in the boundary scan chain or upload data to the succeeding devices while the Device ID Register is selected for the ATmega32. Hence. captured data from the preceding devices in the boundary scan chain are lost and replaced by all-ones.
Updated “Test Access Port – TAP” on page 217 regarding the JTAGEN fuse. 2503E-09/03 to Rev. Updated Table 15 on page 35. 3.Datasheet Change Log for ATmega32 Changes from Rev. 2503C-10/02 to Rev. Added information about PWM symmetry for Timer0 and Timer2. Added EEAR9 in EEARH in “Register Summary” on page 6. 2503F-12/03 Changes from Rev. Changes from Rev. 4. 16 ATmega32(L) 2503F–AVR–12/03 . 1. 5. 1. 2. 9. 6. Changes from Rev. Added “Power Consumption” data in “Features” on page 1. 3.Added updated “Packaging Information” on page 12. Updated and changed “On-chip Debug System” to “JTAG Interface and Onchip Debug System” on page 33. 4. Updated description for Bit 7 – JTD: JTAG Interface Disable on page 226. Added Chip Erase as a first step in“Programming the Flash” on page 282 and “Programming the EEPROM” on page 283. 2503E-09/03 Please note that the referring page numbers in this section are referred to this document. 2503D-02/03 to Rev. which do not exist. 2. 6. 8. Updated the “DC Characteristics” on page 285. 7. 2503B-10/02 to Rev. DC Characteristics and ADC Characteristics in “Electrical Characteristics” on page 285. Updated “Calibrated Internal RC Oscillator” on page 27. Added note about Differential Mode with Auto Triggering in “Prescaling and Conversion Timing” on page 202. 10. 5. Updated Absolute Maximum Ratings* . 2503C-10/02 1. Updated Table 90 on page 230. Added a note regarding JTAGEN fuse to Table 105 on page 255. 2503D-02/03 1. Added a proposal for solving problems regarding the JTAG instruction IDCODE in “Errata” on page 15. Removed reference to “Multi-purpose Oscillator” application note and “32 kHz Crystal Oscillator” application note. Added note in “Filling the Temporary Buffer (Page Loading)” on page 249 about writing to the EEPROM during an SPM Page Load. Added section “EEPROM Write During Power-down Sleep Mode” on page 20. 7. The referring revision in this section are referring to the document revision.
In the datasheet. 11.ATmega32(L) Changes from Rev. 4. Updated VIL. and 8 MHz Oscillator selections.4 – ADHSM – in SFIOR Register removed. Corrected Table 67 on page 162 (USART). Corrected typo in Table 42. 10. 2. Updated Description of OSCCAL Calibration Byte. Updated Table 119. 2503B-10/02 1. and Table 122. 6. When using External Clock there are some limitations regards to change of frequency. Added a sub section regarding OCD-system and power consumption in the section “Minimizing Power Consumption” on page 32. and IIH parameter in “DC Characteristics” on page 285. 3. 17 2503F–AVR–12/03 . IIL. 13.000 Write/Erase Cycles. This is now added in the following sections: Improved description of “Oscillator Calibration Register – OSCCAL” on page 28 and “Calibration Byte” on page 256. Added the section “Default Clock Source” on page 23. it was not explained how to take advantage of the calibration bytes for 2. Bit nr. Table 121. 4. 5. Added “Errata” on page 15. Corrected typo (WGM-bit setting) for: – – – – “Fast PWM Mode” on page 73 (Timer/Counter0) “Phase Correct PWM Mode” on page 74 (Timer/Counter0) “Fast PWM Mode” on page 118 (Timer/Counter2) “Phase Correct PWM Mode” on page 119 (Timer/Counter2) 7. 9. 12. Canged the endurance on the Flash to 10. 2503A-03/02 to Rev. This is described in “External Clock” on page 29 and Table 118 on page 287. Corrected description in Table 45 and Table 46. 8.
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