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Beagle_SRM_XM_A2_01

Beagle_SRM_XM_A2_01

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Published by Jason Kridner

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Published by: Jason Kridner on Mar 06, 2011
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11/24/2012

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This section describes the 26MHz clock section of the BeagleBoard.

8.12.2.1 26MHz Source

The BeagleBoard is designed to support two suppliers of the 26MHz oscillator. The
26MHz clock is provided by an onboard oscillator, Y1. The TPS65950 receives the
external HFCLKIN signal on ball A14 and uses it to synchronize or generate the clocks
required to operate the TPS65950 subsystems. The TPS65950 must have this clock in
order to function to the point where it can power up the BeagleBoard. This is the reason
the 26MHz clock is routed through the TPS65950.

8.12.2.2 TPS65950 Setup

When the TPS65950 enters an active state, the Processor must immediately indicate the
HFCLKIN frequency (26 MHz) by setting the HFCLK_FREQ bit field (bits [1:0]) in the
CFG_BOOT register of the TPS65950. HFCLK_FREQ has a default of being not
programmed, and in that condition, the USB subsection does not work. The three DCDC
switching supplies (VIO, VDD1, and VDD2) operate from their free-running 3-MHz
(RC) oscillators, and the PWR registers are accessed at a default 1.5-M byte.
HFCLK_FREQ must be set by the processor during the initial power-up sequence. On the
BeagleBoard, this is done by the internal boot ROM on startup.

8.12.2.3 Processor 26MHz

The 26MHz clock for the processor is provided by the TPS65950 on ball R12 through
R38, a 33 ohm resistor is providing to minimize any reflections on the clock line. The
clock signal enters via ball AE17 on the PROCESSOR.

Page 70 of 171

REF: BB_SRM_xM

BeagleBoard-xM System
Reference Manual

Revision A2

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