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Cache Memory Simulation
By: Holiano, Chaka, and Rotor
Index 0.0 1.0 1.1 1.2 1.3 1.4 1.5 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4.0 4.1 4.2 4.3 5.0 6.0
Title Tables of Contents System Overview -System Diagram -Specifications -I/O List -Direct-mapped Cache Algorithm -Main Components Description Components Descriptions -Memory Cell -Memory Cell Tests and Timing -Demux 1-to-4 -Mux 4-to-1 -Demux 1-to-4 Tests -Mux 1-to-4 Tests -4-bit Tag Comparator -4-bit Tag Comparator Tests Final System -Core Layout -Core + Pads + Test Signal Layout -Core Placement and Layout -SPR Setup -PADFrame Placement and Layout -Placement and Routing Summary -DRC Error Check -DRE Geometry Error Details (disabled check) Systems Testing -Read/Write Test -Hit/Miss Test -Hit/Miss Timing Analysis Conclusion Pin Layout
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1|P a ge
System Diagram: Tag_In 4bits Line_In 2bit Data_In 8bit We Tag Line Data F2 Tag Re Data Data Demux 4 bits Tag 4 bits Tag Data Tag Data Comparator Demux F1 4 bits 32 bits 4 bits Mux 2 bits 8 bits Status Data_Out Specification: Data width: 8-bit Tag: 4-bit Address: 4-bit Index 2-bit Replacement Policy: Direct Mapped Cache Fill Perform the following functions: Operation Read_en Write_en Read-Hit 1 X Read-Miss 1 X Write-Hit 0 1 Write-Miss 0 1 Status 1 0 X X Data Out Mem[index] Previous Data X X 2|P a ge .
It essentially takes the main memory address and indexes the address by using modulus. 3|P a ge .Inputs: From CPU: New Data: 8-bit Address: 6-bit Address<5:2> Tag: 4-bit Address<1:0> Index: 2-bit Read enable: 1-bit Write enable: 1-bit Outputs: To CPU: Dataout: 8-bit Status: 1-bit [Signifies when data is ready] Total pins required: 25pins + 1 Vdd + 1 gnd. Extra outputs: Ring Oscillator Test Signal: 1-bit Ring Oscillator Test Signal w/En: 2-bits Inverter: 2-bits Replacement Algorithm: Direct Mapped Cache Fill This is the fastest algorithm for cache replacement where the cache takes 2 least significant bits of the address as index.
Main components: Muxes/Demuxes – The memory design simulates a cache memory. In each memory line/cell we store 8-bits of actual data. read or write only. In the design. The demuxes is essential in ensuring that the signals between the components arrive at the correct memory cell for proper operation. and the Tag of the data requested. 4|P a ge . Memory – Stores all the cache memory data. and 4-bit for tag comparison. Comparator – Compares the Tag of the data from the memory. but you can read while write is on. you cannot write while read is on. Muxes are essential in ensuring that data from the memory cells can be selected for the output. read is prominent. similar to a register memory. and modified to have two signals for read and write enables. The memory cells are designed using flip-flops.
Memory Cell: 1-bit Cell: This is a single bit memory cell utilizing the Flip-flop design and a independent read or write enable signals. 5|P a ge . and Q_b is the inverted output. We have separate read and write signals for tag and for the data. 12-bit Memory Cell: Cascaded single-bit cells to form one line. Q is the output of the memory cell.
Read/Write Test: 6|P a ge .
1-bit Demux 1-to-4 1-bit Mux 4-to-1 7|P a ge .
Demux 1-to-4 Test: 8|P a ge .
Mux 4-to-1 Test: 9|P a ge .
4-bit Tag Comparator: Comparator Test: 10 | P a g e .
Core Layout: Core + Pads + Test Signals Layout: 11 | P a g e .
Core Placement and Layout: Core = 2448λ x 1232.5λ SPR Setup: 3-metal Layers: H2: Metal3 V-H2: Via2 V: Metal2 H1-V: Via1 H1: Metal1 12 | P a g e .
Core cell "Core" generated.Padframe cell "Min_Frame" generated.00 Length of nets in core : 161951.Chip cell "Library_Test_s" generated.tdb' Date and time : 05/22/2008-21:12 1 Lambda = 1.tdb Placement optimization factor : 1.00 Lambda Generated vias in core : 647 SPR elapsed time : 0:00:04 13 | P a g e .PadFrame Placement and Layout: Placement and Routing Summary: SPR SUMMARY 'mAMIs050DL_AND_PADS.5 Core area (Lambda^2) : 2751847.5 x 1128.00 x 5000.333 Micron(s) Design file : E:\reda en160 proj BU\mAMIs050DL_AND_PADS. ------------------------------------------------------------Number of standard cells : 184 Number of signals in netlist : 336 Core size in Lambda : 2438.tdb Netlist file : Project\cache_pads.000 Lambda = 3.tpr Library file : mAMIs050DL_AND_PADS. .00 Routing optimization (3 layer) : Netlength and via reduction Standard Cell Place and Route done : .00 Frame area (Lambda^2) : 25000000.25 Frame size in Lambda : 5000. .
5M DRC JOB RESULTS SUMMARY Total DRC Errors Generated 0 CPU Time 00:00:05 Real Time 00:00:05 Rules Executed 93 DRC Errors Generated by Rule Set DRC Standard Rule Set RUN-TIME DRC ERRORS AND WARNINGS 0 GEOMETRY FLAG SUMMARY ACUTE ANGLES ALL ANGLE EDGES OFFGRID ZERO-WIDTH WIRES POLYGONS WITH OVER 199 VERTICES WIRES WITH OVER 200 VERTICES SELF INTERSECTIONS WIRE JOIN/END STYLES Disabled 0 Disabled 0 0 0 0 0 CELLS WITH ERRORS FOUND RESULTS SUMMARY DRC Errors Generated 0 CPU Time 00:00:05 REAL Time 00:00:05 Input Objects 404 (404) Rules Executed 93 Geometry Flags Executed 6 Disabled Rules 18 14 | P a g e .tdb Cell Name Channel_4 (May 22 21:20:08 2008) User Name Rotor Computer Name SREDA-XP1 Memory used at start 46.10.50UM .19:30:32 Rule Set Name MOSIS AMI 0.20060718.DRC Error Check: L-Edit DRC SUMMARY REPORT EXECUTION SUMMARY Execution Start Time May 22 2008 21:20:11 L-Edit Version L-Edit Win32 12.SUBMICRON RULES_ Last Updated 10/08/2001 File Name E:\reda en160 proj BU\mAMIs050DL_AND_PADS.
15 | P a g e .DRC Geometry Error Details (Acute Angles): Error #1 Error #6 These error checks were disabled.
Systems Analysis: Single-bit Read/Write Systems Test: 16 | P a g e .
Status Hit/Miss Systems Test: Timing Analysis: Read time: tdf = 17ns tdr = 9ns 17 | P a g e .
There were unpredictable design errors on the way. All verification data appears to meet the design criteria. but none that stopped the cache memory to function normally. to determine the maximum size of cache that is possible using the type of memory cells that we have. Other improvements would be to actually use 6T SRAM cell design for the memory cell instead of Flipflops that requires more area due to more transistors in each memory cell. This is a functionality that can be added on in the future. We have not yet expanded the design to include fetching control systems to a Main Memory system. DRC errors turned up geometrical errors on the Padless frame generated by SPR. We also have not expanded the cache size. The DRC errors also determined that there were some metal to metal spacing errors in the core after SPR.Conclusion: We successfully implemented a Cache Memory Simulation device. There were also disconnected Metal layers on the Padless Frame that had to be manually connected. 18 | P a g e .
Pin Layout: Index<0> Index<1> Test2_in Test1_in Tag<0> Tag<1> Tag<2> Data<7> Data<6> Data<5> Data<4> Vd-d Data<3> Data<2> Data<1> Data<0> Test3_out Tag<3> We Re Test1_out Data_out<0> Data_out <1> Data_out <2> Data_out <3> gnd Data_out <4> Data_out <5> Data_out <6> Data_out <7> Status Data_out_sl<7> Data_out_sl<6> Data_out_sl<5> Data_out_sl<4> Data_out_sl<3> Data_out_sl<2> Data_out_sl<1> Test2_out Data_out_sl<0> Test Signals: Test 1: Inverter Test1_in 0 1 Test1_out 1 0 Test2: Ring Oscillator w/En Test2_in 0 Test2_out 0 Test 3: Ring Oscillator Test3_out 1 19 | P a g e .