VERILOG CODE:SOME BASIC EXAMPLES.

Verilog code for flip-flop with a positive-edge clock Verilog code for a flip-flop with a negative-edge clock and asynchronous clear Verilog code for the flip-flop with a positive-edge clock and synchronous set Verilog code for the flip-flop with a positive-edge clock and clock enable Verilog code for a 4-bit register with a positive-edge clock, asynchronous set and clock enable Verilog code for a latch with a positive gate Verilog code for a latch with a positive gate and an asynchronous clear. Verilog code for a 4-bit latch with an inverted gate and an asynchronous preset. Verilog code for a tristate element using a combinatorial process and always block. Verilog code for a tristate element using a concurrent assignment. Verilog code for a 4-bit unsigned up counter with asynchronous clear. Verilog code for a 4-bit unsigned down counter with synchronous set. Verilog code for a 4-bit unsigned up counter with an asynchronous load from the primary input. Verilog code for a 4-bit unsigned up counter with a synchronous load with a constant. Verilog code for a 4-bit unsigned up counter with an asynchronous clear and a clock enable. Verilog code for a 4-bit unsigned up/down counter with an asynchronous clear. Verilog code for a 4-bit signed up counter with an asynchronous reset. Verilog code for a 4-bit signed up counter with an asynchronous reset and a modulo maximum. Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear. Verilog code for an 8-bit shift-left register with a positive-edge clock, serial in and serial out. Verilog code for an 8-bit shift-left register with a negative-edge clock, a clock enable, a serial in and a serial out. Verilog code for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in and serial out. Verilog code for an 8-bit shift-left register with a positive-edge clock, a synchronous set, a serial in and a serial out. Verilog code for an 8-bit shift-left register with a positive-edge clock, a serial in and a parallel out 8-bit shift-left register with a positive-edge clock,an asynchronous parallel load, a serial in and a serial out Verilog code for an 8-bit shift-left register with a positive clock,a synchronous parallel load,a serial in and a serial out Verilog code for an 8-bit shift-left/shift-right register with a positive-edge clock, a serial in and a serial out Verilog code for a 4-to-1 1-bit MUX using an If statement. Verilog Code for a 4-to-1 1-bit MUX using a Case statement. Verilog code for a 3-to-1 1-bit MUX with a 1-bit latch. Verilog code for a 1-of-8 decoder Verilog code leads to the inference of a 1-of-8 decoder Verilog code for a 3-bit 1-of-9 Priority Encoder Verilog code for a logical shifter Verilog code for an unsigned 8-bit adder with carry in Verilog code for an unsigned 8-bit adder with carry out Verilog code for an unsigned 8-bit adder with carry in and carry out
VERILOG EXAMPLES------V.L.K Page 1

VERILOG CODE:SOME BASIC EXAMPLES.
Verilog code for an unsigned 8-bit adder/subtractor Verilog code for an unsigned 8-bit greater or equal comparator Verilog code for an unsigned 8x4-bit multiplier Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as single registers Verilog template shows the multiplication operation placed inside the always block and the pipeline stages are represented as single registers Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as single registers Verilog template shows the multiplication operation placed inside the always block and the pipeline stages are represented as single registers Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as shift registers Use templates to implement Multiplier Adder with 2 Register Levels on Multiplier Inputs in Verilog Verilog code for resource sharing single-port RAM in read-first mode single-port RAM in write-first mode single-port RAM in no-change mode single-port RAM with asynchronous read single-port RAM with "false" synchronous read single-port RAM with synchronous read (read through) Verilog code for a single-port block RAM with enable Verilog code for a dual-port RAM with asynchronous read Verilog code for a dual-port RAM with false synchronous read Verilog code for a dual-port RAM with synchronous read (read through) Verilog code for a dual-port RAM with enable on each port Verilog code for a ROM with registered output Verilog code for a ROM with registered address Verilog code for an FSM with a single process Verilog code for an FSM with two processes Verilog code for an FSM with three processes

VERILOG EXAMPLES------V.L.K

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q). always @(negedge clk or posedge clr) begin if (clr) q <= 1’b0.VERILOG CODE:SOME BASIC EXAMPLES. output q. s. d. s. end endmodule Following is Verilog code for a flip-flop with a negative-edge clock and asynchronous clear. module input output reg flop (clk. clr. reg q. d. output q. module flop (clk. else q <= d. d.K Page 3 . else q <= d. clr. d. clk. q). always @(posedge clk) begin if (s) q <= 1’b1. reg q. q. Following is the Verilog code for flip-flop with a positive-edge clock. d. q).L. input clk. d. end endmodule VERILOG EXAMPLES------V. always @(posedge clk) begin q <= d. end endmodule Following is Verilog code for the flip-flop with a positive-edge clock and synchronous set. input clk. q. module flop (clk.

reg q. module latch (g. d. asynchronous set and clock enable.K Page 4 . d. reg q. always @(g or d) begin if (g) q <= d.VERILOG CODE:SOME BASIC EXAMPLES. ce. else if (ce) q <= d. always @(posedge clk or posedge pre) begin if (pre) q <= 4’b1111. end endmodule VERILOG EXAMPLES------V. pre. Following is Verilog code for the flip-flop with a positive-edge clock and clock enable. always @(posedge clk) begin if (ce) q <= d. end endmodule Following is the Verilog code for a latch with a positive gate. q). ce. output q. q). output q. end endmodule Following is Verilog code for a 4-bit register with a positive-edge clock. d. output [3:0] q. ce.L. d. reg [3:0] q. input clk. module flop (clk. input g. q). input clk. pre. module flop (clk. ce. d. input [3:0] d.

Following is the Verilog code for a latch with a positive gate and an asynchronous clear. reg [3:0] q. clr. module latch (g. pre. d. module latch (g.VERILOG CODE:SOME BASIC EXAMPLES. pre. q).L. end endmodule Following is Verilog code for a 4-bit latch with an inverted gate and an asynchronous preset. output [3:0] q. d. q). always @(g or d or clr) begin if (clr) q <= 1’b0. reg q. else if (g) q <= d. else if (~g) q <= d. output q. always @(g or d or pre) begin if (pre) q <= 4’b1111. input g. input g. end endmodule VERILOG EXAMPLES------V. clr. input [3:0] d.K Page 5 . d.

end assign q = tmp. always @(t or i) begin if (~t) o = i. q). else o = 1’bZ. module counter (clk. o). assign o = (~t) ? i: 1’bZ. s.VERILOG CODE:SOME BASIC EXAMPLES. endmodule Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear. i. module counter (clk. input clk. output o. module three_st (t. output o.K Page 6 . s. output [3:0] q. input clk. output [3:0] q. q). reg [3:0] tmp. else tmp <= tmp + 1’b1. reg o. reg [3:0] tmp.L. input t. endmodule Following is the Verilog code for a 4-bit unsigned down counter with synchronous set. end endmodule Following is the Verilog code for a tristate element using a concurrent assignment. i. clr. o). clr. always @(posedge clk) begin if (s) VERILOG EXAMPLES------V. i. Following is Verilog code for a tristate element using a combinatorial process and always block. module three_st (t. i. input t. always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000.

module counter (clk. endmodule Following is the Verilog code for a 4-bit unsigned up counter with a synchronous load with a constant. load. else tmp <= tmp + 1’b1. reg [3:0] tmp.K Page 7 . input [3:0] d. module counter (clk. reg [3:0] tmp. output [3:0] q.L. endmodule Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous clear and a clock enable. input clk. end assign q = tmp. end assign q = tmp. VERILOG EXAMPLES------V.1’b1. always @(posedge clk or posedge load) begin if (load) tmp <= d. end assign q = tmp. d. else tmp <= tmp . always @(posedge clk) begin if (sload) tmp <= 4’b1010. input clk. output [3:0] q. sload. q). endmodule Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous load from the primary input. else tmp <= tmp + 1’b1. sload. q).VERILOG CODE:SOME BASIC EXAMPLES. load. tmp <= 4’b1111.

1’b1. up_down. clr. else if (ce) tmp <= tmp + 1’b1. output [3:0] q. reg signed [3:0] tmp. clr. endmodule Following is the Verilog code for a 4-bit unsigned up/down counter with an asynchronous clear. reg [3:0] tmp. else tmp <= tmp + 1’b1. q). ce. up_down. end assign q = tmp. module counter (clk. output signed [3:0] q. ce. always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000. endmodule Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset. end assign q = tmp. else tmp <= tmp . always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000. clr. q).K Page 8 . clr. reg [3:0] tmp. input clk. module counter (clk. always @ (posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000. output [3:0] q.L. q). clr. else if (up_down) tmp <= tmp + 1’b1. endmodule VERILOG EXAMPLES------V. module counter (clk. clr. input clk. end assign q = tmp.VERILOG CODE:SOME BASIC EXAMPLES. input clk.

output so. always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000. so). MAX = (MAX_SQRT*MAX_SQRT). clr.si. input clk. input [3:0] d. module accum (clk.L. else tmp <= tmp + d. end assign q = tmp.VERILOG CODE:SOME BASIC EXAMPLES. VERILOG EXAMPLES------V. always @ (posedge clk or posedge clr) begin if (clr) cnt <= 0. reg [7:0] tmp. si. endmodule Following is the Verilog code for a 4-bit unsigned up accumulator with an asynchronous clear. parameter MAX_SQRT = 4. else cnt <= (cnt + 1) %MAX. always @(posedge clk) begin tmp <= tmp << 1. endmodule Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock. serial in and serial out. clr. output [3:0] q. module shift (clk. output [MAX_SQRT-1:0] q. reg [3:0] tmp. Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset and a modulo maximum. clr. input clk. module counter (clk. q). q). d. end assign q = cnt. reg [MAX_SQRT-1:0] cnt.K Page 9 . input clk. clr.

tmp[0] <= si. asynchronous clear. ce. ce. tmp[0] <= si. si. end assign so = tmp[7]. a synchronous set. endmodule Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock.K Page 10 .VERILOG CODE:SOME BASIC EXAMPLES. input clk. reg [7:0] tmp. module shift (clk. so).L. reg [7:0] tmp. input clk. so). a serial in and a serial out. endmodule Following is the Verilog code for an 8-bit shift-left register with a negative-edge clock. clr. always @(negedge clk) begin if (ce) begin tmp <= tmp << 1. serial in and serial out. si. si. module shift (clk. si. end end assign so = tmp[7]. si}. output so. s. always @(posedge clk or posedge clr) begin if (clr) tmp <= 8’b00000000. end assign so = tmp[7]. s. endmodule Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock. so). clr. else tmp <= {tmp[6:0]. input clk. si. a serial in and a serial out. si. VERILOG EXAMPLES------V. a clock enable. module shift (clk. output so.

input [7:0] d. always @(posedge clk or posedge load) begin if (load) tmp <= d.L. a serial in and a serial out. else tmp <= {tmp[6:0]. reg [7:0] tmp.K Page 11 . module shift (clk. si. output [7:0] po. input clk. input clk. reg [7:0] tmp. always @(posedge clk) begin tmp <= {tmp[6:0]. si. si}. endmodule VERILOG EXAMPLES------V. an asynchronous parallel load. module shift (clk. else tmp <= {tmp[6:0]. si. endmodule Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock. si. end assign so = tmp[7]. reg [7:0] tmp.VERILOG CODE:SOME BASIC EXAMPLES. so). load. always @(posedge clk) begin if (s) tmp <= 8’b11111111. end assign so = tmp[7]. endmodule Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock. a serial in and a parallel out. load. end assign po = tmp. si}. si}. po). output so. d. output so.

input clk. module mux (a.d. b. si. output o. left_right. else tmp <= {tmp[6:0]. si. output po. always @(posedge clk) begin if (sload) tmp <= d. endmodule Following is the Verilog code for a 4-to-1 1-bit MUX using an If statement.L. po). s. always @(a or b or c or d or s) begin if (s == 2’b00) o = a. input clk. si}. module shift (clk.VERILOG CODE:SOME BASIC EXAMPLES. input [1:0] s.b. else tmp <= {si. module shift (clk. end assign so = tmp[7]. output so. d. input [7:0] d. else if (s == 2’b01) o = b. end assign po = tmp. d.K Page 12 . a serial in and a serial out. tmp[7:1]}. always @(posedge clk) begin if (left_right == 1’b0) tmp <= {tmp[6:0]. sload. reg o. si}.c. a serial in and a serial out. o). Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock. input a. so). VERILOG EXAMPLES------V. c. left_right. reg [7:0] tmp. si. reg [7:0] tmp. si. sload. endmodule Following is the Verilog code for an 8-bit shift-left/shift-right register with a positive-edge clock. a synchronous parallel load.

always @(a or b or c or d or s) begin case (s) 2’b00 : o = a. input [1:0] s. end endmodule Following is the Verilog Code for a 4-to-1 1-bit MUX using a Case statement. end endmodule Following is the Verilog code for a 1-of-8 decoder. 2’b10 : o = c. reg o.K Page 13 . o).VERILOG CODE:SOME BASIC EXAMPLES. c. else if (s == 2’b10) o = c. module mux (a. c. s. 2’b01 : o = b. always @(a or b or c or d or s) begin if (s == 2’b00) o = a. o). d. d. else o = d. c. c. reg o. b. input a.L. input a. b. input [1:0] s. d. s. d. b. output o. module mux (a. else if (s == 2’b10) o = c. default : o = d. VERILOG EXAMPLES------V. b. endcase end endmodule Following is the Verilog code for a 3-to-1 1-bit MUX with a 1-bit latch. output o. else if (s == 2’b01) o = b.

3’b001 : res = 8’b00000010. 3’b011 : res = 8’b00001000. 3’b010 : res = 8’b00000100. output [7:0] res. always @(sel or res) begin case (sel) 3’b000 : res = 8’b00000001. 3’b001 : res = 8’b00000010. res). module mux (sel. 3’b011 : res = 8’b00001000. input [7:0] sel. reg [2:0] code. 3’b101 : res = 8’b00100000. input [2:0] sel.VERILOG CODE:SOME BASIC EXAMPLES.K Page 14 . VERILOG EXAMPLES------V. input [2:0] sel. 3’b010 : res = 8’b00000100. 3’b110 : res = 8’b01000000. endcase end endmodule Following Verilog code leads to the inference of a 1-of-8 decoder. reg [7:0] res. res). output [7:0] res. reg [7:0] res. always @(sel or res) begin case (sel) 3’b000 : res = 8’b00000001. 3’b101 : res = 8’b00100000.L. 3’b100 : res = 8’b00010000. default : res = 8’b10000000. output [2:0] code. 3’b100 : res = 8’b00010000. code). endcase end endmodule Following is the Verilog code for a 3-bit 1-of-9 Priority Encoder. // 110 and 111 selector values are unused default : res = 8’bxxxxxxxx. module priority (sel. module mux (sel. always @(sel) begin if (sel[0]) code = 3’b000.

module input input input output adder(a. b. Following is the Verilog code for a logical shifter. input [1:0] sel. sum). module lshift (di. endmodule VERILOG EXAMPLES------V. (sel[3]) = 3’b011.L. sel. ci. assign sum = a + b + ci. ci. 2’b01 : so = di << 1. [7:0] a. = 3’bxxx. so). (sel[2]) = 3’b010. always @(di or sel) begin case (sel) 2’b00 : so = di. (sel[6]) = 3’b110. (sel[5]) = 3’b101. (sel[4]) = 3’b100. (sel[7]) = 3’b111. endcase end endmodule Following is the Verilog code for an unsigned 8-bit adder with carry in. 2’b10 : so = di << 2. else if code else if code else if code else if code else if code else if code else if code else code end endmodule (sel[1]) = 3’b001. reg [7:0] so. default : so = di << 3. output [7:0] so. [7:0] sum.K Page 15 . input [7:0] di.VERILOG CODE:SOME BASIC EXAMPLES. [7:0] b.

sum. [8:0] tmp. co. assign tmp = a + b. ci. res). input [7:0] b. [7:0] a. co). oper. endmodule Following is the Verilog code for an unsigned 8-bit adder/subtractor. [7:0] b. module addsub(a.K Page 16 . [7:0] sum. co. input oper. ci. reg [7:0] res. assign sum = tmp [7:0]. assign co = tmp [8]. module input input output output wire adder(a. end endmodule VERILOG EXAMPLES------V. sum. assign tmp = a + b + ci. assign sum = tmp [7:0]. b. b. endmodule Following is the Verilog code for an unsigned 8-bit adder with carry in and carry out. module input input input output output wire adder(a. b. [7:0] b. input [7:0] a. else res = a . output [7:0] res.b. co). [8:0] tmp.L. [7:0] sum. always @(a or b or oper) begin if (oper == 1’b0) res = a + b. assign co = tmp [8]. Following is the Verilog code for an unsigned 8-bit adder with carry out.VERILOG CODE:SOME BASIC EXAMPLES. [7:0] a.

cmp). pipe_1 <= mult_res. res). input [7:0] a. pipe_2. assign cmp = (a >= b) ? endmodule 1’b1 : 1’b0. Following is the Verilog code for an unsigned 8-bit greater or equal comparator. input [7:0] b. [3:0] b. [35:0] mult. b_in <= b. mult <= pipe_3. pipe_2 <= pipe_1. [35:0] pipe_1. module compar(a. [17:0] a. pipe_3 <= pipe_2. b. [7:0] a. pipe_3. clk. b_in. mult). Following is the Verilog code for an unsigned 8x4-bit multiplier. module input input output compar(a. assign mult_res = a_in * b_in.K Page 17 . module input input input output reg reg wire reg mult(clk. always @(posedge clk) begin a_in <= a.VERILOG CODE:SOME BASIC EXAMPLES. [17:0] a_in. a. b. assign res = a * b. [35:0] mult. output cmp. [11:0] res.L. end VERILOG EXAMPLES------V. [35:0] mult_res. b. endmodule Following Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as single registers. [17:0] b.

module input input input output reg reg wire reg mult(clk. pipe_3. input [17:0] a. pipe_1 <= mult_res. pipe_2. reg [17:0] a_in. a. pipe_2 <= mult_res. [17:0] a. b_in <= b. b. mult). b_in <= b. mult <= pipe_3. clk. [17:0] a_in. mult). endmodule Following Verilog template shows the multiplication operation placed inside the always block and the pipeline stages are represented as single registers. VERILOG EXAMPLES------V. assign mult_res = a_in * b_in. [35:0] mult. reg [35:0] mult_res.VERILOG CODE:SOME BASIC EXAMPLES. always @(posedge clk) begin a_in <= a. always @(posedge clk) begin a_in <= a. [17:0] b. reg [35:0] pipe_2. end endmodule Following Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as single registers. input clk. [35:0] pipe_1. b. [35:0] mult.L. pipe_3. b_in. pipe_3 <= pipe_2. mult <= pipe_3. [35:0] mult_res. mult_res <= a_in * b_in.K Page 18 . reg [35:0] mult. b_in. module mult(clk. pipe_3 <= pipe_2. pipe_2 <= pipe_1. a. output [35:0] mult. input [17:0] b.

[35:0] mult_res. mult).pipe_regs[1]. pipe_3. mult_res <= a_in * b_in. reg [35:0] mult_res. [35:0] mult. always @(posedge clk) begin a_in <= a. [17:0] a. input [17:0] b.pipe_regs[1]}. clk. pipe_regs[3]. b. reg [17:0] a_in.pipe_regs[2]. input [17:0] a. end VERILOG EXAMPLES------V. b_in.pipe_regs[0]} <= {mult. {pipe_regs[3]. b_in <= b. input clk. [17:0] a_in. output [35:0] mult. b_in. module input input input output reg reg wire reg mult3(clk. module mult(clk. mult). [35:0] mult. pipe_2 <= mult_res. b.L. a. [17:0] b. [35:0] pipe_regs [3:0].pipe_regs[2]. end endmodule Following Verilog template shows the multiplication operation placed outside the always block and the pipeline stages represented as shift registers. reg [35:0] mult. b_in <= b. a. always @(posedge clk) begin a_in <= a. assign mult_res = a_in * b_in. reg [35:0] pipe_2.K Page 19 .VERILOG CODE:SOME BASIC EXAMPLES. end endmodule Following Verilog template shows the multiplication operation placed inside the always block and the pipeline stages are represented as single registers. pipe_3 <= pipe_2. mult <= pipe_3.

c. VERILOG EXAMPLES------V. end endmodule Following templates show a single-port RAM in read-first mode. c. a_reg2 <= a_reg1.c. input [07:0] a. input [7:0] a. module addsub(a. wire [15:0] multaddsub. output [7:0] res. input oper. input [07:0] b. input [7:0] c. oper. b. input [07:0] c. res). assign res = multaddsub. b_reg1. end assign multaddsub = a_reg2 * b_reg2 + c. b. input [7:0] b.K Page 20 .VERILOG CODE:SOME BASIC EXAMPLES. else res = a . a_reg2.L. endmodule Following is the Verilog code for resource sharing. output [15:0] res. reg [07:0] a_reg1. endmodule Following templates to implement Multiplier Adder with 2 Register Levels on Multiplier Inputs in Verilog. reg [7:0] res. module mvl_multaddsub1(clk. b_reg2 <= b_reg1. b_reg2. res). always @(a or b or c or oper) begin if (oper == 1’b0) res = a + b. input clk. b_reg1 <= b. a. always @(posedge clk) begin a_reg1 <= a.

module raminfr (clk. di. reg [3:0] do. always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di. addr.VERILOG CODE:SOME BASIC EXAMPLES. we. en. input clk. input [3:0] di. module raminfr (clk. input clk. di. do <= RAM[addr]. module raminfr (clk. input en.L. end end assign do = RAM[read_addr]. we. en. addr. input [4:0] addr. input we. input [3:0] di. end end endmodule Following templates show a single-port RAM in write-first mode. input clk. we. do). reg [3:0] RAM [31:0]. reg [3:0] RAM [31:0]. en. reg [4:0] read_addr. input [4:0] addr. output [3:0] do. do). read_addr <= addr. di. input [4:0] addr. input en. input en.K Page 21 . input we. input we. endmodule Following templates show a single-port RAM in no-change mode. always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di. output [3:0] do. do). addr. VERILOG EXAMPLES------V.

reg [3:0] do. a. always @(posedge clk) begin if (we) ram[a] <= di. input [3:0] di. reg [3:0] ram [31:0]. input [4:0] a. input [3:0] di. reg [3:0] ram [31:0]. input clk.L. a. end assign do = ram[a]. we. output [3:0] do. do). always @(posedge clk) begin if (en) begin if (we) RAM[addr] <= di. input we. end end endmodule Following is the Verilog code for a single-port RAM with asynchronous read. di. input [4:0] a. do <= ram[a]. else do <= RAM[addr]. module raminfr (clk. reg [3:0] do. end endmodule VERILOG EXAMPLES------V. output [3:0] do. do). always @(posedge clk) begin if (we) ram[a] <= di. module raminfr (clk. endmodule Following is the Verilog code for a single-port RAM with "false" synchronous read. input [3:0] di. di. we. output [3:0] do.VERILOG CODE:SOME BASIC EXAMPLES. input we.K Page 22 . input clk. reg [3:0] RAM [31:0].

we. en. dpra.VERILOG CODE:SOME BASIC EXAMPLES.L. input [4:0] a. module raminfr (clk. reg [3:0] ram [31:0]. end end assign do = ram[read_a]. output [3:0] do. a. input clk. di. always @(posedge clk) begin if (we) ram[a] <= di. spo. reg [3:0] ram [31:0]. a. di. we. input [3:0] di. read_a <= a. input we. reg [4:0] read_a. input [3:0] di. read_a <= a. endmodule Following is the Verilog code for a single-port block RAM with enable. di. module raminfr (clk. input en. dpo). reg [4:0] read_a. we. output [3:0] do. Following is the Verilog code for a single-port RAM with synchronous read (read through). a. end assign do = ram[read_a]. input we. do). module raminfr (clk. always @(posedge clk) begin if (en) begin if (we) ram[a] <= di. input clk. endmodule Following is the Verilog code for a dual-port RAM with asynchronous read. VERILOG EXAMPLES------V. do). input [4:0] a.K Page 23 .

[3:0] spo.K Page 24 . end assign spo = ram[a]. module input input input input input output raminfr (clk. we. input [4:0] a. output [3:0] spo. a. output [3:0] dpo. input [3:0] di. input [3:0] di. clk. input clk. input [4:0] dpra. di. assign dpo = ram[dpra]. dpo).L. we. dpo). input we. module raminfr (clk. endmodule Following is the Verilog code for a dual-port RAM with false synchronous read. [4:0] dpra. [4:0] a. input clk. input we. end endmodule Following is the Verilog code for a dual-port RAM with synchronous read (read through). reg [3:0] ram [31:0]. output [3:0] spo. we. input [4:0] a. output [3:0] dpo. dpra. dpra. reg [3:0] dpo. di. input [4:0] dpra. dpo = ram[dpra]. always @(posedge clk) begin if (we) ram[a] <= di. always @(posedge clk) begin if (we) ram[a] <= di. VERILOG EXAMPLES------V. reg [3:0] ram [31:0]. spo. [3:0] di. spo. reg [3:0] spo.VERILOG CODE:SOME BASIC EXAMPLES. a. spo = ram[a].

read_a <= a. en. endmodule Following is Verilog code for a ROM with registered output. reg [3:0] ram [31:0]. input clk. endmodule Following is the Verilog code for a dual-port RAM with enable on each port. addrb.K Page 25 . reg [4:0] read_dpra. always @(posedge clk) begin if (we) ram[a] <= di. addra. always @(posedge clk) begin if (ena) begin if (wea) begin ram[addra] <= dia. read_addrb. enb. doa. dia. enb. dob). ena. reg [4:0] read_addra. assign dpo = ram[read_dpra]. input [3:0] dia. input en. wea. wea. assign dob = ram[read_addrb]. end assign spo = ram[read_a]. end end end always @(posedge clk) begin if (enb) begin read_addrb <= addrb. input clk. input [4:0] addra. VERILOG EXAMPLES------V.VERILOG CODE:SOME BASIC EXAMPLES. data). module raminfr (clk. module rominfr (clk. end end assign doa = ram[read_addra]. dob. addr. output [3:0] dpo. read_dpra <= dpra. reg [3:0] ram [31:0]. output [3:0] doa. ena. input [4:0] addr.L. reg [4:0] read_a. addrb.

K Page 26 . 4’b0000. 4’b0010. reg [4:0] raddr. 4’b0010.L. 4’b0010. 4’b1100. 4’b0100. 4’b0000. 4’b1110. always @(posedge clk) begin if (en) raddr <= addr. 4’b0100. module rominfr (clk. 4’b0010. 4’b0010. 4’b1100. 4’b0010. 4’b1100. 4’b0000. 4’b1010. input [4:0] addr. 4’b1110. input clk.VERILOG CODE:SOME BASIC EXAMPLES. data). addr. en. 4’b0100. 4’bXXXX. 4’b1110. Following is Verilog code for a ROM with registered address. input en. 4’b1010. output reg [3:0] data. end always @(raddr) begin if (en) case(raddr) 4’b0000: 4’b0001: 4’b0010: 4’b0011: 4’b0100: 4’b0101: 4’b0110: 4’b0111: 4’b1000: data data data data data data data data data = = = = = = = = = 4’b0010. output reg [3:0] data. 4’b1010. 4’b1010. 4’b1010. always @(posedge clk) begin if (en) case(addr) 4’b0000: data 4’b0001: data 4’b0010: data 4’b0011: data 4’b0100: data 4’b0101: data 4’b0110: data 4’b0111: data 4’b1000: data 4’b1001: data 4’b1010: data 4’b1011: data 4’b1100: data 4’b1101: data 4’b1110: data 4’b1111: data default: data endcase end endmodule <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= 4’b0010. VERILOG EXAMPLES------V.

4’b0000. 4’b0100. reset. Following is the Verilog code for an FSM with a single process.VERILOG CODE:SOME BASIC EXAMPLES. 4’b1010. x1. end end s2: begin state <= s4. outp <= 1’b0.L. parameter s4 = 2’b11. 4’b1100. outp <= 1’b1. reg outp. output outp. 4’bXXXX. parameter s3 = 2’b10. 4’b0010. end s3: begin state <= s4. reg [1:0] state. parameter s2 = 2’b01. outp <= 1’b1. end else begin case (state) s1: begin if (x1 == 1’b1) begin state <= s2. end endcase end end VERILOG EXAMPLES------V. outp). end s4: begin state <= s1. 4’b1001: 4’b1010: 4’b1011: 4’b1100: 4’b1101: 4’b1110: 4’b1111: default: endcase end endmodule data data data data data data data data = = = = = = = = 4’b0010. x1. end else begin state <= s3. reset. always @(posedge clk or posedge reset) begin if (reset) begin state <= s1. outp <= 1’b0. parameter s1 = 2’b00. outp <= 1’b1.K Page 27 . module fsm (clk. outp <= 1’b1. 4’b1110. input clk.

L. s3: state <= s4. endmodule Following is the Verilog code for an FSM with two processes. parameter s3 = 2’b10. outp). parameter s3 = 2’b10. parameter s1 = 2’b00. output outp. endcase end end always @(state) begin case (state) s1: outp = 1’b1. module fsm (clk. reg [1:0] state. x1. x1. else begin case (state) s1: if (x1 == 1’b1) state <= s2. s4: outp = 1’b0. always @(posedge clk or posedge reset) begin VERILOG EXAMPLES------V. reg outp. always @(posedge clk or posedge reset) begin if (reset) state <= s1. x1. output outp. parameter s1 = 2’b00. else state <= s3. parameter s4 = 2’b11. s3: outp = 1’b0. reset. s4: state <= s1. reg outp. x1. reset. s2: state <= s4. module fsm (clk. outp). parameter s4 = 2’b11.K Page 28 . input clk. endcase end endmodule Following is the Verilog code for an FSM with three processes. parameter s2 = 2’b01.VERILOG CODE:SOME BASIC EXAMPLES. reset. reg [1:0] next_state. input clk. reg [1:0] state. reset. s2: outp = 1’b1. parameter s2 = 2’b01.

K Page 29 .L. s3: next_state = s4. else next_state = s3. s4: next_state = s1.VERILOG CODE:SOME BASIC EXAMPLES. s2: next_state = s4. else state <= next_state. end always @(state or x1) begin case (state) s1: if (x1 == 1’b1) next_state = s2. endcase end VERILOG EXAMPLES------V. if (reset) state <= s1.

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