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CMOS layout

CMOS layout

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CMOS 1 Drawing CMOS Layout for IC Design Beginning Level

DTT6530

CMOS 1 Drawing CMOS Layout for IC Design Beginning Level

January 1996

Technical Publications and Training Design Technology

Intel Corporation Copyright  Intel Corporation 1996 Document requests: http://ats. msulliv@scdt .intel. RN4-43.Published by Technical Publications and Training. FM5-43. psandova@pcocd2 Mary Sullivan. 356-6348. 765-5576.com/Docs/ Technical information: Document comments: Phil Sandoval.

............................................................................................................................................. 2-6 Chapter 3: How to Interpret Logic-level Schematics Chapter Overview ............. 2-5 What Are the Design Data Representations? ..............c: Identify the Parts of the Logic-level Schematic ..........................................................................................b: Identify the Logic Symbols of the Logic-level Schematic ....CMOS 1 0 Table of Contents Chapter 1: Introduction to the Course Introduction to the Course........................... 3-12 Intel Confidential i ............. 3-6 Logic Symbols of the Basic Logic Functions ...............a: Identify the Nodes of the Logic-level Schematic ............................................................................................................................................ 1-2 Chapter 2: Introduction to CMOS 1 Drawing CMOS Layout for IC Design Beginning Level Chapter Overview . 2-3 How Is an IC Designed? ....... 3-10 Lab 3-1..................................... 3-8 Lab 3-1................................................................................................................................................................................................................................. 3-5 Lab 3-1........... 3-2 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic Lesson Overview........................ 3-9 Logic-level Schematic Drawing Conventions ............................................................................ 2-2 What is an IC?...................... 2-4 Basic Layout Design Tasks............................................................. 3-4 What Is a Logic-level Schematic? ....................

.......... 4-6 Nodes of a Transistor-level Schematic ......................................... 3-14 What Are the Standard Logic Functions? .............. 4-10 Lab 4-1: Identify the Parts of Transistor-level Schematics ....b: Determine the Number of Columns and Rows for a Truth Table...................................................................................................................................................................................... 3-36 Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic Chapter Overview ..............................................d: Describe Logic Functions with Truth Tables .......................................................................................... 4-19 Practice 4-2: Verify the Transistor-level Function of the Logic Symbols ........................................... 4-18 How Are Truth Table Values Verified? ......................................................................................................................................CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol Lesson Overview........................................................... 3-18 What Are Truth Tables? ................................. 4-12 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol Lesson Overview........................ 3-23 Practice 3-2...................... 3-19 How Is the Number of Rows for a Truth Table Determined? ............ 3-20 Practice 3-2..... 3-26 Output Values of the Truth Tables ............ 4-17 Values that Turn a Transistor On or Off ................ 3-27 Practice 3-2............ 4-9 Transistor Representations of the Logic-level Schematics ............................................................................................................................................................... 4-2 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic Lesson Overview................. 4-5 What Is a Transistor? ............................................................................................................. 4-22 ii Intel Confidential .......................................a: Evaluate Boolean Algebra Equations ........................................................................................................ 3-21 How Are Input Values for a Truth Table Filled In? ..................................... 3-15 Practice 3-2........................................c: Fill in the Input Values for a Truth Table ...... 4-4 What Is a Transistor-level Schematic?..................... 3-29 Chapter Summary ..................................................

.......................................... 4-29 How Is a Logic-level Schematic Converted to a Transistor-level Schematic? ................................................................................................... 4-34 How Is a Complex Logic-level Schematic Converted to N-Type Transistors? .......................................................c: Convert Complex Logic-level Schematics to Transistor-level Schematics.................................... 5-5 Layers of the Transistor Cross Section ........ 4-44 Chapter Summary ................................... 4-43 Lab 4-3................................................................................................................................ 5-6 Layers of the Die Cross Section........................................................................................... 4-32 What is Complex Logic? ...................................... 4-38 How Is a Complex Logic-level Schematic Converted to P-Type Transistors? ................................................................................... 4-45 Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic Chapter Overview ........................................... 5-8 How Is a Transistor Turned On or Off? ......................................................................................................................................... 5-4 What Is a Cross Section?.............................................................................................................. 5-17 Intel Confidential iii ...................................... 4-33 Order of the Series Transistors ...................... 4-40 Lab 4-3..................................... 5-16 How Are Process Design Rules Identified on the Transistor Cross Section? ................................................................................................... 5-15 Basic Process Design Rules .......................................a: Convert Complex Logic-level Schematics to N-Type Transistors ..............CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic Lesson Overview................................................. 5-10 Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section Lesson Overview.................................... 5-7 What Is a Diode?..................... 4-28 Logic Functions Defined with Transistors ....................................................... 5-14 What Is a Design Rule? .................... 5-2 Lesson 5-1: How to Identify a Transistor on the IC Cross Section Lesson Overview......................................................b: Convert Complex Logic-level Schematics to P-Type Transistors ............. 4-30 Practice 4-3: Convert a Logic-level Schematic to a Transistor-level Schematic ................... 4-35 Lab 4-3..............

....... 5-23 How Is a Stick Diagram Created? .................................... 5-31 Lesson 5-4: How to Get Better Layout Density with Node Sharing Lesson Overview.................................................................................................................................. 5-43 Lab 5-5...........................................................................................................................................................a: Calculate Resistance Values ..........................................b: Convert Units of Measure ............. 5-21 Legend for a Stick Diagram.b: Estimate the Width of a Layout Drawing from a Stick Diagram ........................ 5-29 Lab 5-3....................a: Create a Stick Diagram ........................................... 5-40 Area Calculation..................... 5-58 iv Intel Confidential ....... 5-26 How Is the Width of a Layout Drawing Estimated from a Stick Diagram? ..... 5-53 How Is Sheet Resistance Calculated? ............................................................................................................................................................ 5-44 Average Area per Transistor Calculation ........................................c: Calculate the Average Area per Transistor .......................... 5-51 Lab 5-6........................................................ 5-22 Series and Parallel Transistors in a Stick Diagram . 5-47 Lesson 5-6: How to Calculate Resistance Lesson Overview.................................................................................................................b: Calculate Sheet Resistance..................................................................................................... 5-46 Lab 5-5............... 5-36 Lab 5-4: Use Node Sharing to Increase Density ......CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram Lesson Overview.......................................... 5-34 What Is Node Sharing? .................................................. 5-24 Lab 5-3............ 5-50 What Is Resistance? ..................................... 5-38 Lesson 5-5: How to Estimate Area Lesson Overview............................................ 5-41 Lab 5-5...................a: Calculate Area ...................................................... 5-56 Lab 5-6........................................................... 5-42 Units of Measure Conversion ....................... 5-35 How Is Node Sharing Achieved? .......................................................... 5-20 What Is a Stick Diagram?..............................................................................................................................................................................................

.................................................. 5-75 How Is a Transistor Drawn with a Bent Gate? ................................... 5-60 What Is a Layout Drawing? .. 5-70 Lab 5-8: Draw a Layout Drawing with a Standard Cell Template ......................................................................... 5-71 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions Lesson Overview................................................ 5-77 Lab 5-9: Draw Layout to Meet Layout Restrictions ................... 5-61 What Is Transistor Size? ..................................................... 5-64 Visually Verifying a Layout Drawing .................. 5-80 Appendix A: Glossary Terms ..................................... 5-79 Chapter Summary .................. 5-66 Lesson 5-8: How to Draw Layout with a Standard Cell Template Lesson Overview........................................................................CMOS 1 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing Lesson Overview.................................. 5-68 What Is a Standard Cell Template? .............................................b: Visually Verify a Layout Drawing ...................................................................................................................................................................... 5-63 Lab 5-7................................................................................. 5-74 How Is a Transistor Drawn with Multiple Legs? .........................A-2 Intel Confidential v ........................................................................... 5-69 How Is a Layout Drawing Drawn with a Standard Cell Template?................................... 5-62 How Is a Stick Diagram Converted to a Layout Drawing? ...................................................a: Convert a Stick Diagram to a Layout ..................................................................................................... 5-65 Lab 5-7................................................

CMOS 1 vi Intel Confidential .

CMOS 1 Chapter 1: Introduction to the Course 01 Chapter 1: Introduction to the Course Intel Confidential 1-1 .

which gives hands-on experience. The labels refer to the contents of that paragraph or block of information. A page number on the upper left corner of the foil indicates the corresponding page in your course guide.Chapter 1: Introduction to the Course CMOS 1 Introduction to the Course Introduction The goal of this course is to provide the information and practice needed to create layout drawings with CMOS technology. G The foils follow the sequence of the student material but contain only key points. — Concept: Provides definitions and examples — Process: Explains how something works — Procedure (practice/lab): Tells how to perform a task — Guidelines: Provide suggestions for performing a task or tackling a problem G Margin labels (labels on the left side of the page) provide visual cues to help increase information access and retrieval time. The instructor presents information using foils. G Format Information is categorized as follows. the number of lessons depending on the complexity and scope of the topic being taught. 1-2 Intel Confidential . A chapter is devoted to each task as follows: G G G Structure Interpret Logic-Level Schematics Convert Logic-Level Schematics to Transistor-Level Schematics Create Layout Drawings from Transistor-Level Schematics Chapters are divided into lessons. Each lesson has a practice or lab. The course material is presented in a mapped-page format. This course is structured around the three main tasks of the basic layout design process. Objectives Every chapter and lesson has a clearly stated objective so that you will know exactly what you are expected to learn.

Mary Kamprath. Also. Mark Drake. Gell Gellman. Manhaz Padash. Lynn Olson.CMOS 1 Chapter 1: Introduction to the Course Introduction to the Course (continued) Practices and Labs You will be given two types of exercises. G G Practice: Reinforces material for general knowledge building. Intel Confidential 1-3 . Phil Sandoval. Lab: Reinforces material directly related to a job task. who created the class that this one is based on. Brent Jensen. Acknowledgments Special thanks go to Phil Sandoval. Barbara Drummer. Myrna Irwin. and Seema Shafajoo. thanks to all who helped with the content of this class: Brian Cyphert.

Chapter 1: Introduction to the Course CMOS 1 1-4 Intel Confidential .

CMOS 1 Chapter 2: Introduction to CMOS 1 11 Chapter 2: Introduction to CMOS 1 Intel Confidential 2-1 .

............... How Is an IC Designed? . In this class.................. you will learn how to convert logic-level schematics to transistor-level schematics to layout drawings.... Basic Layout Design Tasks ..... What Are the Design Data Representations? .......................Chapter 2: Introduction to CMOS 1 CMOS 1 Chapter Overview Introduction This class covers the major job tasks for creating basic CMOS layout......................................... 2-2 Intel Confidential ........................... Additional knowledge is presented to aid in the understanding of the layout design process.................... and how to create layout drawings to design specifications..... The following topics are covered in this chapter: Topics Page Objectives Topics What is an IC? ............................................................................................

include the following: Definition Examples Type of IC microprocessor/CPU memory micro-controller imbedded processor/controller computers Use data storage and retrieval communication between ICs printers. Examples of ICs. which holds 75% of the marketplace. Producing ICs is the primary business of Intel. along with their applications. An IC is a single piece of silicon that performs various electronic functions. The graphic below shows a silicon wafer and one IC in the wafer. Silicon Wafer IC Example Periphery: Connections are made to the periphery of the IC with wires.CMOS 1 Chapter 2: Introduction to CMOS 1 What is an IC? Introduction Integrated Circuits (ICs) are used in millions of applications. Intel Confidential 2-3 . anti-lock brakes CMOS Technology Complementary Metal Oxide Semiconductor (CMOS) is the name of the technology used to create ICs.

The following figure shows the IC design process. and who implements that step: Design Process Micro-Architecture Design and Verification Example Define the product Who Implements Engineer Logic Design and Verification Describe product functions Engineer Circuit Design and Performance Verification Implement product functions Engineer Layout Design and Verification Represent functions physically Mask Designer Mask Generation Transfer physical representation onto template Vendor Tapeout and Fabrication Create the product from the template Manufacturer Tapeout and First Silicon Create the first sample of the actual product Manufacturer 2-4 Intel Confidential .Chapter 2: Introduction to CMOS 1 CMOS 1 How Is an IC Designed? Introduction Process There are many phases required in the creation of an IC. an example of each process step.

The mask designer takes the design from logic-level schematics to transistor-level schematics to drawn layout. The following figure shows how the basic layout design tasks fit into the IC design process: Design Process Micro-Architecture Design and Verification Layout Design Tasks Logic Design and Verification Basic Layout Design Tasks Interpret Logic-level Schematics Circuit Design and Performance Verification 1 Layout Design and Verification Convert Logic-level to Transistor-level Schematics Create Layout Drawings from Transistor-level Schematics 2 Mask Generation 3 Tapeout and Fabrication Tapeout and First Silicon Intel Confidential 2-5 .CMOS 1 Chapter 2: Introduction to CMOS 1 Basic Layout Design Tasks Introduction The basic layout design tasks are part of the layout design and verification stage of the IC design process.

As you progress through the layout design tasks. and layout representation. The design data representations are graphical ways of displaying the design data. The figure below shows one electrical function — an inverter — in the logic-level schematic. you will work with an increasing amount of design data detail.Chapter 2: Introduction to CMOS 1 CMOS 1 What Are the Design Data Representations? Introduction There are different ways to represent the design of an integrated circuit. Logic-level Schematic Definition Examples Basic Layout Design Tasks 1 Interpret Logic-level Schematics Transistor-level Schematic 2 Convert Logic-level to Transistor-level Schematics Create Layout Drawings from Transistor-level Schematics Layout Drawing 3 2-6 Intel Confidential . transistor-level schematic.

CMOS 1 Chapter 3: How to Interpret Logic-level Schematics Chapter 3: How to Interpret Logic-level Schematics 1 Interpret Logic-level Schematics 2 Convert Logic-level to Transistor-level Schematic 3 Create Layout Drawing from Transistor-level Schematic Intel Confidential 3-1 .

. . . The following topics are covered in this chapter: Topic Page Objective Topics Lesson 3-1: How to Identify the Parts of a Logic-level 3-3 Schematic . . . Lesson 3-2: How to Describe the Function of a Logic Symbol 3-13 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Chapter 3: How to Interpret Logic-level Schematics CMOS 1 Chapter Overview Introduction Logic-level schematics are a standard way for the engineers to communicate the functions of an IC to other project members. . . . you will learn to identify the parts of logic-level schematics and describe the function of the logic symbols. . . . . . . In this chapter. . . 3-36 3-2 Intel Confidential . . . . . . . . . . . . . . . . . . .

CMOS 1 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic Lesson 3-1: How to Identify the Parts of a Logic-level Schematic Intel Confidential 3-3 .

. The logic-level schematic is the first graphical data representation of the IC’s function. . . .b: Identify the Logic Symbols of the Logic-level Schematic . . . . . . . . . . . . . 3-12 3-4 Intel Confidential .Lesson 3-1: How to Identify the Parts of a Logic-level Schematic CMOS 1 Lesson 3-1 Overview Introduction To accomplish the task of interpreting the logic-level schematic. . . 3-8 Lab 3-1. . . The following topics are covered in this lesson: Topic Page Objective Topics What Is a Logic-level Schematic? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic . . . . . . . . . . . . . . . . . . . 3-9 Logic-level Schematic Drawing Conventions . . .a: Identify the Nodes of the Logic-level Schematic 3-6 Logic Symbols of the Basic Logic Functions . . . . . . . . . . . . . . . . In this lesson. . . . . . 3-5 Lab 3-1. . . . . you must be able to identify its parts. . . . you will learn to identify the parts of a logic-level schematic. . . . . . . . . . . . .

— Output: Carry information away from the logic symbol. There are three types of nodes on a logic-level schematic. Nodes are drawn as lines. Two main parts of logic-level schematics are logic symbols and nodes. as follows: — Input: Supply information to the logic symbol.CMOS 1 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic What Is a Logic-level Schematic? Introduction Mask designers must be able to identify the parts of a logic-level schematic in order to convert it into a transistor-level schematic. G Definition Logic symbol: a short-hand representation for basic or complex logic functions. Logic Symbols A Input Nodes Internal Node Output Node B C OUT Intel Confidential 3-5 . The logic-level schematic is a short-hand representation of the actual functions that make up the IC. Logic Symbol A OUT Nodes Example 2 The following figure is a logic-level schematic containing two logic symbols with the logic symbols and nodes labeled. Node: an electrical path between logic symbols or the inputs and output of the logic symbols. G Example 1 The following figure is a logic-level schematic containing a single logic symbol with the logic symbol and nodes labeled. — Internal: Carry information between logic symbols.

complete the exercises.a: Identify the Nodes of the Logic-level Schematic Introduction Now that you know two of the main parts of a logic-level schematic. How many logic symbols are in the logic-level schematic? Color each of the nodes in the logic-level schematic a different color. c. f. a. logic symbols and nodes.a 1.Lesson 3-1: How to Identify the Parts of a Logic-level Schematic CMOS 1 Lab 3-1. Instructions for Lab 3-1. b. you will identify the logic symbols and nodes in a logic-level schematic. e. Given the following logic-level schematic. How many nodes are in the logic-level schematic? How many input nodes are in the logic-level schematic? How many internal nodes are in the logic-level schematic? How many output nodes are in the logic-level schematic? 3-6 Intel Confidential . d.

complete the exercises. Given the following logic-level schematic. e. b. How many logic symbols are in the logic-level schematic? Color each of the nodes in the logic-level schematic a different color. d. a. c.CMOS 1 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic Instructions for Lab 3-1.a 2. f. How many nodes are in the logic-level schematic? How many input nodes are in the logic-level schematic? How many internal nodes are in the logic-level schematic? How many output nodes are in the logic-level schematic? Intel Confidential 3-7 .

OR. The Inverter logic symbol is as follows: A OUT Inverter Logic Symbol AND Logic Symbol The AND logic symbol is as follows: A B OUT NAND Logic Symbol By inverting the output of the AND logic symbol (represented by the bubble on the output node). the NOR logic symbol is created. the inverter can only have one input node. However. NAND. and NOR logic symbols. the NAND logic symbol is created. A logic symbols is always drawn with its input and output nodes. There is only one output node on the basic logic symbols used in this class. The 2-input NAND logic symbol is as follows: A B OUT OR Logic Symbol The OR logic symbol is as follows: A B OUT NOR Logic Symbol By inverting the output of the OR logic symbol (represented by the bubble on the output node). Number of Output Nodes 3-8 Intel Confidential . The 2-input NOR logic symbol is as follows: A B OUT Number of Input Nodes There can be more than two input nodes on the AND.Lesson 3-1: How to Identify the Parts of a Logic-level Schematic CMOS 1 Logic Symbols of the Basic Logic Functions Introduction Following are the standard logic symbols used to represent the basic functions.

CMOS 1 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic Lab 3-1. fill in the table below with the names of logic symbols and the number of input nodes each logic symbol has. Given the following logic-level schematic.b 1. 1 2 3 5 4 Logic Symbol Number 1 2 3 4 5 Logic Symbol Function Number of Input Nodes Intel Confidential 3-9 . you will identify the function name and the number of inputs for each logic symbol in a logic-level schematic. Instructions for Lab 3-1.b: Identify the Logic Symbols of the Logic-level Schematic Introduction Now that you know the name of the function that each logic symbol represents.

3-10 Intel Confidential . they are not connected.Lesson 3-1: How to Identify the Parts of a Logic-level Schematic CMOS 1 Logic-level Schematic Drawing Conventions Introduction To draw and interpret logic-level schematics. but are not connected Nodes are connected continued. you must follow a set of conventions. the following inverter logic symbols are all equivalent. Each project has slightly different conventions. The following are the conventions for this class. The orientation of the logic symbol does not affect its functionality. Logic Symbol Orientation Connecting Nodes Nodes to be connected are drawn with a dot connecting the lines. When nodes cross without a dot... Connected Nodes: A A A A A Crossing Unconnected Nodes: A B Example: Connected and crossing nodes are drawn in a schematic as follows: Nodes cross.

CMOS 1 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic Logic-level Schematic Drawing Conventions (continued) Supply Voltages G Vcc or Power is the logical high: 1 Vcc G Vss or Ground is the logical low: 0 Vss Example: A NAND logic symbol with one input node connected to Vcc and the other input node connected to Vss. C Intel Confidential 3-11 .

Instructions for Lab 3-1. 2. and the node drawing convention. 3. 1. b. How many unique nodes are in the logic-level schematic? 3-12 Intel Confidential . List the function names of the logic symbols.Lesson 3-1: How to Identify the Parts of a Logic-level Schematic CMOS 1 Lab 3-1.c: Identify the Parts of the Logic-level Schematic Introduction Now that you know how to identify the function of the logic symbols. Given the following logic-level schematic. 4. 1 2 3 4 a. complete the following exercises. you will identify the function of the logic symbols and the number of unique nodes in a logic-level schematic.c 1.

CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol Lesson 3-2: How to Describe the Function of a Logic Symbol Intel Confidential 3-13 .

. . . . 3-18 What Are Truth Tables? . . . . . . . . . . . . . . . . . .a: Evaluate Boolean Algebra Equations . . . . . . . . . . . . . . . . . 3-21 How Are Input Values for a Truth Table Filled In? . . . . . . The following topics are covered in this lesson: Topic Page Objective Topics What Are the Standard Logic Functions? . . 3-27 Practice 3-2. . . . . . . . . . . . . .Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 Lesson 3-2 Overview Introduction To really understand the function of a logic symbol. . . . . . . . . . .d: Describe Logic Functions with Truth Tables 3-29 3-14 Intel Confidential . . . . . . . .c: Fill in the Input Values for a Truth Table . In this lesson. . 3-26 Output Values of the Truth Tables . . .b: Determine the Number of Columns and Rows for a Truth Table . . . . . . . . . . 3-19 How Is the Number of Rows for a Truth Table Determined? 3-20 Practice 3-2. . 3-15 Practice 3-2. . you will learn how to describe the logic function of the logic symbols with truth tables. . . . you must be able to describe its function. . . . . 3-23 Practice 3-2. . . . . . . . . . .

Boolean algebra uses the following symbols for the logic functions: Boolean Symbol Logic Function Name Inverse * + AND OR continued.CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol What Are the Standard Logic Functions? Introduction Logic functions are the basis of defining the functionality that exists in an IC. Boolean algebra and truth tables are used to identify the relationship between the input and output values of the logic functions... for example: State 1 High 1 On Vcc State 2 Low 0 Off Vss Definition Logic Functions The basic logic functions are defined by Boolean algebra. The input and output values are in one of two states. Intel Confidential 3-15 . A logic function is a definition of an output condition based on a set of input conditions.

Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 What Are the Standard Logic Functions? (continued) Basic Functions The basic logic functions defined by Boolean algebra are as follows: G Inverse function: The Inverse function output is always a 0 when the input is a 1 and always a 1 when the input is a 0.. 3-16 Intel Confidential . A = OUT Value A=0 Invert Value 0=1 1=0 INVERSE 0=1 1=0 A G OUT A=1 AND function: the output is 1 only when all inputs are 1’s. A + B = OUT A B OUT OR 0+0=0 0+1=1 1+1=1 continued. A * B = OUT A B OUT AND 0*0=0 0*1=0 1*1=1 G OR function: the output is 0 only when all inputs are 0’s..

A + B = OUT A B OUT OR 0+0=1 0+1=0 1+1=0 Invert OR 0 + 0 = 0 =1 0+1=1=0 1+1=1=0 NOR 0+0=1 0+1=0 1+1=0 Intel Confidential 3-17 . A * B = OUT A B OUT AND 0*0=0 0*1=0 1*1=1 Invert AND 0*0=0=1 0*1=0=1 1*1=1=0 NAND 0*0=1 0*1=1 1*1=0 G NOR function: the output is 1 only when all inputs are 0’s.CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol What Are the Standard Logic Functions? (continued) Inverse Functions The Boolean Algebra is created by inverting the basic functions: G NAND function: the output is 0 only when all inputs are 1’s.

Instructions for Practice 3-2.a: Evaluate Boolean Algebra Equations Introduction Now that you know how to describe the definitions of the logic functions with Boolean algebra. For the following Boolean algebra equations.a 1. provide the name of the logic function and the output value.Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 Practice 3-2. you will evaluate the following Boolean algebra equations. Equation 1+1= 1+0= 0*1= 1*1= 1*0= 0+0= 0*0= 1*1= 1+1+1= 1+1+0= 0*0*0= 0*1*0= 1*1*1= 1+1+0= 0*0*1= 1+1+1+0= 0*0*0*1= Function Name Output Value 3-18 Intel Confidential .

Input Columns: A column for each input node. Output Column B 1. To complete a truth table for a logic symbol. 4. The node values are either 0’s or 1’s. Input/Output Node Values: The value of the input or output node. 3. The maximum number of rows is equal to the maximum number of input combinations. 1. G G Definition Which logic function does the logic symbol represent? How many input nodes does the logic symbol have? Parts of a Truth Table The parts of the truth table are as follows. Input Columns 4.CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol What Are Truth Tables? Introduction An easy way to display the Boolean algebra equations is with a truth table. 2. Input/Output Node Values 0 0 1 1 A 0 1 0 1 OUT 0 0 0 1 Intel Confidential 3-19 . Output Column: A column for the output node. Input/Output Rows 2. The number of input columns is equal to the number of input nodes of the logic symbol. A truth table is a chart of the output values of a logic function when all possible combinations of 1’s and 0’s are applied as inputs. you need to know two things. There is always one output column for a logic symbol. 3. Input/Output Rows: A row for each combination of input values and the output value.

Action Identify the number of input nodes for the logic symbol you are describing.Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 How Is the Number of Rows for a Truth Table Determined? Introduction The number of rows that a truth table needs is defined by the maximum number of combinations for the input node values. Determine the number of rows for the truth table as follows: Procedure Step 1. There is one row in the truth table for each combination of input node values. Calculate the maximum number of combinations for the input nodes with the following formula: Maximum Combinations = 2(number of input nodes) Examples An example using the formula with a 2-input NAND logic symbol is as follows: A B OUT Maximum Combinations = 22 = 2 * 2 = 4 An example using the formula with a 3-input NOR logic symbol is as follows: A B C OUT Maximum Combinations = 23 = 2 * 2 * 2 = 8 3-20 Intel Confidential . 2.

CMOS 1

Lesson 3-2: How to Describe the Function of a Logic Symbol

Practice 3-2.b: Determine the Number of Columns and Rows for a Truth Table
Introduction Now that you know how to determine the number of columns and rows that are needed to create a truth table, determine the number of columns and rows for the following logic symbols.

Instructions for Practice 3-2.b 1. For an Inverter, complete the following. a. Draw the logic symbol.

b. 2.

How many inputs columns does the truth table for this logic symbol have?

For a 4-input AND, complete the following. a. Draw the logic symbol.

b. 3.

How many input columns does the truth table for a 4-input logic symbol have?

For a 4-input OR, complete the following. a. Draw the logic symbol.

b.

Calculate the maximum number of input combinations for a 4-input logic symbol. Show your work.

Intel Confidential

3-21

Lesson 3-2: How to Describe the Function of a Logic Symbol

CMOS 1

Instructions for Practice 3-2.b 4. For a 5-input NOR, complete the following. a. Draw the logic symbol.

b.

Calculate the maximum number of input combinations for a 5-input logic symbol. Show your work.

c.

Calculate the number of rows.

d.

Draw the truth table.

3-22

Intel Confidential

CMOS 1

Lesson 3-2: How to Describe the Function of a Logic Symbol

How Are Input Values for a Truth Table Filled In?
Introduction It is important to list all possible input combinations in the truth table, so that the logic function can be completely described. Once all of the input combinations are filled into the truth table, the output values can be calculated. Determine all possible input combinations as follows:

Procedure

Step 1. 2. 3. 4.

Action Draw the truth table with the correct number of rows and columns. For the right-most input column, fill in each box down this column with alternating 0’s and 1’s. Start with a 0 in the top box. For the next column to the left, fill in this column with alternating groups of two 0’s then two 1’s. For each column to the left, continue to alternate between groups of 0’s and 1’s. In each column, double the number of 0’s and 1’s in each group.

continued...

Intel Confidential

3-23

Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 How Are Input Values for a Truth Table Filled In? (continued) Example Using the above procedure fill in the input values for a 3-input NAND logic symbol.. Action Draw the truth table with the correct number of rows and columns. Start with a 0 in the top box.. 3-24 Intel Confidential . C B A 0 1 0 1 0 1 0 1 OUT continued. For the right-most input column. fill in each box down this column with alternating 0’s and 1’s. Three inputs = three input columns 23 = 2 * 2 * 2 = 8 rows C B A OUT 2. Step 1.

there would be eight 0’s and 1’s in each group. C B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 OUT 4. then two 1’s. fill in this column with alternating groups of two 0’s. double the number of 0’s and 1’s in each group. Action For the next column to the left. For this column. If there was another column.CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol How Are Input Values for a Truth Table Filled In? (continued) Example (continued) Step 3. For each column to the left. continue to alternate between groups of 0’s and 1’s. there are four 0’s and 1’s in each group. C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 OUT Intel Confidential 3-25 . In each column.

3-26 Intel Confidential . Calculate the number of rows for the truth table. and the output is OUT. b. c. you will draw truth tables and fill in the input values. the inputs are A.Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 Practice 3-2. Fill in the input values.c: Fill in the Input Values for a Truth Table Introduction Now that you know the procedure to fill in the input values for a truth table. d. Draw the truth table. Complete the following steps to create a truth table for a 3-input logic symbol. Calculate the number of columns for the truth table.c 1. Instructions for Practice 3-2. B. a. C. do not fill in the output column.

CMOS 1

Lesson 3-2: How to Describe the Function of a Logic Symbol

Output Values of the Truth Tables
Introduction Using the input values of a truth table and the correct Boolean algebra equation, you can determine the output values. For the Inverter function, the output value is always the complement (inverse) of the input value.
G

Inverter Truth Table

The Inverter function truth table is as follows: A = OUT
A 1 0 OUT 0 1

A

OUT

1=0 0=1

AND Truth Table

For the AND function, if any of the inputs are 0, then the output is 0.
G

The 2-input AND function truth table is as follows:

A

B 0 1 0 1

OUT 0 0 0 1

A * B = OUT A B
0

OUT

0*0=0 0*1=0 1*1=1

0 1 1

OR Truth Table

For the OR function, if any of the inputs is 1, then the output is 1.
G

The 2-input OR function truth table are is as follows:

A

B 0 1 0 1

OUT 0 1 1 1

A + B = OUT A B
0

OUT

0+0=0 0+1=1 1+1=1

0 1 1

continued...
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CMOS 1

Output Values of the Truth Tables (continued)
NAND Truth Table For the NAND function, if any of the inputs is 0, then the output is 1.
G

The 2-input NAND function truth table is as follows:

A

B 0 1 0 1

OUT 1 1 1 0

A * B = OUT A B
0

OUT

0*0=1 0*1=1 1*1=0

0 1 1

NOR Truth Table

For the NOR function, if any of the inputs is 1, then the output is 0.
G

The 2-input NOR function truth table is as follows:

A

B 0 1 0 1

OUT 1 0 0 0

A + B = OUT A B
0

OUT

0+0=1 0+1=0 1+1=0

0 1 1

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Lesson 3-2: How to Describe the Function of a Logic Symbol

Practice 3-2.d: Describe Logic Functions with Truth Tables
Introduction Now that you know how to describe the logic functions with truth tables, you will create truth tables for different logic functions.

Instructions for Practice 3-2.d 1. Complete the following truth table for a room light that is controlled by two switches, one at each door. If either of the switches is on, then the light is on.

1

1 0

A 0

B

Switch A

Switch B

Light

a.

Does the above example describe an AND or an OR logic function?

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Determine the maximum number of rows. Determine the number of input columns. Draw the truth table. c. Write the Boolean algebra equation for the logic function.Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 Instructions for Practice 3-2. Draw the logic symbol.d 2. Fill in all input combinations and the output values. 3-30 Intel Confidential . b. Complete the following steps to create a truth table for a 3-input AND logic function. e. a. d.

a. c. Write the Boolean algebra equation for the logic function.d 3. Draw the logic symbol. Fill in all input combinations and the output values. e. Determine the maximum number of rows.CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol Instructions for Practice 3-2. b. Intel Confidential 3-31 . Draw the truth table. Determine the number of input columns. d. Complete the following steps to create a truth table for a 3-input OR logic function.

b. a. Write the Boolean algebra equation for the logic function. Fill in all input combinations and the output values.d 4. Complete the following steps to create a truth table for a 4-input AND logic function. c. 3-32 Intel Confidential . e. d. Determine the number of input columns. Draw the logic symbol. Determine the maximum number of rows.Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 Instructions for Practice 3-2. Draw the truth table.

Complete the following steps to create a truth table for a 4-input NAND logic function. e. a. Fill in all input combinations and the output values. Intel Confidential 3-33 . Write the Boolean algebra equation for the logic function. Draw the truth table. Draw the logic symbol. d. b. Determine the maximum number of rows.CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol Instructions for Practice 3-2. Determine the number of input columns.d 5. c.

Create a truth table for a 4-input NOR logic function. 3-34 Intel Confidential .d 6.Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 Instructions for Practice 3-2.

B. Complete all missing input and output values in the following table. B NAND A. C NAND A.d 7. A 0 B 0 C 0 INV A NOR A.CMOS 1 Lesson 3-2: How to Describe the Function of a Logic Symbol Instructions for Practice 3-2. B NOR A. B. C 1 1 1 Intel Confidential 3-35 .

A summary of the logic functions is as follows: B 0 0 1 1 A 0 1 0 1 A 1 0 1 0 A*B 0 0 0 1 A*B 1 1 1 0 A+B 0 1 1 1 A+B 1 0 0 0 G 3-36 Intel Confidential . you learned to. — Inverter: A = OUT — AND: A * B = OUT — OR: A + B = OUT — NAND: A * B = OUT — NOR: A + B = OUT create truth tables that chart the output values of a logic function when all possible combinations of 1’s and 0’s are applied as inputs. — Node: electrical path between logic symbols or the inputs and output of the logic symbols. — Logic symbol: short-hand representation for basic or complex logic functions. In this chapter. G Summary identify the parts of the logic-level schematic.Lesson 3-2: How to Describe the Function of a Logic Symbol CMOS 1 Chapter Summary Introduction In this chapter. This is the first task of basic layout design. G describe the function of the logic symbols with Boolean algebra. Nodes are drawn as lines. you learned how to identify the parts of logic-level schematics and to describe the functions of the logic symbols with Boolean algebra and truth tables.

CMOS 1 Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic 3 Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic 1 Interpret Logic-level Schematics 2 Convert Logic-level to Transistor-level Schematic 3 Create Layout Drawing from Transistor-level Schematics Intel Confidential 4-1 .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol . . . . . . . . . . . . . . . The following topics are covered in this chapter: Lesson Page Objective Topics Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic . . . . . . . . . . . . . . . . . . . . . . .Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 Chapter Overview Introduction The layout designer needs more detail than the logic-level schematic provides. . . . . 4-27 Chapter Summary . . . . . . . . . . . . . . . . . . 4-45 4-2 Intel Confidential . . . . . . . . . so the logic-level schematic must be converted into a transistor-level schematic. . . . . . . . . . . . . . . In this chapter. you will learn to convert a logic-level schematic to transistor-level schematic. . . . . . . . . 4-16 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic . . .

CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic 40 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic Intel Confidential 4-3 .

. . . . . 4-5 What Is a Transistor? . . . 4-10 Lab 4-1: Identify the Parts of Transistor-level Schematics . . . . . . . 4-9 Transistor Representations of the Logic-level Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . you need to know the parts of the transistor-level schematic. . . . .Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic CMOS 1 Lesson 4-1 Overview Introduction Before you can convert the logic-level schematic to a transistor schematic. . . 4-12 4-4 Intel Confidential . . . . . . 4-6 Nodes of a Transistor-level Schematic . . . . . . . . . . . . you will learn to identify the parts of a transistor-level schematic. . In this lesson. The following are covered in this lesson: Lesson Page Objective Topics What Is a Transistor-level Schematic? .

CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic What Is a Transistor-level Schematic? Introduction The transistor-level schematic has more details than the logic-level schematic. Vcc Nodes A B Transistors Vss Intel Confidential 4-5 . Example The following figure is a transistor-level schematic of an inverter with the nodes labeled. the shorthand symbols of the logic-level schematic are converted to the transistor-level schematic. The transistor-level schematic is a representation of the actual transistors and the connections that create the logic functions of the IC. Node: an electrical path between transistors or the inputs and output of the transistors. G G Definition Transistors: representation of the actual layout transistors. and just the power supplies and transistors pulled apart. Nodes are drawn as lines.

. Analogy The source. Intel uses the Complementary Metal Oxide Semiconductor (CMOS) technology.Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic CMOS 1 What Is a Transistor? Introduction There are different types of technologies used to create transistors. The transistor is the basic building block of all functions on any IC. G G G G gate: input terminal source: terminal closest to Vcc or Vss drain: output terminal bulk: material that the transistor “sits” in The complementary part of CMOS means that pairs of p-type and ntype transistors are used to create the functions of the logic symbols. CMOS technology uses two types of Metal Oxide Semiconductor Field Effect Transistors (MOSFET) G G Definition pFET (p-type) nFET (n-type) Each type of MOSFET transistor has the following four elements. and drain of a transistor are similar to the circuits in your home. 4-6 Intel Confidential .. Transistor Source Gate Drain Your Home Power Company Light switch Lamp continued. gate.

Source and Drain Regions The source and drain regions are interchangeable and from this point on are referred to as source/drain (S/D). All of the following n-type transistors are equivalent... continued.CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic What Is a Transistor? (continued) Example The p-type transistor and the n-type transistor are drawn as follows: p-type Transistor Source Gate Bubble Bulk Gate Hole Flow Drain Source Gate Electron Flow Bulk n-type Transistor Drain P-Type vs. Intel Confidential 4-7 . N-Type Transistors The p-type and n-type transistors differ as follows: p-type Majority Current Carrier Gate Bubble Logical On Bulk hole yes 0 n-well n-type electron no 1 epitaxial Orientation The orientation of the transistor does not affect the performance or function of the transistor.

A hole flows in the opposite direction as the current. Hole Electron Current 4-8 Intel Confidential . Current is the movement of electrons through a circuit. An electron flows in the same direction as the current. the current flows through the transistor.Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic CMOS 1 What Is a Transistor? (continued) Logical On A logical on is when a transistor is logically on. An electron is the basic atomic particle orbiting an atom. A hole is a mobile vacancy within a semi-conductor material created by the lack of an electron.

or Vss node as follows.CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic Nodes of a Transistor-level Schematic Introduction It is important for you to be able to identify all of the nodes in a transistor-level schematic. Vcc. the connections between two transistors. Internal Node Intel Confidential 4-9 . are all nodes on a transistor-level schematic. output. from the lower S/D region of the p-type transistor to the upper S/D region of the n-type transistor to the output node 4. between the lower S/D region of the n-type transistor and Vss Logic-level Schematic A B 2 A B 3 Transistor-level Schematic 1 Nodes of a Transistorlevel Schematic 4 Internal Nodes There will be times when a node is not an input. between the upper S/D region of the p-type transistor and Vcc 2. A transistor-level schematic of an INVERTER has the following four nodes: 1. Vcc and Vss. from the input node to the gate of both transistors 3. The input and output nodes.

transistor-level representation.Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic CMOS 1 Transistor Representations of the Logic-level Schematics Introduction The following are the logic symbol.. and transistor-level representations of the logic symbols used in this class. and truth table are as follows: A B Logic-level A 0 0 1 1 B 0 1 0 1 OUT 1 1 1 0 A C B OUT Truth Table Transistor-level continued.. and truth table are as follows: A B Inverter Representations Logic-level A A 0 1 OUT 1 0 Transistor-level OUT Truth Table NAND Representations The NAND logic. transistor-level representation. 4-10 Intel Confidential . truth table. The Inverter logic.

transistor representation. Logic symbols with dots drawn are as follows: Intel Confidential 4-11 . and truth table are as follows: A B Logic-level C A A 0 0 1 1 B 0 1 0 1 Truth Table Out 1 0 0 0 Transistor-level B OUT Logic Symbol Dots A dot drawn on the logic symbol indicates how the series transistors are drawn. The dot affects only the drawing of the series transistors. the convention is that the dot indicates which series transistor is drawn closest to the output node. The placement of the dot is determined by the design engineer to address any timing issues. For this class.CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic Transistor Representations of the Logic-level Schematics (continued) NOR Representations The NOR logic.

d. Instructions for Lab 4-1 1. complete the exercises. you will identify the transistors and nodes in the following exercises. How many nodes does the logic-level schematic have? Color each node of the transistor-level schematic with a different color. How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have? 4-12 Intel Confidential . c. b. A OUT A OUT a.Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic CMOS 1 Lab 4-1: Identify the Parts of Transistor-level Schematics Introduction Now that you know the parts of the transistor-level schematic. e. Given the following logic and transistor-level schematic.

complete the exercises. d. f. b. e. Given the following logic and transistor-level schematic. c. How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have? Intel Confidential 4-13 . What type of logic symbol is this? How many nodes does the logic-level schematic have? Color each node of the transistor-level schematic with a different color.CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic Instructions for Lab 4-1 2. B A A B OUT OUT a.

How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have? 4-14 Intel Confidential .Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic CMOS 1 Instructions for Lab 4-1 3. A A B OUT B OUT a. e. c. complete the exercises. d. What type of logic symbol is this? Color each node of the transistor-level schematic with a different color. Given the following logic and transistor-level schematic. b.

CMOS 1 Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic Instructions for Lab 4-1 4. c. d. e. A C OUT A B C 30 OUT 15 B a. complete the exercises. Given the following logic and transistor-level schematic. How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have? Intel Confidential 4-15 . b. What type of logic symbol is this? Color each node of the transistor-level schematic with a different color.

Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol CMOS 1 41 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol 4-16 Intel Confidential .

. . . . . . . . . .CMOS 1 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol Lesson 4-2 Overview Introduction Knowledge of how transistors work allows a better understanding of how the logic functions execute. . . . . . . . . 4-18 How Are Truth Table Values Verified? . . . . . . . . . . . . . . . . . you will learn to verify the input and output values of the truth table against how the transistors turn on and off to allow current to flow. . . . . . . . 4-19 Practice 4-2: Verify the Transistor-level Function of the Logic Symbols . . . . . . . . The following are covered in this lesson: Topic Page Objective Topics Values that Turn a Transistor On or Off . . . . . . . . . . . 4-22 Intel Confidential 4-17 . . . . In this lesson. . . . . . . . .

An analogy is a light switch in your home. Remember that when a transistor is logically on. and the truth tables of the basic logic symbols.Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol CMOS 1 Values that Turn a Transistor On or Off Introduction You have seen the logic. the current is flowing through the transistor. when the light switch is turned on the current flows from the power company to the lamp. Now it is time to trace the nodes through the transistors from the input to the output. the transistor representation. P-Type Logical value to turn transistor on Logical value to turn transistor off Memory aid 0 1 Bubble N-Type 1 0 No Bubble Turning a Transistor On or Off 4-18 Intel Confidential . This will validate that the truth tables accurately represent the logic.

Repeat for each row of the truth table. Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Intel Confidential 4-19 . 4. If a path is found from Vcc. Verify the inputs and outputs against the truth table with the following steps: Step 1. Note that the value at the output node matches the truth table.. Determine which transistor gates are on and off. Action Apply the first row of the truth table to the input nodes.CMOS 1 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol How Are Truth Table Values Verified? Introduction By tracing the input values and their affect on the transistors. Write “on” or “off” for each transistor. 5. Reminders Remember the values that turn the p-type and n-type transistors on and off.. G G Procedure If a path is found from Vss. Determine which path is complete. then the output value is 0. you can see how the output value is created. 2. P-Type Logical value to turn transistor on Logical value to turn transistor off Memory aid 0 1 Bubble N-Type 1 0 No Bubble Remember that Vcc and Vss have the following logical values: G G Vcc = 1 Vss = 0 continued. then the output value is 1. 3.

Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol CMOS 1 How Are Truth Table Values Verified? (continued) Inverter Example Using the transistor-level schematic and the truth table. so a logical 1 is at the output. The input of a logical 0 is inverted to a logical 1. 2. then the output value is 0. Determine which path is complete.. 4-20 Intel Confidential . complete the steps of the above procedure to verify the inputs and output values. If a path is found from Vcc. Note that the value at the output node matches the truth table. Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Action Apply the first row of the truth table to the input nodes. Determine which transistor gates are on and off. G G If a path is found from Vss. a. Write “on” or “off” for each transistor. the n-type transistor is off on A=0 off B=0 3. the p-type transistor is on b. continued. then the output value is 1. A A B 0 1 OUT 1 0 Use the procedure for the first line of the truth table.. as follows: Step 1. A path is found from Vcc to the output node. 4.

CMOS 1 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol How Are Truth Table Values Verified? (continued) Inverter Example (continued) Use the same transistor-level schematic and truth table. then the output value is 0. a. Intel Confidential 4-21 . the n-type transistor is on off A=1 on B=0 3. Action Repeat for the next row of the truth table. as follows: Step 1. A A B 0 1 OUT 1 0 Repeat the procedure for the next line of the truth table. A path is found from Vss to the output node. then the output value is 1. if a path is found from Vcc. 2. so a logical 0 is at the output. Determine which transistor gates are on and off. the p-type transistor is off b. Note that the value at the output node matches the truth table. G G If a path is found from Vss. 4. Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Write “on” or “off” for each transistor. Determine which path is complete. The input of a logical 1 is inverted to a logical 0.

Repeat for each row of the truth table. Note that the value at the output node matches the truth table. Determine which transistor gates are on and off. Given the following 2-input NAND transistor-level schematic and truth table. you will verify the following transistor-level schematics and truth tables. Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Write “ON” or “OFF” for each transistor. 4-22 Intel Confidential . as directed. Determine which path is complete. 2. Instructions for Practice 4-2 1. then the output value is 0 if a path is found from Vcc. 5. B B A OUT 0 0 1 1 A 0 1 0 1 OUT 1 1 1 0 Step 1. Action Apply the first row of the truth table to the input nodes. use the outlined procedure to verify the truth table values. 3. G G If a path is found from Vss. then the output value is 1 4.Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol CMOS 1 Practice 4-2: Verify the Transistor-level Function of the Logic Symbols Introduction Now that you know what value turns on a p-type and an n-type transistor and how to verify the values of a truth table.

B A OUT Intel Confidential 4-23 . Apply the third row of the truth table to the following transistor-level schematic. B A OUT c.CMOS 1 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol Instructions for Practice 4-2 2. B A OUT b. Apply the first row of the truth table to the following transistor-level schematic. a. Apply the second row of the truth table to the following transistor-level schematic.

2. B A OUT 4. Action Apply the first row of the truth table to the input nodes. Given the following 2-input NOR transistor-level schematic and truth table. d. 4-24 Intel Confidential . use the outlined procedure to verify the truth table values. Determine which transistor gates are on and off. Apply the fourth row of the truth table to the following transistor-level schematic. then the output value is 1 4. Determine which path is complete. then the output value is 0 if a path is found from Vcc. Repeat for each row of the truth table. B A 0 0 B OUT 1 1 0 1 0 1 1 0 0 0 A OUT Step 1.Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol CMOS 1 Instructions for Practice 4-2 3. G G If a path is found from Vss. 5. Note that the value at the output node matches the truth table. 3. Write “ON” or “OFF” for each transistor. Trace a path through the transistors from Vss to the output node and from Vcc to the output node.

Apply the second row of the truth table to the following transistor-level schematic.CMOS 1 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol Instructions for Practice 4-2 5. a. A B OUT Intel Confidential 4-25 . A B OUT c. Apply the third row of the truth table to the following transistor-level schematic. A B OUT b. Apply the first row of the truth table to the following transistor-level schematic.

Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol

CMOS 1

Instructions for Practice 4-2 6. d. Apply the fourth row of the truth table to the following transistor-level schematic.

A

B

OUT

7.

For the 3-input NAND logic symbol, complete the following. a. b. c. Draw the transistor-level schematic. Draw and fill in the truth table. Using the same procedure as in the previous exercises, verify the truth table values.

8.

For the 3-input NOR logic symbol, complete the following. a. b. c. Draw the transistor-level schematic. Draw and fill in the truth table. Using the same procedure as in the previous exercises, verify the truth table values.

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Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic

42

Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic

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Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic

CMOS 1

Lesson 4-3 Overview
Introduction Up to this point, the transistor-level schematics have been given to you. However, you will need to know how to draw the transistorlevel schematics. The level of detail of the transistor-level schematic is needed to create the layout drawings. In this lesson you will learn to convert a logic-level schematic to a transistor-level schematic. The following are covered in this lesson: Topic Page

Objective

Topics

Logic Functions Defined with Transistors . . . . . . . . . . . . . . 4-29 How Is a Logic-level Schematic Converted to a Transistorlevel Schematic? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Practice 4-3: Convert a Logic-level Schematic to a Transistorlevel Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 What is Complex Logic? . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 Order of the Series Transistors . . . . . . . . . . . . . . . . . . . . . . . 4-34 How Is a Complex Logic-level Schematic Converted to NType Transistors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Lab 4-3.a: Convert Complex Logic-level Schematics to NType Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 How Is a Complex Logic-level Schematic Converted to PType Transistors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Lab 4-3.b: Convert Complex Logic-level Schematics to PType Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 Lab 4-3.c: Convert Complex Logic-level Schematics to Transistor-level Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 4-44

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CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic Logic Functions Defined with Transistors Introduction Before converting a logic-level schematic to a transistor-level schematic. The logical function of a logic symbol is always defined by the ntype transistors. G Logic Functions NAND function — based on the AND function — n-type transistors are in series — p-type transistors are parallel parallel transistors A A B OUT series transistors B OUT G NOR function — based on the OR function — n-type transistors are parallel — p-type transistors are in series series transistors A B OUT A B OUT parallel transistors Intel Confidential 4-29 . you need to understand how the transistors define the logic of the function.

Create the n-type transistors according to the logic function of the logic symbol and label all transistor nodes according to the logic-level schematic.. If n-type transistors are. parallel in series 6.Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 How Is a Logic-level Schematic Converted to a Transistor-level Schematic? Introduction The transistor-level schematic equivalent of a logic-level schematic is drawn with a straightforward procedure. in series parallel then p-type transistors are. 2... continued. Remember: Procedure 5. as follows: # of transistors = 2 * (# of input nodes) For example. 4. Calculate the number of transistors. Connect all common nodes.. Draw the output node as a horizontal line. The procedure of converting a logic-level schematic to a transistorlevel schematic is as follows: Step 1. 3. 4-30 Intel Confidential . Add the p-type transistors as the complement to the n-type transistors and label all nodes according to the logic-level schematic.. for a 2-input NAND logic symbol: # of transistors = 2 * (2) = 4 Half of the transistors are p-type transistors and half are n-type transistors. Action Determine the logic function of the logic symbol: NAND or NOR..

Action Determine the logic function of the logic symbol: NAND or NOR. Add the p-type transistors as the complement to the n-type transistors and label all nodes according to the logic-level schematic. Step 1. the n-type transistors are in series. A B OUT NAND. OUT 3. Draw the output node as a horizontal line. OUT A B 5. 2. OUT A B 4. Create the n-type transistors according to the logic function of the logic symbol and label all transistor nodes according to the logic-level schematic. Connect all common nodes.CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic How Is a Logic-level Schematic Converted to a Transistor-level Schematic? (continued) Example Use the NAND logic symbol and the procedure outlined. A B OUT Intel Confidential 4-31 . as follows.

A B Out c.Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 Practice 4-3: Convert a Logic-level Schematic to a Transistor-level Schematic Introduction Now that you know how to convert logic symbols to transistor-level schematics. Instructions for Practice 4-3 1. A B N1 OUT d. A N1 B OUT e. Using the described procedure. convert the following logic-level schematics to a transistor-level schematic. you will convert the following logic symbols. A B C D E F N1 OUT N2 4-32 Intel Confidential . A B OUT b. a.

you need to be able to a convert complex logic function into transistor-level schematic.CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic What is Complex Logic? Introduction Understanding the basic logic functions is not enough. Example A logic-level schematic of a complex logic symbol is as follows: A B C D Inverted Function OUT Definition Non-Inverted Functions Internal Nodes There are internal nodes in complex logic where the logic symbols touch. The new function is drawn with fewer transistors and has increased performance. as follows: A B C D Internal Node OUT Internal Node Intel Confidential 4-33 . Complex logic is the combination of non-inverted logic functions and an inverted logic function that produce a new function. The non-inverted logic functions cannot be drawn directly with the CMOS process.

A logic-level schematic with dots is drawn as follows: A B OUT C D 4-34 Intel Confidential . A dot drawn on the logic symbol indicates the transistor that is drawn closest to the output node. the ordering is important for timing purposes and is communicated by the design engineer on the logic-level schematic. The dot affects the drawing of the series transistors and the series “boxes” of complex logic. G G Logic Symbol Dots A dot on the parent indicated the box closest to the output node.Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 Order of the Series Transistors Introduction For the transistors drawn in series. A dot on the logic symbol in a box indicates the transistor of the logic symbol that must be closest to the output node.

continued. Procedure 4. to the output node and to Vss as defined by the function of parent. Draw a horizontal line to represent the output node and label it. Identify the inputs to parent. internal nodes. Since the n-type transistors determine the logic function it is easier to draw them first. Action Identify the parts of the logic-level schematic. 7. Draw a box around the logic symbol the output node is connected to and call this parent. Box1. Draw and connect the boxes. Intel Confidential 4-35 . Tip: Remember that the n-type transistors determine the logic function of the logic symbol (in series or parallel). Draw the n-type transistors into the corresponding boxes for each logic symbol and label all the input nodes. Determine the logic function (NAND or NOR) of the n-type transistors of parent. you will learn to add the p-type transistors.. logic symbols. in series or parallel. input. Draw a box around each of the logic symbols and input nodes going into parent. 6. 5. Identify the inverted logic function.CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic How Is a Complex Logic-level Schematic Converted to N-Type Transistors? Introduction Converting a complex logic-level schematic is accomplished with the following procedure.. Box2. for example. Label each of these boxes. 3. The procedure of converting a complex logic-level schematic to the n-type transistors is as follows: Step 1. 2. In the next section. Begin the transistor-level schematic. output.

parent OUT parent OUT continued.. Draw a horizontal line to represent the output node and label it. Identify the inputs to parent.. Begin the transistor-level schematic.Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 How Is a Complex Logic-level Schematic Converted to N-Type Transistors? (continued) Example Using the following complex logic-level schematic: A B C D OUT Complete the conversion procedure. Draw a box around each of the logic symbols and input nodes going into parent. logic symbols. logic function of parent is the NAND function. so the n-type transistor boxes are drawn in series. Box2. Identify the inverted logic function. Draw a box around the logic symbol the output node is connected to and call this parent. internal nodes. In this example. A B C D 3. Box1. input. Action Identify the parts of the logic-level schematic. for example. Label each of these boxes. OUT 5. 4-36 Intel Confidential . output. Determine the logic function (NAND or NOR) of the n-type transistors of parent. Box 1 A B C D Box 2 4. as follows: Step 1. 2.

Action Draw and connect the boxes. OUT Box 1 Box 2 7. OUT A B Box 1 C D Box 2 Intel Confidential 4-37 . to the output node and to Vss as defined by the function of parent. Draw the n-type transistors into the corresponding boxes for each logic symbol and label all the input nodes. The transistors are in series. — Box 1: OR function. The transistors are parallel.CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic How Is a Complex Logic-level Schematic Converted to NType Transistors? (continued) Example (continued) The rest of the steps are as follows: Step 6. in series or parallel. Since the n-type transistors of the NAND logic are in series. draw the boxes in series. — Box 2: AND function.

Instructions for Lab 4-3. b. Given the following logic-level schematic.a: Convert Complex Logic-level Schematics to N-Type Transistors Introduction Now that you know how to convert a complex logic-level schematic to the n-type transistors and how to determine which transistors must be closest to the output node. 4-38 Intel Confidential .Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 Lab 4-3. complete the following. 1. you will draw the n-type transistors in the correct order for complex logic-level schematics. How many n-type transistors are needed? Draw the n-type transistors for the logic-level schematic.a Use a full page of paper for each drawing. Put the n-type transistors at the bottom of the page and leave room at the top to later add the p-type transistors. pay attention to the dot notation. A B OUT C D a.

Intel Confidential 4-39 .CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic Instructions for Lab 4-3. 3. A B C D E F OUT a. complete the following. Given the following logic-level schematic.a 2. How many n-type transistors are needed? Draw the n-type transistors for the logic-level schematic. How many n-type transistors are needed? Draw the n-type transistors for the logic-level schematic. A B C OUT a. complete the following. Given the following logic-level schematic. pay attention to the dot notation. b. pay attention to the dot notation. b.

. Pay attention to which logic symbol is marked to be drawn nearest to the output node.. continued. 2. Action Draw and connect the boxes to hold the p-type transistors in a way that is complementary to the boxes holding the n-type transistors. Draw the p-type transistors in the new boxes. connect the transistors to the output and Vcc nodes. Procedure If N-Type transistors are. and label the input nodes. Tip: Remember that the n-type and p-type transistors are complementary. 4-40 Intel Confidential . The procedure of converting a complex logic-level schematic to the p-type transistors is as follows: Step 1.. parallel in series 3...Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 How Is a Complex Logic-level Schematic Converted to P-Type Transistors? Introduction You know how to draw the n-type transistors of the complex logic. in series parallel then P-Type transistors are. etc. Connect the common nodes: A to A. Now you will add the p-type transistors..

. Intel Confidential 4-41 . Action Draw and connect the boxes to hold the p-type transistors in a way that is complementary to the boxes holding the n-type transistors. In this example.CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic How Is a Complex Logic-level Schematic Converted to P-Type Transistors? (continued) Example Use the same complex logic-level schematic used to draw the n-type transistors. so the p-type transistor boxes are parallel. the n-type transistor boxes are in series. Box 1 A B C D Box 2 parent OUT Add the p-type transistors using the procedure. as follows: Step 1. Pay attention to which logic symbol is marked to be drawn nearest to the output node.. Box 1 Box 2 OUT A B Box 1 C D Box 2 continued.

Box 2 C Box 1 B A OUT A Box 1 D Box 2 4-42 Intel Confidential . — — Box 1: n-type transistors are parallel. etc. Box 2 Box 1 B A C D OUT 3. connect the transistors to the output and Vcc nodes. and label the input nodes. so the p-type transistors are in series. so the p-type transistors are parallel. Box 2: n-type transistors are in series.Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 How Is a Complex Logic-level Schematic Converted to P-Type Transistors? (continued) Example (continued) The rest of the steps are as follows: Step 2. Action Draw the p-type transistors in the new boxes. Connect the common nodes: A to A.

add the p-type transistors to the transistor-level schematics you drew in the last practice. add the p-type transistors to the transistor-level schematics you drew in the last practice. Instructions for Lab 4-3.CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic Lab 4-3. A B C D E F OUT 3. A B C OUT Intel Confidential 4-43 . you will add the p-type transistors in the correct order for the complex logic-level schematics you drew in the last practice. For the following logic-level schematic.b Use the drawings you made in the previous lab and add the p-type transistors for the following exercises. A B OUT C D 2. For the following logic-level schematic.b: Convert Complex Logic-level Schematics to P-Type Transistors Introduction Now that you know how to convert a complex logic-level schematic to the p-type transistors. For the following logic-level schematic. add the p-type transistors to the transistor-level schematics you drew in the last practice. 1.

For the following logic-level schematic. For the following logic-level schematic. Instructions for Lab 4-3. draw the transistor-level schematic. draw the transistor-level schematic.Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 Lab 4-3. A B C D E F OUT 4-44 Intel Confidential .c: Convert Complex Logic-level Schematics to Transistor-level Schematics Introduction Now that you know how to convert a complex logic-level schematic to the n-type and p-type transistors. you will draw both the n-type and p-type transistors for complex logic-level schematics.c 1. A B C D OUT 2.

and how to convert logic-level schematics to transistor-level schematics..CMOS 1 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic Chapter Summary Introduction In this chapter. Vcc and Vss.. you learned how to identify the parts of a transistorlevel schematic. In this chapter. Intel Confidential 4-45 . the connections between two transistors. – pFET (p-type) – nFET (n-type) The p-type and n-type transistors differ as follows: P-type Majority Current Carrier Gate Bubble Logical On Bulk hole yes 0 n-well N-type electron no 1 epitaxial — Node: an electrical path between transistors or the inputs and output of the transistors. G verify the transistor-level function of the logic symbols How to turn a transistor on: P-Type Logical value to turn transistor on Logical value to turn transistor off Memory aid 0 1 Bubble N-Type 1 0 No Bubble continued. how to verify the transistor-level function of the logic symbols. The input and output nodes. you learned to G Summary identify the parts of the transistor-level schematic. — Transistors: transistor-level schematic transistors represent the actual layout transistors. are all nodes on a transistor-level schematic. Nodes are drawn as lines.

NAND symbols – based on the AND function – n-type transistors are in series – p-type transistors are parallel A B OUT A B OUT NOR symbol – based on the OR function – n-type transistors are parallel – p-type transistors are in series A B OUT A OUT B 4-46 Intel Confidential .Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic CMOS 1 Chapter Summary (continued) Summary (continued) G convert logic-level schematics to transistor-level schematics The logical function of a logic symbol is always defined by the n-type transistors.

CMOS 1 Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic 43 Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic 1 Interpret Logic-level Schematic 2 Convert Logic-level to Transistor-level Schematic 3 Create Layout Drawing from a Transistor-level Schematic Intel Confidential 5-1 .

5-49 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing. . . . The following topics are covered in this chapter: Lesson Page Objective Topics Lesson 5-1: How to Identify a Transistor on the IC Cross Section. . . . 5-13 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80 5-2 Intel Confidential . . . . . . . . . . . . . . . . . . . . . 5-59 Lesson 5-8: How to Draw Layout with a Standard Cell Template . . . . . . . . . . . . . .Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic CMOS 1 Chapter Overview Introduction To create the masks for IC fabrication. . . . . . . 5-33 Lesson 5-5: How to Estimate Area . 5-19 Lesson 5-4: How to Get Better Layout Density with Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . the actual geometry size and spacing is needed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The transistor-level schematic must therefore be converted into a layout drawing. . . . . . . . . . . . . . . . 5-73 Chapter Summary . To convert a transistor-level schematic to a layout drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 Lesson 5-6: How to Calculate Resistance. . . . 5-3 Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section . . .

CMOS 1 Lesson 5-1: How to Identify a Transistor on the IC Cross Section Lesson 5-1: How to Identify a Transistor on the IC Cross Section Intel Confidential 5-3 .

. . . . . . . . . . 5-7 What Is a Diode? . . . . . . . . . . . . . . 5-6 Layers of the Die Cross Section . . . .Lesson 5-1: How to Identify a Transistor on the IC Cross Section CMOS 1 Lesson 5-1 Overview Introduction The objective of creating layout drawings is to create the die for the IC. . . you will learn how your layout drawing affects the creation of the die for the IC. . . . . The following topics are covered in this lesson: Topic Page Objective Topics What Is a Cross Section? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . so it is important to understand how your work affects the die. . . . 5-8 How Is a Transistor Turned On or Off? . . . . . . . . . . . . . . . . . . . . . 5-10 5-4 Intel Confidential . . . . 5-5 Layers of the Transistor Cross Section . . . . . . . . . . . . . . . . . . . . . . . In this lesson.

After slicing the cake open. you see that it is made up of many layers of different types of cake. it is necessary to look at the transistor cross section. you have to slice it open.CMOS 1 Lesson 5-1: How to Identify a Transistor on the IC Cross Section What Is a Cross Section? Introduction In order to understand how the p-type and n-type transistors function. Think of a cake as the IC. The same is true when you slice an IC. filling. To see what makes up the cake. A cross section is formed when you slice open an object and look at the cut edge. the frosting. When you look at the top of the cake you see only the top layer. n-type transistor p-type transistor Intel Confidential 5-5 . The following is the cross section of an n-type and a p-type transistor. Cake Cake Cross Section Definition Analogy The die is made up of many layers of different materials that are used to achieve the various functions an IC is capable of. and frosting.

Lesson 5-1: How to Identify a Transistor on the IC Cross Section CMOS 1 Layers of the Transistor Cross Section Introduction The p-type and n-type transistors are made of different diffusion material. so their cross section drawings are different. The layers of the p-type transistor are as follows: P-Type Transistor Gate Oxide S/D (Boron) Polysilicon S/D (Boron) Nwell Tap (Arsenic) Nwell Epitaxial Wafer N-Type Transistor The layers of the n-type transistor are as follows: Gate Oxide S/D (Arsenic) Polysilicon S/D (Arsenic) Substrate Tap (Boron) Epitaxial Wafer 5-6 Intel Confidential .

The process begins with a pure silicon ingot cylinder 8 inches in diameter and about 2-3 feet long. The layers on different die may vary with the fabrication process used to create the die. Polysilicon: for the gates and minimal routing 6. 4. Via 1: hole in the field oxide so the Metal2 can make a connection to Metal1 11. Field Oxide: same as above 10. Metal2: second layer of aluminum for interconnect 12. Contact: hole in the field oxide so the Metal1 can make a connection to polysilicon or diffusion 8. or wafer 2. Gate Oxide (gox): thin layer below gates 5.CMOS 1 Lesson 5-1: How to Identify a Transistor on the IC Cross Section Layers of the Die Cross Section Introduction A complete IC is created by accurately fabricating many layers of materials. Field Oxide: same as above 13. The ingot is sliced into thin wafers creating circular disks (like a CD). Nwell: provides a collection of electrons for the p-type transistors to sit in 3. Passivation: oxide to insulate the die Fabrication Process Layers Intel Confidential 5-7 . are the foundation of ICs. Field Oxide (fox): thick layer to insulate different layers 7. 1. Repeat 10-12 for each metal layer in the process 14. Metal1: first layer of aluminum for interconnect 9. The following is a typical layering of the materials on a die. also known as substrate. and boron for p-diffusion S/D. Source/Drain: arsenic for n-diffusion S/D. Epitaxial: higher resistance than the substrate. The wafers.

Parts of a Diode The terminals of a diode are the anode and the cathode. which prevents electrical current from flowing between opposite polarity diffusions when they are abutting. 5-8 Intel Confidential . ++ ++ ++ Anode ------Cathode continued. The cathode is the n-type diffusion. Diodes can be G Definition intentional: purposely added to the circuit to function as an Electro-static Discharge (ESD) device parasitic: occurring naturally when p-type and n-type materials touch G The normal operating condition of a diode in CMOS is reverse biased.. G G The anode is the p-type diffusion.. A diode is created when the p-type and n-type diffusions physically touch.Lesson 5-1: How to Identify a Transistor on the IC Cross Section CMOS 1 What Is a Diode? Introduction Inherent in the fabrication of the CMOS transistor is the creation of a parasitic diode. A diode is a semiconductor device that allows current to flow in one direction only.

Reverse Biased Diodes Forward Biased Diode Parasitic Diodes in an Inverter There are five parasitic diodes in an inverter.CMOS 1 Lesson 5-1: How to Identify a Transistor on the IC Cross Section What is a Diode? (continued) Example In the reverse biased diode. as shown in the following diagram. However. in the forward biased diode. the current flows unrestricted. current does not flow. Nwell Epitaxial Intel Confidential 5-9 .

The positive charge at the gate repels the positively charged ions in the epitaxial below the gate. Process Nwell Epitaxial continued. In a Field Effect Transistor (FET). 5-10 Intel Confidential . The current cannot flow between the source and drain. there is a predictable field effect on the region immediately below the gate. so that current can be blocked or flow between the source and drain. the current never flows between the gate and the epitaxial layer. between the source drain. However. creating an inversion layer.. 1 P-Type A positive electrical charge is applied to the gate. blocking the current flow. The current can now flow freely between the source and drain. turns the transistor on and allows current to flow from the source to the drain. Apply a logical 1 to the n-type and p-type transistors as follows: Applying a Logical 1 N-Type A positive electrical charge is applied to the gate. or a logical 0 to a p-type transistor. The positive charge at the gate attracts the negatively charged ions in the n-well below the gate..Lesson 5-1: How to Identify a Transistor on the IC Cross Section CMOS 1 How Is a Transistor Turned On or Off? Introduction Applying a logical 1 to an n-type transistor.

The negative charge at the gate attracts the positively charged ions in the epitaxial. blocking the current flow. The current cannot flow between the source and drain. creating an inversion layer.CMOS 1 Lesson 5-1: How to Identify a Transistor on the IC Cross Section How Is a Transistor Turned On or Off? (continued) Process (continued) Apply a logical 0 to the n-type and p-type transistors as follows: Applying a Logical 0 N-Type A negative electrical charge is applied to the gate. 0 P-Type A negative electrical charge is applied to the gate. The current can now flow freely between the source and drain. The negative charge of the gate repels the negatively charged ions of the n-well below the gate. Nwell Epitaxial Memory Aid The positive and negative ions attract and repel as follows: Ion Charge + + Ion Charge + Action Repel Attract Repel Intel Confidential 5-11 .

Lesson 5-1: How to Identify a Transistor on the IC Cross Section CMOS 1 5-12 Intel Confidential .

CMOS 1 Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section Intel Confidential 5-13 .

Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section CMOS 1 Lesson 5-2 Overview Introduction To ensure that transistors on the die are fabricated correctly. . . 5-17 5-14 Intel Confidential . . In this lesson. . . . . . . . . . . . 5-16 How Are Process Design Rules Identified on the Transistor Cross Section? . . . . . . . . . . . . . . . . . . . . . . . . . a set of process-specific design rules must be followed. . . . . . . . . Your layout drawings directly affect the fabrication of the die. . . . . . . . . . . . . . . . . . . . . . . . . . . you will learn to identify some of the design rules on the IC cross section. . The following are covered in this lesson: Topic Page Objective Topics What Is a Design Rule? . . . 5-15 Basic Process Design Rules . . . . . . . . . . .

CMOS 1 Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section What Is a Design Rule? Introduction To avoid unwanted results in the fabrication of an IC. What you draw directly affects what is created on silicon. rules must be followed when drawing the layout. certain process-specific design rules must be followed when drawing layout. The minimum dimensions are defined by G Definition the smallest geometry and spacing that can accurately be fabricated the smallest geometry and spacing that maintains electrical isolation and/or functionality the minimum overlap of two materials G G How to Avoid Design Violations To avoid these process design violations. Intel Confidential 5-15 . The process design rules are the minimum allowable drawn dimensions. These rules affect the x and y dimensions of layout not the depth/vertical dimension.

. . . . . . . . . . . .Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section CMOS 1 Basic Process Design Rules 1. . . . Minimum Spacing . . . . . . . . . . . . . . 2. . . . . . . . . . . . Nwell Spacing . .0 2. Minimum Diffusion/Polysilicon Overlap . 3. Minimum Width S/D . . . 3. . . . . . . . . .0 B. . . 2. . . . . Nwell Overlap of Diffusion . . . 2. . . . . . . . . 10. . .0 C. . . . .0 B. . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Metal Overlap of Contact . . . . Metal A. . . . . . . . . . . . . . . . .0 C. . . 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nwell A. . . . . . . . . . . . . . . . . . Minimum Spacing of Stacked Gates . . . . . . . . .0 4. . Minimum Size . . . . . . . . . . . . . .0 D. . . . . . .0 C. . . . . . . . . . . N+ and P+ Diffusion A. Minimum Width . . . . . . . 4. . . . . . .0 C. . . . . Field Polysilicon to Diffusion Separation . . . . . 3. . . Minimum Spacing to Active Gate . . . .0 B. . . .0 x 2. . 2. . 0. . . . . . Metal Contacts A. Minimum Nwell Width . . . . . . . . . . . . . . . . . . 2. .0 D. . . . . . . 10. . . . . . . . . . . . . . . . . . . . . . . . . . . .0 3. . . . . . . . . . . . . . . . . . . . . . . . . . . Polysilicon A. . . 0. . 2. . 2. Nwell Spacing to Diffusion . . . . . . . . . . . Minimum Width . . . . . . . . . . . Minimum Spacing . .0 B. . . . . Minimum Spacing . . . Polysilicon End Cap . . . . . . . . . . . . . . .0 D. . . . .0 5-16 Intel Confidential . . . . . . . . . 2. . . . . . . . . . .0 B. . . . .0 5. .

minimum S/D width 5. minimum polysilicon width 3. contact width 4. contact width 6. min diffusion spacing Example 3. In the following example. metal overlap of contact 2. min polysilicon width 4. minimum metal overlap of contact 2. min S/D width 5. minimum diffusion spacing 6. minimum Nwell width 1.CMOS 1 Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section How Are Process Design Rules Identified on the Transistor Cross Section? Introduction Some of the basic process design rules can be identified in a cross section of the layout. min nwell width Nwell Epitaxial Intel Confidential 5-17 . the following rules can be identified: 1.

Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section CMOS 1 5-18 Intel Confidential .

CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram Intel Confidential 5-19 .

. . . . . . . . .Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1 Lesson 5-3 Overview Introduction Critical to a good design. . . . The following topics are covered in this lesson: Topic Page Objective Topics What Is a Stick Diagram? . . . . . . . . . 5-29 Lab 5-3. . . . . . 5-26 How Is the Width of a Layout Drawing Estimated from a Stick Diagram? . . .a: Create a Stick Diagram . . . . . . . . . . . . . 5-31 5-20 Intel Confidential . . . . . 5-24 Lab 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . In this lesson. . . . . . . . . . . . . . . . . . you will learn how to create a stick diagram for transistor placement and connections. . . . . . . . . . . . . . . . . . . 5-21 Legend for a Stick Diagram . . . . . . . . . . . . is creating a good plan before drawing any layout. . . . . . . . . .b: Estimate the Width of a Layout Drawing from a Stick Diagram . . 5-22 Series and Parallel Transistors in a Stick Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 How Is a Stick Diagram Created? . .

This diagram is a shorthand representation of what your layout will look like. A stick diagram is a technique to generate a free-form. Definition ✍ Parts of a Stick Diagram Note: In layout. Graphical symbols representing the transistors are drawn relative to each other and are connected together by other symbols representing the interconnect mask layers. The stick diagram equivalents of a transistor-level schematic are as follows: Transistor-level Schematic Stick Diagram S/D (p-type) Gate (polysilicon) S/D (n-type) Gate (polysilicon) Practice How many transistors are in the following stick diagram? Intel Confidential 5-21 . topological plan of a circuit for layout without regard to the actual geometry sizing or process design rules. This diagram helps you plan where to place transistors to achieve the maximum density and best performance. transistors are formed by crossing polysilicon and diffusion.CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram What Is a Stick Diagram? Introduction To help create an optimal layout. first create a stick diagram.

Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1 Legend for a Stick Diagram Introduction Stick diagrams are best drawn in color but can be drawn in black and white using different patterns for the lines. The legend for the different symbols is as follows: Layer P Diffusion N Diffusion Polysilicon Metal Metal Contacts N-Well Symbol Color Legend X Example The INVERTER schematics and stick diagram are as follows: A OUT Vcc A OUT Vss 5-22 Intel Confidential .

transistors will often be drawn in series or parallel. Series transistors are drawn with one path from Vcc/Vss to the output node. as follows: A B OUT Vss OUT Vss A B Intel Confidential 5-23 . as follows: Vcc A N1 OUT Series Transistors B OUT A B Parallel Transistors Parallel transistors are drawn with multiple paths from Vcc/Vss to the output node.CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram Series and Parallel Transistors in a Stick Diagram Introduction When converting transistor-level schematics to stick diagrams.

Convert the transistor-level schematic. plan to have the p-type devices above the n-type devices. 3. All metal connections to polysilicon and diffusions must have at least one contact. Label the gates. b. Procedure Guidelines G When creating parallel transistors in the stick diagram. d. Create a stick drawing as follows: Step 1. Trace the transistor-level schematic and label the stick diagram to match. Both S/D of a transistor cannot be connected to the same node. # of transistors = 2 (# of inputs) 2. you can achieve a good layout for simple schematics. c. from the logic-level schematic. Draw the transistor-level schematic of the logic-level schematic. All common nodes must be connected. For this class. Make sure that all S/D nodes of each transistor match between the transistor-level schematic and the stick diagram. Draw vertical polysilicon lines to create the correct number of gates. a. G G G G G 5-24 Intel Confidential .Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1 How Is a Stick Diagram Created? Introduction There are some well-defined methods for creating stick drawings. When polysilicon crosses diffusion a transistor is always created. Do not connect to S/D regions with polysilicon. Action Determine how many transistors are needed. Draw horizontal lines for the p-type and n-type diffusion. minimize the number of connections to the output node. By following the steps outlined below.

b. For this class. Step 1. Draw horizontal lines for the p-type and n-type diffusion. Action Determine how many transistors are needed. plan to have the p-type devices above the n-type devices. A Vcc OUT Vss Intel Confidential 5-25 . Draw the transistor-level schematic of the logic-level schematic. Convert the transistor-level schematic. A OUT c. # of transistors = 2 (1) = 2 2. Trace the transistor-level schematic and label the stick diagram to match. Draw vertical polysilicon lines to create the correct number of gates. A OUT 3. Label the gates. from the logic-level schematic.CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram How Is a Stick Diagram Created? (continued) Example Use the procedure described and create a stick diagram for the Inverter. a.

3. Convert the transistor-level schematic. 2. 3.a: Create a Stick Diagram Introduction Now that you know how to draw stick diagrams for transistor-level schematics. you will draw a stick diagram for the following exercises. a. c. plan to have the p-type devices above the n-type devices. # of transistors = 2 (# of inputs) 2. from the logic-level schematic. create a stick diagram for a 2-input NOR function. Draw vertical polysilicon lines to create the correct number of gates. Using the procedure described. Trace the transistor-level schematic and label the stick diagram to match. d. 4. create a stick diagram for a 3-input NAND function. Draw horizontal lines for the the p-type and n-type diffusion. Instructions for Lab 5-3. create a stick diagram for a 3-input NOR function. 5-26 Intel Confidential . Using the procedure described.a 1. Using the procedure described. Using the procedure described. Make sure that all S/D nodes of each transistor match between the transistor-level schematic and the stick diagram. b. create a stick diagram for a 2-input NAND function. Draw the transistor-level schematic of the logic-level schematic. Label the gates. Step 1. For this class.Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1 Lab 5-3. Action Determine how many transistors are needed.

OUTB OUTA A B C Intel Confidential 5-27 . Using the procedure described and the following logic-level schematic. Using the procedure described and the following logic-level schematic. IN OUT 8.CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram Instructions for Lab 5-3. draw the stick diagram. draw the stick diagram. A B OUT C D 7. Using the procedure described and the following logic-level schematic. draw the stick diagram. A B C OUT 6. draw the stick diagram. A B OUT 9. Using the procedure described and the following logic-level schematic.a 5. draw the stick diagram. Using the procedure described and the following logic-level schematic.

Using the procedure described and the following logic-level schematic. draw the stick diagram.a 10. Using the procedure described and the following logic-level schematic. draw the stick diagram. draw the stick diagram. draw the stick diagram. A B C OUT 12. Using the procedure described and the following logic-level schematic. A B C OUT 13. A OUT B C 5-28 Intel Confidential . A B OUTA C OUTB 11.Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1 Instructions for Lab 5-3. Using the procedure described and the following logic-level schematic.

Action Starting at one end of the stick diagram. you must be aware of the layout design rules. Procedure 2. Intel Confidential 5-29 . Compare the width of the p-type and n-type transistors. This gives you the width for the p-type transistors. continued. Determine the width of your layout as follows: Step 1. This gives you the width of the n-type transistors. Repeat the above step for all objects for the n-type transistors. add up the minimum width and spacing requirements for all objects for the p-type transistors in the diagram.. The larger value is the estimated width for the layout drawing.CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram How Is the Width of a Layout Drawing Estimated from a Stick Diagram? Introduction To be able to calculate an area estimation. 3. and you must have a stick diagram..

Repeat the above step for all objects for the n-type transistors. 5-30 Intel Confidential .Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1 How Is the Width of a Layout Drawing Estimated from a Stick Diagram? (continued) Example Use the procedure to estimate the width of the Inverter layout drawing. 2 2 2 2 2 2 2 2 Vcc A OUT 2 Vss 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 = 18µ 2. The larger value is the estimated width for the layout drawing. this cell is 18µ wide. Vcc A OUT Vss 2 2 2 2 2 2 2 2 + 2 + 2 + 2 + 2 + 2 + 2 = 14µ 3. This gives you the width of the n-type transistors. Since 18µ is larger than 14µ. add up the minimum width and spacing requirements for all objects for the p-type transistors in the diagram. Compare the width of the p-type and n-type transistors. Step 1. Action Starting at one end of the stick diagram. This gives you the width for the p-type transistors.

Compare the estimated value to actual value. Compare the width of the p-type and n-type transistors. 2. a. b. add up the minimum width and spacing requirements for all of the objects for the p-type transistors in the diagram. Instructions for Lab 5-3. This gives you the width of the n-type transistors. Use your stick drawing and estimate the width of the layout drawing. Measure the actual width of the layout drawing.b: Estimate the Width of a Layout Drawing from a Stick Diagram Introduction Now that you know how to estimate the width of a layout drawing from a stick diagram. Complete the following exercises for both logic functions. Action Starting at one end of your stick diagram. Are the values close? Intel Confidential 5-31 . you will use your previous stick diagrams to estimate the layout drawing width and compare this value to the actual layout drawing width. The larger value is the width of your cell. 3. Step 1. Repeat the above step for all of the objects for the n-type transistors.b 1. Use the stick drawing and layout drawing you drew for the 2-input NOR and 3-input NAND. This gives you the width for the p-type transistors.CMOS 1 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram Lab 5-3.

Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram CMOS 1 5-32 Intel Confidential .

CMOS 1 Lesson 5-4: How to Get Better Layout Density with Node Sharing Lesson 5-4: How to Get Better Layout Density with Node Sharing Intel Confidential 5-33 .

. .Lesson 5-4: How to Get Better Layout Density with Node Sharing CMOS 1 Lesson 5-4 Overview Introduction Arranging transistors so the common nodes share the same S/D diffusion region helps to gain better density and performance. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 Lab 5-4: Use Node Sharing to Increase Density . . . . The following topics are covered in this lesson: Topic Page Objective Topics What Is Node Sharing? . 5-35 How Is Node Sharing Achieved? . In this lesson. . . . . . . you will learn to arrange the transistors so common nodes share the same S/D diffusion region whenever possible. . . . . . 5-38 5-34 Intel Confidential . . . . . . . . . . . . . .

By touching or overlapping the common terminal. S/D Diffusion Terminals with Design Rule Spacing Vcc Vcc Definition Example ZING Overlapping S/D Diffusion Terminals Vcc ZANG ZING ZANG Intel Confidential 5-35 . as shown in the following graphic. the two transistors take up less room than if the two transistor are spaced away from each other according to the diffusion to diffusion spacing process design rule. it is often necessary for common S/D nodes to share the same diffusion region. Node sharing is touching or overlapping of same-node S/D terminals from two different transistors. thus taking up less room. Two p-type transistors that share a common node can be drawn so that the common node of the transistors overlaps.CMOS 1 Lesson 5-4: How to Get Better Layout Density with Node Sharing What Is Node Sharing? Introduction In the attempt to draw more transistors in less area.

Identify the internal nodes on the stick diagram and label each internal node with the same name you gave it on the transistor-level schematic. 4.. This arrangement G Procedure 3. as follows: Step 1. Try to rearrange the common nodes so that they are next to each other. Look at the n-type and the p-type transistors on the stick diagram and identify any common nodes that are not drawn next to each other. Find the nodes that can be shared. 2. you can determine which transistors should share nodes and rearrange the transistors in the stick diagram.. 5-36 Intel Confidential .Lesson 5-4: How to Get Better Layout Density with Node Sharing CMOS 1 How Is Node Sharing Achieved? Introduction Before creating a layout drawing. Action Identify the internal nodes on the transistor-level schematic and label them with unique names. reduces the breaks in diffusion — better density shorter wire lengths fewer routing lines minimizes routing — — G continued.

Identify the internal nodes on the stick diagram and able each internal node with the same name you gave it on the transistor-level schematic. 4. OUT A N1 B ZING Intel Confidential 5-37 . OUT ZING Action Identify the internal nodes on the transistor-level schematic and label them with unique names. A B Step 1.CMOS 1 Lesson 5-4: How to Get Better Layout Density with Node Sharing How Is Node Sharing Achieved? (continued) Example Use the procedure to achieve node sharing for the following logic-level schematic. B A OUT ZING N1 2. Try to rearrange the common nodes so that they are next to each other. OUT B N1 A ZING 3. Look at the n-type and the p-type transistors on the stick diagram and identify any common nodes that are not drawn next to each other.

1. A B 5-38 Intel Confidential . Instructions for Lab 5-4 Use the node-sharing procedure to create a layout drawing for each of the following logic-level schematics. A B Out b. you will use the node sharing procedure to draw the stick drawings for the following logic-level schematics.Lesson 5-4: How to Get Better Layout Density with Node Sharing CMOS 1 Lab 5-4: Use Node Sharing to Increase Density Introduction Now that you know how to achieve node sharing. C Out D E d. N17 Do It PHZ c. a. BING BANG BOOM ZAP e.

CMOS 1 Lesson 5-5: How to Estimate Area 54 Lesson 5-5: How to Estimate Area Intel Confidential 5-39 .

5-42 Units of Measure Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Lesson 5-5: How to Estimate Area CMOS 1 Lesson 5-5 Overview Introduction A very important aspect in the layout of any design is the area utilized by the transistors and the interconnect. . . . . . . . . . . . . . . . . 5-47 5-40 Intel Confidential . . . . . . . . . . . . . .b: Convert Units of Measure . . . 5-46 Lab 5-5. . . The following topics are covered in this lesson: Topic Page Objective Topics Area Calculation . . . . . . . . . . . . .a: Calculate Area . .c: Calculate the Average Area per Transistor . . . . . . . . . . 5-41 Lab 5-5. . . . . . . . . . . . you will learn to calculate area values. . . . 5-43 Lab 5-5. . . . . . . . . . . . . 5-44 Average Area per Transistor Calculation . . . In this lesson. . .

There is a simple formula to determine area. then the area units are square microns (µ2). The formula to calculate area is: area = width x length area = X * Y If X = 4 inches and Y = 2 inches. Area is the actual space that the layout will occupy. If the length and width are measured in microns (µ).CMOS 1 Lesson 5-5: How to Estimate Area Area Calculation Introduction Area estimation is used to forecast the space needed for your circuit which is an important part of planning. then the area is calculated as follows: Area = 4 in * 2 in = 8 in2 Calculation Y X Area Units The units for area are “square” units. Intel Confidential 5-41 .

Lesson 5-5: How to Estimate Area

CMOS 1

Lab 5-5.a: Calculate Area
Introduction Now that you know the formula to calculate area, you will complete the following area calculations.

Instructions for Lab 5-5.a
1.

Calculate the area, given the following width and length values. a. b. c. d. 20 µ x 100 µ = 85 µ x 34 µ = 56 µ x 135 µ = 97 µ x 210 µ =

2.

Given the area and one of the sides, calculate what the other side must be. a. b. c. 58 µ x ____ = 5626 µ2 13 µ x ____ = 312 µ2 56 µ x ____ = 1900 µ2

5-42

Intel Confidential

CMOS 1

Lesson 5-5: How to Estimate Area

Units of Measure Conversion
Introduction It is important to know how to convert between mils and microns and vice versa, because both units of measure are used in chip design. The micron is the unit of measure in a transistor layout. However, the mil is the unit of measure when dealing with the functional unit, unit, or chip level. The units of measure are as follows: micron (µ) = 1,000,000th of a meter mil = 1,000th of an inch Conversion
G

Units of Measure

To convert mils to microns, multiply by 25.4 µ/mil mil * (25.4 µ/mil) = µ Example: 2 mil * (25.4 µ/mil) = 50.8 µ

G

To convert microns to mils, divide by 25.4 mil/µ µ / (25.4 mil/µ) = mil Example: 28 µ / (25.4 mil/µ) = 1.1 mil

G

To convert square mils (m2) to square microns (µ2), multiply by
645.16 µ2/m2

m2 * (645.16 µ2/m2) = µ2 Example: 120 m2 * (645.16 µ2/m2) = 77419.2µ2 Rounding All results must be rounded to two digits to the right of the decimal point.

Intel Confidential

5-43

Lesson 5-5: How to Estimate Area

CMOS 1

Lab 5-5.b: Convert Units of Measure
Introduction Now that you know how to convert the units of measure for layout drawings, you will complete the following unit conversions.

Instructions for Lab 5-5.b 1. Fill in the correct values for the micron column in the following table: mil
1 354 443 138

Conversion
* 25.4 * 25.4 * 25.4 * 25.4 = = = =

micron

2.

Fill in the correct values for the mil column in the following table: micron
25.4 5435 8943 138

Conversion
/ 25.4 / 25.4 / 25.4 / 25.4 = = = =

mil

3.

Fill in the correct values for the mil2 column in the following table: mil2
1 123 321 645

Conversion
* 645.16 * 645.16 * 645.16 * 645.16 = = = =

micron2

5-44

Intel Confidential

b 4. Fill in the correct values in the mil2 column in the following table: Device Area (mil2) 12 10.CMOS 1 Lesson 5-5: How to Estimate Area Instructions for Lab 5-5.7 33 # of Devices 8 7 11 15 23 = = = = = Area/Transistor Intel Confidential 5-45 .3 14.4 18.

To calculate the area per transistor. then the total area and density values are calculated as follows: total_area = 100µ * 100µ = 10000µ2 density = 10000µ2 / 25 transistors = 400µ2/transistor Calculation 5-46 Intel Confidential . you must first determine the total area of the transistors.Lesson 5-5: How to Estimate Area CMOS 1 Average Area per Transistor Calculation Introduction The average area per transistor or density can be calculated with a simple formula. the smaller the values is the better. This information will be used in planning. use the total area value in the following formula to calculate the density. The average area per transistor is a value used to compare different layout drawings. density = total_area / number_logic-level_trans Example If the layout of a circuit contains 25 transistors and is 100µ by 100µ. total_area = X * Y Next.

a. If the total area of the layout of a circuit is 350µ2 and the average area per transistor is 50µ2. complete the calculation.CMOS 1 Lesson 5-5: How to Estimate Area Lab 5-5. or the density for layout drawings. then what are the total area and density values? b. you will complete the following density calculations.c: Calculate the Average Area per Transistor Introduction Now that you know how to calculate the average area per transistor. If the layout of a circuit contains 20 transistors and is 100µ by 90µ. Given the following information. then what are the total area and density values? c. If the layout of a circuit contains 75 transistors and is 100µ by 90µ.c 1. then how many transistors are in the layout? Intel Confidential 5-47 . Instructions for Lab 5-5.

Lesson 5-5: How to Estimate Area CMOS 1 5-48 Intel Confidential .

CMOS 1 Lesson 5-6: How to Calculate Resistance Lesson 5-6: How to Calculate Resistance Intel Confidential 5-49 .

. 5-58 5-50 Intel Confidential . . . . . . . you will learn to calculate resistance. . . . . . . . . In this lesson. . . . . . . . . 5-51 Lab 5-6. . . . .b: Calculate Sheet Resistance . . . . . . . . . . . . . . The following topics are covered in this lesson: Topic Page Objective Topics What Is Resistance? . . . . . . . .Lesson 5-6: How to Calculate Resistance CMOS 1 Lesson 5-6 Overview Introduction A very important aspect in the layout of any design is the resistance of the interconnect. . . . . .a: Calculate Resistance Values . . . . . . . . . . . . . . 5-56 Lab 5-6. . 5-53 How Is Sheet Resistance Calculated? . . . . . . . . . . . .

Resistors are drawn to show resistance. Intel Confidential 5-51 . so the total current flows through all of the resistors (R1 and R2 .. R Total = R 1 + R 2 + … + R n current current R1=20 Ω R2=40 Ω current For the above resistors the total resistance is as follows: R Total = 20Ω + 40Ω = 60Ω continued.. The unit of measure for resistance is the ohm (Ω).. and Rn). Definition The effects of resistance in series or parallel interconnect are described below. The total resistance is equal to the sum of the individual resistances. Series Resistance Calculation The current has only one path to follow. It can be either intentional or parasitic.. You must be able to increase and decrease the resistance in a circuit to obtain the correct circuit functionality. Resistance is the opposition of current flow. The orientation of the resistor does not affect the resistor.CMOS 1 Lesson 5-6: How to Calculate Resistance What Is Resistance? Introduction Resistance has a direct and measurable effect on the performance of a circuit. Each material has a different resistive value that represents how much that material opposes current flow.

  20Ω 40Ω  5-52 Intel Confidential . and it follows the path of least resistance: through the smallest resistor.  R1 R2 R3 Rn  In the following example. since R1 has less resistance then R2.+ ----.+ ---------. the current has more than one path to follow. 1 R total = --------------------------------------------------------------1 1 1 1  ----. R1=20Ω current current current current R2=40Ω For the above resistors the total resistance is as follows: 1 R total = ---------------------------------. more current will flow through R1 than R2. The total resistance will be less than the smallest resistor.+ … + ----.+ ----.= 13.33Ω 1 1  ---------.Lesson 5-6: How to Calculate Resistance CMOS 1 What Is Resistance? (continued) Parallel Resistance Calculation With parallel resistors.

complete the exercises. you will calculate the resistance in the following exercises. Intel Confidential 5-53 . Are these resistors in series or parallel? Calculate the total resistance. complete the exercises. b. R1 = 30Ω R1 = 40Ω R1 = 50Ω a. Given the following resistors.a 1. 2. R1 = 60Ω R2 = 65Ω R3 = 105Ω a. Instructions for Lab 5-6. Are these resistors in series or parallel? Calculate the total resistance. b. Given the following resistors.a: Calculate Resistance Values Introduction Now that you know how to calculate the total resistance.CMOS 1 Lesson 5-6: How to Calculate Resistance Lab 5-6.

Lesson 5-6: How to Calculate Resistance CMOS 1 Instructions for Lab 5-6. 5-54 Intel Confidential . R1 = 10Ω R2 = 20Ω R3 = 30Ω a. 4.a 3. b. Are these resistors in series or parallel? Calculate the total resistance. complete the exercises. R1 = 85Ω R5 = 1000Ω R2 = 620Ω R3 = 330Ω R4 = 100Ω a. Given the following resistors. Are these resistors in series or parallel? Calculate the total resistance. complete the exercises. b. Given the following resistors.

R1 = 1000Ω R2 = 880Ω R3 = 316Ω a. complete the exercises. Intel Confidential 5-55 . b. 6. Are these resistors in series or parallel? Calculate the total resistance. Are these resistors in series or parallel? Calculate the total resistance.a 5.CMOS 1 Lesson 5-6: How to Calculate Resistance Instructions for Lab 5-6. complete the exercises. R1 = 100Ω R2 = 100Ω a. Given the following resistors. b. Given the following resistors.

but each square of the same material will have the same amount of resistance. you must know the ohms per square. so both are 30 ohms.. To calculate this. Some examples of values are as follows: G G G Definition S/D Diffusion Polysilicon Metal 1 30Ω/square 25Ω/square .03Ω/square The dimensions of a square can be 3 x 3 or 20 x 20..Lesson 5-6: How to Calculate Resistance CMOS 1 How Is Sheet Resistance Calculated? Introduction In order to determine if routing has met the engineering specifications. 3µ x 3µ 30Ω 20µ x 20µ 30Ω Practice Which of the above materials has the least resistance? continued. The sheet resistance or ohms per square or RHO is the electrical resistance per square of a given material. Each of the following shapes represent one square of diffusion. 5-56 Intel Confidential . it is often important to know how much resistance the routing has.

Total Resistance = RT = ST * Sheet Resistance 15 squares * 25Ω/square = 375Ω Intel Confidential 5-57 . Action Calculate the number of squares. Action Calculate the number of squares. Step 1. then how much resistance does this piece of polysilicon have? 2µ 30µ Step 1. If polysilicon has a sheet resistance of 25Ω/square. Calculate the total resistance. Total Resistance = RT = ST * Sheet Resistance Example A piece of polysilicon is 2µ wide and 30µ long. Number of squares = ST = length / width 2. multiply the number of squares by the sheet resistance. Number of squares = ST = 30µ / 2µ = 15 squares 2. Calculate the total resistance.CMOS 1 Lesson 5-6: How to Calculate Resistance How Is Sheet Resistance Calculated? (continued) Procedure Calculate the sheet resistance as follows. multiply the number of squares by the sheet resistance.

5µ wide? 3.3Ω/square. If Metal1 has a sheet resistivity of 0.b: Calculate Sheet Resistance Introduction Now that you know how to calculate sheet resistance. how much polysilicon should be added if the polysilicon width is 20µ and you need 30Ω of resistance? 4.b 1. how long must the resistor be? 2. width. An engineer wants a 5000Ω diffusion resistor that is 10µ wide. A Metal1 line is 2. and length in the following exercises.4µ wide and runs 44000µ across the chip. you will calculate the sheet resistance.084Ω/square. If diffusion has a sheet resistivity of 30Ω/square. what is the total resistance of the node? 5-58 Intel Confidential .Lesson 5-6: How to Calculate Resistance CMOS 1 Lab 5-6. Instructions for Lab 5-6. If polysilicon has a sheet resistivity of 22. If polysilicon has a sheet resistivity of 30Ω/square. what is the total resistance of a polysilicon line that is 300µ long and 2. An inverter needs to have some delay added to its output.

CMOS 1 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing 56 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing Intel Confidential 5-59 .

. .b: Visually Verify a Layout Drawing . . into a layout drawing. . . . . 5-64 Visually Verifying a Layout Drawing . . 5-65 Lab 5-7. 5-62 How Is a Stick Diagram Converted to a Layout Drawing? . . your plan. . . . . . . . . . . you will learn how to convert the stick diagram. . .a: Convert a Stick Diagram to a Layout . . . . . . . . . . In this lesson. . . . . . . . . . . . . 5-66 5-60 Intel Confidential . . . . . .Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing CMOS 1 Lesson 5-7 Overview Introduction The final step of the layout design process is actually create a layout drawing. . . . . . . . . . . . . 5-63 Lab 5-7. . . . . . . The following topics are covered in this lesson: Topic Page Objective Topics What Is a Layout Drawing? . . . . . . . . . . . . . . . 5-61 What Is Transistor Size? . . . . . .

A layout drawing is the actual geometries that will create the transistors and routing on the IC die. Logic-level Schematic Transistor-level Schematic A Stick Diagram Vcc A OUT OUT Vss Vcc Layout Drawing A OUT Vss Intel Confidential 5-61 . transistor-level schematic. Routing is created with metal. and layout drawing of an Inverter. polysilicon.CMOS 1 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing What Is a Layout Drawing? Introduction All prior information in this class has prepared you to create a layout drawing. and contacts. stick diagram. G Example The following graphics illustrate the logic-level schematic. G Definition Transistors are created with diffusion for the source and drain regions and with polysilicon for the gate region. The stick drawing is your actual plan for drawing your layout.

. G G the more energy the gate uses the more devices it can drive The z/l values are drawn on the logic-level schematic as follows. 16 8 Example 10/3 5/3 The following transistor layout shows the z and l dimensions.. the “l” value is assumed to be the default for the design process. The n-type transistors and p-type transistors have different z/l ratios.Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing CMOS 1 What Is Transistor Size? Introduction The transistor sizes are established by the engineering design specifications. The transistor size is determined by the z/l ratio which is the gate width and length. When there is only one number. Transistor-level Schematic polysilicon Layout Drawing z= width diffusion l = length 5-62 Intel Confidential . G G Definition z = gate width l = gate length The larger the ratio.

Do this by creating rectangles of the correct minimum width for each material. Redraw the stick diagram as a layout drawing. do not be concerned about the spacing process design rules. Redraw the stick diagram as a layout drawing. labeling all nodes. The steps to convert a stick drawing to a layout drawing are as follows: Step 1.CMOS 1 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing How Is a Stick Diagram Converted to a Layout Drawing? Introduction Once you have a stick diagram. Example Use the procedure to convert the Inverter stick diagram to a layout drawing. A Vcc Out Vss 2. Vcc A Vss OUT Intel Confidential 5-63 . At this time. labeling all nodes. Do this by creating rectangles of the correct minimum width for each material. the layout drawing can easily be created. Procedure 2. Action Get an idea of what the layout will look like by “fattening” the lines on your stick diagram. Step 1. Action Get an idea of what the layout will look like by “fattening” the lines on your stick diagram.

2-input NOR 2-input NAND 3-input NOR 3-input NAND Use the design rules provided by your instructor and draw the layout drawings for the following logic functions with the correct width and spacing design rules. b. d. c.a 1. Draw all materials to the correct minimum width process design rules. Redraw the stick diagram as a layout drawing.Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing CMOS 1 Lab 5-7. however do not be concerned about the spacing design rules at this time. labeling all nodes. 2. Do this by creating rectangles of the correct minimum width for each material. 2. Use a stick diagram and the following procedure to create the layout drawing that reflects the following logic functions. b. do not be concerned about the spacing process design rules. a. Step 1.a to draw the layout drawing in the following exercises. use the stick diagrams you drew in lab 5-3.a: Convert a Stick Diagram to a Layout Introduction Now that you know the process to convert a stick diagram to a layout drawing. At this time. a. Action Get an idea of what the layout will look like by “fattening” the lines on your stick diagram. c. 2-input NOR 2-input NAND 3-input NOR 3-input NAND 5-64 Intel Confidential . d. Instructions for Lab 5-7.

2. 4. 7. Polysilicon head minimum size: 6 x 6µ Diffusion head minimum size: 6 x 6µ Metal pitch: 5µ End cap: 2µ Tap density: 1/cell Contact to gate spacing: 2µ Width and spacing process-specific design rules Template width and spacing requirements Checklist Intel Confidential 5-65 .CMOS 1 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing Visually Verifying a Layout Drawing Introduction To ensure that layout drawings meet the process design rule specifications and template requirements. Check 1. 5. To verify that a layout drawing meets the process design rules. 8. complete the following checklist against your layout. 6. you must verify all layout drawings. 3.

Use the simplified process design rule checklist to verify the layout drawings your instructor provides. you are ready to verify your layout drawings. 2.Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing CMOS 1 Lab 5-7.b: Visually Verify a Layout Drawing Introduction Now that you know how to visually verify a layout drawing with the simplified process design rule checklist. Use the simplified process design rule checklist to verify the layout drawings you drew in prior labs.b 1. Instructions for Lab 5-7. 5-66 Intel Confidential .

CMOS 1 Lesson 5-8: How to Draw Layout with a Standard Cell Template 57 Lesson 5-8: How to Draw Layout with a Standard Cell Template Intel Confidential 5-67 .

....... The following topics are covered in this lesson: Topic Page Objective Topics What Is a Standard Cell Template? ..................................................... you will learn to draw a standard cell layout drawing to the specifications of a standard cell template..... 5-69 How Is a Layout Drawing Drawn with a Standard Cell Template? .............. you will use a standard cell template.......................................... 5-71 5-68 Intel Confidential .................................................... In this lesson.......Lesson 5-8: How to Draw Layout with a Standard Cell Template CMOS 1 Lesson 5-8 Overview Introduction To easily combine a layout drawing with other layout drawings.................... 5-70 Lab 5-8: Draw a Layout Drawing with a Standard Cell Template ..

reduce the drawing time and ensuring predictable performance. Layout drawn to specifications of a standard cell template can occupy a large area of an IC. A standard cell template is a graphical guide that defines the layout design rules to create standard cells. The requirements for standard cells are often communicated with a template. A typical standard cell template is as follows: Tap Region Definition Parts of a Standard Cell Template Vcc 10 µm NWELL Metal tracks for Interconnect 3 µm 2 µm Vss 10 µm NAC Region Intel Confidential 5-69 .CMOS 1 Lesson 5-8: How to Draw Layout with a Standard Cell Template What Is a Standard Cell Template? Introduction Standard cells are layout drawings that are drawn to a special set of layout requirements.

you must follow the specifications of a standard cell template. Transfer the template specifications to your drawing. Procedure Example With your instructor. Add the layout to your drawing. 10/2 IN 8/2 OUT 5-70 Intel Confidential . Create a layout drawing to the specifications of a standard cell template as follows. use the above procedure and the template provided to create a layout drawing for an Inverter. 3. Step 1. 2.Lesson 5-8: How to Draw Layout with a Standard Cell Template CMOS 1 How Is a Layout Drawing Drawn with a Standard Cell Template? Introduction To make sure that a layout meets the design specifications. Action Use the correct standard cell template.

3-input NAND C D E 12/1 OUT 6/1 d. 2-input NOR A B 12/1 OUT 6/1 c. Complex logic F G H J 12/1 OUT 8/1 Intel Confidential 5-71 . 2. a. Instructions for Lab 5-8 1. Use the template provided by your instructor to draw a standard cell layout drawing for the following logic functions. you will use one to draw a standard cell layout. Inverter 10/2 IN 8/2 OUT b. calculate how many transistors are needed for each layout function.CMOS 1 Lesson 5-8: How to Draw Layout with a Standard Cell Template Lab 5-8: Draw a Layout Drawing with a Standard Cell Template Introduction Now that you know what a standard cell template is. Given the following logic-level schematics.

Lesson 5-8: How to Draw Layout with a Standard Cell Template CMOS 1 5-72 Intel Confidential .

CMOS 1 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions 58 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions Intel Confidential 5-73 .

. . . you will learn to draw transistors with multiple legs and bent gates. . . .Lesson 5-9: How to Draw Layout to Meet Layout Restrictions CMOS 1 Lesson 5-9 Overview Introduction It is often necessary to alter how a transistor is drawn due to process or area restrictions. . . . . . The following topics are covered in this lesson: Topic Page Objective Topics How Is a Transistor Drawn with Multiple Legs? . 5-77 Lab 5-9: Draw Layout to Meet Layout Restrictions . In this lesson. . 5-75 How Is a Transistor Drawn with a Bent Gate? . 5-79 5-74 Intel Confidential . . . . . . . . . . .

Intel Confidential 5-75 . three parallel n-type transistors each with a z/l of 10/2 is equivalent to one n-type transistor with a z/l of 30/2. A transistor with multiple legs is a set of parallel transistors with a total z value equivalent to the desired z value. the gate must be broken into multiple legs.CMOS 1 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions How Is a Transistor Drawn with Multiple Legs? Introduction When a transistor is too long to fit into the given area or the transistor gate is too long for the maximum gate length of the process. For example... 10/2 10/2 10/2 30/2 Definition parallel transistors equivalent to the single transistor single transistor equivalent to the parallel transistors continued.

b. Round L1 up to the next whole number to get the actual number of legs. Action Calculate the number of legs needed to replace a single leg transistor as follows: a.75) = 4 Each leg is 30µ / 4µ = 7. # of Legs = round(L1) c. Number of legs = (total z) / (maximum z) = 30 / 8 = 3.Lesson 5-9: How to Draw Layout to Meet Layout Restrictions CMOS 1 How Is a Transistor Drawn with Multiple Legs? (continued) Procedure Drawing transistors with multiple legs consists of the following: Step 1. Draw the multiple legs of the transistor in parallel with the new gate length.5µ 5-76 .75 Number of legs = round (3. If L1 is not a whole number. Number of legs = (total z) / (maximum z) = 30 / 10 = 3 Each leg is 30µ / 3µ = 10µ. New gate length = (total z) / (# of legs) 2. A OUT Vss A Vss A OUT A Vss Intel Confidential Example 1 If z/l = 30/2 and the maximum z value is 10µ then. than continue to steps b and c. than this is the number of legs. Divide the total z value by the maximum z value. Example 2 If z/l = 30/2 and the maximum z value is 8µ then. L1 = (total z) / (maximum z) If L1 is a whole number. Divide the total z value by the actual number of legs to get the length of each leg.

do not count the overlap. Note: For this class. Action Calculate the total z value of the gate. Count length Overlapping corners Count length Bent gate with overlapping corners continued. draw bends at 90°. Symbolic editor CAD tools usually cannot draw bent gates. 2.CMOS 1 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions How Is a Transistor Drawn with a Bent Gate? Introduction Some processes allow the gate of a transistor to be bent. determine the total z value of the gate as follows: G G Do not count corners when calculating the total z value. Procedure Guidelines When drawing bent gates in this class. Bending the transistor gates can increase the layout density... Drawing layout with bent gates consists of the following: Step 1. the polygon editor CAD tools can draw bent gates. (See guidelines below.) Draw the layout with the bent gate. When both corners overlap. Intel Confidential 5-77 .

14µ = 4µ This bent gate provides an area savings of 4µ in the vertical dimension. Metal 1 Diffusion Contact 6µ Bent Gate Corner 14µ 6µ 6µ 5-78 Intel Confidential .Lesson 5-9: How to Draw Layout to Meet Layout Restrictions CMOS 1 How Is a Transistor Drawn with a Bent Gate? (continued) Example The following bent gate provides a savings of 4µ in the vertical dimension of the diffusion. Gate length = 6µ + 6µ + 6µ = 18µ Diffusion height = 14µ Diffusion height savings = 18µ .

once with a bent gate and once with multiple leg devices.CMOS 1 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions Lab 5-9: Draw Layout to Meet Layout Restrictions Introduction Now that you know how to draw layout to meet layout restrictions. Instructions for Lab 5-9 1. Draw each logic function twice. use the template provided by your instructor to draw a standard cell layout drawing for the following logic functions. 2-input NOR A B 12/2 OUT 10/2 3. Complex logic F G H J 12/2 OUT 8/2 Intel Confidential 5-79 . 3-input NAND C D E 20/2 OUT 12/2 4. Inverter 20/2 IN 8/2 OUT 2. The maximum z value is 8µ.

and how to create a layout drawing from a stick diagram. how to estimate area. you learned how transistors are created in silicon. how to calculate resistance.Lesson 5-9: How to Draw Layout to Meet Layout Restrictions CMOS 1 Chapter Summary Introduction In this chapter. you learned to do the following: G G G G G G G G G Summary identify a transistor and a diode on the IC cross section identify process design rules on the transistor cross section identify the parts of a stick diagram estimate area calculate resistance convert a stick diagram to a layout drawing get better layout density with node sharing draw layout with a standard cell template draw layout to meet layout restrictions 5-80 Intel Confidential . In this chapter.

CMOS 1 Appendix A: Glossary 0 Appendix A: Glossary Intel Confidential A-1 .

0 and 1. The unit of measurement for electrical current in coulombs per second. Also called linear. the terminal that controls the current flow. A numbering system with only two digits. but it is usually between one and two volts. One ampere flows in a circuit that has one ohm resistance when one volt is applied to the circuit. In a bipolar transistor. Cells are connected in a series to obtain a higher voltage or in parallel to obtain greater current capacity. The p-type diffusion of a semiconductor diode. The metal most often used in semiconductor processing to form the interconnects between the devices on an integrated circuit chip. Ten angstroms equals one nanometer. The unit used to depict the wavelength of light or other electromagnetic radiation. The voltage produced by a fresh cell depends on the materials used. A type of transistor where a flow of both conduction electrons and holes determines the device characteristics. Contrast with digital. Two hundred fifty-four million angstroms equals one inch. The n-type dopant commonly used for the source and drain of nchannel MOS integrated circuits.Appendix A: Glossary CMOS 1 Terms Alternating Current (AC) Aluminum An electrical current that continuously changes in magnitude and in direction of flow. A source of electromotive force (voltage and current) obtained from chemical reaction in an assembly called a cell. Ampere Analog Angstrom Anode Arsenic Base Battery Binary Bipolar A-2 Intel Confidential . A signal that varies in amplitude continuously and without interruption.

CMOS 1 Appendix A: Glossary Bi-CMOS A technology in which the advantages of bipolar transistors (speed) and of CMOS devices (low power consumption) are combined in the fabrication of a single IC. A square or rectangular area on the die that is used to attach the die to the package by wire bonding. Expressed in mho (ohm spelled backwards. This structure is often fabricated in the manufacturing of integrated circuits. 2. A substance through which electrons flow with relative ease. 1. Computer-AidedDesign (CAD) Conductance Conductivity Conductor Intel Confidential A-3 . An interconnection of electrical or electronic components to accomplish a specific function. Each transistor is made of three elements: gate.) The inverse of resistivity. A design technique (using a computer and special software) that can be used in the design of a product and in the verification of its performance by simulation. A circuit element formed by placing an insulating layer between two conducting layers. Bonding Pads Boron Capacitor Cathode Circuit Complementary Metal Oxide Semiconductor (CMOS) A semiconductor that has low power drain. A complete path that allows electrical current from one terminal of a voltage source to the other terminal. and source. The negative electrode of a semiconductor diode. A p-type dopant commonly used for the source and drain of pchannel MOS integrated circuits. It is produced by an integrated-circuit fabrication technique using both P-channel and N-channel MOS transistors. The reciprocal of resistance in DC circuits or of the real part of impedance in AC circuits. A measure of the ease of conducting current. drain.

The insulating material between the plates of a capacitor.Appendix A: Glossary CMOS 1 Contact A vertical hole cut into the field oxide and allowing connection of two vertical materials of an IC. Current that flows in only one direction. The movement of electrons through a circuit. usually without change in magnitude. the terminal to which the carriers flow. The deposition of a single crystal layer on the silicon wafer. The diode is used to control current flow. Diode Direct Current (DC) Doping Drain Electron Epitaxial (Epi) A-4 Intel Confidential . Another name for the impurities implanted into silicon devices. A semiconductor device made of n+ and p+ diffusions abutting. The movement of particles away from regions of high concentration (caused by the random thermal motion of atoms and molecules). 2. Current is measured in amperes. The basic atomic particle having a negative charge. A single piece of silicon cut from a wafer and containing the complete device. Current Die Dielectric Diffusion Digital Representing information in discrete or quantized form or in the form of pieces such as bits or digits. A process used to change the electrical characteristics of the wafer by ion implantation (diffusion). This is the first layer added to the new wafer and usually has a higher resistance than the raw wafer. In a MOS transistor. 1.

A process in which engineering schematics are transposed into graphic symbols that will by used to make a mask. It is considered the brain of a circuit or a computet. The process of growing a layer of silicon dioxide onto the wafer. Current path that divides from a single source into two or more separate paths that will later rejoin. a microprocessor is a hardware device that can be electrically “rewired” by using software instructions. the terminal that controls the current flow. A tiny slice or chip of material on which a complex electrical circuit is etched or imprinted. It appears as if it were a moving positive charge. It performs semi-intelligent functions based on software instructions. A circuit component has a resistance of one ohm when one volt applied to the component produces a current of one ampere. A cylindrical crystal grown from polysilicon material that is sliced into wafers. Fundamentally. Ingot Integrated Circuit (IC) Layout Micron (µ) Microprocessor Ohm (Ω) Oxidation Passivation Parallel Circuit Intel Confidential A-5 . A unit of length equal to one millionth of a meter. A process in which a thin layer of nitride is deposited over the metal layer to protect it.CMOS 1 Appendix A: Glossary Gate Hole In a MOS transistor. The central processor of a computer fabricated as an integrated circuit. The unit of electrical resistance. ICs are made from semiconductor material and work according to semiconductor physics. A vacancy within the valence band of a semiconductor material caused by the deficiency of an electron.

A type of electronically programmable semiconductor memory device which is programmed after manufacture. Raw silicon comes in ingots of poly prior to crystal growth. The opposition to current flow. such as silicon. A light sensitive material used during the photolithography process. A semiconductor memory which is programmed during manufacture. Polysilicon may be deposited accidentally during epitaxial deposition by depositing it too fast or at too low a temperature. that exhibits characteristics between a good conductor and a poor conductor. It results in loss of energy in a circuit and is dissipated as heat. It is related to the number of n-type donor. The contents of random access memory can be readily changed. Photo Resist Polycrystalline Silicon (Polysilicon) Programmable Read Only Memory (PROM) Random Access Memory (RAM) Read-Only Memory (ROM) Resistance Semiconductor Series Circuit Sheet Resistance (RHO) A-6 Intel Confidential . a memory system in which any memory location can be directly accessed as easily and as quickly as any other.Appendix A: Glossary CMOS 1 Phosphorus The n-type dopant commonly used for the emitter diffusion in standard bipolar integrated-circuit technology and for the n-channel source and drain of MOS integrated circuits. Silicon composed of many (poly) crystals. or acceptor atoms in a semiconductor. Chemical vapor deposition (CVD) of polysilicon usually occurs on a layer of silicon dioxide. A type of material. but whose contents are unalterable once programmed. In computer or digital systems. Current that flows through one or more devices in a single path. A measurement (in ohms per square cm) that is frequently used to evaluate predispositions and drive-ins. or p-type acceptor donor. The contents can be read but cannot be altered.

that is used as the foundation on which integrated circuits are built. made usually from semiconductor material such as silicon.000 transistors.10. The process of creating an integrated circuit (IC) that contains 1000 .CMOS 1 Appendix A: Glossary Silicon Dioxide The oxide of silicon that is used (either deposited or thermally grown) in chip fabrication as an insulating layer and as a barrier to unwanted impurities. In a MOS transistor. The substrate. A three-terminal circuit element manufactured using semiconductor material. the terminal from which the carriers flow. Source Transistor Very Large Scale Integration (VLSI) Wafer White Space Intel Confidential A-7 . The transistor provides signal amplification. Unused area on the die.

Appendix A: Glossary CMOS 1 A-8 Intel Confidential .

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