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Class Notes Digital Lec25

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03/21/2011

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# `~ivjvcbx t wc,G,we,G·, 9661920-73/4980

Telephone : PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq
XvKv-1000, evsjv‡`k

DEPT. OF APPLIED PHYSICS, ELECTRONICS & COMMUNICATION ENGINEERING UNIVERSITY OF DHAKA
DHAKA-1000, BANGLADESH FAX: 880-2-8615583 E-MAIL: APECE@univdhaka.edu

Ref. No............................

September 21, 2010 Dated, the………………………….

Combinational Circuits: A combinational circuit is one where the output at any time depends only on the present combination of inputs at that point of time with total disregard to the past state of the inputs. The logic gate is the most basic building block of combinational logic. The logical function performed by a combinational circuit is fully defined by a set of Boolean expressions. In combinational circuits, input variables come from an external source and output variables feed an external destination. The different steps involved in the design of a combinational logic circuit are as follows – (1) Statement of the problem. (2) Identification of input and output variables. (3) Expressing the relationship between the input and output variables. (4) Construction of a truth table to meet input-output requirements. (5) Writing Boolean expressions for various output variables in terms of input variables. (6) Minimization of Boolean expressions. (7) Implementation of minimized Boolean expressions. The following guidelines should be followed while choosing the preferred form for hardware implementation – (1) The implementation should have the minimum number of gates, with the gates used having the minimum number of inputs. (2) There should be a minimum number of interconnections, and the propagation time should be the shortest. (3) Limitation on the driving capability of the gates should not be ignored. Half-Adder: A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1
A B Half Adder S C

Fig.: Truth table of a half-adder. A half-adder is an arithmetic circuit block that can be used to add two bits. Such a circuit thus has two inputs that represent the two bits to be added and two outputs, with one producing the SUM output and the other producing the CARRY. The Boolean expressions for the SUM and CARRY outputs are given by the equations – SUM, S = A.B + A .B = A ⊕ B CARRY, C = A.B Figure below shows the implementation of a half-adder using a two-input EX-OR gate for the SUM output and a twoinput AND gate for the CARRY output.
A B

S = A .B + A.B
C=A.B

Fig.: Logic implementation of a half-adder. [Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

Lec-25, Pg-01

`~ivjvcbx t wc,G,we,G·, 9661920-73/4980

Telephone : PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq
XvKv-1000, evsjv‡`k

DEPT. OF APPLIED PHYSICS, ELECTRONICS & COMMUNICATION ENGINEERING UNIVERSITY OF DHAKA
DHAKA-1000, BANGLADESH FAX: 880-2-8615583 E-MAIL: APECE@univdhaka.edu

Ref. No............................

September 21, 2010 Dated, the………………………….

Full Adder: A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM and a CARRY output. Such a building block becomes a necessity when it comes to adding binary numbers with a large number of bits.
B Augend bit input A 0 0 0 0 1 1 1 1 Addend bit input B 0 0 1 1 0 0 1 1 Carry bit input CIN 0 1 0 1 0 1 0 1 Sum bit output S 0 1 1 0 1 0 0 1 Carry bit output COUT 0 0 0 1 0 1 1 1

S CIN FA COUT

A

Fig.: Truth table for a full-adder circuit. Figure shows the truth table of a full adder circuit showing all possible input combinations and corresponding outputs. Using the sum-of-products method, the expression for S can be written as – S = A B C IN + A BC IN + AB C IN + ABC IN
= A B C IN + BC IN + A B C IN + BC IN = A (B ⊕ C IN
IN

(

) ( ) + A(B ⊕ C )

)

= A ⊕ B ⊕ C IN The sum-of-products expression for COUT can be written as – C OUT = A BC IN + AB C IN + ABC IN + ABC IN
= C IN ( A B + AB ) + AB (C IN + C IN ) = C IN ( A ⊕ B ) + AB The expressions for S and COUT can be implemented as shown below.
A B CIN COUT FA S

Fig.: Complete circuitry for a full adder.

Lec-25, Pg-02

`~ivjvcbx t wc,G,we,G·, 9661920-73/4980

Telephone : PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq
XvKv-1000, evsjv‡`k

DEPT. OF APPLIED PHYSICS, ELECTRONICS & COMMUNICATION ENGINEERING UNIVERSITY OF DHAKA
DHAKA-1000, BANGLADESH FAX: 880-2-8615583 E-MAIL: APECE@univdhaka.edu

Ref. No............................

September 21, 2010 Dated, the………………………….

From memory LOAD CLK D CLK D CLK D CLK D B register B3 B2 B1 B0

C4 FA S3

C3 FA S2

C2 FA S1

C1 FA S0

C0

D CLK

A3

D CLK

A2

D CLK

A1

D CLK

A0 A register

CLR CLEAR
TRANSFER

CLR

CLR

CLR

Accumulator outputs

CLEAR

TRANSFER t1 t2 t3 t4 t5

Fig.: Complete four-bit parallel adder with registers and signals used to add binary numbers. Figure shows the diagram of a four-bit parallel adder including the storage registers. The augend bits A3 through A0 are stored in the accumulator registers and the addend bits B3 through B0 are stored in the B register. The contents of the A register is added to the contents of the B register by the four FAs, and the sum is produced at outputs S3 through S0. C4 is the carry out of the fourth FA, and it can be used as the carry input to a fifth FA, or as an overflow bit to indicate that the sum exceeds 1111. Assuming C0=0, that is, there is no carry into the LSB position, the process of adding the binary numbers 1001 and 0101 is – 1) [A]=0000. A CLEAR pulse is applied to the asynchronous inputs ( CLR ) of each FF in register A. This occurs at time t1.

Lec-25, Pg-03

`~ivjvcbx t wc,G,we,G·, 9661920-73/4980

Telephone : PABX : 9661920-73/4980

dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq
XvKv-1000, evsjv‡`k

DEPT. OF APPLIED PHYSICS, ELECTRONICS & COMMUNICATION ENGINEERING UNIVERSITY OF DHAKA
DHAKA-1000, BANGLADESH FAX: 880-2-8615583 E-MAIL: APECE@univdhaka.edu

Ref. No............................

September 21, 2010 Dated, the………………………….

2) [M] [B]. This first binary number is transferred from memory (M) to the B register. In this case, the binary number 1001 is loaded into register B on the PGT of the LOAD pulse at t2. 3) [S] [A]. With [B]=1001 and [A]=0000, the full adders produce a sum of 1001, that is, [S]=1001. These sum outputs are transferred into the A register on the PGT of the TRANSFER pulse at t3. This makes [A]=1001. 4) [M] [B]. The second binary number 0101 is transferred from memory into the B register on the PGT of the second LOAD pulse at t4. This makes [B]=0101. 5) [S] [A]. With [B]=0101 and [A]=1001, the FAs produce [S]=1110. These sum outputs are transferred into the A register when the second TRANSFER pulse occurs at t5. Thus, [A]=1110. 6) At this point, the sum of the two binary numbers is present in the accumulator. In most computers the contents of the accumulator [A] will usually be transferred to the computer’s memory so that the adder circuit can be used for a new set of numbers. [Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

Lec-25, Pg-04