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bus_pci

bus_pci

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Published by Rati Ranjan

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Published by: Rati Ranjan on Mar 23, 2011
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03/23/2011

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Buses

• • • • There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)

What is a Bus?
• • • A communication pathway connecting two or more devices Usually broadcast Often grouped — A number of channels in one bus — e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown

Data Bus
• Carries data — Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance — 8, 16, 32, 64 bit

Address bus
• • • Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system — e.g. 8080 has 16 bit address bus giving 64k address space

Control Bus
• Control and timing information — Memory read/write signal

— Interrupt request — Clock signals Bus Interconnection Scheme Physical Realization of Bus Architecture Single Bus Problems If large number of devices are connected to the single shared bus . performance will suffer. There are following problems .

system bus and expansion bus 1. Input /output transfer to and from the main memory across the system bus do not interface with the processor activity because process accesses cache memory. Local bus connects the processor to cache memory and may support one or more local devices 2. other waits. The cache memory controller connects the cache to local bus and to the system bus.1>Bus length is longer. Figure shows some typical example of I/O devices that might be attached to expansion devices The traditional bus connection uses three buses local bus . 3. This propagation dealy can affect performance. Because data rate generated by attached deviceslike graphics and video controller are growing rapidly 3>Only one master bus can operate at a time. System bus also connects main memory module 4. . When control of the bus passes from one device to another frequently 2>The bus may become bottleneck as aggreagate data transfer demand approaches the capacity of bus. To overcome this problem most computer system use multiple buses. Therefore propagaton time is more. generally laid out in hierarchy.

block Bus Design Parameter in details 1. . E. W.An expansion bus interface buffers data transfer between system bus and i/o controller on the expansion bus. it is called dedicated bus. E. Arbitration : Centralized or distributed 3.5. Read. AD7 – AD0. Synchronous or Asynchronus 4. A more efficient solution is to make use of one or more expansion buses for this purpose. Modify Write. Bus Type : i) Dedicated bus: When a bus is permanently assigned only 1 functiion .g. It is possible to connect I/O controllers directly on to the system bus. R.g. Timing . ii) Multiplexed bus: When the bus is used for more than 1 funcion in different time zones it is called multiplexed bus.A0 in first clock cycles on pins. Bus width . Address or data 5. Type : Dedicated or multiplexed 2. Bus design parameter Before designing a bus there are some few parameters like 1. Data Transfer Type . separate address and data lines separate bus for memory and I/O modules Advantages: It gives high performance and less bus contention Disadvantages : Increased size and cost. after write. 8085 microprocessor outputs A7. This arrangement allows the system to support a wide variety of i/o devices and at the same time insulate memory to process or traffic from i/o traffic.

d) Read after write. Writer transfer is followed with read transfer after some access time . More addrss lines means more memory can be accessed e. Equal responsibility is given to all devices to carry out arbitration process. Read data transfer is followed by write data transfer at the same address. it is used for checking purpose. without using a central arbiter 3. Bus Timing: In synchronous timing . It is faster system. few pins lines are required .g 16 line address make 2 16 = 64 kb . . A selection mechanism called bus arbitration describes which device should be given access to the bus i) In Centralized approach. Now data is read from bus c) Read . 2) For non-multiplexed bus : Address and data outputted at the same time on different bus.g. e) Block operation. Bus width: It decides the number of lines to be used for address and data. It uses one of the following type (1) Daisy chaining (2) Polling (3) Multiple priority levels ii) In Distributed Approach: each master has arbiter compared to only single in centralized approach.Advantages . Bus Arbitration: Several bus master connected to a common bus may require access to the same bus at the same time. More data lines means more number of bits can be transferred at a time. It stop other cpu to use bus. Therefore speed increases. saving file in secondary storage.e very event is synchronized by clock whereas in asynchronous every event occurring depends on previous events of bus . modify write. number of data are transferred at the same address one after another e. less cost and save space Disadvantages: slow in speed 2. A hardware device called bus controller or bus arbiter allocates bus. 20 address line makes 220 = 1 mb memory access . A bus can support various type of data transfer 1) For multiplexed bus a) Write operation : data is outputted immediately outputting address b) Read operation: First address is outputted then sufficient acces s time is given gto address device to output data. Data transfer type. 4. 5.

It Allows for transfer of data amongst peripherals independently of the processor.PCI The Peripheral Component Interconnect is an interconnect bus developed by Intel in 1992 which runs at 33 MHz and supports plug-and-play .The PCI bus is a 32 bit wide bus capable of transferring at data rates up to 132 MBytes per second. 64-bit version is capable of transfer rates of up to 524 Mbytes/second. . It allows high speed connection between peripherals. It is found on many desktops. but not limited to them. and from the peripherals to the processor. A 66 MHz.

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