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© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 JanuarySlide
20071
Objectives
z At the end of this class you will:
– Understand the basic PICmicro peripherals
and their associated registers
– Have “HANDS ON” experience initializing
Mid-Range peripherals
– Be able to implement peripherals not
covered here
– Understand interrupts and polling
– Write your own application code from
“scratch”
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 2
To get the most from this Class
z Timer1
– Timer1 Lab
z Timer2
– Timer2 Lab
z Analog Comparator
z Analog to Digital Converters (ADC)
– ADC Lab
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 JanuarySlide
20076
Mid-Range PIC Block Diagram
STATUS REGISTER
Pages of PROGRAM COUNTER
Program
Memory
14-bits
WORKING AUSART
INSTRUCTION REGISTER REGISTER
MSSP
PERIPHERALS
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 7
Program Memory
Reset Vector 0000h
z Maximum 8K words
– (8K x 14 bits/word)/1 byte
= 14Kbytes of memory
Interrupt Vector 0004h
z Reset Vector at 0000h 0005h
Page 0
– Program Counter (PC) will 07FFh
go to this address on 0800h
reset Page 1 0FFFh
1000h
z Interrupt Vector at 0004h Page 2 17FFh
– Program Counter (PC) will
1800h
go to this address upon Page 3 1FFFh
any Interrupt
z 13-bit PC
– PCLÆ ALU result (8-bits) or PCH<12:8> PCL PC<12:0>
OPCODE(11-bits)
CALL, RETURN,
– PCHÆ Paging bits RETFIE, RETLW
128
Bytes General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
Bank0 Bank1
RP1 RP0
RP1
0 RP0
0 BANK0
0 1 BANK1
z Contains: 1 0 BANK2
– Arithmetic status of the 1 1 BANK3
ALU
– The RESET status Indirect Register Bank Select bit:
(used for indirect addressing)
– Bank select bits for data
memory 1 = Bank 2,3
0 = Bank 0,1
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 14
MPLAB® IDE
z MPLAB® IDE (Integrated Development
Environment)
z Integrates different Microchip and third
party tools
– Code Editor
– Cross Compilers
– Assemblers
– Simulators, In-Circuit Debuggers, Emulators
– Programmers
RS232
Connector
Analog Pot
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 19
Polling and Interrupts
z Often we would like the processor to
perform a task if a specific event occurs
z Two methods to check if this event has
occurred:
– Polling:
z Continuously check for event at various points in
the code
– Interrupts:
z “INTERRUPTS” the Main program and starts an
Interrupt Service Routine when an event occurs
;========================= Main
Main
int_vector code 004h program
program
execution
execution
Interrupt Service
Routine (ISR) retfie
instruction interrupt flag
retfie ;return from set
;interrupt
;=========================
end
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 22
Enabling Interrupts
TMR2IE
TMR2IF
GIE
ADIE
ADIF
Other peripherals
PEIE
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 24
INTCON Register
(Core Interrupts)
Enable Bits Description
GIE Global Interrupt Enable Must be set to use
any Interrupts
PEIE Peripheral Interrupt Enable
TMRIE Timer0 Interrupt Enable Must be set to use
INTE External Interrupt Enable any Peripheral
Interrupts
RBIE PORTB change Interrupt Enable
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 35
Interrupt
Return to Main
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 41
Mid-Range Family Peripherals
z I/O Ports
z Timers (0, 1, 2)
z Capture/Compare/PWM
z Comparators
z Analog-to-Digital
Converter
z AUSART
z I2C and SPI Serial
Interface
Data
Configures Data Direction
PORTB Tri-State Register (TRISB)
TRISB7
TRISB7TRISB6
TRISB6TRISB5
TRISB5TRISB4
TRISB4TRISB3
TRISB3TRISB2
TRISB2TRISB1
TRISB1TRISB0
TRISB0
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 50
Timers
z Timers are used for many functions:
– timing reference to generate an event
– count the number of events
– waveform generation etc...
synchronize
T0CKI
pin
scaled clock TMR0
TMR0
prescaler PS2 PS1 PS0 RATE
Watchdog Timer
WDT out
0 0 0 1:2
0 1 0 1:8
RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0
0 1 1 1:16
synchronize
T0CKI
pin
scaled clock TMR0
prescaler
Watchdog Timer INTCON register
TMR0IF
Fosc/4
T1CKI
TMR1H TMR1L
pin
Enable
Fosc/4
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 60
Timer1 Lab
Clear IF
Initialize Timer1 clock
Reload Timer1
source and pre-scaler:
Timer1 interrupts
every 100,000 Instruction cycles
Toggle LED 0
Restore Context
Retfie
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 62
Lab Specifics
z The code for the lab is in
C:\RTC\201_ASP\Lab2-TMR1
Postscaler
COMPARATOR 1:1 Æ 1:16
PR2
Fosc/4
0
1:1, 1:4,1 1:16 1 0 1:7
0 1 1 1 1:8
1 0 0 0 1:9
Postscaler
1
1
0
0
0
1
1
0
COMPARATOR
1:10
1:11 1:1 Æ 1:16
1 0 1 1 1:12
1 1 0
PR2 1:13
0
1 1 0 1 1:14
1 1 1 0 1:15
1 1 1 1 1:16
Postscaler
COMPARATOR 1:1 Æ 1:16
PR2
Load Period PIR1
Register 1 1 1 1 1 0 0 0
1
TMR2IF
Timer2 Control Register (T2CON)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Flag set on first
match with
postscaler = 1:1
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 71
Timer2 Lab
z The Goal of Lab 3 is to become familiar with
the following:
– Timer2 Clock Source
– Setting the Prescaler
– Setting the Postscaler
– Turning on Timer2
– Setting the Interrupt Enable bits needed for
Timer2 to successfully generate an interrupt.
Set up Timer2
Increment counter the Period,
number of times Prescaler,
Timer2 has interrupted Postscaler
NOP
Restore context
retfie
;*****************************************************************
;Enable Timer2 interrupts, Peripheral and Global Interrupts
;*****************************************************************
Question:
Does the user have to account for the free
running Timer2 in order to ensure a precise
interrupt period?
Answer:
No, Interrupt occurs on match not overflow
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 77
Capture/Compare/PWM
Module
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 78
Capture/Compare/PWM
(CCP) Overview
z Capture
– Times the duration of an external event using an
input pin
z Compare
– Changes an output pin or generates an interrupt
when a specific amount of time has passed
z Pulse Width Modulation (PWM)
– Creates a reconfigurable, steady duty-cycle, square
wave output at a defined frequency
– Provides enhanced features for various bridge
connectivity
BIT FUNCTION
CCP Mode Select Bits configure the module as Input Capture,
CCP1M<3:0>
Output Compare, or PWM
CCP1<X:Y> PWM duty cycle 2 LSB’s (8 MSB’s located in CCPR1L)
TMR1H TMR1L
Edge Detect
and Single Buffered
CCPxCON
TMR1H TMR1L
CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE
Edge Detect
0 1 0 and 0 Capture every falling edgeBuffered
Single
0 1 0 1 Capture every rising edge
0 1 1 0 Capture every 4th rising edge
System Clock (Fosc)
0 1 1 1 Capture every 16th rising edge
CCPRxH CCPRxL
CCPxCON
NO
COMPARATOR
COMPARATOR
Does
DoesTMR1H:TMR1L
TMR1H:TMR1L
==CCPRxH:CCPRxL
CCPRxH:CCPRxL
OUTPUT
OUTPUT
YES CCPx
?? LOGIC
LOGIC
??
CCPRxH CCPRxL
Special Event Trigger
CCP1CON
P1M1 P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
NO
COMPARATOR
CCPxM3 COMPARATOR
CCPxM2 CCPxM1 CCPxM0 MODE
Does
DoesTMR1H:TMR1L
TMR1H:TMR1L
1 ==CCPRxH:CCPRxL
0 0
CCPRxH:CCPRxL 0 Set output onOUTPUT
OUTPUT
match (CCPxIF is set)
YES CCPx
?? LOGIC
LOGIC
1 0 ?? 0 1 Clear output on match (CCPxIF is set)
Generate software interrupt on match
1 0 1 0
(CCPxIF is set CCP1 pin unaffected)
Trigger special event
1 0 1 1 (CCPxIF is set, CCP1 resets TMR1 or
CCPRxH CCPRxL TMR2 and starts an A/D conversion if
Special Event Trigger
enabled)
CCPR1L
DUTY CYCLE VALUE
CCP1<X:Y>
DOUBLE 10
BUFFER
CCPR1H LATCH
10
Period CCP1 Output Pin
TMR2 = CCPR1H
COMPARATOR Start
10 R
Latch
TMR2incrementing
TMR2 Reset to 0’s (1) 0
1
8 S CCP1
pin
COMPARATOR
TMR2 = PR2
;Clear Timer2 0 1 1 1 1 1 1 1
banksel TMR2
clrf TMR2 CCPR1L
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 92
PWM Lab Objectives
NOP
;*****************************************************************
; Put CCP1 module in PWM mode.
;*****************************************************************
;*****************************************************************
; Configure Timer2 pre and post scale of 1:1 and turn Timer2 on
;*****************************************************************
bsf T2CON,TMR2ON ; ### turn on TMR2
Answer:
PWM will run concurrently with the PICmicro
MCU without slowing the processor down
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 100
Output Compare Lab
z Goals of the lab are to gain experience with
the following:
– Setting up the CCP for Output Compare
– Configure the Special Event Flag to reset Timer1
– Configure the CCP to generate an Interrupt on
Timer1 overflow
– Using an Interrupt Vector to modify the interval
between Interrupts
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 101
Compare Lab Overview
z This lab configures the CCP into output compare
mode driven by Timer1
z An Interrupt is used to change the sound of the
buzzer
z During the Interrupt Service Routine (ISR):
– The RC2/CCP1 pin (connected to buzzer) is toggled
– The ISR period is reduced:
z The Compare Register (CCPR1L) is decremented
z The Timer1 count registers are reset
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 102
Compare Lab Overview
Interrupt Vector Main Program
Save Context Configure CCP as
Output Compare
Clear IF
Initialize Timer1
Toggle CCP
Output Pin
Drives Initialize PORT C
Buzzer Decrement
CCPR1L
Turn on timer1
Reset
Timer1 NOP
RETFIE
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 103
Compare Lab Specifics
z The code for this lab is in
C:\RTC\201_ASP\Lab5-CCP
z Complete the following sections:
– Configure the CCP as an Output Compare
that sets the Special Event Flag and CCP1IF
– Configure Timer1 with a clock source of
Fosc/4 and a pre-scaler of 1:8
– Configure Special Function Registers to
allow the CCP interrupt to occur
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 104
What you need to know
z The registers needed to complete this lab are:
– INTCON (Interrupt Control)
– T1CON (Timer1 Control)
– CCP1CON (CCP1 Control)
– PIE1 (Peripheral Interrupt Enable)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 105
Compare Lab Solution
;
; Set CCP1CON to Output Compare mode with Special Event Trigger
; to clear the Timer 1 register pair on a match
;****************************************************************
movlw 0x0B ; ### value for CCP1CON
movwf CCP1CON ; move to CCP1CON
;
; Configure Timer 1 for Fosc/4 operation. 8:1 Prescaler
;
;****************************************************************
movlw 0x30 ; ### value for TMR1
movwf T1CON ; ### move to TMR1 control register
;
; Enable Timer 1 interrupts, Peripheral Interrupts and
; Global Interrupts
;****************************************************************
bsf PIE1,CCP1IE ; ### enable CCP1 interrupt
bsf INTCON,PEIE ; ### enable peripheral interrupts
bsf INTCON,GIE ; ### enable global interrupts
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 106
Lab Question
Question:
The PWM did not require an interrupt in order
to work. Do we need an interrupt to operate in
output compare mode?
Answer:
Not necessarily
– Peripherals always set their associated interrupt
flag, so you have the choice of polling or
directly responding to the interrupt.
– The choice is based on the need of your
application.
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 107
Comparators
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 108
Comparator Overview
z Comparator Module:
– Compares analog input voltage to a reference
and outputs a digital result
Vref
Vin
Analog Input
(Vin) Output
+ (Vout)
Comp
Reference Voltage
(Vref) -
Vout
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 109
Comparator Reference Voltage
z Voltage Reference can be either:
– External from a device pin
– Internally generated with the Voltage Reference
Module
z Provides 16 selectable voltages from 0 to 75% of VDD
– Some devices can also scale VREF+ and VREF-
z Some devices also have a fixed reference (0.6V)
– Independent of VDD
VREF+
VRSS = 1
8R R R R R VRR
VRSS = 0
V 15 8R
CVREFDD
To Comparators VREF-
and ADC Module 0 VRSS = 1
CVREF 4 VR<3:0>
VRSS = 0
VROE VREN
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 110
Comparator Interrupts
z An Interrupt occurs when the comparator
output changes
– Some devices share one flag for both
comparators
– Some devices have independent flags
z Must read the comparator output before
clearing interrupt flags
– Outputs found in the comparator control
register (CMCON or CMxCON0)
– Resets the output mismatch condition
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 111
Comparators and Sleep Mode
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 112
Analog-to-Digital
Converter (ADC)
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 113
ADC Overview
z Analog-to-Digital Converter Module
– Converts analog input signal into an 8 or 10-bit
binary value
– Selectable internal or external reference voltage
– Interrupt can be generated after conversion is
completed
z The interrupt can wake the PICmicro from SLEEP
ADC
Analog Digital
Input Output
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 114
ADC Control Registers
z The ADC implements two control registers
– ADCON0 and ADCON1
– Devices with > 8 analog inputs do not have same bits
shown below
BIT FUNCTION
ADCS<1:0> A/D Conversion Clock Select bits
Use with ADCS2 in ADCON1
CHSx bits Analog Channel Select bits
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 115
ADC Control Registers
z The ADC implements two control registers
– ADCON0 and ADCON1
– Devices with > 8 analog inputs do not have same bits
shown below
BIT FUNCTION
ADFM ADC Result Registers Format bit
1 = Right Justified, 0 = Left Justified
ADCS2 A/D Conversion Clock Select bit
Use with ADCS<1:0> in ADCON0
PCFG<3:0> Port Configuration Bits
Configures I/O as analog or digital
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 116
ADC Result Registers
z 10 bit ADC result in is placed in two registers
– ADRESH and ADRESL
– Left or Right Justified
z Determined by Format Select bit (ADFM) in ADCON1 register
ADRESH ADRESL
MSB LSB
AN0 VREF+
AN1 pin
AN2 Start Conversion
AN3 Conversion Complete
AN4 ADC
AN5
AN6 00000011 11111111
AN7 Holding ADRESH ADRESL
Capacitor Left Justified Right Justified
VREF-
pin
ADCON0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON
Vss
ADCON1
ADFM ADCS2 PCFG3 PCFG2 PCFG1 PCFG0
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 118
ADC Module Diagram
PCFG AN7
<3:0> AN6 AN5 AN4 AN3 AN2 AN1
VddAN0
Conversion
Port Config Bits Fosc clock scaler
AN0 VREF+
AN1 pin
AN2 Start Conversion
AN3 Conversion Complete
AN4 ADC
AN5
AN6 00000011 11111111
AN7 Holding ADRESH ADRESL
Capacitor Left Justified Right Justified
VREF-
pin
ADCON0
ADCS1 ADCS0 CHS2
0 0
CHS1 CHS0
0 0
1
GO/DONE ADON
Vss
ADCON1
0
ADFM
1 ADCS2 PCFG3 PCFG2 PCFG1 PCFG0
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 119
Timing Considerations for ADC
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 120
Analog-to-Digital
Conversion LAB
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 121
ADC Lab
z This Lab will familiarize you with:
– Setting up the ADC module
– Operating a peripheral from the “Main”
program, not an interrupt vector
– Using the value read from one peripheral
(ADC) to drive another peripheral (CCP in
PWM mode)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 122
ADC Lab Overview
Main Program
Configure Timer 2
Configure PORT C
Configure and
Turn on ADC
Enable interrupts
Continued on
next page
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 123
ADC Lab Overview (cont.)
Continued from
Previous Page
Main Loop NO
TMR2IF=1
YES
Start ADC
NO
ADC done?
YES
Put ADC value in
CCPR1L
Output 4 LSBs of
ADC value to LEDs
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 124
ADC Lab Specifics
z Complete the following sections of code
in the project C:\RTC\201_ASP\Lab6-ADC
– Configure the ADC to return a left justified
value
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 126
ADC Solution
;*************************************************************************
; Configure ADC: Channel 0, left justified, Tad = 8 * Tosc, turn on ADC
;*************************************************************************
clrf ADCON0 ; ### ensure default channel is set to channel 0
bsf ADCON0,ADCS1 ; ### set Tad = Fosc/4
bsf ADCON0,ADON ; ### turn on ADC
bsf STATUS,RP0 ; ### point to BANK1
movlw 0x0E ; ### left justify, configure AN0 analog
movwf ADCON1
;
; Enable Timer 2 interrupts, Peripheral Interrupts and Global Interrupts
;
bsf PIE1,TMR2IE
bsf INTCON,GIE
bsf INTCON,PEIE
bcf STATUS,RP0 ; return to BANK0
;
;*************************************************************************
; add three lines of code to start the ADC conversion and wait for the
; conversion to complete
;*************************************************************************
bsf ADCON0,GO ; ### start ADC conversion
btfsc ADCON0,GO ; ### Is the conversion done?
goto $-1 ; ### no: loop until done
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 127
ADC Lab Question
Question:
Instead of waiting for TMR2IF to be set in
the main program, could we start the ADC
from within an interrupt routine?
Answer:
YES
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 128
ADDRESSABLE Universal
Synchronous Asynchronous
Receiver Transmitter
(AUSART)
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 129
AUSART Overview
z Serial I/O communications peripheral
– Sometimes called Serial Communications
Interface (SCI)
z Main Functions:
– Can be synchronous or asynchronous
– Can receive and transmit
z Full-duplex asynchronous transmit and receive
z Half-duplex synchronous master and slave
z Most common use
– RS-232 communications to a PC serial port
z Needs driver for RS-232 level shifter
z Enhanced (EUSART) features allow interface
with a Local Interconnect Network (LIN) bus
system
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 130
AUSART Registers
z Baud rate generator registers
– SPBRG (8 bit for AUSART)
– SPBRG and SPBRGH (16 bit for EUSART)
z Transmit status and control
– TXSTA
z Receive status and control
– RCSTA
z Transmit data register
– TXREG
z Receive data register
– RCREG
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 131
TXSTA Register
CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D
Bit Function
CSRC Clock Source Select
1 = Master Mode (clock generated internally from BRG)
0 = Slave Mode (clock from external source)
TX9 Ninth bit transmission enable
TXEN Transmit Enable bit, 1 = Tx enabled, 0 = Tx disabled
SYNC AUSART Mode , 1 = Synchronous Mode, 0 = Asynchronous Mode
SENB For EUSART only
1 = Send sync break character bit
0 = Sync break transmission is completed
BRGH Baud Rate Select, 1 = High Speed, 0 = Low Speed
TRMT Transmit Shift Register (TSR) status
1 = TSR empty, 0 = TSR is full
TX9D Ninth bit of transmit data
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 132
RCSTA Register
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
Bit Function
SPEN Serial Port Enable
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 134
Receive Block Diagram
Enable Serial Port
SPEN
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 135
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 136
MSSP Overview
z The MSSP module can operate in one of two modes:
– SPI (Serial Peripheral Interface)
z 3 pins are used
– Serial Data Out (SDO)
– Serial Data In (SDI)
– Serial Clock (SCK)
– I2C (Inter-Integrated Circuit)
z Full Master mode
z Slave mode (with general address call)
z 2 pins are used
– Serial Clock (SCL)
– Serial Data (SDA)
– RESTART (R)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 138
External IC EEPROM Read +5V
SCL
MASTER
SDA
READ
WRITE
GOTO
STOP
MODE
DATA
ADDRESS
BUSY BUSY
PIC
LISTEN LISTEN LISTEN
EEPROM
EEPROM
SLAVE
START
RESTART
STOP
ACK
NACK
MEMORY SLAVES DATA
ACK
ADDRESS
ADDRESS
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 139
MSSP Control Registers
2 (I C mode)
BIT FUNCTION
SMP Slew Rate Control bit
CKE Not used in I2C mode
D/A Last byte Rx/Tx was data or address
P Stop Condition Detected
S Start Condition Detected
R/W Slave :READ/WRITE or Master = transmit in progress
UA Address needs to be updated
BF The SSPBUF register is full
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 140
MSSP Control Registers
2 (I C mode)
BIT FUNCTION
SMP Slew Rate Control bit
CKE Not used in I2C mode
D/A Last byte Rx/Tx was data or address
P Stop Condition Detected
S Start Condition Detected
R/W Slave :READ/WRITE or Master = transmit in progress
UA Address needs to be updated
BF The SSPBUF register is full
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 141
MSSP Control Registers
2 (I C mode)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 142
MSSP Control Registers
SSPM3 SSPM2 2 SSPM1 SSPM0 (I C mode)
Mode
0 0 0 0 SPI Master mode, clock = FOSC/4
0 0 0 1 SPI Master mode, clock = FOSC/16
0
2 of 3:
0
MSSP
1
Control
0
Register 1 (SSPCON)
SPI Master mode, clock = FOSC/64
0 0 WCOL1 SSPOV
1 SSPEN CKP mode,
SPI Master SSPM3
clockSSPM2 SSPM1 SSPM0
= TMR2 output/2
0 1 0 0
CONTROL BITSSPI Slave mode, DETECTION
clock = SCK pin, SS pin control enabled
BITS (FLAGS)
0 1 0 1 SPI Slave mode, clock = SCK pin, SS pin control disabled,
BIT FUNCTION
SS can be used as I/O pin
0 WCOL
1 1 0 Write
I2C Slave mode,Collision Detected
7-bit address
0 1 1
SSPOV A 1write to I2C
theSlave mode, 10-bit address
SSPBUF before previous value processed
1 0 0 0 I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
SSPEN Enables MSSP module
1 0 0 1 Reserved
1 CKP
0 1 0 Reserved Enables clock
1 SSPM3
0 1 1 Mode Select
I2C firmware controlled MasterBit
mode (Slave idle)
1 1 0 0 Reserved
SSPM2
1
1
1
SSPM1
1
0
1
1
0
Mode Select bits
Reserved
I2C Slave mode, 7-bit address with Start and Stop bit
SSPM0 interrupts enabled
1 1 1 1 I2C Slave mode, 10-bit address with Start and Stop bit
interrupts enabled
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 143
MSSP Control Registers
2 (I C mode)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 144
MSSP Control Registers
2 (I C mode)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 145
Tx/Rx Buffer (SSPBUF)
z Buffer register containing Tx and Rx data
– SSPBUF interfaces to a shift register (SSPSR) for
shifting data in or out
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 146
I2C Address Register
(SSPADD)
z Slave mode:
– Contains the slave address of the PIC
– Compared against the received value
z Master mode:
– Used to calculate the clock speed
(BAUD rate) of the I2C system.
Fosc
BAUD RATE =
4 × ( SPADD + 1)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 148
I2C Based Temp Sensor
Lab
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 149
I2C Based Temp Sensor
Lab Objective
z Configure some MSSP control registers to
enable I2C communication to the I2C based
Temp sensor on the PICDEM 2 Plus board.
z Temperature reading (lowest 4 bits) will be
displayed on the LEDs.
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 150
I2C Lab Overview
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 151
I2C Lab Overview
Main Code
Configure I/0s
Configure MSSP
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 152
I2C Lab Specifics
z Code for the lab is in
C:\RTC\201_ASP\Lab7-I2C
z Complete the following sections:
– Disable the slew rate control
z We’ll be using I2C standard rate (100KHz)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 154
I2C Lab Solution
;--------------------------------------------------------------
; set the slew rate and baud rate for 100 MHZ operation
;--------------------------------------------------------------
; Configure as I2C master with Fosc/4 Clock source
BANKSEL SSPCON
bsf SSPCON,SSPM3 ; ### set to I2C master mode with
; Fosc/4 clock source
bsf SSPCON,SSPEN ; ### Enable SDA and SCL pins to
; operate in I2C mode
;--------------------------------------------------------------
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 155
Multiple Interrupt
Lab
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 156
Multiple Interrupts Lab
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 157
Lab Overview
Main Program
Set up CCP as Output
Compare just as in Lab 6
NOP
Continued on next slide
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 158
Lab Overview
Interrupt Service Routines
INT_ISR CCP_ISR
Call “debounce” Clear IF
Delay routine
Put -1 in WREG
Toggle variable
Called
“push_flag” push_flag
Set ?
Add WREG to
Return to Main CCPR1L
Return to Main
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 159
Lab Overview (cont.)
Save
context
Interrupt Handler
NO
Go to CCP YES
service routine Service External
Interrupt
Return to Main
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 160
Lab Specifics
z Lab is found in:
– C:\RTC\201_ASP\Lab8-MXINT
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 162
Lab Solution
Int_Service_Routine
call save_regs; ; save W, STATUS, & PCLATH
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 163
Lab Solution ( cont.)
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 164
Lab Questions
Question:
Why is there a noticeable silence when S3 is
pushed?
Answer:
Since “debounce” is called during an interrupt
and the GIE bit is cleared, the CCP1 interrupt
that toggles the buzzer is not allowed to
operate. Therefore, the buzzer goes quiet.
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 165
Lab Questions (cont.)
Question:
How can this silence be eliminated and the
buzzer continue to run?
Answer:
1. Capture S3 in “Main” and call “debounce”
while GIE is set
2. Use a timer to accomplish the delay
3. Re-enable interrupts during the INT ISR
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 166
201ASP Wrap-Up
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 167
Peripherals Class Wrap-up
z Today we covered the following
peripherals on the Mid-Range family
– I/O ports
– Interrupt structure and processing
– Timers (timer0, timer1, timer2)
– CCP Module ( Output Compare, Input Capture,
PWM)
– Comparators and Analog-to-Digital Converters
z Voltage Reference
– AUSART – Serial Port
– I2C using the MSSP module
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 168
Final Word
z This discussion has followed the standard
Microchip datasheet flow:
Overview of Peripheral Use these sections to:
• Develop logical flow charts or
pseudo-code (Avoid Spaghetti
Register Description Programming!!)
and Configuration
Other Tips:
• Comment your code thoroughly
Enhanced or • Choose descriptive names
Special Features for user defined registers
© 2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 170
Thank You!!
© 2006 Microchip Technology Incorporated. All Rights Reserved. 201ASP v8.0 January 2007
Slide 171