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Krishna Ram Budhathoki
Department of ECE, UA

??Ê  ? ? ? 
 ? ? ? 
? ? ? average Using Parametric Sweep in the PSPàCE, the values of


? ? ?  ? ? ? ?   ? L and C could be found for the 10 percent ripple in the output
? ?   ? ? ? 
? ? ?   ? ? voltage of the rectifier he values of L and C could also be

 ????? found out using the Fourier series expansion of the average
 ??? ? ???

?? ??  ?
output voltage of the full wave rectifiers [4] he design of
 ??? ??? ??  ??
????? ? ?? control circuit could be done like Pulse Width Modulation
?  ???
?? (PWM) àn this paper, the different approach of control circuit
   ? !? ? ? ? ? ?  ? ? ?  
? design is shown using 555 timer and OPAMPS
?  ?? ?? ??? ?

? ? 

 ?  ?   ? ? "#$?  ? àV COVEER OPERAàO AD DESà
? ? &&&? ?  ? ? ?  ? 
 ? ?  ? ??
?   ???? ??
? ?
 ? he basic full wave rectifier circuit to be implemented is
shown in Fig 1
à   ? ?  ?  ?  ? 
? ?  ?' ?(?


he semi-controlled rectifier¶s circuit is different to that of

full controlled rectifier circuit in the sense that it contains both
the diodes and thyristors as the uncontrolled and controlled
elements Due to the presence of diodes in the semi-controlled
rectifiers, freewheeling operation takes place restricting the
rectifier operation to only one quadrant [3]
Fig 1: Basic Circuit Diagram for the full wave rectifier?
he rectifier circuit consists of two diodes in the upper half
he primary purpose of the rectifier circuit is to produce and two thyristors in the lower half he circuit is operated by
dc power from the ac supply herefore, it finds users in the 120V(rms), 60Hz supply he firing of thyristors 1 and
almost all the electronic equipments Using the Semi- 1 are controlled by the control circuit he load is of 10Ÿ
controlled rectifiers, the variable dc output is produced from resistor and the output at the load is filtered by the second
the constant ac source [1] he output voltage is varied by order LC filter so as to limit the output peak-peak ripple in Vo
controlling the delay (or firing angle) of the thyristor A ( voltage across resistor) to approximately 10% of
phase-controlled thyristor is turned on by applying a short <V0>(average value of Vo)
pulse to its gate and turned off due to natural or line
commutation; and in case of highly inductive load, it is turned i Positive half cycle (´  
off by firing another thyristor of the rectifier during its
negative half cycle [2] àt is also used for detecting the Diode D2 and thyristor 1 are forward biased while D1 and
amplitude-modulated wave Controlled rectifiers are used in 2 are reversed biased So when 1 is fired at an angle Į,
the generation of polarized voltage for welding negative voltage waveform would be found at load R

ii  During negative half cycle(U 

Diode D1 and thyristor 2 would be forward biased and 1
and D2 would be reversed biased Since 2 would not conduct
Different techniques can be used to find the L and C values for
before Į, the current at the inductor is freewheeled by D2 and
the rectifier to limit the output voltage ripple to 10 % of its
1 So when 2 is fired at an angle Į, current starts building
through already forward biased D1 and 2 Output at the Second order filter was designed with L and C in the hope to
resistor would be negative for this cycle also he inductor in reduce the size of L in order to limit the output voltage ripple
the output would filter ripples in the output current while the to 10% of the average
capacitor would filter ripples in the output voltage

A  Design of ànductive Filter Since the average voltage across the inductor in the steady
state is zero, the average output voltage for continuous
Design of inductive filter was made for Į=0, C=0 and R=10Ÿ inductor current from eqn (1 2) is,
he value of series inductance is to be calculated for the peak 2r
to peak ripple to be 10% of the average output voltage (v0) ï ö
For the full wave rectifier, sinusoidal voltage across the load Average inductor current must equal the average resistor
can be expressed as a Fourier series consisting of a dc term current because the average capacitor current is zero
and the even harmonics [6]
ï 2r
 ö  ö ö (1 4)
ï ± ï  
cos(  ï   ) (1 1) Considering the second harmonics,
2r  1 1 
where, 2     72 052ï
2 r
1 3
ï  (1 2) Assuming the capacitor is short circuited to ac terms, the
harmonics voltage V2 exists across the inductor
2r  1 1 
    (1 3) àf V02 be the output voltage at load R for the second harmonic,

1 1 then using voltage division rule,
For the given supply voltage, average output voltageV0 is
given by
02  72 052
(1 5)
2 r

2 2 120
 108 037 ï
   2  2

Average current ,  ï   10 80 r
 Since average voltage across the inductor is zero, the average
For n=2 and 4 , from eqn (1 3) voltage across the resistor is,
2 r  1 1  2r
2     72 025ï ï ö ö 108 03ï

1 3 |
For the peak to peak ripple at the load to be 10% of its average
2  1 1 
4  r    14 405ï value,

3 5 10
For output voltage ripple to be within 10% of Vo D  ö  ï ö 10 80ï and

 ´    ´

´  D
 D ï   1 08r
he current amplitude at each frequency is calculated by 
2 And the current in resistor due to the second harmonic voltage
 ö ö ö (1 4) is,
±10 2  377 
22 144 05
 ï  2  2      1 08  02 
(1 6)
10  2 377 10  2 377 
which gives L=0 176H But,
B  Design of second order filter V ï ö 2  02 ö ö 1 08r

Putting R=10Ÿ ,
02 ö 5 4ï 2  ero crossing detection
he zero crossing detectors consists of two parts he first is
Putting the value of  in equation (1), and choosing step down transformer and the second is the comparator
ö 110r arbitrarily and solving for C , we get
ransformer is used for down converting the 170 Peak-Peak
› 150 ac voltage to about 17 peak-peak voltage he conversion is
chosen in by selecting the values of L1 and L2 according to
V COROL CàRCUà DESà equation (2 1)[5]

he design of the control circuit is the most important part of „1  1

  (2 1)
the project he control circuit should be such that it is
possible to send the control signal for firing the thyristor at the „2

specified firing angle (Į) We can design the control circuit

from different ways he goal of all the circuit should be to Where L1,1 and L2,2 are the inductance and turns of the
produce the periodic pulse at the specified angle taking input primary and secondary respectively
signal as the reference For the transformer with V1 as input and V2 as output,
he control circuit that is used here uses the 555 timer to
calculate the delay angle (Į) for firing the thyristor 555 timer
would produce a pulse at certain delay at each zero crossing of 1 1
the input signal  (2 2)
2 2
A  Block Diagram of Control circuit
So, transformer is designed with L1=240H and L2=20H to
he general block diagram of control circuit is shown if Fig 2 keep the output voltage to nearly 17 peak to peak

For the zero crossing detection, two separate circuits are

designed for the positive edge and negative edge zero crossing
of the input voltage waveform

i Positive edge zero crossing detection

he positive edge zero crossing detection of the input voltage

waveform is shown in m 

Fig 2: Block diagram of the control circuit
Fig 3: Circuit diagrams for the positive edge zero crossing detection of the
input voltage waveform

1  Reference Signal
he transformer input voltage is the supply voltage which is
he reference signal is the same input supply voltage of 120V 170 volt peak to peak at 60 Hz he transformer inductances
(rms), 60Hz
L1 and L2 are chosen as 260 and 2 henry respectively in half cycle of the input wave he negative edge zero crossing
order to get 17 volt peak to peak at the secondary circuit is shown in fig(8) and the corresponding waveform is
For the simulation of transformer, XFRM_LàEAR of the shown in fig(10)
Analog Library, in pspice is used he coupling factor K is
chosen to be 1 Since the secondary circuit needs a DC
connection to ground, it is done by adding a large resistor of
he ua741OPAMP is used as a comparator he output
voltage of the transformer is directly fed to the Opamp ua741
which is biased to +5volt at +Vcc and and 0Volt to ±Vcc,
produces the output pulses as shown in Fig 4

Fig 6: egative edge zero crossing detection of the input voltage waveform

3 Phase Control Circuit

here are two separate phase control circuits for the two
Fig 4: Positive edge, zero crossing detection of the input voltage waveform thyristors àt consists of 555 timers and MOSFE as a
(out1) switch he MOFE used is the àRF540 he 555 timer is
As shown in Fig 4, the pulse generated by the opamp starts at operated in monostable mode àn the monostable mode of the
the positive edge zero crossing point of the input voltage 555 timer, the output pulse of duration equivalent to 1 1RC
wave hese pulses are later used for the firing of first second is produced at the output pin 2 when a negative edge
hyrisotr(1), which becomes forward biased during the transition occurs at the trigger pin 2
positive half cycle of the input voltage wave
i Operation of phase control circuit
ii  egative edge zero crossing detection of the
input voltage waveform àn the monostable mode of operation, pins 6(threshold) and
7(discharge) are shorted and connected to the Vcc(+12V) via a
For the zero crossing detection of the input voltage wave resistor(R) and connected to the ground via a capacitor(C2) as
while going from negative value to positive value (i e for the shown in Fig 7 hese values of R and C determines the period
negative edge zero crossing detection), the signal from the of the output pulse given by 1 1RC sec Pin 5(control) is
transformer is inverted using the an opamp as an inverter grounded via a capacitor(C1) Pin 4(reset output) is connected
whose gain is adjusted to 1 by keeping the values of R1 and to the Vcc Pin2(trigger) input to the 555 timer is connected to
Rf equal his inverted signal is sent to the another opamp as a the source terminal of the MOSFE(M2) which his connected
comparator as shown in Fig 5 to generate the pulse at the to the source via a resistor
negative zero crossing edge
he MOSFE(àRF(540) is used as a switch which is driven by
the pulse generated at the zero crossing of the input voltage
waveform When there is no input pulse at the gate terminal of
the MOSFE, MOSFE behaves as an open circuit thus a
trigger input of the 555 timer remains at the high voltage level
As soon as the gate of the MOSFE receives the input pulse
from the zero crossing detection circuit, it behaves as a short
circuit thus shorting trigger pin of 555 timer his result in the
transition from a high voltage to low( 0 volt) in the trigger
Fig 5: Circuit for the negative zero-crossing detection of the input voltage input of timer, which triggers the timer he output voltage at
wave pin3 of timer remains high for the time interval of 1 1RC
second Fig 7shows the output pulse of the 555 timer used for
his method could detect the zero crossing of the negative firing the Q1 thyristor he O time is 3 3mS as estimated by
edge of input wave(pulse generated starts from the negative 1 1*R*C ( R=500Ÿ and C=6µF) Similarly Fig 8 shows the
zero crossing), but it could not detect the positive edge phase control circuit diagram for firing thyristor Q2 Fig 10
crossing of input wave( which is already determined ) shows the output voltage waveform of 555 timer which has
egative edge detection is used for firing the second the O time of 3 3ms as calculated by 1 1RC
thyristor(2) since it gets forward biased only in the negative
Fig 10: Output of the 555 timer for firing the Q2 thyristor

Since duration of output pulse of the 555 timer depends on the

R and C values of the 555 timer, one can vary them to get the
firing pulse at the desired angle

4  ate Drive Circuit

he gate drive circuit uses pulse transformers for the isolation
Fig 7: Phase control circuit for the firing hyristor (Q1) of control signal from input voltage signal àt is shown in Fig
11 he gate drive circuit is designed for the thryristor 23899
which requires 4 to 5 2mA triggering current at its gate for
firing he MOSFES at the first stage of the gate drive
circuit (M11 and M14) invert the pulse obtained from the
respective 555 timer hese inverted pulses are used as
controls for the second stage MOSFES(M8 and M12) he
corresponding second stage voltage waveforms at terminal n1
and n2 of MOSFES (M8 and M12) are shown in Fig 12 and
Fig 13 respectively When input to the second stage MOSFE
is low( corresponding to the high voltage at 555 timer output),
the primary side of the transformer would not be grounded and
thus no current flows at the primary loop ow when input to
Fig 8: Output of the 1st 555 timer for firing the thyristor Q1 the second stage MOSFE is high( corresponding to the high
voltage at 555 timer output), the MOSFE behaves as a short
circuit connecting the primary of the transformer to the +12V
supply he diode across the primary is needed to circulate the
magnetizing current of the transformer[7] By this method, the
primary is connected to the +12V supply during period when
the value of output pulse of 555 timer goes low àn the
secondary side of the transformer, one end is connected to the
gate of the thryster via a diode and a resistor while the other
side is connected to the common ground of the bridge
rectifier As soon as the primary of the pulse transformer gets
connected to the +12V supply, an impulse of short duration at
the secondary terminal would be produced as shown in Fig
14and Fig 15 he diode in the secondary would allow the
unidirectional flow of impulse current to the gate he resistor
values are chosen such that the impulse current would be
sufficient to fire the thyristors as shown in Fig 16and Fig 17
Fig 9: Control circuit for firing thyristor (Q2)
Fig 11: Semi controlled full wave rectifier along with the control circuitry

Fig 12: voltage pulse found at n1 Fig 14: Voltage pulse found at m1

Fig 13: Voltage pulse found at n2 Fig 15: Voltage pulse found at m2
›  ‘ ö 0u       

waveform Vs(source voltage)Fig 19, Vd(Diodes voltage)Fig
20, inductor current (à0)Fig 21, source current (às)Fig 22 and
output voltage (V0)Fig 23 are as shown

Fig 16: Current pulse found at g1

Fig 19: Source voltage Vs

Fig 17: current pulse found at g2

Và SàMULAàO RESUL Fig 20: Voltage( Vd)

he full wave rectifier circuit of Fig 11 is simulated using

›  ‘ ö 71 26 ›  

For R and C values of 555 timers as 500Ÿ and 6µF, pulse
delay from 555 timer becomes,
c  1 1  › (3 1)
c  1 1 500 6   3 3 r
Fig 21: ànductor current (à0)
For 60Hz source frequency, =16 67ms
‘ 3 3r  71 26 
16 67 r
Corresponding output waveform at 10Ÿ load of full bridge
rectifier for ‘ ö 71 26 , C=0 and L=0 is shown in Fig 18

Fig 22: Source current às

Fig 18: Output voltage waveform

 Fig 23: Output voltage(Vo)

Calculation of power factor(pf) and HD

 ö ö (3 2)
 ,r   ,r
From the plot of output current (Fig 25) ,
 r ö 102 22 r
r ö ö 120 2 and
 ö ö 1 045

From eqn (3 2),
Fig 25: Source current (à s)
1 045 2
   0 845
120 20 10 28
 r  1,2r
c  (3 3)
But the fundamental source rms current calculated from FF
of current(às) from PSPàCE, Fig 22 is
1, r  0 4895 
Fig 26: ànductor current (à0)
Putting the values in eqn(3 3) , we get
|  ö 0 4895
Output voltage ripple calculated from the simulation, Fig 23
Dï  100 (3 4)

109 54  99 03
Dï  100  10 16
103 8
Fig 27: Capacitor voltage ( v0)

›  ‘ ö 0  ï ï   r  
› Gm Power factor and HD calculation for case ààà

From eqn (3 2),

For ‘ ö 0 and second order filter (L=110mH and C=150GF),
source voltage (vs), diode voltage (vd)Fig 24, source current

 ö ö
(às)Fig 25, inductor current(ào)Fig 26 and capacitor  , r   ,r
voltage(vo)Fig 27 are as shown
From Fig(27),
ï , r ö 103 44 ï
ö ö 1 07 

r ö  ö 120 2
From Fig 25,
  ,r ö 10 288 r
1 07 2
So    0 865
120 2 10 288
Fig 24: Source voltage (Vs) and diode voltage (vd)
›  ‘ ö 30       

r ö ö 120 2

From Fig(28) and Fig(29),
 r ö 2 37

 ïr ö 2 38
ö  ïr   ö 56 56

1r ö ö 2 26

 56 56
 ö ö ö ö 0 198
 , r   ,r 120 2  2 37 Fig 30: waveform for (Vs) and load voltage(Vo)

From eqn(3 3),

 r i 1,2r
| ö ö 0 31

Fig 31: waveform of inductor current(à0)

Fig(30) shows the output voltage waveform and Fig(31)

shows the waveform form the inductor current

›  ‘ ö 30   ï ï   r  
Fig 28: Source current(às) › m 

he waveforms of source current (às) Fig(32), FF of source

current (Fig(33), voltage across capacitor(Fig(34) and
capacitor current(Fig(35) are as shown

Power factor and HD calculation:

From Fig(33), Fig(34) and Fig(35)
1r   3 18 

 r ö 3 74
ïr ö 32 82ï

 107 71 
Fig 29:FF of source current(às) 

From eqn(3 2)
107 71
   0 23
3 74
From eqn(3 3),

 r i 1,2r
| ö ö 0 619

Fig(35) shows that average current across capacitor is 0

Fig 34: Waveform for the voltage across capacitor

Fig 32: waveform of source current ( às)

Fig 35: waveform for the capacitor current


he semi-controlled rectifier circuit uses both the diodes and

thyristors by which we can get one quadrant output àn this
way, a variable dc output voltage could be obtained from the
constant ac source by varying the firing angle he simulation
was done is cadence 16 3 and the result came as expected he
first and second order filters were designed to limit the output
voltage ripple to 10% of its average For the firning of
thyristor, control circuit was designed using 555 timer in
monostble mode he output waveforms were generated for
different values of firing angle and the corresponding power
Fig 33: FF of source current(à s)
factor and HD were calculated and average inductor voltage
and average capacitor current were found zero he designed
circuit now could be implemented in hardware 

[1] http://www scribd com/doc/18667041/Controlled-Rectifiers-Sharifah-

[2] Power Electronics,Circuits ,devices and application,second
edition,Muhammad H Rashid pg 323,345
[3] http://www services eng uts edu au/~venkat/pe_html/ch06s1/ch06s1p1 h
[4] Power Electronics, Daniel W Hart, McRAW HàLLpg, 135,136
[5] http://www seas upenn edu/~jan/spice/PSpicePrimer pdf
[6] Power Electronics, Daniel W Hart pg 120
[7] http:// www engr siu edu/staff1/hatz/EE483/LABS/Exp3 html