LIST OF CONTENT

S.NO. 1. 2. 3. CONTENT INTRODUCTION SYLLABUS MANUALS OF ALL EXPERIMENTS PAGE NO.

INTRODUCTION

Here are some guidelines to help you perform the experiments and to submit the reports: 1. Read all instructions carefully and carry them all out. 2. Ask a demonstrator if you are unsure of anything.
3.

Record actual results (comment on them if they are unexpected!)

4. Write up full and suitable conclusions for each experiment. 5. If you have any doubt about the safety of any procedure, contact the demonstrator before hand. 6. THINK about what you are doing!

THE BREADBOARD

The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a node. That is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily for power supply connections, but are also used for any node requiring a large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts is a node. You will build your circuits on the terminal strips by inserting the leads of circuit components into the contact receptacles and making connections with 22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power supply connections to separate bus strips.

The 5V supply MUST NOT BE EXCELLED since this will damage the IC’s (Integrated Circuits) used during the experiments. Incorrect connection of power to

the ICs could result in them exploding or becoming very hot – with the possible serious injury occuring to the people working on the experiment! Ensure that the power supply polarity and all components and connections are correct before switching on power.

Building the Circuit
Throughout these experiments we will use TTL chips to build circuits. The steps for wiring a circuit should be completed in the order described below: 1. Turn the power (Trainer Kit) off before you build anything! 2. Make sure the power is off before you build anything!
3.

Connect the +5V and ground (GND) leads of the power supply to the power and ground bus strips on your breadboard.

4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction with 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip package). 5. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard. 6. Select a connection on your schematic and place a piece of hook-up wire between corresponding pins of the chips on your breadboard. It is better to make the short connections before the longer ones. Mark each connection on your schematic as you go, so as not to try to make the same connection again at a later stage.
7.

Get one of your roup members to check the connections, before you turn the power on.

8. If an error is made and is not spotted before you turn the power on, Turn the power off immediately before you begin the rewire the circuit.
9.

At the end of the laboratory session, collect your hook-up wires, chips and all equipment and return them to the demonstrator.

In all experiments. Not connecting the ground and/or power pins for all chips. Common Causes of Problems 1. 2. Leaving out wires. Please inform the demonstrator or technician if you locate faulty equipment. Plugging wires into the wrong holes. you will be expected to obtain all instruments. 4. don’t put it back in the box of chips for somebody else to use. inform a demonstrator. components at the start of the experiment and return them to their proper place after you have finished the experiment. Not turning on the power supply before checking the operation of the circuit. . Tidy the area that you were working in and leave it in the same condition as it was before you started. If you damage a chip. 3. 5. leads. Modifying the circuit with the power on.10.

Sometimes the chip manufacturer may denote the first pin by a small indented circle above the first pin of the chip. Remember that you must connect power to the chips to get them to work . to save confusion at a later stage. Place your chips in the same direction.

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SYLLABUS Introduction to digital electronics lab. T and D flip-flops using NAND & NOR gates. To verify the operation of a digital comparator. Implementation of the given Boolean function using logic gates in both SOP and POS forms. Implementation of 4x1 multiplexer and 1x4 demultiplexer using logic gates. 4. verification of the truth tables of logic gates using TTL ICs. Implementation of 4-bit parallel adder using 7483 IC. 1. and verify the 2-bit asynchronous counter. 8. concept of Vcc and ground. Verification of state tables of RS. Implementation and verification of Decoder and Encoder using logic gates. Design. JK.nomenclature of digital ICs. 6. To design a 16:1 multiplexer using two 8:1 multiplexers. 2. . 7. 9. study of the data sheet. 10. 5. 3. Mini Project. specifications.

Mainly used in digital electronics lab are the TTL and the high speed CMOS families. 1 2 3 4 5 6 7 8 Name of Apparatus 7400 7408 7432 7402 7404 7486 Digital Trainer kit Patch Cords Specifications Qty.Various families of logic ICs exist on the market however the families.nomenclature of digital ICs. specifications. verification of the truth tables of logic gates using TTL ICs.1 OBJECTIVE: Introduction to digital electronics lab. study of the datasheet. Nomenclature of digital IC’s:MM74XXXNNRP .No.EXPERIMENT NO. concept of Vcc and ground. APPARATUS REQUIRED: S. TTL NAND Gate 01 TTL AND Gate TTL OR gate TTL NOR Gate TTL NOT Gate TTL X-OR Gate 01 01 01 01 01 With Bread board 01 & 5V dc Supply As required THEORY: IC Family Summary :.

Package Type Manufacturer --.Technology type .Low speed CMOS Vcc :. Ground :.Revision .Manufacturer Temperature range . Vcc terminal is always Red.Standard (commercial) 0 to 70ºC .It is zero potential point. PROCEDURE: .It is supply voltage which operate any instrument without damaged.Military -55 to 125ºC Technology Type XXX LS – Low power schottky ALS – Advanced low power schottky Fv -.Fast TTL HC -.National Semiconductor Temperature Range – 74 or 54 74 54 .MM SN .MM 74/54 XXX NNN R RP .Logic Function .Texas Instrument. Motorola DM . GND terminal is always black.high speed CMOS C -.

• Repeat step 2 to 4 as given for OR gate. OR Gate • Place the 2 Input OR gate IC 7432 in the bread board. 2. 3. NOR Gate • • Place the 2 Input NOR gate IC 7402 on the bread board. • Make the connection for gate 1 connect among pin 1and 2. • Connect pin no. NOT Gate • Place NOT gate IC 7404 on the bread board.14 to Vcc(+5V) and pin no. • Make the connection for gate 1 connect among pin 1. AND Gate • Place the 2 Input AND gate IC 7408 on the bread board. • Verify the truth table for various combinations of inputs. • Verify the truth table for various combinations of inputs. . • Connect pin no. 4. • Connect the output to pin no. • Verify the truth table for various combinations of inputs. 3. • Repeat step 2 to 4 as given for OR gate. 7 to ground.1. 7 to ground.2 and 3.14 to Vcc(+5V) and pin no. NAND Gate • Place the 2 Input NAND gate IC 7400 on the bread board. 5. • Verify the truth table for various combinations of inputs. Repeat step 2 to 3 as given for OR gate.

• Verify the truth table for various combinations of inputs. Mathematically x = A. Mathematically x = A+B The OR gate is a logic gate that gives an output that is opposite the state of its input. 6. Thus its is ‘0’ whenever atleast one of its input is ‘0’. Thus its is ‘1’ whenever atleast one of its input is ‘1’. X-OR Gate • Place the 2 Input X-OR gate IC 7486 on the bread board. • Repeat step 2 to 4 as given for OR gate.B The OR gate is a logic gate that gives an output of ‘0’only when all of its inputs are ‘0’. B 0 0 0 1 X=A+ B 0 1 1 1 OR GATE NOT GATE NAND GATE . Thus for the same combinations TRUTH TABLE A 0 0 1 1 A 0 0 1 1 A 0 1 A 0 1 0 B 0 1 B 0 1 0 1 B 0 1 0 1 X=A. • Verify the truth table for various combinations of inputs Logic Diagram and Truth Tables for various logic gates: GATE AND GATE DESCRIPTION The AND gate is a logic gate that gives an output of ‘1’only when all of its inputs are ‘1’. The NAND gate is and AND gate with a NOT gate at its end.

PRECAUTIONS: 1. The Exclusive OR gate is a logic gate that gives an output of ‘1’ when only one of the input is ‘1’. All connections should be tight. All the ICs should be checked before use the apparatus. Thus for the same combinations of the inputs.of the inputs. 2. The circuit should be off before change the connections. 5. 1 0 0 0 EX-OR GATE B RESULT: Introduction to digital electronics lab. Always connect GND first and then connect Vcc. Use suitable type Patch cords. 3.nomenclature of digital ICs. concept of Vcc and ground. 6. . the output of the NOR gate will be opposite that of an OR gate. specifications study of data sheet. 4. the output of the NAND gate will be opposite that of an AND gate. Verification of truth tables of logic gates using TTL ICs. All LEDs should be checked. 0 1 1 A 0 0 1 1 A 0 0 1 1 1 0 1 B 0 1 0 1 B 0 1 0 1 0 1 1 0 1 1 0 NOR GATE The NOR gate is and OR gate with a NOT gate at its end.

EXPERIMENTAL QUIZ: 1.2 OBJECTIVE: .After completed experiments switch off the supply of the apparatus. Which gate is generally used to recognize words that have odd number of one’s? 3. EXPERIMENT NO. What is universal gates? 2. How can you inhibit an AND gate? 4. Using only NAND gates. realize the NOR logic function.

In this approach we assign ‘1’ value to the normal variable and ‘0’ to its complements. An arbitrary logic function can be expressed in the following forms: i) Sum of Products (SOP) ii) Product of Sums (POS) Sum of Products (SOP): The logic sum of two or more logical product terms is called a Sum of Products Expression.7432 Quantity 01 As required THEORY: Logical functions are generally expressed in terms of logical variables. 1 2 Name of Apparatus SOP & POS kit Patch cords Specifications Using 7404. 7408. Values taken on by the logical functions and logical variables are in the binary form.NO. . APPARATUS REQUIRED: S.Implementation of the given Boolean function using logic gates in both SOP and POS forms. Also considered the values to find the expression from any arithmetic or logic calculation. It is basically an OR operation of AND operated variable such as: In this approach we simplified the given Boolean expression using basic Boolean laws and theorem.

Connect the circuit as per circuit diagram. Also considered the values to find any arithmetic or logic calculation. It is basically an AND operation of OR operated variables such as: In POS form we simplified the given Boolean expression using basic Boolean laws and theorem. . PROCEDURE:1. In this approach we assign ‘0’ values to normal variable and ‘1’ to its complements.Product of Sums (POS) Product of Sums(POS): A product of Sums expression is a logical product of two or logical sum terms.

All the connection should be tight. 2.2. Give the inputs to A & B through switches. PRECAUTIONS: 1. For different combination of inputs observe the output and match them with respective truth table and verify the equations SOP & POS. 4. 5. All ICs should be checked before starting the experiment. 3. . Observe the output Y on the kit through LEDs. Switch ON the experimental board. TRUTH TABLE FOR SOP INPUT A 0 0 1 1 0 1 0 1 B 0 1 1 0 OUTPUT TRUTH TABLE FOR POS INPUT A 0 0 1 1 0 1 0 1 B 1 0 0 1 OUTPUT RESULT: Study of Boolean function and both equations SOP & POS are verified.

5. 4. Differentiate between minterms and maxterms. 3. After completed the experiments switch off the supply of the apparatus. Suitable type wire should be used for different types of circuit. What are literals? EXPERIMENT NO. 3 .3. How do you convert an SOP form to a POS form and vice-versa? 2. Always connect ground first and then connect Vcc. The kit should be off before change the connections. EXPERIMENTAL QUIZ: 1. 6.

A<B. The logic symbol and pin diagram of a 4-bit comparator is shown below:A1 A2 A>B A3 A=B B0 B1 B2 B3 B1 LOGIC SYMBOL B2 B3 IC B3 A<Bin A=Bin A>Bin A>Bout A=Bout A<Bout A <B 16 1 2 3 4 7485 5 6 7 Vc c A3 B2 A2 A1 B1 A0 15 14 13 12 11 10 9 8 B0 7485 . the logic comparison of two quantities is frequently required. Magnitude comparators are often used as a part of address decoding circuitry used in computer to select a specific input or output device.STUDY OF DIGITAL COMPARATOR MOTIVATION: In digital circuits. it has three cascading inputs. These A0 inputs allow several comparators to be cascaded for comparison of any number of bits greater than four. A>B. A=B. OBJECTIVE: To verify the operation of a digital comparator. THEORY: A comparator compares the magnitude of two numbers and indicates which one is bigger of the two. A>B or A<B. IC 7485 is a 4-bit comparator which indicates whether A=B. or if the two numbers are equal. The basic function of the combinational circuit-comparator is to compare and determine the relationship of two binary quantities.PIN DIAGRAM G N D . In addition.

The following conditions are possible:If A1 = 1. If A1 = B1. the relationship of the two numbers is established and any other inequalities in lower-order bit positions must be ignored. When such an inequality is found. Connect pin 16 of IC 7485 to Vcc and pin 8 to ground. number A is greater than number B. Verify the truth table of the comparator for different combinations of A and B. A1 0 0 0 0 0 0 0 0 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 A=B 1 0 0 0 0 1 0 0 0 0 1 0 A>B 0 0 0 0 1 0 0 0 1 1 0 0 . B1 = 0. number A is less than number B. A1 and B0. 2. connecting wires. Connect the terminals A0. then examine the lower bit position. EQUIPMENT REQUIRED: IC 7485. Connect A<Bout. first examine the highest order bit in number. A=Bout and A>Bout at the output. Thus to determine the inequality of binary numbers A and B. PROCEDURE: 1. 4. B1 to binary inputs. 5. starting with MSB. If A1 = 0. 3.The general procedure used in a comparator is to check for an inequality in a bit position. digital trainer kit. B1= 1. Prepare the truth table of comparator .

A0 as D. . B1 as A and B0 as B.1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 For K-Maps we are considering A1 as C. K-Map for A<B K-Map for A=B K-Map for A>B RESULT: Operation of Digital Comparator is verified.

Draw the combinational circuit of a 3-bit comparator using gates.4 . 5. 4. What is the utility of a comparator? 2. Write down the Boolean expression for A=B. A>B and A<B for the above circuit. EXPERIMENT NO. Construct the truth table of a three-bit comparator. Which gate serves as a basic comparator? 3.POST-EXPERIMENTAL QUIZ: 1.

Parallel Adder : A n-bit parallel adder can be constructed using number of full adders circuit connected in parallel the carry output of each is connected to the carry input of the next higher-order adder. IC 7483 3. B3 are BCD inputs S0. Digital Trainer Kit. 2. Connecting Wires THEORY: Adder: An adder is a logic circuit which adds two or three bits at a time and give sum and carry as the result. S3 are Sum outputs. Since all the bits of the augends and addend are fed into the adder circuits simultaneously and the additions in each position are known as parallel adder. S1.OBJECTIVE: Implementation of 4-bit parallel adder using 7483 IC. B2. . B1. A3 & B0. A2. A1. APPARATUS REQUIRED: 1. S2. A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 → Augends bits → Addend bits → Sum bits LOGIC DIAGRAM OF BCD ADDER & SUBTRACTOR Where A0.

A2. 5.13 to ground so that carry input(CY1) will be logic ‘0’ state. Connect ground and Vcc to 7483 IC from trainer kit through patch cords. Connect carry in from pin no. 2.B1.B2.A3 and B0.PIN DIAGRAM OF 7483 IC PROCEDURE: 1. 9. Connect inputs A0.A1.S1. Verify truth tables for different combinations of inputs.S2.B3 to logic input switches. Connect S0.S3 and carry out(CY0) from pin nos.2. TRUTH TABLE: The Truth table operation of the 4-bit Parallel Adder is shown below: INPUTS A0 A1 A2 A3 B0 B1 B2 B3 CY1 OUTPUT S0 S1 S2 S3 CY0 .6. 4. 3.15 and 14 to the output display.

2. observed the LED output and verified the truth table. 2. All the connection should be tight. Make the truth table and logic diagram of a half adder. 4. 5. Implement a half adder using only NAND gates.0 1 0 0 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 RESULT: For various combinations of selected input lines. Draw the block diagram of a full adder as a combination of two half adders. POST-EXPERIMENTAL QUIZ: 1. All ICs should be checked before starting the experiment. 5(a) Implementation of 4x1 multiplexer using logic gates. EXPERIMENT NO. The kit should be off before change the connections. Implement a full adder using only NOR logic. 3. 6. PRECAUTIONS: 1. . Derive the Boolean expressions for the outputs S and Co of a full adder from the truth table. After completed the experiments switch off the supply of the apparatus. 4. 3. Suitable type wire should be used for different types of circuit. 5. Always connect ground first and then connect Vcc.

If the number of n inputs lines is equal to 2m. NOT-7404 Gate IC. These devices significantly reduce IC package count. data output Y is equal to D0 if and only if S1=0 and S0=0. The logic symbol for a 1 to 4 data selector/multiplexer is shown in Figure: Data Select S0 S1 D0 D1 0 MUX 1 0 1 2 3 Y Data D2 Inputs D3 The selection lines decide the number of inputs lines of particular multiplexer. Connecting wires. OBJECTIVE: Implementation of 4x1 multiplexer using logic gates. EQUIPMENT REQUIRED: Digital trainer kit. To achieve this MUX has several data lines and a single output along with data-select inputs. Thus it is necessary for the designer to become familiar with the functions of these devices. OR-7432. AND-7411. THEORY: Multiplexer: A multiplexer (MUX) is a device that accepts data from one of many input sources for transmission over a common shared line. Note that if a binary zero appears on the data-select lines then data on input line D0 will appear on the output. thereby reducing the system count and improving the system reliability.MOTIVATION: Multiplexer are complex integrated circuits that find application in combinational system design. Thus. . then m select lines are required to select one of the n input line. which permit digital data on any of the inputs to be switched to the output line.

. the data output is equal to D1. D2 and D3 for . Thus the total multiplexer logic expression. Connections are made as per circuit diagram.Similarly. formed from ORing terms is The implementation of this equation is as shown in figure: TRUTH TABLE : Data Select Input S1 0 0 1 1 S0 0 1 0 1 D0 D1 D2 D3 Input Selected PROCEDURE: 1. and respectively.

Connecting wires. OBJECTIVE: Implementation of 1x4 demultiplexer using logic gates. EQUIPMENT REQUIRED: Digital trainer kit. POST-EXPERIMENTAL QUIZ: 1. NAND-7410. 3. After completed the experiments switch off the supply of the apparatus. Suitable type wire should be used for different types of circuit. MOTIVATION: To study the working of transmission of multiple user’s data on single line. Draw the circuit of full adder using multiplexer. What are the advantages of using multiplexers over gates in order to realize any function? 3. 5. . Always connect ground first and then connect Vcc. What is a multiplexer? 2. EXPERIMENT NO. PRECAUTIONS: 1.2. Verify the truth table. All the connection should be tight. All ICs should be checked before starting the experiment. 5(b) Implementation of 1x4 Demultiplexer using logic gates. Also connect Vcc and Ground then performed experiment. The kit should be off before change the connections. 2. 6. 3. NOT-7404 Gate IC. 4. RESULT: Study of 4×1 multiplexer and verified its truth table .

it takes a single input and distributes it over several outputs. The input data line goes to all of the NAND gates. The truth table for a 1:4 Demultiplexer is shown below .The two select lines S0 and S1 enable only one gate at a time. So .THEORY: A Demultiplexer performs the reverse operation. below shows the logic circuitry for a 1-line to 4-line Demultiplexer circuit . and the data appearing on the input will pass through the selected gate the associated output line.since it transmits the same data to different destinations. Thus Demultiplexer is a 1-to-N(or 2n) device.a Demultiplexer can be thought of as a “distributor” . Fig.

Connect the data input (1) to any of the multiplexer inputs. 2. Select lines S0. 4.6 . RESULT: Study of 1:4 demultiplexer and verified its truth table. observe the LED output and verify the truth table. S1 are connected to binary inputs 0/1. Give supply to pin 16 and connect pin 8 to ground. 3. Connect All ICS on the bread board of digital trainer kit. EXPERIMENT NO. 5. For various combinations of select input lines. POST-EXPERIMENTAL QUIZ: 1) Design the circuit of 1:8 demultiplexer.PROCEDURE: 1.

digital trainer kit. one out of 8 inputs is to be selected and the number of select lines is 3. So is the case in . In MUX1. When the number of inputs is more than 8. IC 7404. the number of select inputs required is m where 2 m = N. also called a multiplexer stack. Hence it is essential to get familiar with the design of multiplexer trees or stacks. wires.1 If one out of N inputs is to be selected. 1 shows an arrangement for 16:1 multiplexer using two 8:1 MUX and one 2:1 MUX. a multiplexer tree can be used. OBJECTIVE: To design a 16:1 multiplexer using two 8:1 multiplexers EQUIPMENT REQUIRED: IC 74151A (2).MULTIPLEXER TREE MOTIVATION: In order to meet the requirement of larger number of inputs. THEORY: A single 8:1 multiplexer IC can handle a maximum of 8 inputs. multimeter. there should be a provision for expansion of the multiplexers. IC 7432. 0 1 2 Data Inputs 3 4 5 6 L o g i c 0 7 B C D 8 9 Data Inputs 1 0 1 1 1 2 1 3 1 4 1 5 L o g i c 0 8 : 1 M U X Y 2 S 2 S 1 S 0 L o g i c A 0 S 2 S 1 S 0 2 : 1 S M U X Y 8 : 1 M U X Y 1 ( M S B ) Fig. Fig.

In MUX3. final output will be I5. If ABCD = 1101. If BCD is 000.MUX2. output of MUX1 will be the final output.2 using two 8:1 MUX and one OR gate. the output of MUX1 will be I0. If A = 0. final output will be I13. For example. . output of MUX2 will be the final output. one out of two inputs is to be selected and the number of select lines is 1.2 If ABCD = 0101. If A = 1. if BCD = 000. the final output will be I4. MUX1 selects one out of its 8 inputs (I0 to I7) depending on the address BCD. output of M2 will be I8. MUX3 selects one out of its two inputs depending on the address A. 0 1 2 Data Inputs 3 4 5 6 7 B C D 8 9 Data Inputs 1 0 1 1 1 2 1 3 1 4 1 5 A ( M S B ) 1 7 2 4 0 4 8 : 1 M U X Y 2 S 2 S 1 S 0 S 2 S 1 S 0 1 2 3 Y 8 : 1 M U X Y 1 Fig. So if ABCD = 0100. Another method is shown in fig. Similarly MUX2 selects one out of its 8 inputs (I8 to I15) depending on the address BCD.

Switch on the supply +5V. 4.B. Give binary inputs A. 2. Observe the output. 5. POST-EXPERIMENTAL QUIZ: . Connect the circuit as shown in fig.D. Verify the truth table shown below.C. 3.2.PROCEDURE: 1. TRUTH TABLE: INPUTS A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT Y I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 RESULT: : Study of 16:1 multiplexer using 8:1 multiplexers and verified its truth table.

11. 3. 13.1. The Boolean expression for a 4 variable logic function is: Y= Σ m (0. EXPERIMENT 7 IMPLEMENTATION OF DECODER & ENCODER USING LOGIC GATES . 2. 9. 15) Implement using a 16:1 MUX. Design an XOR gate using one 2:1 MUX. 6. What is a multiplexer tree? 2. 8.

Decoder is used at the receiver to convert the received encoded data back to the original message. 7432 IC. EQUIPMENT REQUIRED: Digital trainer kit. 7411 IC and Connecting wires. OBJECTIVE : Implementation and verification of decoder and encoder using logic gates. 7404 IC.MOTIVATION: Decoder is an important part of Digital Circuit and is used not only in computer systems but also in communication systems. .

The number of bits depends upon the decimal value which is being encoded.Encoder is used at the starting stage to encode the message into a unique code. The encoded binary word has number of bits associated with it. . Encoder encodes different types of messages into various forms. In Digital Circuits it encodes a decimal value into a binary word. For example in case of decimal values ranging from 0 to 7 the number of bits required to encode these values is 3.

. Connect the supply from the trainer kit through patch chords. Observe the output Y0.TRUTH TABLE OF 4:2 ENCODER I3 0 0 0 1 PROCEDURE: INPUT I2 I1 0 0 0 1 1 0 0 0 I0 1 0 0 0 OUTPUT Y1 Y0 0 0 0 1 1 0 1 1 1. How decoder is different from demultiplexer? Define various types of Encoders.I2 and I3. For the different combinations of inputs observe the output and match the truth table. RESULT: Truth tables of Encoder and decoder are verified. also connect circuit as per circuit diagram. 3.I1. 2. Convert 2x4 decoder into 1:4 Demultiplexer. Y1 on the trainer kit through LED’s. POST-EXPERIMENTAL QUIZ: 1. 2. 4. How many 2x4 decoders are required to make one 4x16 decoder. 4. 3. Give the input connections to I0.

EQUIPMENT REQUIRED: IC 7400 (NAND Gate). IC 7408 (AND Gate) THEORY: : In case of sequential circuits the effect of all previous inputs on the outputs is represented by a state of the circuit. Flip-flops are combined together to form counters. Flip-flops are classifieds according to the number of inputs. These also determine the next state of the circuit. The present state designates the state of flip-flops before the occurrence of a clock pulse. flip flop is the most widely used memory element. The relationship that exists among the inputs. State Table The state table representation of a sequential circuit consists of three sections labeled present state. . Practically. next state and output. FLIP-FLOP: The basic one bit digital memory circuit is known as flip-flop.EXPERIMENT NO. Thus. OBJECTIVE: Verification of state tables of 1) R-S flip-flop 2) J-K flip-flop 3) T flip-flop 4) D flip-flop Using NAND and NOR gates. IC 7402 (NOR Gate). present states and next states can be specified by either the state table or the state diagram. it is necessary to become familiar with their operation. MOTIVATION: The basic building block of a sequential circuit is a flip-flop. and the output section lists the value of the output variables during the present state. shift registers and various memory devices. R-S FLIP-FLOP : The circuit is similar to SR latch except enable signal is replaced by clock pulse.-8 VERIFICATION OF STATE TABLES OF FLIP FLOPS USING NAND & NOR GATES.It can store either 0 or 1. the output of the circuit at any time depends upon its current state and the input. So. outputs. The next state shows the states of flip-flops after the clock pulse.

In many practical applications. .From the truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs are same. these input conditions are not required. These input conditions can be avoided by making then complement of each other.LOGIC DIAGRAM : CLOCK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ S 0 0 0 0 1 1 1 1 R 0 0 1 0 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 0 1 1 X X State Qn (No Change) Reset Set Prohibited State D FLIP-FLOP: The modified clocked SR flip-flop is known as D-flip-flop.

. The RS flip-flop circuit may be rejoined if both inputs are 1 than also the output are complement of each other.J-K FLIP-FLOP: In a RS flip-flop the input R=S=1 leads to an indeterminate output.

. The T flip-flop is modification of the JK flip-flop.CLOCK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 0 1 1 X X State Qn (No Change) Reset Set Qn (toggle) T FLIP-FLOP: T flip-flop is known as toggle flip-flop. Both the JK inputs of the JK flip-flop are held at logic 1 and the clock signal continuous to change the outputs will simply change state with each rising edge of the clock signal.

Verify truth-tables for various combinations of input. The circuit should be off before change the connections. Always connect GROUND first and then Vcc. Connections are made as per circuit diagram. 3. RESULT: Study and verified truth-tables of various flip-flops. T 0 0 1 1 Qn 0 1 0 1 Qn+1 0 1 1 0 STATE NC Toggle 2. 2. What is the advantage of JK flip flop over SR flip flop? 2. Convert a JK flip flop into SR flip flop. All connections should be tight. 4. POST-EXPERIMENTAL QUIZ: 1. All the IC’s should be checked before use the apparatus. All LED’s should be checked. 5. After completing the experiment switch off the supply to apparatus. 6. PRECAUTIONS: 1.TRUTH TABLE: CLOCK ↑ ↑ ↑ ↑ PROCEDURE: 1. . What is the race around condition in flip-flops? 3.

EXPERIMENT NO. Counters are broadly classified as Synchronous and Asynchronous counters. The n bit asynchronous counter uses n flip flops and counts 2n clock pulses.-9 MOTIVATION: To verify Two bit asynchronous counter using J-K flip flops OBJECTIVE: Design. THEORY: Counters are the sequential circuits used to count the clock pulses. and verify the 2-bit asynchronous counter. Asynchronous counters are also known as Ripple counters In case of synchronous counters a single clock is used for all the flip flops whereas the clock used for asynchronous counter depends on the previous output of flip flop. The stages of flip flops depend on the number of states. Due to this reason the asynchronous counters are slower than synchronous counterpart. 1 2 PRE 4 J C 6 K Q K Q 1 1 Q 01 J C 6 K PRE 5 4 1 4 1 2 Q K Q 1 4 1 5 Q 1 C L K 1 1 L C LR L C LR 3 3 . Ripple counters are deigned by using J-K and T flip flops.

Give supply by connecting the corresponding pins to Vcc and and ground of the flip flop IC. Connect All ICS on the bread board of digital trainer kit. The inputs of both the flip flops are connected to logic high. PROCEDURE: 1. RESULT: 2-bit asynchronous counter is verified. Connecting wires. After the active edge of each clock pulse the state of flip flops changes and thus clock pulses are counted. 3.TIMING DIAGRAM OF 2 BIT ASYNCRONOUS COUNTER EQUIPMENT REQUIRED Dgital trainer kit. 5. 4. Give clock input from trainer kit to the first flip flop and clock input for the second flip flop is the output of the first flip flop. J-K-7476 IC. Design a Negative edge triggered MOD-12 Asynchronous Down counter flops? using J-K Flip . POST-EXPERIMENTAL QUIZ Q1). 2.

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