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ppt by mudit n vibhu

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Published by: Funnyguy Savy on Apr 10, 2011
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04/10/2011

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Computer Operations
1. Control Unit 2. Arithmetic and Logic Unit 3. Instruction Cycle

Simple Computer

Simple Model Computer block diagram
control bus address bus

CPU

Arithmetic and logic unit

Control unit

Memory unit

Input/ output unit

data bus

Arithmetic and logic unit 1 Arithmetic and Logical operations are performed in the ALU ALU 2 ALU consists of an accumulator (ACC). and a status register (SR). SR ACC . a set of logic circuits.

the instruction register (IR) and the instruction decoder. PC 2 Control Unit Consists of the program Counter (PC). IR .Control unit 1 Control Unit Instruction decoder controls the overall operations of the computer.

Memory Unit 1 address decoder main memory 1 MAR Memory unit consists of the main store. 2 Main store is composed of a large number of memory locations. the memory address register (MAR). the memory data register (MDR). and the address decoder. MDR .

Memory Unit 1 3 Address decoder is responsible for selecting the appropriate memory location. The memory data register holds the piece of information read from or written to the specified memory location 4 5 The memory address register holds the address of the memory location to be accessed. .

Instruction Cycle .

Instruction is then executed. .Instruction Cycle 1 2 3 4 The instruction is fetched from memory addressed by PC. PC is advanced to address the next instruction. Instruction Decoder decodes the instruction held in IR. The process is repeated until the complete set of instructions is fetched.

Instruction Cycle Fetch instruction from memory to IR Increment PC Execute the instruction Decode the instruction .

address decoder main memory MAR Instruction decoder ALU PC SR ACC IR MDR I/O unit .

Memory unit address decoder main memory MAR Instruction decoder PC ALU SR ACC IR MDR I/O unit .

Control unit Memory unit address decoder main memory MAR Instruction decoder PC ALU SR ACC IR MDR I/O unit .

Arithmetic and logic unit Control unit address decoder Memory unit main memory MAR Instruction decoder PC ALU SR ACC IR MDR I/O unit .

Instruction number 1 2 3 Instruction Load the contents in memory location 11111 into the ACC Add the contents in memory location 11110 to the ACC Store the result held in the ACC in memory location 11101 Address location 10000 10001 10010 .

Main memory .

Load the contents in memory location 11111 into the ACC .

Fetch cycle .

Fetch cycle .step 1 10000 PC .

step 2 MAR 10000 10000 PC .Fetch cycle .

Fetch cycle .step 3 MAR 10000 Address decoder Main memory Instruction 1 10000 10000 PC .

Fetch cycle .step 4 10000 Address decoder Main memory Instruction 1 Instruction 2 Instruction 3 10000 10001 10010 10000 Number 1 11111 Instruction 1 MDR .

step 5 10000 10000 Instruction 1 IR Instruction 1 MDR .Fetch cycle .

Executing cycle .

Executing cycle .step 1 10000 10000 10001 PC Instruction 1 Instruction 1 .

step 2 10000 Instruction decoder 10001 PC Instruction 1 IR Instruction 1 .Executing cycle .

step 3 MAR 10000 11111 Instruction decoder 10001 Instruction 1 Instruction 1 .Executing cycle .

step 4 MAR 11111 Address decoder Main memory 10001 Number 1 Instruction 1 Instruction 1 11111 .Executing cycle .

Executing cycle .step 5 11111 Main memory 10001 Number 1 Instruction 1 11111 Number 1 Instruction 1 MDR .

Executing cycle .step 6 11111 10001 Number 1 Number 1 ACC Instruction 1 Number 1 MDR .

Fetch Executing .

Add the contents in memory location 11110 to the ACC .

Fetch cycle MAR 10001 11111 Address decoder Main memory Instruction 2 10000 10001 10010 10001 PC Number 1 1 Instruction 2 IR Number 1 Instruction 2 MDR .

Executing cycle MAR 10001 11110 ALU Instruction decoder Address decoder Main memory 10001 10010 PC Number 2 11110 Number 1 ACC Result Instruction 2 IR Instruction22 MDR Number .

Store the result held in the ACC in memory location 11101 .

Fetch cycle MAR 11111 10010 Address decoder Main memory 10000 Instruction 3 10010 10010 PC Result 1 Instruction 3 IR Number 1 Instruction 3 MDR .

Executing cycle MAR 10001 11101 Instruction decoder Address decoder Main memory 10001 10011 PC Result Number 2 11101 Result ACC Instruction 3 IR Result 3 Instruction 2 MDR .

Decode the instruction in IR PC --- .Summary Control nit Register Instruction Register Program Counter Instruction Decoder Abbreviation IR unction Stores the current instruction Stores the address of the next instruction to be executed.

The End !!! Thank You!!! .

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