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Computer Engineering Department Course Name: Basic Electronics Semester: Spring 2010, 3rd Batch: 2009(Sections: A,B)

Assignments # 1

Course Responsible

Syed Hassan Raza Naqvi Assistant Professor, Computer Engineering Department Office: STI,

B) Last Submission Date: 6th MARCH. Load Line Analysis: Q1 – to – Q4 Series Diode Configuration with DC Inputs: Q5 – to – Q9 Parallel and Series Parallel Configuration: Q10 – to – Q13 Half Wave Rectification: Q22 – to – Q27 Full Wave Rectification: Q28 – to – Q31 Clipper: Q32 – to – Q36 Clamper: Q37 – to – Q41 Zener Diode: Q42 – to – Q46 Voltage Multiplier: Q47 – to – Q48 . Assignment # 1 1. 7. 6. 2010.SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY COMPUTER ENGINEERING DEPARTMENT BASIC ELECTRONICS 2009 BATCH (Sections: A. 8. 5. 9. 4. 4PM. 2. 3.

131 Problems 1. (a) Using the characteristics of Fig. Repeat part (a) with R 0. (b) Perform the same analysis as part (a) using the ideal model for the diode.132 that will result in a diode current of 10 mA if E 7 V.§ 2. and VR for the circuit of Fig. 2. determine the level of VD.18 k . 4. ID. (b) Repeat part (a) using the approximate model for the diode and compare results. (a) Using the approximate characteristics for the Si diode. 2.131a.131b. 3 How do the resulting levels of ID compare? Comment accordingly. Use the characteristics of Fig.133.132 Problems 2.131b for the diode.47 k .132. Is the level of VD relatively close to 0. 2. 2. determine ID.133 Problem 4 103 . (c) Repeat part (a) using the ideal model for the diode and compare results.2 Load-Line Analysis 1. Determine the value of R for the circuit of Fig.131b. 2. PROBLEMS Figure 2. 3. determine ID and VD for the circuit of Fig. 2. 2. Repeat part (a) with R 0. (a) (b) (c) (d) Using the characteristics of Fig. VD.7 V in each case? Figure 2. (c) Do the results obtained in parts (a) and (b) suggest that the ideal model can provide a good approximation for the actual response under some conditions? Problems Figure 2. 2 2. and VR for the circuit of Fig.

Determine Vo and ID for the networks of Fig.137 Problem 8 104 Chapter 2 Diode Applications .§ 2.134 Problem 5 6. Determine the level of Vo for each network of Fig. Figure 2.136 Problem 7 * 8.134 using the approximate equivalent model for the diode. 2. 2.135 Problems 6. 49 * 7. Determine Vo and ID for the networks of Fig. Determine the current I for each of the configurations of Fig. Figure 2. Figure 2.136. Figure 2. 2. 2.135.137.4 Series Diode Configurations with DC Inputs 5.

2. Figure 2. Determine Vo1 and Vo2 for the networks of Fig. Figure 2.5 Parallel and Series–Parallel Configurations 10.140 Problem 11 Problems 105 .138. 50 * 11. Determine Vo and I for the networks of Fig. 2.140.139. Figure 2.139 Problems 10. 2. Determine Vo and ID for the networks of Fig.* 9.138 Problem 9 § 2.

146 Problem 21 § 2. 20. Determine Vo for the network of Fig.7 Sinusoidal Inputs.148 Problem 24 Figure 2. 15. Determine Vo for the negative logic AND gate of Fig. 2. * 13. 19. 2. 51 § 2.144 Problem 19 Figure 2.149. Determine Vo for the negative logic OR gate of Fig. Figure 2. 25. 2. sketch vi.146. 2.144. 23. 17. 2. Figure 2. Half-Wave Rectification 22. and I for the network of Fig. 2. Sketch vL and iL. Determine Vo for the network of Fig. The input is a sinusoidal waveform with a frequency of 60 Hz * 23.149 Problem 25 106 Chapter 2 Diode Applications . Figure 2.143 Problem 18 21. 2.148.41 with 10 V on both inputs. Determine the level of Vo for the gate of Fig.143. 24 Figure 2. Determine Vo for the network of Fig.6 AND/OR Gates 14.145. 2.38 with 0 V on both inputs.38 with 10 V on both inputs. Assuming an ideal diode. Vo2. and id for the half-wave rectifier of Fig. Determine Vo and ID for the network of Fig. Determine Vo for the configuration of Fig. 18.147. 16.142 Problems 13. 2.142. For the network of Fig. Figure 2.141 Problem 12 Figure 2. 2.141. Repeat Problem 22 with a 6. 2.7 V). load applied as shown in Fig. 2. 2.147 Problems 22.8-k 0. Determine Vo1.145 Problem 20 Figure 2. sketch vo and determine Vdc.12.41 with 0 V on both inputs. vd. Repeat Problem 22 with a silicon diode (VT * 24. Determine Vo for the network of Fig.

Figure 2. Figure 2.150 Problem 26 * 27. 2. (c) Find the maximum current through each diode during conduction. (a) Given Pmax 14 mW for each diode of Fig. (d) What is the required power rating of each diode? 29.151 Problem 27 § 2. A full-wave bridge rectifier with a 120-V rms sinusoidal input has a load resistor of 1 k . (e) If only one diode were present. (a) If silicon diodes are employed.* 26. (c) Determine the current through each diode at Vimax using the results of part (b).152 Problem 29 Problems 107 .152. sketch vo and iR.151.8 Full-Wave Rectification 28.150. 2. 2. what is the dc voltage available at the load? (b) Determine the required PIV rating of each diode. determine the diode current and compare it to the maximum rating. Figure 2. determine the maximum current rating of each diode (using the approximate equivalent model). Determine vo and the required PIV rating of each diode for the configuration of Fig. (b) Determine Imax for Vimax 160 V. For the network of Fig.

Determine vo for each network of Fig. Figure 2.154 Problem 31 § 2.153 and determine the dc voltage available.155 for the input shown.* 30.156 Problem 33 108 Chapter 2 Diode Applications .154 and determine the dc voltage available. Figure 2.156 for the input shown.9 Clippers 32. Determine vo for each network of Fig. 2.153 Problem 30 * 31. 2. 2. Figure 2. 2. Sketch vo for the network of Fig. Sketch vo for the network of Fig.155 Problem 32 33. Figure 2.

159 Problem 36 § 2. 2. Figure 2.159 for the input shown. 2. Determine vo for each network of Fig. Sketch iR and vo for the network of Fig.160 for the input shown.10 Clampers 37.160 Problem 37 Problems 109 . Figure 2.158 for the input shown.157 Problem 34 * 35.157 for the input shown. Sketch vo for each network of Fig. Figure 2. 2.* 34. Determine vo for each network of Fig. 2. Figure 2.158 Problem 35 36.

161 for the input shown.164 Problem 41 110 Chapter 2 Diode Applications . For the network of Fig. Figure 2. Design a clamper to perform the function indicated in Fig. 2. 2.162: (a) (c) Calculate 5 .38. Figure 2.162 Problem 39 * 40. 2. Sketch vo for each network of Fig.161 Problem 38 * 39. Design a clamper to perform the function indicated in Fig. Would it be a good approximation to consider the diode to be ideal for both configurations? Why? Figure 2. Sketch vo. 2.164.163.163 Problem 40 * 41. Figure 2. (b) Compare 5 to half the period of the applied signal.

52.165 Problem 42 * 43. (a) Determine VL. IZ. 46. 2.165 if RL 180 (b) Repeat part (a) if RL 470 . § 2.121 if the secondary voltage of the transformer is 120 V (rms). Perform an analysis of the network of Fig. 2. That is.135 using PSpice Windows. Figure 2. 50. 45. Figure 2. Determine the required PIV ratings of the diodes of Fig.11 Zener Diodes * 42. Repeat for a 5-V square wave. 2.13 PSpice Windows 49.167. determine the range of Vi that will maintain VL at 8 V and not exceed the maximum power rating of the Zener diode. (a) Design the network of Fig. Design a voltage regulator that will maintain an output voltage of 20 V across a 1-k load with an input that will vary between 30 and 50 V. 2. * 44.139 using PSpice Windows. IL. Sketch the output of the network of Fig. and IR for the network Fig.121 in terms of the peak secondary voltage Vm. Perform an analysis of the network of Fig.166 to maintain VL at 12 V for a load variation (IL) from 0 to 200 mA. 51. Determine the voltage available from the voltage doubler of Fig. 2. 2. 2. (d) Determine the minimum value of RL to ensure that the Zener diode is in the “on” state. For the network of Fig.120 if the input is a 50-V square wave. determine the proper value of Rs and the maximum current IZM. Problems 111 .167 Problems 44.12 Voltage-Multiplier Circuits 47.167 using PSpice Windows.§ 2. Figure 2. 48. 2. Perform an analysis of the network of Fig. (b) Determine PZmax for the Zener diode of part (a). 2. Perform a general analysis of the Zener network of Fig.166 Problem 43 § 2. (c) Determine the value of RL that will establish maximum power conditions for the Zener diode.142 using PSpice Windows. That is. determine Rs and VZ. 2. 52 * Please Note: Asterisks indicate more difficult problems.

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