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hw4_practice_sol|Views: 298|Likes: 0

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Winter 2001

**Practice Problems on Pararasitics & Interconnects Solutions
**

Notes: For all problems assume the following parameters for MOS transistors: V tn = 0.75 V , µn ε o x µp ε ox Vtp = –0.75 V , k n' = ------------- = 21 µA ⁄ V2 , and k p' = ------------- = 7 µA ⁄ V2 . Also assume that to x t ox the supply rails and the logic levels at the inputs are set at 0V and 3.3V.

Q 1. (10.0 points) In order to drive a large capacitance (C L = 20 pF) from a minimum-size gate (with input capacitance, C i = 10fF), a designer decides to introduce a two-staged buffer as shown in the figure below. Assume that the propagation delay of a minimum-size inverter (loaded by an identical gate) is given by t p0 = 70 ps. Also, assume that the input capacitance of a gate is proportional to its size. Determine the sizing of the two additional buffer stages that will minimize the propagation delay as well as the value of the minimum delay.

A 1. Ci = 10 fF CL = 20 pF = 20000 fF = 2000 * Ci From class, the best case would be when the delay is equally distributed among the three stages. This is achieved by gradually scaling up by a constant factor u, i.e. stage 2 is u times larger than stage 1, and stage 3 is u times larger than stage 2, and C L is u times larger than stage 3. u3 = 2000, or u = 12.6.

1 of 7

3µm wide. you may ignore the resistance and inductance of the clock distribution network.043 fF/µm. given a voltage swing on the clock lines of 5 V and a maximum delay (for the output to reach 90% of the final value) of 5 nsec between clock source and destination node R. Q 2. For this part.0 points) The figure below shows a clock distribution network. a.6 = 158. the height of the wire remains con- 2 of 7 . Determine the average current of the clock driver.EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001 Therefore.5+3.7 times larger than those in the minimum sized gate. Assume that each straight segment of the network can be modeled as Π-network as shown below. (3. Draw the equivalent circuit and annotate the values of resistors and capacitors. d. and is implemented in polysilicon. Unfortunately the resistance of the polysilicon cannot be ignored. R The Π-network model for a distributed RC line C/2 C/2 c. and sheet resistance of 10 Ω/square. The delay through the new buffer = 3utp0 = 3*12. fringing capacitance to substrate of 0.6 and 12. b. Assume now that the interconnect technology get scaled in the following way: the width of the wires and the oxide thickness decrease with a factor 2.5+4+4 = 15. the two additional stages will have transistors whose W/L’s are 12.058 fF/µm2. Determine the dominant time-constant of the clock response at node R. Polysilicon has parallel-plate capaci100 fF 100 fF 100 fF R 100 fF tance to substrate of 0. This is much less than the original (signe stage) delay of 2000*70 ps = 140000 ps. Each straight segment of the clock network (between the nodes) is 5mm long.6*12.6*70 ps = 2646 ps. At each of the terminal nodes resides a load capacitance of 100 fF.

EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001 stant.9 Volt = ( 4 × 100 fF + 7 × Cwire segment ) × --------------------------5 nsec 5 × 0. Determine the speed-up or slow-down.058 fF/µm 2 + 2 × 5 mm × 0. Iaverage = C total × ∆--. while its length doubles.V --∆t 5 × 0. A 2.043 fF/µm ) ) × --------------------------5 nsec 5 × 0. The load capacitance of the fanout decreases with a factor of 2 as well.667 kΩ = 217.5C ws Rws + 7Rws × 100 fF = 9. the dominant time constant at node R is given by τ = 1. a.667 kΩ 3 µm This gives rise to the following equivalent circuit: c. Consider a straight wire of length L and width W driving a load C L .5C ws ( Rws + 2Rws ) + ( 0.5C ws + 100 fF ) ( Rws + Rws + 2Rws + 3Rws ) = 9.55 mA b. Before scaling.5 × 1300 fF × 16.9 Volt = ( 400 fF + 7 × ( 5 mm × 3 µm × 0. -------------Rws = Rwire segment = 5 mm × 10Ω ⁄ square = 16.9 Volt = ( 400 fF + 7 × ( 870 fF + 430 fF) ) × --------------------------5 nsec 5 × 0.667 kΩ + 7 × 100 fF × 16.9 Volt = 9500 fF × --------------------------5 nsec = 8. C ws = C wire segment = ( 870 + 430 ) fF = 1300 fF Also.5 ns d. Using the Penfield-Rubenstein-Horowitz approach dicussed in the class. the wire resistance and capacitance are given by 3 of 7 . You should use a single wire segment for this analysis (consisting of a straight wire connected to a load). As shown above.

5*Cws L R old = Rs × ---- W C old = 0.5*C ws Rw s Rws 100 fF + 0.5*C ws 1.5*Cws 100 fF + 0.5*C ws R ws 100 fF + 0.EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001 R ws 100 fF + 0.5*Cws 0.043 × (2 × L ) = 2 × C old 2 The slow-down is given by: 4 of 7 .043 × L After scaling. + 2 × 0.5*Cws R ws 1.058 × 2 ) × ( 2L ) × --. the wire resistance and capacitance are: 2L Rnew = Rs × ---------- = 4 × R old W - -2 W Cnew = ( 0.5*Cws R ws R ws 1.058 × L × W + 2 × 0.

determine how long it will take the output signal to come and stay within 10% of its final value.5 ----------1300 Plugging in the numbers. 100 8 + 0..5 ---------C old = --------------------------CL 1 + ---------C old For CL > 14Cold there would be a speed up.4/1. You can model the driver as a voltage source 5 of 7 .043 × L = 0.2 and 5. The copper wire on the board. consisting of very large devices of (120/1. a. C old = 0.8/1.2) for NMOS and (360/1.5 .058 × 5 mm × 3 µm + 2 × 0. otherwise a slow-down. For a single wire segment. one sees that there is a slow-down by a factor of ----------------------------. The wire inductance per unit length equals 75E-8 H/m. Determine the time it takes for a change in signal to propagate from the source to destination (the time of flights).EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001 τ new Slow-down = ---------τ old CL Rnew C new + ------ 2 = -----------------------------------------Rold ( C old + C L ) CL 4Rold 2C old + ------ 2 = ---------------------------------------------Rold ( Cold + C L ) CL 8 + 0.= 7. The bus driver is a CMOS inverter.2. an off-chip connection is necessary as shown in the figure below. which can be considered infinite. You may also assume that the on-resistance of the minimum-size devices (1. The memory input pins represent a very high impedance.043 × 5 mm = 1300 fF while C L = 100 fF .0 points) To connect a processor to an external memory. Given the driver device sizes defined above. 100 1 + ----------1300 Q 3. (5+5+5 = 15. which is 15 cm long. acts as a transmission line with characteristic impedance of 100 Ω. b.058 × L × W + 2 × 0.2) for PMOS. for NMOS and PMOS respectively) equals 10 kΩ. and scales proportionately with the size of the transistors.

Resize the device dimensions of the driver to minimize the transmission line delay.on) = 10 kΩ/(120/1.15 m Z0 = 100 Ω ZL = infinity l = 75E-8 H/m a. Determine the reflection coefficients on both the source and destination ends and draw the lattice diagram for the transmission line. Determine the minimum time and derive the sizes for the NMOS and PMOS transistors. Given: wire length characteristic impedance load impedance inductane per unit length L = 0.15/(100/75E-8) m/s = 1.e.2 Reflection coefficient at destination = 1 The lattice diagram till destination voltage is within 10% of its final value (i. A 3. Source impedance ZS = R NMOS.8) = 150 Ω Reflection coefficient at source = (150-100)/(150+100) = 0.125 ns b. between 4.EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001 with the driving device acting as series source resistance. c.on (= RPMOS.5V and 6 of 7 . time for signal propagation from source to destination = L/v = L/(Z0/l) = 0. Assume a supply and step voltage of 5V.

we will get the desired performance with NMOS and PMOS of size 180/1.EE116B : VLSI Systems Design (Mani Srivastava) Winter 2001 5.5V) is: Vsource 5V * 100/(150+100) = 2V 2V 2V + 2V * (1+0. it takes 3 trips through the wire before the output is within 10% of its final value. As described in the class.2 respectively. the source impedance should be matched with the characteristic impedance of the line.4V 2V 0V + 2V * (1+1) = 4V V dest As one can see.4V 0.125 ns.8V 0. the NMOS and the PMOS should have on resistance of 100 Ω.4/1. in this case the output will reach the desired value after one propagation delay of the waveform. To get the least transmission line delay. Since 1.4 * (1+1) = 4.e.2 and 5.4V 4V + 0.2) = 4. i.375 ns. c.2 and 540/1. In other words.2 sized NMOS and PMOS have on resistance of 10 kΩ. 1. 7 of 7 . or 3.8/1.

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Chapter04 Ex

Chapter 5 Problems CMOS INVERTER

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Chapter3 Ex

CMOS Digital Integrated Circuits Solution Manual

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