October 11, 2000

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USB 2.0 Transceiver Macrocell
Steve McGowan - Intel Corporation Clarence Lewis - Texas Instruments Haoran Duan - Agilent Technologies

October 11, 2000

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USB 2.0 Transceiver Macrocell Interface

Overview

October 11, 2000

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Macrocell Requirements 
Enable Peripherals  Does not address hubs and hosts
² No downstream port support 
Disconnect Detection 40 bit EOP

² No repeater support 
Very implementation dependent Requires separate port

October 11, 2000

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Macrocell Requirements 
Simplify the design process for peripheral vendors
² Consolidate high speed logic in to a discrete module ² Provide a ´standardµ USB 2.0 hardware interface

Overview 

Minimize time to market
² Isolate process dependent transceiver development 
Enable standard library elements from ASIC vendors

² Peripheral vendors can focus on product specific development 
Easy port of existing USB 1.1 SIE logic
October 11, 2000

Enable High Volume Devices

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USB Device Development 
Assumptions
² Prototyping 
FPGA + UTMI Compliant Discrete Transceiver

Overview

² Production 
Low Volume Gate Array + UTMI Compliant Discrete Transceiver High Volume ASIC + integrated UTMI Compliant Transceiver Macrocell

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Device Anatomy
Overview 
USB Transceiver Macrocell (UTM)  Serial Interface Engine  Device Specific Logic
ASIC Device Hardware Serial Interface Engine Device Specific Logic
Endpoint Logic Endpoint Logic SIE Control Logic

UTM Interface

«

USB 2.0 Transceiver

USB 2.0

Endpoint Logic

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Serial Interface Engine 
SIE Control Logic

Overview

² USB Transaction State Machine ² PID, Address, and EP match logic ² Checks receive completion status ² Chains packets into transactions 

Endpoint Logic
² FIFOs and FIFO control
Serial Interface Engine To Device Specific Logic
October 11, 2000 Endpoint Logic Endpoint Logic « Endpoint Logic SIE Control Logic Control Data In Data Out 8

To Transceiver

Transceiver Macrocell
Overview 
Converts USB signaling into a parallel interface
² USB 2.0 compliant serial interface ² Multiple Parallel Data Interface Options ² Multiple Speed Options 
HS/FS, FS Only, LS Only
Control To SIE Data In Data Out
October 11, 2000 9

USB 2.0 Transceiver

USB 2.0

To Bus

Macrocell Functions
Overview 
HS and FS signaling and termination  HS receiver squelch  USB clock recovery  Bit stuffing  NRZI encoding  Serializing and deserializing  Data-rate tolerance Data Data buffering  Single interface for HS/FS, FS or LS operation
October 11, 2000 10

Block Diagram
Overview
DD+

HS Interface

Shared ogic
Bit Stuffer Bit Unstuffer Seralizer X Holding Reg RX Holding Reg Data Parallel Interface

o USB

D
mux

Deseralizer

o SIE Control

FS Interface

Control

D

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Interface Features
Macrocell Functions 
Packet Engine
² Automatically handles SYNC Pattern and EOP 

Flow Control
² Compensates for Bit Stuffing and Data Rate Tolerance 

Complete Primitives for Full Protocol Support  Speed Switching  Clock Generation  Power Control
October 11, 2000 12

Interface Options
Macrocell Functions 
Integrated Macrocell
² 8-Bit Uni-directional Uni² 16-Bit Uni-directional 16- Uni- 

Discrete Transceiver
² 8-Bit Bi-directional Bi² 16-Bit Bi-directional / 8-Bit Uni-directional 16- Bi8- Uni-

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8-Bit Uni-Directional
Interface Options
8-Bit Interface DataIn(0DataIn(0-7) TXValid DataOut(0DataOut(0-7) TXReady RXActive RXValid Reset SusepsndM XcvrSelect TermSelect OpMode(0OpMode(0-1)
October 11, 2000

CLK RXError DP DM LineState(0LineState(0-1)
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16-Bit Uni-Directional
Interface Options
16-Bit Interface 16DataIn(8-15) DataIn(0-7) TXValid TXValidH DataOut(8DataOut(8-15) DataOut(0DataOut(0-7) TXReady RXActive RXValid RXValidH Reset SusepsndM XcvrSelect TermSelect OpMode(0-1)
October 11, 2000

CLK RXError DP DM LineState(0LineState(0-1)
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8-Bit Bi-Directional
Interface Options 
TXValid Determines data direction
8-Bit Bi-Directional Interface BiData(0Data(0-7) DataOut(0DataOut(0-7) TXValid DataIn(0DataIn(0-7)

October 11, 2000

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16-Bit Bi-Directional
Interface Options 
ValidH provides multiplexed high-byte valid flag high16-Bit Bi-Directional Interface 16- BiDataBus16_8 Data(8Data(8-15) Data(0Data(0-7) ValidH DataOut(8DataOut(8-15) DataOut(0DataOut(0-7) TXValid RXValidH
October 11, 2000

DataIn(8DataIn(8-15) DataIn(0DataIn(0-7) TXReady TXValidH
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Protocol Primitive Support
Macrocell Functions 
Resume Assertion  Resume Detection  Suspend Detection  Reset Detection  HS Detection Handshake

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Clock Generation
Macrocell Functions 
Macrocell supplies clocks to the SIE  Frequency depends on implementation
² HS/FS 
60 MHz 8-bit uni-directional 8- uni30 MHz 16-bit uni- or bi-directional 16- uni- bi-

² FS Only 
48 MHz 8-bit uni-directional 8- uni-

² LS Only 
6 MHz 8-bit uni-directional 8- uniOctober 11, 2000 19

Power Control
Macrocell Functions 
SuspendM signal
² Shuts down clocks ² Maintains terminations 

Vendor determined Drive Current Control
² Enabled during transmits ² Enabled by receives ² Always on
HS_Current_Source_Enable HS_Drive_Enable
October 11, 2000

HS_Data_Driver_Input

DP DM

High-speed Current Driver

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USB 2.0 Transceiver Macrocell Interface

Testing

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Testing 
UTMI Test Connector Specification  Test Environment - 3 board set
² Off the shelf i960 eval board ² Custom SIE card 
FPGA, DPRAM, and Test Points

² Daughter Card with UTMI Transceiver 

Functionality
² Packet Blaster 
Single Packet operations

² Device Emulator 
Transaction level operations
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UTMI Test Connector Specification 
UTMI Test Connector
² 100 Pins 

Electrical interface
² Timing ² Levels 

Mechanical design
² PCB layout

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Board Set 
Processor Card

Testing

² EVAL80960VH Evaluation Platform Board ² RAM, ROM, FLASH, Serial Port 

FPGA Card
² Dual Port RAM - 64KB ² FPGA - Quicklogic ² Test Points 

Transceiver Daughter Card
² Discrete UTMI compliant transceiver ² Custom circuitry
October 11, 2000 24

Block Diagram
Testing
RSRS-232 Device Specific Logic
i960 DRAM Flash UART

I960 Local Bus Serial Interface Engine
DPRAM FPGA

I960 Card

FPGA Card

UTM Interface

USB 2.0 Transceiver
Transceiver / Macrocell

Transceiver Daughter Card

USB 2.0
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Mechanicals
Testing
i960 Card
RAM CPU

RSRS-232 Connector

Test Chip Daughter Card
FPGA
Xcvr

To USB Device

FPGA Card

DP RAM

100 Pin UTMI Connector
October 11, 2000

PCI Slots (Power)
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Pinout Features 
Vendor Status and Vendor Control support  Multiple Datapath Options Supported
² 8-Bit Bi-Directional Bi² 8-Bit Uni-Directional Uni² 16-Bit Bi-Directional/8-Bit Uni-Directional 16- Bi-Directional/8- Uni- 

Vendor ID  13 General Purpose I/O pins  Vbus Control
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Pinout
Testing
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GPIO0 GND GPIO2 GND GPIO4 GPIO5 GPIO7 VDD GND VControl3 GPIO9 GPIO11 GND VControlLoadM VStatus4 VDD Reset OpMode1 XcvrSelect TermSelect GND SuspendM LineState0 GND LineState1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GPIO1 GND VBUS_out GPIO3 VendorID_0 Data15 GND Data13 Data11 GND Data9 Data7 VDD GND Force_RxErr Data5 Data3 GND Data1 VStatus0 GND VBUS_in VStatus6 VDD Vdbus16_8 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 GND System Clock GND GND VControl0 GPIO6 VDD GPIO8 VControl2 TxValid GPIO10 GND GPIO12 IFType0 GND RxActive OpMode0 GND VDD VStatus1 VStatus2 RxValid GND RxError TxReady 76 GND 77 ValidH 78 DataBus16_8 79 VControl1 80 GND 81 VDD 82 Data14 83 Data12 84 GND 85 Data10 86 Data8 87 VDD 88 Data6 89 IFType1 90 CLK 91 Data4 92 GND 93 Data2 94 Data0 95 GND 96 VStatus3 97 VStatus5 98 VStatus7 99 VendorID_1 100 GND

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Next Steps 
Get the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification
² http://developer.intel.com/technology/usb/ ² No Royalty 

Design to the UTMI Specification  Get the UTMI Test Connector Specification
² http://developer.intel.com/technology/usb/ 

Get your ASIC vendors to provide a UTMI Compliant Macrocells
October 11, 2000 29

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