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Final Year Projects 2011 Vlsi

Final Year Projects 2011 Vlsi

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Published by: suresh_2 on May 08, 2011
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VLSI DOMAIN : IEEE TRANSACTIONS ON CORE VLSI YEAR 2010 2010 2010 2009 2009 2008 2008 2008

CODE PROJECT TITLES V0CV01 COMPLEXITY ANALYSIS AND EFFICIENT IMPLEMENTATIONS OF BIT PARALLEL FINITE FIELD MULTIPLIERS BASED ON KARATSUBA-OFMAN ALGORITHM ON FPGAS V0CV02 BANDWIDTH ADAPTIVE HARDWARE ARCHITECTURE OF K-MEANS CLUSTERING FOR VIDEO ANALYSIS V0CV03 A MULTIBANK MEMORY-BASED VLSI ARCHITECTURE OF DVB SYMBOL DEINTERLEAVER V9CV01 TAG OVERFLOW BUFFERING: REDUCING TOTAL MEMORY ENERGY BY REDUCED-TAG MATCHING V9CV02 DESIGN AND SYNTHESIS OF PROGRAMMABLE LOGIC BLOCK WITH MIXED LUT AND MACROGATE V8CV03 IMPROVING ERROR TOLERANCE FOR MULTITHREADED REGISTER FILES V8CV04 AREA-EFFICIENT ARITHMETIC EXPRESSION EVALUATION USING DEEPLY PIPELINED FLOATING POINT CORES USING VHDL V8CV05 DESIGN OF REVERSIBLE FINITE FIELD ARITHMETIC CIRCUITS WITH ERROR DETECTION DOMAIN CODE V0ELP0 1 V0ELP0 2 V0ELP0 3 V0ELP0 4 V0ELP0 5 V0ELP0 6 V0ELP0 7 V0ELP0 8 V0ELP0 9 V0ELP1 0 : IEEE TRANSACTIONS ON LOW POWER AND FPGA PROJECT TITLES A LOW-COST VLSI IMPLEMENTATION FOR EFFICIENT REMOVAL OF IMPULSE NOISE DYNAMIC CONTEXT COMPRESSION FOR LOW-POWER COARSE-GRAINED RECONFIGURABLE ARCHITECTURE SMALL AREA RECONFIGURABLE FFT DESIGN BY VEDIC MATHEMATICS A RECONFIGURABLE AND HIGH PRECISION VLSI ARCHITECTURE FOR FAST FOURIER TRANSFORMS DESIGN AND ANALYSIS OF HIGH RADIX COMPLEX DIVIDERS DESIGN OF LOW-POWER HIGH-SPEED TRUNCATION-ERROR-TOLERANT ADDER AND ITS APPLICATION IN DIGITAL SIGNAL PROCESSING IMPROVED AREA-EFFICIENT WEIGHTED MODULO 2n + 1 ADDER DESIGN WITH SIMPLE CORRECTION SCHEMES A HIGH-SPEED 32-BIT SIGNED/UNSIGNED PIPELINED MULTIPLIER LUT OPTIMIZATION FOR MEMORY-BASED COMPUTATION ENERGY-EFFICIENT DESIGN METHODOLOGIES: HIGH-PERFORMANCE VLSI ADDERS

YEAR 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010

V9ELP0 1 V9ELP0 2 V8ELP0 4 V8ELP0 5 DOMAIN CODE V0EIP01 V0EIP02 V9EIP03 BZ-FAD: A LOW-POWER LOW-AREA MULTIPLIER BASED ON SHIFT-AND-ADD ARCHITECTURE THE ARISE APPROACH FOR EXTENDING EMBEDDED PROCESSORS WITH ARBITRARY HARDWARE ACCELERATORS LOW POWER DESIGN OF PRECOMPUTATION-BASED CONTENTADDRESSABLE MEMORY L-CBF: A LOW-POWER. FAST COUNTING BLOOM FILTER ARCHITECTURE USING VHDL : IEEE TRANSACTIONS ON IMAGE PROCESSING PROJECT TITLE DYNAMIC BIT-WIDTH ADAPTATION IN DCT: AN APPROACH TO TRADE OFF IMAGE QUALITY AND COMPUTATION ENERGY DESIGN AND ANALYSIS OF HIGH-THROUGHPUT LOSSLESS IMAGE COMPRESSION ENGINE USING VLSI-ORIENTED FELICS ALGORITHM DOWN-SAMPLING DESIGN IN DCT DOMAIN WITH ARBITRARY RATIO FOR IMAGE/VIDEO TRANSCODING 2009 2009 2008 2008 YEAR 2010 2010 2009 .

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->