EXEPRIMENT NO: - 5

OBJECTIVE: -To Design 4-bit comparator using VHDL. APPARATUS/TOOL REQUIRED: Xilinx ISE 10.1 synthesis and simulation tool. PROGRAM:Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity comp is Port (a,b:in STD_LOGIC_VECTOR (3 DOWN TO 0); agb: out STD_LOGIC; alb:out STD_LOGIC; aeb:out STD_LOGIC; End comp; Architecture arc_comp of comp is Begin Process (a,b) Begin If a>b then Agb<=¶1¶; Alb<=¶0¶; Aeb<=¶0¶; Elsif a<b then Alb<=¶1¶; Agb<=¶0¶; Aeb<=¶0¶; Elsif a=b then Alb<=¶0¶; Agb<=¶0¶; Aeb<=¶1¶; End if; End process; End arch_comp;

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LOGIC SYMBOL OF DEVICE:-

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