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vlsi file Layout of Transmission Gate

vlsi file Layout of Transmission Gate

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Published by: avinash960 on May 12, 2011
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05/12/2011

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LAYOUT OF TRANSMISSION GATE

OUTPUT WAVEFORM FOR TRANSIENT CHARACTERISTICS OF TRANSMISSION GATE CIRCUIT

EXPERIMENT 7 AIM:
TO DESIGN A TRANSMISSION GATE CIRCUIT AND STUDY ITS CHARACTERISTICS USING TANNER TOOL

PROGRAM: T-SPICE CODE
M2 4 1 3 6 PMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u * M2 DRAIN GATE SOURCE BULK (11 5 13 11) M1 4 2 3 5 NMOS L=2u W=6u AD=36p PD=24u AS=36p PS=24u * M1 DRAIN GATE SOURCE BULK (11 -12 13 -6) VPP 6 0 5V VNN 5 0 0V VIN 3 0 BIT({0101}) VAA 2 0 BIT({0011}) VA0 1 0 BIT({1100}) .TRAN 100ns 200ns .PRINT V(1) V(2) V(3) V(4) .include "C:\Tanner\TSpice70\models\ml2_125.md"

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