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System Integration Document

www.opal-rt.com
1751 Richardson, suite 2525
Montréal (Québec) Canada H3K 1G6

www.opal-rt.com
© 2011 All rights reserved
Printed in Canada
Contents

Overview ....................................................................................................................................................................... 6

SECTION A – SYSTEM SUMMARY ........................................................................................................................... 7

Hardware Target Station ...................................................................................................................................................................... 7

SECTION B – SYSTEM DIAGRAMS AND SCHEMATICS ........................................................................................ 8

SECTION C – MAPPING I/O BLOCKS TO SIGNAL CONDITIONING................................................................... 9

SECTION D – SIGNAL CONDITIONING CONFIGURATION ................................................................................ 20

PCI Card Configuration ...................................................................................................................................................................... 20

Signal Conditioning Cartridge Configuration........................................................................................................................... 20

PCI OP5142 Configuration ................................................................................................................................................................ 22

SECTION E – CABLE DESCRIPTIONS AND PIN ASSIGNMENTS ....................................................................... 24

16 Din (OP5311 – Section A) and 16 Dout (OP5312 – Section B) ...................... Error! Bookmark not defined.

16 Aout (OP5330 – Section A) and 16 Ain (OP5340 – Section B) ................................................................................. 27


OVERVIEW

PROJECT: PFXXX-XXX

CLIENT: OPAL-RT

SYSTEM S/N: PFXXXXXXS01

Section A System Summary


Section B System Schematics and Photographs
Section C Mapping I/O Blocks to Signal Conditioning
Section D Signal Conditioning Configuration
Section E Cable Descriptions and Pin Assignments
SECTION A – SYSTEM SUMMARY

HARDWARE TARGET STATION

Items Quantity Description


Operating System 1 Empty
Chassis Type 1 Empty
CPU 2 Empty
Total Core # 12
Memory 4 1GB
Motherboard Empty
IP Address 192.168.10.101
Opal-RT I/O Hardware Refer to section D for details
3rd Party I/O Hardware Refer to section D for details
Signal Conditioning Refer to section D for details
SECTION B – SYSTEM DIAGRAMS AND SCHEMATICS
SECTION C – MAPPING I/O BLOCKS TO SIGNAL CONDITIONING

Slot 1 Section A: 16 Analog Out

Relation between Simulink blocks and OP5330

Simulink block library path:


RT-LAB I/O \ Opal-RT \ OP5142 \ OP5142EX1 OP5142EX1AnalogOut
RT-LAB I/O \ Opal-RT \ OP5142 \ OpCtrl OP5142EX1, bit. OP5142_1-EX-0000-1_3_4-S_160_C3_C1_EB_EA_EB_EA-01-01.bin

Description Pinout
Block # Channels
Icon Name: OP5142EX1 AnalogOut # pin Name Comments
A32 +CH00
0
OpFcnOP5142EX1AnalogOut Parameters B32 -CH00
C32 +CH01
1
A31 -CH01
B31 +CH02
2
C31 -CH02
A30 +CH03
3
B30 -CH03
1 Controller Name ‘OP5142EX1 Ctrl’ C30 +CH04
4
DataIn port number 1 A29 -CH04
Number of AOut
8
channels 5 B29 +CH05
C29 -CH05
A28 +CH06
6
B28 -CH06
C28 +CH07
7
A27 -CH07
B27 +CH08
8
OpFcnOP5142EX1AnalogOut Parameters C27 -CH08
A26 +CH09
9
B26 -CH09
C26 +CH10
10
A25 -CH10
2
B25 +CH11
11
C25 -CH11
Controller Name ‘OP5142EX1 Ctrl’ A24 +CH12
12
DataIn port number 2 B24 -CH12
Number of AOut
8 13
channels C24 +CH13
A23 -CH13
B23 +CH14
14
C23 -CH14
A22 +CH15
15
B22 -CH15
Slot 1 Section B: 16 Analog In

Relation between Simulink blocks and OP5330

Simulink block library path:


RT-LAB I/O \ Opal-RT \ OP5142 \ OP5142EX1 OP5142EX1 AnalogIn
RT-LAB I/O \ Opal-RT \ OP5142 \ OpCtrl OP5142EX1, bit. OP5142_1-EX-0000-1_3_4-S_160_C3_C1_EB_EA_EB_EA-01-01.bin

Description Pinout
Block # Channels
Icon Name: OpOP5142EX1 AnalogIn # pin Name Comments
A16 +CH00
16
OpFcnOP5142EX1AnalogIn Parameters B16 -CH00
C16 +CH01
17
A15 -CH01
B15 +CH02
18
C15 -CH02
A14 +CH03
19
B14 -CH03
3
Controller Name ‘OP5142EX1 Ctrl’ C14 +CH04
20
DataOut port number 1 A13 -CH04
Number of AIn channels 8 B13 +CH05
21
C13 -CH05
A12 +CH06
22
B12 -CH06
C12 +CH07
23
A11 -CH07
B11 +CH08
24
OpFcnOP5142EX1AnalogIn Parameters C11 -CH08
A10 +CH09
25
B10 -CH09
C10 +CH10
26
A09 -CH10
B09 +CH11
27
C09 -CH11
4
Controller Name ‘OP5142EX1 Ctrl’ A08 +CH12
28
DataOut port number 2 B08 -CH12
Number of AIn channels 8 C08 +CH13
29
A07 -CH13
B07 +CH14
30
C07 -CH14
A06 +CH15
31
B06 -CH15
Slot 2 Section A: 32 Digital in

Relation between Simulink blocks and OP5251

Simulink block library path:


RT-LAB I/O \ Opal-RT \ OP5142 \ OP5142EX1 EventDetector
RT-LAB I/O \ Opal-RT \ OP5142 \ OpCtrl OP5142EX1, bit. OP5142_1-EX-0000-1_3_4-S_160_C3_C1_EB_EA_EB_EA-01-01.bin

Block # Description Pinout


Channels
Icon Name: OP5142EX1 EventDetector # pin Name Comments
0 B27 IN00

OP5142EX1EventDetector Parameters 1 C27 IN01


2 A26 IN02
Controller Name ‘OP5142EX1 Ctrl’ 3 B26 IN03
1 DataOut port
3 4
number C26 IN04
Number of channels 8 5 A25 IN05
Events per channel 4 6 B25 IN06
7 C25 IN07
8 A24 IN08

OP5142EX1EventDetector Parameters 9 B24 IN09


10 C24 IN10
Controller Name ‘OP5142EX1 Ctrl’ 11 A23 IN11
2 DataIOut port
4 12
number B23 IN12
Number of channels 8 13 C23 IN13
Events per channel 4 14 A22 IN14
15 B22 IN15
16 C22 IN16

OP5142EX1EventDetector Parameters 17 A21 IN17


18 B21 IN18
Controller Name ‘OP5142EX1 Ctrl’ 19 C21 IN19
3 DataOut port
5 20
number A20 IN20
Number of channels 8 21 B20 IN21
Events per channel 4 22 C20 IN22
23 A19 IN23
24 B19 IN24

OP5142EX1EventDetector Parameters 25 C19 IN25


4
26 A18 IN26
Controller Name ‘OP5142EX1 Ctrl’ 27 B18 IN27
DataOut port
6 28
number C18 IN28
Number of channels 8 29 A17 IN29
Events per channel 4 30 B17 IN30
31 C17 IN31

NOTE: The digital input circuit needs an external supply source (Vuser-DIN) to power the
onboard circuitry. See Section E for OP5251 pinout details. By default, the module comes with
the resistor values set to 680 Ohms, which is recommended for 5 to 12 Volts input.
Slot 2 Section B: 32 Digital Out

Relation between Simulink blocks and OP5251

Simulink block library path:


RT-LAB I/O \ Opal-RT \ OP5142 \ OP5142EX1 EventGenerator
RT-LAB I/O \ Opal-RT \ OP5142 \ OpCtrl OP5142EX1, bit. OP5142_1-EX-0000-1_3_4-S_160_C3_C1_EB_EA_EB_EA-01-01.bin

Block # Description Pinout


Channels
Icon Name: OP5142EX1 EventGenerator # pin Name Comments
0 A16 OUT00

OP5142EX1EventGenerator Parameters 1 B16 OUT01


2 C16 OUT02
Controller Name ‘OP5142EX1 Ctrl’ 3 A15 OUT03
1
DataIn port number 3 4 B15 OUT04
Number of channels 8 5 C15 OUT05
Events per channel 4 6 A14 OUT06
7 B14 OUT07
8 C14 OUT08

OP5142EX1EventGenerator Parameters 9 A13 OUT09


10 B13 OUT10
Controller Name ‘OP5142EX1 Ctrl’ 11 C13 OUT11
2
DataIn port number 4 12 A12 OUT12
Number of channels 8 13 B12 OUT13
Events per channel 4 14 C12 OUT14
15 A11 OUT15
16 C06 OUT16

OP5142EX1EventGenerator Parameters 17 A05 OUT17


18 B05 OUT18
Controller Name ‘OP5142EX1 Ctrl’ 19 C05 OUT19
3
DataIn port number 5 20 A04 OUT20
Number of channels 8 21 B04 OUT21
Events per channel 4 22 C04 OUT22
23 A03 OUT23
24 B03 OUT24

OP5142EX1EventGenerator Parameters 25 C03 OUT25


26 A02 OUT26
Controller Name ‘OP5142EX1 Ctrl’ 27 B02 OUT27
4
DataIn port number 6 28 C01 OUT28
Number of channels 8 29 A01 OUT29
Events per channel 4 30 B01 OUT30
31 C01 OUT31
NOTE: The on-board Opto-isolation circuitry has its own isolated power source and does not
require any external power feed. If an external load is required, the power source to that load
must be provided externally by the user (Vuser-DOUT). See Section E for OP5251 pinout details.
The pull-up resistor value is set by default to 4.7 kOhms.
Slot 3 Section A: 32 Digital in

Relation between Simulink blocks and OP5251

Simulink block library path:


RT-LAB I/O \ Opal-RT \ OP5142 \ OP5142EX1 EventDetector
RT-LAB I/O \ Opal-RT \ OP5142 \ OpCtrl OP5142EX1, bit. OP5142_1-EX-0000-1_3_4-S_160_C3_C1_EB_EA_EB_EA-01-01.bin

Block # Description Pinout


Channels
Icon Name: OP5142EX1 EventDetector # pin Name Comments
0 B27 IN00

OP5142EX1EventDetector Parameters 1 C27 IN01


2 A26 IN02
Controller Name ‘OP5142EX1 Ctrl’ 3 B26 IN03
1 DataOut port
7 4
number C26 IN04
Number of channels 8 5 A25 IN05
Events per channel 4 6 B25 IN06
7 C25 IN07
8 A24 IN08

OP5142EX1EventDetector Parameters 9 B24 IN09


10 C24 IN10
Controller Name ‘OP5142EX1 Ctrl’ 11 A23 IN11
2 DataIOut port
8 12
number B23 IN12
Number of channels 8 13 C23 IN13
Events per channel 4 14 A22 IN14
15 B22 IN15
16 C22 IN16

OP5142EX1EventDetector Parameters 17 A21 IN17


18 B21 IN18
Controller Name ‘OP5142EX1 Ctrl’ 19 C21 IN19
3 DataOut port
9 20
number A20 IN20
Number of channels 8 21 B20 IN21
Events per channel 4 22 C20 IN22
23 A19 IN23
24 B19 IN24

OP5142EX1EventDetector Parameters 25 C19 IN25


26 A18 IN26
4
Controller Name ‘OP5142EX1 Ctrl’ 27 B18 IN27
DataOut port
10 28
number C18 IN28
Number of channels 8 29 A17 IN29
Events per channel 4 30 B17 IN30
31 C17 IN31

NOTE: The digital input circuit needs an external supply source (Vuser-DIN) to power the
onboard circuitry. See Section E for OP5251 pinout details. By default, the module comes with
the resistor values set to 680 Ohms, which is recommended for 5 to 12 Volts input.
Slot 2 Section B: 32 Digital Out

Relation between Simulink blocks and OP5251

Simulink block library path:


RT-LAB I/O \ Opal-RT \ OP5142 \ OP5142EX1 EventGenerator
RT-LAB I/O \ Opal-RT \ OP5142 \ OpCtrl OP5142EX1, bit. OP5142_1-EX-0000-1_3_4-S_160_C3_C1_EB_EA_EB_EA-01-01.bin

Block # Description Pinout


Channels
Icon Name: OP5142EX1 EventGenerator # pin Name Comments
0 A16 OUT00

OP5142EX1EventGenerator Parameters 1 B16 OUT01


2 C16 OUT02
Controller Name ‘OP5142EX1 Ctrl’ 3 A15 OUT03
1
DataIn port number 7 4 B15 OUT04
Number of channels 8 5 C15 OUT05
Events per channel 4 6 A14 OUT06
7 B14 OUT07
8 C14 OUT08

OP5142EX1EventGenerator Parameters 9 A13 OUT09


10 B13 OUT10
Controller Name ‘OP5142EX1 Ctrl’ 11 C13 OUT11
2
DataIn port number 8 12 A12 OUT12
Number of channels 8 13 B12 OUT13
Events per channel 4 14 C12 OUT14
15 A11 OUT15
16 C06 OUT16

OP5142EX1EventGenerator Parameters 17 A05 OUT17


18 B05 OUT18
Controller Name ‘OP5142EX1 Ctrl’ 19 C05 OUT19
3
DataIn port number 9 20 A04 OUT20
Number of channels 8 21 B04 OUT21
Events per channel 4 22 C04 OUT22
23 A03 OUT23
24 B03 OUT24

OP5142EX1EventGenerator Parameters 25 C03 OUT25


26 A02 OUT26
Controller Name ‘OP5142EX1 Ctrl’ 27 B02 OUT27
4
DataIn port number 10 28 C01 OUT28
Number of channels 8 29 A01 OUT29
Events per channel 4 30 B01 OUT30
31 C01 OUT31
NOTE: The on-board Opto-isolation circuitry has its own isolated power source and does not
require any external power feed. If an external load is required, the power source to that load
must be provided externally by the user (Vuser-DOUT). See Section E for OP5251 pinout details.
The pull-up resistor value is set by default to 4.7 kOhms.
SECTION D – SIGNAL CONDITIONING CONFIGURATION

PCI CARD CONFIGURATION

Power Slot Power source Notes


A +5 VDC, +12 VDC
B +/- 18 VDC N/A

PCI Slot PCI Card Notes


1 Empty
2 Empty
3 Empty
4 Empty
5 Empty
6 Empty
7 Empty

SIGNAL CONDITIONING CARTRIDGE CONFIGURATION

I/O Slot Carrier Type Section A Section B


1 OP5220 OP5330 Analog Out OP5340 Analog In
2 OP5210-S3 OP5311 Digital In OP5312 Digital Out
3 Empty Empty Empty
4 Empty Empty Empty
PCI OP5142 CONFIGURATION

I/O BitStream Index


OP5142_1-EX-0000-1_3_4-S_160_C3_C1_EB_EA_EB_EA-01-01.bin 0

OP5142 Configuration
# Name Description
1 S1 FPGA Engine manual reset
2 JTAG1 FPGA JTAG interface
3 JTAG2 CPLD JTAG interface
4 JUMP4 JTAG Architecture selection
5 JTAG3 PCIe Bridge JTAG interface
6 JTAG4 SerDes JTAG interface
7 JP1 PCIe & Synchronization bus and Power supply
8 J1/J2/J3 Backplane data, ID and I2C interface
9 JUMP1 Identification EEPROM write protection
10 JUMP2 FPGA configuration mode selection
11 JUMP3 Flash memory Write protection
12 J4 Flash memory forced programmation voltage
SECTION E – CABLE DESCRIPTIONS AND PIN ASSIGNMENTS

The order of the pins in the connector and their assigned functions allow the accurate connection to the system. Pay
careful attention to the position diagram and Pin Assignment table to ensure proper and safe connection.

B32
A32 C32

A1 C1
B1
Carrier Front view,
Male connector
32 DIN AND 32 DOUT OPTO-ISOLATED OP5251

32 Din 32 Dout

Screw 126-0274 Module pin assignment Screw 126-0274 Module pin assignment

A32 RS422_IN_CH0¬ A16 OUT 00 / RS422_OUT_CH0+


B32 RS422_IN_CH1¬ B16 OUT 01 / RS422_OUT_CH1+

C32 RS422_IN_CH2¬ C16 OUT 02 / RS422_OUT_CH2+

A31 RS422_IN_CH3¬ A15 OUT 03 / RS422_OUT_CH3+

B31 RS422_IN_CH4¬ B15 OUT 04 / RS422_OUT_CH4+


C31 RS422_IN_CH5¬ C15 OUT 05 / RS422_OUT_CH5+

A30 RS422_IN_CH6¬ A14 OUT 06 / RS422_OUT_CH6+

B30 RS422_IN_CH7¬ B14 OUT 07 / RS422_OUT_CH7+


C30 RS422_OUT_CH0¬ C14 OUT 08

A29 RS422_OUT-CH1¬ A13 OUT 09

B29 RS422_OUT_CH2¬ B13 OUT 10

C29 RS422_OUT_CH3¬ C13 OUT 11


A28 RS422_OUT_CH4¬ A12 OUT 12

B28 RS422_OUT_CH5¬ B12 OUT 13

C28 Vuser-DIN C12 OUT 14


A27 Vuser-DIN A11 OUT 15

B27 IN 00 / RS422_IN_CH0+ B11 Vuser-DOUT

C27 IN 01 / RS422_IN_CH1+ C11 Vuser-DOUT

A26 IN 02 / RS422_IN_CH2+ A10 Vuser-DOUT


B26 IN 03 / RS422_IN_CH3+ B10 Vuser-DOUT

C26 IN 04 / RS422_IN_CH4+ C10 Vuser_RTN

A25 IN 05 / RS422_IN_CH5+ A09 Vuser_RTN


B25 IN 06 / RS422_IN_CH6+ B09 Vuser_RTN

C25 IN 07 / RS422_IN_CH7+ C09 Vuser_RTN

A24 IN 08 A08 Vuser_RTN

B24 IN 09 B08 Vuser_RTN


C24 IN 10 C08 Vuser_RTN

A23 IN 11 A07 Vuser_RTN

B23 IN 12 B07 Vuser_RTN


C23 IN 13 C07 Vuser_RTN
32 Din 32 Dout

Screw 126-0274 Module pin assignment Screw 126-0274 Module pin assignment

A22 IN 14 A06 RS422_OUT_CH6

B22 IN 15 B06 RS422_OUT_CH7


C22 IN 16 C06 OUT 16

A21 IN 17 A05 OUT 17

B21 IN 18 B05 OUT 18

C21 IN 19 C05 OUT 19


A20 IN 20 A04 OUT 20

B20 IN 21 B04 OUT 21

C20 IN 22 C04 OUT 22


A19 IN 23 A03 OUT 23

B19 IN 24 B03 OUT 24

C19 IN 25 C03 OUT 25

A18 IN 26 A02 OUT 26


B18 IN 27 B02 OUT 27

C18 IN 28 C02 OUT 28

A17 IN 29 A01 OUT 29


B17 IN 30 B01 OUT 30

C17 IN 31 C01 OUT 31


16 AOUT (OP5330 – SECTION A) AND 16 AIN (OP5340 – SECTION B)

16 Aout 16 Ain

Screw 126- Screw 126-


Module pin assignment Module pin assignment
0274 0274

A32 OUT 00 A16 + CH00


B32 GND B16 - CH00

C32 OUT 01 C16 + CH01

A31 GND A15 - CH01

B31 OUT 02 B15 + CH02


C31 GND C15 - CH02

A30 OUT 03 A14 + CH03

B30 GND B14 - CH03


C30 OUT 04 C14 + CH04

A29 GND A13 - CH04

B29 OUT 05 B13 + CH05

C29 GND C13 - CH05


A28 OUT 06 A12 + CH06

B28 GND B12 - CH06

C28 OUT 07 C12 + CH07


A27 GND A11 - CH07

B27 OUT 08 B11 + CH08

C27 GND C11 - CH08


A26 OUT 09 A10 + CH09

B26 GND B10 - CH09

C26 OUT 10 C10 + CH10

A25 GND A09 - CH10


B25 OUT 11 B09 + CH11

C25 GND C09 - CH11

A24 OUT 12 A08 + CH12


B24 GND B08 - CH12

C24 OUT 13 C08 + CH13

A23 GND A07 - CH13


B23 OUT 14 B07 + CH14
16 Aout 16 Ain

Screw 126- Screw 126-


Module pin assignment Module pin assignment
0274 0274

C23 GND C07 - CH14

A22 OUT 15 A06 + CH15


B22 GND B06 - CH15

C22 GND C06 GND

A21 *FP_A_00 (DIO 3.3v) A05 *FP_B_00 (DIO 3.3v)


B21 *FP_A_01 (DIO 3.3v) B05 *FP_B_01 (DIO 3.3v)

C21 *FP_A_02 (DIO 3.3v) C05 *FP_B_02 (DIO 3.3v)

A20 *FP_A_03 (DIO 3.3v) A04 *FP_B_03 (DIO 3.3v)

B20 GND B04 GND


C20 *FP_A_04 (DIO 3.3v) C04 *FP_B_04 (DIO 3.3v)

A19 *FP_A_05 (DIO 3.3v) A03 *FP_B_05 (DIO 3.3v)

B19 EXT_A_V+ B03 EXT_B_V+


C19 EXT_A_V+ C03 EXT_B_V+

A18 *FP_A_06 (DIO 3.3v) A02 *FP_B_06 (DIO 3.3v)

B02
B18 EXT_A_GND EXT_B_GND
44
C18 EXT_A_GND C02 EXT_B_GND

A17 *FP_A_07 (DIO 3.3v) A01 *FP_B_07 (DIO 3.3v)

B17 EXT_A_V- B01 EXT_B_V-


C17 EXT_A_V- C01 EXT_B_V-

* Only available when using OP5130 Carrier in XSG


Tel.: 514-935-2323

Toll free: 1-877-935-2323

Technical Services

www.opal-rt.com/support

CONTACT

Opal-RT Corporate Headquarters

1751 Richardson, Suite 2525

Montréal, Québec, Canada

H3K 1G6
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This publication is not intended to form the basis of

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Note:

While every effort has been made to ensure

accuracy in this publication, no responsibility can be

accepted for errors or omissions. Data may change,