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FFT, Fast, fourier, transform, filters, FPGA, DFT, Discrete, Abhijay, Sisodia, VHDL

- Project report-FFT1
- OFDM_FPGA
- Report FFT Implementation 08gr943
- DESIGN_AND_IMPLEMENTATION_OF_RADIX-4
- Dissertation- Implementation of Fast Fourier Transform on FPGA
- Implementation Of Fast Fourier Transform (FFT) Using VHDL
- FFT VHDL
- FFT
- FFT Implementation in FPGA
- fft_fpga
- FFT Using Vhdl
- fft implementation vhdl
- 15074150-DESIGN-AND-IMPLEMENTATION-OF-OFDM-TRANSMITTER-AND-RECEIVER-ON-FPGA-HARDWARE.pdf
- VHDL Code for 8 Point FFT Algorithm
- Measurement and Error
- fft vhdl code
- Hardware Implemntation of OFDM Transimiter and Receeiver Using FPGA
- Parallel FFT
- Altera OFDM Guide AN503
- Ballistic Galvanometer

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The objective of this project is to design and implement Fast Fourier Transform (FFT)

and Inverse Fast Fourier Transform (IFFT) module on a FPGA hardware. This project

concentrates on developing FFT and IFFT. The work includes in designing of the

module. The design uses 8-point FFT and IFFT for the processing module which indicate

that the processing block contain 8 inputs data. The Fast Fourier Transform and Inverse

Fast Fourier Transform are derived from the main function which is called Discrete

Fourier Transform (DFT). The idea of using FFT/IFFT instead of DFT is that the

computation of the function can be made faster where this is the main criteria for

implementation in the digital signal processing. In DFT the computation for N-point of

the DFT will calculate one by one for each point. While for FFT/IFFT, the computation is

done simultaneously and this method saves quite a lot of time. The project uses radix-2

DIF-FFT algorithm which breaks the entire DFT calculation down into a number of 2-

butterfly

The modules are designed using VHDL programming language and implement using

FPGA board. The board is connected to computer through serial port and software is used

to provide interface between user and the hardware. All processing is executed in FPGA

board and user only requires to give the inputs data to the hardware through software.

Input and output data is displayed to computer and the results is compared using

simulation software. The design process and downloading process into FPGA board uses

iii

List of Figures

Figure 2.2 Application of DFT

Figure 2.3 : Comparison between Real and Complex Transform

Figure 2.4 : Conversion between polar and rectangular Co-ordinates

Figure 2.5 Values of Twiddle Factor

Figure 3.2 : 8- point DIT FFT algorithm

Figure 3.3 DIT-FFT Signal Flow Graph

Figure 3.4 : Bit reversal Example

Figure 3.5 : DIF-FFT butterfly structure

Figure 3.6 DIF-FFT algorithm

Figure 3.7 –Point DIF-FFT Signal Flow Graph using Decimation in Frequency (DIF)

Figure 4.2: FPGA Configurable Logic Block [25]

Figure 4.3: FPGA Configurable I/O Block

Figure 4.4: FPGA Programmable Interconnect

Figure 4.5: FPGA Design Flow

Figure 4.6: Top-Down Design

Figure 4.7: Asynchronous: Race Condition

Figure 4.8: Synchronous: No Race Condition

Figure 4.9: Asynchronous: Delay Dependent Logic

Figure 4.10: Synchronous: Delay Independent Logic

Figure 4.11: Asynchronous: Hold Time Violation

Figure 4.12: Asynchronous: Glitch

Figure 4.13: Synchronous: No Glitch

Figure 4.14: Asynchronous: Bad Clocking

Figure 4.15: Synchronous: Good Clocking

iv

Figure 4.16: Metastability - The Problem

Figure 5.1 : Mapping Module

Figure 5.2 : FFT module

Figure 6.2 : A clock wave form with constant on–off period

Figure 6.3 : Y-chart

Figure 7.2 : Simulation Result

Figure 8.2 : Example of twiddle multiplication

Figure 8.3 : Addition of decimal number

v

Dedicated to

vi

Table of Contents

CHAPTER PAGE

NUMBER

Certificate i

Acknowledgements ii

Abstract iii

List of Figures iv-v

1. Introduction 1-2

1.1 Motivation 1

1.2 Objective 2

2.1 Introduction 4

2.2 Brief History 8

2.3 Fundamentals of Fast Fourier Transform (FFT) Algorithm 9

2.3 Classification 10

2.3.1 On the basis of storage of component 10

2.3.1.1 In-Place FFT algorithm 10

2.3.1.2 Natural Input-Output FFT algorithm 11

2.3.2 On the basis of decimation process 11

2.3.2.1 Decimation-in Time FFT algorithm 11

2.3.2.1 Decimation-in Frequency FFT algorithm 11

2.4 Comparison of direct computation of DFT and by FFT algorithm 12

3.1 Decimation-in time FFT algorithm 13

3.2 Decimation-in frequency FFT algorithm 17

3.2.1 Steps for computation of DIF-FFT 18

vii

3.4 Inverse Fast Fourier Transform(IFFT) 20

3.5 Classification of architecture 21

4.1 Field Programmable Gate Array (FPGA) 23

4.2 FPGA Architecture 23

4.3 Configurable Logic Blocks 24

4.4 Configurable I/O Blocks 25

4.5 Programmable Interconnect 25

4.6 Clock Circuitry 26

4.7 Small v/s Large Granularity 27

4.8 SRAM v/s Anti-fuse Programming 27

4.9 Example of FPGA Families 28

4.10 The Design Flow 28

4.11 Writing a Specification 30

4.11.1 Choosing a Technology 30

4.11.2 Choosing a Design Entry Method 31

4.11.3 Choosing a Synthesis tool 31

4.11.4 Designing a Chip 31

4.11.5 Simulating – Design Review 32

4.11.6 Synthesis 32

4.11.7 Place and Route 32

4.11.8 Re-simulating – Final Review 32

4.11.9 Testing 33

4.12 Design Issues 33

4.12.1 Top-Down Design 33

4.12.2 Keep the Architecture in Mind 34

4.12.3 Synchronous Design 35

4.13 Race Conditions 35

4.14 Delay Dependent Logic 36

4.15 Hold Time violations 37

4.16 Glitches 38

4.17 Bad Clocking 39

viii

4.18 Metastability 40

4.19 Timing Simulation 42

5.1 Introduction 44

5.2 Design Considerations 44

5.3 Implementation 46

5.4 Hardware Modules 47

5.4.1 FFT module 47

5.4.2 IFFT module 47

6.1 Introduction 48

6.2 Review study topics 48

6.3 Design Process 49

6.4 Description of VHDL 52

6.4.1 VHDL Terminology 52

6.4.2 Superceding traditional Design Methods 57

6.4.3 Symbol Vs Entity 60

6.4.4 Schematic and Architecture 60

6.4.5 VHDL Design Process 61

6.4.6 VHDL test – Bench and Verification 62

6.4.7 VHDL Modeling 62

6.4.7.1 Structural Style of Modeling 62

6.4.7.2 Data Flow Style of Modeling 64

6.4.7.3 Behavioral Style of Modeling 66

6.4.7.4 Mixed Style of Modeling 69

6.4.7.1 State Machine Modeling 71

6.5 MATLAB 73

7.1 Synthesis Report 74

ix

7. 2 RTL Schematic Diagram 87

7.3 Simulation Result 88

8.1 Design Solution 89

8.2 Suggestion for Future Research 89

8.3 Implementation Challenges 90

8.3.1 Accuracy 90

8.3.2 Multiplication by Twiddle factor 91

8.3.3 Division by eight 92

8.3.4 Overflow 92

References 94-95

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