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Wiley .Verilog.coding.for.Logic.synthesis.(2003)

Wiley .Verilog.coding.for.Logic.synthesis.(2003)

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Published by Berba Chuot
verilog for fun
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Published by: Berba Chuot on May 18, 2011
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06/02/2013

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Synchronous reset is a reset that can only occur at the rising edge of clock for
a positive clock-triggered flip-flop and falling edge of clock for a negative
clock-triggered flip-flop.This means that synchronous reset is only recognized
during rising edge or falling edge of clock.In other words,synchronous reset
is referenced to the clock signal.It cannot occur independent of the clock.
Figure 4.9 shows a simple synchronous reset design.The output value of the

52

CODING STYLE: BEST-KNOWN METHOD FOR SYNTHESIS

D

Q

RST

clock

FIGURE 4.8.Diagram showing a design with an asynchronous reset flip-flop.

Rising edge of reset

flip-flop is updated during the rising edge of clock.The output value of the
flip-flop is a logical zero,if during the rising edge of clock,reset is at logical
one.The output value of the flip-flop is the logical value of the input data of
the flip-flop,if reset is at logical zero during rising edge of clock.Example 4.7
shows the Verilog code for a design example of synchronous reset.

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