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Wiley .Verilog.coding.for.Logic.synthesis.(2003)

Wiley .Verilog.coding.for.Logic.synthesis.(2003)

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Verilog uses a sensitivity list to determine if a block of sequential statements
needs to be evaluated by the simulator during certain simulation cycles.For
Verilog,a sensitivity list is required for the alwaysstatement.
Example 4.16 shows a Verilog code for a design module that has an
always”block.This block is to be evaluated by the simulator whenever there
is a change in the signals corresponding to the sensitivity list of the “always
block.

Example 4.16Verilog Example Showing Sensitivity List for
“always” Block

module senselist (X, Y, Z, AB);
input X, Y, Z;
output AB;

always @ (X or Y or Z)
begin

// design source code

end
endmodule

Referring to Example 4.16,the sensitivity list consists of three signals,X, Y,
and Z.The block of sequential statements within the “always”block is
evaluated by the simulator whenever there is a change of values in either
signal X, Y,or Z.

An incomplete signal list in the sensitivity list for an “always”block may
cause simulation results to be inaccurate.It may also cause a mismatch
between the synthesis results of the Verilog code and the simulation results.It
is therefore important to always keep note that signals evaluated in an
always”block needs to be included in the sensitivity list.
Table 4.1 is an example of the differences in simulation that may occur due
to an incomplete senstivity list.
Notice how the simulation results for the modules differ.The result of
outputAfor the module that has incomplete sensitivity list has a logic value
of “1”for all combinations of inputs inputA, inputB,and inputC.The module
that has complete sensitivity list has the results of outputAat logic “0”when
inputs inputA, inputB,and inputCare at a combination of “111.”
Both of the modules,although having different simulation results,when syn-
thesized will generate a NAND gate.In this case,it is clear that that synthe-
sized logic will never match the simulation result of the module with
incomplete sensitivity list.It is therefore very important for a designer to
always use a complete sensitivity list when using an alwaysstatement in
Verilog.

66

CODING STYLE: BEST-KNOWN METHOD FOR SYNTHESIS

Sensitivity list which
consists of X, Yand Z.

SENSITIVITY LIST

67

TABLE 4.1.Differences in simulation resulting from an incomplete sensitivity list

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