Unit 1

1. What are the steps involved in implementations & analysis of digitel systems?
2. What are the capabilities of VHDL?
3. What are operators? Explain all six different types.
4. What are the different specifications for the design of digitel systems?
5. Explain with the example of half adder, the dataflow style & behavioral style of modelling.
6. What are identifiers?
7. Enumerate the difference between data objects & data types.
8. Compare: a. Symbols Vs Entities b. Schemetics Vs Architechture
9. In behavioral modelling explain transport & inertial delays.
10. What are data types? Explains all its types with program examples.
11. What is VHDL? Who formulated rules of VHDL? What are its specific capabilities?
12. What is entity declaration? Explain it for 2-4 decoder circuit.
13. How is behavioral style of modelling different from mixed style of modelling?
14. How many types of identifiers are there?
15. Diffrentiate between sub & scalar types of data types.
16. In behavioral modelling what are signal drivers?
17. What is the effect of transport delay on signal drivers?
18. What are the different capabilites of VHDL?
19. Use entity declaration for the 3:8 decoder circuits.
20. Differentiate between behavioural & structural style of modelling.
21. Why do we use identifiers? Explain with example.
22. What do you mean by a hardware description language? Discuss in brief the history of VHDL.
23. Discuss various types of classes & operators in VHDL.
24. Explain the concept of delta delay, transport delay & overloading with example.
25. Explain the steps involved in specifying & implementing digital systems.
26. Explain the various utilities of digital tools for analysing digital system.
27. How many types of modelling styles are there in VHDL? Explain each of them with the help of
example.
28. Discuss various types of data objects & operators used in VHDL.
29. Discuss various types of delays.
30. Compare the following: a. Concurrent & sequential statements.
b. behavioural & structural modelling
31. What is meant by operator overloading? Discuss with suitable example.
32. Write procedure for half adder using dataflow style of modelling.
33. What is the difference between behavioural & structural style of modeling in VHDL? Explain with
suitable example.
34. Discuss various types of delays used in VHDL.
35. What are the different data types used in VHDL?

Unit 2
1. Explain the significance of conditional signal assignment statement and selected signal assignment
statement?
2. How will you compare component declaration & component instantiation?
3. Diffrentiate arrays & loops. Explain with the help of examples.
4. Write down the configuration specification for full adder circuit.
5. Write short notes on: a. Functions b. Subprogram overloading
6. What are overloading & resolution functions?
7. In behavioural modelling: explain a. Architechture body b. Process statement
c. signal assignmenet statement d. Wait statement e. Case statement
8. What are attributes? Explain predefined attributes in details.
9. Write short note. b. Generics c. Component declaration d. Liberaries
10. What are generics & why they are being used?
11. Differentiate between value type & value array attributes. Why attributes are being used?
12. What are EXIT & ASSERT statements in sequential processing.
13. What is subprogram overloading? Explain with examples.
14. What are technology liberaries?
15. What are attributes? Explain it with the help of any digitel circuit.
16. What are technology liberaries? How delay effects are used in delay models?
17. Use ‘IF’ control flow statement for implementing 3-input OR gate.
18. How Case statement is different from Loop statement?
19. What is liberary clause & why it is used?
20. Differentiate between operator & subprogram overloading.
21. Discuss package & liberaries used in VHDL.
22. What are subprograms? Explain with example.
23. Explain the use of following VHDL with examples: a. Generics b. Resolution Functions
c. Procedures d. Concurrent & sequential statements
24. What is a statement? How is it defined? How many types are there? Explain each with program
examples.
25. Differentiate between subprogram & operator overloading.
26. Write VHDL code of 4:1 multiplexer using: a. Case statement b. If then else statement.
27. Explain functions & procedures used in VHDL with suitable examples.
28. Discuss the following as are used in: a. Data types b. package c. Generics
d. Procedure
29. Explain the following with suitable examples: a. Process statement b. Loop statement
c. Subprogram overloading d. Functions

30. Write short note on packages & liberaries.

31. What are conversion functions? Why do we use them & how?

32. What are generics? Explain with suitable example.

Unit 3

1. What is the difference between: a. Decoder & Demultiplexer b. Encoder & Multiplexer
2. What is the difference between combination & sequential circuits?
3. Write VHDL code for half addder using:
a. Dataflow modelling b. Structural modelling
4. Using process statement implement 4 input MUX symbol & its functions.
5. Write VHDL code for 8:3 encoder using dataflow modelling.
6. Write VHDL code for any comparator.
7. Draw & explain a ciruit diagram of a 4 bit comparator. Also explain the Race around condition.
8. Model & simulate a priority encoder.
9. Model & simulate a 16:1 multiplexer using NAND gates only.
10. Write VHDL code for 16:1 multiplexer using 4:1 multiplexer as component.
11. Write the VHDL code for full adder using structural modelling.
12. Write down truth table, VHDL code for following:
a. 1:8 demultiplexer b. Code converter (any type).
13. Use structural modelling for explaining the circuit of 9-bit parity generator.
14. Write a program for the simulation of a buffered multiplier, using behavioral modelling.
15. Write a program using mixed modelling to implement a comparator circuit.

Unit 4
1. Design & implement a counter in VHDL, which counts upto 9 and downcounts again from 9 to 0.
2. What is the difference between a flipflop and latch?
3. Model & simulate 4-bit bi-directional shift register. Assume the counter is:
a. SIPO b. PISO mode
4. Write steps for modelling synchoronus logic.
5. Design a pulse counter which shows overflow, if count exceeds ‘MAX COUNT’.
6. What is the difference between a flipflop and latch?
7. Model Johnson counter in behavioural modelling.
8. Simulate a flip flop using VITAL simulation.
9. Draw & explain look ahead carry circuit.
10. Draw a complete structural model for a 9 bit parity generator circuit in structural modelling.
11. Explain Simulation of Johnson counter.
12. Draw the circuit diagram & write VHDL code for decade counter using JK flipflops.
13. Draw the circuit diagram & write VHDL code for shift right register.
14. Model & simulate a PISO shift register using JK flipflop only.
15. Model & simulate a Decade counter using JK flipflop only.
16. Write the truth table & VHDL code for the follwing:
a. JK flip flop b. Mod 8 up counter
17. Write VHDL code for 3 bit up counter using JK flip flop as component.
18. Write VHDL code for JK flip flop using:
a. If then else statement b. Case statement

19. Write VHDL coe for shift right register.

Unit 5

1. Explain how a microcomputer system works. Explain its implementations using VHDL.
2. How macro cell is a memory element? If so explain.
3. Implement a simple microcomputer system.
4. Description of processor implementation in VHDL
5. Draw a block diagram of CPU & implement it using synthesis description.
6. Implement a Simple microcomputer using VHDL.
7. Give architechture of a simple microcomputer system.
8. How do you implement a microcomputer using VHDL?
9. Explain in detail the basic components of a computer with the help of a block diagram.
10. Discuss in detail implementation of simple microcomputer system using VHDL.
11. Discuss basic components of computer. Write VHDL code for ALU.

Unit 6

1. What are PLDs? Eplain specifically 16L8, 16R6 in detail. Also implement them using VHDL.
2. What are Aliases? What is its syntax? Explain with examples.
3. Collect the comparative & contrasting statement b/w PAL, PLA & GAL.
4. Write short note. a. FPGA
5. Write short notes: a. Designing using PLD’s b. FPGA
6. Write short notes on: a. PLD designing b. FPGA
7. What is a test bench & what is the purpose of writing a test bench?
8. Write short notes on: a. FPGA b. PAL’s c. PEEL
9. Write short notes on: a. PLD’s i.e. 16R6 b. PAL c. FPGA
10. How ROM can be used as: a. PAL b. PLA
11. Write short notes on: a. CPLD’s c. Test bench
12. Draw & explain PAL circuit.
13. Write short notes on: a. PEEL b. FPGA c. ROM