A 32-bit address bus allows access to a memory of capacity (a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb

2. Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors 3. In 8086 microprocessor one of the following statements is not true. a) Coprocessor is interfaced in MAX mode b) Coprocessor is interfaced in MIN mode c) I/O can be interfaced in MAX / MIN mode d) Supports pipelining

4. The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus. A. B. C. D. control bus control instructions address decoder CPU

5. In an 8085 microprocessor, the instruction CMP B has been executed while the contents

of accumulator is less than that of register B. As a result carry flag and zero flag will be respectively (A) set, reset (B) reset, set (C) reset, reset (D) set, set 6. To put the 8085 microprocessor in the wait state (i) lower the-HOLD input (ii) lower the READY input (iii) raise the HOLD input (iv) raise the READY input 7. Registers, which are partially visible to users and used to hold conditional, are known as a. PC b. Memory address registers c. General purpose register d. Flags


8. What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status

9. Who invented the microprocessor? a. Marcian E Huff b. Herman H Goldstein c. Joseph Jacquard d. All of above 10. Before a modem transmits, it send a: a. CTS b.DTR c.DSR d. RTS

11. The number of memory cycles required to execute the following 8085 instructions (i) LDA 3000H (ii) LXI D, FOF1H would be (B) 2 for (i) and 2 for (ii) (C) 4 for (i) and 2 for (ii) (D) 3 for (i) and 3 for (ii) (E) 3 for (i) and 4 for (ii) 12. The 8255 Programmable Peripheral Interface isused as described below. (i) An A/D converter is interfaced to a microprocessor through an 8255. The conversion is initiated by a signal from the 8255 on Port C. A signal on Port C causes data to be stobed into Port A. (ii) Two computers exchange data using a pair of 8255s. Port A works as a bidirectional data port supported by appropriate handshaking signals. The appropriate modes of operation of the 8255 for (i) and (ii) would be (A) Mode 0 for (i) and Mode 1 for (ii) (B) Mode 1 for (i) and Mode 2 for (ii) (C) Mode 2 for (i) and Mode 0 for (ii) (D) Mode 2 for (i) and Mode 1 for (ii) 13. The microprocessor 8085 has _____ basic instructions and _____ opcodes. a) 80, 246 b) 70, 346 c) 80, 346 d) 70, 246
14. What does microprocessor speed depends on MS.R.RAJAKUMARI AP/IT, PMU,VALLAM

a) Clock

b) Data bus width

c) Address bus width

d)Size of register

15. The status that cannot be operated by direct instructions is a) Cy b) Z c) P d) AC 16. The number of software interrupts in 8085 is ____ a) 5 b) 8 c) 9 d) 10 17. Adress line for RST 3 is a) 0020H b) 0028H c) 0018H d) 0038H 18. The necessary steps carried out to perform the operation of accessing either memory or I/O Device, constitute a ___________________ a) fetch operation b) execute operation c) machine cycle d) instruction cycle 19. Which is a 8 bit Microprocessor __________ a) Intel 4040 b) Pentium – I c) 8088 d) Motorala MC-6801 20. Interfacing devices for DMA controller, programmable interval timer are respectively… a) 8257, 8253 b) 8253, 8257 c) 8257,8251 d)8251,8257 21. Consider the following set of 8085 instruction. MVI A,82H ORA A JP DSPLY XRA A DSPLY:OUT PORT1 HLT. The output at PORT1 is a) 00H execution is a) A5H b) FFH c) 92H d) 11H

22. The contents of accumulator before CMA instruction is A5H. Its content after instruction

b) 5AH

c) AAH

d) 55H

23. In an 8085 based system, the maximum number of input output devices can be connected using I/0 mapped I/O method is a) 64 b) 512 c) 256 d) 65536
24. How many transistors does the 8086 have? a) 10,000 b) 29,000 c) 110,000 d) 129,000
25. What generation chip is the Pentium 4 for the Intel central processing units? A. Seventh generation B. Eighth generation


C. D.

Ninth generation Tenth Generation

26. The first processor to include Virtual memory in the Intel microprocessor family was: a.) 80286 b.) 80386 c.) 80486 d.) Pentium 27. Intel Itanium processors are designed for a. Servers and personal computers b. Servers only c. Personal computers only d. Calculators

28. In 8086 microprocessor one of the following instructions is executed before an arithmetic operation a. AAM b) AAD c) DAS d) DAA
29. In 8051,After reset the SP register is initialized to address________. a. 8H b) 9H c) 7H d) 6H

30. Serial port interrupt is generated, if ____ bits are set a) IE b) RI, IE c) IP, TI d) RI, TI 31. In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1

32. When the 8051 is reset and the line is LOW, the program counter points to the first program instruction in the: A. B. C. D. internal code memory external code memory internal data memory external data memory

33. In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
34. In a microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an interrupt is (A) non-maskable and non-vectored


(B) maskable and non-vectored (C) non-maskable and vectored (D) maskable and vectored
35. For the 8085 assembly language program given below, the content of the accumulator after the execution of the program is

3000 3002 3003 3004 3005 3006


(A) 00H (B) 45H (C) 67H (D) E7H 36. An 8255 chip is Interfaced to an 8085 Microprocessor system as an I/O Mapped I/O. The Address lines A0, A1 of 8085 are used by the 8255 chip to decode internally its three ports and the control register.The address lines A3-A7 and IO/M signal are used for address decoding. The range of the addresses for which the 8255 chip would get selected is (a) F8H-FBH (b) F8H-FCH (c) F8H-FFH (d)F0H-F7H

37. The TRAP is one of the interrupts available its INTEL 8085. Which one of the following statements is true of TRAP? (a) It is level triggered (b) It is negative edge triggered (c) It is positive edge triggered (d) It is both positive edge triggered and level triggered 38. In a 16-bit microprocessor, words are stored in two consecutive memory locations. The entire word can be read in one operation provided the first (a) word is even (b) word is odd (c) memory location is odd (d) memory address is even 39. The ESC instruction of 8086 may have two formats. In one of the formats, no memory operand is used. Under this format, the number of external op-codes (for the coprocessor) which can be specified is? a. b. c. d. 64 128 256 512

40. DB, DW and DD directives are used to place data in particular location or to simply allocate space without preassigning anything to space. The DW and DD directories are used to generate

a. offsets b. full address of variables c. full address of labels d. offsets of full address of labels and variables 41. When the RET instruction at the end of subroutine is executed, 1. the information where the stack is iniatialized is transferred to the stack pointer 2. the memory address of the RET instruction is transferred to the program counter 3. two data bytes stored in the top two locations of the stack are transferred to the program counter 4. two data bytes stored in the top two locations of the stack are transferred to the stack pointer


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